/*
 * Copyright (c) 2020 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
 * above copyright notice and this permission notice appear in all
 * copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */

//////////////////////////////////////////////////////////////////////////////
// lithium_top_reg.h generated by: GenArmCHeader.pl
//////////////////////////////////////////////////////////////////////////////
// **** W A R N I N G ****  THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
//////////////////////////////////////////////////////////////////////////////
// 
// RCS File        : -USE CVS LOG-
// Revision        : -USE CVS LOG-
// Last Check In   : -USE CVS LOG-
//////////////////////////////////////////////////////////////////////////////
// Description     : Constants related to Hardware Registers
//
// Byte Addresses are used for all BASES and ADDRESSES
//////////////////////////////////////////////////////////////////////////////
#ifndef LITHIUM_TOP_REG_H

#define LITHIUM_TOP_REG_H

enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND};


#define PHYA                        (0x00300000)

#define PHYA_PCSS_PDMEM_PDMEM_L_n(n)     (0x00300000+0x8*(n))
#define   PHYA_PCSS_PDMEM_PDMEM_L_n_nMIN 0    
#define   PHYA_PCSS_PDMEM_PDMEM_L_n_nMAX 0    
#define   PHYA_PCSS_PDMEM_PDMEM_L_n_ELEM 1    
#define   PHYA_PCSS_PDMEM_PDMEM_L_n___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_PDMEM_PDMEM_L_n___POR        0x00000000
#define   PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___POR 0x00000000
#define   PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___M 0xFFFFFFFF
#define   PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___S               0
#define   PHYA_PCSS_PDMEM_PDMEM_L_n___M          0xFFFFFFFF   
#define   PHYA_PCSS_PDMEM_PDMEM_L_n___S                        0
#define PHYA_PCSS_PDMEM_PDMEM_L_0                 (0x00300000)
#define   PHYA_PCSS_PDMEM_PDMEM_L_0___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_PDMEM_PDMEM_L_0__PDMEM_LOW___M 0xFFFFFFFF
#define   PHYA_PCSS_PDMEM_PDMEM_L_0__PDMEM_LOW___S               0

#define PHYA_PCSS_PDMEM_PDMEM_U_n(n)     (0x00300004+0x8*(n))
#define   PHYA_PCSS_PDMEM_PDMEM_U_n_nMIN 0    
#define   PHYA_PCSS_PDMEM_PDMEM_U_n_nMAX 0    
#define   PHYA_PCSS_PDMEM_PDMEM_U_n_ELEM 1    
#define   PHYA_PCSS_PDMEM_PDMEM_U_n___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_PDMEM_PDMEM_U_n___POR        0x00000000
#define   PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___POR 0x00000000
#define   PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___M 0xFFFFFFFF
#define   PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___S               0
#define   PHYA_PCSS_PDMEM_PDMEM_U_n___M          0xFFFFFFFF   
#define   PHYA_PCSS_PDMEM_PDMEM_U_n___S                        0
#define PHYA_PCSS_PDMEM_PDMEM_U_0                 (0x00300004)
#define   PHYA_PCSS_PDMEM_PDMEM_U_0___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_PDMEM_PDMEM_U_0__PDMEM_HIGH___M 0xFFFFFFFF
#define   PHYA_PCSS_PDMEM_PDMEM_U_0__PDMEM_HIGH___S               0

#define PHYA_PCSS_GLOBAL_CONFIG_L                 (0x00380000)
#define   PHYA_PCSS_GLOBAL_CONFIG_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_GLOBAL_CONFIG_L___POR        0x00000000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___POR 0x0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___M 0x00040000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___S              18
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___M 0x00038000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___S              15
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___M 0x00004000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___S              14
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___M 0x00002000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___S              13
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___M 0x00001000
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___S              12
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___M 0x00000800
#define   PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___S              11
#define   PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___M  0x00000700
#define   PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___S                8
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___M  0x000000C0
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___S                6
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___M  0x00000020
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___S                5
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___M 0x00000010
#define   PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___S               4
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___M  0x0000000C
#define   PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___S                2
#define   PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___M 0x00000002
#define   PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___S               1
#define   PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___M 0x00000001
#define   PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___S               0
#define   PHYA_PCSS_GLOBAL_CONFIG_L___M          0x0007FFFF   
#define   PHYA_PCSS_GLOBAL_CONFIG_L___S                        0

#define PHYA_PCSS_M3_STATUS_L                     (0x00380008)
#define   PHYA_PCSS_M3_STATUS_L___RWC               QCSR_REG_RO    
#define   PHYA_PCSS_M3_STATUS_L___POR            0x00000000
#define   PHYA_PCSS_M3_STATUS_L__M3_STS___POR    0x0
#define   PHYA_PCSS_M3_STATUS_L__M3_STS___M      0x00000007
#define   PHYA_PCSS_M3_STATUS_L__M3_STS___S                    0
#define   PHYA_PCSS_M3_STATUS_L___M              0x00000007   
#define   PHYA_PCSS_M3_STATUS_L___S                            0

#define PHYA_PCSS_M3_CTRL_L                       (0x00380010)
#define   PHYA_PCSS_M3_CTRL_L___RWC                 QCSR_REG_RW    
#define   PHYA_PCSS_M3_CTRL_L___POR              0x00000000
#define   PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__M3_640_EN___POR   0x0
#define   PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___POR  0x0
#define   PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__M3_ENABLE___POR   0x0
#define   PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___POR 0x0
#define   PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___M 0x00000100
#define   PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___S               8
#define   PHYA_PCSS_M3_CTRL_L__M3_640_EN___M     0x00000080
#define   PHYA_PCSS_M3_CTRL_L__M3_640_EN___S                   7
#define   PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___M    0x00000040
#define   PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___S                  6
#define   PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___M   0x00000020
#define   PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___S                 5
#define   PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___M 0x00000010
#define   PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___S               4
#define   PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___M   0x00000008
#define   PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___S                 3
#define   PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___M   0x00000004
#define   PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___S                 2
#define   PHYA_PCSS_M3_CTRL_L__M3_ENABLE___M     0x00000002
#define   PHYA_PCSS_M3_CTRL_L__M3_ENABLE___S                   1
#define   PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___M   0x00000001
#define   PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___S                 0
#define   PHYA_PCSS_M3_CTRL_L___M                0x000001FF   
#define   PHYA_PCSS_M3_CTRL_L___S                              0

#define PHYA_PCSS_M3_BP_L                         (0x00380018)
#define   PHYA_PCSS_M3_BP_L___RWC                   QCSR_REG_RW    
#define   PHYA_PCSS_M3_BP_L___POR                0x00000000
#define   PHYA_PCSS_M3_BP_L__BP_DBG_CMD___POR    0x00000000
#define   PHYA_PCSS_M3_BP_L__BP_DBG_CMD___M      0xFFFFFFFF
#define   PHYA_PCSS_M3_BP_L__BP_DBG_CMD___S                    0
#define   PHYA_PCSS_M3_BP_L___M                  0xFFFFFFFF   
#define   PHYA_PCSS_M3_BP_L___S                                0

#define PHYA_PCSS_M3_BP_U                         (0x0038001C)
#define   PHYA_PCSS_M3_BP_U___RWC                   QCSR_REG_RW    
#define   PHYA_PCSS_M3_BP_U___POR                0x00000000
#define   PHYA_PCSS_M3_BP_U__BREAKPOINT___POR    0x0
#define   PHYA_PCSS_M3_BP_U__BREAKPOINT___M      0x00000001
#define   PHYA_PCSS_M3_BP_U__BREAKPOINT___S                    0
#define   PHYA_PCSS_M3_BP_U___M                  0x00000001   
#define   PHYA_PCSS_M3_BP_U___S                                0

#define PHYA_PCSS_M3_IPCREG_L                     (0x00380020)
#define   PHYA_PCSS_M3_IPCREG_L___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_M3_IPCREG_L___POR            0x00000000
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___POR 0x0000000
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___POR 0x0
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___M 0xFFFFFFF0
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___S               4
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___M 0x0000000F
#define   PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___S               0
#define   PHYA_PCSS_M3_IPCREG_L___M              0xFFFFFFFF   
#define   PHYA_PCSS_M3_IPCREG_L___S                            0

#define PHYA_PCSS_M3_IPCREG_U                     (0x00380024)
#define   PHYA_PCSS_M3_IPCREG_U___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_M3_IPCREG_U___POR            0x00000000
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___POR 0x0000000
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___POR 0x0
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___M 0xFFFFFFF0
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___S               4
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___M 0x0000000F
#define   PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___S               0
#define   PHYA_PCSS_M3_IPCREG_U___M              0xFFFFFFFF   
#define   PHYA_PCSS_M3_IPCREG_U___S                            0

#define PHYA_PCSS_M3_M3_IPCREG_L                  (0x00380028)
#define   PHYA_PCSS_M3_M3_IPCREG_L___RWC            QCSR_REG_RW    
#define   PHYA_PCSS_M3_M3_IPCREG_L___POR         0x00000000
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___POR 0x0000000
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___POR 0x0
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___M 0xFFFFFFF0
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___S               4
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___M 0x0000000F
#define   PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___S               0
#define   PHYA_PCSS_M3_M3_IPCREG_L___M           0xFFFFFFFF   
#define   PHYA_PCSS_M3_M3_IPCREG_L___S                         0

#define PHYA_PCSS_M3_SW_LOG_0_L                   (0x00380030)
#define   PHYA_PCSS_M3_SW_LOG_0_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_M3_SW_LOG_0_L___POR          0x00000000
#define   PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___POR 0x00000000
#define   PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___M  0xFFFFFFFF
#define   PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___S                0
#define   PHYA_PCSS_M3_SW_LOG_0_L___M            0xFFFFFFFF   
#define   PHYA_PCSS_M3_SW_LOG_0_L___S                          0

#define PHYA_PCSS_M3_SW_LOG_0_U                   (0x00380034)
#define   PHYA_PCSS_M3_SW_LOG_0_U___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_M3_SW_LOG_0_U___POR          0x00000000
#define   PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___POR 0x00000000
#define   PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___M  0xFFFFFFFF
#define   PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___S                0
#define   PHYA_PCSS_M3_SW_LOG_0_U___M            0xFFFFFFFF   
#define   PHYA_PCSS_M3_SW_LOG_0_U___S                          0

#define PHYA_PCSS_M3_SW_LOG_1_L                   (0x00380038)
#define   PHYA_PCSS_M3_SW_LOG_1_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_M3_SW_LOG_1_L___POR          0x00000000
#define   PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___POR 0x00000000
#define   PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___M 0xFFFFFFFF
#define   PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___S               0
#define   PHYA_PCSS_M3_SW_LOG_1_L___M            0xFFFFFFFF   
#define   PHYA_PCSS_M3_SW_LOG_1_L___S                          0

#define PHYA_PCSS_M3_SW_LOG_1_U                   (0x0038003C)
#define   PHYA_PCSS_M3_SW_LOG_1_U___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_M3_SW_LOG_1_U___POR          0x00000000
#define   PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___POR 0x00000000
#define   PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___M 0xFFFFFFFF
#define   PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___S               0
#define   PHYA_PCSS_M3_SW_LOG_1_U___M            0xFFFFFFFF   
#define   PHYA_PCSS_M3_SW_LOG_1_U___S                          0

#define PHYA_PCSS_CRC_CTRL_L                      (0x00380040)
#define   PHYA_PCSS_CRC_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_PCSS_CRC_CTRL_L___POR             0x00000000
#define   PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___POR 0x0
#define   PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___POR 0x0
#define   PHYA_PCSS_CRC_CTRL_L__CRC_START___POR  0x0
#define   PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___POR   0x0
#define   PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___POR 0x0
#define   PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___M 0x00000020
#define   PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___S               5
#define   PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___M 0x00000010
#define   PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___S               4
#define   PHYA_PCSS_CRC_CTRL_L__CRC_START___M    0x00000008
#define   PHYA_PCSS_CRC_CTRL_L__CRC_START___S                  3
#define   PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___M     0x00000004
#define   PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___S                   2
#define   PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___M 0x00000003
#define   PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___S               0
#define   PHYA_PCSS_CRC_CTRL_L___M               0x0000003F   
#define   PHYA_PCSS_CRC_CTRL_L___S                             0

#define PHYA_PCSS_CRC_DATA0_L                     (0x00380048)
#define   PHYA_PCSS_CRC_DATA0_L___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_CRC_DATA0_L___POR            0x00000000
#define   PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___POR 0x00000000
#define   PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___M 0xFFFFFFFF
#define   PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___S               0
#define   PHYA_PCSS_CRC_DATA0_L___M              0xFFFFFFFF   
#define   PHYA_PCSS_CRC_DATA0_L___S                            0

#define PHYA_PCSS_CRC_DATA0_U                     (0x0038004C)
#define   PHYA_PCSS_CRC_DATA0_U___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_CRC_DATA0_U___POR            0x00000000
#define   PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___POR 0x00000000
#define   PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___M 0xFFFFFFFF
#define   PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___S               0
#define   PHYA_PCSS_CRC_DATA0_U___M              0xFFFFFFFF   
#define   PHYA_PCSS_CRC_DATA0_U___S                            0

#define PHYA_PCSS_CRC_DATA1_L                     (0x00380050)
#define   PHYA_PCSS_CRC_DATA1_L___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_CRC_DATA1_L___POR            0x00000000
#define   PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___POR 0x00000000
#define   PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___M 0xFFFFFFFF
#define   PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___S               0
#define   PHYA_PCSS_CRC_DATA1_L___M              0xFFFFFFFF   
#define   PHYA_PCSS_CRC_DATA1_L___S                            0

#define PHYA_PCSS_CRC_DATA1_U                     (0x00380054)
#define   PHYA_PCSS_CRC_DATA1_U___RWC               QCSR_REG_RW    
#define   PHYA_PCSS_CRC_DATA1_U___POR            0x00000000
#define   PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___POR 0x00000000
#define   PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___M 0xFFFFFFFF
#define   PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___S               0
#define   PHYA_PCSS_CRC_DATA1_U___M              0xFFFFFFFF   
#define   PHYA_PCSS_CRC_DATA1_U___S                            0

#define PHYA_PCSS_CRC_RESULT_L                    (0x00380058)
#define   PHYA_PCSS_CRC_RESULT_L___RWC              QCSR_REG_RO    
#define   PHYA_PCSS_CRC_RESULT_L___POR           0x000000FF
#define   PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___POR 0xFF
#define   PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___M 0x000000FF
#define   PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___S               0
#define   PHYA_PCSS_CRC_RESULT_L___M             0x000000FF   
#define   PHYA_PCSS_CRC_RESULT_L___S                           0

#define PHYA_PCSS_RRI_CTRL_0_L                    (0x00380060)
#define   PHYA_PCSS_RRI_CTRL_0_L___RWC              QCSR_REG_RW    
#define   PHYA_PCSS_RRI_CTRL_0_L___POR           0x00000000
#define   PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___POR 0x0
#define   PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___M 0x00000001
#define   PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___S               0
#define   PHYA_PCSS_RRI_CTRL_0_L___M             0x00000001   
#define   PHYA_PCSS_RRI_CTRL_0_L___S                           0

#define PHYA_PCSS_RRI_CTRL_0_U                    (0x00380064)
#define   PHYA_PCSS_RRI_CTRL_0_U___RWC              QCSR_REG_RW    
#define   PHYA_PCSS_RRI_CTRL_0_U___POR           0x00000000
#define   PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___POR 0x000000
#define   PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___M 0x00FFFFFF
#define   PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___S               0
#define   PHYA_PCSS_RRI_CTRL_0_U___M             0x00FFFFFF   
#define   PHYA_PCSS_RRI_CTRL_0_U___S                           0

#define PHYA_PCSS_RRI_CTRL_1_L                    (0x00380068)
#define   PHYA_PCSS_RRI_CTRL_1_L___RWC              QCSR_REG_RW    
#define   PHYA_PCSS_RRI_CTRL_1_L___POR           0x00000000
#define   PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___POR 0x000000
#define   PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___M 0x00FFFFFF
#define   PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___S               0
#define   PHYA_PCSS_RRI_CTRL_1_L___M             0x00FFFFFF   
#define   PHYA_PCSS_RRI_CTRL_1_L___S                           0

#define PHYA_PCSS_CORE_RESET_L                    (0x00380070)
#define   PHYA_PCSS_CORE_RESET_L___RWC              QCSR_REG_WO    
#define   PHYA_PCSS_CORE_RESET_L___POR           0x00000000
#define   PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___POR 0x0
#define   PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___M 0x00000800
#define   PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___S              11
#define   PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___M 0x00000400
#define   PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___S              10
#define   PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___M 0x00000200
#define   PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___S               9
#define   PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___M 0x00000100
#define   PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___S               8
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___M 0x00000080
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___S               7
#define   PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___M 0x00000040
#define   PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___S               6
#define   PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___M 0x00000020
#define   PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___S               5
#define   PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___M 0x00000010
#define   PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___S               4
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___M 0x00000008
#define   PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___S               3
#define   PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___M 0x00000004
#define   PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___S               2
#define   PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___M 0x00000002
#define   PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___S               1
#define   PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___M 0x00000001
#define   PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___S               0
#define   PHYA_PCSS_CORE_RESET_L___M             0x00000FFF   
#define   PHYA_PCSS_CORE_RESET_L___S                           0

#define PHYA_PCSS_PHY_VER_REG_L                   (0x00380078)
#define   PHYA_PCSS_PHY_VER_REG_L___RWC             QCSR_REG_RO    
#define   PHYA_PCSS_PHY_VER_REG_L___POR          0x00080000
#define   PHYA_PCSS_PHY_VER_REG_L__MINOR___POR   0x008
#define   PHYA_PCSS_PHY_VER_REG_L__STEP___POR    0x0000
#define   PHYA_PCSS_PHY_VER_REG_L__MINOR___M     0x0FFF0000
#define   PHYA_PCSS_PHY_VER_REG_L__MINOR___S                  16
#define   PHYA_PCSS_PHY_VER_REG_L__STEP___M      0x0000FFFF
#define   PHYA_PCSS_PHY_VER_REG_L__STEP___S                    0
#define   PHYA_PCSS_PHY_VER_REG_L___M            0x0FFFFFFF   
#define   PHYA_PCSS_PHY_VER_REG_L___S                          0

#define PHYA_PCSS_PHY_VER_REG_U                   (0x0038007C)
#define   PHYA_PCSS_PHY_VER_REG_U___RWC             QCSR_REG_RO    
#define   PHYA_PCSS_PHY_VER_REG_U___POR          0x00000001
#define   PHYA_PCSS_PHY_VER_REG_U__SEG_ID___POR  0x0
#define   PHYA_PCSS_PHY_VER_REG_U__MAJOR___POR   0x1
#define   PHYA_PCSS_PHY_VER_REG_U__SEG_ID___M    0x00000300
#define   PHYA_PCSS_PHY_VER_REG_U__SEG_ID___S                  8
#define   PHYA_PCSS_PHY_VER_REG_U__MAJOR___M     0x0000000F
#define   PHYA_PCSS_PHY_VER_REG_U__MAJOR___S                   0
#define   PHYA_PCSS_PHY_VER_REG_U___M            0x0000030F   
#define   PHYA_PCSS_PHY_VER_REG_U___S                          0

#define PHYA_PCSS_PHY_OTP_L                       (0x00380080)
#define   PHYA_PCSS_PHY_OTP_L___RWC                 QCSR_REG_RO    
#define   PHYA_PCSS_PHY_OTP_L___POR              0x00000000
#define   PHYA_PCSS_PHY_OTP_L__PHY_OTP___POR     0x00000000
#define   PHYA_PCSS_PHY_OTP_L__PHY_OTP___M       0xFFFFFFFF
#define   PHYA_PCSS_PHY_OTP_L__PHY_OTP___S                     0
#define   PHYA_PCSS_PHY_OTP_L___M                0xFFFFFFFF   
#define   PHYA_PCSS_PHY_OTP_L___S                              0

#define PHYA_PCSS_NTS_CTRL_L                      (0x00380088)
#define   PHYA_PCSS_NTS_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_PCSS_NTS_CTRL_L___POR             0x00000000
#define   PHYA_PCSS_NTS_CTRL_L__NTS_ACK___POR    0x0
#define   PHYA_PCSS_NTS_CTRL_L__NTS_EN___POR     0x0
#define   PHYA_PCSS_NTS_CTRL_L__NTS_ACK___M      0x00000002
#define   PHYA_PCSS_NTS_CTRL_L__NTS_ACK___S                    1
#define   PHYA_PCSS_NTS_CTRL_L__NTS_EN___M       0x00000001
#define   PHYA_PCSS_NTS_CTRL_L__NTS_EN___S                     0
#define   PHYA_PCSS_NTS_CTRL_L___M               0x00000003   
#define   PHYA_PCSS_NTS_CTRL_L___S                             0

#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L             (0x00380090)
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L___POR    0x00000000
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___POR 0x0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___M 0x00000100
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___S               8
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___M 0x00000080
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___S               7
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___M 0x00000078
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___S               3
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___M 0x00000004
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___S               2
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___M 0x00000002
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___S               1
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___M 0x00000001
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___S               0
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L___M      0x000001FF   
#define   PHYA_PCSS_TIMER_WDOG_CLK_EN_L___S                    0

#define PHYA_PCSS_LDPC_CONFIG_0_L                 (0x00380098)
#define   PHYA_PCSS_LDPC_CONFIG_0_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_0_L___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___M 0x0000000F
#define   PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___S               0
#define   PHYA_PCSS_LDPC_CONFIG_0_L___M          0x0000000F   
#define   PHYA_PCSS_LDPC_CONFIG_0_L___S                        0

#define PHYA_PCSS_LDPC_CONFIG_0_U                 (0x0038009C)
#define   PHYA_PCSS_LDPC_CONFIG_0_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_0_U___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___POR 0x000000
#define   PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___M 0x003FFFFF
#define   PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___S               0
#define   PHYA_PCSS_LDPC_CONFIG_0_U___M          0x003FFFFF   
#define   PHYA_PCSS_LDPC_CONFIG_0_U___S                        0

#define PHYA_PCSS_LDPC_CONFIG_1_L                 (0x003800A0)
#define   PHYA_PCSS_LDPC_CONFIG_1_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_1_L___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___POR 0x000000
#define   PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___M 0x00FFFFFF
#define   PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___S               0
#define   PHYA_PCSS_LDPC_CONFIG_1_L___M          0x00FFFFFF   
#define   PHYA_PCSS_LDPC_CONFIG_1_L___S                        0

#define PHYA_PCSS_LDPC_CONFIG_1_U                 (0x003800A4)
#define   PHYA_PCSS_LDPC_CONFIG_1_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_1_U___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___POR 0x00000
#define   PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___M   0x0001FFFF
#define   PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___S                 0
#define   PHYA_PCSS_LDPC_CONFIG_1_U___M          0x0001FFFF   
#define   PHYA_PCSS_LDPC_CONFIG_1_U___S                        0

#define PHYA_PCSS_LDPC_CONFIG_2_L                 (0x003800A8)
#define   PHYA_PCSS_LDPC_CONFIG_2_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_2_L___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___POR 0x00000
#define   PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___M   0x0001FFFF
#define   PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___S                 0
#define   PHYA_PCSS_LDPC_CONFIG_2_L___M          0x0001FFFF   
#define   PHYA_PCSS_LDPC_CONFIG_2_L___S                        0

#define PHYA_PCSS_LDPC_CONFIG_2_U                 (0x003800AC)
#define   PHYA_PCSS_LDPC_CONFIG_2_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_2_U___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___POR 0x00000
#define   PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___M 0x0001FFFF
#define   PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___S               0
#define   PHYA_PCSS_LDPC_CONFIG_2_U___M          0x0001FFFF   
#define   PHYA_PCSS_LDPC_CONFIG_2_U___S                        0

#define PHYA_PCSS_LDPC_CONFIG_3_L                 (0x003800B0)
#define   PHYA_PCSS_LDPC_CONFIG_3_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_3_L___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___POR 0x00000
#define   PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___M 0x0001FFFF
#define   PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___S               0
#define   PHYA_PCSS_LDPC_CONFIG_3_L___M          0x0001FFFF   
#define   PHYA_PCSS_LDPC_CONFIG_3_L___S                        0

#define PHYA_PCSS_LDPC_CONFIG_3_U                 (0x003800B4)
#define   PHYA_PCSS_LDPC_CONFIG_3_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_3_U___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___M 0x01000000
#define   PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___S              24
#define   PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___M 0x00010000
#define   PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___S              16
#define   PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___M 0x00000300
#define   PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___S               8
#define   PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___M 0x00000007
#define   PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___S               0
#define   PHYA_PCSS_LDPC_CONFIG_3_U___M          0x01010307   
#define   PHYA_PCSS_LDPC_CONFIG_3_U___S                        0

#define PHYA_PCSS_LDPC_CONFIG_4_L                 (0x003800B8)
#define   PHYA_PCSS_LDPC_CONFIG_4_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_LDPC_CONFIG_4_L___POR        0x00000000
#define   PHYA_PCSS_LDPC_CONFIG_4_L__START___POR 0x0
#define   PHYA_PCSS_LDPC_CONFIG_4_L__START___M   0x00000001
#define   PHYA_PCSS_LDPC_CONFIG_4_L__START___S                 0
#define   PHYA_PCSS_LDPC_CONFIG_4_L___M          0x00000001   
#define   PHYA_PCSS_LDPC_CONFIG_4_L___S                        0

#define PHYA_PCSS_LDPC_STATUS_L                   (0x003800C0)
#define   PHYA_PCSS_LDPC_STATUS_L___RWC             QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_STATUS_L___POR          0x00000000
#define   PHYA_PCSS_LDPC_STATUS_L__READY___POR   0x0
#define   PHYA_PCSS_LDPC_STATUS_L__READY___M     0x00000001
#define   PHYA_PCSS_LDPC_STATUS_L__READY___S                   0
#define   PHYA_PCSS_LDPC_STATUS_L___M            0x00000001   
#define   PHYA_PCSS_LDPC_STATUS_L___S                          0

#define PHYA_PCSS_LDPC_PARAM_0_L                  (0x003800C8)
#define   PHYA_PCSS_LDPC_PARAM_0_L___RWC            QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_PARAM_0_L___POR         0x00000001
#define   PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___POR 0x0000
#define   PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___POR 0x0
#define   PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___POR 0x1
#define   PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___M 0xFFFF0000
#define   PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___S              16
#define   PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___M 0x00000300
#define   PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___S               8
#define   PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___M 0x00000001
#define   PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___S               0
#define   PHYA_PCSS_LDPC_PARAM_0_L___M           0xFFFF0301   
#define   PHYA_PCSS_LDPC_PARAM_0_L___S                         0

#define PHYA_PCSS_LDPC_PARAM_0_U                  (0x003800CC)
#define   PHYA_PCSS_LDPC_PARAM_0_U___RWC            QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_PARAM_0_U___POR         0x00000000
#define   PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___POR 0x0000
#define   PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___POR 0x0000
#define   PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___M 0xFFFF0000
#define   PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___S              16
#define   PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___M   0x0000FFFF
#define   PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___S                 0
#define   PHYA_PCSS_LDPC_PARAM_0_U___M           0xFFFFFFFF   
#define   PHYA_PCSS_LDPC_PARAM_0_U___S                         0

#define PHYA_PCSS_LDPC_PARAM_1_L                  (0x003800D0)
#define   PHYA_PCSS_LDPC_PARAM_1_L___RWC            QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_PARAM_1_L___POR         0x00000000
#define   PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___POR  0x0000
#define   PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___POR  0x000
#define   PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___M    0xFFFF0000
#define   PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___S                 16
#define   PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___M    0x000007FF
#define   PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___S                  0
#define   PHYA_PCSS_LDPC_PARAM_1_L___M           0xFFFF07FF   
#define   PHYA_PCSS_LDPC_PARAM_1_L___S                         0

#define PHYA_PCSS_LDPC_PARAM_1_U                  (0x003800D4)
#define   PHYA_PCSS_LDPC_PARAM_1_U___RWC            QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_PARAM_1_U___POR         0x00000000
#define   PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___POR 0x0000000
#define   PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___M 0x03FFFFFF
#define   PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___S               0
#define   PHYA_PCSS_LDPC_PARAM_1_U___M           0x03FFFFFF   
#define   PHYA_PCSS_LDPC_PARAM_1_U___S                         0

#define PHYA_PCSS_LDPC_PARAM_2_L                  (0x003800D8)
#define   PHYA_PCSS_LDPC_PARAM_2_L___RWC            QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_PARAM_2_L___POR         0x00000000
#define   PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___POR 0x0000000
#define   PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___M 0x01FFFFFF
#define   PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___S               0
#define   PHYA_PCSS_LDPC_PARAM_2_L___M           0x01FFFFFF   
#define   PHYA_PCSS_LDPC_PARAM_2_L___S                         0

#define PHYA_PCSS_LDPC_CALC_DEBUG_L               (0x003800E0)
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L___RWC         QCSR_REG_RO    
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L___POR      0x00000000
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___POR 0x0
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___POR 0x0
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___M 0x00000F00
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___S               8
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___M 0x00000001
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___S               0
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L___M        0x00000F01   
#define   PHYA_PCSS_LDPC_CALC_DEBUG_L___S                      0

#define PHYA_PCSS_NOC_SMARTMUX_MASK_L             (0x003800E8)
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L___POR    0x00000000
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___POR 0x00
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___M 0x000000FF
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___S               0
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L___M      0x000000FF   
#define   PHYA_PCSS_NOC_SMARTMUX_MASK_L___S                    0

#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L           (0x003800F0)
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L___POR  0x00000000
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___S               0
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_L___S                  0

#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U           (0x003800F4)
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U___POR  0x00000000
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___S               0
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_CONFIG_REG_U___S                  0

#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L          (0x003800F8)
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L___RWC    QCSR_REG_RO    
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___S               0
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L___M   0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_L___S                 0

#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U          (0x003800FC)
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U___RWC    QCSR_REG_RO    
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___S               0
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U___M   0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_STATUS_REG0_U___S                 0

#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L          (0x00380100)
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L___RWC    QCSR_REG_RO    
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___S               0
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L___M   0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_L___S                 0

#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U          (0x00380104)
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U___RWC    QCSR_REG_RO    
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___POR 0x00000000
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___M 0xFFFFFFFF
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___S               0
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U___M   0xFFFFFFFF   
#define   PHYA_PCSS_WATCHDOG_STATUS_REG1_U___S                 0

#define PHYA_PCSS_PCSS_SPARE_L                    (0x00380108)
#define   PHYA_PCSS_PCSS_SPARE_L___RWC              QCSR_REG_RW    
#define   PHYA_PCSS_PCSS_SPARE_L___POR           0x00000000
#define   PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___S               0
#define   PHYA_PCSS_PCSS_SPARE_L___M             0xFFFFFFFF   
#define   PHYA_PCSS_PCSS_SPARE_L___S                           0

#define PHYA_PCSS_PCSS_SPARE_U                    (0x0038010C)
#define   PHYA_PCSS_PCSS_SPARE_U___RWC              QCSR_REG_RW    
#define   PHYA_PCSS_PCSS_SPARE_U___POR           0x00000000
#define   PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___S               0
#define   PHYA_PCSS_PCSS_SPARE_U___M             0xFFFFFFFF   
#define   PHYA_PCSS_PCSS_SPARE_U___S                           0

#define PHYA_PCSS_PCSS_ECO_L                      (0x00380110)
#define   PHYA_PCSS_PCSS_ECO_L___RWC                QCSR_REG_RW    
#define   PHYA_PCSS_PCSS_ECO_L___POR             0x00000000
#define   PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___POR 0x00000000
#define   PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___M   0xFFFFFFFF
#define   PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___S                 0
#define   PHYA_PCSS_PCSS_ECO_L___M               0xFFFFFFFF   
#define   PHYA_PCSS_PCSS_ECO_L___S                             0

#define PHYA_PCSS_PCSS_ECO_U                      (0x00380114)
#define   PHYA_PCSS_PCSS_ECO_U___RWC                QCSR_REG_RW    
#define   PHYA_PCSS_PCSS_ECO_U___POR             0x00000000
#define   PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___POR 0x00000000
#define   PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___M   0xFFFFFFFF
#define   PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___S                 0
#define   PHYA_PCSS_PCSS_ECO_U___M               0xFFFFFFFF   
#define   PHYA_PCSS_PCSS_ECO_U___S                             0

#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L      (0x00380118)
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___POR 0x00000000
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___POR 0x00
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___M 0x000000FF
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___S               0
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___M 0x000000FF   
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___S               0

#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L      (0x00380120)
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___POR 0x00000000
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___POR 0x00
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___M 0x000000FF
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___S               0
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___M 0x000000FF   
#define   PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___S               0

#define PHYA_PCSS_TIMEOUT_DEBUG0_L                (0x00380128)
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG0_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG0_U                (0x0038012C)
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG0_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG1_L                (0x00380130)
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG1_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG1_U                (0x00380134)
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG1_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG2_L                (0x00380138)
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG2_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG2_U                (0x0038013C)
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG2_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG3_L                (0x00380140)
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG3_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG3_U                (0x00380144)
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG3_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG4_L                (0x00380148)
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG4_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG4_U                (0x0038014C)
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG4_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG5_L                (0x00380150)
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG5_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG5_U                (0x00380154)
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG5_U___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG6_L                (0x00380158)
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L___POR       0x00000000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___POR 0x00
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___M 0x00FFFF00
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___S               8
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___M 0x000000FF
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L___M         0x00FFFFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG6_L___S                       0

#define PHYA_PCSS_TIMEOUT_DEBUG6_U                (0x0038015C)
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U___POR       0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___POR 0x1
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___POR 0x0
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___POR 0x0000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___M 0x00040000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___S              18
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___M 0x00020000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___S              17
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___M 0x00010000
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___S              16
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___M 0x0000FFFF
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___S               0
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U___M         0x0007FFFF   
#define   PHYA_PCSS_TIMEOUT_DEBUG6_U___S                       0

#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L             (0x00380160)
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___POR    0x00010001
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___POR 0x1
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___POR 0x0001
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___M 0x00010000
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___S              16
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___M 0x0000FFFF
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___S               0
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___M      0x0001FFFF   
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___S                    0

#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U             (0x00380164)
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___POR    0x00010138
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___POR 0x1
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___POR 0x0138
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___M 0x00010000
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___S              16
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___M 0x0000FFFF
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___S               0
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___M      0x0001FFFF   
#define   PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___S                    0

#define PHYA_PCSS_NOC_CFG_STS_0_L                 (0x00380168)
#define   PHYA_PCSS_NOC_CFG_STS_0_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_NOC_CFG_STS_0_L___POR        0x01900028
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___POR 0x0190
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___POR 0x0028
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___M 0xFFFF0000
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___S              16
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___M 0x0000FFFF
#define   PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___S               0
#define   PHYA_PCSS_NOC_CFG_STS_0_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_NOC_CFG_STS_0_L___S                        0

#define PHYA_PCSS_NOC_CFG_STS_0_U                 (0x0038016C)
#define   PHYA_PCSS_NOC_CFG_STS_0_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_NOC_CFG_STS_0_U___POR        0x00030014
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___POR 0x0
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___POR 0x3
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___POR 0x0014
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___M 0x01000000
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___S              24
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___M 0x00030000
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___S              16
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___M 0x0000FFFF
#define   PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___S               0
#define   PHYA_PCSS_NOC_CFG_STS_0_U___M          0x0103FFFF   
#define   PHYA_PCSS_NOC_CFG_STS_0_U___S                        0

#define PHYA_PCSS_NOC_CFG_STS_1_L                 (0x00380170)
#define   PHYA_PCSS_NOC_CFG_STS_1_L___RWC           QCSR_REG_RO    
#define   PHYA_PCSS_NOC_CFG_STS_1_L___POR        0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___POR 0x0000
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___POR 0x0000
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___M 0xFFFF0000
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___S              16
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___M 0x0000FFFF
#define   PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___S               0
#define   PHYA_PCSS_NOC_CFG_STS_1_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_NOC_CFG_STS_1_L___S                        0

#define PHYA_PCSS_NOC_CFG_STS_1_U                 (0x00380174)
#define   PHYA_PCSS_NOC_CFG_STS_1_U___RWC           QCSR_REG_RO    
#define   PHYA_PCSS_NOC_CFG_STS_1_U___POR        0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___POR 0x0
#define   PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___M 0x00000001
#define   PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___S               0
#define   PHYA_PCSS_NOC_CFG_STS_1_U___M          0x00000001   
#define   PHYA_PCSS_NOC_CFG_STS_1_U___S                        0

#define PHYA_PCSS_NOC_CFG_STS_2_L                 (0x00380178)
#define   PHYA_PCSS_NOC_CFG_STS_2_L___RWC           QCSR_REG_RO    
#define   PHYA_PCSS_NOC_CFG_STS_2_L___POR        0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___POR 0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___M 0xFFFFFFFF
#define   PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___S               0
#define   PHYA_PCSS_NOC_CFG_STS_2_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_NOC_CFG_STS_2_L___S                        0

#define PHYA_PCSS_NOC_CFG_STS_2_U                 (0x0038017C)
#define   PHYA_PCSS_NOC_CFG_STS_2_U___RWC           QCSR_REG_RO    
#define   PHYA_PCSS_NOC_CFG_STS_2_U___POR        0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___POR 0x00000000
#define   PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___M 0xFFFFFFFF
#define   PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___S               0
#define   PHYA_PCSS_NOC_CFG_STS_2_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_NOC_CFG_STS_2_U___S                        0

#define PHYA_PCSS_DMA_AXI_CTRL_L                  (0x00380180)
#define   PHYA_PCSS_DMA_AXI_CTRL_L___RWC            QCSR_REG_RW    
#define   PHYA_PCSS_DMA_AXI_CTRL_L___POR         0x00000020
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___POR 0x1
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___POR 0x0
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___M 0x00000040
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___S               6
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___M 0x00000020
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___S               5
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___M 0x00000010
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___S               4
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___M 0x00000008
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___S               3
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___M 0x00000004
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___S               2
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___M 0x00000002
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___S               1
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___M 0x00000001
#define   PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___S               0
#define   PHYA_PCSS_DMA_AXI_CTRL_L___M           0x0000007F   
#define   PHYA_PCSS_DMA_AXI_CTRL_L___S                         0

#define PHYA_PCSS_DUMMY_L                         (0x00380200)
#define   PHYA_PCSS_DUMMY_L___RWC                   QCSR_REG_RW    
#define   PHYA_PCSS_DUMMY_L___POR                0x00000000
#define   PHYA_PCSS_DUMMY_L__DUMMY___POR         0x0
#define   PHYA_PCSS_DUMMY_L__DUMMY___M           0x00000001
#define   PHYA_PCSS_DUMMY_L__DUMMY___S                         0
#define   PHYA_PCSS_DUMMY_L___M                  0x00000001   
#define   PHYA_PCSS_DUMMY_L___S                                0

#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L            (0x00380400)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L            (0x00380408)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L            (0x00380410)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L            (0x00380418)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L            (0x00380420)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L            (0x00380428)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L            (0x00380430)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L            (0x00380438)
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC0_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L             (0x00380440)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG0_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L             (0x00380448)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG1_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L             (0x00380450)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG2_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L             (0x00380458)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG3_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L             (0x00380460)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG4_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L             (0x00380468)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG5_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L             (0x00380470)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG6_L___S                    0

#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L             (0x00380478)
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L___POR    0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___POR 0x0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___S               0
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L___M      0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY2_REG7_L___S                    0

#define PHYA_PCSS_DMAC0_DMA_CTRL_L                (0x00380480)
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC0_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC0_DMA_CTRL_U                (0x00380484)
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC0_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L            (0x00380488)
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U            (0x0038048C)
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC0_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L            (0x00380490)
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L           (0x00380498)
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U           (0x0038049C)
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L            (0x003804A0)
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L           (0x003804A8)
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___M    0x000601FF   
#define   PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC0_DMA_SPARE_L               (0x003804B0)
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC0_DMA_SPARE_U               (0x003804B4)
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC0_DMA_ECO_L                 (0x003804B8)
#define   PHYA_PCSS_DMAC0_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC0_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC0_DMA_ECO_U                 (0x003804BC)
#define   PHYA_PCSS_DMAC0_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC0_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0           (0x003804C0)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1           (0x003804D8)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2           (0x003804F0)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3           (0x00380508)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4           (0x00380520)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5           (0x00380538)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6           (0x00380550)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7           (0x00380568)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0           (0x003804C4)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1           (0x003804DC)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2           (0x003804F4)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3           (0x0038050C)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4           (0x00380524)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5           (0x0038053C)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6           (0x00380554)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7           (0x0038056C)
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0           (0x003804C8)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1           (0x003804E0)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2           (0x003804F8)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3           (0x00380510)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4           (0x00380528)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5           (0x00380540)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6           (0x00380558)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7           (0x00380570)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0           (0x003804CC)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1           (0x003804E4)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2           (0x003804FC)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3           (0x00380514)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4           (0x0038052C)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5           (0x00380544)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6           (0x0038055C)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7           (0x00380574)
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0           (0x003804D0)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1           (0x003804E8)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2           (0x00380500)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3           (0x00380518)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4           (0x00380530)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5           (0x00380548)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6           (0x00380560)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7           (0x00380578)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0           (0x003804D4)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1           (0x003804EC)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2           (0x00380504)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3           (0x0038051C)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4           (0x00380534)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5           (0x0038054C)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6           (0x00380564)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7           (0x0038057C)
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L      (0x00380580)
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___M 0x000000FF   
#define   PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC0_DUMMY_L                   (0x00380648)
#define   PHYA_PCSS_DMAC0_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC0_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC0_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC0_DUMMY_L___S                          0

#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L            (0x00380800)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L            (0x00380808)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L            (0x00380810)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L            (0x00380818)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L            (0x00380820)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L            (0x00380828)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L            (0x00380830)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L            (0x00380838)
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC1_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L             (0x00380840)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG0_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L             (0x00380848)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG1_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L             (0x00380850)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG2_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L             (0x00380858)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG3_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L             (0x00380860)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG4_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L             (0x00380868)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG5_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L             (0x00380870)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG6_L___S                    0

#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L             (0x00380878)
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L___POR    0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___POR 0x0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___S               0
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L___M      0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY2_REG7_L___S                    0

#define PHYA_PCSS_DMAC1_DMA_CTRL_L                (0x00380880)
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC1_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC1_DMA_CTRL_U                (0x00380884)
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC1_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L            (0x00380888)
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U            (0x0038088C)
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC1_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L            (0x00380890)
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L           (0x00380898)
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U           (0x0038089C)
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L            (0x003808A0)
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L           (0x003808A8)
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___M    0x000601FF   
#define   PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC1_DMA_SPARE_L               (0x003808B0)
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC1_DMA_SPARE_U               (0x003808B4)
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC1_DMA_ECO_L                 (0x003808B8)
#define   PHYA_PCSS_DMAC1_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC1_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC1_DMA_ECO_U                 (0x003808BC)
#define   PHYA_PCSS_DMAC1_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC1_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0           (0x003808C0)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1           (0x003808D8)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2           (0x003808F0)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3           (0x00380908)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4           (0x00380920)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5           (0x00380938)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6           (0x00380950)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7           (0x00380968)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0           (0x003808C4)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1           (0x003808DC)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2           (0x003808F4)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3           (0x0038090C)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4           (0x00380924)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5           (0x0038093C)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6           (0x00380954)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7           (0x0038096C)
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0           (0x003808C8)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1           (0x003808E0)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2           (0x003808F8)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3           (0x00380910)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4           (0x00380928)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5           (0x00380940)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6           (0x00380958)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7           (0x00380970)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0           (0x003808CC)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1           (0x003808E4)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2           (0x003808FC)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3           (0x00380914)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4           (0x0038092C)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5           (0x00380944)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6           (0x0038095C)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7           (0x00380974)
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0           (0x003808D0)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1           (0x003808E8)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2           (0x00380900)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3           (0x00380918)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4           (0x00380930)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5           (0x00380948)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6           (0x00380960)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7           (0x00380978)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0           (0x003808D4)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1           (0x003808EC)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2           (0x00380904)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3           (0x0038091C)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4           (0x00380934)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5           (0x0038094C)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6           (0x00380964)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7           (0x0038097C)
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L      (0x00380980)
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___M 0x000000FF   
#define   PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC1_DUMMY_L                   (0x00380A48)
#define   PHYA_PCSS_DMAC1_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC1_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC1_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC1_DUMMY_L___S                          0

#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L            (0x00380C00)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L            (0x00380C08)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L            (0x00380C10)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L            (0x00380C18)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L            (0x00380C20)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L            (0x00380C28)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L            (0x00380C30)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L            (0x00380C38)
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC2_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L             (0x00380C40)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG0_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L             (0x00380C48)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG1_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L             (0x00380C50)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG2_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L             (0x00380C58)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG3_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L             (0x00380C60)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG4_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L             (0x00380C68)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG5_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L             (0x00380C70)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG6_L___S                    0

#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L             (0x00380C78)
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L___POR    0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___POR 0x0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___S               0
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L___M      0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY2_REG7_L___S                    0

#define PHYA_PCSS_DMAC2_DMA_CTRL_L                (0x00380C80)
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC2_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC2_DMA_CTRL_U                (0x00380C84)
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC2_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L            (0x00380C88)
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U            (0x00380C8C)
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC2_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L            (0x00380C90)
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L           (0x00380C98)
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U           (0x00380C9C)
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L            (0x00380CA0)
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L           (0x00380CA8)
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___M    0x000601FF   
#define   PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC2_DMA_SPARE_L               (0x00380CB0)
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC2_DMA_SPARE_U               (0x00380CB4)
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC2_DMA_ECO_L                 (0x00380CB8)
#define   PHYA_PCSS_DMAC2_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC2_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC2_DMA_ECO_U                 (0x00380CBC)
#define   PHYA_PCSS_DMAC2_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC2_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0           (0x00380CC0)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1           (0x00380CD8)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2           (0x00380CF0)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3           (0x00380D08)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4           (0x00380D20)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5           (0x00380D38)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6           (0x00380D50)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7           (0x00380D68)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0           (0x00380CC4)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1           (0x00380CDC)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2           (0x00380CF4)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3           (0x00380D0C)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4           (0x00380D24)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5           (0x00380D3C)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6           (0x00380D54)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7           (0x00380D6C)
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0           (0x00380CC8)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1           (0x00380CE0)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2           (0x00380CF8)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3           (0x00380D10)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4           (0x00380D28)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5           (0x00380D40)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6           (0x00380D58)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7           (0x00380D70)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0           (0x00380CCC)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1           (0x00380CE4)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2           (0x00380CFC)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3           (0x00380D14)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4           (0x00380D2C)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5           (0x00380D44)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6           (0x00380D5C)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7           (0x00380D74)
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0           (0x00380CD0)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1           (0x00380CE8)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2           (0x00380D00)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3           (0x00380D18)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4           (0x00380D30)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5           (0x00380D48)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6           (0x00380D60)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7           (0x00380D78)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0           (0x00380CD4)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1           (0x00380CEC)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2           (0x00380D04)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3           (0x00380D1C)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4           (0x00380D34)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5           (0x00380D4C)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6           (0x00380D64)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7           (0x00380D7C)
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L      (0x00380D80)
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___M 0x000000FF   
#define   PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC2_DUMMY_L                   (0x00380E48)
#define   PHYA_PCSS_DMAC2_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC2_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC2_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC2_DUMMY_L___S                          0

#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L            (0x00381000)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L            (0x00381008)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L            (0x00381010)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L            (0x00381018)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L            (0x00381020)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L            (0x00381028)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L            (0x00381030)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L            (0x00381038)
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC3_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L             (0x00381040)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG0_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L             (0x00381048)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG1_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L             (0x00381050)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG2_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L             (0x00381058)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG3_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L             (0x00381060)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG4_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L             (0x00381068)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG5_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L             (0x00381070)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG6_L___S                    0

#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L             (0x00381078)
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L___POR    0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___POR 0x0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___S               0
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L___M      0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY2_REG7_L___S                    0

#define PHYA_PCSS_DMAC3_DMA_CTRL_L                (0x00381080)
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC3_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC3_DMA_CTRL_U                (0x00381084)
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC3_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L            (0x00381088)
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U            (0x0038108C)
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC3_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L            (0x00381090)
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L           (0x00381098)
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U           (0x0038109C)
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L            (0x003810A0)
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L           (0x003810A8)
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___M    0x000601FF   
#define   PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC3_DMA_SPARE_L               (0x003810B0)
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC3_DMA_SPARE_U               (0x003810B4)
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC3_DMA_ECO_L                 (0x003810B8)
#define   PHYA_PCSS_DMAC3_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC3_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC3_DMA_ECO_U                 (0x003810BC)
#define   PHYA_PCSS_DMAC3_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC3_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0           (0x003810C0)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1           (0x003810D8)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2           (0x003810F0)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3           (0x00381108)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4           (0x00381120)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5           (0x00381138)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6           (0x00381150)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7           (0x00381168)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0           (0x003810C4)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1           (0x003810DC)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2           (0x003810F4)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3           (0x0038110C)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4           (0x00381124)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5           (0x0038113C)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6           (0x00381154)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7           (0x0038116C)
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0           (0x003810C8)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1           (0x003810E0)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2           (0x003810F8)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3           (0x00381110)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4           (0x00381128)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5           (0x00381140)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6           (0x00381158)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7           (0x00381170)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0           (0x003810CC)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1           (0x003810E4)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2           (0x003810FC)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3           (0x00381114)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4           (0x0038112C)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5           (0x00381144)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6           (0x0038115C)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7           (0x00381174)
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0           (0x003810D0)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1           (0x003810E8)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2           (0x00381100)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3           (0x00381118)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4           (0x00381130)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5           (0x00381148)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6           (0x00381160)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7           (0x00381178)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0           (0x003810D4)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1           (0x003810EC)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2           (0x00381104)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3           (0x0038111C)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4           (0x00381134)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5           (0x0038114C)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6           (0x00381164)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7           (0x0038117C)
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L      (0x00381180)
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___M 0x000000FF   
#define   PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC3_DUMMY_L                   (0x00381248)
#define   PHYA_PCSS_DMAC3_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC3_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC3_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC3_DUMMY_L___S                          0

#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L            (0x00381400)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L            (0x00381408)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L            (0x00381410)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L            (0x00381418)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L            (0x00381420)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L            (0x00381428)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L            (0x00381430)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L            (0x00381438)
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC4_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L             (0x00381440)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG0_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L             (0x00381448)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG1_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L             (0x00381450)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG2_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L             (0x00381458)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG3_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L             (0x00381460)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG4_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L             (0x00381468)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG5_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L             (0x00381470)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG6_L___S                    0

#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L             (0x00381478)
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L___RWC       QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L___POR    0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___POR 0x0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___S               0
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L___M      0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY2_REG7_L___S                    0

#define PHYA_PCSS_DMAC4_DMA_CTRL_L                (0x00381480)
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC4_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC4_DMA_CTRL_U                (0x00381484)
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC4_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L            (0x00381488)
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U            (0x0038148C)
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC4_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L            (0x00381490)
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L           (0x00381498)
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U           (0x0038149C)
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L            (0x003814A0)
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L           (0x003814A8)
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___M    0x000601FF   
#define   PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC4_DMA_SPARE_L               (0x003814B0)
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC4_DMA_SPARE_U               (0x003814B4)
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC4_DMA_ECO_L                 (0x003814B8)
#define   PHYA_PCSS_DMAC4_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC4_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC4_DMA_ECO_U                 (0x003814BC)
#define   PHYA_PCSS_DMAC4_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC4_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0           (0x003814C0)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1           (0x003814D8)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2           (0x003814F0)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3           (0x00381508)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4           (0x00381520)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5           (0x00381538)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6           (0x00381550)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7           (0x00381568)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0           (0x003814C4)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1           (0x003814DC)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2           (0x003814F4)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3           (0x0038150C)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4           (0x00381524)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5           (0x0038153C)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6           (0x00381554)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7           (0x0038156C)
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0           (0x003814C8)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1           (0x003814E0)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2           (0x003814F8)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3           (0x00381510)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4           (0x00381528)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5           (0x00381540)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6           (0x00381558)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7           (0x00381570)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0           (0x003814CC)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1           (0x003814E4)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2           (0x003814FC)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3           (0x00381514)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4           (0x0038152C)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5           (0x00381544)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6           (0x0038155C)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7           (0x00381574)
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0           (0x003814D0)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1           (0x003814E8)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2           (0x00381500)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3           (0x00381518)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4           (0x00381530)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5           (0x00381548)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6           (0x00381560)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7           (0x00381578)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0           (0x003814D4)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1           (0x003814EC)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2           (0x00381504)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3           (0x0038151C)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4           (0x00381534)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5           (0x0038154C)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6           (0x00381564)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7           (0x0038157C)
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L      (0x00381580)
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___M 0x000000FF   
#define   PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC4_DUMMY_L                   (0x00381648)
#define   PHYA_PCSS_DMAC4_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC4_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC4_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC4_DUMMY_L___S                          0

#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L       (0x00381800)
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___S               0
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___S               0

#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U       (0x00381804)
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___POR 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___POR 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___S               0
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___S               0

#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L      (0x00381808)
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___POR 0x00000020
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___POR 0x1
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___M 0x00000080
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___S               7
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___M 0x00000040
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___S               6
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___M 0x00000020
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___S               5
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___M 0x0000000C
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___S               2
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___M 0x00000002
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___S               1
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___S               0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___M 0x000000EF   
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___S               0

#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U      (0x0038180C)
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___RWC QCSR_REG_WO    
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___S               0
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___S               0

#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L      (0x00381810)
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___S               0
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___M 0x00000001   
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___S               0

#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U      (0x00381814)
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___S               0
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___M 0x00000001   
#define   PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___S               0

#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L          (0x00381818)
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___S               0
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___M   0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___S                 0

#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L       (0x00381820)
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___S               0
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___S               0

#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U       (0x00381824)
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___POR 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___POR 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___S               0
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___S               0

#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L      (0x00381828)
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___POR 0x00000020
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___POR 0x1
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___M 0x00000080
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___S               7
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___M 0x00000040
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___S               6
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___M 0x00000020
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___S               5
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___M 0x0000000C
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___S               2
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___M 0x00000002
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___S               1
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___S               0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___M 0x000000EF   
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___S               0

#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U      (0x0038182C)
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___RWC QCSR_REG_WO    
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___S               0
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___M 0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___S               0

#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L      (0x00381830)
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___S               0
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___M 0x00000001   
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___S               0

#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U      (0x00381834)
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___RWC QCSR_REG_RO    
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___POR 0x0
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___M 0x00000001
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___S               0
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___M 0x00000001   
#define   PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___S               0

#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L          (0x00381838)
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___POR 0x00000000
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___M 0xFFFFFFFF
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___S               0
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___M   0xFFFFFFFF   
#define   PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___S                 0

#define PHYA_PCSS_WDOG_WDOGLOAD_L                 (0x00381C00)
#define   PHYA_PCSS_WDOG_WDOGLOAD_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_WDOG_WDOGLOAD_L___POR        0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___POR 0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___M 0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___S               0
#define   PHYA_PCSS_WDOG_WDOGLOAD_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_WDOG_WDOGLOAD_L___S                        0

#define PHYA_PCSS_WDOG_WDOGLOAD_U                 (0x00381C04)
#define   PHYA_PCSS_WDOG_WDOGLOAD_U___RWC           QCSR_REG_RO    
#define   PHYA_PCSS_WDOG_WDOGLOAD_U___POR        0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___POR 0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___M 0xFFFFFFFF
#define   PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___S               0
#define   PHYA_PCSS_WDOG_WDOGLOAD_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_WDOG_WDOGLOAD_U___S                        0

#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L            (0x00381C08)
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L___POR   0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___POR 0x0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___POR 0x0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___M 0x00000002
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___S               1
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___M 0x00000001
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___S               0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L___M     0x00000003   
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_L___S                   0

#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U            (0x00381C0C)
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U___RWC      QCSR_REG_WO    
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U___POR   0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___POR 0x0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___M 0x00000001
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___S               0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U___M     0x00000001   
#define   PHYA_PCSS_WDOG_CONTROL_CLR_0_U___S                   0

#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L            (0x00381C10)
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L___POR   0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___POR 0x0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___M 0x00000001
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___S               0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L___M     0x00000001   
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_L___S                   0

#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U            (0x00381C14)
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U___POR   0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___POR 0x0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___M 0x00000001
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___S               0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U___M     0x00000001   
#define   PHYA_PCSS_WDOG_CONTROL_CLR_1_U___S                   0

#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L            (0x00382800)
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L___POR   0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___POR 0x00000000
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___M 0xFFFFFFFF
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___S               0
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L___M     0xFFFFFFFF   
#define   PHYA_PCSS_WDOG_CONTROL_CLR_2_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L            (0x00382C00)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L            (0x00382C08)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L            (0x00382C10)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L            (0x00382C18)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L            (0x00382C20)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L            (0x00382C28)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L            (0x00382C30)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L            (0x00382C38)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L            (0x00382C40)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG8_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L            (0x00382C48)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L___M     0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG9_L___S                   0

#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L           (0x00382C50)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG10_L___S                  0

#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L           (0x00382C58)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG11_L___S                  0

#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L           (0x00382C60)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG12_L___S                  0

#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L           (0x00382C68)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG13_L___S                  0

#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L           (0x00382C70)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG14_L___S                  0

#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L           (0x00382C78)
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___POR 0x0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___M 0x00000001
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___S               0
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L___M    0x00000001   
#define   PHYA_PCSS_DMAC5_TRIGGER_REG15_L___S                  0

#define PHYA_PCSS_DMAC5_DMA_CTRL_L                (0x00382C80)
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC5_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC5_DMA_CTRL_U                (0x00382C84)
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC5_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L            (0x00382C88)
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U            (0x00382C8C)
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC5_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L            (0x00382C90)
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L           (0x00382C98)
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U           (0x00382C9C)
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L            (0x00382CA0)
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L           (0x00382CA8)
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x0000
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x0001FFFE
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___M    0x0007FFFF   
#define   PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC5_DMA_SPARE_L               (0x00382CB0)
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC5_DMA_SPARE_U               (0x00382CB4)
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC5_DMA_ECO_L                 (0x00382CB8)
#define   PHYA_PCSS_DMAC5_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC5_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC5_DMA_ECO_U                 (0x00382CBC)
#define   PHYA_PCSS_DMAC5_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC5_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0           (0x00382CC0)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1           (0x00382CD8)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2           (0x00382CF0)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3           (0x00382D08)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4           (0x00382D20)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5           (0x00382D38)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6           (0x00382D50)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7           (0x00382D68)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8           (0x00382D80)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9           (0x00382D98)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10          (0x00382DB0)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11          (0x00382DC8)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12          (0x00382DE0)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13          (0x00382DF8)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14          (0x00382E10)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15          (0x00382E28)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0           (0x00382CC4)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1           (0x00382CDC)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2           (0x00382CF4)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3           (0x00382D0C)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4           (0x00382D24)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5           (0x00382D3C)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6           (0x00382D54)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7           (0x00382D6C)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8           (0x00382D84)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9           (0x00382D9C)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10          (0x00382DB4)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11          (0x00382DCC)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12          (0x00382DE4)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13          (0x00382DFC)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14          (0x00382E14)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15          (0x00382E2C)
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0           (0x00382CC8)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1           (0x00382CE0)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2           (0x00382CF8)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3           (0x00382D10)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4           (0x00382D28)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5           (0x00382D40)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6           (0x00382D58)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7           (0x00382D70)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8           (0x00382D88)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9           (0x00382DA0)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10          (0x00382DB8)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11          (0x00382DD0)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12          (0x00382DE8)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13          (0x00382E00)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14          (0x00382E18)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15          (0x00382E30)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0           (0x00382CCC)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1           (0x00382CE4)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2           (0x00382CFC)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3           (0x00382D14)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4           (0x00382D2C)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5           (0x00382D44)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6           (0x00382D5C)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7           (0x00382D74)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8           (0x00382D8C)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9           (0x00382DA4)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10          (0x00382DBC)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11          (0x00382DD4)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12          (0x00382DEC)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13          (0x00382E04)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14          (0x00382E1C)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15          (0x00382E34)
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0           (0x00382CD0)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1           (0x00382CE8)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2           (0x00382D00)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3           (0x00382D18)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4           (0x00382D30)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5           (0x00382D48)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6           (0x00382D60)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7           (0x00382D78)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8           (0x00382D90)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9           (0x00382DA8)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10          (0x00382DC0)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11          (0x00382DD8)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12          (0x00382DF0)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13          (0x00382E08)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14          (0x00382E20)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15          (0x00382E38)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0           (0x00382CD4)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1           (0x00382CEC)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2           (0x00382D04)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3           (0x00382D1C)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4           (0x00382D34)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5           (0x00382D4C)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6           (0x00382D64)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7           (0x00382D7C)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8           (0x00382D94)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9           (0x00382DAC)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___S                  0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10          (0x00382DC4)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11          (0x00382DDC)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12          (0x00382DF4)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13          (0x00382E0C)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14          (0x00382E24)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___S                 0

#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15          (0x00382E3C)
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___S               6
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___S               5
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___S               2
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___S               0
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___S                 0

#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L      (0x00382E40)
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x0000
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x0000FFFF
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___M 0x0000FFFF   
#define   PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC5_DUMMY_L                   (0x00382E48)
#define   PHYA_PCSS_DMAC5_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC5_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC5_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC5_DUMMY_L___S                          0

#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L            (0x00383000)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG0_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L            (0x00383008)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG1_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L            (0x00383010)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG2_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L            (0x00383018)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG3_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L            (0x00383020)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG4_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L            (0x00383028)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG5_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L            (0x00383030)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG6_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L            (0x00383038)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG7_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L            (0x00383040)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG8_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L            (0x00383048)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L___RWC      QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L___M     0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG9_L___S                   0

#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L           (0x00383050)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG10_L___S                  0

#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L           (0x00383058)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG11_L___S                  0

#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L           (0x00383060)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG12_L___S                  0

#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L           (0x00383068)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG13_L___S                  0

#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L           (0x00383070)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG14_L___S                  0

#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L           (0x00383078)
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___POR 0x0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___M 0x00000001
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___S               0
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L___M    0x00000001   
#define   PHYA_PCSS_DMAC6_TRIGGER_REG15_L___S                  0

#define PHYA_PCSS_DMAC6_DMA_CTRL_L                (0x00383080)
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L___POR       0x00000000
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___S               0
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L___M         0x00000001   
#define   PHYA_PCSS_DMAC6_DMA_CTRL_L___S                       0

#define PHYA_PCSS_DMAC6_DMA_CTRL_U                (0x00383084)
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U___POR       0x00000000
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___S               0
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U___M         0x0000003F   
#define   PHYA_PCSS_DMAC6_DMA_CTRL_U___S                       0

#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L            (0x00383088)
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___S              24
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___S              16
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___S               8
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___S               0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L___M     0x0F0F0F01   
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_L___S                   0

#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U            (0x0038308C)
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U___POR   0x00000000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___S              16
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___S               8
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___S               0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U___M     0x01FF0F0F   
#define   PHYA_PCSS_DMAC6_DMA_STATUS_0_U___S                   0

#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L            (0x00383090)
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___S               0
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L___M     0x00FFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_STATUS_1_L___S                   0

#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L           (0x00383098)
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S               0
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___S                  0

#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U           (0x0038309C)
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S               0
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___S                  0

#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L            (0x003830A0)
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___RWC      QCSR_REG_RO    
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___POR   0x00000000
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S               8
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S               0
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___M     0x0000FFFF   
#define   PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___S                   0

#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L           (0x003830A8)
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x0000
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S              18
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___S              17
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x0001FFFE
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___S               1
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___S               0
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___M    0x0007FFFF   
#define   PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___S                  0

#define PHYA_PCSS_DMAC6_DMA_SPARE_L               (0x003830B0)
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L___POR      0x00000000
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___S               0
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_SPARE_L___S                      0

#define PHYA_PCSS_DMAC6_DMA_SPARE_U               (0x003830B4)
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U___RWC         QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U___POR      0x00000000
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___S               0
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U___M        0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_SPARE_U___S                      0

#define PHYA_PCSS_DMAC6_DMA_ECO_L                 (0x003830B8)
#define   PHYA_PCSS_DMAC6_DMA_ECO_L___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_ECO_L___POR        0x00000000
#define   PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___S               0
#define   PHYA_PCSS_DMAC6_DMA_ECO_L___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_ECO_L___S                        0

#define PHYA_PCSS_DMAC6_DMA_ECO_U                 (0x003830BC)
#define   PHYA_PCSS_DMAC6_DMA_ECO_U___RWC           QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMA_ECO_U___POR        0x00000000
#define   PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___S               0
#define   PHYA_PCSS_DMAC6_DMA_ECO_U___M          0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DMA_ECO_U___S                        0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0           (0x003830C0)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1           (0x003830D8)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2           (0x003830F0)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3           (0x00383108)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4           (0x00383120)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5           (0x00383138)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6           (0x00383150)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7           (0x00383168)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8           (0x00383180)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9           (0x00383198)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10          (0x003831B0)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11          (0x003831C8)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12          (0x003831E0)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13          (0x003831F8)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14          (0x00383210)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15          (0x00383228)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0           (0x003830C4)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1           (0x003830DC)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2           (0x003830F4)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3           (0x0038310C)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4           (0x00383124)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5           (0x0038313C)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6           (0x00383154)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7           (0x0038316C)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8           (0x00383184)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9           (0x0038319C)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10          (0x003831B4)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11          (0x003831CC)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12          (0x003831E4)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13          (0x003831FC)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14          (0x00383214)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15          (0x0038322C)
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___POR 0x00000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___M 0xFFFFC000
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___M 0x00003FC0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___M 0x0000003F
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0           (0x003830C8)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1           (0x003830E0)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2           (0x003830F8)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3           (0x00383110)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4           (0x00383128)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5           (0x00383140)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6           (0x00383158)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7           (0x00383170)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8           (0x00383188)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9           (0x003831A0)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10          (0x003831B8)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11          (0x003831D0)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12          (0x003831E8)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13          (0x00383200)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14          (0x00383218)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15          (0x00383230)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0           (0x003830CC)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1           (0x003830E4)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2           (0x003830FC)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3           (0x00383114)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4           (0x0038312C)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5           (0x00383144)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6           (0x0038315C)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7           (0x00383174)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8           (0x0038318C)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9           (0x003831A4)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10          (0x003831BC)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11          (0x003831D4)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12          (0x003831EC)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13          (0x00383204)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14          (0x0038321C)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15          (0x00383234)
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0           (0x003830D0)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1           (0x003830E8)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2           (0x00383100)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3           (0x00383118)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4           (0x00383130)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5           (0x00383148)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6           (0x00383160)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7           (0x00383178)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8           (0x00383190)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9           (0x003831A8)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10          (0x003831C0)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11          (0x003831D8)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12          (0x003831F0)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13          (0x00383208)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14          (0x00383220)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15          (0x00383238)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___M 0xFFFFFFFF
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0           (0x003830D4)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1           (0x003830EC)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2           (0x00383104)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3           (0x0038311C)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4           (0x00383134)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5           (0x0038314C)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6           (0x00383164)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7           (0x0038317C)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8           (0x00383194)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9           (0x003831AC)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___RWC     QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___POR  0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___M    0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___S                  0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10          (0x003831C4)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11          (0x003831DC)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12          (0x003831F4)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13          (0x0038320C)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14          (0x00383224)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___S                 0

#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15          (0x0038323C)
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___RWC    QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___POR 0x000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___POR 0x00
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___POR 0x0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___M 0xFFF00000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___S              20
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___M 0x000FC000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___S              14
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___M 0x00002000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___S              13
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___M 0x00001000
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___S              12
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___M 0x00000800
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___S              11
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___M 0x00000400
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___S              10
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___M 0x00000200
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___S               9
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___M 0x00000100
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___S               8
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___M 0x00000080
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___S               7
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___M 0x00000040
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___S               6
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___M 0x00000020
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___S               5
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___M 0x00000010
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___S               4
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___M 0x00000008
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___S               3
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___M 0x00000004
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___S               2
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___M 0x00000002
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___S               1
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___M 0x00000001
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___S               0
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___M   0xFFFFFFFF   
#define   PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___S                 0

#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L      (0x00383240)
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___POR 0x00000000
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x0000
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x0000FFFF
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S               0
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___M 0x0000FFFF   
#define   PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___S               0

#define PHYA_PCSS_DMAC6_DUMMY_L                   (0x00383248)
#define   PHYA_PCSS_DMAC6_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_PCSS_DMAC6_DUMMY_L___POR          0x00000000
#define   PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___POR   0x0
#define   PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___M     0x00000001
#define   PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___S                   0
#define   PHYA_PCSS_DMAC6_DUMMY_L___M            0x00000001   
#define   PHYA_PCSS_DMAC6_DUMMY_L___S                          0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW        (0x00388000)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___RWC  QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___POR 0x00021F1B
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___POR 0x02
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___POR 0x1F1B
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH       (0x00388004)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW     (0x00388008)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S               2
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___S               1
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___M 0x00000007   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW      (0x00388010)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW  (0x00388018)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW     (0x00388020)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW    (0x00388028)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW    (0x00388030)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW (0x00388038)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW    (0x00388040)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW     (0x00388048)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW (0x00388100)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW (0x00388140)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW (0x00388180)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW (0x003881C0)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW (0x00388200)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW (0x00388240)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW (0x00388280)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW (0x003882C0)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW (0x00388300)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW (0x00388340)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW (0x00388380)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW (0x003883C0)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW (0x00388400)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW (0x00388440)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW (0x00388480)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___POR 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___POR 0x7F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___S               9
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___S               8
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___M 0x0000077F   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW (0x003884C0)
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___S               0
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___M 0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW     (0x00389000)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___POR 0x001237AA
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___POR 0x12
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___POR 0x37AA
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH    (0x00389004)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW  (0x00389008)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___M 0x0000002F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW (0x00389010)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW (0x00389018)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW (0x00389020)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW   (0x00389028)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW  (0x00389030)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___M 0x00000007
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___M 0x00000007   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW (0x00389120)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH (0x00389124)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW (0x00389128)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH (0x0038912C)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW (0x00389138)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW (0x00389140)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___M 0x0000000F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW (0x00389178)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW (0x00389180)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW (0x00389190)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___M 0x00000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW (0x00389220)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH (0x00389224)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW (0x00389228)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH (0x0038922C)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW (0x00389238)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW (0x00389240)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___M 0x0000000F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW (0x00389278)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW (0x00389280)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW (0x00389290)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___M 0x00000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW    (0x00389400)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___POR 0x0012C2E1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___POR 0x12
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___POR 0xC2E1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH   (0x00389404)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW (0x00389408)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___M 0x0000002F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW (0x00389410)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW (0x00389418)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW (0x00389420)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW  (0x00389428)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___M 0x80000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___S              31
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___M 0x80000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW (0x00389430)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___M 0x00000007
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___M 0x00000007   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW (0x00389520)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH (0x00389524)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW (0x00389528)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH (0x0038952C)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW (0x00389538)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW (0x00389540)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___M 0x0000000F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW (0x00389578)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW (0x00389580)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW (0x00389590)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___M 0x00000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW (0x00389620)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH (0x00389624)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW (0x00389628)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___S               6

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH (0x0038962C)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW (0x00389638)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW (0x00389640)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___S               3
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___S               2
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___S               1
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___M 0x0000000F   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW (0x00389678)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW (0x00389680)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___S               0

#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW (0x00389690)
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S               0
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___M 0x00000003   
#define   PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW (0x00389800)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___POR 0x000341AC
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x41AC
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH (0x00389804)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW (0x00389808)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW (0x00389810)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW (0x00389818)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW (0x00389820)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___POR 0x01400000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW (0x00389828)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH (0x0038982C)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___S               8

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW (0x00389840)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW (0x00389848)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW (0x00389850)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW (0x00389858)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW (0x00389860)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW (0x00389868)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW (0x00389870)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW (0x00389878)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW (0x00389880)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00389920)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___S              10
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00389928)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___S              10
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW (0x00389938)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW (0x00389968)
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___S               4
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___S               3
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___S               2
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___S               1
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___S               0
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW (0x0038A000)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___POR 0x00039006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH (0x0038A004)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW (0x0038A008)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW (0x0038A010)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW (0x0038A018)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW (0x0038A020)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___POR 0x01400000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW (0x0038A028)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH (0x0038A02C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___S               8

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW (0x0038A040)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW (0x0038A048)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW (0x0038A050)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW (0x0038A058)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW (0x0038A060)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW (0x0038A068)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW (0x0038A070)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW (0x0038A078)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW (0x0038A080)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A120)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A124)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A128)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A12C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW (0x0038A138)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW (0x0038A200)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___POR 0x00039006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH (0x0038A204)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW (0x0038A208)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW (0x0038A210)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW (0x0038A218)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW (0x0038A220)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___POR 0x01400000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW (0x0038A228)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH (0x0038A22C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___S               8

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW (0x0038A240)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW (0x0038A248)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW (0x0038A250)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW (0x0038A258)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW (0x0038A260)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW (0x0038A268)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW (0x0038A270)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW (0x0038A278)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW (0x0038A280)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A320)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A324)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A328)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A32C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW (0x0038A338)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW (0x0038A400)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___POR 0x00039006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH (0x0038A404)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW (0x0038A408)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW (0x0038A410)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW (0x0038A418)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW (0x0038A420)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___POR 0x01400000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW (0x0038A428)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH (0x0038A42C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___S               8

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW (0x0038A440)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW (0x0038A448)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW (0x0038A450)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW (0x0038A458)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW (0x0038A460)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW (0x0038A468)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW (0x0038A470)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW (0x0038A478)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW (0x0038A480)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A520)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A524)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A528)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A52C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW (0x0038A538)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW (0x0038A600)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___POR 0x00039006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH (0x0038A604)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW (0x0038A608)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW (0x0038A610)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW (0x0038A618)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW (0x0038A620)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___POR 0x01400000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW (0x0038A628)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH (0x0038A62C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___S               8

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW (0x0038A640)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW (0x0038A648)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW (0x0038A650)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW (0x0038A658)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW (0x0038A660)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW (0x0038A668)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW (0x0038A670)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW (0x0038A678)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW (0x0038A680)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A720)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A724)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A728)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A72C)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW (0x0038A738)
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW            (0x0038A800)
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW___RWC      QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW___POR   0x000CE93B
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___POR 0x0C
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___POR 0xE93B
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW___M     0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_STP_SWID_LOW___S                   0

#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH           (0x0038A804)
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___RWC     QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___POR  0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___M    0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___S                  0

#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW           (0x0038A808)
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___RWC     QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___POR  0x00000000
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___S               0
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___M    0x00000001   
#define   PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___S                  0

#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW           (0x0038A810)
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___RWC     QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___POR  0x00000000
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___POR 0x00
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___M 0x0000007F
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___S               0
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___M    0x0000007F   
#define   PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___S                  0

#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW   (0x0038A818)
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S               0
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF   
#define   PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___S               0

#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW            (0x0038A900)
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___RWC      QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___POR   0x0001E93B
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___S              16
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___M     0x00FFFFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___S                   0

#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH           (0x0038A904)
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___RWC     QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___POR  0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___M    0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___S                  0

#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW         (0x0038A908)
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___RWC   QCSR_REG_RW    
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___S               1
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___M  0x00000003   
#define   PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___S                0

#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW          (0x0038A910)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___RWC    QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___M   0x00000001   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___S                 0

#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW          (0x0038A918)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___RWC    QCSR_REG_WO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___M   0x00000001   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___S                 0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW         (0x0038A920)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___RWC   QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___S               4
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___M  0x0F3F7777   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___S                0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH        (0x0038A924)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___RWC  QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW         (0x0038A928)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___RWC   QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___M  0x0000FFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___S                0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH        (0x0038A92C)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___RWC  QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW         (0x0038A930)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___RWC   QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___M  0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___S                0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH        (0x0038A934)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___RWC  QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___S               0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW         (0x0038A938)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___RWC   QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___M  0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___S                0

#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH        (0x0038A93C)
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___RWC  QCSR_REG_RO    
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___S               0

#define PHYA_TXFD_ECO_CONTROL_L                   (0x00390000)
#define   PHYA_TXFD_ECO_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_ECO_CONTROL_L___POR          0x00000000
#define   PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___M  0xFFFFFFFF
#define   PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___S                0
#define   PHYA_TXFD_ECO_CONTROL_L___M            0xFFFFFFFF   
#define   PHYA_TXFD_ECO_CONTROL_L___S                          0

#define PHYA_TXFD_ECO_CONTROL_U                   (0x00390004)
#define   PHYA_TXFD_ECO_CONTROL_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_ECO_CONTROL_U___POR          0x00000000
#define   PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000
#define   PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___M   0xFFFFFFFF
#define   PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___S                 0
#define   PHYA_TXFD_ECO_CONTROL_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_ECO_CONTROL_U___S                          0

#define PHYA_TXFD_ECO_STATUS_L                    (0x00390008)
#define   PHYA_TXFD_ECO_STATUS_L___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_ECO_STATUS_L___POR           0x00000000
#define   PHYA_TXFD_ECO_STATUS_L__ECO_STAT___POR 0x00000000
#define   PHYA_TXFD_ECO_STATUS_L__ECO_STAT___M   0xFFFFFFFF
#define   PHYA_TXFD_ECO_STATUS_L__ECO_STAT___S                 0
#define   PHYA_TXFD_ECO_STATUS_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_ECO_STATUS_L___S                           0

#define PHYA_TXFD_CONFIG_CONFIG_L                 (0x00390010)
#define   PHYA_TXFD_CONFIG_CONFIG_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_CONFIG_CONFIG_L___POR        0x00000000
#define   PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___POR 0x0
#define   PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___M 0x00000001
#define   PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___S               0
#define   PHYA_TXFD_CONFIG_CONFIG_L___M          0x00000001   
#define   PHYA_TXFD_CONFIG_CONFIG_L___S                        0

#define PHYA_TXFD_EVENT_STATUS_L                  (0x00390018)
#define   PHYA_TXFD_EVENT_STATUS_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_EVENT_STATUS_L___POR         0x00000000
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___M 0x80000000
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___S              31
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___M 0x40000000
#define   PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___S              30
#define   PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___M 0x20000000
#define   PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___S              29
#define   PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___M 0x10000000
#define   PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___S              28
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___M 0x08000000
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___S              27
#define   PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___M 0x04000000
#define   PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___S              26
#define   PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___M 0x02000000
#define   PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___S              25
#define   PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___M 0x01000000
#define   PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___S              24
#define   PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___M 0x00800000
#define   PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___S              23
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___M 0x00400000
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___S              22
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___M 0x00200000
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___S              21
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___M 0x00100000
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___S              20
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___M 0x00080000
#define   PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___S              19
#define   PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___M 0x00040000
#define   PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___S              18
#define   PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___M 0x00020000
#define   PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___S              17
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___M 0x00010000
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___S              16
#define   PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___M 0x00008000
#define   PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___S              15
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___M 0x00004000
#define   PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___S              14
#define   PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___M 0x00002000
#define   PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___S              13
#define   PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___M 0x00001000
#define   PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___S              12
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___M 0x00000800
#define   PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___S              11
#define   PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___M 0x00000400
#define   PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___S              10
#define   PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___M 0x00000200
#define   PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___S               9
#define   PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___M 0x00000100
#define   PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___S               8
#define   PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___M 0x00000080
#define   PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___S               7
#define   PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___M 0x00000040
#define   PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___S               6
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___M 0x00000020
#define   PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___S               5
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___M 0x00000010
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___S               4
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___M 0x00000008
#define   PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___S               3
#define   PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___M 0x00000004
#define   PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___S               2
#define   PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_TXFD_EVENT_STATUS_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_EVENT_STATUS_L___S                         0

#define PHYA_TXFD_EVENT_STATUS_U                  (0x0039001C)
#define   PHYA_TXFD_EVENT_STATUS_U___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_EVENT_STATUS_U___POR         0x00000000
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___POR 0x0
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___M 0x00008000
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___S              15
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___M 0x00004000
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___S              14
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___M 0x00002000
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___S              13
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___M 0x00001000
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___S              12
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___M 0x00000800
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___S              11
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___M 0x00000400
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___S              10
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___M 0x00000200
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___S               9
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___M 0x00000100
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___S               8
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___M 0x00000080
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___S               7
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___M 0x00000040
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___S               6
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___M 0x00000020
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___S               5
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___M 0x00000010
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___S               4
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___M 0x00000008
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___S               3
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___M 0x00000004
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___S               2
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___M 0x00000002
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___S               1
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___M 0x00000001
#define   PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___S               0
#define   PHYA_TXFD_EVENT_STATUS_U___M           0x0000FFFF   
#define   PHYA_TXFD_EVENT_STATUS_U___S                         0

#define PHYA_TXFD_EVENT_MASK_L                    (0x00390020)
#define   PHYA_TXFD_EVENT_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_EVENT_MASK_L___POR           0xFFFFFFFF
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___M 0x80000000
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___S              31
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___M 0x40000000
#define   PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___S              30
#define   PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___M 0x20000000
#define   PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___S              29
#define   PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___M 0x10000000
#define   PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___S              28
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___M 0x08000000
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___S              27
#define   PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___M 0x04000000
#define   PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___S              26
#define   PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___M 0x02000000
#define   PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___S              25
#define   PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___M 0x01000000
#define   PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___S              24
#define   PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___M 0x00800000
#define   PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___S              23
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___M 0x00400000
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___S              22
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___M 0x00200000
#define   PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___S              21
#define   PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___M 0x00100000
#define   PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___S              20
#define   PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___M 0x00080000
#define   PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___S              19
#define   PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___M 0x00040000
#define   PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___S              18
#define   PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___M 0x00020000
#define   PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___S              17
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___M 0x00010000
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___S              16
#define   PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___M 0x00008000
#define   PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___S              15
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___M 0x00004000
#define   PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___S              14
#define   PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___M 0x00002000
#define   PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___S              13
#define   PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___M 0x00001000
#define   PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___S              12
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___M 0x00000800
#define   PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___S              11
#define   PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___M 0x00000400
#define   PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___S              10
#define   PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___M 0x00000200
#define   PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___S               9
#define   PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___M 0x00000100
#define   PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___S               8
#define   PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___M 0x00000080
#define   PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___S               7
#define   PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___M 0x00000040
#define   PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___S               6
#define   PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___M 0x00000020
#define   PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___S               5
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___M 0x00000010
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___S               4
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___M 0x00000008
#define   PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___S               3
#define   PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___M 0x00000004
#define   PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___S               2
#define   PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_TXFD_EVENT_MASK_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_EVENT_MASK_L___S                           0

#define PHYA_TXFD_EVENT_MASK_U                    (0x00390024)
#define   PHYA_TXFD_EVENT_MASK_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_EVENT_MASK_U___POR           0x0000FFFF
#define   PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___POR 0x1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___M 0x00008000
#define   PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___S              15
#define   PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___M 0x00004000
#define   PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___S              14
#define   PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___M 0x00002000
#define   PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___S              13
#define   PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___M 0x00001000
#define   PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___S              12
#define   PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___M 0x00000800
#define   PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___S              11
#define   PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___M 0x00000400
#define   PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___S              10
#define   PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___M 0x00000200
#define   PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___S               9
#define   PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___M 0x00000100
#define   PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___S               8
#define   PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___M 0x00000080
#define   PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___S               7
#define   PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___M 0x00000040
#define   PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___S               6
#define   PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___M 0x00000020
#define   PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___S               5
#define   PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___M 0x00000010
#define   PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___S               4
#define   PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___M 0x00000008
#define   PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___S               3
#define   PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___M 0x00000004
#define   PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___S               2
#define   PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___M 0x00000002
#define   PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___S               1
#define   PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___M 0x00000001
#define   PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___S               0
#define   PHYA_TXFD_EVENT_MASK_U___M             0x0000FFFF   
#define   PHYA_TXFD_EVENT_MASK_U___S                           0

#define PHYA_TXFD_EVENT_TLV_STATUS_L              (0x00390028)
#define   PHYA_TXFD_EVENT_TLV_STATUS_L___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_EVENT_TLV_STATUS_L___POR     0x00000000
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___M 0x00008000
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___S              15
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___M 0x00004000
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___S              14
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___M 0x00002000
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___S              13
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___M 0x00001000
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___S              12
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___M 0x00000800
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___S              11
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___M 0x00000400
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___S              10
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___M 0x00000200
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___S               9
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___M 0x00000100
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___S               8
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___M 0x00000080
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___S               7
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___M 0x00000040
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___S               6
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___M 0x00000020
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___S               5
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___M 0x00000010
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___S               4
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___M 0x00000008
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___S               3
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___M 0x00000004
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___S               2
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___M 0x00000002
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___S               1
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___M 0x00000001
#define   PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___S               0
#define   PHYA_TXFD_EVENT_TLV_STATUS_L___M       0x0000FFFF   
#define   PHYA_TXFD_EVENT_TLV_STATUS_L___S                     0

#define PHYA_TXFD_EVENT_TLV_MASK_L                (0x00390030)
#define   PHYA_TXFD_EVENT_TLV_MASK_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_EVENT_TLV_MASK_L___POR       0x00000000
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___POR 0x0
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___M 0x00008000
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___S              15
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___M 0x00004000
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___S              14
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___M 0x00002000
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___S              13
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___M 0x00001000
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___S              12
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___M 0x00000800
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___S              11
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___M 0x00000400
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___S              10
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___M 0x00000200
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___S               9
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___M 0x00000100
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___S               8
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___M 0x00000080
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___S               7
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___M 0x00000040
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___S               6
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___M 0x00000020
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___S               5
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___M 0x00000010
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___S               4
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___M 0x00000008
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___S               3
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___M 0x00000004
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___S               2
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___M 0x00000002
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___S               1
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___M 0x00000001
#define   PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___S               0
#define   PHYA_TXFD_EVENT_TLV_MASK_L___M         0x0000FFFF   
#define   PHYA_TXFD_EVENT_TLV_MASK_L___S                       0

#define PHYA_TXFD_ERROR_CODE_L                    (0x00390038)
#define   PHYA_TXFD_ERROR_CODE_L___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_CODE_L___POR           0x00000000
#define   PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___POR 0x00000000
#define   PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_TXFD_ERROR_CODE_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_CODE_L___S                           0

#define PHYA_TXFD_ERROR_STATUS_L                  (0x00390040)
#define   PHYA_TXFD_ERROR_STATUS_L___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_STATUS_L___POR         0x00000000
#define   PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___M 0x80000000
#define   PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___S              31
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___M 0x40000000
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___S              30
#define   PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___M 0x20000000
#define   PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___S              29
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___M 0x10000000
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___S              28
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___M 0x08000000
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___S              27
#define   PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___M 0x04000000
#define   PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___S              26
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___M 0x02000000
#define   PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___S              25
#define   PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___M 0x01000000
#define   PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___S              24
#define   PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___M 0x00800000
#define   PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___S              23
#define   PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___M 0x00400000
#define   PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___S              22
#define   PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___M 0x00200000
#define   PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___S              21
#define   PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___M 0x00100000
#define   PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___S              20
#define   PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___M 0x00080000
#define   PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___S              19
#define   PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___M 0x00040000
#define   PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___S              18
#define   PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___M 0x00020000
#define   PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___S              17
#define   PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___M 0x00010000
#define   PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___S              16
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___M 0x00008000
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___S              15
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___M 0x00004000
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___S              14
#define   PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___M 0x00002000
#define   PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___S              13
#define   PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___M 0x00001000
#define   PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___S              12
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___M 0x00000800
#define   PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___S              11
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___M 0x00000400
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___S              10
#define   PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___M 0x00000200
#define   PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___S               9
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___M 0x00000100
#define   PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___S               8
#define   PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___M 0x00000080
#define   PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___S               7
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___M 0x00000040
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___S               6
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___M 0x00000020
#define   PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___S               5
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___M 0x00000010
#define   PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___S               4
#define   PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___M 0x00000008
#define   PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___S               3
#define   PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___M 0x00000004
#define   PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___S               2
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___M 0x00000002
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___S               1
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___M 0x00000001
#define   PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___S               0
#define   PHYA_TXFD_ERROR_STATUS_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_STATUS_L___S                         0

#define PHYA_TXFD_ERROR_STATUS_U                  (0x00390044)
#define   PHYA_TXFD_ERROR_STATUS_U___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_STATUS_U___POR         0x00000000
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___M 0x00000004
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___S               2
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___M 0x00000002
#define   PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___S               1
#define   PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___M 0x00000001
#define   PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___S               0
#define   PHYA_TXFD_ERROR_STATUS_U___M           0x00000007   
#define   PHYA_TXFD_ERROR_STATUS_U___S                         0

#define PHYA_TXFD_ERROR_MASK_L                    (0x00390048)
#define   PHYA_TXFD_ERROR_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_MASK_L___POR           0xFFFFFFFF
#define   PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___M 0x80000000
#define   PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___S              31
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___M 0x40000000
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___S              30
#define   PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___M 0x20000000
#define   PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___S              29
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___M 0x10000000
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___S              28
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___M 0x08000000
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___S              27
#define   PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___M 0x04000000
#define   PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___S              26
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___M 0x02000000
#define   PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___S              25
#define   PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___M 0x01000000
#define   PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___S              24
#define   PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___M 0x00800000
#define   PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___S              23
#define   PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___M 0x00400000
#define   PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___S              22
#define   PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___M 0x00200000
#define   PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___S              21
#define   PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___M 0x00100000
#define   PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___S              20
#define   PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___M 0x00080000
#define   PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___S              19
#define   PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___M 0x00040000
#define   PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___S              18
#define   PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___M 0x00020000
#define   PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___S              17
#define   PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___M 0x00010000
#define   PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___S              16
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___M 0x00008000
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___S              15
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___M 0x00004000
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___S              14
#define   PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___M 0x00002000
#define   PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___S              13
#define   PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___M 0x00001000
#define   PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___S              12
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___M 0x00000800
#define   PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___S              11
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___M 0x00000400
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___S              10
#define   PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___M 0x00000200
#define   PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___S               9
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___M 0x00000100
#define   PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___S               8
#define   PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___M 0x00000080
#define   PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___S               7
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___M 0x00000040
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___S               6
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___M 0x00000020
#define   PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___S               5
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___M 0x00000010
#define   PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___S               4
#define   PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___M 0x00000008
#define   PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___S               3
#define   PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___M 0x00000004
#define   PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___S               2
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___M 0x00000002
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___S               1
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___M 0x00000001
#define   PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___S               0
#define   PHYA_TXFD_ERROR_MASK_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_MASK_L___S                           0

#define PHYA_TXFD_ERROR_MASK_U                    (0x0039004C)
#define   PHYA_TXFD_ERROR_MASK_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_MASK_U___POR           0x00000007
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___M 0x00000004
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___S               2
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___M 0x00000002
#define   PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___S               1
#define   PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___M 0x00000001
#define   PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___S               0
#define   PHYA_TXFD_ERROR_MASK_U___M             0x00000007   
#define   PHYA_TXFD_ERROR_MASK_U___S                           0

#define PHYA_TXFD_PHYDBG_MPI_0_L                  (0x00390050)
#define   PHYA_TXFD_PHYDBG_MPI_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_0_L___POR         0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___POR 0x0
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___POR 0x00
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___POR 0x0
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___M 0x00030000
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___S              16
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___M 0x0000FF00
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___S               8
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___M 0x00000001
#define   PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___S               0
#define   PHYA_TXFD_PHYDBG_MPI_0_L___M           0x0003FF01   
#define   PHYA_TXFD_PHYDBG_MPI_0_L___S                         0

#define PHYA_TXFD_PHYDBG_MPI_1_L                  (0x00390058)
#define   PHYA_TXFD_PHYDBG_MPI_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_1_L___POR         0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___S               0
#define   PHYA_TXFD_PHYDBG_MPI_1_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_1_L___S                         0

#define PHYA_TXFD_PHYDBG_MPI_1_U                  (0x0039005C)
#define   PHYA_TXFD_PHYDBG_MPI_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_1_U___POR         0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___S               0
#define   PHYA_TXFD_PHYDBG_MPI_1_U___M           0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_1_U___S                         0

#define PHYA_TXFD_PHYDBG_MPI_20_L                 (0x00390060)
#define   PHYA_TXFD_PHYDBG_MPI_20_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_20_L___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___S               0
#define   PHYA_TXFD_PHYDBG_MPI_20_L___M          0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_20_L___S                        0

#define PHYA_TXFD_PHYDBG_MPI_20_U                 (0x00390064)
#define   PHYA_TXFD_PHYDBG_MPI_20_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_20_U___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___S               0
#define   PHYA_TXFD_PHYDBG_MPI_20_U___M          0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_20_U___S                        0

#define PHYA_TXFD_PHYDBG_MPI_21_L                 (0x00390068)
#define   PHYA_TXFD_PHYDBG_MPI_21_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_21_L___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___S               0
#define   PHYA_TXFD_PHYDBG_MPI_21_L___M          0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_21_L___S                        0

#define PHYA_TXFD_PHYDBG_MPI_21_U                 (0x0039006C)
#define   PHYA_TXFD_PHYDBG_MPI_21_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_MPI_21_U___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___S               0
#define   PHYA_TXFD_PHYDBG_MPI_21_U___M          0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_MPI_21_U___S                        0

#define PHYA_TXFD_PHYDBG_TXFD_0_L                 (0x00390070)
#define   PHYA_TXFD_PHYDBG_TXFD_0_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_0_L___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___POR 0x00
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___POR 0x00
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___POR 0x0
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___POR 0x0
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___M 0x3F000000
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___S              24
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___M 0x00FF0000
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___S              16
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___M 0x00000100
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___S               8
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___M 0x00000001
#define   PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_0_L___M          0x3FFF0101   
#define   PHYA_TXFD_PHYDBG_TXFD_0_L___S                        0

#define PHYA_TXFD_PHYDBG_TXFD_0_U                 (0x00390074)
#define   PHYA_TXFD_PHYDBG_TXFD_0_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_0_U___POR        0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___POR 0x0
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___POR 0x00
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___POR 0x00
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___POR 0x0
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___M 0x0F000000
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___S              24
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___M 0x00FF0000
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___S              16
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___M 0x00003F00
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___S               8
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___M 0x0000000F
#define   PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_0_U___M          0x0FFF3F0F   
#define   PHYA_TXFD_PHYDBG_TXFD_0_U___S                        0

#define PHYA_TXFD_PHYDBG_TXFD_10_L                (0x00390078)
#define   PHYA_TXFD_PHYDBG_TXFD_10_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_10_L___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_10_L___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_10_L___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_10_U                (0x0039007C)
#define   PHYA_TXFD_PHYDBG_TXFD_10_U___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_10_U___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_10_U___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_10_U___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_11_L                (0x00390080)
#define   PHYA_TXFD_PHYDBG_TXFD_11_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_11_L___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_11_L___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_11_L___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_11_U                (0x00390084)
#define   PHYA_TXFD_PHYDBG_TXFD_11_U___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_11_U___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_11_U___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_11_U___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_12_L                (0x00390088)
#define   PHYA_TXFD_PHYDBG_TXFD_12_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_12_L___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_12_L___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_12_L___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_12_U                (0x0039008C)
#define   PHYA_TXFD_PHYDBG_TXFD_12_U___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_12_U___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_12_U___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_12_U___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_13_L                (0x00390090)
#define   PHYA_TXFD_PHYDBG_TXFD_13_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_13_L___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_13_L___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_13_L___S                       0

#define PHYA_TXFD_PHYDBG_TXFD_13_U                (0x00390094)
#define   PHYA_TXFD_PHYDBG_TXFD_13_U___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_PHYDBG_TXFD_13_U___POR       0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___POR 0x00000000
#define   PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___M 0xFFFFFFFF
#define   PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___S               0
#define   PHYA_TXFD_PHYDBG_TXFD_13_U___M         0xFFFFFFFF   
#define   PHYA_TXFD_PHYDBG_TXFD_13_U___S                       0

#define PHYA_TXFD_FTPG_CTRL_0_L                   (0x00390098)
#define   PHYA_TXFD_FTPG_CTRL_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_0_L___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___M 0x00010000
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___S              16
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___M 0x00000100
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___S               8
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___M 0x00000001
#define   PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___S               0
#define   PHYA_TXFD_FTPG_CTRL_0_L___M            0x00010101   
#define   PHYA_TXFD_FTPG_CTRL_0_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_0_U                   (0x0039009C)
#define   PHYA_TXFD_FTPG_CTRL_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_0_U___POR          0x00000001
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___POR 0x0001
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___M 0x0F000000
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___S              24
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___M 0x00010000
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___S              16
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___M 0x0000FFFF
#define   PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___S               0
#define   PHYA_TXFD_FTPG_CTRL_0_U___M            0x0F01FFFF   
#define   PHYA_TXFD_FTPG_CTRL_0_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_1_L                   (0x003900A0)
#define   PHYA_TXFD_FTPG_CTRL_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_1_L___POR          0x64010000
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___POR 0x64
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___POR 0x01
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___POR 0x0
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___M 0xFF000000
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___S              24
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___M 0x007F0000
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___S              16
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___M 0x00000100
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___S               8
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___M 0x00000003
#define   PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___S               0
#define   PHYA_TXFD_FTPG_CTRL_1_L___M            0xFF7F0103   
#define   PHYA_TXFD_FTPG_CTRL_1_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_1_U                   (0x003900A4)
#define   PHYA_TXFD_FTPG_CTRL_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_1_U___POR          0x0064000A
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___POR 0x0064
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___POR 0x0A
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___M 0xFFFF0000
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___S              16
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___M 0x0000003F
#define   PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___S               0
#define   PHYA_TXFD_FTPG_CTRL_1_U___M            0xFFFF003F   
#define   PHYA_TXFD_FTPG_CTRL_1_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_2_L                   (0x003900A8)
#define   PHYA_TXFD_FTPG_CTRL_2_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_2_L___POR          0x00000001
#define   PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___POR 0x1
#define   PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___M 0x00000001
#define   PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___S               0
#define   PHYA_TXFD_FTPG_CTRL_2_L___M            0x00000001   
#define   PHYA_TXFD_FTPG_CTRL_2_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_2_U                   (0x003900AC)
#define   PHYA_TXFD_FTPG_CTRL_2_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_2_U___POR          0x00000FA0
#define   PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___POR 0x00000FA0
#define   PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___S               0
#define   PHYA_TXFD_FTPG_CTRL_2_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_2_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_3_L                   (0x003900B0)
#define   PHYA_TXFD_FTPG_CTRL_3_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_3_L___POR          0x00000280
#define   PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___POR 0x0280
#define   PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___M 0x0000FFFF
#define   PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___S               0
#define   PHYA_TXFD_FTPG_CTRL_3_L___M            0x0000FFFF   
#define   PHYA_TXFD_FTPG_CTRL_3_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_3_U                   (0x003900B4)
#define   PHYA_TXFD_FTPG_CTRL_3_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_3_U___POR          0x4E790001
#define   PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___POR 0x4E790001
#define   PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___S               0
#define   PHYA_TXFD_FTPG_CTRL_3_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_3_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_4_L                   (0x003900B8)
#define   PHYA_TXFD_FTPG_CTRL_4_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_4_L___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___POR 0x00000000
#define   PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___S               0
#define   PHYA_TXFD_FTPG_CTRL_4_L___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_4_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_4_U                   (0x003900BC)
#define   PHYA_TXFD_FTPG_CTRL_4_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_4_U___POR          0xDEADBEEF
#define   PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___POR 0xDEADBEEF
#define   PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___S               0
#define   PHYA_TXFD_FTPG_CTRL_4_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_4_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_5_L                   (0x003900C0)
#define   PHYA_TXFD_FTPG_CTRL_5_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_5_L___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___POR 0x00000000
#define   PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___S               0
#define   PHYA_TXFD_FTPG_CTRL_5_L___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_5_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_5_U                   (0x003900C4)
#define   PHYA_TXFD_FTPG_CTRL_5_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_5_U___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___POR 0x00000000
#define   PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___S               0
#define   PHYA_TXFD_FTPG_CTRL_5_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_5_U___S                          0

#define PHYA_TXFD_FTPG_CTRL_6_L                   (0x003900C8)
#define   PHYA_TXFD_FTPG_CTRL_6_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_6_L___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___POR 0x00000000
#define   PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___S               0
#define   PHYA_TXFD_FTPG_CTRL_6_L___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_6_L___S                          0

#define PHYA_TXFD_FTPG_CTRL_6_U                   (0x003900CC)
#define   PHYA_TXFD_FTPG_CTRL_6_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_CTRL_6_U___POR          0x00000000
#define   PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___POR 0x00000000
#define   PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___M 0xFFFFFFFF
#define   PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___S               0
#define   PHYA_TXFD_FTPG_CTRL_6_U___M            0xFFFFFFFF   
#define   PHYA_TXFD_FTPG_CTRL_6_U___S                          0

#define PHYA_TXFD_FTPG_STATUS_L                   (0x003900D0)
#define   PHYA_TXFD_FTPG_STATUS_L___RWC             QCSR_REG_RO    
#define   PHYA_TXFD_FTPG_STATUS_L___POR          0x00000000
#define   PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___POR 0x0000
#define   PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___M 0x0000FFFF
#define   PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___S               0
#define   PHYA_TXFD_FTPG_STATUS_L___M            0x0000FFFF   
#define   PHYA_TXFD_FTPG_STATUS_L___S                          0

#define PHYA_TXFD_FTPG_USER_CFG_L                 (0x003900D8)
#define   PHYA_TXFD_FTPG_USER_CFG_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_USER_CFG_L___POR        0x00000000
#define   PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___POR 0x0000
#define   PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___M 0x00001FFF
#define   PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___S               0
#define   PHYA_TXFD_FTPG_USER_CFG_L___M          0x00001FFF   
#define   PHYA_TXFD_FTPG_USER_CFG_L___S                        0

#define PHYA_TXFD_FTPG_USER_CFG_U                 (0x003900DC)
#define   PHYA_TXFD_FTPG_USER_CFG_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_FTPG_USER_CFG_U___POR        0x00000000
#define   PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___POR 0x000000
#define   PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___M 0x007FFFFF
#define   PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___S               0
#define   PHYA_TXFD_FTPG_USER_CFG_U___M          0x007FFFFF   
#define   PHYA_TXFD_FTPG_USER_CFG_U___S                        0

#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n(n) (0x003902D8+0x8*(n))
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_nMIN 0    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_nMAX 0    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_ELEM 1    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___POR 0x00000000
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___POR 0x00000000
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___S               0
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___M  0xFFFFFFFF   
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___S                0
#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0         (0x003902D8)
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0__PEF_COEFF_BW_OSR_HC_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0__PEF_COEFF_BW_OSR_HC_0___S               0

#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n(n) (0x003902DC+0x8*(n))
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_nMIN 0    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_nMAX 0    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_ELEM 1    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___POR 0x00000000
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___POR 0x00000000
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___S               0
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___M  0xFFFFFFFF   
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___S                0
#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0         (0x003902DC)
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0__PEF_COEFF_BW_OSR_HC_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0__PEF_COEFF_BW_OSR_HC_1___S               0

#define PHYA_TXFD_TXB_CFG_0_L                     (0x003915D8)
#define   PHYA_TXFD_TXB_CFG_0_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_0_L___POR            0x00000000
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___POR 0x0
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___POR 0x0
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___POR 0x0
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___M 0x00010000
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___S              16
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___M 0x00000300
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___S               8
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___M 0x00000001
#define   PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___S               0
#define   PHYA_TXFD_TXB_CFG_0_L___M              0x00010301   
#define   PHYA_TXFD_TXB_CFG_0_L___S                            0

#define PHYA_TXFD_TXB_CFG_10_L                    (0x003915E0)
#define   PHYA_TXFD_TXB_CFG_10_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_10_L___POR           0x00000000
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___S              24
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___S              16
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___S               8
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___S               0
#define   PHYA_TXFD_TXB_CFG_10_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_10_L___S                           0

#define PHYA_TXFD_TXB_CFG_10_U                    (0x003915E4)
#define   PHYA_TXFD_TXB_CFG_10_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_10_U___POR           0x00000000
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___POR 0x00
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___S              24
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___S              16
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___S               8
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___S               0
#define   PHYA_TXFD_TXB_CFG_10_U___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_10_U___S                           0

#define PHYA_TXFD_TXB_CFG_11_L                    (0x003915E8)
#define   PHYA_TXFD_TXB_CFG_11_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_11_L___POR           0xEEB74ADC
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___POR 0xEE
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___POR 0xB7
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___POR 0x4A
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___POR 0xDC
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___S              24
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___S              16
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___S               8
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___S               0
#define   PHYA_TXFD_TXB_CFG_11_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_11_L___S                           0

#define PHYA_TXFD_TXB_CFG_11_U                    (0x003915EC)
#define   PHYA_TXFD_TXB_CFG_11_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_11_U___POR           0x00000000
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___POR 0x00
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___POR 0x00
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___POR 0x00
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___POR 0x00
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___S              24
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___S              16
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___S               8
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___S               0
#define   PHYA_TXFD_TXB_CFG_11_U___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_11_U___S                           0

#define PHYA_TXFD_TXB_CFG_12_L                    (0x003915F0)
#define   PHYA_TXFD_TXB_CFG_12_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_12_L___POR           0x00000000
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___S              24
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___S              16
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___S               8
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___S               0
#define   PHYA_TXFD_TXB_CFG_12_L___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_12_L___S                           0

#define PHYA_TXFD_TXB_CFG_12_U                    (0x003915F4)
#define   PHYA_TXFD_TXB_CFG_12_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_12_U___POR           0x00000000
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___POR 0x00
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___M 0xFF000000
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___S              24
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___M 0x00FF0000
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___S              16
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___S               8
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___M 0x000000FF
#define   PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___S               0
#define   PHYA_TXFD_TXB_CFG_12_U___M             0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_12_U___S                           0

#define PHYA_TXFD_TXB_CFG_2_L                     (0x003915F8)
#define   PHYA_TXFD_TXB_CFG_2_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_2_L___POR            0x00015303
#define   PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___POR 0x0
#define   PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___POR 0x1
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___POR 0x53
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___POR 0x3
#define   PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___M 0x01000000
#define   PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___S              24
#define   PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___M 0x00010000
#define   PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___S              16
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___M 0x0000FF00
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___S               8
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___M 0x0000000F
#define   PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___S               0
#define   PHYA_TXFD_TXB_CFG_2_L___M              0x0101FF0F   
#define   PHYA_TXFD_TXB_CFG_2_L___S                            0

#define PHYA_TXFD_TXB_CFG_2_U                     (0x003915FC)
#define   PHYA_TXFD_TXB_CFG_2_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_2_U___POR            0x00000000
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___POR 0x0
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___POR 0x0
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___M 0x00000100
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___S               8
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___M 0x00000001
#define   PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___S               0
#define   PHYA_TXFD_TXB_CFG_2_U___M              0x00000101   
#define   PHYA_TXFD_TXB_CFG_2_U___S                            0

#define PHYA_TXFD_TXB_CFG_3_L                     (0x00391600)
#define   PHYA_TXFD_TXB_CFG_3_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_3_L___POR            0x00000064
#define   PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___POR 0x00000064
#define   PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___M 0xFFFFFFFF
#define   PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___S               0
#define   PHYA_TXFD_TXB_CFG_3_L___M              0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_3_L___S                            0

#define PHYA_TXFD_TXB_CFG_3_U                     (0x00391604)
#define   PHYA_TXFD_TXB_CFG_3_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_3_U___POR            0x000000C8
#define   PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___POR 0x000000C8
#define   PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___M 0xFFFFFFFF
#define   PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___S               0
#define   PHYA_TXFD_TXB_CFG_3_U___M              0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_3_U___S                            0

#define PHYA_TXFD_TXB_CFG_4_L                     (0x00391608)
#define   PHYA_TXFD_TXB_CFG_4_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_TXB_CFG_4_L___POR            0x00000096
#define   PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___POR 0x00000096
#define   PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___M 0xFFFFFFFF
#define   PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___S               0
#define   PHYA_TXFD_TXB_CFG_4_L___M              0xFFFFFFFF   
#define   PHYA_TXFD_TXB_CFG_4_L___S                            0

#define PHYA_TXFD_WUR_CFG_0_L                     (0x00391610)
#define   PHYA_TXFD_WUR_CFG_0_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_0_L___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___POR 0x00000000
#define   PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___M  0xFFFFFFFF
#define   PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___S                0
#define   PHYA_TXFD_WUR_CFG_0_L___M              0xFFFFFFFF   
#define   PHYA_TXFD_WUR_CFG_0_L___S                            0

#define PHYA_TXFD_WUR_CFG_0_U                     (0x00391614)
#define   PHYA_TXFD_WUR_CFG_0_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_0_U___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___POR 0x00000000
#define   PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___M  0xFFFFFFFF
#define   PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___S                0
#define   PHYA_TXFD_WUR_CFG_0_U___M              0xFFFFFFFF   
#define   PHYA_TXFD_WUR_CFG_0_U___S                            0

#define PHYA_TXFD_WUR_CFG_1_L                     (0x00391618)
#define   PHYA_TXFD_WUR_CFG_1_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_1_L___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___POR 0x00000000
#define   PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___M 0xFFFFFFFF
#define   PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___S               0
#define   PHYA_TXFD_WUR_CFG_1_L___M              0xFFFFFFFF   
#define   PHYA_TXFD_WUR_CFG_1_L___S                            0

#define PHYA_TXFD_WUR_CFG_20_L                    (0x00391620)
#define   PHYA_TXFD_WUR_CFG_20_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_20_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___S              16
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___S               0
#define   PHYA_TXFD_WUR_CFG_20_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_20_L___S                           0

#define PHYA_TXFD_WUR_CFG_20_U                    (0x00391624)
#define   PHYA_TXFD_WUR_CFG_20_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_20_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___S              16
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___S               0
#define   PHYA_TXFD_WUR_CFG_20_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_20_U___S                           0

#define PHYA_TXFD_WUR_CFG_21_L                    (0x00391628)
#define   PHYA_TXFD_WUR_CFG_21_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_21_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___S              16
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___S               0
#define   PHYA_TXFD_WUR_CFG_21_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_21_L___S                           0

#define PHYA_TXFD_WUR_CFG_21_U                    (0x0039162C)
#define   PHYA_TXFD_WUR_CFG_21_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_21_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___S              16
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___S               0
#define   PHYA_TXFD_WUR_CFG_21_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_21_U___S                           0

#define PHYA_TXFD_WUR_CFG_22_L                    (0x00391630)
#define   PHYA_TXFD_WUR_CFG_22_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_22_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___S              16
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___S               0
#define   PHYA_TXFD_WUR_CFG_22_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_22_L___S                           0

#define PHYA_TXFD_WUR_CFG_22_U                    (0x00391634)
#define   PHYA_TXFD_WUR_CFG_22_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_22_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___S              16
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___S               0
#define   PHYA_TXFD_WUR_CFG_22_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_22_U___S                           0

#define PHYA_TXFD_WUR_CFG_23_L                    (0x00391638)
#define   PHYA_TXFD_WUR_CFG_23_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_23_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___S              16
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___S               0
#define   PHYA_TXFD_WUR_CFG_23_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_23_L___S                           0

#define PHYA_TXFD_WUR_CFG_23_U                    (0x0039163C)
#define   PHYA_TXFD_WUR_CFG_23_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_23_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___S              16
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___S               0
#define   PHYA_TXFD_WUR_CFG_23_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_23_U___S                           0

#define PHYA_TXFD_WUR_CFG_30_L                    (0x00391640)
#define   PHYA_TXFD_WUR_CFG_30_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_30_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___S              16
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___S               0
#define   PHYA_TXFD_WUR_CFG_30_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_30_L___S                           0

#define PHYA_TXFD_WUR_CFG_30_U                    (0x00391644)
#define   PHYA_TXFD_WUR_CFG_30_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_30_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___S              16
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___S               0
#define   PHYA_TXFD_WUR_CFG_30_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_30_U___S                           0

#define PHYA_TXFD_WUR_CFG_31_L                    (0x00391648)
#define   PHYA_TXFD_WUR_CFG_31_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_31_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___S              16
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___S               0
#define   PHYA_TXFD_WUR_CFG_31_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_31_L___S                           0

#define PHYA_TXFD_WUR_CFG_31_U                    (0x0039164C)
#define   PHYA_TXFD_WUR_CFG_31_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_31_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___S              16
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___S               0
#define   PHYA_TXFD_WUR_CFG_31_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_31_U___S                           0

#define PHYA_TXFD_WUR_CFG_32_L                    (0x00391650)
#define   PHYA_TXFD_WUR_CFG_32_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_32_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___S              16
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___S               0
#define   PHYA_TXFD_WUR_CFG_32_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_32_L___S                           0

#define PHYA_TXFD_WUR_CFG_32_U                    (0x00391654)
#define   PHYA_TXFD_WUR_CFG_32_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_32_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___S              16
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___S               0
#define   PHYA_TXFD_WUR_CFG_32_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_32_U___S                           0

#define PHYA_TXFD_WUR_CFG_33_L                    (0x00391658)
#define   PHYA_TXFD_WUR_CFG_33_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_33_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___S              16
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___S               0
#define   PHYA_TXFD_WUR_CFG_33_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_33_L___S                           0

#define PHYA_TXFD_WUR_CFG_33_U                    (0x0039165C)
#define   PHYA_TXFD_WUR_CFG_33_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_33_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___S              16
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___S               0
#define   PHYA_TXFD_WUR_CFG_33_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_33_U___S                           0

#define PHYA_TXFD_WUR_CFG_40_L                    (0x00391660)
#define   PHYA_TXFD_WUR_CFG_40_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_40_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___S              16
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___S               0
#define   PHYA_TXFD_WUR_CFG_40_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_40_L___S                           0

#define PHYA_TXFD_WUR_CFG_40_U                    (0x00391664)
#define   PHYA_TXFD_WUR_CFG_40_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_40_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___S              16
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___S               0
#define   PHYA_TXFD_WUR_CFG_40_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_40_U___S                           0

#define PHYA_TXFD_WUR_CFG_41_L                    (0x00391668)
#define   PHYA_TXFD_WUR_CFG_41_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_41_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___S              16
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___S               0
#define   PHYA_TXFD_WUR_CFG_41_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_41_L___S                           0

#define PHYA_TXFD_WUR_CFG_41_U                    (0x0039166C)
#define   PHYA_TXFD_WUR_CFG_41_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_41_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___S              16
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___S               0
#define   PHYA_TXFD_WUR_CFG_41_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_41_U___S                           0

#define PHYA_TXFD_WUR_CFG_42_L                    (0x00391670)
#define   PHYA_TXFD_WUR_CFG_42_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_42_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___S              16
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___S               0
#define   PHYA_TXFD_WUR_CFG_42_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_42_L___S                           0

#define PHYA_TXFD_WUR_CFG_42_U                    (0x00391674)
#define   PHYA_TXFD_WUR_CFG_42_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_42_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___S              16
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___S               0
#define   PHYA_TXFD_WUR_CFG_42_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_42_U___S                           0

#define PHYA_TXFD_WUR_CFG_43_L                    (0x00391678)
#define   PHYA_TXFD_WUR_CFG_43_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_43_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___S              16
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___S               0
#define   PHYA_TXFD_WUR_CFG_43_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_43_L___S                           0

#define PHYA_TXFD_WUR_CFG_43_U                    (0x0039167C)
#define   PHYA_TXFD_WUR_CFG_43_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_43_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___S              16
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___S               0
#define   PHYA_TXFD_WUR_CFG_43_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_43_U___S                           0

#define PHYA_TXFD_WUR_CFG_50_L                    (0x00391680)
#define   PHYA_TXFD_WUR_CFG_50_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_50_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___S              16
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___S               0
#define   PHYA_TXFD_WUR_CFG_50_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_50_L___S                           0

#define PHYA_TXFD_WUR_CFG_50_U                    (0x00391684)
#define   PHYA_TXFD_WUR_CFG_50_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_50_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___S              16
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___S               0
#define   PHYA_TXFD_WUR_CFG_50_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_50_U___S                           0

#define PHYA_TXFD_WUR_CFG_51_L                    (0x00391688)
#define   PHYA_TXFD_WUR_CFG_51_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_51_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___S              16
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___S               0
#define   PHYA_TXFD_WUR_CFG_51_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_51_L___S                           0

#define PHYA_TXFD_WUR_CFG_51_U                    (0x0039168C)
#define   PHYA_TXFD_WUR_CFG_51_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_51_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___S              16
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___S               0
#define   PHYA_TXFD_WUR_CFG_51_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_51_U___S                           0

#define PHYA_TXFD_WUR_CFG_52_L                    (0x00391690)
#define   PHYA_TXFD_WUR_CFG_52_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_52_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___S              16
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___S               0
#define   PHYA_TXFD_WUR_CFG_52_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_52_L___S                           0

#define PHYA_TXFD_WUR_CFG_52_U                    (0x00391694)
#define   PHYA_TXFD_WUR_CFG_52_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_52_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___S              16
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___S               0
#define   PHYA_TXFD_WUR_CFG_52_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_52_U___S                           0

#define PHYA_TXFD_WUR_CFG_53_L                    (0x00391698)
#define   PHYA_TXFD_WUR_CFG_53_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_53_L___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___S              16
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___S               0
#define   PHYA_TXFD_WUR_CFG_53_L___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_53_L___S                           0

#define PHYA_TXFD_WUR_CFG_53_U                    (0x0039169C)
#define   PHYA_TXFD_WUR_CFG_53_U___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_53_U___POR           0x00000000
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___POR 0x0000
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___M 0x3FFF0000
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___S              16
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___M 0x00003FFF
#define   PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___S               0
#define   PHYA_TXFD_WUR_CFG_53_U___M             0x3FFF3FFF   
#define   PHYA_TXFD_WUR_CFG_53_U___S                           0

#define PHYA_TXFD_WUR_CFG_6_L                     (0x003916A0)
#define   PHYA_TXFD_WUR_CFG_6_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_6_L___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___POR 0x0
#define   PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___M 0x00000001
#define   PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___S               0
#define   PHYA_TXFD_WUR_CFG_6_L___M              0x00000001   
#define   PHYA_TXFD_WUR_CFG_6_L___S                            0

#define PHYA_TXFD_WUR_CFG_7_L                     (0x003916A8)
#define   PHYA_TXFD_WUR_CFG_7_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_7_L___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___POR 0x00000000
#define   PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___M  0xFFFFFFFF
#define   PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___S                0
#define   PHYA_TXFD_WUR_CFG_7_L___M              0xFFFFFFFF   
#define   PHYA_TXFD_WUR_CFG_7_L___S                            0

#define PHYA_TXFD_WUR_CFG_7_U                     (0x003916AC)
#define   PHYA_TXFD_WUR_CFG_7_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_WUR_CFG_7_U___POR            0x00000000
#define   PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___POR 0x00000000
#define   PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___M  0xFFFFFFFF
#define   PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___S                0
#define   PHYA_TXFD_WUR_CFG_7_U___M              0xFFFFFFFF   
#define   PHYA_TXFD_WUR_CFG_7_U___S                            0

#define PHYA_TXFD_CFG_0_L                         (0x003916B0)
#define   PHYA_TXFD_CFG_0_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_0_L___POR                0x00000000
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___POR 0x0
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___POR 0x0
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___POR 0x0
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___POR   0x0
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___M 0x01000000
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___S              24
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___M 0x00010000
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___S              16
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___M 0x00000100
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___S               8
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___M     0x00000001
#define   PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___S                   0
#define   PHYA_TXFD_CFG_0_L___M                  0x01010101   
#define   PHYA_TXFD_CFG_0_L___S                                0

#define PHYA_TXFD_CFG_0_U                         (0x003916B4)
#define   PHYA_TXFD_CFG_0_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_0_U___POR                0x00000100
#define   PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___POR   0x0
#define   PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___POR 0x0
#define   PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___POR 0x1
#define   PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___POR 0x0
#define   PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___M     0x01000000
#define   PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___S                  24
#define   PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___M   0x00010000
#define   PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___S                16
#define   PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___M  0x00000100
#define   PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___S                8
#define   PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___M 0x00000001
#define   PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___S               0
#define   PHYA_TXFD_CFG_0_U___M                  0x01010101   
#define   PHYA_TXFD_CFG_0_U___S                                0

#define PHYA_TXFD_CFG_1_L                         (0x003916B8)
#define   PHYA_TXFD_CFG_1_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_1_L___POR                0x00000001
#define   PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___POR 0x0
#define   PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___POR 0x1
#define   PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___M 0x03000000
#define   PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___S              24
#define   PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___M 0x00010000
#define   PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___S              16
#define   PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___M 0x00000100
#define   PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___S               8
#define   PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___M 0x00000001
#define   PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___S               0
#define   PHYA_TXFD_CFG_1_L___M                  0x03010101   
#define   PHYA_TXFD_CFG_1_L___S                                0

#define PHYA_TXFD_CFG_1_U                         (0x003916BC)
#define   PHYA_TXFD_CFG_1_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_1_U___POR                0x00000000
#define   PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___POR 0x0
#define   PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___POR 0x0
#define   PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___M 0x00000100
#define   PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___S               8
#define   PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___M 0x00000001
#define   PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___S               0
#define   PHYA_TXFD_CFG_1_U___M                  0x00000101   
#define   PHYA_TXFD_CFG_1_U___S                                0

#define PHYA_TXFD_CFG_2_L                         (0x003916C0)
#define   PHYA_TXFD_CFG_2_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_2_L___POR                0x0004040A
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___POR 0x04
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___POR 0x04
#define   PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___POR 0x0A
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___M 0x00FF0000
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___S              16
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___M 0x0000FF00
#define   PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___S               8
#define   PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___M 0x0000001F
#define   PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___S               0
#define   PHYA_TXFD_CFG_2_L___M                  0x00FFFF1F   
#define   PHYA_TXFD_CFG_2_L___S                                0

#define PHYA_TXFD_CFG_2_U                         (0x003916C4)
#define   PHYA_TXFD_CFG_2_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_2_U___POR                0x140F03E8
#define   PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___POR 0x14
#define   PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___POR 0x0F
#define   PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___POR 0x03E8
#define   PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___M 0xFF000000
#define   PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___S              24
#define   PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___M 0x001F0000
#define   PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___S              16
#define   PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___M 0x0000FFFF
#define   PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___S               0
#define   PHYA_TXFD_CFG_2_U___M                  0xFF1FFFFF   
#define   PHYA_TXFD_CFG_2_U___S                                0

#define PHYA_TXFD_CFG_3_L                         (0x003916C8)
#define   PHYA_TXFD_CFG_3_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_3_L___POR                0x00007C96
#define   PHYA_TXFD_CFG_3_L__NON_M3_MODE___POR   0x0
#define   PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___POR 0x7C
#define   PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___POR 0x96
#define   PHYA_TXFD_CFG_3_L__NON_M3_MODE___M     0x00010000
#define   PHYA_TXFD_CFG_3_L__NON_M3_MODE___S                  16
#define   PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___M 0x0000FF00
#define   PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___S               8
#define   PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___M 0x000000FF
#define   PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___S               0
#define   PHYA_TXFD_CFG_3_L___M                  0x0001FFFF   
#define   PHYA_TXFD_CFG_3_L___S                                0

#define PHYA_TXFD_CFG_3_U                         (0x003916CC)
#define   PHYA_TXFD_CFG_3_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_3_U___POR                0x00003E80
#define   PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___POR 0x00003E80
#define   PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___M 0xFFFFFFFF
#define   PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___S               0
#define   PHYA_TXFD_CFG_3_U___M                  0xFFFFFFFF   
#define   PHYA_TXFD_CFG_3_U___S                                0

#define PHYA_TXFD_CFG_4_L                         (0x003916D0)
#define   PHYA_TXFD_CFG_4_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_4_L___POR                0x001E00A0
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___POR 0x001E
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___POR 0x00A0
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___M 0xFFFF0000
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___S              16
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___M 0x0000FFFF
#define   PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___S               0
#define   PHYA_TXFD_CFG_4_L___M                  0xFFFFFFFF   
#define   PHYA_TXFD_CFG_4_L___S                                0

#define PHYA_TXFD_CFG_4_U                         (0x003916D4)
#define   PHYA_TXFD_CFG_4_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_4_U___POR                0x01010096
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___POR 0x1
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___POR 0x1
#define   PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___POR 0x0096
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___M 0x01000000
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___S              24
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___M 0x00010000
#define   PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___S              16
#define   PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___M 0x0000FFFF
#define   PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___S               0
#define   PHYA_TXFD_CFG_4_U___M                  0x0101FFFF   
#define   PHYA_TXFD_CFG_4_U___S                                0

#define PHYA_TXFD_CFG_5_L                         (0x003916D8)
#define   PHYA_TXFD_CFG_5_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_5_L___POR                0x00010000
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___POR 0x0
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___POR 0x1
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___POR 0x0
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___POR 0x0
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___M 0x01000000
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___S              24
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___M 0x00010000
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___S              16
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___M 0x00000100
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___S               8
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___M 0x00000007
#define   PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___S               0
#define   PHYA_TXFD_CFG_5_L___M                  0x01010107   
#define   PHYA_TXFD_CFG_5_L___S                                0

#define PHYA_TXFD_CFG_5_U                         (0x003916DC)
#define   PHYA_TXFD_CFG_5_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_5_U___POR                0x00000001
#define   PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___POR 0x0
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___POR 0x0
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___POR 0x1
#define   PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___M 0x01000000
#define   PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___S              24
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___M 0x00010000
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___S              16
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___M 0x00000100
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___S               8
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___M 0x00000001
#define   PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___S               0
#define   PHYA_TXFD_CFG_5_U___M                  0x01010101   
#define   PHYA_TXFD_CFG_5_U___S                                0

#define PHYA_TXFD_CFG_6_L                         (0x003916E0)
#define   PHYA_TXFD_CFG_6_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_6_L___POR                0x08000000
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___POR 0x8
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___POR 0x0
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___M 0x0F000000
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___S              24
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___M 0x00010000
#define   PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___S              16
#define   PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___M 0x00000100
#define   PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___S               8
#define   PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___M 0x00000001
#define   PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___S               0
#define   PHYA_TXFD_CFG_6_L___M                  0x0F010101   
#define   PHYA_TXFD_CFG_6_L___S                                0

#define PHYA_TXFD_CFG_6_U                         (0x003916E4)
#define   PHYA_TXFD_CFG_6_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_6_U___POR                0x00000015
#define   PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___POR 0x15
#define   PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___M 0x0000003F
#define   PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___S               0
#define   PHYA_TXFD_CFG_6_U___M                  0x0000003F   
#define   PHYA_TXFD_CFG_6_U___S                                0

#define PHYA_TXFD_CFG_7_L                         (0x003916E8)
#define   PHYA_TXFD_CFG_7_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_7_L___POR                0x00000101
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___POR 0x0
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___POR 0x0
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___POR 0x1
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___POR 0x1
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___M 0x03000000
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___S              24
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___M 0x00030000
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___S              16
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___M 0x00000300
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___S               8
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___M 0x00000003
#define   PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___S               0
#define   PHYA_TXFD_CFG_7_L___M                  0x03030303   
#define   PHYA_TXFD_CFG_7_L___S                                0

#define PHYA_TXFD_CFG_7_U                         (0x003916EC)
#define   PHYA_TXFD_CFG_7_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_7_U___POR                0x00010100
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___POR 0x0
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___POR 0x1
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___POR 0x1
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___POR 0x0
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___M 0x03000000
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___S              24
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___M 0x00030000
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___S              16
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___M 0x00000300
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___S               8
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___M 0x00000003
#define   PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___S               0
#define   PHYA_TXFD_CFG_7_U___M                  0x03030303   
#define   PHYA_TXFD_CFG_7_U___S                                0

#define PHYA_TXFD_CFG_8_L                         (0x003916F0)
#define   PHYA_TXFD_CFG_8_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_8_L___POR                0x01000000
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___POR 0x1
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___POR 0x0
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___POR 0x0
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___POR 0x0
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___M 0x03000000
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___S              24
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___M 0x00030000
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___S              16
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___M 0x00000300
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___S               8
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___M 0x00000003
#define   PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___S               0
#define   PHYA_TXFD_CFG_8_L___M                  0x03030303   
#define   PHYA_TXFD_CFG_8_L___S                                0

#define PHYA_TXFD_CFG_9_L                         (0x003916F8)
#define   PHYA_TXFD_CFG_9_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_9_L___POR                0x000003C0
#define   PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___POR 0x03C0
#define   PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___M 0x0000FFFF
#define   PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___S               0
#define   PHYA_TXFD_CFG_9_L___M                  0x0000FFFF   
#define   PHYA_TXFD_CFG_9_L___S                                0

#define PHYA_TXFD_CFG_9_U                         (0x003916FC)
#define   PHYA_TXFD_CFG_9_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_CFG_9_U___POR                0x00001400
#define   PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___POR 0x00001400
#define   PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___S               0
#define   PHYA_TXFD_CFG_9_U___M                  0xFFFFFFFF   
#define   PHYA_TXFD_CFG_9_U___S                                0

#define PHYA_TXFD_CFG_10_L                        (0x00391700)
#define   PHYA_TXFD_CFG_10_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_10_L___POR               0x00000000
#define   PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___POR 0x0
#define   PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___POR 0x0
#define   PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___POR 0x0
#define   PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___POR 0x0
#define   PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___M 0x01000000
#define   PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___S              24
#define   PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___M 0x00010000
#define   PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___S              16
#define   PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___M 0x00000300
#define   PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___S               8
#define   PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___M 0x00000001
#define   PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___S               0
#define   PHYA_TXFD_CFG_10_L___M                 0x01010301   
#define   PHYA_TXFD_CFG_10_L___S                               0

#define PHYA_TXFD_CFG_10_U                        (0x00391704)
#define   PHYA_TXFD_CFG_10_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_10_U___POR               0x00000101
#define   PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___POR 0x01
#define   PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___POR 0x1
#define   PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___M 0x0000FF00
#define   PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___S               8
#define   PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___M 0x00000001
#define   PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___S               0
#define   PHYA_TXFD_CFG_10_U___M                 0x0000FF01   
#define   PHYA_TXFD_CFG_10_U___S                               0

#define PHYA_TXFD_CFG_11_L                        (0x00391708)
#define   PHYA_TXFD_CFG_11_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_11_L___POR               0x00000000
#define   PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___POR 0x00000000
#define   PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___M 0xFFFFFFFF
#define   PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___S               0
#define   PHYA_TXFD_CFG_11_L___M                 0xFFFFFFFF   
#define   PHYA_TXFD_CFG_11_L___S                               0

#define PHYA_TXFD_CFG_11_U                        (0x0039170C)
#define   PHYA_TXFD_CFG_11_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_11_U___POR               0x00000000
#define   PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___POR 0x00000000
#define   PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___M 0xFFFFFFFF
#define   PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___S               0
#define   PHYA_TXFD_CFG_11_U___M                 0xFFFFFFFF   
#define   PHYA_TXFD_CFG_11_U___S                               0

#define PHYA_TXFD_CFG_12_L                        (0x00391710)
#define   PHYA_TXFD_CFG_12_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_12_L___POR               0x00000000
#define   PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___POR 0x00
#define   PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___POR 0x00
#define   PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___POR 0x0
#define   PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___M 0x00FF0000
#define   PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___S              16
#define   PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___M 0x0000FF00
#define   PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___S               8
#define   PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___M 0x00000001
#define   PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___S               0
#define   PHYA_TXFD_CFG_12_L___M                 0x00FFFF01   
#define   PHYA_TXFD_CFG_12_L___S                               0

#define PHYA_TXFD_CFG_12_U                        (0x00391714)
#define   PHYA_TXFD_CFG_12_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_12_U___POR               0x00040008
#define   PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___POR 0x00040008
#define   PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___M 0xFFFFFFFF
#define   PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___S               0
#define   PHYA_TXFD_CFG_12_U___M                 0xFFFFFFFF   
#define   PHYA_TXFD_CFG_12_U___S                               0

#define PHYA_TXFD_CFG_13_L                        (0x00391718)
#define   PHYA_TXFD_CFG_13_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_13_L___POR               0x00000100
#define   PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___POR 0x1
#define   PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___POR 0x0
#define   PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___M 0x00000100
#define   PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___S               8
#define   PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___M 0x00000001
#define   PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___S               0
#define   PHYA_TXFD_CFG_13_L___M                 0x00000101   
#define   PHYA_TXFD_CFG_13_L___S                               0

#define PHYA_TXFD_CFG_14_L                        (0x00391720)
#define   PHYA_TXFD_CFG_14_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_14_L___POR               0x00000200
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___POR 0x02
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___POR 0x00
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___M 0x0000FF00
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___S               8
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___M 0x000000FF
#define   PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___S               0
#define   PHYA_TXFD_CFG_14_L___M                 0x0000FFFF   
#define   PHYA_TXFD_CFG_14_L___S                               0

#define PHYA_TXFD_CFG_15_L                        (0x00391728)
#define   PHYA_TXFD_CFG_15_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXFD_CFG_15_L___POR               0x00000200
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___POR 0x02
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___POR 0x00
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___M 0x0000FF00
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___S               8
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___M 0x000000FF
#define   PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___S               0
#define   PHYA_TXFD_CFG_15_L___M                 0x0000FFFF   
#define   PHYA_TXFD_CFG_15_L___S                               0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L             (0x00391730)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___POR    0x00000EEF
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U             (0x00391734)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___POR    0x00000EEF
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L             (0x00391738)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___POR    0x00000EEF
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U             (0x0039173C)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___POR    0x00000EEF
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___POR 0x1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L             (0x00391740)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U             (0x00391744)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L             (0x00391748)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U             (0x0039174C)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L             (0x00391750)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U             (0x00391754)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L             (0x00391758)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U             (0x0039175C)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L             (0x00391760)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U             (0x00391764)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L             (0x00391768)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___S                    0

#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U             (0x0039176C)
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___POR    0x00000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___POR 0x0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___M 0x80000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___S              31
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___M 0x40000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___S              30
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___M 0x20000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___S              29
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___M 0x10000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___S              28
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___M 0x08000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___S              27
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___M 0x04000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___S              26
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___M 0x02000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___S              25
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___M 0x01000000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___S              24
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___M 0x00800000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___S              23
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___M 0x00400000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___S              22
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___M 0x00200000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___S              21
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___M 0x00100000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___S              20
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___M 0x00080000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___S              19
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___M 0x00040000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___S              18
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___M 0x00020000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___S              17
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___M 0x00010000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___S              16
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___M 0x00008000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___S              15
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___M 0x00004000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___S              14
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___M 0x00002000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___S              13
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___M 0x00001000
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___S              12
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___M 0x00000800
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___S              11
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___M 0x00000400
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___S              10
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___M 0x00000200
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___S               9
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___M 0x00000100
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___S               8
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___M 0x00000080
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___S               7
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___M 0x00000040
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___S               6
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___M 0x00000020
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___S               5
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___M 0x00000010
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___S               4
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___M 0x00000008
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___S               3
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___M 0x00000004
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___S               2
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___M 0x00000002
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___S               1
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___M 0x00000001
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___S               0
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___S                    0

#define PHYA_TXFD_PUBLIC_SPARE_L                  (0x00391770)
#define   PHYA_TXFD_PUBLIC_SPARE_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_PUBLIC_SPARE_L___POR         0x00000000
#define   PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S               0
#define   PHYA_TXFD_PUBLIC_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_PUBLIC_SPARE_L___S                         0

#define PHYA_TXFD_PUBLIC_SPARE_U                  (0x00391774)
#define   PHYA_TXFD_PUBLIC_SPARE_U___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_PUBLIC_SPARE_U___POR         0x00000000
#define   PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S               0
#define   PHYA_TXFD_PUBLIC_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_TXFD_PUBLIC_SPARE_U___S                         0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L         (0x00391778)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U         (0x0039177C)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L         (0x00391780)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U         (0x00391784)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L         (0x00391788)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U         (0x0039178C)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L         (0x00391790)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U         (0x00391794)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L         (0x00391798)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U         (0x0039179C)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L         (0x003917A0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U         (0x003917A4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L         (0x003917A8)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U         (0x003917AC)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L         (0x003917B0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U         (0x003917B4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L         (0x003917B8)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U         (0x003917BC)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L         (0x003917C0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U         (0x003917C4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___S                0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L        (0x003917C8)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U        (0x003917CC)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L        (0x003917D0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U        (0x003917D4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L        (0x003917D8)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U        (0x003917DC)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L        (0x003917E0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U        (0x003917E4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L        (0x003917E8)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U        (0x003917EC)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L        (0x003917F0)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___S               0

#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U        (0x003917F4)
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___POR 0x00000000
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___S               0
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___S               0

#define PHYA_TXFD_PRIVATE_SPARE_L                 (0x003917F8)
#define   PHYA_TXFD_PRIVATE_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PRIVATE_SPARE_L___POR        0x00000000
#define   PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S               0
#define   PHYA_TXFD_PRIVATE_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_TXFD_PRIVATE_SPARE_L___S                        0

#define PHYA_TXFD_PRIVATE_SPARE_U                 (0x003917FC)
#define   PHYA_TXFD_PRIVATE_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PRIVATE_SPARE_U___POR        0x00000000
#define   PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S               0
#define   PHYA_TXFD_PRIVATE_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_TXFD_PRIVATE_SPARE_U___S                        0

#define PHYA_TXFD_PRE_PKT_START_WR_0_L            (0x00391800)
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L___POR   0x00000100
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___POR 0x1
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___M 0x00000100
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___S               8
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___M 0x00000001
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L___M     0x00000101   
#define   PHYA_TXFD_PRE_PKT_START_WR_0_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_0_U            (0x00391804)
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U___POR   0x00000033
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___POR 0x000033
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___M 0x00FFFFFF
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U___M     0x00FFFFFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_0_U___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_1_L            (0x00391808)
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L___POR   0xFF010100
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___POR 0xFF
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___POR 0x1
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___POR 0x01
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___M 0xFF000000
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___S              24
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___M 0x00010000
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___S              16
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___M 0x0000FF00
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___S               8
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___M 0x0000000F
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L___M     0xFF01FF0F   
#define   PHYA_TXFD_PRE_PKT_START_WR_1_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_1_U            (0x0039180C)
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___M 0x00000001
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U___M     0x00000001   
#define   PHYA_TXFD_PRE_PKT_START_WR_1_U___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_2_L            (0x00391810)
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___POR 0x00
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___POR 0x00
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___M 0x0000FF00
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___S               8
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___M 0x000000FF
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L___M     0x0000FFFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_2_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_3_L            (0x00391818)
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L___POR   0x00000033
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___POR 0x0033
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___M 0x00010000
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___S              16
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___M 0x0000FFFF
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L___M     0x0001FFFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_3_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_4_L            (0x00391820)
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___POR 0x0000
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___POR 0x0000
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___M 0x3FFF0000
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___S              16
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___M 0x00003FFF
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L___M     0x3FFF3FFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_4_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_5_L            (0x00391830)
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___M 0x00000001
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L___M     0x00000001   
#define   PHYA_TXFD_PRE_PKT_START_WR_5_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_6_L            (0x00391838)
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___POR 0x0000
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___POR 0x0000
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___M 0x3FFF0000
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___S              16
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___M 0x00003FFF
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L___M     0x3FFF3FFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_6_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_7_L            (0x00391848)
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L___POR   0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___POR 0x0
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___M 0x00000001
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L___M     0x00000001   
#define   PHYA_TXFD_PRE_PKT_START_WR_7_L___S                   0

#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L        (0x00391850)
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___S               0

#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U        (0x00391854)
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___S               0
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___S               0

#define PHYA_TXFD_PKT_START_FAST_WR_L             (0x00391858)
#define   PHYA_TXFD_PKT_START_FAST_WR_L___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_WR_L___POR    0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___S               0
#define   PHYA_TXFD_PKT_START_FAST_WR_L___M      0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_WR_L___S                    0

#define PHYA_TXFD_PKT_START_FAST_WR_U             (0x0039185C)
#define   PHYA_TXFD_PKT_START_FAST_WR_U___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_WR_U___POR    0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___S               0
#define   PHYA_TXFD_PKT_START_FAST_WR_U___M      0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_WR_U___S                    0

#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L       (0x00391860)
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___S               0
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___S               0

#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U       (0x00391864)
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___S               0
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___S               0

#define PHYA_TXFD_PKT_START_FAST_RD_L             (0x00391868)
#define   PHYA_TXFD_PKT_START_FAST_RD_L___RWC       QCSR_REG_RO    
#define   PHYA_TXFD_PKT_START_FAST_RD_L___POR    0x00000000
#define   PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___POR 0x0
#define   PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___M 0x00000001
#define   PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___S               0
#define   PHYA_TXFD_PKT_START_FAST_RD_L___M      0x00000001   
#define   PHYA_TXFD_PKT_START_FAST_RD_L___S                    0

#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L       (0x00391870)
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___S               0
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___S               0

#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U       (0x00391874)
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___S               0
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___S               0

#define PHYA_TXFD_PKT_START_SLOW_WR_0_L           (0x00391878)
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L___POR  0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___M 0x00010000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___S              16
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___M 0x00000100
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___S               8
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___M 0x00000001
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L___M    0x00010101   
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_L___S                  0

#define PHYA_TXFD_PKT_START_SLOW_WR_0_U           (0x0039187C)
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U___POR  0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___POR 0x0000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___POR 0x0000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___M 0xFFFF0000
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___S              16
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___M 0x0000FFFF
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U___M    0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_SLOW_WR_0_U___S                  0

#define PHYA_TXFD_PKT_START_SLOW_WR_1_L           (0x00391880)
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L___POR  0x00010000
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___POR 0x1
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___M 0x01000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___S              24
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___M 0x00010000
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___S              16
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___M 0x00000100
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___S               8
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___M 0x00000001
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L___M    0x01010101   
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_L___S                  0

#define PHYA_TXFD_PKT_START_SLOW_WR_1_U           (0x00391884)
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U___POR  0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___POR 0x0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___M 0x00000100
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___S               8
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___M 0x00000001
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U___M    0x00000101   
#define   PHYA_TXFD_PKT_START_SLOW_WR_1_U___S                  0

#define PHYA_TXFD_SYM_SEQ_TBL0_L                  (0x00391888)
#define   PHYA_TXFD_SYM_SEQ_TBL0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_SYM_SEQ_TBL0_L___POR         0x00040302
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___POR 0x04
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___POR 0x03
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___POR 0x02
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___M 0x1F000000
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___S              24
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___M 0x001F0000
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___S              16
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___M 0x00001F00
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___S               8
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___M 0x0000001F
#define   PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___S               0
#define   PHYA_TXFD_SYM_SEQ_TBL0_L___M           0x1F1F1F1F   
#define   PHYA_TXFD_SYM_SEQ_TBL0_L___S                         0

#define PHYA_TXFD_SYM_SEQ_TBL0_U                  (0x0039188C)
#define   PHYA_TXFD_SYM_SEQ_TBL0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_SYM_SEQ_TBL0_U___POR         0x00000000
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___M 0x1F000000
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___S              24
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___M 0x001F0000
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___S              16
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___M 0x00001F00
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___S               8
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___M 0x0000001F
#define   PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___S               0
#define   PHYA_TXFD_SYM_SEQ_TBL0_U___M           0x1F1F1F1F   
#define   PHYA_TXFD_SYM_SEQ_TBL0_U___S                         0

#define PHYA_TXFD_SYM_SEQ_TBL1_L                  (0x00391890)
#define   PHYA_TXFD_SYM_SEQ_TBL1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_SYM_SEQ_TBL1_L___POR         0x00000000
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___M 0x1F000000
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___S              24
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___M 0x001F0000
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___S              16
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___M 0x00001F00
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___S               8
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___M 0x0000001F
#define   PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___S               0
#define   PHYA_TXFD_SYM_SEQ_TBL1_L___M           0x1F1F1F1F   
#define   PHYA_TXFD_SYM_SEQ_TBL1_L___S                         0

#define PHYA_TXFD_SYM_SEQ_TBL1_U                  (0x00391894)
#define   PHYA_TXFD_SYM_SEQ_TBL1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXFD_SYM_SEQ_TBL1_U___POR         0x00000000
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___POR 0x00
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___M 0x1F000000
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___S              24
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___M 0x001F0000
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___S              16
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___M 0x00001F00
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___S               8
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___M 0x0000001F
#define   PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___S               0
#define   PHYA_TXFD_SYM_SEQ_TBL1_U___M           0x1F1F1F1F   
#define   PHYA_TXFD_SYM_SEQ_TBL1_U___S                         0

#define PHYA_TXFD_REQ_TBL0_L                      (0x00391898)
#define   PHYA_TXFD_REQ_TBL0_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL0_L___POR             0x00000020
#define   PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___POR 0x20
#define   PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___S               0
#define   PHYA_TXFD_REQ_TBL0_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL0_L___S                             0

#define PHYA_TXFD_REQ_TBL0_U                      (0x0039189C)
#define   PHYA_TXFD_REQ_TBL0_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL0_U___POR             0x000003E8
#define   PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___POR 0x000003E8
#define   PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___S               0
#define   PHYA_TXFD_REQ_TBL0_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL0_U___S                             0

#define PHYA_TXFD_REQ_TBL1_L                      (0x003918A0)
#define   PHYA_TXFD_REQ_TBL1_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL1_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___POR 0x00
#define   PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___S               0
#define   PHYA_TXFD_REQ_TBL1_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL1_L___S                             0

#define PHYA_TXFD_REQ_TBL1_U                      (0x003918A4)
#define   PHYA_TXFD_REQ_TBL1_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL1_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___S               0
#define   PHYA_TXFD_REQ_TBL1_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL1_U___S                             0

#define PHYA_TXFD_REQ_TBL2_L                      (0x003918A8)
#define   PHYA_TXFD_REQ_TBL2_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL2_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___POR 0x00
#define   PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___S               0
#define   PHYA_TXFD_REQ_TBL2_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL2_L___S                             0

#define PHYA_TXFD_REQ_TBL2_U                      (0x003918AC)
#define   PHYA_TXFD_REQ_TBL2_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL2_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___S               0
#define   PHYA_TXFD_REQ_TBL2_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL2_U___S                             0

#define PHYA_TXFD_REQ_TBL3_L                      (0x003918B0)
#define   PHYA_TXFD_REQ_TBL3_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL3_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___POR 0x00
#define   PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___S               0
#define   PHYA_TXFD_REQ_TBL3_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL3_L___S                             0

#define PHYA_TXFD_REQ_TBL3_U                      (0x003918B4)
#define   PHYA_TXFD_REQ_TBL3_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL3_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___S               0
#define   PHYA_TXFD_REQ_TBL3_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL3_U___S                             0

#define PHYA_TXFD_REQ_TBL4_L                      (0x003918B8)
#define   PHYA_TXFD_REQ_TBL4_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL4_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___POR 0x00
#define   PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___S               0
#define   PHYA_TXFD_REQ_TBL4_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL4_L___S                             0

#define PHYA_TXFD_REQ_TBL4_U                      (0x003918BC)
#define   PHYA_TXFD_REQ_TBL4_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL4_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___S               0
#define   PHYA_TXFD_REQ_TBL4_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL4_U___S                             0

#define PHYA_TXFD_REQ_TBL5_L                      (0x003918C0)
#define   PHYA_TXFD_REQ_TBL5_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL5_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___POR 0x00
#define   PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___S               0
#define   PHYA_TXFD_REQ_TBL5_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL5_L___S                             0

#define PHYA_TXFD_REQ_TBL5_U                      (0x003918C4)
#define   PHYA_TXFD_REQ_TBL5_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL5_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___S               0
#define   PHYA_TXFD_REQ_TBL5_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL5_U___S                             0

#define PHYA_TXFD_REQ_TBL6_L                      (0x003918C8)
#define   PHYA_TXFD_REQ_TBL6_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL6_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___POR 0x00
#define   PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___S               0
#define   PHYA_TXFD_REQ_TBL6_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL6_L___S                             0

#define PHYA_TXFD_REQ_TBL6_U                      (0x003918CC)
#define   PHYA_TXFD_REQ_TBL6_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL6_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___S               0
#define   PHYA_TXFD_REQ_TBL6_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL6_U___S                             0

#define PHYA_TXFD_REQ_TBL7_L                      (0x003918D0)
#define   PHYA_TXFD_REQ_TBL7_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL7_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___POR 0x00
#define   PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___S               0
#define   PHYA_TXFD_REQ_TBL7_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL7_L___S                             0

#define PHYA_TXFD_REQ_TBL7_U                      (0x003918D4)
#define   PHYA_TXFD_REQ_TBL7_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL7_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___S               0
#define   PHYA_TXFD_REQ_TBL7_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL7_U___S                             0

#define PHYA_TXFD_REQ_TBL8_L                      (0x003918D8)
#define   PHYA_TXFD_REQ_TBL8_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL8_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___POR 0x00
#define   PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___S               0
#define   PHYA_TXFD_REQ_TBL8_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL8_L___S                             0

#define PHYA_TXFD_REQ_TBL8_U                      (0x003918DC)
#define   PHYA_TXFD_REQ_TBL8_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL8_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___S               0
#define   PHYA_TXFD_REQ_TBL8_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL8_U___S                             0

#define PHYA_TXFD_REQ_TBL9_L                      (0x003918E0)
#define   PHYA_TXFD_REQ_TBL9_L___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL9_L___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___POR 0x00
#define   PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___S               0
#define   PHYA_TXFD_REQ_TBL9_L___M               0x0000003F   
#define   PHYA_TXFD_REQ_TBL9_L___S                             0

#define PHYA_TXFD_REQ_TBL9_U                      (0x003918E4)
#define   PHYA_TXFD_REQ_TBL9_U___RWC                QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL9_U___POR             0x00000000
#define   PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___S               0
#define   PHYA_TXFD_REQ_TBL9_U___M               0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL9_U___S                             0

#define PHYA_TXFD_REQ_TBL10_L                     (0x003918E8)
#define   PHYA_TXFD_REQ_TBL10_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL10_L___POR            0x00000000
#define   PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___POR 0x00
#define   PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___S               0
#define   PHYA_TXFD_REQ_TBL10_L___M              0x0000003F   
#define   PHYA_TXFD_REQ_TBL10_L___S                            0

#define PHYA_TXFD_REQ_TBL10_U                     (0x003918EC)
#define   PHYA_TXFD_REQ_TBL10_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL10_U___POR            0x00000000
#define   PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___S               0
#define   PHYA_TXFD_REQ_TBL10_U___M              0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL10_U___S                            0

#define PHYA_TXFD_REQ_TBL11_L                     (0x003918F0)
#define   PHYA_TXFD_REQ_TBL11_L___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL11_L___POR            0x00000000
#define   PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___POR 0x00
#define   PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___M 0x0000003F
#define   PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___S               0
#define   PHYA_TXFD_REQ_TBL11_L___M              0x0000003F   
#define   PHYA_TXFD_REQ_TBL11_L___S                            0

#define PHYA_TXFD_REQ_TBL11_U                     (0x003918F4)
#define   PHYA_TXFD_REQ_TBL11_U___RWC               QCSR_REG_RW    
#define   PHYA_TXFD_REQ_TBL11_U___POR            0x00000000
#define   PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___POR 0x00000000
#define   PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___M 0xFFFFFFFF
#define   PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___S               0
#define   PHYA_TXFD_REQ_TBL11_U___M              0xFFFFFFFF   
#define   PHYA_TXFD_REQ_TBL11_U___S                            0

#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L       (0x003918F8)
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___S               0

#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U       (0x003918FC)
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___S               0
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___S               0

#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L            (0x00391900)
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___POR   0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___M 0xFF000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___S              24
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___M 0x00FF0000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___S              16
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___M 0x0000FF00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___S               8
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___M 0x000000FF
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___S               0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___M     0xFFFFFFFF   
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___S                   0

#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U            (0x00391904)
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___POR   0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___POR 0x00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___M 0xFF000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___S              24
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___M 0x00FF0000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___S              16
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___M 0x0000FF00
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___S               8
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___M 0x000000FF
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___S               0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___M     0xFFFFFFFF   
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___S                   0

#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L            (0x00391908)
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___POR   0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___POR 0x0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___M 0x00000003
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___S               0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___M     0x00000003   
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___S                   0

#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L        (0x00391910)
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___S               0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___S               0

#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U        (0x00391914)
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___S               0
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___S               0

#define PHYA_TXFD_ERROR_EVENT_RD_0_L              (0x00391918)
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___POR 0x00
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___M 0x000000FF
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L___M       0x000000FF   
#define   PHYA_TXFD_ERROR_EVENT_RD_0_L___S                     0

#define PHYA_TXFD_ERROR_EVENT_RD_0_U              (0x0039191C)
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___POR 0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_EVENT_RD_0_U___S                     0

#define PHYA_TXFD_ERROR_EVENT_RD_1_L              (0x00391920)
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___POR 0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_EVENT_RD_1_L___S                     0

#define PHYA_TXFD_ERROR_EVENT_RD_1_U              (0x00391924)
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___POR 0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_EVENT_RD_1_U___S                     0

#define PHYA_TXFD_ERROR_EVENT_RD_2_L              (0x00391928)
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___POR 0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_EVENT_RD_2_L___S                     0

#define PHYA_TXFD_ERROR_EVENT_RD_2_U              (0x0039192C)
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U___POR     0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___POR 0x00000000
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___S               0
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_EVENT_RD_2_U___S                     0

#define PHYA_TXFD_ERROR_RD_SPARE_0_L              (0x00391930)
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L___POR     0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___S               0
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_RD_SPARE_0_L___S                     0

#define PHYA_TXFD_ERROR_RD_SPARE_0_U              (0x00391934)
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U___POR     0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___S               0
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_RD_SPARE_0_U___S                     0

#define PHYA_TXFD_ERROR_EVENT_WR_L                (0x00391938)
#define   PHYA_TXFD_ERROR_EVENT_WR_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_EVENT_WR_L___POR       0x00000000
#define   PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___POR 0x00
#define   PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___POR 0x0
#define   PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___POR 0x0
#define   PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___M 0x003F0000
#define   PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___S              16
#define   PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___M 0x00000100
#define   PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___S               8
#define   PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___M 0x00000001
#define   PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___S               0
#define   PHYA_TXFD_ERROR_EVENT_WR_L___M         0x003F0101   
#define   PHYA_TXFD_ERROR_EVENT_WR_L___S                       0

#define PHYA_TXFD_ERROR_RD_SPARE_1_L              (0x00391940)
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L___POR     0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___S               0
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_RD_SPARE_1_L___S                     0

#define PHYA_TXFD_ERROR_RD_SPARE_1_U              (0x00391944)
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U___POR     0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___S               0
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U___M       0xFFFFFFFF   
#define   PHYA_TXFD_ERROR_RD_SPARE_1_U___S                     0

#define PHYA_TXFD_FW_SYM_START_WR_L               (0x00391948)
#define   PHYA_TXFD_FW_SYM_START_WR_L___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_FW_SYM_START_WR_L___POR      0x00000000
#define   PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___POR 0x0
#define   PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___POR 0x0000
#define   PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___M 0x00070000
#define   PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___S              16
#define   PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___M 0x0000FFFF
#define   PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___S               0
#define   PHYA_TXFD_FW_SYM_START_WR_L___M        0x0007FFFF   
#define   PHYA_TXFD_FW_SYM_START_WR_L___S                      0

#define PHYA_TXFD_NULL_LUT_2_L                    (0x00391950)
#define   PHYA_TXFD_NULL_LUT_2_L___RWC              QCSR_REG_RW    
#define   PHYA_TXFD_NULL_LUT_2_L___POR           0x00001222
#define   PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___POR 0x001222
#define   PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___M 0x00FFFFFF
#define   PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___S               0
#define   PHYA_TXFD_NULL_LUT_2_L___M             0x00FFFFFF   
#define   PHYA_TXFD_NULL_LUT_2_L___S                           0

#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L         (0x00391958)
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___S               0
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L___M  0xFFFFFFFF   
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_L___S                0

#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U         (0x0039195C)
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___S               0
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_FW_SYM_START_WR_SPARE_U___S                0

#define PHYA_TXFD_ALL_SYM_START_RD_L              (0x00391960)
#define   PHYA_TXFD_ALL_SYM_START_RD_L___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ALL_SYM_START_RD_L___POR     0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___POR 0x0000
#define   PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___POR 0x00
#define   PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___M 0xFFFF0000
#define   PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___S              16
#define   PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___M 0x0000001F
#define   PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___S               0
#define   PHYA_TXFD_ALL_SYM_START_RD_L___M       0xFFFF001F   
#define   PHYA_TXFD_ALL_SYM_START_RD_L___S                     0

#define PHYA_TXFD_ALL_SYM_START_RD_U              (0x00391964)
#define   PHYA_TXFD_ALL_SYM_START_RD_U___RWC        QCSR_REG_RO    
#define   PHYA_TXFD_ALL_SYM_START_RD_U___POR     0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___POR 0x0000
#define   PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___M 0x0000FFFF
#define   PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___S               0
#define   PHYA_TXFD_ALL_SYM_START_RD_U___M       0x0000FFFF   
#define   PHYA_TXFD_ALL_SYM_START_RD_U___S                     0

#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L        (0x00391968)
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___S               0
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___S               0

#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U        (0x0039196C)
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___S               0
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___S               0

#define PHYA_TXFD_ALL_SYM_START_WR_L              (0x00391970)
#define   PHYA_TXFD_ALL_SYM_START_WR_L___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_WR_L___POR     0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___POR 0x000
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___POR 0x0
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___M 0x07FF0000
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___S              16
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___M 0x00000003
#define   PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___S               0
#define   PHYA_TXFD_ALL_SYM_START_WR_L___M       0x07FF0003   
#define   PHYA_TXFD_ALL_SYM_START_WR_L___S                     0

#define PHYA_TXFD_ALL_SYM_START_WR_U              (0x00391974)
#define   PHYA_TXFD_ALL_SYM_START_WR_U___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_WR_U___POR     0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___POR 0x000
#define   PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___M 0x000007FF
#define   PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___S               0
#define   PHYA_TXFD_ALL_SYM_START_WR_U___M       0x000007FF   
#define   PHYA_TXFD_ALL_SYM_START_WR_U___S                     0

#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L          (0x00391978)
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L___RWC    QCSR_REG_RW    
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L___POR 0x00000000
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___POR 0x00
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___M 0x000000FF
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___S               0
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L___M   0x000000FF   
#define   PHYA_TXFD_WUR_ALL_SYM_START_WR_L___S                 0

#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L        (0x00391980)
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___S               0
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___S               0

#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U        (0x00391984)
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___S               0
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___S               0

#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n(n) (0x00391988+0x8*(n))
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_nMIN 0    
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_nMAX 0    
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_ELEM 1    
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___RWC    QCSR_REG_RW    
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___POR 0x00000000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___POR 0x0
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___POR 0x0
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___POR 0x0000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___M 0x00020000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___S              17
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___M 0x00010000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___S              16
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___M 0x0000FFFF
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___S               0
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___M   0x0003FFFF   
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___S                 0
#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0          (0x00391988)
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0___RWC    QCSR_REG_RW    
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_LAST___M 0x00020000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_LAST___S              17
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_START___M 0x00010000
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_START___S              16
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_DATA___M 0x0000FFFF
#define   PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_DATA___S               0

#define PHYA_TXFD_HE_SIGA_FIFO_L_n(n)    (0x00391A08+0x8*(n))
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n___POR       0x00000000
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___S               0
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n___M         0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGA_FIFO_L_n___S                       0
#define PHYA_TXFD_HE_SIGA_FIFO_L_0                (0x00391A08)
#define   PHYA_TXFD_HE_SIGA_FIFO_L_0___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_FIFO_L_0__HE_SIGA_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_FIFO_L_0__HE_SIGA_0___S               0

#define PHYA_TXFD_HE_SIGA_FIFO_U_n(n)    (0x00391A0C+0x8*(n))
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n___POR       0x00000000
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___S               0
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n___M         0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGA_FIFO_U_n___S                       0
#define PHYA_TXFD_HE_SIGA_FIFO_U_0                (0x00391A0C)
#define   PHYA_TXFD_HE_SIGA_FIFO_U_0___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_FIFO_U_0__HE_SIGA_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_FIFO_U_0__HE_SIGA_1___S               0

#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L         (0x00391A88)
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___POR 0x0
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___M 0x0000000F
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___S               0
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___M  0x0000000F   
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___S                0

#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U         (0x00391A8C)
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___RWC   QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___S               0
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___M  0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___S                0

#define PHYA_TXFD_HE_SIGB0_FIFO_L_n(n)   (0x00391A90+0x8*(n))
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n___POR      0x00000000
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___S               0
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n___M        0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_n___S                      0
#define PHYA_TXFD_HE_SIGB0_FIFO_L_0               (0x00391A90)
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_0___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_0__HE_SIGB0_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB0_FIFO_L_0__HE_SIGB0_FIFO_0___S               0

#define PHYA_TXFD_HE_SIGB0_FIFO_U_n(n)   (0x00391A94+0x8*(n))
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n___POR      0x00000000
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___S               0
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n___M        0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_n___S                      0
#define PHYA_TXFD_HE_SIGB0_FIFO_U_0               (0x00391A94)
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_0___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_0__HE_SIGB0_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB0_FIFO_U_0__HE_SIGB0_FIFO_1___S               0

#define PHYA_TXFD_HE_SIGB1_FIFO_L_n(n)   (0x00391B10+0x8*(n))
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n___POR      0x00000000
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___S               0
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n___M        0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_n___S                      0
#define PHYA_TXFD_HE_SIGB1_FIFO_L_0               (0x00391B10)
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_0___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_0__HE_SIGB1_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB1_FIFO_L_0__HE_SIGB1_FIFO_0___S               0

#define PHYA_TXFD_HE_SIGB1_FIFO_U_n(n)   (0x00391B14+0x8*(n))
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n_nMIN 0    
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n_nMAX 0    
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n_ELEM 1    
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n___POR      0x00000000
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___POR 0x00000000
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___S               0
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n___M        0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_n___S                      0
#define PHYA_TXFD_HE_SIGB1_FIFO_U_0               (0x00391B14)
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_0___RWC         QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_0__HE_SIGB1_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGB1_FIFO_U_0__HE_SIGB1_FIFO_1___S               0

#define PHYA_TXFD_TLV_FIFO_L_n(n)        (0x00391B90+0x8*(n))
#define   PHYA_TXFD_TLV_FIFO_L_n_nMIN 0    
#define   PHYA_TXFD_TLV_FIFO_L_n_nMAX 0    
#define   PHYA_TXFD_TLV_FIFO_L_n_ELEM 1    
#define   PHYA_TXFD_TLV_FIFO_L_n___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_L_n___POR           0x00000000
#define   PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___POR 0x00000000
#define   PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___S               0
#define   PHYA_TXFD_TLV_FIFO_L_n___M             0xFFFFFFFF   
#define   PHYA_TXFD_TLV_FIFO_L_n___S                           0
#define PHYA_TXFD_TLV_FIFO_L_0                    (0x00391B90)
#define   PHYA_TXFD_TLV_FIFO_L_0___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_L_0__TLV_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_L_0__TLV_FIFO_0___S               0

#define PHYA_TXFD_TLV_FIFO_U_n(n)        (0x00391B94+0x8*(n))
#define   PHYA_TXFD_TLV_FIFO_U_n_nMIN 0    
#define   PHYA_TXFD_TLV_FIFO_U_n_nMAX 0    
#define   PHYA_TXFD_TLV_FIFO_U_n_ELEM 1    
#define   PHYA_TXFD_TLV_FIFO_U_n___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_U_n___POR           0x00000000
#define   PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___POR 0x00000000
#define   PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___S               0
#define   PHYA_TXFD_TLV_FIFO_U_n___M             0xFFFFFFFF   
#define   PHYA_TXFD_TLV_FIFO_U_n___S                           0
#define PHYA_TXFD_TLV_FIFO_U_0                    (0x00391B94)
#define   PHYA_TXFD_TLV_FIFO_U_0___RWC              QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_U_0__TLV_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_U_0__TLV_FIFO_1___S               0

#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n(n) (0x00391C10+0x8*(n))
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n_nMIN 0    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n_nMAX 0    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n_ELEM 1    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n___RWC     QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n___POR  0x00000000
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___POR 0x00000000
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___S               0
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n___M    0xFFFFFFFF   
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_n___S                  0
#define PHYA_TXFD_TLV_FIFO_PER_USER_L_0           (0x00391C10)
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_0___RWC     QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_0__TLV_FIFO_PER_USER_0___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_PER_USER_L_0__TLV_FIFO_PER_USER_0___S               0

#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n(n) (0x00391C14+0x8*(n))
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n_nMIN 0    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n_nMAX 0    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n_ELEM 1    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n___RWC     QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n___POR  0x00000000
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___POR 0x00000000
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___S               0
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n___M    0xFFFFFFFF   
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_n___S                  0
#define PHYA_TXFD_TLV_FIFO_PER_USER_U_0           (0x00391C14)
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_0___RWC     QCSR_REG_RO    
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_0__TLV_FIFO_PER_USER_1___M 0xFFFFFFFF
#define   PHYA_TXFD_TLV_FIFO_PER_USER_U_0__TLV_FIFO_PER_USER_1___S               0

#define PHYA_TXFD_PKT_END_RD_0_L                  (0x00391C90)
#define   PHYA_TXFD_PKT_END_RD_0_L___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_PKT_END_RD_0_L___POR         0x00000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___M 0x80000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___S              31
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___M 0x40000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___S              30
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___M 0x20000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___S              29
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___M 0x10000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___S              28
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___M 0x08000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___S              27
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___M 0x04000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___S              26
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___M 0x02000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___S              25
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___M 0x01000000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___S              24
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___M 0x00800000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___S              23
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___M 0x00400000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___S              22
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___M 0x00200000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___S              21
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___M 0x00100000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___S              20
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___M 0x00080000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___S              19
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___M 0x00040000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___S              18
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___M 0x00020000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___S              17
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___M 0x00010000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___S              16
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___M 0x00008000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___S              15
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___M 0x00004000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___S              14
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___M 0x00002000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___S              13
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___M 0x00001000
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___S              12
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___M 0x00000800
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___S              11
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___M 0x00000400
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___S              10
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___M 0x00000200
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___S               9
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___M 0x00000100
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___S               8
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___M 0x00000080
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___S               7
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___M 0x00000040
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___S               6
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___M 0x00000020
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___S               5
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___M 0x00000010
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___S               4
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___M 0x00000008
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___S               3
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___M 0x00000004
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___S               2
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___M 0x00000002
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___S               1
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___M 0x00000001
#define   PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___S               0
#define   PHYA_TXFD_PKT_END_RD_0_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_PKT_END_RD_0_L___S                         0

#define PHYA_TXFD_PKT_END_RD_0_U                  (0x00391C94)
#define   PHYA_TXFD_PKT_END_RD_0_U___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_PKT_END_RD_0_U___POR         0x00000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___POR 0x0
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___M 0x80000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___S              31
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___M 0x40000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___S              30
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___M 0x20000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___S              29
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___M 0x10000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___S              28
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___M 0x08000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___S              27
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___M 0x04000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___S              26
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___M 0x02000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___S              25
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___M 0x01000000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___S              24
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___M 0x00800000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___S              23
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___M 0x00400000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___S              22
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___M 0x00200000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___S              21
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___M 0x00100000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___S              20
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___M 0x00080000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___S              19
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___M 0x00040000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___S              18
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___M 0x00020000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___S              17
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___M 0x00010000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___S              16
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___M 0x00008000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___S              15
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___M 0x00004000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___S              14
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___M 0x00002000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___S              13
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___M 0x00001000
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___S              12
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___M 0x00000800
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___S              11
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___M 0x00000400
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___S              10
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___M 0x00000200
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___S               9
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___M 0x00000100
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___S               8
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___M 0x00000080
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___S               7
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___M 0x00000040
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___S               6
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___M 0x00000020
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___S               5
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___M 0x00000010
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___S               4
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___M 0x00000008
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___S               3
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___M 0x00000004
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___S               2
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___M 0x00000002
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___S               1
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___M 0x00000001
#define   PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___S               0
#define   PHYA_TXFD_PKT_END_RD_0_U___M           0xFFFFFFFF   
#define   PHYA_TXFD_PKT_END_RD_0_U___S                         0

#define PHYA_TXFD_PKT_END_RD_1_L                  (0x00391C98)
#define   PHYA_TXFD_PKT_END_RD_1_L___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_PKT_END_RD_1_L___POR         0x00000000
#define   PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___POR 0x0000
#define   PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___M 0x0000FFFF
#define   PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___S               0
#define   PHYA_TXFD_PKT_END_RD_1_L___M           0x0000FFFF   
#define   PHYA_TXFD_PKT_END_RD_1_L___S                         0

#define PHYA_TXFD_PKT_END_SPARE_L                 (0x00391CA0)
#define   PHYA_TXFD_PKT_END_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PKT_END_SPARE_L___POR        0x00000000
#define   PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___S               0
#define   PHYA_TXFD_PKT_END_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_TXFD_PKT_END_SPARE_L___S                        0

#define PHYA_TXFD_PKT_END_SPARE_U                 (0x00391CA4)
#define   PHYA_TXFD_PKT_END_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_PKT_END_SPARE_U___POR        0x00000000
#define   PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___S               0
#define   PHYA_TXFD_PKT_END_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_TXFD_PKT_END_SPARE_U___S                        0

#define PHYA_TXFD_MAC_ABORT_RD_L                  (0x00391CA8)
#define   PHYA_TXFD_MAC_ABORT_RD_L___RWC            QCSR_REG_RO    
#define   PHYA_TXFD_MAC_ABORT_RD_L___POR         0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___POR 0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___M 0xFFFFFFFF
#define   PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___S               0
#define   PHYA_TXFD_MAC_ABORT_RD_L___M           0xFFFFFFFF   
#define   PHYA_TXFD_MAC_ABORT_RD_L___S                         0

#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L            (0x00391CB0)
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L___POR   0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___S               0
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L___M     0xFFFFFFFF   
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_L___S                   0

#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U            (0x00391CB4)
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U___POR   0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___S               0
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U___M     0xFFFFFFFF   
#define   PHYA_TXFD_MAC_ABORT_RD_SPARE_U___S                   0

#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L              (0x00391CB8)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L___POR     0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___M 0x000F0000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___S              16
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___M 0x00000F00
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___S               8
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___M 0x00000001
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L___M       0x000F0F01   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_L___S                     0

#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U              (0x00391CBC)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U___POR     0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___POR 0x00000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___M 0x0001FFFF
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U___M       0x0001FFFF   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_0_U___S                     0

#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L              (0x00391CC0)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L___POR     0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___M 0x01000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___S              24
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___M 0x00010000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___S              16
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___M 0x00000700
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___S               8
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___M 0x00000007
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L___M       0x01010707   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_L___S                     0

#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U              (0x00391CC4)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U___POR     0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___POR 0x00
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___POR 0x00
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___POR 0x0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___M 0x00FF0000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___S              16
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___M 0x0000FF00
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___S               8
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___M 0x00000003
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U___M       0x00FFFF03   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_1_U___S                     0

#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L          (0x00391CC8)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___S                 0

#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U          (0x00391CCC)
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___S               0
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___S                 0

#define PHYA_TXFD_HE_PARAMS_0_L                   (0x00391CD0)
#define   PHYA_TXFD_HE_PARAMS_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_HE_PARAMS_0_L___POR          0x00000000
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___M 0x01000000
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___S              24
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___M 0x00070000
#define   PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___S              16
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___M 0x00000300
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___S               8
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___M 0x00000001
#define   PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___S               0
#define   PHYA_TXFD_HE_PARAMS_0_L___M            0x01070301   
#define   PHYA_TXFD_HE_PARAMS_0_L___S                          0

#define PHYA_TXFD_HE_PARAMS_1_L                   (0x00391CD8)
#define   PHYA_TXFD_HE_PARAMS_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_HE_PARAMS_1_L___POR          0x00000000
#define   PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___POR  0x0
#define   PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___POR  0x0
#define   PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___M 0x03000000
#define   PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___S              24
#define   PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___M    0x00070000
#define   PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___S                 16
#define   PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___M    0x00000100
#define   PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___S                  8
#define   PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___M 0x0000000F
#define   PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___S               0
#define   PHYA_TXFD_HE_PARAMS_1_L___M            0x0307010F   
#define   PHYA_TXFD_HE_PARAMS_1_L___S                          0

#define PHYA_TXFD_HE_PARAMS_1_U                   (0x00391CDC)
#define   PHYA_TXFD_HE_PARAMS_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_HE_PARAMS_1_U___POR          0x00000000
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___M 0x00000100
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___S               8
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___M 0x00000003
#define   PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___S               0
#define   PHYA_TXFD_HE_PARAMS_1_U___M            0x00000103   
#define   PHYA_TXFD_HE_PARAMS_1_U___S                          0

#define PHYA_TXFD_HE_PARAMS_2_L                   (0x00391CE0)
#define   PHYA_TXFD_HE_PARAMS_2_L___RWC             QCSR_REG_RW    
#define   PHYA_TXFD_HE_PARAMS_2_L___POR          0x00000000
#define   PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___POR 0x0
#define   PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___M 0x0000000F
#define   PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___S               0
#define   PHYA_TXFD_HE_PARAMS_2_L___M            0x0000000F   
#define   PHYA_TXFD_HE_PARAMS_2_L___S                          0

#define PHYA_TXFD_POWER_NORM_CFG_L                (0x00391CE8)
#define   PHYA_TXFD_POWER_NORM_CFG_L___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_POWER_NORM_CFG_L___POR       0x01010001
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___POR 0x1
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___POR 0x1
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___POR 0x0
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___POR 0x1
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___M 0x01000000
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___S              24
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___M 0x00010000
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___S              16
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___M 0x00000100
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___S               8
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___M 0x00000001
#define   PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___S               0
#define   PHYA_TXFD_POWER_NORM_CFG_L___M         0x01010101   
#define   PHYA_TXFD_POWER_NORM_CFG_L___S                       0

#define PHYA_TXFD_POWER_NORM_CFG_U                (0x00391CEC)
#define   PHYA_TXFD_POWER_NORM_CFG_U___RWC          QCSR_REG_RW    
#define   PHYA_TXFD_POWER_NORM_CFG_U___POR       0x00000001
#define   PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___POR 0x1
#define   PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___M 0x00000001
#define   PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___S               0
#define   PHYA_TXFD_POWER_NORM_CFG_U___M         0x00000001   
#define   PHYA_TXFD_POWER_NORM_CFG_U___S                       0

#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L     (0x00391CF0)
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___S               0
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___S               0

#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U     (0x00391CF4)
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___S               0
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___S               0

#define PHYA_TXFD_SERVICE_TLV_MEM_L_n(n) (0x00391CF8+0x8*(n))
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n_nMIN 0    
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n_nMAX 0    
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n_ELEM 1    
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n___POR    0x00000000
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___POR 0x00000000
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___M 0xFFFFFFFF
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___S               0
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n___M      0xFFFFFFFF   
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_n___S                    0
#define PHYA_TXFD_SERVICE_TLV_MEM_L_0             (0x00391CF8)
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_0___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_0__SERVICE_TLV_MEM_0___M 0xFFFFFFFF
#define   PHYA_TXFD_SERVICE_TLV_MEM_L_0__SERVICE_TLV_MEM_0___S               0

#define PHYA_TXFD_SERVICE_TLV_MEM_U_n(n) (0x00391CFC+0x8*(n))
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n_nMIN 0    
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n_nMAX 0    
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n_ELEM 1    
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n___POR    0x00000000
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___POR 0x00000000
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___M 0xFFFFFFFF
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___S               0
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n___M      0xFFFFFFFF   
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_n___S                    0
#define PHYA_TXFD_SERVICE_TLV_MEM_U_0             (0x00391CFC)
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_0___RWC       QCSR_REG_RW    
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_0__SERVICE_TLV_MEM_1___M 0xFFFFFFFF
#define   PHYA_TXFD_SERVICE_TLV_MEM_U_0__SERVICE_TLV_MEM_1___S               0

#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L       (0x00391D20)
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___S               0
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___S               0

#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U       (0x00391D24)
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___S               0
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___S               0

#define PHYA_TXFD_USER_PARAMS_L_n(n)     (0x00391D28+0x8*(n))
#define   PHYA_TXFD_USER_PARAMS_L_n_nMIN 0    
#define   PHYA_TXFD_USER_PARAMS_L_n_nMAX 0    
#define   PHYA_TXFD_USER_PARAMS_L_n_ELEM 1    
#define   PHYA_TXFD_USER_PARAMS_L_n___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_USER_PARAMS_L_n___POR        0x00000000
#define   PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___POR 0x00000000
#define   PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___M 0xFFFFFFFF
#define   PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___S               0
#define   PHYA_TXFD_USER_PARAMS_L_n___M          0xFFFFFFFF   
#define   PHYA_TXFD_USER_PARAMS_L_n___S                        0
#define PHYA_TXFD_USER_PARAMS_L_0                 (0x00391D28)
#define   PHYA_TXFD_USER_PARAMS_L_0___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_USER_PARAMS_L_0__USER_PARAMS_0___M 0xFFFFFFFF
#define   PHYA_TXFD_USER_PARAMS_L_0__USER_PARAMS_0___S               0

#define PHYA_TXFD_USER_PARAMS_U_n(n)     (0x00391D2C+0x8*(n))
#define   PHYA_TXFD_USER_PARAMS_U_n_nMIN 0    
#define   PHYA_TXFD_USER_PARAMS_U_n_nMAX 0    
#define   PHYA_TXFD_USER_PARAMS_U_n_ELEM 1    
#define   PHYA_TXFD_USER_PARAMS_U_n___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_USER_PARAMS_U_n___POR        0x00000000
#define   PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___POR 0x00000000
#define   PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___M 0xFFFFFFFF
#define   PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___S               0
#define   PHYA_TXFD_USER_PARAMS_U_n___M          0xFFFFFFFF   
#define   PHYA_TXFD_USER_PARAMS_U_n___S                        0
#define PHYA_TXFD_USER_PARAMS_U_0                 (0x00391D2C)
#define   PHYA_TXFD_USER_PARAMS_U_0___RWC           QCSR_REG_RW    
#define   PHYA_TXFD_USER_PARAMS_U_0__USER_PARAMS_1___M 0xFFFFFFFF
#define   PHYA_TXFD_USER_PARAMS_U_0__USER_PARAMS_1___S               0

#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L      (0x00392128)
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___M 0x03FF0000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___S              16
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___M 0x000003FF
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___S               0
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___M 0x03FF03FF   
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U      (0x0039212C)
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___POR 0x00000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___M 0x03FF0000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___S              16
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___M 0x000003FF
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___S               0
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___M 0x03FF03FF   
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___S               0

#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L      (0x00392130)
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___POR 0x000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___M 0x03FF0000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___S              16
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___M 0x000003FF
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___S               0
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___M 0x03FF03FF   
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U      (0x00392134)
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___POR 0x00000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___M 0xFF000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___S              24
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___M 0x00FF0000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___S              16
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___M 0x0000FF00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___S               8
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___M 0x000000FF
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___S               0
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___M 0xFFFFFFFF   
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___S               0

#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L      (0x00392138)
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___POR 0x00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___M 0x0000FF00
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___S               8
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___M 0x000000FF
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___S               0
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___M 0x0000FFFF   
#define   PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L        (0x00392140)
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L        (0x00392148)
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L        (0x00392150)
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L        (0x00392158)
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L        (0x00392160)
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L        (0x00392168)
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L        (0x00392170)
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L        (0x00392178)
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L        (0x00392180)
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L        (0x00392188)
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L        (0x00392190)
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L        (0x00392198)
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L        (0x003921A0)
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L        (0x003921A8)
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L        (0x003921B0)
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L        (0x003921B8)
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L        (0x003921C0)
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L        (0x003921C8)
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L        (0x003921D0)
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L        (0x003921D8)
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L        (0x003921E0)
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L        (0x003921E8)
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L        (0x003921F0)
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L        (0x003921F8)
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L        (0x00392200)
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L        (0x00392208)
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L        (0x00392210)
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L        (0x00392218)
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L        (0x00392220)
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L        (0x00392228)
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L       (0x00392230)
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L       (0x00392238)
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L       (0x00392240)
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L       (0x00392248)
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L       (0x00392250)
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L       (0x00392258)
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L       (0x00392260)
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L       (0x00392268)
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L       (0x00392270)
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L       (0x00392278)
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L       (0x00392280)
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L       (0x00392288)
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L       (0x00392290)
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L       (0x00392298)
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L       (0x003922A0)
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L       (0x003922A8)
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L       (0x003922B0)
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L       (0x003922B8)
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L       (0x003922C0)
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L       (0x003922C8)
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L       (0x003922D0)
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L       (0x003922D8)
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L       (0x003922E0)
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L       (0x003922E8)
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L       (0x003922F0)
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L       (0x003922F8)
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L       (0x00392300)
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L       (0x00392308)
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L       (0x00392310)
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L       (0x00392318)
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L       (0x00392320)
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L       (0x00392328)
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L       (0x00392330)
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L       (0x00392338)
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L       (0x00392340)
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L       (0x00392348)
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L       (0x00392350)
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L       (0x00392358)
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L       (0x00392360)
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L       (0x00392368)
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L       (0x00392370)
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L       (0x00392378)
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L       (0x00392380)
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L       (0x00392388)
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L       (0x00392390)
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L       (0x00392398)
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L       (0x003923A0)
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L       (0x003923A8)
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L       (0x003923B0)
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L       (0x003923B8)
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L       (0x003923C0)
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L       (0x003923C8)
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L       (0x003923D0)
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L       (0x003923D8)
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L       (0x003923E0)
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L       (0x003923E8)
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L       (0x003923F0)
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L       (0x003923F8)
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L       (0x00392400)
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L       (0x00392408)
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L       (0x00392410)
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L       (0x00392418)
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L       (0x00392420)
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L       (0x00392428)
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L       (0x00392430)
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L       (0x00392438)
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L       (0x00392440)
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L       (0x00392448)
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L       (0x00392450)
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L       (0x00392458)
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L       (0x00392460)
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L       (0x00392468)
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L       (0x00392470)
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L       (0x00392478)
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L       (0x00392480)
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L       (0x00392488)
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L       (0x00392490)
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L       (0x00392498)
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L       (0x003924A0)
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L       (0x003924A8)
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L       (0x003924B0)
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L       (0x003924B8)
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L       (0x003924C0)
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L       (0x003924C8)
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L       (0x003924D0)
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L       (0x003924D8)
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L       (0x003924E0)
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L       (0x003924E8)
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L       (0x003924F0)
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L       (0x003924F8)
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L       (0x00392500)
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L       (0x00392508)
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L       (0x00392510)
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L       (0x00392518)
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L       (0x00392520)
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L       (0x00392528)
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L       (0x00392530)
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L       (0x00392538)
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L       (0x00392540)
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L       (0x00392548)
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L       (0x00392550)
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L       (0x00392558)
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L       (0x00392560)
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L       (0x00392568)
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L       (0x00392570)
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L       (0x00392578)
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L       (0x00392580)
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L       (0x00392588)
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L       (0x00392590)
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L       (0x00392598)
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L       (0x003925A0)
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L       (0x003925A8)
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L       (0x003925B0)
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L       (0x003925B8)
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L       (0x003925C0)
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L       (0x003925C8)
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L       (0x003925D0)
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L       (0x003925D8)
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L       (0x003925E0)
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L       (0x003925E8)
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L       (0x003925F0)
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L       (0x003925F8)
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L       (0x00392600)
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L       (0x00392608)
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L       (0x00392610)
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L       (0x00392618)
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L       (0x00392620)
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L       (0x00392628)
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L       (0x00392630)
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L       (0x00392638)
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L       (0x00392640)
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L       (0x00392648)
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L       (0x00392650)
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L       (0x00392658)
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L       (0x00392660)
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L       (0x00392668)
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L       (0x00392670)
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L       (0x00392678)
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L       (0x00392680)
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L       (0x00392688)
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L       (0x00392690)
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L       (0x00392698)
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L       (0x003926A0)
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L       (0x003926A8)
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L       (0x003926B0)
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L       (0x003926B8)
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L       (0x003926C0)
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L       (0x003926C8)
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L       (0x003926D0)
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L       (0x003926D8)
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L       (0x003926E0)
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L       (0x003926E8)
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L       (0x003926F0)
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L       (0x003926F8)
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L       (0x00392700)
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L       (0x00392708)
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L       (0x00392710)
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L       (0x00392718)
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L       (0x00392720)
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L       (0x00392728)
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L       (0x00392730)
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L       (0x00392738)
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L       (0x00392740)
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L       (0x00392748)
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L       (0x00392750)
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L       (0x00392758)
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L       (0x00392760)
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L       (0x00392768)
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L       (0x00392770)
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L       (0x00392778)
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L       (0x00392780)
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L       (0x00392788)
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L       (0x00392790)
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L       (0x00392798)
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L       (0x003927A0)
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L       (0x003927A8)
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L       (0x003927B0)
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L       (0x003927B8)
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L       (0x003927C0)
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L       (0x003927C8)
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L       (0x003927D0)
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L       (0x003927D8)
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L       (0x003927E0)
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L       (0x003927E8)
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L       (0x003927F0)
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L       (0x003927F8)
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L       (0x00392800)
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L       (0x00392808)
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L       (0x00392810)
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L       (0x00392818)
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___POR 0x0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___POR 0x0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___M 0x000F0000
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___S              16
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___M 0x00000300
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___S               8
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___M 0x00000007
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___S               0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___M 0x000F0307   
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___S               0

#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L       (0x00392820)
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___POR 0x0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___M 0x00000100
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___S               8
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___M 0x00000001
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___S               0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___M 0x00000101   
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___S               0

#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L       (0x00392828)
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___POR 0x00000000
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___POR 0x00
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___M 0x00003F00
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___S               8
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___M 0x0000003F
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___S               0
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___M 0x00003F3F   
#define   PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___S               0

#define PHYA_TXFD_USER_PARAM_CORR_WR_L            (0x00392830)
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L___RWC      QCSR_REG_RW    
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L___POR   0x00000000
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___POR 0x0000
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___M 0x0000FFFF
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___S               0
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L___M     0x0000FFFF   
#define   PHYA_TXFD_USER_PARAM_CORR_WR_L___S                   0

#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0        (0x00392838)
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___POR 0x00000000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___POR 0x0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___POR 0x00
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___POR 0x0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___M 0x00010000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___S              16
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___M 0x0000FF00
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___S               8
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___M 0x00000001
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___S               0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___M 0x0001FF01   
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___S               0

#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1        (0x003929B0)
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___POR 0x00000000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___POR 0x0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___POR 0x00
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___POR 0x0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___M 0x00010000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___S              16
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___M 0x0000FF00
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___S               8
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___M 0x00000001
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___S               0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___M 0x0001FF01   
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___S               0

#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0        (0x0039283C)
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___POR 0x00000000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___POR 0x0000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___M 0x00003FFF
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___S               0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___M 0x00003FFF   
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___S               0

#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1        (0x003929B4)
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___RWC  QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___POR 0x00000000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___POR 0x0000
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___M 0x00003FFF
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___S               0
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___M 0x00003FFF   
#define   PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___S               0

#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0           (0x00392960)
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___POR  0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___S               0
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___M    0xFFFFFFFF   
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___S                  0

#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1           (0x00392AD8)
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___POR  0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___S               0
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___M    0xFFFFFFFF   
#define   PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___S                  0

#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0           (0x00392964)
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___POR  0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___S               0
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___M    0xFFFFFFFF   
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___S                  0

#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1           (0x00392ADC)
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___POR  0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___S               0
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___M    0xFFFFFFFF   
#define   PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___S                  0

#define PHYA_TXFD_DUMMY_L                         (0x00397FF8)
#define   PHYA_TXFD_DUMMY_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXFD_DUMMY_L___POR                0x00000000
#define   PHYA_TXFD_DUMMY_L__DUMMY___POR         0x0
#define   PHYA_TXFD_DUMMY_L__DUMMY___M           0x00000001
#define   PHYA_TXFD_DUMMY_L__DUMMY___S                         0
#define   PHYA_TXFD_DUMMY_L___M                  0x00000001   
#define   PHYA_TXFD_DUMMY_L___S                                0

#define PHYA_RXTD_ECO_CONTROL_L                   (0x003A0000)
#define   PHYA_RXTD_ECO_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_ECO_CONTROL_L___POR          0x00000000
#define   PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___M  0xFFFFFFFF
#define   PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___S                0
#define   PHYA_RXTD_ECO_CONTROL_L___M            0xFFFFFFFF   
#define   PHYA_RXTD_ECO_CONTROL_L___S                          0

#define PHYA_RXTD_ECO_CONTROL_U                   (0x003A0004)
#define   PHYA_RXTD_ECO_CONTROL_U___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_ECO_CONTROL_U___POR          0x00000000
#define   PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000
#define   PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___M   0xFFFFFFFF
#define   PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___S                 0
#define   PHYA_RXTD_ECO_CONTROL_U___M            0xFFFFFFFF   
#define   PHYA_RXTD_ECO_CONTROL_U___S                          0

#define PHYA_RXTD_ECO_STATUS_L                    (0x003A0008)
#define   PHYA_RXTD_ECO_STATUS_L___RWC              QCSR_REG_RO    
#define   PHYA_RXTD_ECO_STATUS_L___POR           0x00000000
#define   PHYA_RXTD_ECO_STATUS_L__ECO_STAT___POR 0x00000000
#define   PHYA_RXTD_ECO_STATUS_L__ECO_STAT___M   0xFFFFFFFF
#define   PHYA_RXTD_ECO_STATUS_L__ECO_STAT___S                 0
#define   PHYA_RXTD_ECO_STATUS_L___M             0xFFFFFFFF   
#define   PHYA_RXTD_ECO_STATUS_L___S                           0

#define PHYA_RXTD_EVENT_STATUS_L                  (0x003A0010)
#define   PHYA_RXTD_EVENT_STATUS_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_EVENT_STATUS_L___POR         0x00000000
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___POR 0x0
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___M 0x00800000
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___S              23
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___M 0x00400000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___S              22
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___M 0x00200000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___S              21
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___M 0x00100000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___S              20
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___M 0x00080000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___S              19
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___M 0x00040000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___S              18
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___M 0x00020000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___S              17
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___M 0x00010000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___S              16
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___M 0x00008000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___S              15
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___M 0x00004000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___S              14
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___M 0x00002000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___S              13
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___M 0x00001000
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___S              12
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___M 0x00000800
#define   PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___S              11
#define   PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___M 0x00000400
#define   PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___S              10
#define   PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___M 0x00000200
#define   PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___S               9
#define   PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___M 0x00000100
#define   PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___S               8
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___M 0x00000080
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___S               7
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___M 0x00000040
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___S               6
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___M 0x00000020
#define   PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___S               5
#define   PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___M 0x00000010
#define   PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___S               4
#define   PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___M 0x00000008
#define   PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___S               3
#define   PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___M 0x00000004
#define   PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___S               2
#define   PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___M 0x00000002
#define   PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___S               1
#define   PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___M 0x00000001
#define   PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___S               0
#define   PHYA_RXTD_EVENT_STATUS_L___M           0x00FFFFFF   
#define   PHYA_RXTD_EVENT_STATUS_L___S                         0

#define PHYA_RXTD_EVENT_MASK_L                    (0x003A0018)
#define   PHYA_RXTD_EVENT_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_EVENT_MASK_L___POR           0x00FFFFFF
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___POR 0x1
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___M 0x00800000
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___S              23
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___M 0x00400000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___S              22
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___M 0x00200000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___S              21
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___M 0x00100000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___S              20
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___M 0x00080000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___S              19
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___M 0x00040000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___S              18
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___M 0x00020000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___S              17
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___M 0x00010000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___S              16
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___M 0x00008000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___S              15
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___M 0x00004000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___S              14
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___M 0x00002000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___S              13
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___M 0x00001000
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___S              12
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___M 0x00000800
#define   PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___S              11
#define   PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___M 0x00000400
#define   PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___S              10
#define   PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___M 0x00000200
#define   PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___S               9
#define   PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___M 0x00000100
#define   PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___S               8
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___M 0x00000080
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___S               7
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___M 0x00000040
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___S               6
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___M 0x00000020
#define   PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___S               5
#define   PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___M 0x00000010
#define   PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___S               4
#define   PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___M 0x00000008
#define   PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___S               3
#define   PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000004
#define   PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___S               2
#define   PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___M 0x00000002
#define   PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___S               1
#define   PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___S               0
#define   PHYA_RXTD_EVENT_MASK_L___M             0x00FFFFFF   
#define   PHYA_RXTD_EVENT_MASK_L___S                           0

#define PHYA_RXTD_ERROR_CODE_L                    (0x003A0020)
#define   PHYA_RXTD_ERROR_CODE_L___RWC              QCSR_REG_RO    
#define   PHYA_RXTD_ERROR_CODE_L___POR           0x00000000
#define   PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___POR 0x00
#define   PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___M 0x000000FF
#define   PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_RXTD_ERROR_CODE_L___M             0x000000FF   
#define   PHYA_RXTD_ERROR_CODE_L___S                           0

#define PHYA_RXTD_ERROR_STATUS_L                  (0x003A0028)
#define   PHYA_RXTD_ERROR_STATUS_L___RWC            QCSR_REG_RO    
#define   PHYA_RXTD_ERROR_STATUS_L___POR         0x00000000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___POR 0x0
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___M 0x00800000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___S              23
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___M 0x00400000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___S              22
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___M 0x00200000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___S              21
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___M 0x00100000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___S              20
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___M 0x00080000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___S              19
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___M 0x00040000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___S              18
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___M 0x00020000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___S              17
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___M 0x00010000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___S              16
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___M 0x00008000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___S              15
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___M 0x00004000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___S              14
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___M 0x00002000
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___S              13
#define   PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___M 0x00001000
#define   PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___S              12
#define   PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___M 0x00000800
#define   PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___S              11
#define   PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___M 0x00000400
#define   PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___S              10
#define   PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___M 0x00000200
#define   PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___S               9
#define   PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___M 0x00000100
#define   PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___S               8
#define   PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___M 0x00000080
#define   PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___S               7
#define   PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___M 0x00000040
#define   PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___S               6
#define   PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___M 0x00000020
#define   PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___S               5
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___M 0x00000010
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___S               4
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___M 0x00000008
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___S               3
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___M 0x00000004
#define   PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___S               2
#define   PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___M 0x00000002
#define   PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___S               1
#define   PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___M 0x00000001
#define   PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___S               0
#define   PHYA_RXTD_ERROR_STATUS_L___M           0x00FFFFFF   
#define   PHYA_RXTD_ERROR_STATUS_L___S                         0

#define PHYA_RXTD_ERROR_MASK_L                    (0x003A0030)
#define   PHYA_RXTD_ERROR_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_ERROR_MASK_L___POR           0x00000000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RTT_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___M 0x00800000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___S              23
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___M 0x00400000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___S              22
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___M 0x00200000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___S              21
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___M 0x00100000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___S              20
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___M 0x00080000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___S              19
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___M 0x00040000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___S              18
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___M 0x00020000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___S              17
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___M 0x00010000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___S              16
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___M 0x00008000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___S              15
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___M 0x00004000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___S              14
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___M 0x00002000
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___S              13
#define   PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___M 0x00001000
#define   PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___S              12
#define   PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___M 0x00000800
#define   PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___S              11
#define   PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___M 0x00000400
#define   PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___S              10
#define   PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___M 0x00000200
#define   PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___S               9
#define   PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___M 0x00000100
#define   PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___S               8
#define   PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___M 0x00000080
#define   PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___S               7
#define   PHYA_RXTD_ERROR_MASK_L__RTT_MASK___M   0x00000040
#define   PHYA_RXTD_ERROR_MASK_L__RTT_MASK___S                 6
#define   PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___M 0x00000020
#define   PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___S               5
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___M 0x00000010
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___S               4
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___M 0x00000008
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___S               3
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___M 0x00000004
#define   PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___S               2
#define   PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___M 0x00000002
#define   PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___S               1
#define   PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___M 0x00000001
#define   PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___S               0
#define   PHYA_RXTD_ERROR_MASK_L___M             0x00FFFFFF   
#define   PHYA_RXTD_ERROR_MASK_L___S                           0

#define PHYA_RXTD_GEN_CONFIG_L                    (0x003A0038)
#define   PHYA_RXTD_GEN_CONFIG_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GEN_CONFIG_L___POR           0x00000100
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___POR 0x0
#define   PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___POR 0x0
#define   PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___POR 0x1
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___POR 0x0
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___M 0x01000000
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___S              24
#define   PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___M 0x00010000
#define   PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___S              16
#define   PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___M 0x00000100
#define   PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___S               8
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___M 0x00000001
#define   PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___S               0
#define   PHYA_RXTD_GEN_CONFIG_L___M             0x01010101   
#define   PHYA_RXTD_GEN_CONFIG_L___S                           0

#define PHYA_RXTD_GEN_CONTROLS_L                  (0x003A0040)
#define   PHYA_RXTD_GEN_CONTROLS_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_GEN_CONTROLS_L___POR         0x00000000
#define   PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___POR 0x0
#define   PHYA_RXTD_GEN_CONTROLS_L__DEFER___POR  0x0
#define   PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___POR 0x0
#define   PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___M 0x00000004
#define   PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___S               2
#define   PHYA_RXTD_GEN_CONTROLS_L__DEFER___M    0x00000002
#define   PHYA_RXTD_GEN_CONTROLS_L__DEFER___S                  1
#define   PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___M 0x00000001
#define   PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___S               0
#define   PHYA_RXTD_GEN_CONTROLS_L___M           0x00000007   
#define   PHYA_RXTD_GEN_CONTROLS_L___S                         0

#define PHYA_RXTD_MIXER_CONFIG_L                  (0x003A0048)
#define   PHYA_RXTD_MIXER_CONFIG_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_MIXER_CONFIG_L___POR         0x00000004
#define   PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___POR 0x1
#define   PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___POR 0x0
#define   PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___M 0x00000004
#define   PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___S               2
#define   PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___M 0x00000003
#define   PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___S               0
#define   PHYA_RXTD_MIXER_CONFIG_L___M           0x00000007   
#define   PHYA_RXTD_MIXER_CONFIG_L___S                         0

#define PHYA_RXTD_PDBWC_WEAK_LOW_L                (0x003A0050)
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L___POR       0x00000254
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___POR 0x01
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___POR 0x05
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___POR 0x4
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___M 0x00003E00
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___S               9
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___M 0x000001F0
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___S               4
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___M 0x0000000F
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___S               0
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L___M         0x00003FFF   
#define   PHYA_RXTD_PDBWC_WEAK_LOW_L___S                       0

#define PHYA_RXTD_PDBWC_WEAK_L                    (0x003A0058)
#define   PHYA_RXTD_PDBWC_WEAK_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_PDBWC_WEAK_L___POR           0x00000258
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___POR 0x01
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___POR 0x05
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___POR 0x8
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___M 0x00003E00
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___S               9
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___M 0x000001F0
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___S               4
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___M 0x0000000F
#define   PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___S               0
#define   PHYA_RXTD_PDBWC_WEAK_L___M             0x00003FFF   
#define   PHYA_RXTD_PDBWC_WEAK_L___S                           0

#define PHYA_RXTD_PDBWC_STRONG_L                  (0x003A0060)
#define   PHYA_RXTD_PDBWC_STRONG_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_PDBWC_STRONG_L___POR         0x00000258
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___POR 0x01
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___POR 0x05
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___POR 0x8
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___M 0x00003E00
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___S               9
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___M 0x000001F0
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___S               4
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___M 0x0000000F
#define   PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___S               0
#define   PHYA_RXTD_PDBWC_STRONG_L___M           0x00003FFF   
#define   PHYA_RXTD_PDBWC_STRONG_L___S                         0

#define PHYA_RXTD_PDBWC_L                         (0x003A0068)
#define   PHYA_RXTD_PDBWC_L___RWC                   QCSR_REG_RW    
#define   PHYA_RXTD_PDBWC_L___POR                0x00000001
#define   PHYA_RXTD_PDBWC_L__PD_WIN_LEN___POR    0x01
#define   PHYA_RXTD_PDBWC_L__PD_WIN_LEN___M      0x0000001F
#define   PHYA_RXTD_PDBWC_L__PD_WIN_LEN___S                    0
#define   PHYA_RXTD_PDBWC_L___M                  0x0000001F   
#define   PHYA_RXTD_PDBWC_L___S                                0

#define PHYA_RXTD_LEAKYB_CTRL_L                   (0x003A0070)
#define   PHYA_RXTD_LEAKYB_CTRL_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_LEAKYB_CTRL_L___POR          0x01C3FFFF
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___POR 0x07
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___POR 0x01FFFF
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___POR   0x1
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___M 0x07C00000
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___S              22
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___M 0x003FFFFE
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___S               1
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___M     0x00000001
#define   PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___S                   0
#define   PHYA_RXTD_LEAKYB_CTRL_L___M            0x07FFFFFF   
#define   PHYA_RXTD_LEAKYB_CTRL_L___S                          0

#define PHYA_RXTD_ADCPWR_ADJ_1_L                  (0x003A0078)
#define   PHYA_RXTD_ADCPWR_ADJ_1_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_ADCPWR_ADJ_1_L___POR         0x00014014
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___POR 0x014
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___POR 0x014
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___M 0x00FFF000
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___S              12
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___M 0x00000FFF
#define   PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___S               0
#define   PHYA_RXTD_ADCPWR_ADJ_1_L___M           0x00FFFFFF   
#define   PHYA_RXTD_ADCPWR_ADJ_1_L___S                         0

#define PHYA_RXTD_ADCPWR_ADJ_2_L                  (0x003A0080)
#define   PHYA_RXTD_ADCPWR_ADJ_2_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_ADCPWR_ADJ_2_L___POR         0x00000014
#define   PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___POR 0x014
#define   PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___M 0x00000FFF
#define   PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___S               0
#define   PHYA_RXTD_ADCPWR_ADJ_2_L___M           0x00000FFF   
#define   PHYA_RXTD_ADCPWR_ADJ_2_L___S                         0

#define PHYA_RXTD_PRI20PWR_ADJ_0_L                (0x003A0088)
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L___POR       0x00000000
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___POR 0x000
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___POR 0x000
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___M 0x00FFF000
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___S              12
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___M 0x00000FFF
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___S               0
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L___M         0x00FFFFFF   
#define   PHYA_RXTD_PRI20PWR_ADJ_0_L___S                       0

#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L           (0x003A0090)
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___POR  0x00000000
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___POR 0x000
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___M 0x00000FFF
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___S               0
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___M    0x00000FFF   
#define   PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___S                  0

#define PHYA_RXTD_CCA_PWR_ADJ_L                   (0x003A0098)
#define   PHYA_RXTD_CCA_PWR_ADJ_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_CCA_PWR_ADJ_L___POR          0x00000000
#define   PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___POR 0x000
#define   PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___M 0x00000FFF
#define   PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___S               0
#define   PHYA_RXTD_CCA_PWR_ADJ_L___M            0x00000FFF   
#define   PHYA_RXTD_CCA_PWR_ADJ_L___S                          0

#define PHYA_RXTD_PKDET_KRELPWR_L                 (0x003A00A0)
#define   PHYA_RXTD_PKDET_KRELPWR_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_PKDET_KRELPWR_L___POR        0x0763B1EC
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___POR 0x1D8
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___POR 0x1D8
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___POR 0x1EC
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___M 0x07FC0000
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___S              18
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___M 0x0003FE00
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___S               9
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___M 0x000001FF
#define   PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___S               0
#define   PHYA_RXTD_PKDET_KRELPWR_L___M          0x07FFFFFF   
#define   PHYA_RXTD_PKDET_KRELPWR_L___S                        0

#define PHYA_RXTD_PKDET_KPRIPWR_L                 (0x003A00A8)
#define   PHYA_RXTD_PKDET_KPRIPWR_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_PKDET_KPRIPWR_L___POR        0x0673259C
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___POR 0x19C
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___POR 0x192
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___POR 0x19C
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___M 0x07FC0000
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___S              18
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___M 0x0003FE00
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___S               9
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___M 0x000001FF
#define   PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___S               0
#define   PHYA_RXTD_PKDET_KPRIPWR_L___M          0x07FFFFFF   
#define   PHYA_RXTD_PKDET_KPRIPWR_L___S                        0

#define PHYA_RXTD_PKDET_KRELSTEP_L                (0x003A00B0)
#define   PHYA_RXTD_PKDET_KRELSTEP_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_PKDET_KRELSTEP_L___POR       0x0003399C
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___POR 0x19C
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___POR 0x19C
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___M 0x0003FE00
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___S               9
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___M 0x000001FF
#define   PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___S               0
#define   PHYA_RXTD_PKDET_KRELSTEP_L___M         0x0003FFFF   
#define   PHYA_RXTD_PKDET_KRELSTEP_L___S                       0

#define PHYA_RXTD_PKDET_KPRISTEP_L                (0x003A00B8)
#define   PHYA_RXTD_PKDET_KPRISTEP_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_PKDET_KPRISTEP_L___POR       0x00033805
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___POR 0x19C
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___POR 0x005
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___M 0x0003FE00
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___S               9
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___M 0x000001FF
#define   PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___S               0
#define   PHYA_RXTD_PKDET_KPRISTEP_L___M         0x0003FFFF   
#define   PHYA_RXTD_PKDET_KPRISTEP_L___S                       0

#define PHYA_RXTD_PKDET_PARAMS_L                  (0x003A00C0)
#define   PHYA_RXTD_PKDET_PARAMS_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_PKDET_PARAMS_L___POR         0x12020020
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___POR 0x2
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___POR 0x2
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___POR 0x020
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___POR 0x020
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___M 0x38000000
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___S              27
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___M  0x07000000
#define   PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___S               24
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___M 0x00FFF000
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___S              12
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___M 0x00000FFF
#define   PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___S               0
#define   PHYA_RXTD_PKDET_PARAMS_L___M           0x3FFFFFFF   
#define   PHYA_RXTD_PKDET_PARAMS_L___S                         0

#define PHYA_RXTD_RSSI_THR_L                      (0x003A00C8)
#define   PHYA_RXTD_RSSI_THR_L___RWC                QCSR_REG_RW    
#define   PHYA_RXTD_RSSI_THR_L___POR             0x12880AB1
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___POR 0x12
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___POR 0x88
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___POR 0x0A
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___POR 0xB1
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___M 0xFF000000
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___S              24
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___M 0x00FF0000
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___S              16
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___M 0x0000FF00
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___S               8
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___M 0x000000FF
#define   PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___S               0
#define   PHYA_RXTD_RSSI_THR_L___M               0xFFFFFFFF   
#define   PHYA_RXTD_RSSI_THR_L___S                             0

#define PHYA_RXTD_RSSI_THR_U                      (0x003A00CC)
#define   PHYA_RXTD_RSSI_THR_U___RWC                QCSR_REG_RW    
#define   PHYA_RXTD_RSSI_THR_U___POR             0x0000000F
#define   PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___POR 0x1
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___POR 0x1
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___POR 0x1
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___POR 0x1
#define   PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___M 0x00000008
#define   PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___S               3
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___M 0x00000004
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___S               2
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___M 0x00000002
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___S               1
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___M 0x00000001
#define   PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___S               0
#define   PHYA_RXTD_RSSI_THR_U___M               0x0000000F   
#define   PHYA_RXTD_RSSI_THR_U___S                             0

#define PHYA_RXTD_TIMESTAMP_L                     (0x003A00D0)
#define   PHYA_RXTD_TIMESTAMP_L___RWC               QCSR_REG_RW    
#define   PHYA_RXTD_TIMESTAMP_L___POR            0x00000000
#define   PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___POR 0x00000000
#define   PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___POR 0x0
#define   PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___POR 0x0
#define   PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___M  0xFFFFFFFC
#define   PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___S                2
#define   PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___M 0x00000002
#define   PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___S               1
#define   PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___M 0x00000001
#define   PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___S               0
#define   PHYA_RXTD_TIMESTAMP_L___M              0xFFFFFFFF   
#define   PHYA_RXTD_TIMESTAMP_L___S                            0

#define PHYA_RXTD_RADAR_SBS_CTRL_0_L              (0x003A00D8)
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L___POR     0x00000000
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___M 0x00000008
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___S               3
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___M 0x00000004
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___S               2
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___M 0x00000002
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___S               1
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___M 0x00000001
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___S               0
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L___M       0x0000000F   
#define   PHYA_RXTD_RADAR_SBS_CTRL_0_L___S                     0

#define PHYA_RXTD_RADAR_SBS_CTRL_1_L              (0x003A00E0)
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L___POR     0x0007E013
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___POR 0x00
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___POR 0x3F
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___POR 0x00
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___POR 0x1
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___POR 0x1
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___POR 0x1
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___M 0x1FE00000
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___S              21
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___M 0x001FE000
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___S              13
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___M 0x00001FE0
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___S               5
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___M 0x00000010
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___S               4
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___M 0x0000000C
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___S               2
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___M 0x00000002
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___S               1
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___M 0x00000001
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___S               0
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L___M       0x1FFFFFFF   
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_L___S                     0

#define PHYA_RXTD_RADAR_SBS_CTRL_1_U              (0x003A00E4)
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U___POR     0x003F003F
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___POR 0x00
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___POR 0x3F
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___POR 0x00
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___POR 0x3F
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___M 0xFF000000
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___S              24
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___M 0x00FF0000
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___S              16
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___M 0x0000FF00
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___S               8
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___M 0x000000FF
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___S               0
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U___M       0xFFFFFFFF   
#define   PHYA_RXTD_RADAR_SBS_CTRL_1_U___S                     0

#define PHYA_RXTD_RADAR_SBS_CTRL_2_L              (0x003A00E8)
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L___POR     0x009C402A
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___POR 0x0
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___POR 0x09C40
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___POR 0x2A
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___M 0xC0000000
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___S              30
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___M 0x30000000
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___S              28
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___M 0x0FFFFF00
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___S               8
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___M 0x000000FF
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___S               0
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L___M       0xFFFFFFFF   
#define   PHYA_RXTD_RADAR_SBS_CTRL_2_L___S                     0

#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L             (0x003A00F0)
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L___POR    0x01800800
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___POR 0x1
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___POR 0x800
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___POR 0x800
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___M 0x01000000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___S              24
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___M 0x00FFF000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___S              12
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___M 0x00000FFF
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___S               0
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L___M      0x01FFFFFF   
#define   PHYA_RXTD_HT_STF_AGC_CTRL_1_L___S                    0

#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L             (0x003A00F8)
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L___POR    0x01000000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___POR 0x1
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___POR 0x000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___POR 0x000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___M 0x01000000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___S              24
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___M 0x00FFF000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___S              12
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___M 0x00000FFF
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___S               0
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L___M      0x01FFFFFF   
#define   PHYA_RXTD_HT_STF_AGC_CTRL_2_L___S                    0

#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L             (0x003A0100)
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L___POR    0xDA0005E4
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___POR 0xDA
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___POR 0x0005
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___POR 0xE4
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___M 0xFF000000
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___S              24
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___M 0x00FFFF00
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___S               8
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___M 0x000000FF
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___S               0
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L___M      0xFFFFFFFF   
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_L___S                    0

#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U             (0x003A0104)
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U___POR    0x000000DA
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___POR 0xDA
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___M 0x000000FF
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___S               0
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U___M      0x000000FF   
#define   PHYA_RXTD_HT_STF_AGC_CTRL_3_U___S                    0

#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L            (0x003A0108)
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___POR   0x00000000
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___POR 0x0
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___POR 0x0
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___POR 0x00
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___POR 0x0
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___M 0x00000200
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___S               9
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___M 0x00000100
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___S               8
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___M 0x000000FE
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___S               1
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___M 0x00000001
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___S               0
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___M     0x000003FF   
#define   PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___S                   0

#define PHYA_RXTD_AGC_CCA_DUP_L                   (0x003A0110)
#define   PHYA_RXTD_AGC_CCA_DUP_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_DUP_L___POR          0x05208208
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___POR 0x05
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___M 0x3F000000
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___S              24
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___M 0x00FC0000
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___S              18
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___M 0x0003F000
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___S              12
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___M 0x00000FC0
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___S               6
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___M 0x0000003F
#define   PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___S               0
#define   PHYA_RXTD_AGC_CCA_DUP_L___M            0x3FFFFFFF   
#define   PHYA_RXTD_AGC_CCA_DUP_L___S                          0

#define PHYA_RXTD_AGC_CCA_DUP_U                   (0x003A0114)
#define   PHYA_RXTD_AGC_CCA_DUP_U___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_DUP_U___POR          0x00000208
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___POR 0x08
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___M 0x00000FC0
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___S               6
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___M 0x0000003F
#define   PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___S               0
#define   PHYA_RXTD_AGC_CCA_DUP_U___M            0x00000FFF   
#define   PHYA_RXTD_AGC_CCA_DUP_U___S                          0

#define PHYA_RXTD_AGC_CCA_THRA_L                  (0x003A0118)
#define   PHYA_RXTD_AGC_CCA_THRA_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_THRA_L___POR         0x0C0C0C0C
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___M 0xFF000000
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___S              24
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___M 0x00FF0000
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___S              16
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___M 0x0000FF00
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___S               8
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___S               0
#define   PHYA_RXTD_AGC_CCA_THRA_L___M           0xFFFFFFFF   
#define   PHYA_RXTD_AGC_CCA_THRA_L___S                         0

#define PHYA_RXTD_AGC_CCA_THRB_L                  (0x003A0120)
#define   PHYA_RXTD_AGC_CCA_THRB_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_THRB_L___POR         0x0C0C0C0C
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___M 0xFF000000
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___S              24
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___M 0x00FF0000
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___S              16
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___M 0x0000FF00
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___S               8
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___S               0
#define   PHYA_RXTD_AGC_CCA_THRB_L___M           0xFFFFFFFF   
#define   PHYA_RXTD_AGC_CCA_THRB_L___S                         0

#define PHYA_RXTD_AGC_CCA_THRC_L                  (0x003A0128)
#define   PHYA_RXTD_AGC_CCA_THRC_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_THRC_L___POR         0x0C0C0C0C
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___POR 0x0C
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___M 0xFF000000
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___S              24
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___M 0x00FF0000
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___S              16
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___M 0x0000FF00
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___S               8
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___S               0
#define   PHYA_RXTD_AGC_CCA_THRC_L___M           0xFFFFFFFF   
#define   PHYA_RXTD_AGC_CCA_THRC_L___S                         0

#define PHYA_RXTD_AGC_CCA_CONFIG_L                (0x003A0130)
#define   PHYA_RXTD_AGC_CCA_CONFIG_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_CONFIG_L___POR       0x0BFFF802
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___POR 0x1
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___POR 0x0
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___POR 0x1
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___POR 0x3
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___POR 0x3F
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___POR 0x3F
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___POR 0x000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___POR 0x1
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___POR 0x0
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___M 0x08000000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___S              27
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___M 0x04000000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___S              26
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___M 0x02000000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___S              25
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___M 0x01800000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___S              23
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___M 0x007E0000
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___S              17
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___M 0x0001F800
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___S              11
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___M 0x000007FC
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___S               2
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___M 0x00000002
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___S               1
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___M 0x00000001
#define   PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___S               0
#define   PHYA_RXTD_AGC_CCA_CONFIG_L___M         0x0FFFFFFF   
#define   PHYA_RXTD_AGC_CCA_CONFIG_L___S                       0

#define PHYA_RXTD_CCA_RXFRAME_FORCE_L             (0x003A0138)
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L___POR    0x000000FF
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___POR 0x00
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___POR 0xFF
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___M 0x0000FF00
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___S               8
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___M 0x000000FF
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___S               0
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L___M      0x0000FFFF   
#define   PHYA_RXTD_CCA_RXFRAME_FORCE_L___S                    0

#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L           (0x003A0140)
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___POR  0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___POR 0xFF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___S               0
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___M    0x000000FF   
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___S                  0

#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L           (0x003A0148)
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___POR  0x00000000
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___POR 0x00
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___S               0
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___M    0x000000FF   
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___S                  0

#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L           (0x003A0150)
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___POR  0x00000000
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___POR 0x00
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___S               0
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___M    0x000000FF   
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___S                  0

#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L           (0x003A0158)
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___POR  0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___POR 0xFF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___M 0x000000FF
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___S               0
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___M    0x000000FF   
#define   PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___S                  0

#define PHYA_RXTD_RSSI_CONFIG_L                   (0x003A0160)
#define   PHYA_RXTD_RSSI_CONFIG_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_RSSI_CONFIG_L___POR          0x00000000
#define   PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___POR 0x000
#define   PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___POR 0x0
#define   PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___M 0x01FF0000
#define   PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___S              16
#define   PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___M 0x00000003
#define   PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___S               0
#define   PHYA_RXTD_RSSI_CONFIG_L___M            0x01FF0003   
#define   PHYA_RXTD_RSSI_CONFIG_L___S                          0

#define PHYA_RXTD_RSSI_CONFIG_U                   (0x003A0164)
#define   PHYA_RXTD_RSSI_CONFIG_U___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_RSSI_CONFIG_U___POR          0x00000000
#define   PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___POR 0x00
#define   PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___M 0x000000FF
#define   PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___S               0
#define   PHYA_RXTD_RSSI_CONFIG_U___M            0x000000FF   
#define   PHYA_RXTD_RSSI_CONFIG_U___S                          0

#define PHYA_RXTD_CCA_FORCE_L                     (0x003A0168)
#define   PHYA_RXTD_CCA_FORCE_L___RWC               QCSR_REG_RW    
#define   PHYA_RXTD_CCA_FORCE_L___POR            0xFFFF0000
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___POR 0xFF
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___POR 0xFF
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___POR 0x0
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___POR 0x0
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___M 0xFF000000
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___S              24
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___M 0x00FF0000
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___S              16
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___M 0x00000100
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___S               8
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___M 0x00000001
#define   PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___S               0
#define   PHYA_RXTD_CCA_FORCE_L___M              0xFFFF0101   
#define   PHYA_RXTD_CCA_FORCE_L___S                            0

#define PHYA_RXTD_CCA_FORCE_U                     (0x003A016C)
#define   PHYA_RXTD_CCA_FORCE_U___RWC               QCSR_REG_RW    
#define   PHYA_RXTD_CCA_FORCE_U___POR            0x00FFFFFF
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___POR 0xFF
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___POR 0xFF
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___POR 0xFF
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___M 0x00FF0000
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___S              16
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___M 0x0000FF00
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___S               8
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___M 0x000000FF
#define   PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___S               0
#define   PHYA_RXTD_CCA_FORCE_U___M              0x00FFFFFF   
#define   PHYA_RXTD_CCA_FORCE_U___S                            0

#define PHYA_RXTD_GAIN_RATIO_CONFIG_L             (0x003A0170)
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L___POR    0x000001BB
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___POR 0x0
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___POR 0x1
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___POR 0xBB
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___M 0x00000200
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___S               9
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___M 0x00000100
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___S               8
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___M 0x000000FF
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___S               0
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L___M      0x000003FF   
#define   PHYA_RXTD_GAIN_RATIO_CONFIG_L___S                    0

#define PHYA_RXTD_AGC_NFCAL_PHY0_L                (0x003A0178)
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L___POR       0xE0A60003
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___POR 0xE0
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___POR 0xA6
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___POR 0x0
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___POR 0x3
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___M 0xFF000000
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___S              24
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___M 0x00FF0000
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___S              16
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___M 0x00000100
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___S               8
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___M 0x0000000F
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___S               0
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L___M         0xFFFF010F   
#define   PHYA_RXTD_AGC_NFCAL_PHY0_L___S                       0

#define PHYA_RXTD_VSRC_CONFIG_L                   (0x003A0180)
#define   PHYA_RXTD_VSRC_CONFIG_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_VSRC_CONFIG_L___POR          0x00000002
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___POR 0x0
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___POR 0x02
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___M 0x00000020
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___S               5
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___M 0x0000001F
#define   PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___S               0
#define   PHYA_RXTD_VSRC_CONFIG_L___M            0x0000003F   
#define   PHYA_RXTD_VSRC_CONFIG_L___S                          0

#define PHYA_RXTD_VSRC_CONFIG_U                   (0x003A0184)
#define   PHYA_RXTD_VSRC_CONFIG_U___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_VSRC_CONFIG_U___POR          0x00000000
#define   PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___POR 0x00000000
#define   PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___M 0xFFFFFFFF
#define   PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___S               0
#define   PHYA_RXTD_VSRC_CONFIG_U___M            0xFFFFFFFF   
#define   PHYA_RXTD_VSRC_CONFIG_U___S                          0

#define PHYA_RXTD_NOTCH_CNTL_1_L                  (0x003A0188)
#define   PHYA_RXTD_NOTCH_CNTL_1_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_NOTCH_CNTL_1_L___POR         0x12200C91
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___POR 0x4
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___POR 0x4
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___POR 0x0
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___POR 0x200
#define   PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___POR 0x1
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___POR 0x4
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___POR 0x4
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___POR 0x4
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___POR 0x0
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___POR 0x1
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___M 0x1C000000
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___S              26
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___M 0x03800000
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___S              23
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___M 0x00400000
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___S              22
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___M 0x003FF000
#define   PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___S              12
#define   PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___M 0x00000800
#define   PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___S              11
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___M 0x00000700
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___S               8
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___M 0x000000E0
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___S               5
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___M 0x0000001C
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___S               2
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___M 0x00000002
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___S               1
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___M 0x00000001
#define   PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___S               0
#define   PHYA_RXTD_NOTCH_CNTL_1_L___M           0x1FFFFFFF   
#define   PHYA_RXTD_NOTCH_CNTL_1_L___S                         0

#define PHYA_RXTD_CTE_CONFIG_1_0_L                (0x003A0190)
#define   PHYA_RXTD_CTE_CONFIG_1_0_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_CTE_CONFIG_1_0_L___POR       0x00499BE1
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___POR 0x4
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___POR 0x266
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___POR 0x3E1
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___M 0x00700000
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___S              20
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___M 0x000FFC00
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___S              10
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___M 0x000003FF
#define   PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___S               0
#define   PHYA_RXTD_CTE_CONFIG_1_0_L___M         0x007FFFFF   
#define   PHYA_RXTD_CTE_CONFIG_1_0_L___S                       0

#define PHYA_RXTD_CTE_CONFIG_1_0_U                (0x003A0194)
#define   PHYA_RXTD_CTE_CONFIG_1_0_U___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_CTE_CONFIG_1_0_U___POR       0x7C299BE1
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___POR 0x3E1
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___POR 0x0
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___POR 0x266
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___POR 0x3E1
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___M 0x7FE00000
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___S              21
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___M 0x00100000
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___S              20
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___M 0x000FFC00
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___S              10
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___M 0x000003FF
#define   PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___S               0
#define   PHYA_RXTD_CTE_CONFIG_1_0_U___M         0x7FFFFFFF   
#define   PHYA_RXTD_CTE_CONFIG_1_0_U___S                       0

#define PHYA_RXTD_CTE_CONFIG_1_1_L                (0x003A0198)
#define   PHYA_RXTD_CTE_CONFIG_1_1_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_CTE_CONFIG_1_1_L___POR       0x00000266
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___POR 0x0
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___POR 0x266
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___M 0x00000400
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___S              10
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___M 0x000003FF
#define   PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___S               0
#define   PHYA_RXTD_CTE_CONFIG_1_1_L___M         0x000007FF   
#define   PHYA_RXTD_CTE_CONFIG_1_1_L___S                       0

#define PHYA_RXTD_BTCF_CONFIG_1_L                 (0x003A01A0)
#define   PHYA_RXTD_BTCF_CONFIG_1_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_1_L___POR        0x03C29FA3
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___POR 0x1E
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___POR 0x14
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___POR 0xFD1
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___POR 0x1
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___M 0x1FE00000
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___S              21
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___M 0x001FE000
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___S              13
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___M 0x00001FFE
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___S               1
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___M 0x00000001
#define   PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___S               0
#define   PHYA_RXTD_BTCF_CONFIG_1_L___M          0x1FFFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_1_L___S                        0

#define PHYA_RXTD_BTCF_CONFIG_1_U                 (0x003A01A4)
#define   PHYA_RXTD_BTCF_CONFIG_1_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_1_U___POR        0x00060708
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___POR 0x06
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___POR 0x07
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___POR 0x08
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___M 0x00FF0000
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___S              16
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___M 0x0000FF00
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___S               8
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___M 0x000000FF
#define   PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___S               0
#define   PHYA_RXTD_BTCF_CONFIG_1_U___M          0x00FFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_1_U___S                        0

#define PHYA_RXTD_BTCF_CONFIG_3_L                 (0x003A01A8)
#define   PHYA_RXTD_BTCF_CONFIG_3_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_3_L___POR        0x0160B05F
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___POR 0x058
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___POR 0x058
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___POR 0x05F
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___M 0x07FC0000
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___S              18
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___M 0x0003FE00
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___S               9
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___M 0x000001FF
#define   PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___S               0
#define   PHYA_RXTD_BTCF_CONFIG_3_L___M          0x07FFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_3_L___S                        0

#define PHYA_RXTD_BTCF_CONFIG_3_U                 (0x003A01AC)
#define   PHYA_RXTD_BTCF_CONFIG_3_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_3_U___POR        0x00000000
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___POR 0x0000
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___POR 0x0000
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___M 0xFFFF0000
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___S              16
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___M 0x0000FFFF
#define   PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___S               0
#define   PHYA_RXTD_BTCF_CONFIG_3_U___M          0xFFFFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_3_U___S                        0

#define PHYA_RXTD_BTCF_CONFIG_2_L                 (0x003A01B0)
#define   PHYA_RXTD_BTCF_CONFIG_2_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_2_L___POR        0x04CE3503
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___POR 0x133
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___POR 0x11A
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___POR 0x103
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___M 0x07FC0000
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___S              18
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___M 0x0003FE00
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___S               9
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___M 0x000001FF
#define   PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___S               0
#define   PHYA_RXTD_BTCF_CONFIG_2_L___M          0x07FFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_2_L___S                        0

#define PHYA_RXTD_BTCF_CONFIG_2_U                 (0x003A01B4)
#define   PHYA_RXTD_BTCF_CONFIG_2_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_2_U___POR        0x8399004D
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___POR 0x10
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___POR 0x0E6
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___POR 0x080
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___POR 0x04D
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___M 0xF8000000
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___S              27
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___M 0x07FC0000
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___S              18
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___M 0x0003FE00
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___S               9
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___M 0x000001FF
#define   PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___S               0
#define   PHYA_RXTD_BTCF_CONFIG_2_U___M          0xFFFFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_2_U___S                        0

#define PHYA_RXTD_GIC_CTRL_0_L                    (0x003A01B8)
#define   PHYA_RXTD_GIC_CTRL_0_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_0_L___POR           0xB3000000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___POR 0x2
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___POR 0xC
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___POR 0xC
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___POR 0x0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___M  0xC0000000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___S               30
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___M 0x3C000000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___S              26
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___M 0x03C00000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___S              22
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___M 0x00380000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___S              19
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___M 0x00070000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___S              16
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___M 0x00008000
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___S              15
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___M 0x00007800
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___S              11
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___M 0x00000700
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___S               8
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___M 0x000000E0
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___S               5
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___M 0x00000010
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___S               4
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___M 0x0000000F
#define   PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___S               0
#define   PHYA_RXTD_GIC_CTRL_0_L___M             0xFFFFFFFF   
#define   PHYA_RXTD_GIC_CTRL_0_L___S                           0

#define PHYA_RXTD_GIC_CTRL_1_L                    (0x003A01C0)
#define   PHYA_RXTD_GIC_CTRL_1_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_1_L___POR           0x000168B4
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___POR 0x0B4
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___POR 0x0B4
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___M 0x0003FE00
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___S               9
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___M 0x000001FF
#define   PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___S               0
#define   PHYA_RXTD_GIC_CTRL_1_L___M             0x0003FFFF   
#define   PHYA_RXTD_GIC_CTRL_1_L___S                           0

#define PHYA_RXTD_GIC_CTRL_2_L                    (0x003A01C8)
#define   PHYA_RXTD_GIC_CTRL_2_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_2_L___POR           0x057968B4
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___POR 0x15E
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___POR 0x0B4
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___POR 0x0B4
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___M 0x07FC0000
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___S              18
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___M 0x0003FE00
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___S               9
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___M 0x000001FF
#define   PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___S               0
#define   PHYA_RXTD_GIC_CTRL_2_L___M             0x07FFFFFF   
#define   PHYA_RXTD_GIC_CTRL_2_L___S                           0

#define PHYA_RXTD_GIC_CTRL_3_L                    (0x003A01D0)
#define   PHYA_RXTD_GIC_CTRL_3_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_3_L___POR           0x00320190
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___POR 0x640
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___POR 0x190
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___M 0x003FF800
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___S              11
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___M 0x000007FF
#define   PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___S               0
#define   PHYA_RXTD_GIC_CTRL_3_L___M             0x003FFFFF   
#define   PHYA_RXTD_GIC_CTRL_3_L___S                           0

#define PHYA_RXTD_GIC_CTRL_4_L                    (0x003A01D8)
#define   PHYA_RXTD_GIC_CTRL_4_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_4_L___POR           0x00028050
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___POR 0x050
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___POR 0x050
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___M 0x003FF800
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___S              11
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___M 0x000007FF
#define   PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___S               0
#define   PHYA_RXTD_GIC_CTRL_4_L___M             0x003FFFFF   
#define   PHYA_RXTD_GIC_CTRL_4_L___S                           0

#define PHYA_RXTD_GIC_CTRL_5_L                    (0x003A01E0)
#define   PHYA_RXTD_GIC_CTRL_5_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_5_L___POR           0x000A0140
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___POR 0x140
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___POR 0x140
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___M 0x003FF800
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___S              11
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___M 0x000007FF
#define   PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___S               0
#define   PHYA_RXTD_GIC_CTRL_5_L___M             0x003FFFFF   
#define   PHYA_RXTD_GIC_CTRL_5_L___S                           0

#define PHYA_RXTD_GIC_CTRL_6_L                    (0x003A01E8)
#define   PHYA_RXTD_GIC_CTRL_6_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_GIC_CTRL_6_L___POR           0x000A0140
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___POR 0x140
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___POR 0x140
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___M 0x003FF800
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___S              11
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___M 0x000007FF
#define   PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___S               0
#define   PHYA_RXTD_GIC_CTRL_6_L___M             0x003FFFFF   
#define   PHYA_RXTD_GIC_CTRL_6_L___S                           0

#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L           (0x003A01F0)
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L___POR  0x0007000A
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___POR 0x0007
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___POR 0x000A
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___M 0xFFFF0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___S              16
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___M 0x0000FFFF
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___S               0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L___M    0xFFFFFFFF   
#define   PHYA_RXTD_AGC_GAIN_SETTLING_1_L___S                  0

#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L         (0x003A01F8)
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___POR 0x00000000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___POR 0x0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___POR 0x0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___M 0xFFFF0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___S              16
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___M 0x0000FFFF
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___S               0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___M  0xFFFFFFFF   
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___S                0

#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L           (0x003A0200)
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L___POR  0x00050000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___POR 0x0005
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___POR 0x0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___M 0xFFFF0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___S              16
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___M 0x0000FFFF
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___S               0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L___M    0xFFFFFFFF   
#define   PHYA_RXTD_AGC_GAIN_SETTLING_3_L___S                  0

#define PHYA_RXTD_AGC_GC_DELAY_L                  (0x003A0208)
#define   PHYA_RXTD_AGC_GC_DELAY_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GC_DELAY_L___POR         0x00000001
#define   PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___POR 0x1
#define   PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___M 0x0000000F
#define   PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___S               0
#define   PHYA_RXTD_AGC_GC_DELAY_L___M           0x0000000F   
#define   PHYA_RXTD_AGC_GC_DELAY_L___S                         0

#define PHYA_RXTD_PEAK_DET_CTRL_1_L               (0x003A0210)
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L___POR      0x00000001
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___POR 0x0
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___POR 0x0
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___POR 0x1
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___M 0x00000004
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___S               2
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___M 0x00000002
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___S               1
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___M 0x00000001
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___S               0
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L___M        0x00000007   
#define   PHYA_RXTD_PEAK_DET_CTRL_1_L___S                      0

#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L           (0x003A0218)
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___POR  0x00000000
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___POR 0x0
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___POR 0x0
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___M 0x00000002
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___S               1
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___M 0x00000001
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___S               0
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___M    0x00000003   
#define   PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___S                  0

#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L         (0x003A0220)
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___POR 0x00A01E3C
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___POR 0x0A0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___POR 0x1E
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___POR 0x3C
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___M 0x03FF0000
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___S              16
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___M 0x0000FF00
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___S               8
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___M 0x000000FF
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___S               0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___M  0x03FFFFFF   
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___S                0

#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U         (0x003A0224)
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___POR 0x00005050
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___POR 0x50
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___POR 0x50
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___M 0x0000FF00
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___S               8
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___M 0x000000FF
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___S               0
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___M  0x0000FFFF   
#define   PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___S                0

#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L              (0x003A0228)
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L___POR     0x00000000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___POR 0x0
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___M 0x00000001
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___S               0
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L___M       0x00000001   
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_L___S                     0

#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U              (0x003A022C)
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U___POR     0x00000000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___POR 0x0000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___M 0x0000FFFF
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___S               0
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U___M       0x0000FFFF   
#define   PHYA_RXTD_AGC_UL_MU_CTRL_1_U___S                     0

#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L              (0x003A0230)
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L___POR     0x00000000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___POR 0x0000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___POR 0x0000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___M 0xFFFF0000
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___S              16
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___M 0x0000FFFF
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___S               0
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L___M       0xFFFFFFFF   
#define   PHYA_RXTD_AGC_UL_MU_CTRL_2_L___S                     0

#define PHYA_RXTD_AGC_SRCH_CTRL_1_L               (0x003A0238)
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L___POR      0x00000009
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___POR 0x0
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___POR 0x1
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___POR 0x0
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___POR 0x0
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___POR 0x1
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___M 0x00000010
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___S               4
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___M 0x00000008
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___S               3
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___M 0x00000004
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___S               2
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___M 0x00000002
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___S               1
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___M 0x00000001
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___S               0
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L___M        0x0000001F   
#define   PHYA_RXTD_AGC_SRCH_CTRL_1_L___S                      0

#define PHYA_RXTD_PEAK_DET_CTRL_2_L               (0x003A0240)
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L___POR      0x07823A28
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___POR 0x0F
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___POR 0x00
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___POR 0x23
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___POR 0x28
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___POR 0x28
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___M 0x1F800000
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___S              23
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___M 0x007C0000
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___S              18
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___M 0x0003F000
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___S              12
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___M 0x00000FC0
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___S               6
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___M 0x0000003F
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___S               0
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L___M        0x1FFFFFFF   
#define   PHYA_RXTD_PEAK_DET_CTRL_2_L___S                      0

#define PHYA_RXTD_PEAK_DET_CTRL_3_L               (0x003A0248)
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L___POR      0x003DE8E3
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___POR 0x0F
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___POR 0x1E
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___POR 0x23
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___POR 0x23
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___M 0x00FC0000
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___S              18
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___M 0x0003F000
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___S              12
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___M 0x00000FC0
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___S               6
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___M 0x0000003F
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___S               0
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L___M        0x00FFFFFF   
#define   PHYA_RXTD_PEAK_DET_CTRL_3_L___S                      0

#define PHYA_RXTD_AGC_PWR_THR_L                   (0x003A0250)
#define   PHYA_RXTD_AGC_PWR_THR_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_AGC_PWR_THR_L___POR          0x28FD9C9C
#define   PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___POR 0x28
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___POR 0xFD
#define   PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___POR 0x9C
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___POR 0x9C
#define   PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___M 0xFF000000
#define   PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___S              24
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___M 0x00FF0000
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___S              16
#define   PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___M 0x0000FF00
#define   PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___S               8
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___M 0x000000FF
#define   PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___S               0
#define   PHYA_RXTD_AGC_PWR_THR_L___M            0xFFFFFFFF   
#define   PHYA_RXTD_AGC_PWR_THR_L___S                          0

#define PHYA_RXTD_AGC_PWR_TARGET_1_L              (0x003A0258)
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L___POR     0x017ECEDA
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___POR 0x1
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___POR 0x7E
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___POR 0xCE
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___POR 0xDA
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___M 0x01000000
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___S              24
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___M 0x00FF0000
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___S              16
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___M 0x0000FF00
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___S               8
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___M 0x000000FF
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___S               0
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L___M       0x01FFFFFF   
#define   PHYA_RXTD_AGC_PWR_TARGET_1_L___S                     0

#define PHYA_RXTD_AGC_PWR_TARGET_2_L              (0x003A0260)
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L___POR     0x06D6D001
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___POR 0xDA
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___POR 0xDA
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___POR 0x00
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___POR 0x0
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___POR 0x1
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___M 0x07F80000
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___S              19
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___M 0x0007F800
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___S              11
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___M 0x000007F0
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___S               4
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___M 0x0000000C
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___S               2
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___M 0x00000003
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___S               0
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L___M       0x07FFFFFF   
#define   PHYA_RXTD_AGC_PWR_TARGET_2_L___S                     0

#define PHYA_RXTD_AGC_PWR_TARGET_3_L              (0x003A0268)
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L___POR     0x0000DADA
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___POR 0xDA
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___POR 0xDA
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___M 0x0000FF00
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___S               8
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___M 0x000000FF
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___S               0
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L___M       0x0000FFFF   
#define   PHYA_RXTD_AGC_PWR_TARGET_3_L___S                     0

#define PHYA_RXTD_AGC_QUICKDROP_L                 (0x003A0270)
#define   PHYA_RXTD_AGC_QUICKDROP_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_AGC_QUICKDROP_L___POR        0x00D8CECE
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___POR 0xD8
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___POR 0xCE
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___POR 0xCE
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___M 0x00FF0000
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___S              16
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___M 0x0000FF00
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___S               8
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___M 0x000000FF
#define   PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___S               0
#define   PHYA_RXTD_AGC_QUICKDROP_L___M          0x00FFFFFF   
#define   PHYA_RXTD_AGC_QUICKDROP_L___S                        0

#define PHYA_RXTD_AGC_PWR_HIGH_L                  (0x003A0278)
#define   PHYA_RXTD_AGC_PWR_HIGH_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_AGC_PWR_HIGH_L___POR         0x0013E80A
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___POR 0x0
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___POR 0x0
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___POR 0x0
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___POR 0x0
#define   PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___POR 0x4
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___POR 0x1F4
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___POR 0x00A
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___M 0x02000000
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___S              25
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___M 0x01000000
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___S              24
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___M 0x00800000
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___S              23
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___M 0x00400000
#define   PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___S              22
#define   PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___M 0x003C0000
#define   PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___S              18
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___M 0x0003FE00
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___S               9
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___M 0x000001FF
#define   PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___S               0
#define   PHYA_RXTD_AGC_PWR_HIGH_L___M           0x03FFFFFF   
#define   PHYA_RXTD_AGC_PWR_HIGH_L___S                         0

#define PHYA_RXTD_BTCF_METRICS_1_0_L              (0x003A0280)
#define   PHYA_RXTD_BTCF_METRICS_1_0_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_METRICS_1_0_L___POR     0x00000000
#define   PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___POR 0x00
#define   PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___M 0x0000001F
#define   PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___S               0
#define   PHYA_RXTD_BTCF_METRICS_1_0_L___M       0x0000001F   
#define   PHYA_RXTD_BTCF_METRICS_1_0_L___S                     0

#define PHYA_RXTD_BTCF_METRICS_1_0_U              (0x003A0284)
#define   PHYA_RXTD_BTCF_METRICS_1_0_U___RWC        QCSR_REG_RO    
#define   PHYA_RXTD_BTCF_METRICS_1_0_U___POR     0x00000000
#define   PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___POR 0x00000000
#define   PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___M 0xFFFFFFFF
#define   PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___S               0
#define   PHYA_RXTD_BTCF_METRICS_1_0_U___M       0xFFFFFFFF   
#define   PHYA_RXTD_BTCF_METRICS_1_0_U___S                     0

#define PHYA_RXTD_BTCF_METRICS_1_1_L              (0x003A0288)
#define   PHYA_RXTD_BTCF_METRICS_1_1_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_METRICS_1_1_L___POR     0x00000000
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___POR 0x0
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___POR 0x000
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___M 0x00010000
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___S              16
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___M 0x000003FF
#define   PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___S               0
#define   PHYA_RXTD_BTCF_METRICS_1_1_L___M       0x000103FF   
#define   PHYA_RXTD_BTCF_METRICS_1_1_L___S                     0

#define PHYA_RXTD_BTCF_METRICS_1_1_U              (0x003A028C)
#define   PHYA_RXTD_BTCF_METRICS_1_1_U___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_METRICS_1_1_U___POR     0x00000FFF
#define   PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___POR 0x0FFF
#define   PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___M 0x0000FFFF
#define   PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___S               0
#define   PHYA_RXTD_BTCF_METRICS_1_1_U___M       0x0000FFFF   
#define   PHYA_RXTD_BTCF_METRICS_1_1_U___S                     0

#define PHYA_RXTD_BTCF_CONFIG_4_L                 (0x003A0290)
#define   PHYA_RXTD_BTCF_CONFIG_4_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_4_L___POR        0x00000005
#define   PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___POR 0x00000005
#define   PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___M 0xFFFFFFFF
#define   PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___S               0
#define   PHYA_RXTD_BTCF_CONFIG_4_L___M          0xFFFFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_4_L___S                        0

#define PHYA_RXTD_BTCF_CONFIG_4_U                 (0x003A0294)
#define   PHYA_RXTD_BTCF_CONFIG_4_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_4_U___POR        0x001F0000
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___POR 0x1F
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___POR 0x0000
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___M 0x00FF0000
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___S              16
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___M 0x0000FFFF
#define   PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___S               0
#define   PHYA_RXTD_BTCF_CONFIG_4_U___M          0x00FFFFFF   
#define   PHYA_RXTD_BTCF_CONFIG_4_U___S                        0

#define PHYA_RXTD_BTCF_CONFIG_5_L                 (0x003A0298)
#define   PHYA_RXTD_BTCF_CONFIG_5_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BTCF_CONFIG_5_L___POR        0x00000064
#define   PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___POR 0x0
#define   PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___POR 0x64
#define   PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___M 0x00000100
#define   PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___S               8
#define   PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___M 0x000000FF
#define   PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___S               0
#define   PHYA_RXTD_BTCF_CONFIG_5_L___M          0x000001FF   
#define   PHYA_RXTD_BTCF_CONFIG_5_L___S                        0

#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L          (0x003A02A0)
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___POR 0x00000000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___POR 0x0000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___POR 0x0
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___M 0x3FFF0000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___S              16
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___M 0x00000001
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___S               0
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___M   0x3FFF0001   
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___S                 0

#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U          (0x003A02A4)
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___POR 0x00000000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___POR 0x0000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___POR 0x0
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___M 0x3FFF0000
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___S              16
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___M 0x00000001
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___S               0
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___M   0x3FFF0001   
#define   PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___S                 0

#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L          (0x003A02A8)
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___POR 0x00000000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___POR 0x000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___POR 0x000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___POR 0x0
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___M 0x01FFE000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___S              13
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___M 0x00001FFE
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___S               1
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___M 0x00000001
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___S               0
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___M   0x01FFFFFF   
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___S                 0

#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U          (0x003A02AC)
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___POR 0x00000000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___POR 0x000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___POR 0x000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___M 0x00FFF000
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___S              12
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___M 0x00000FFF
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___S               0
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___M   0x00FFFFFF   
#define   PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___S                 0

#define PHYA_RXTD_TFEST_CONTROL_L                 (0x003A02B0)
#define   PHYA_RXTD_TFEST_CONTROL_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TFEST_CONTROL_L___POR        0x0000005F
#define   PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___POR 0x5F
#define   PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___M 0x0000007F
#define   PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___S               0
#define   PHYA_RXTD_TFEST_CONTROL_L___M          0x0000007F   
#define   PHYA_RXTD_TFEST_CONTROL_L___S                        0

#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L           (0x003A02B8)
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___POR  0x01903000
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___POR 0x019
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___POR 0x00C
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___POR 0x000
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___M 0x3FF00000
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___S              20
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___M 0x000FFC00
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___S              10
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___M 0x000003FF
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___S               0
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___M    0x3FFFFFFF   
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___S                  0

#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L           (0x003A02C0)
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___POR  0x0440CC27
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___POR 0x044
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___POR 0x033
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___POR 0x027
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___M 0x3FF00000
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___S              20
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___M 0x000FFC00
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___S              10
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___M 0x000003FF
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___S               0
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___M    0x3FFFFFFF   
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___S                  0

#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L           (0x003A02C8)
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___POR  0x00014451
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___POR 0x051
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___POR 0x051
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___M 0x000FFC00
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___S              10
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___M 0x000003FF
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___S               0
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___M    0x000FFFFF   
#define   PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___S                  0

#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L             (0x003A02D0)
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L___POR    0x0000483E
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___POR 0x000
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___POR 0x012
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___POR 0x03E
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___M 0x3FF00000
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___S              20
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___M 0x000FFC00
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___S              10
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___M 0x000003FF
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___S               0
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L___M      0x3FFFFFFF   
#define   PHYA_RXTD_BT_COEX_XLNA_GAIN_L___S                    0

#define PHYA_RXTD_BT_COEX_CTRL_L                  (0x003A02D8)
#define   PHYA_RXTD_BT_COEX_CTRL_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_CTRL_L___POR         0x00000000
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___POR 0x0
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___M 0x00000040
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___S               6
#define   PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___M 0x00000020
#define   PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___S               5
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___M 0x00000010
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___S               4
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___M 0x00000008
#define   PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___S               3
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___M 0x00000004
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___S               2
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___M 0x00000002
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___S               1
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___M 0x00000001
#define   PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___S               0
#define   PHYA_RXTD_BT_COEX_CTRL_L___M           0x0000007F   
#define   PHYA_RXTD_BT_COEX_CTRL_L___S                         0

#define PHYA_RXTD_BT_COEX_DET_FLAGS_L             (0x003A02E0)
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L___POR    0x00000000
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___POR 0x000
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___M 0x000003FF
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___S               0
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L___M      0x000003FF   
#define   PHYA_RXTD_BT_COEX_DET_FLAGS_L___S                    0

#define PHYA_RXTD_LISTEN_MASK_L                   (0x003A02E8)
#define   PHYA_RXTD_LISTEN_MASK_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_LISTEN_MASK_L___POR          0x00000001
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___POR 0x0
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___POR 0x00
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___POR 0x00
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___POR 0x01
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___M 0x0F000000
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___S              24
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___M 0x00FF0000
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___S              16
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___M 0x0000FF00
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___S               8
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___M 0x000000FF
#define   PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___S               0
#define   PHYA_RXTD_LISTEN_MASK_L___M            0x0FFFFFFF   
#define   PHYA_RXTD_LISTEN_MASK_L___S                          0

#define PHYA_RXTD_RCV_MASK_0_L                    (0x003A02F0)
#define   PHYA_RXTD_RCV_MASK_0_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_RCV_MASK_0_L___POR           0x00000001
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___POR 0x0
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___POR 0x00
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___POR 0x00
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___POR 0x01
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___M 0x0F000000
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___S              24
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___M 0x00FF0000
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___S              16
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___M 0x0000FF00
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___S               8
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___M 0x000000FF
#define   PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___S               0
#define   PHYA_RXTD_RCV_MASK_0_L___M             0x0FFFFFFF   
#define   PHYA_RXTD_RCV_MASK_0_L___S                           0

#define PHYA_RXTD_RCV_MASK_1_L                    (0x003A02F8)
#define   PHYA_RXTD_RCV_MASK_1_L___RWC              QCSR_REG_RW    
#define   PHYA_RXTD_RCV_MASK_1_L___POR           0x00000000
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___POR 0x0
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___POR 0x00
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___POR 0x00
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___POR 0x00
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___M 0x0F000000
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___S              24
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___M 0x00FF0000
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___S              16
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___M 0x0000FF00
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___S               8
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___M 0x000000FF
#define   PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___S               0
#define   PHYA_RXTD_RCV_MASK_1_L___M             0x0FFFFFFF   
#define   PHYA_RXTD_RCV_MASK_1_L___S                           0

#define PHYA_RXTD_ACK_RESPONSE_L                  (0x003A0300)
#define   PHYA_RXTD_ACK_RESPONSE_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_ACK_RESPONSE_L___POR         0x00000000
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___POR 0x0
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___POR 0x0
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___M 0x00000100
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___S               8
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___M 0x00000003
#define   PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___S               0
#define   PHYA_RXTD_ACK_RESPONSE_L___M           0x00000103   
#define   PHYA_RXTD_ACK_RESPONSE_L___S                         0

#define PHYA_RXTD_RXTD_CONTROL_CFG_L              (0x003A0308)
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L___POR     0x00000100
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___POR 0x000
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___POR 0x1
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___M 0x0FFF0000
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___S              16
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___M 0x00000100
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___S               8
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___M 0x00000001
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___S               0
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L___M       0x0FFF0101   
#define   PHYA_RXTD_RXTD_CONTROL_CFG_L___S                     0

#define PHYA_RXTD_XBAR_L                          (0x003A0310)
#define   PHYA_RXTD_XBAR_L___RWC                    QCSR_REG_RW    
#define   PHYA_RXTD_XBAR_L___POR                 0x00FAC688
#define   PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___POR   0xFAC688
#define   PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___M     0x00FFFFFF
#define   PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___S                   0
#define   PHYA_RXTD_XBAR_L___M                   0x00FFFFFF   
#define   PHYA_RXTD_XBAR_L___S                                 0

#define PHYA_RXTD_XBAR_U                          (0x003A0314)
#define   PHYA_RXTD_XBAR_U___RWC                    QCSR_REG_RW    
#define   PHYA_RXTD_XBAR_U___POR                 0x000000FF
#define   PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___POR 0xFF
#define   PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___M 0x000000FF
#define   PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___S               0
#define   PHYA_RXTD_XBAR_U___M                   0x000000FF   
#define   PHYA_RXTD_XBAR_U___S                                 0

#define PHYA_RXTD_RX11B_DET_CTRL0_L               (0x003A0318)
#define   PHYA_RXTD_RX11B_DET_CTRL0_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RX11B_DET_CTRL0_L___POR      0x7C0000DA
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___POR 0xF8
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___POR 0x0
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___POR 0x0
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___POR 0x00
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___POR 0xDA
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___M 0x7F800000
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___S              23
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___M 0x00780000
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___S              19
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___M 0x00078000
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___S              15
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___M 0x00007F00
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___S               8
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___M 0x000000FF
#define   PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___S               0
#define   PHYA_RXTD_RX11B_DET_CTRL0_L___M        0x7FFFFFFF   
#define   PHYA_RXTD_RX11B_DET_CTRL0_L___S                      0

#define PHYA_RXTD_RX11B_DET_CTRL0_U               (0x003A031C)
#define   PHYA_RXTD_RX11B_DET_CTRL0_U___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RX11B_DET_CTRL0_U___POR      0x00E8FF55
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___POR 0xE8
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___POR 0xFF
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___POR 0x55
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___M 0x00FF0000
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___S              16
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___M 0x0000FF00
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___S               8
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___M 0x000000FF
#define   PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___S               0
#define   PHYA_RXTD_RX11B_DET_CTRL0_U___M        0x00FFFFFF   
#define   PHYA_RXTD_RX11B_DET_CTRL0_U___S                      0

#define PHYA_RXTD_RX11B_DET_CTRL1_L               (0x003A0320)
#define   PHYA_RXTD_RX11B_DET_CTRL1_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RX11B_DET_CTRL1_L___POR      0x00645A26
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___POR 0x32
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___POR 0x2D
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___POR 0x026
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___M 0x01FE0000
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___S              17
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___M 0x0001FE00
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___S               9
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___M 0x000001FF
#define   PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___S               0
#define   PHYA_RXTD_RX11B_DET_CTRL1_L___M        0x01FFFFFF   
#define   PHYA_RXTD_RX11B_DET_CTRL1_L___S                      0

#define PHYA_RXTD_RX11B_DET_CTRL1_U               (0x003A0324)
#define   PHYA_RXTD_RX11B_DET_CTRL1_U___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RX11B_DET_CTRL1_U___POR      0x025B2214
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___POR 0x096C
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___POR 0x4
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___POR 0x2
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___POR 0x14
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___M 0x07FFC000
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___S              14
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___M 0x00003800
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___S              11
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___M 0x00000700
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___S               8
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___M 0x000000FF
#define   PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___S               0
#define   PHYA_RXTD_RX11B_DET_CTRL1_U___M        0x07FFFFFF   
#define   PHYA_RXTD_RX11B_DET_CTRL1_U___S                      0

#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L         (0x003A0328)
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___POR 0x00000000
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___POR 0x000
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___M 0x000001FF
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___S               0
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___M  0x000001FF   
#define   PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___S                0

#define PHYA_RXTD_RXB_RX_RESET_L                  (0x003A0330)
#define   PHYA_RXTD_RXB_RX_RESET_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_RXB_RX_RESET_L___POR         0x00000000
#define   PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___POR 0x0
#define   PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___M 0x00000001
#define   PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___S               0
#define   PHYA_RXTD_RXB_RX_RESET_L___M           0x00000001   
#define   PHYA_RXTD_RXB_RX_RESET_L___S                         0

#define PHYA_RXTD_RXB_RX_CONFIG_1_L               (0x003A0338)
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L___POR      0x02B49EDE
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___POR 0x2
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___POR 0x1
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___POR 0x3
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___POR 0x127
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___POR 0x2DE
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___M 0x03000000
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___S              24
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___M 0x00800000
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___S              23
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___M 0x00700000
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___S              20
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___M 0x000FFC00
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___S              10
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___M 0x000003FF
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___S               0
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L___M        0x03FFFFFF   
#define   PHYA_RXTD_RXB_RX_CONFIG_1_L___S                      0

#define PHYA_RXTD_RXB_RX_CONFIG_2_L               (0x003A0340)
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L___POR      0x0000107D
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___POR 0x10
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___POR 0x7D
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___M 0x00003F00
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___S               8
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___M 0x000000FF
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___S               0
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L___M        0x00003FFF   
#define   PHYA_RXTD_RXB_RX_CONFIG_2_L___S                      0

#define PHYA_RXTD_RXB_RX_DISABLES_L               (0x003A0348)
#define   PHYA_RXTD_RXB_RX_DISABLES_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_RXB_RX_DISABLES_L___POR      0x000000FB
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___POR 0x0
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___POR 0x0
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___POR 0x0
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___POR 0x0
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___POR 0x0
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___POR 0xFB
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___M 0x00001000
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___S              12
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___M 0x00000800
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___S              11
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___M 0x00000400
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___S              10
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___M 0x00000200
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___S               9
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___M 0x00000100
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___S               8
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___M 0x000000FF
#define   PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___S               0
#define   PHYA_RXTD_RXB_RX_DISABLES_L___M        0x00001FFF   
#define   PHYA_RXTD_RXB_RX_DISABLES_L___S                      0

#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L         (0x003A0350)
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___POR 0x00002819
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___POR 0x2
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___POR 0x2
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___POR 0x0
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___POR 0x0
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___POR 0x19
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___M 0x00003000
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___S              12
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___M 0x00000C00
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___S              10
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___M 0x00000300
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___S               8
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___M 0x000000C0
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___S               6
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___M 0x0000003F
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___S               0
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___M  0x00003FFF   
#define   PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___S                0

#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L              (0x003A0358)
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L___RWC        QCSR_REG_RO    
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L___POR     0x00000000
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___S              16
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___S               0
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L___M       0xFFFFFFFF   
#define   PHYA_RXTD_RXB_RX_SSFD_LSFD_L___S                     0

#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L         (0x003A0360)
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___RWC   QCSR_REG_RO    
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___POR 0x00000000
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___S              16
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___S               0
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___M  0xFFFFFFFF   
#define   PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___S                0

#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L             (0x003A0368)
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L___RWC       QCSR_REG_RO    
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L___POR    0x00000000
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___S               0
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L___M      0x0000FFFF   
#define   PHYA_RXTD_RXB_RX_CRC_ERRORS_L___S                    0

#define PHYA_RXTD_RXB_RX_BYTES_L                  (0x003A0370)
#define   PHYA_RXTD_RXB_RX_BYTES_L___RWC            QCSR_REG_RO    
#define   PHYA_RXTD_RXB_RX_BYTES_L___POR         0x00000000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___POR 0x0
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___POR 0x0
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___POR 0x0
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___POR 0x0
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___M 0xF0000000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___S              28
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___M 0x0F000000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___S              24
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___M 0x00F00000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___S              20
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___M 0x000F0000
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___S              16
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___S               0
#define   PHYA_RXTD_RXB_RX_BYTES_L___M           0xFFFFFFFF   
#define   PHYA_RXTD_RXB_RX_BYTES_L___S                         0

#define PHYA_RXTD_RXB_MPI_SOF_EOF_L               (0x003A0378)
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L___POR      0x00000000
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___S              16
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___S               0
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L___M        0xFFFFFFFF   
#define   PHYA_RXTD_RXB_MPI_SOF_EOF_L___S                      0

#define PHYA_RXTD_RXB_START_ABORT_L               (0x003A0380)
#define   PHYA_RXTD_RXB_START_ABORT_L___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_RXB_START_ABORT_L___POR      0x00000000
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___POR 0x0000
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___S              16
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___S               0
#define   PHYA_RXTD_RXB_START_ABORT_L___M        0xFFFFFFFF   
#define   PHYA_RXTD_RXB_START_ABORT_L___S                      0

#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L          (0x003A0388)
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___RWC    QCSR_REG_RO    
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___POR 0x00000000
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___POR 0x0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___POR 0x0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___S              16
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___S               0
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___M   0xFFFFFFFF   
#define   PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___S                 0

#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L          (0x003A0390)
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___RWC    QCSR_REG_RO    
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___POR 0x00000000
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___POR 0x0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___POR 0x0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___M 0xFFFF0000
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___S              16
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___S               0
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___M   0xFFFFFFFF   
#define   PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___S                 0

#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L            (0x003A0398)
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___RWC      QCSR_REG_RO    
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___POR   0x00000000
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___POR 0x0000
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___M 0x0000FFFF
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___S               0
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___M     0x0000FFFF   
#define   PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___S                   0

#define PHYA_RXTD_FORCE_CLKEN_CCK_L               (0x003A03A0)
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L___POR      0x00000000
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___POR 0x0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___M 0x00000020
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___S               5
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___M 0x00000010
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___S               4
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___M 0x00000008
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___S               3
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___M 0x00000004
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___S               2
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___M 0x00000002
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___S               1
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___M 0x00000001
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___S               0
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L___M        0x0000003F   
#define   PHYA_RXTD_FORCE_CLKEN_CCK_L___S                      0

#define PHYA_RXTD_RXB_SPARE_01_L                  (0x003A03A8)
#define   PHYA_RXTD_RXB_SPARE_01_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_RXB_SPARE_01_L___POR         0x00000000
#define   PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___POR 0x0000000
#define   PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___M 0x03FFFFFF
#define   PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___S               0
#define   PHYA_RXTD_RXB_SPARE_01_L___M           0x03FFFFFF   
#define   PHYA_RXTD_RXB_SPARE_01_L___S                         0

#define PHYA_RXTD_PMI_OUTPUT_L                    (0x003A03B0)
#define   PHYA_RXTD_PMI_OUTPUT_L___RWC              QCSR_REG_RO    
#define   PHYA_RXTD_PMI_OUTPUT_L___POR           0x00000000
#define   PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___POR 0x00000
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___POR 0x0
#define   PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___M 0x02000000
#define   PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___S              25
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___M 0x01000000
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___S              24
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___M 0x00C00000
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___S              22
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___M 0x00200000
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___S              21
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___M 0x001FFFF0
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___S               4
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___M 0x0000000E
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___S               1
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___M 0x00000001
#define   PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___S               0
#define   PHYA_RXTD_PMI_OUTPUT_L___M             0x03FFFFFF   
#define   PHYA_RXTD_PMI_OUTPUT_L___S                           0

#define PHYA_RXTD_RBCTL_AGC_INFO_L                (0x003A03B8)
#define   PHYA_RXTD_RBCTL_AGC_INFO_L___RWC          QCSR_REG_RO    
#define   PHYA_RXTD_RBCTL_AGC_INFO_L___POR       0x00000000
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___POR 0x0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___M 0x00000020
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___S               5
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___M 0x00000010
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___S               4
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___M 0x00000008
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___S               3
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___M 0x00000004
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___S               2
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___M 0x00000002
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___S               1
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___M 0x00000001
#define   PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___S               0
#define   PHYA_RXTD_RBCTL_AGC_INFO_L___M         0x0000003F   
#define   PHYA_RXTD_RBCTL_AGC_INFO_L___S                       0

#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L              (0x003A03C0)
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L___POR     0x00000000
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___POR 0x00
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___POR 0x0
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___M 0x0000FF00
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___S               8
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___M 0x00000001
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___S               0
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L___M       0x0000FF01   
#define   PHYA_RXTD_RXTD_PHYDBG_CTRL_L___S                     0

#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L        (0x003A03C8)
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___RWC  QCSR_REG_RW    
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___POR 0x00000000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___POR 0x0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___POR 0x0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___M 0x03FF0000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___S              16
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___M 0x00000100
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___S               8
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___M 0x00000001
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___S               0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___M 0x03FF0101   
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___S               0

#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L        (0x003A03D0)
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___POR 0x00000000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___M 0x07FF0000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___S              16
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___M 0x000007FF
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___S               0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___M 0x07FF07FF   
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___S               0

#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U        (0x003A03D4)
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___POR 0x00000000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___POR 0x0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___M 0x00030000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___S              16
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___M 0x000003FF
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___S               0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___M 0x000303FF   
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___S               0

#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L        (0x003A03D8)
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___POR 0x00000000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___M 0x07FF0000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___S              16
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___M 0x000007FF
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___S               0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___M 0x07FF07FF   
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___S               0

#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U        (0x003A03DC)
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___POR 0x00000000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___POR 0x0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___POR 0x000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___M 0x00030000
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___S              16
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___M 0x000003FF
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___S               0
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___M 0x000303FF   
#define   PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___S               0

#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L             (0x003A03E0)
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___POR    0x03020000
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___POR 0x3
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___POR 0x2
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___POR 0x0
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___POR 0x00
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___M 0x03000000
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___S              24
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___M 0x00070000
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___S              16
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___M 0x00000F00
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___S               8
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___M 0x0000003F
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___S               0
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___M      0x03070F3F   
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___S                    0

#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U             (0x003A03E4)
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___POR    0x00000000
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___POR 0x00
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___M 0x000000FF
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___S               0
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___M      0x000000FF   
#define   PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___S                    0

#define PHYA_RXTD_FFT_BUF_CONFIG_0_L              (0x003A03E8)
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L___POR     0x00030000
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___POR 0x3
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___POR 0x0
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___POR 0x0
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___M 0x00030000
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___S              16
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___M 0x00000100
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___S               8
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___M 0x00000007
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___S               0
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L___M       0x00030107   
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_L___S                     0

#define PHYA_RXTD_FFT_BUF_CONFIG_0_U              (0x003A03EC)
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U___POR     0x00000000
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___POR 0x00000000
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___M 0xFFFFFFFF
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___S               0
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U___M       0xFFFFFFFF   
#define   PHYA_RXTD_FFT_BUF_CONFIG_0_U___S                     0

#define PHYA_RXTD_FFT_BUF_CONFIG_1_L              (0x003A03F0)
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L___POR     0x00000001
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___POR 0x1
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___M 0x00000001
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___S               0
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L___M       0x00000001   
#define   PHYA_RXTD_FFT_BUF_CONFIG_1_L___S                     0

#define PHYA_RXTD_OCL_CONFIG_0_L                  (0x003A03F8)
#define   PHYA_RXTD_OCL_CONFIG_0_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_OCL_CONFIG_0_L___POR         0x00000000
#define   PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___POR 0x00
#define   PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___POR 0x00
#define   PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___POR 0x0
#define   PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0
#define   PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___M 0x00000F80
#define   PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___S               7
#define   PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___M 0x0000007C
#define   PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___S               2
#define   PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___M 0x00000002
#define   PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___S               1
#define   PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001
#define   PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___S               0
#define   PHYA_RXTD_OCL_CONFIG_0_L___M           0x00000FFF   
#define   PHYA_RXTD_OCL_CONFIG_0_L___S                         0

#define PHYA_RXTD_OCL_CONFIG_1_L                  (0x003A0400)
#define   PHYA_RXTD_OCL_CONFIG_1_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_OCL_CONFIG_1_L___POR         0x00000000
#define   PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___POR 0x00
#define   PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___M 0x0000007F
#define   PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___S               0
#define   PHYA_RXTD_OCL_CONFIG_1_L___M           0x0000007F   
#define   PHYA_RXTD_OCL_CONFIG_1_L___S                         0

#define PHYA_RXTD_OCL_CONFIG_2_L                  (0x003A0408)
#define   PHYA_RXTD_OCL_CONFIG_2_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_OCL_CONFIG_2_L___POR         0x01452300
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___POR 0x0145
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___POR 0x23
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___POR 0x0
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___M 0x3FFF0000
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___S              16
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___M 0x0000FF00
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___S               8
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___M 0x00000001
#define   PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___S               0
#define   PHYA_RXTD_OCL_CONFIG_2_L___M           0x3FFFFF01   
#define   PHYA_RXTD_OCL_CONFIG_2_L___S                         0

#define PHYA_RXTD_OCL_CONFIG_2_U                  (0x003A040C)
#define   PHYA_RXTD_OCL_CONFIG_2_U___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_OCL_CONFIG_2_U___POR         0x00000001
#define   PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___POR 0x1
#define   PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___M 0x00000001
#define   PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___S               0
#define   PHYA_RXTD_OCL_CONFIG_2_U___M           0x00000001   
#define   PHYA_RXTD_OCL_CONFIG_2_U___S                         0

#define PHYA_RXTD_EVENT_CONFIG_L                  (0x003A0410)
#define   PHYA_RXTD_EVENT_CONFIG_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_EVENT_CONFIG_L___POR         0x00010000
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___POR 0x1
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___POR 0x0
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___POR 0x0
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___M 0x00010000
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___S              16
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___M 0x00000100
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___S               8
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___M 0x00000001
#define   PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___S               0
#define   PHYA_RXTD_EVENT_CONFIG_L___M           0x00010101   
#define   PHYA_RXTD_EVENT_CONFIG_L___S                         0

#define PHYA_RXTD_FFT_CTRL_DBG_L                  (0x003A0418)
#define   PHYA_RXTD_FFT_CTRL_DBG_L___RWC            QCSR_REG_RO    
#define   PHYA_RXTD_FFT_CTRL_DBG_L___POR         0x00000000
#define   PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___POR 0x0000
#define   PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___M 0x0000FFFF
#define   PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___S               0
#define   PHYA_RXTD_FFT_CTRL_DBG_L___M           0x0000FFFF   
#define   PHYA_RXTD_FFT_CTRL_DBG_L___S                         0

#define PHYA_RXTD_FFT_CTRL_L                      (0x003A0420)
#define   PHYA_RXTD_FFT_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_L___POR             0x00000000
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___POR 0x0
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___POR 0x0
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___POR 0x0000
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___M 0x07000000
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___S              24
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___M 0x00030000
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___S              16
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___M 0x0000FFFF
#define   PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___S               0
#define   PHYA_RXTD_FFT_CTRL_L___M               0x0703FFFF   
#define   PHYA_RXTD_FFT_CTRL_L___S                             0

#define PHYA_RXTD_FFT_CTRL_U                      (0x003A0424)
#define   PHYA_RXTD_FFT_CTRL_U___RWC                QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_U___POR             0x00000000
#define   PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___POR 0x0
#define   PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___M 0x00000001
#define   PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___S               0
#define   PHYA_RXTD_FFT_CTRL_U___M               0x00000001   
#define   PHYA_RXTD_FFT_CTRL_U___S                             0

#define PHYA_RXTD_FFT_CTRL_SCALE_L                (0x003A0428)
#define   PHYA_RXTD_FFT_CTRL_SCALE_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_SCALE_L___POR       0x00000000
#define   PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___POR 0x000000
#define   PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___M 0x00FFFFFF
#define   PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___S               0
#define   PHYA_RXTD_FFT_CTRL_SCALE_L___M         0x00FFFFFF   
#define   PHYA_RXTD_FFT_CTRL_SCALE_L___S                       0

#define PHYA_RXTD_FFT_CTRL_CFO_0_L                (0x003A0430)
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L___POR       0x00000000
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___POR 0x000000
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___M 0x001FFFFF
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___S               0
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L___M         0x001FFFFF   
#define   PHYA_RXTD_FFT_CTRL_CFO_0_L___S                       0

#define PHYA_RXTD_FFT_CTRL_CFO_0_U                (0x003A0434)
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U___POR       0x00000000
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___POR 0x000000
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___M 0x001FFFFF
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___S               0
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U___M         0x001FFFFF   
#define   PHYA_RXTD_FFT_CTRL_CFO_0_U___S                       0

#define PHYA_RXTD_FFT_CTRL_CFO_1_L                (0x003A0438)
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L___POR       0x00000000
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___POR 0x000000
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___M 0x001FFFFF
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___S               0
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L___M         0x001FFFFF   
#define   PHYA_RXTD_FFT_CTRL_CFO_1_L___S                       0

#define PHYA_RXTD_FFT_CTRL_CFO_1_U                (0x003A043C)
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U___POR       0x00000000
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___POR 0x000000
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___M 0x001FFFFF
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___S               0
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U___M         0x001FFFFF   
#define   PHYA_RXTD_FFT_CTRL_CFO_1_U___S                       0

#define PHYA_RXTD_TD_CFO_CTRL_0_L                 (0x003A0440)
#define   PHYA_RXTD_TD_CFO_CTRL_0_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TD_CFO_CTRL_0_L___POR        0x00000000
#define   PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___POR 0x000000
#define   PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___M 0x001FFFFF
#define   PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___S               0
#define   PHYA_RXTD_TD_CFO_CTRL_0_L___M          0x001FFFFF   
#define   PHYA_RXTD_TD_CFO_CTRL_0_L___S                        0

#define PHYA_RXTD_TD_CFO_CTRL_0_U                 (0x003A0444)
#define   PHYA_RXTD_TD_CFO_CTRL_0_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TD_CFO_CTRL_0_U___POR        0x00000000
#define   PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___POR 0x000000
#define   PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___M 0x001FFFFF
#define   PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___S               0
#define   PHYA_RXTD_TD_CFO_CTRL_0_U___M          0x001FFFFF   
#define   PHYA_RXTD_TD_CFO_CTRL_0_U___S                        0

#define PHYA_RXTD_TD_CFO_CTRL_1_L                 (0x003A0448)
#define   PHYA_RXTD_TD_CFO_CTRL_1_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TD_CFO_CTRL_1_L___POR        0x00000000
#define   PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___POR 0x000000
#define   PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___M 0x001FFFFF
#define   PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___S               0
#define   PHYA_RXTD_TD_CFO_CTRL_1_L___M          0x001FFFFF   
#define   PHYA_RXTD_TD_CFO_CTRL_1_L___S                        0

#define PHYA_RXTD_TD_CFO_CTRL_1_U                 (0x003A044C)
#define   PHYA_RXTD_TD_CFO_CTRL_1_U___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TD_CFO_CTRL_1_U___POR        0x00000000
#define   PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___POR 0x000000
#define   PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___M 0x001FFFFF
#define   PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___S               0
#define   PHYA_RXTD_TD_CFO_CTRL_1_U___M          0x001FFFFF   
#define   PHYA_RXTD_TD_CFO_CTRL_1_U___S                        0

#define PHYA_RXTD_TD_CFO_CTRL_2_L                 (0x003A0450)
#define   PHYA_RXTD_TD_CFO_CTRL_2_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_TD_CFO_CTRL_2_L___POR        0x00000000
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___POR 0x0
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___POR 0x0
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___POR 0x0000
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___M 0x03000000
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___S              24
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___M 0x00070000
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___S              16
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___M 0x0000FFFF
#define   PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___S               0
#define   PHYA_RXTD_TD_CFO_CTRL_2_L___M          0x0307FFFF   
#define   PHYA_RXTD_TD_CFO_CTRL_2_L___S                        0

#define PHYA_RXTD_TD_MIXERFIR_CTRL_L              (0x003A0458)
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L___POR     0x00000000
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___POR 0x0000
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___POR 0x0
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___M 0xFFFF0000
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___S              16
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___M 0x00000003
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___S               0
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L___M       0xFFFF0003   
#define   PHYA_RXTD_TD_MIXERFIR_CTRL_L___S                     0

#define PHYA_RXTD_RXTD_CONTROL_DYN_L              (0x003A0460)
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L___RWC        QCSR_REG_WO    
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L___POR     0x00000000
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___M 0x00000100
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___S               8
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___M 0x00000001
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___S               0
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L___M       0x00000101   
#define   PHYA_RXTD_RXTD_CONTROL_DYN_L___S                     0

#define PHYA_RXTD_VSRC_DYN_CONFIG_L               (0x003A0468)
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L___POR      0x00000000
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___POR 0x0000
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___POR 0x00
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___M 0xFFFF0000
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___S              16
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___M 0x0000001F
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___S               0
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L___M        0xFFFF001F   
#define   PHYA_RXTD_VSRC_DYN_CONFIG_L___S                      0

#define PHYA_RXTD_VSRC_PPM_L                      (0x003A0470)
#define   PHYA_RXTD_VSRC_PPM_L___RWC                QCSR_REG_RW    
#define   PHYA_RXTD_VSRC_PPM_L___POR             0x00000000
#define   PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___POR   0x00000
#define   PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___M     0x0003FFFF
#define   PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___S                   0
#define   PHYA_RXTD_VSRC_PPM_L___M               0x0003FFFF   
#define   PHYA_RXTD_VSRC_PPM_L___S                             0

#define PHYA_RXTD_MMSE_DYN_CONFIG_L               (0x003A0478)
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L___POR      0x00000000
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___POR 0x0
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___M 0x0000000F
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___S               0
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L___M        0x0000000F   
#define   PHYA_RXTD_MMSE_DYN_CONFIG_L___S                      0

#define PHYA_RXTD_RESTART_DISABLE_CTRL_L          (0x003A0480)
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L___POR 0x00000000
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___POR 0x0
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___POR 0x0000
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___M 0x00010000
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___S              16
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___M 0x0000FFFF
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___S               0
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L___M   0x0001FFFF   
#define   PHYA_RXTD_RESTART_DISABLE_CTRL_L___S                 0

#define PHYA_RXTD_RXTD_CONTROL_CMD_L              (0x003A0488)
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L___POR     0x00000000
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___POR 0x0
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___M 0x00010000
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___S              16
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___M 0x00000100
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___S               8
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___M 0x00000001
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___S               0
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L___M       0x00010101   
#define   PHYA_RXTD_RXTD_CONTROL_CMD_L___S                     0

#define PHYA_RXTD_DYN_CONTROL_PKT_L               (0x003A0490)
#define   PHYA_RXTD_DYN_CONTROL_PKT_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_DYN_CONTROL_PKT_L___POR      0x00000000
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___POR 0x0
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___POR 0x0
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___POR 0x000
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___M 0x01000000
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___S              24
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___M 0x00010000
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___S              16
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___M 0x00000FFF
#define   PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___S               0
#define   PHYA_RXTD_DYN_CONTROL_PKT_L___M        0x01010FFF   
#define   PHYA_RXTD_DYN_CONTROL_PKT_L___S                      0

#define PHYA_RXTD_DYN_CONTROL_PKT_U               (0x003A0494)
#define   PHYA_RXTD_DYN_CONTROL_PKT_U___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_DYN_CONTROL_PKT_U___POR      0x00000000
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___POR 0x0
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___POR 0x0
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___POR 0x0
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___M 0x00010000
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___S              16
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___M 0x00000100
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___S               8
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___M 0x00000001
#define   PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___S               0
#define   PHYA_RXTD_DYN_CONTROL_PKT_U___M        0x00010101   
#define   PHYA_RXTD_DYN_CONTROL_PKT_U___S                      0

#define PHYA_RXTD_DYN_E2E_HW_STATUS_L             (0x003A0498)
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L___POR    0x00000000
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___POR 0x0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___POR 0x0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___POR 0x0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___POR 0x0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___M 0x01000000
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___S              24
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___M 0x00010000
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___S              16
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___M 0x00000100
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___S               8
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___M 0x00000001
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___S               0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L___M      0x01010101   
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_L___S                    0

#define PHYA_RXTD_DYN_E2E_HW_STATUS_U             (0x003A049C)
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U___RWC       QCSR_REG_RO    
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U___POR    0x00000000
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___POR 0x0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___M 0x00000001
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___S               0
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U___M      0x00000001   
#define   PHYA_RXTD_DYN_E2E_HW_STATUS_U___S                    0

#define PHYA_RXTD_FSM_STATE_L                     (0x003A04A0)
#define   PHYA_RXTD_FSM_STATE_L___RWC               QCSR_REG_RO    
#define   PHYA_RXTD_FSM_STATE_L___POR            0x00000000
#define   PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___POR 0x00000000
#define   PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___M 0xFFFFFFFF
#define   PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___S               0
#define   PHYA_RXTD_FSM_STATE_L___M              0xFFFFFFFF   
#define   PHYA_RXTD_FSM_STATE_L___S                            0

#define PHYA_RXTD_FSM_STATE_U                     (0x003A04A4)
#define   PHYA_RXTD_FSM_STATE_U___RWC               QCSR_REG_RO    
#define   PHYA_RXTD_FSM_STATE_U___POR            0x00000000
#define   PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___POR 0x00000000
#define   PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___M 0xFFFFFFFF
#define   PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___S               0
#define   PHYA_RXTD_FSM_STATE_U___M              0xFFFFFFFF   
#define   PHYA_RXTD_FSM_STATE_U___S                            0

#define PHYA_RXTD_DYN_HW_STATUS_0_L               (0x003A04A8)
#define   PHYA_RXTD_DYN_HW_STATUS_0_L___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_DYN_HW_STATUS_0_L___POR      0x00000000
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___POR 0x0000
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___POR 0x000
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___M 0xFFFF0000
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___S              16
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___M 0x000003FF
#define   PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___S               0
#define   PHYA_RXTD_DYN_HW_STATUS_0_L___M        0xFFFF03FF   
#define   PHYA_RXTD_DYN_HW_STATUS_0_L___S                      0

#define PHYA_RXTD_DYN_HW_STATUS_0_U               (0x003A04AC)
#define   PHYA_RXTD_DYN_HW_STATUS_0_U___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_DYN_HW_STATUS_0_U___POR      0x00000000
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___M 0xFFFF0000
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___S              16
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF
#define   PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___S               0
#define   PHYA_RXTD_DYN_HW_STATUS_0_U___M        0xFFFFFFFF   
#define   PHYA_RXTD_DYN_HW_STATUS_0_U___S                      0

#define PHYA_RXTD_DYN_HW_STATUS_1_L               (0x003A04B0)
#define   PHYA_RXTD_DYN_HW_STATUS_1_L___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_DYN_HW_STATUS_1_L___POR      0x00000000
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___POR 0x0
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___POR 0x00
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___POR 0x00
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___POR 0x00
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___M 0x0F000000
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___S              24
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___M 0x003F0000
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___S              16
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___M 0x00003F00
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___S               8
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___M 0x000000FF
#define   PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___S               0
#define   PHYA_RXTD_DYN_HW_STATUS_1_L___M        0x0F3F3FFF   
#define   PHYA_RXTD_DYN_HW_STATUS_1_L___S                      0

#define PHYA_RXTD_DYN_HW_STATUS_1_U               (0x003A04B4)
#define   PHYA_RXTD_DYN_HW_STATUS_1_U___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_DYN_HW_STATUS_1_U___POR      0x00000000
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___POR 0x0
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___POR 0x00
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___POR 0x00
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___M 0x000F0000
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___S              16
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___M 0x00003F00
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___S               8
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___M 0x0000003F
#define   PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___S               0
#define   PHYA_RXTD_DYN_HW_STATUS_1_U___M        0x000F3F3F   
#define   PHYA_RXTD_DYN_HW_STATUS_1_U___S                      0

#define PHYA_RXTD_RSSI_COMB_0_L                   (0x003A04B8)
#define   PHYA_RXTD_RSSI_COMB_0_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_0_L___POR          0x00000000
#define   PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___POR 0x0
#define   PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___M 0x00000003
#define   PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___S               0
#define   PHYA_RXTD_RSSI_COMB_0_L___M            0x00000003   
#define   PHYA_RXTD_RSSI_COMB_0_L___S                          0

#define PHYA_RXTD_RSSI_COMB_1_L                   (0x003A04C0)
#define   PHYA_RXTD_RSSI_COMB_1_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_1_L___POR          0x00000080
#define   PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___POR 0x80
#define   PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___S               0
#define   PHYA_RXTD_RSSI_COMB_1_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_1_L___S                          0

#define PHYA_RXTD_RSSI_COMB_2_L                   (0x003A04C8)
#define   PHYA_RXTD_RSSI_COMB_2_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_2_L___POR          0x00000080
#define   PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___POR 0x80
#define   PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___S               0
#define   PHYA_RXTD_RSSI_COMB_2_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_2_L___S                          0

#define PHYA_RXTD_RSSI_COMB_3_L                   (0x003A04D0)
#define   PHYA_RXTD_RSSI_COMB_3_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_3_L___POR          0x00000080
#define   PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___POR 0x80
#define   PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___S               0
#define   PHYA_RXTD_RSSI_COMB_3_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_3_L___S                          0

#define PHYA_RXTD_RSSI_COMB_4_L                   (0x003A04D8)
#define   PHYA_RXTD_RSSI_COMB_4_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_4_L___POR          0x00000080
#define   PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___POR 0x80
#define   PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___S               0
#define   PHYA_RXTD_RSSI_COMB_4_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_4_L___S                          0

#define PHYA_RXTD_RSSI_COMB_5_L                   (0x003A04E0)
#define   PHYA_RXTD_RSSI_COMB_5_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_5_L___POR          0x00000080
#define   PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___POR 0x80
#define   PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___S               0
#define   PHYA_RXTD_RSSI_COMB_5_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_5_L___S                          0

#define PHYA_RXTD_RSSI_COMB_6_L                   (0x003A04E8)
#define   PHYA_RXTD_RSSI_COMB_6_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_RSSI_COMB_6_L___POR          0x00000000
#define   PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___POR 0x00
#define   PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___M 0x000000FF
#define   PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___S               0
#define   PHYA_RXTD_RSSI_COMB_6_L___M            0x000000FF   
#define   PHYA_RXTD_RSSI_COMB_6_L___S                          0

#define PHYA_RXTD_PKT_PARAM_0_L                   (0x003A04F0)
#define   PHYA_RXTD_PKT_PARAM_0_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_PKT_PARAM_0_L___POR          0x00000000
#define   PHYA_RXTD_PKT_PARAM_0_L__DET_11B___POR 0x0
#define   PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___POR 0x00
#define   PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___POR 0x000
#define   PHYA_RXTD_PKT_PARAM_0_L__DET_11B___M   0x01000000
#define   PHYA_RXTD_PKT_PARAM_0_L__DET_11B___S                24
#define   PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___M 0x00FF0000
#define   PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___S              16
#define   PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___M 0x00000FFF
#define   PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___S               0
#define   PHYA_RXTD_PKT_PARAM_0_L___M            0x01FF0FFF   
#define   PHYA_RXTD_PKT_PARAM_0_L___S                          0

#define PHYA_RXTD_PKT_PARAM_0_U                   (0x003A04F4)
#define   PHYA_RXTD_PKT_PARAM_0_U___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_PKT_PARAM_0_U___POR          0x00000000
#define   PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___POR 0x0
#define   PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___M 0x00000001
#define   PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___S               0
#define   PHYA_RXTD_PKT_PARAM_0_U___M            0x00000001   
#define   PHYA_RXTD_PKT_PARAM_0_U___S                          0

#define PHYA_RXTD_PKT_PARAM_1_L                   (0x003A04F8)
#define   PHYA_RXTD_PKT_PARAM_1_L___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_PKT_PARAM_1_L___POR          0x00000000
#define   PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___POR 0x00000000
#define   PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___M 0xFFFFFFFF
#define   PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___S               0
#define   PHYA_RXTD_PKT_PARAM_1_L___M            0xFFFFFFFF   
#define   PHYA_RXTD_PKT_PARAM_1_L___S                          0

#define PHYA_RXTD_PKT_PARAM_1_U                   (0x003A04FC)
#define   PHYA_RXTD_PKT_PARAM_1_U___RWC             QCSR_REG_RO    
#define   PHYA_RXTD_PKT_PARAM_1_U___POR          0x00000000
#define   PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___POR 0x0
#define   PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___M 0x0000000F
#define   PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___S               0
#define   PHYA_RXTD_PKT_PARAM_1_U___M            0x0000000F   
#define   PHYA_RXTD_PKT_PARAM_1_U___S                          0

#define PHYA_RXTD_AGC_NFCAL_PHY_L                 (0x003A0500)
#define   PHYA_RXTD_AGC_NFCAL_PHY_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_AGC_NFCAL_PHY_L___POR        0x00000000
#define   PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___POR 0x0
#define   PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___M 0x00000001
#define   PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___S               0
#define   PHYA_RXTD_AGC_NFCAL_PHY_L___M          0x00000001   
#define   PHYA_RXTD_AGC_NFCAL_PHY_L___S                        0

#define PHYA_RXTD_BT_COEX_TLV_1_L                 (0x003A0508)
#define   PHYA_RXTD_BT_COEX_TLV_1_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_TLV_1_L___POR        0x00000000
#define   PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___POR 0x0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___M 0x00000600
#define   PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___S               9
#define   PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___M 0x00000100
#define   PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___S               8
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___M 0x000000C0
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___S               6
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___M 0x00000038
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___S               3
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___M 0x00000004
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___S               2
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___M 0x00000002
#define   PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___S               1
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___M 0x00000001
#define   PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___S               0
#define   PHYA_RXTD_BT_COEX_TLV_1_L___M          0x000007FF   
#define   PHYA_RXTD_BT_COEX_TLV_1_L___S                        0

#define PHYA_RXTD_BT_COEX_TLV_2_L                 (0x003A0510)
#define   PHYA_RXTD_BT_COEX_TLV_2_L___RWC           QCSR_REG_RW    
#define   PHYA_RXTD_BT_COEX_TLV_2_L___POR        0x00000000
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___POR 0x00
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___POR 0x00
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___POR 0x00
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___POR 0x00
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___M 0xFF000000
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___S              24
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___M 0x00FF0000
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___S              16
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___M 0x0000FF00
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___S               8
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___M 0x000000FF
#define   PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___S               0
#define   PHYA_RXTD_BT_COEX_TLV_2_L___M          0xFFFFFFFF   
#define   PHYA_RXTD_BT_COEX_TLV_2_L___S                        0

#define PHYA_RXTD_DETECT_PWR_ERR_L                (0x003A0518)
#define   PHYA_RXTD_DETECT_PWR_ERR_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_DETECT_PWR_ERR_L___POR       0x0101140C
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___POR 0x1
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___POR 0x1
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___POR 0x14
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___POR 0x0C
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___M 0x01000000
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___S              24
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___M 0x00010000
#define   PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___S              16
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___M 0x00001F00
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___S               8
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___M 0x0000001F
#define   PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___S               0
#define   PHYA_RXTD_DETECT_PWR_ERR_L___M         0x01011F1F   
#define   PHYA_RXTD_DETECT_PWR_ERR_L___S                       0

#define PHYA_RXTD_DETECT_PWR_ERR_U                (0x003A051C)
#define   PHYA_RXTD_DETECT_PWR_ERR_U___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_DETECT_PWR_ERR_U___POR       0x00000000
#define   PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___POR 0x0
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___POR 0x0
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___POR 0x0
#define   PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___M 0x00010000
#define   PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___S              16
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___M 0x00000100
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___S               8
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___M 0x00000001
#define   PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___S               0
#define   PHYA_RXTD_DETECT_PWR_ERR_U___M         0x00010101   
#define   PHYA_RXTD_DETECT_PWR_ERR_U___S                       0

#define PHYA_RXTD_RXTD_RESTART_CAUSE_L            (0x003A0520)
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L___POR   0x00000000
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___M 0x00000200
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___S               9
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___M 0x00000100
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___S               8
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___M 0x00000080
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___S               7
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___M 0x00000040
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___S               6
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___M 0x00000020
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___S               5
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___M 0x00000010
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___S               4
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___M 0x00000008
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___S               3
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___M 0x00000004
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___S               2
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___M 0x00000002
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___S               1
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___M 0x00000001
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___S               0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L___M     0x000003FF   
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_L___S                   0

#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L       (0x003A0528)
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___POR 0x00000000
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___POR 0x0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___M 0x00000200
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___S               9
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___M 0x00000100
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___S               8
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___M 0x00000080
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___S               7
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___M 0x00000040
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___S               6
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___M 0x00000020
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___S               5
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___M 0x00000010
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___S               4
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___M 0x00000008
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___S               3
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___M 0x00000004
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___S               2
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___M 0x00000002
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___S               1
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___M 0x00000001
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___S               0
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___M 0x000003FF   
#define   PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___S               0

#define PHYA_RXTD_CCK_ERROR_CAUSE_L               (0x003A0530)
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L___RWC         QCSR_REG_RO    
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L___POR      0x00000000
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___POR 0x00
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___M 0x000000FF
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___S               0
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L___M        0x000000FF   
#define   PHYA_RXTD_CCK_ERROR_CAUSE_L___S                      0

#define PHYA_RXTD_DET0_RADAR_DETECTION_L          (0x003A0538)
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L___POR 0x007FFC07
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___POR 0x80
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___M 0x03800000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___S              23
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___M 0x00400000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___S              22
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___M 0x00200000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___S              21
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___M 0x00100000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___S              20
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___M 0x00080000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___S              19
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___M 0x00040000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___S              18
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___M 0x00020000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___S              17
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___S              16
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___M 0x00008000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___S              15
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___M 0x00004000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___S              14
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___M 0x00002000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___S              13
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___M 0x00001000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___S              12
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___M 0x00000800
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___S              11
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___M 0x000007F8
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___S               3
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___M 0x00000004
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___S               2
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___M 0x00000002
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___S               1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___S               0
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L___M   0x03FFFFFF   
#define   PHYA_RXTD_DET0_RADAR_DETECTION_L___S                 0

#define PHYA_RXTD_DET0_RADAR_DETECTION_U          (0x003A053C)
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U___POR 0x01A78478
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___POR 0x6
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___POR 0x9
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___POR 0xE1
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___POR 0x078
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___M 0x08000000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___S              27
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___M 0x04000000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___S              26
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___M 0x03C00000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___S              22
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___M 0x003C0000
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___S              18
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___M 0x0003FC00
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___S              10
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___S               0
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U___M   0x0FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_DETECTION_U___S                 0

#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L            (0x003A0540)
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L___POR   0x00000000
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___POR 0x000
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___S               0
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L___M     0x000003FF   
#define   PHYA_RXTD_DET0_RADAR_TIMEOUT_L___S                   0

#define PHYA_RXTD_DET0_RADAR_POW_DET_L            (0x003A0548)
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L___POR   0x13832064
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___POR 0x4
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___POR 0x18
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___POR 0x0C8
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___POR 0x064
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___M 0x1C000000
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___S              26
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___M 0x02000000
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___S              25
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___M 0x01F00000
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___S              20
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___M 0x000FFC00
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___S              10
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___S               0
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L___M     0x1FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_POW_DET_L___S                   0

#define PHYA_RXTD_DET0_RADAR_POW_DET_U            (0x003A054C)
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U___POR   0x0C8053CD
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___POR 0x32
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___POR 0x014
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___POR 0x3
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___POR 0xCD
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___M 0x1FC00000
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___S              22
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___M 0x003FFC00
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___S              10
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___M 0x00000300
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___S               8
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___M 0x000000FF
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___S               0
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U___M     0x1FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_POW_DET_U___S                   0

#define PHYA_RXTD_DET0_RADAR_FFT_THR_L            (0x003A0550)
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L___POR   0x841905D4
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___POR 0x8
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___POR 0x4
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___POR 0x064
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___POR 0x17
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___POR 0x14
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___M 0xF0000000
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___S              28
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___M 0x0F000000
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___S              24
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___M 0x00FFC000
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___S              14
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___M 0x00003FC0
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___S               6
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___M 0x0000003F
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___S               0
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L___M     0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_L___S                   0

#define PHYA_RXTD_DET0_RADAR_FFT_THR_U            (0x003A0554)
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U___POR   0x00000005
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___POR 0x5
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___M 0x00000010
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___S               4
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___M 0x0000000F
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___S               0
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U___M     0x0000001F   
#define   PHYA_RXTD_DET0_RADAR_FFT_THR_U___S                   0

#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L           (0x003A0558)
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___POR  0x400FFFC1
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___POR 0x400
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___POR 0x1
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___POR 0x1
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___POR 0xFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___POR 0x1
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___M 0xFFF00000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___S              20
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___M 0x00080000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___S              19
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___M 0x00040000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___S              18
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___M 0x0003FFC0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___S               6
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___M 0x00000030
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___S               4
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___M 0x0000000C
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___S               2
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___M 0x00000002
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___S               1
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___M 0x00000001
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___M    0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___S                  0

#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U           (0x003A055C)
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___POR  0x00500802
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___POR 0x05
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___POR 0x002
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___POR 0x002
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___M 0x03F00000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___S              20
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___M 0x000FFC00
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___S              10
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___M 0x000003FF
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___M    0x03FFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___S                  0

#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L         (0x003A0560)
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___POR 0x009B170B
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___POR 0x09B
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___POR 0x17
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___POR 0x0B
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___M 0x03FF0000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___S              16
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___M 0x0000FF00
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___S               8
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___M 0x000000FF
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___M  0x03FFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___S                0

#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U         (0x003A0564)
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___POR 0x0023FCC8
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___POR 0x2
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___POR 0x3
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___POR 0x3F
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___POR 0x0C8
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___M 0x00800000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___S              23
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___M 0x00700000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___S              20
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___M 0x000F0000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___S              16
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___M 0x0000FC00
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___S              10
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___M 0x000003FF
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___M  0x00FFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___S                0

#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L         (0x003A0568)
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___POR 0x0000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___M 0x001F0000
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___S              16
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___M 0x0000FFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___M  0x001FFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___S                0

#define PHYA_RXTD_DET0_RADAR_TIME_THR_L           (0x003A0570)
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L___POR  0x20141928
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___POR 0x20
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___POR 0x14
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___POR 0x19
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___POR 0x28
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___M 0x3F000000
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___S              24
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___M 0x00FF0000
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___S              16
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___M 0x0000FF00
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___S               8
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___M 0x000000FF
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___S               0
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L___M    0x3FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_L___S                  0

#define PHYA_RXTD_DET0_RADAR_TIME_THR_U           (0x003A0574)
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U___POR  0x05031405
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___POR 0x14
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___POR 0x03
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___POR 0x05
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___POR 0x005
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___M 0x0FC00000
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___S              22
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___M 0x003F0000
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___S              16
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___M 0x0000FC00
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___S              10
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___S               0
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U___M    0x0FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_TIME_THR_U___S                  0

#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L          (0x003A0578)
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L___POR 0x3B11A815
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___POR 0x0E
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___POR 0x62
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___POR 0x0D
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___POR 0x10
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___POR 0x0A
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___M 0xFC000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___S              26
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___M 0x03F80000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___S              19
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___M 0x0007E000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___S              13
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___M 0x00001F80
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___S               7
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___M 0x0000007E
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___S               1
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L___M   0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_L___S                 0

#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U          (0x003A057C)
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U___POR 0x000AB38E
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___POR 0x55
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___POR 0x0E
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___POR 0x0E
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___M 0x01000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___S              24
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___M 0x00F00000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___S              20
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___M 0x000FE000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___S              13
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___M 0x00001000
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___S              12
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___M 0x00000FC0
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___S               6
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___M 0x0000003F
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U___M   0x01FFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_THR_U___S                 0

#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L        (0x003A0580)
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___RWC  QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___POR 0x02D06C0A
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___POR 0x6
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___POR 0x8
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___POR 0x3
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___POR 0x0C
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___POR 0x01
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___POR 0x2
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___M 0x02000000
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___S              25
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___M 0x01E00000
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___S              21
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___M 0x001E0000
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___S              17
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___M 0x0001E000
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___S              13
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___M 0x00001F00
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___S               8
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___M 0x000000F8
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___S               3
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___M 0x00000007
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___S               0
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___M 0x03FFFFFF   
#define   PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___S               0

#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L            (0x003A0588)
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L___POR   0x0081C850
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___POR 0x20
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___POR 0xC8
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___POR 0x50
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___M 0x03FC0000
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___S              18
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___M 0x00020000
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___S              17
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___S              16
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___M 0x0000FF00
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___S               8
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___M 0x000000FF
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___S               0
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L___M     0x03FFFFFF   
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_L___S                   0

#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U            (0x003A058C)
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U___POR   0x00066A05
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___POR 0x19
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___POR 0x0A
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___POR 0x05
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___M 0x000FC000
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___S              14
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___M 0x00002000
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___S              13
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___M 0x00001F00
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___S               8
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___M 0x000000FF
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___S               0
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U___M     0x000FFFFF   
#define   PHYA_RXTD_DET0_RADAR_LB_CTRL_U___S                   0

#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L           (0x003A0590)
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___POR  0x001BA050
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___POR 0x0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___POR 0x0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___POR 0x01B
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___POR 0xA0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___POR 0x5
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___POR 0x0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___POR 0x0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___M 0x20000000
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___S              29
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___M 0x10000000
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___S              28
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___M 0x0FFF0000
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___S              16
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___M 0x0000FF00
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___S               8
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___M 0x000000F0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___S               4
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___M 0x0000000E
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___S               1
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___M 0x00000001
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___S               0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___M    0x3FFFFFFF   
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___S                  0

#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L           (0x003A0598)
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___POR  0x00080C00
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___POR 0x0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___POR 0x08
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___POR 0x0C
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___POR 0x00
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___M 0x03C00000
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___S              22
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___M 0x003F0000
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___S              16
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___M 0x0000FF00
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___S               8
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___M 0x000000FF
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___S               0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___M    0x03FFFFFF   
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___S                  0

#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U           (0x003A059C)
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___POR  0x0000000A
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___POR 0x00A
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___M 0x000003FF
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___S               0
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___M    0x000003FF   
#define   PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___S                  0

#define PHYA_RXTD_DET0_RADAR_START_0_L            (0x003A05A0)
#define   PHYA_RXTD_DET0_RADAR_START_0_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_START_0_L___POR   0x00000000
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___M 0x01000000
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___S              24
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___S              16
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___S               8
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___S               0
#define   PHYA_RXTD_DET0_RADAR_START_0_L___M     0x01010101   
#define   PHYA_RXTD_DET0_RADAR_START_0_L___S                   0

#define PHYA_RXTD_DET0_RADAR_START_0_U            (0x003A05A4)
#define   PHYA_RXTD_DET0_RADAR_START_0_U___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_START_0_U___POR   0x00000000
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___M 0x01000000
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___S              24
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___S              16
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___S               8
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___S               0
#define   PHYA_RXTD_DET0_RADAR_START_0_U___M     0x01010101   
#define   PHYA_RXTD_DET0_RADAR_START_0_U___S                   0

#define PHYA_RXTD_DET0_RADAR_START_1_L            (0x003A05A8)
#define   PHYA_RXTD_DET0_RADAR_START_1_L___RWC      QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_START_1_L___POR   0x00000000
#define   PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___S               0
#define   PHYA_RXTD_DET0_RADAR_START_1_L___M     0x00000001   
#define   PHYA_RXTD_DET0_RADAR_START_1_L___S                   0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L       (0x003A05B0)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___M 0x00000001   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U       (0x003A05B4)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___M 0x01000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___S              24
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___S              16
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___S               8
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___M 0x01010101   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L       (0x003A05B8)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___POR 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___S              16
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___S               8
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___M 0x00010101   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L      (0x003A05C0)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___M 0x00000001   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U      (0x003A05C4)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___M 0x01000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___S              24
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___S              16
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___S               8
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___M 0x01010101   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L      (0x003A05C8)
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___POR 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___POR 0x1
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___M 0x00010000
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___S              16
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___M 0x00000100
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___S               8
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___M 0x00010101   
#define   PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___S               0

#define PHYA_RXTD_DET0_RTT_CONFIG_0_L             (0x003A05D0)
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L___POR    0x09140001
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___POR 0x09
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___POR 0x14
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___POR 0x00
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___POR 0x1
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___M 0x1F000000
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___S              24
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___M 0x00FF0000
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___S              16
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___M 0x0000FF00
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___S               8
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___M 0x00000001
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___S               0
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L___M      0x1FFFFF01   
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_L___S                    0

#define PHYA_RXTD_DET0_RTT_CONFIG_0_U             (0x003A05D4)
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U___POR    0x00000000
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___POR 0x0
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___POR 0x0
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___POR 0x00
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___POR 0x00
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___M 0x01000000
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___S              24
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___M 0x00010000
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___S              16
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___M 0x0000FF00
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___S               8
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___M 0x0000001F
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___S               0
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U___M      0x0101FF1F   
#define   PHYA_RXTD_DET0_RTT_CONFIG_0_U___S                    0

#define PHYA_RXTD_DET0_RTT_CONFIG_1_L             (0x003A05D8)
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L___POR    0x00000019
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___POR 0x00
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___POR 0x0
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___POR 0x0
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___POR 0x19
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___M 0xFF000000
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___S              24
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___M 0x00010000
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___S              16
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___M 0x00000100
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___S               8
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___M 0x0000003F
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___S               0
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L___M      0xFF01013F   
#define   PHYA_RXTD_DET0_RTT_CONFIG_1_L___S                    0

#define PHYA_RXTD_DET0_RXTD_SPARE_L               (0x003A05E0)
#define   PHYA_RXTD_DET0_RXTD_SPARE_L___RWC         QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RXTD_SPARE_L___POR      0x00000000
#define   PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___POR 0x00000000
#define   PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___S               0
#define   PHYA_RXTD_DET0_RXTD_SPARE_L___M        0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RXTD_SPARE_L___S                      0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L     (0x003A05E8)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___S               0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U     (0x003A05EC)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___POR 0x00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___POR 0x00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___POR 0x0000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___M 0xFF000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___S              24
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___M 0x00FF0000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___S              16
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___M 0x0000FFFF
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___S               0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L     (0x003A05F0)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___POR 0x00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___POR 0x0000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___M 0x3FC00000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___S              22
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___M 0x00200000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___S              21
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___M 0x001FFFE0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___S               5
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___M 0x0000001C
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___S               2
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___M 0x00000003
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___M 0x3FFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___S               0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U     (0x003A05F4)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___POR 0x00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___M 0x0000003F
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___M 0x0000003F   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___S               0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L     (0x003A05F8)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___POR 0x000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___POR 0x00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___POR 0x000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___M 0x80000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___S              31
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___M 0x40000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___S              30
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___M 0x3FF00000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___S              20
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___M 0x000F0000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___S              16
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___M 0x0000FC00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___S              10
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___S               0

#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U     (0x003A05FC)
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___POR 0x0000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___POR 0x000
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___M 0x03FFFC00
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___S              10
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___M 0x000003FF
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___S               0
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___M 0x03FFFFFF   
#define   PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___S               0

#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L     (0x003A0600)
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___S               0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___S               0

#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U     (0x003A0604)
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___POR 0x00
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___POR 0x00
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___POR 0x0000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___M 0xFF000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___S              24
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___M 0x00FF0000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___S              16
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___M 0x0000FFFF
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___S               0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___S               0

#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L     (0x003A0608)
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___POR 0x000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___POR 0x00
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___POR 0x00
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___M 0x80000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___S              31
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___M 0x60000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___S              29
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___M 0x10000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___S              28
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___M 0x0FFC0000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___S              18
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___M 0x00020000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___S              17
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___M 0x0001FE00
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___S               9
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___M 0x00000100
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___S               8
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___M 0x000000FF
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___S               0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___S               0

#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L     (0x003A0610)
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___POR 0x000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___POR 0x000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___M 0x003FF000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___S              12
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___M 0x00000FFF
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___S               0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___M 0x003FFFFF   
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___S               0

#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U     (0x003A0614)
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___RWC QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___POR 0x00000000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___POR 0x0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___POR 0x0000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___M 0x00010000
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___S              16
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___M 0x0000FFFF
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___S               0
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___M 0x0001FFFF   
#define   PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___S               0

#define PHYA_RXTD_DET0_RADAR_EVENT_L              (0x003A0618)
#define   PHYA_RXTD_DET0_RADAR_EVENT_L___RWC        QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT_L___POR     0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___M 0x00000080
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___S               7
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___M 0x00000040
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___S               6
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___M 0x00000020
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___S               5
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___M 0x00000010
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___S               4
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___M 0x00000008
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___S               3
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___M 0x00000004
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___S               2
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___M 0x00000002
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___S               1
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT_L___M       0x000000FF   
#define   PHYA_RXTD_DET0_RADAR_EVENT_L___S                     0

#define PHYA_RXTD_DET0_RADAR_EVENT2_L             (0x003A0620)
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L___RWC       QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L___POR    0x00000000
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___POR 0x0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___M 0x00000080
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___S               7
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___M 0x00000040
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___S               6
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___M 0x00000020
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___S               5
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___M 0x00000010
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___S               4
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___M 0x00000008
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___S               3
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___M 0x00000004
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___S               2
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___M 0x00000002
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___S               1
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___M 0x00000001
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___S               0
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L___M      0x000000FF   
#define   PHYA_RXTD_DET0_RADAR_EVENT2_L___S                    0

#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L        (0x003A0628)
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U        (0x003A062C)
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___POR 0x0000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___M 0xFF000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___S              24
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___M 0x00FF0000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___S              16
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___M 0x0000FFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L        (0x003A0630)
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___POR 0x000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___POR 0x0000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___M 0x3FF80000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___S              19
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___M 0x0007FFE0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___S               5
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___M 0x0000001C
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___S               2
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___M 0x00000003
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___M 0x3FFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U        (0x003A0634)
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___POR 0x000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___POR 0x0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___M 0x000FF000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___S              12
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___M 0x00000FF8
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___S               3
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___M 0x00000007
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___M 0x000FFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L        (0x003A0638)
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___POR 0x000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___POR 0x00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___M 0xFE000000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___S              25
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___M 0x01FC0000
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___S              18
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___M 0x0003FF00
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___S               8
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___M 0x000000FF
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n(n) (0x003A0640+0x8*(n))
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_nMIN 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_nMAX 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_ELEM 1    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___S               0
#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0       (0x003A0640)
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0__DET0_0_FFT_OUT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0__DET0_0_FFT_OUT_MEM___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n(n) (0x003A0644+0x8*(n))
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_nMIN 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_nMAX 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_ELEM 1    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___S               0
#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0       (0x003A0644)
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0__DET0_1_FFT_OUT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0__DET0_1_FFT_OUT_MEM___S               0

#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L       (0x003A1640)
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___POR 0x00000000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___S              16
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___S               0
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___S               0

#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U       (0x003A1644)
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___POR 0x00000000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___S              16
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___S               0
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___S               0

#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L       (0x003A1648)
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___RWC QCSR_REG_RW    
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___POR 0x0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___M 0xFFFF0000
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___S              16
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___M 0x0000FFFF
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___S               0
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___M 0xFFFFFFFF   
#define   PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n(n) (0x003A1650+0x8*(n))
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_nMIN 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_nMAX 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_ELEM 1    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___POR  0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___M    0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___S                  0
#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0           (0x003A1650)
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0__DET0_0_FFT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0__DET0_0_FFT_MEM___S               0

#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n(n) (0x003A1654+0x8*(n))
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_nMIN 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_nMAX 0    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_ELEM 1    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___POR  0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___POR 0x00000000
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___S               0
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___M    0xFFFFFFFF   
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___S                  0
#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0           (0x003A1654)
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0___RWC     QCSR_REG_RW    
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0__DET0_1_FFT_MEM___M 0xFFFFFFFF
#define   PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0__DET0_1_FFT_MEM___S               0

#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L         (0x003A2650)
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___M 0x01000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___S              24
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___M 0x000F0000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___S              16
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___M 0x00000100
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___S               8
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___M 0x00000007
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___S               0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___M  0x010F0107   
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___S                0

#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U         (0x003A2654)
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___RWC   QCSR_REG_RW    
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___POR 0x00000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___POR 0x00
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___M 0x01000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___S              24
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___M 0x00FF0000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___S              16
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___M 0x00000300
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___S               8
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___M 0x00000003
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___S               0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___M  0x01FF0303   
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___S                0

#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L         (0x003A2658)
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___RWC   QCSR_REG_RO    
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___POR 0x00000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___POR 0x0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___POR 0x00
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___POR 0x0000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___M 0x01000000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___S              24
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___M 0x00FF0000
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___S              16
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___M 0x0000FFFF
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___S               0
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___M  0x01FFFFFF   
#define   PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___S                0

#define PHYA_RXTD_ASTF_CONFIG_L                   (0x003A2660)
#define   PHYA_RXTD_ASTF_CONFIG_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_ASTF_CONFIG_L___POR          0x000084A8
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___POR 0x01
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___POR 0x01
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___POR 0x05
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___POR 0x4
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___POR 0x0
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___M 0x000F8000
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___S              15
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___M 0x00007C00
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___S              10
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___M 0x000003E0
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___S               5
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___M 0x0000001E
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___S               1
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___M 0x00000001
#define   PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___S               0
#define   PHYA_RXTD_ASTF_CONFIG_L___M            0x000FFFFF   
#define   PHYA_RXTD_ASTF_CONFIG_L___S                          0

#define PHYA_RXTD_ABTCF_CONFIG_L                  (0x003A2668)
#define   PHYA_RXTD_ABTCF_CONFIG_L___RWC            QCSR_REG_RW    
#define   PHYA_RXTD_ABTCF_CONFIG_L___POR         0x00000078
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___POR 0x03C
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___POR 0x0
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___M 0x000003FE
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___S               1
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___M 0x00000001
#define   PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___S               0
#define   PHYA_RXTD_ABTCF_CONFIG_L___M           0x000003FF   
#define   PHYA_RXTD_ABTCF_CONFIG_L___S                         0

#define PHYA_RXTD_ABTCF_CONFIG_2_L                (0x003A2670)
#define   PHYA_RXTD_ABTCF_CONFIG_2_L___RWC          QCSR_REG_RW    
#define   PHYA_RXTD_ABTCF_CONFIG_2_L___POR       0x00001103
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___POR 0x08
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___POR 0x103
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___M 0x0001FE00
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___S               9
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___M 0x000001FF
#define   PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___S               0
#define   PHYA_RXTD_ABTCF_CONFIG_2_L___M         0x0001FFFF   
#define   PHYA_RXTD_ABTCF_CONFIG_2_L___S                       0

#define PHYA_RXTD_ECTE_CONFIG_L                   (0x003A2678)
#define   PHYA_RXTD_ECTE_CONFIG_L___RWC             QCSR_REG_RW    
#define   PHYA_RXTD_ECTE_CONFIG_L___POR          0x001EF780
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___POR 0x3DE
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___POR 0x3C0
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___POR 0x0
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___M 0x001FF800
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___S              11
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___M 0x000007FE
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___S               1
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___M 0x00000001
#define   PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___S               0
#define   PHYA_RXTD_ECTE_CONFIG_L___M            0x001FFFFF   
#define   PHYA_RXTD_ECTE_CONFIG_L___S                          0

#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0   (0x003A4000)
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___POR 0x000
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___POR 0x0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___POR 0x0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___M 0x0000FFC0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___S               6
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___M 0x00000038
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___S               3
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___M 0x00000007
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___S               0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___M 0x0000FFFF   
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___S               0

#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1   (0x003A5000)
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___POR 0x000
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___POR 0x0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___POR 0x0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___M 0x0000FFC0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___S               6
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___M 0x00000038
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___S               3
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___M 0x00000007
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___S               0
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___M 0x0000FFFF   
#define   PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0          (0x003A4008)
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___POR 0x0000004E
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___POR 0x04E
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___M   0x000003FF   
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___S                 0

#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1          (0x003A5008)
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___POR 0x0000004E
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___POR 0x04E
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___M   0x000003FF   
#define   PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___S                 0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0 (0x003A4010)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1 (0x003A5010)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0 (0x003A4014)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___POR 0x0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___M 0x00000003
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___M 0x00000003   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1 (0x003A5014)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___POR 0x0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___M 0x00000003
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___M 0x00000003   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0 (0x003A4018)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1 (0x003A5018)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0 (0x003A4020)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1 (0x003A5020)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0 (0x003A4024)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___POR 0x0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___M 0x00000003
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___M 0x00000003   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1 (0x003A5024)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___POR 0x0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___M 0x00000003
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___M 0x00000003   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0 (0x003A4028)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1 (0x003A5028)
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___POR 0x00000
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___M 0x000FFFFF
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___S               0
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___M 0x000FFFFF   
#define   PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0 (0x003A4030)
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___S              16
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___S               0
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1 (0x003A5030)
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___S              16
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___S               0
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0 (0x003A4034)
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___S              16
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___S               0
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___S               0

#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1 (0x003A5034)
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___S              16
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___S               0
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___S               0

#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0 (0x003A4038)
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___S              16
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___S               0
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___S               0

#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1 (0x003A5038)
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___S              16
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___S               0
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___S               0

#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0 (0x003A403C)
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___S              16
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___S               0
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___S               0

#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1 (0x003A503C)
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___S              16
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___S               0
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___S               0

#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0    (0x003A4040)
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___S              16
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___S               0
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___S               0

#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1    (0x003A5040)
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___POR 0x000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___S              16
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___S               0
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___S               0

#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0    (0x003A4044)
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___POR 0x00000400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___S              16
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___S               0
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___S               0

#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1    (0x003A5044)
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___POR 0x00000400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___POR 0x000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___M 0x0FFF0000
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___S              16
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___S               0
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___S               0

#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0   (0x003A4048)
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___POR 0x04000400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___M 0x0FFF0000
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___S              16
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___S               0
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___S               0

#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1   (0x003A5048)
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___POR 0x04000400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___POR 0x400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___POR 0x400
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___M 0x0FFF0000
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___S              16
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___M 0x00000FFF
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___S               0
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0  (0x003A4050)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___POR 0x032C032C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___POR 0x32C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___POR 0x32C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1  (0x003A5050)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___POR 0x032C032C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___POR 0x32C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___POR 0x32C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0  (0x003A4054)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___POR 0x000F019C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___POR 0x0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___POR 0xF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___POR 0x19C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___M 0x01000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___S              24
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___M 0x000F0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___M 0x000001FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___M 0x010F01FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1  (0x003A5054)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___RWC QCSR_REG_RW    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___POR 0x000F019C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___POR 0x0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___POR 0xF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___POR 0x19C
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___M 0x01000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___S              24
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___M 0x000F0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___M 0x000001FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___M 0x010F01FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___S               0

#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0        (0x003A4058)
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___POR 0x00008080
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___POR 0x00
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___POR 0x80
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___POR 0x80
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___M 0x03000000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___S              24
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___M 0x00FF0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___S              16
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___M 0x0000FF00
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___S               8
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___M 0x000000FF
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___S               0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___M 0x03FFFFFF   
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___S               0

#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1        (0x003A5058)
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___POR 0x00008080
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___POR 0x00
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___POR 0x80
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___POR 0x80
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___M 0x03000000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___S              24
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___M 0x00FF0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___S              16
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___M 0x0000FF00
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___S               8
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___M 0x000000FF
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___S               0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___M 0x03FFFFFF   
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___S               0

#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0        (0x003A405C)
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___POR 0x0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___M 0xFFFF0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___S              16
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___M 0x00000100
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___S               8
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___M 0x00000001
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___S               0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___M 0xFFFF0101   
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___S               0

#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1        (0x003A505C)
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___RWC  QCSR_REG_RO    
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___POR 0x0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___POR 0x0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___M 0xFFFF0000
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___S              16
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___M 0x00000100
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___S               8
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___M 0x00000001
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___S               0
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___M 0xFFFF0101   
#define   PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0  (0x003A4060)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___M 0x0FFF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___M 0x00000FFF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1  (0x003A5060)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___M 0x0FFF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___M 0x00000FFF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___M 0x0FFF0FFF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0  (0x003A4064)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___M 0x00000FFF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___M 0x00000FFF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1  (0x003A5064)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___POR 0x00000000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___POR 0x000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___M 0x00000FFF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___M 0x00000FFF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0 (0x003A4068)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1 (0x003A5068)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0 (0x003A406C)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1 (0x003A506C)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0 (0x003A4070)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1 (0x003A5070)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0 (0x003A4074)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___S               0

#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1 (0x003A5074)
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___POR 0x02000200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___POR 0x200
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___M 0x03FF0000
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___S              16
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___M 0x000003FF
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___S               0
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___M 0x03FF03FF   
#define   PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___S               0

#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0              (0x003A4078)
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0___RWC        QCSR_REG_RO    
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0___POR     0x00000000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___POR 0x0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___POR 0x0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___M 0xFFFF0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___S              16
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___M 0x0000FFFF
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___S               0
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0___M       0xFFFFFFFF   
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B0___S                     0

#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1              (0x003A5078)
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1___RWC        QCSR_REG_RO    
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1___POR     0x00000000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___POR 0x0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___POR 0x0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___M 0xFFFF0000
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___S              16
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___M 0x0000FFFF
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___S               0
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1___M       0xFFFFFFFF   
#define   PHYA_RXTD_CHN_LB_DC_OFF_L_B1___S                     0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0           (0x003A4080)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___RWC     QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___POR  0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___M    0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___S                  0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1           (0x003A5080)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___RWC     QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___POR  0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___M    0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___S                  0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0      (0x003A4088)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1      (0x003A5088)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0       (0x003A4090)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1       (0x003A5090)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0     (0x003A4098)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1     (0x003A5098)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0 (0x003A40A0)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1 (0x003A50A0)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0 (0x003A40A8)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1 (0x003A50A8)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0       (0x003A40B0)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1       (0x003A50B0)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0  (0x003A40B8)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1  (0x003A50B8)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0   (0x003A40C0)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1   (0x003A50C0)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0 (0x003A40C8)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___S               0

#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1 (0x003A50C8)
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0 (0x003A40D0)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___S               0

#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1 (0x003A50D0)
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0 (0x003A40D8)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___S               0

#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1 (0x003A50D8)
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___RWC QCSR_REG_RO    
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___S               0
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___M 0xFFFFFFFF   
#define   PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___S               0

#define PHYA_TXTD_RESET_CTRL_L                    (0x003B0000)
#define   PHYA_TXTD_RESET_CTRL_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_RESET_CTRL_L___POR           0x00000000
#define   PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___POR 0x0
#define   PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___M 0x00000001
#define   PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___S               0
#define   PHYA_TXTD_RESET_CTRL_L___M             0x00000001   
#define   PHYA_TXTD_RESET_CTRL_L___S                           0

#define PHYA_TXTD_TX_CTRL_L                       (0x003B0008)
#define   PHYA_TXTD_TX_CTRL_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXTD_TX_CTRL_L___POR              0x00000000
#define   PHYA_TXTD_TX_CTRL_L__TX_ABORT___POR    0x0
#define   PHYA_TXTD_TX_CTRL_L__TX_ABORT___M      0x00000001
#define   PHYA_TXTD_TX_CTRL_L__TX_ABORT___S                    0
#define   PHYA_TXTD_TX_CTRL_L___M                0x00000001   
#define   PHYA_TXTD_TX_CTRL_L___S                              0

#define PHYA_TXTD_ECO_CONTROL_L                   (0x003B0010)
#define   PHYA_TXTD_ECO_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ECO_CONTROL_L___POR          0x00000000
#define   PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___M  0xFFFFFFFF
#define   PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___S                0
#define   PHYA_TXTD_ECO_CONTROL_L___M            0xFFFFFFFF   
#define   PHYA_TXTD_ECO_CONTROL_L___S                          0

#define PHYA_TXTD_ECO_CONTROL_U                   (0x003B0014)
#define   PHYA_TXTD_ECO_CONTROL_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ECO_CONTROL_U___POR          0x00000000
#define   PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000
#define   PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___M   0xFFFFFFFF
#define   PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___S                 0
#define   PHYA_TXTD_ECO_CONTROL_U___M            0xFFFFFFFF   
#define   PHYA_TXTD_ECO_CONTROL_U___S                          0

#define PHYA_TXTD_ECO_STATUS_L                    (0x003B0018)
#define   PHYA_TXTD_ECO_STATUS_L___RWC              QCSR_REG_RO    
#define   PHYA_TXTD_ECO_STATUS_L___POR           0x00000000
#define   PHYA_TXTD_ECO_STATUS_L__ECO_STAT___POR 0x00000000
#define   PHYA_TXTD_ECO_STATUS_L__ECO_STAT___M   0xFFFFFFFF
#define   PHYA_TXTD_ECO_STATUS_L__ECO_STAT___S                 0
#define   PHYA_TXTD_ECO_STATUS_L___M             0xFFFFFFFF   
#define   PHYA_TXTD_ECO_STATUS_L___S                           0

#define PHYA_TXTD_EVENT_STATUS_L                  (0x003B0020)
#define   PHYA_TXTD_EVENT_STATUS_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_EVENT_STATUS_L___POR         0x00000000
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___M 0x00008000
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___S              15
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___M 0x00004000
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___S              14
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___M 0x00002000
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___S              13
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___M 0x00001000
#define   PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___S              12
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___M 0x00000800
#define   PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___S              11
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___M 0x00000400
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___S              10
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___M 0x00000200
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___S               9
#define   PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___M 0x00000100
#define   PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___S               8
#define   PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___M 0x00000080
#define   PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___S               7
#define   PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___M 0x00000040
#define   PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___S               6
#define   PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___M 0x00000020
#define   PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___S               5
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___M 0x00000010
#define   PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___S               4
#define   PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___M 0x00000008
#define   PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___S               3
#define   PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___M 0x00000004
#define   PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___S               2
#define   PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_TXTD_EVENT_STATUS_L___M           0x0000FFFF   
#define   PHYA_TXTD_EVENT_STATUS_L___S                         0

#define PHYA_TXTD_EVENT_MASK_L                    (0x003B0028)
#define   PHYA_TXTD_EVENT_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_EVENT_MASK_L___POR           0x0000FFFF
#define   PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___M 0x00008000
#define   PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___S              15
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___M 0x00004000
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___S              14
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___M 0x00002000
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___S              13
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___M 0x00001000
#define   PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___S              12
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___M 0x00000800
#define   PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___S              11
#define   PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___M 0x00000400
#define   PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___S              10
#define   PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___M 0x00000200
#define   PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___S               9
#define   PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___M 0x00000100
#define   PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___S               8
#define   PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___M 0x00000080
#define   PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___S               7
#define   PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___M 0x00000040
#define   PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___S               6
#define   PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___M 0x00000020
#define   PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___S               5
#define   PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___M 0x00000010
#define   PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___S               4
#define   PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___M 0x00000008
#define   PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___S               3
#define   PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___M 0x00000004
#define   PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___S               2
#define   PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_TXTD_EVENT_MASK_L___M             0x0000FFFF   
#define   PHYA_TXTD_EVENT_MASK_L___S                           0

#define PHYA_TXTD_ERROR_CODE_L                    (0x003B0030)
#define   PHYA_TXTD_ERROR_CODE_L___RWC              QCSR_REG_RO    
#define   PHYA_TXTD_ERROR_CODE_L___POR           0x00000000
#define   PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___POR 0x00000000
#define   PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF
#define   PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_TXTD_ERROR_CODE_L___M             0xFFFFFFFF   
#define   PHYA_TXTD_ERROR_CODE_L___S                           0

#define PHYA_TXTD_ERROR_STATUS_L                  (0x003B0038)
#define   PHYA_TXTD_ERROR_STATUS_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_ERROR_STATUS_L___POR         0x00000000
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___POR 0x0
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___M 0x00800000
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___S              23
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___M 0x00400000
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___S              22
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___M 0x00200000
#define   PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___S              21
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___M 0x00100000
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___S              20
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___M 0x00080000
#define   PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___S              19
#define   PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___M 0x00040000
#define   PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___S              18
#define   PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___M 0x00020000
#define   PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___S              17
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___M 0x00010000
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___S              16
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___M 0x00008000
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___S              15
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___M 0x00004000
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___S              14
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___M 0x00002000
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___S              13
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___M 0x00001000
#define   PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___S              12
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___M 0x00000800
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___S              11
#define   PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___M 0x00000400
#define   PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___S              10
#define   PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___M 0x00000200
#define   PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___S               9
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___M 0x00000100
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___S               8
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___M 0x00000080
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___S               7
#define   PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___M 0x00000040
#define   PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___S               6
#define   PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___M 0x00000020
#define   PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___S               5
#define   PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___M 0x00000010
#define   PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___S               4
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___M 0x00000008
#define   PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___S               3
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___M 0x00000004
#define   PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___S               2
#define   PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___M 0x00000002
#define   PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___S               1
#define   PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___M 0x00000001
#define   PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___S               0
#define   PHYA_TXTD_ERROR_STATUS_L___M           0x00FFFFFF   
#define   PHYA_TXTD_ERROR_STATUS_L___S                         0

#define PHYA_TXTD_ERROR_STATUS_U                  (0x003B003C)
#define   PHYA_TXTD_ERROR_STATUS_U___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_ERROR_STATUS_U___POR         0x00000000
#define   PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___POR 0x0000
#define   PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___M 0x0000FFFF
#define   PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___S               0
#define   PHYA_TXTD_ERROR_STATUS_U___M           0x0000FFFF   
#define   PHYA_TXTD_ERROR_STATUS_U___S                         0

#define PHYA_TXTD_ERROR_MASK_L                    (0x003B0040)
#define   PHYA_TXTD_ERROR_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_ERROR_MASK_L___POR           0x00FFFFFF
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___M 0x00800000
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___S              23
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___M 0x00400000
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___S              22
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___M 0x00200000
#define   PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___S              21
#define   PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___M 0x00100000
#define   PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___S              20
#define   PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___M 0x00080000
#define   PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___S              19
#define   PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___M 0x00040000
#define   PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___S              18
#define   PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___M 0x00020000
#define   PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___S              17
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___M 0x00010000
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___S              16
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___M 0x00008000
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___S              15
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___M 0x00004000
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___S              14
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___M 0x00002000
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___S              13
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___M 0x00001000
#define   PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___S              12
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___M 0x00000800
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___S              11
#define   PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___M 0x00000400
#define   PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___S              10
#define   PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___M 0x00000200
#define   PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___S               9
#define   PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___M 0x00000100
#define   PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___S               8
#define   PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___M 0x00000080
#define   PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___S               7
#define   PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___M 0x00000040
#define   PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___S               6
#define   PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___M 0x00000020
#define   PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___S               5
#define   PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___M 0x00000010
#define   PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___S               4
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___M 0x00000008
#define   PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___S               3
#define   PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___M 0x00000004
#define   PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___S               2
#define   PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___M 0x00000002
#define   PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___S               1
#define   PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___M 0x00000001
#define   PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___S               0
#define   PHYA_TXTD_ERROR_MASK_L___M             0x00FFFFFF   
#define   PHYA_TXTD_ERROR_MASK_L___S                           0

#define PHYA_TXTD_ERROR_MASK_U                    (0x003B0044)
#define   PHYA_TXTD_ERROR_MASK_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_ERROR_MASK_U___POR           0x0000FFFF
#define   PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___POR 0xFFFF
#define   PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___M 0x0000FFFF
#define   PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___S               0
#define   PHYA_TXTD_ERROR_MASK_U___M             0x0000FFFF   
#define   PHYA_TXTD_ERROR_MASK_U___S                           0

#define PHYA_TXTD_CORE_STATUS_L                   (0x003B0048)
#define   PHYA_TXTD_CORE_STATUS_L___RWC             QCSR_REG_RO    
#define   PHYA_TXTD_CORE_STATUS_L___POR          0x00000000
#define   PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___POR 0x00000000
#define   PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___S               0
#define   PHYA_TXTD_CORE_STATUS_L___M            0xFFFFFFFF   
#define   PHYA_TXTD_CORE_STATUS_L___S                          0

#define PHYA_TXTD_CORE_STATUS_U                   (0x003B004C)
#define   PHYA_TXTD_CORE_STATUS_U___RWC             QCSR_REG_RO    
#define   PHYA_TXTD_CORE_STATUS_U___POR          0x00000000
#define   PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___POR 0x00000000
#define   PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___S               0
#define   PHYA_TXTD_CORE_STATUS_U___M            0xFFFFFFFF   
#define   PHYA_TXTD_CORE_STATUS_U___S                          0

#define PHYA_TXTD_DATA_DUMP_CTRL_L                (0x003B0050)
#define   PHYA_TXTD_DATA_DUMP_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_DATA_DUMP_CTRL_L___POR       0x0000000F
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___POR 0x0
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___POR 0x0
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___POR 0x0
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___POR 0xF
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___M 0x03000000
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___S              24
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___M 0x00030000
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___S              16
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___M 0x00000700
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___S               8
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___M 0x0000000F
#define   PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___S               0
#define   PHYA_TXTD_DATA_DUMP_CTRL_L___M         0x0303070F   
#define   PHYA_TXTD_DATA_DUMP_CTRL_L___S                       0

#define PHYA_TXTD_DATA_DUMP_CTRL_U                (0x003B0054)
#define   PHYA_TXTD_DATA_DUMP_CTRL_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_DATA_DUMP_CTRL_U___POR       0x00000000
#define   PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___POR 0x0
#define   PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___M 0x00000003
#define   PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___S               0
#define   PHYA_TXTD_DATA_DUMP_CTRL_U___M         0x00000003   
#define   PHYA_TXTD_DATA_DUMP_CTRL_U___S                       0

#define PHYA_TXTD_PUBLIC_SPARE_L                  (0x003B0058)
#define   PHYA_TXTD_PUBLIC_SPARE_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_PUBLIC_SPARE_L___POR         0x00000000
#define   PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S               0
#define   PHYA_TXTD_PUBLIC_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_PUBLIC_SPARE_L___S                         0

#define PHYA_TXTD_PUBLIC_SPARE_U                  (0x003B005C)
#define   PHYA_TXTD_PUBLIC_SPARE_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_PUBLIC_SPARE_U___POR         0x00CC0000
#define   PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00CC0000
#define   PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S               0
#define   PHYA_TXTD_PUBLIC_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_PUBLIC_SPARE_U___S                         0

#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n(n) (0x003B0060+0x8*(n))
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_nMIN 0    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_nMAX 0    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_ELEM 1    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___POR   0x00000000
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___POR 0x0000000
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___M 0x0FFFFFFF
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___S               0
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___M     0x0FFFFFFF   
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___S                   0
#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_0            (0x003B0060)
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_0___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_0__TX_FIR_COEFF_0___M 0x0FFFFFFF
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_L_0__TX_FIR_COEFF_0___S               0

#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n(n) (0x003B0064+0x8*(n))
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_nMIN 0    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_nMAX 0    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_ELEM 1    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___POR   0x00000000
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___POR 0x0000000
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___M 0x0FFFFFFF
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___S               0
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___M     0x0FFFFFFF   
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___S                   0
#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_0            (0x003B0064)
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_0___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_0__TX_FIR_COEFF_1___M 0x0FFFFFFF
#define   PHYA_TXTD_TX_FIR_COEFF_MEM_U_0__TX_FIR_COEFF_1___S               0

#define PHYA_TXTD_CLOCK_GATING_0_L                (0x003B0360)
#define   PHYA_TXTD_CLOCK_GATING_0_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_CLOCK_GATING_0_L___POR       0x00000000
#define   PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___M 0x00000001
#define   PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___S               0
#define   PHYA_TXTD_CLOCK_GATING_0_L___M         0x00000001   
#define   PHYA_TXTD_CLOCK_GATING_0_L___S                       0

#define PHYA_TXTD_CLOCK_GATING_1_L                (0x003B0368)
#define   PHYA_TXTD_CLOCK_GATING_1_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_CLOCK_GATING_1_L___POR       0x00000000
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___M 0x01000000
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___S              24
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___M 0x00010000
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___S              16
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___M 0x00000100
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___S               8
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___M 0x00000001
#define   PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___S               0
#define   PHYA_TXTD_CLOCK_GATING_1_L___M         0x01010101   
#define   PHYA_TXTD_CLOCK_GATING_1_L___S                       0

#define PHYA_TXTD_CLOCK_GATING_1_U                (0x003B036C)
#define   PHYA_TXTD_CLOCK_GATING_1_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_CLOCK_GATING_1_U___POR       0x00000000
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___POR 0x0
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___M 0x00000300
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___S               8
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___M 0x00000001
#define   PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___S               0
#define   PHYA_TXTD_CLOCK_GATING_1_U___M         0x00000301   
#define   PHYA_TXTD_CLOCK_GATING_1_U___S                       0

#define PHYA_TXTD_GEN_CONTROLS_0_L                (0x003B0370)
#define   PHYA_TXTD_GEN_CONTROLS_0_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_GEN_CONTROLS_0_L___POR       0x00010300
#define   PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___POR 0x1
#define   PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___POR 0x3
#define   PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___M 0x00010000
#define   PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___S              16
#define   PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___M 0x00000300
#define   PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___S               8
#define   PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___M 0x00000007
#define   PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___S               0
#define   PHYA_TXTD_GEN_CONTROLS_0_L___M         0x00010307   
#define   PHYA_TXTD_GEN_CONTROLS_0_L___S                       0

#define PHYA_TXTD_GEN_CONTROLS_1_L                (0x003B0378)
#define   PHYA_TXTD_GEN_CONTROLS_1_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_GEN_CONTROLS_1_L___POR       0x00000100
#define   PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___POR 0x1
#define   PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___POR 0x00
#define   PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___M 0x00000100
#define   PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___S               8
#define   PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___M 0x0000007F
#define   PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___S               0
#define   PHYA_TXTD_GEN_CONTROLS_1_L___M         0x0000017F   
#define   PHYA_TXTD_GEN_CONTROLS_1_L___S                       0

#define PHYA_TXTD_GEN_CONTROLS_1_U                (0x003B037C)
#define   PHYA_TXTD_GEN_CONTROLS_1_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_GEN_CONTROLS_1_U___POR       0x0223001F
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___POR 0x1
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___POR 0x0
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___POR 0x2
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___POR 0x3
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___POR 0x001F
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___M 0x10000000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___S              28
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___M 0x08000000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___S              27
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___M 0x04000000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___S              26
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___M 0x02000000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___S              25
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___M 0x01000000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___S              24
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___M 0x00800000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___S              23
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___M 0x00700000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___S              20
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___M 0x000F0000
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___S              16
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___M 0x0000FFFF
#define   PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___S               0
#define   PHYA_TXTD_GEN_CONTROLS_1_U___M         0x1FFFFFFF   
#define   PHYA_TXTD_GEN_CONTROLS_1_U___S                       0

#define PHYA_TXTD_TX_VSRC_GAIN_L                  (0x003B0380)
#define   PHYA_TXTD_TX_VSRC_GAIN_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_VSRC_GAIN_L___POR         0x00000030
#define   PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___POR 0x30
#define   PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___M 0x000000FF
#define   PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___S               0
#define   PHYA_TXTD_TX_VSRC_GAIN_L___M           0x000000FF   
#define   PHYA_TXTD_TX_VSRC_GAIN_L___S                         0

#define PHYA_TXTD_PHYDBG_L                        (0x003B0388)
#define   PHYA_TXTD_PHYDBG_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXTD_PHYDBG_L___POR               0x0000000F
#define   PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___POR  0xF
#define   PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___M    0x0000000F
#define   PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___S                  0
#define   PHYA_TXTD_PHYDBG_L___M                 0x0000000F   
#define   PHYA_TXTD_PHYDBG_L___S                               0

#define PHYA_TXTD_PRETXFIR0_COEFF0_L              (0x003B0390)
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF0_L___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF0_U              (0x003B0394)
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U___POR     0x03FA0000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___POR 0x3FA
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF0_U___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF1_L              (0x003B0398)
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L___POR     0x0041001C
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___POR 0x041
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___POR 0x01C
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF1_L___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF1_U              (0x003B039C)
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U___POR     0x00410052
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___POR 0x041
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___POR 0x052
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF1_U___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF2_L              (0x003B03A0)
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L___POR     0x03FA001C
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___POR 0x3FA
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___POR 0x01C
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF2_L___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF2_U              (0x003B03A4)
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF2_U___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF3_L              (0x003B03A8)
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF3_L___S                     0

#define PHYA_TXTD_PRETXFIR0_COEFF3_U              (0x003B03AC)
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___S              16
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___S               0
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR0_COEFF3_U___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF0_L              (0x003B03B0)
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L___POR     0x03F303FC
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___POR 0x3F3
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___POR 0x3FC
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF0_L___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF0_U              (0x003B03B4)
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U___POR     0x000103EF
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___POR 0x001
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___POR 0x3EF
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF0_U___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF1_L              (0x003B03B8)
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L___POR     0x004C0026
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___POR 0x04C
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___POR 0x026
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF1_L___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF1_U              (0x003B03BC)
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U___POR     0x004C005D
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___POR 0x04C
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___POR 0x05D
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF1_U___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF2_L              (0x003B03C0)
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L___POR     0x00010026
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___POR 0x001
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___POR 0x026
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF2_L___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF2_U              (0x003B03C4)
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U___POR     0x03F303EF
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___POR 0x3F3
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___POR 0x3EF
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF2_U___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF3_L              (0x003B03C8)
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L___POR     0x000003FC
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___POR 0x3FC
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF3_L___S                     0

#define PHYA_TXTD_PRETXFIR1_COEFF3_U              (0x003B03CC)
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___S              16
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___S               0
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR1_COEFF3_U___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF0_L              (0x003B03D0)
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L___POR     0x03EE03F9
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___POR 0x3EE
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___POR 0x3F9
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF0_L___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF0_U              (0x003B03D4)
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U___POR     0x000403F2
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___POR 0x004
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___POR 0x3F2
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF0_U___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF1_L              (0x003B03D8)
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L___POR     0x004C0029
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___POR 0x04C
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___POR 0x029
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF1_L___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF1_U              (0x003B03DC)
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U___POR     0x004C005C
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___POR 0x04C
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___POR 0x05C
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF1_U___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF2_L              (0x003B03E0)
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L___POR     0x00040029
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___POR 0x004
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___POR 0x029
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF2_L___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF2_U              (0x003B03E4)
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U___POR     0x03EE03F2
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___POR 0x3EE
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___POR 0x3F2
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF2_U___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF3_L              (0x003B03E8)
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L___POR     0x000003F9
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___POR 0x3F9
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF3_L___S                     0

#define PHYA_TXTD_PRETXFIR2_COEFF3_U              (0x003B03EC)
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U___POR     0x00000000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___POR 0x000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___M 0x03FF0000
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___S              16
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___M 0x000003FF
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___S               0
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U___M       0x03FF03FF   
#define   PHYA_TXTD_PRETXFIR2_COEFF3_U___S                     0

#define PHYA_TXTD_TX_FIR_CNTL_L                   (0x003B03F0)
#define   PHYA_TXTD_TX_FIR_CNTL_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_TX_FIR_CNTL_L___POR          0x00000000
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___POR 0x0
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___POR 0x0
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___M 0x00000100
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___S               8
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___M 0x0000000F
#define   PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___S               0
#define   PHYA_TXTD_TX_FIR_CNTL_L___M            0x0000010F   
#define   PHYA_TXTD_TX_FIR_CNTL_L___S                          0

#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L            (0x003B03F8)
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L___POR   0x00000001
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___POR 0x1
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___M 0x00000001
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___S               0
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L___M     0x00000001   
#define   PHYA_TXTD_PAPRD_TRAINER_CTRL_L___S                   0

#define PHYA_TXTD_PRIVATE_SPARE_L                 (0x003B0400)
#define   PHYA_TXTD_PRIVATE_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_TXTD_PRIVATE_SPARE_L___POR        0x00000000
#define   PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S               0
#define   PHYA_TXTD_PRIVATE_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_TXTD_PRIVATE_SPARE_L___S                        0

#define PHYA_TXTD_PRIVATE_SPARE_U                 (0x003B0404)
#define   PHYA_TXTD_PRIVATE_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_TXTD_PRIVATE_SPARE_U___POR        0x00000000
#define   PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S               0
#define   PHYA_TXTD_PRIVATE_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_TXTD_PRIVATE_SPARE_U___S                        0

#define PHYA_TXTD_TX_PRE_DESC_WR_0_L              (0x003B0408)
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_L___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_0_U              (0x003B040C)
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_0_U___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_1_L              (0x003B0410)
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_L___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_1_U              (0x003B0414)
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_1_U___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_2_L              (0x003B0418)
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_L___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_2_U              (0x003B041C)
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_2_U___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_3_L              (0x003B0420)
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L___POR     0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_3_L___S                     0

#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L          (0x003B0428)
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___S                 0

#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U          (0x003B042C)
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___S               0
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___S                 0

#define PHYA_TXTD_TX_DESC_WR_0_L                  (0x003B0430)
#define   PHYA_TXTD_TX_DESC_WR_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_0_L___POR         0x00000000
#define   PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___S               0
#define   PHYA_TXTD_TX_DESC_WR_0_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_0_L___S                         0

#define PHYA_TXTD_TX_DESC_WR_0_U                  (0x003B0434)
#define   PHYA_TXTD_TX_DESC_WR_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_0_U___POR         0x00000000
#define   PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___S               0
#define   PHYA_TXTD_TX_DESC_WR_0_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_0_U___S                         0

#define PHYA_TXTD_TX_DESC_WR_1_L                  (0x003B0438)
#define   PHYA_TXTD_TX_DESC_WR_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_1_L___POR         0x00000000
#define   PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___S               0
#define   PHYA_TXTD_TX_DESC_WR_1_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_1_L___S                         0

#define PHYA_TXTD_TX_DESC_WR_1_U                  (0x003B043C)
#define   PHYA_TXTD_TX_DESC_WR_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_1_U___POR         0x00000000
#define   PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___S               0
#define   PHYA_TXTD_TX_DESC_WR_1_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_1_U___S                         0

#define PHYA_TXTD_TX_DESC_WR_2_L                  (0x003B0440)
#define   PHYA_TXTD_TX_DESC_WR_2_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_2_L___POR         0x00000000
#define   PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___S               0
#define   PHYA_TXTD_TX_DESC_WR_2_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_2_L___S                         0

#define PHYA_TXTD_TX_DESC_WR_SPARE_L              (0x003B0448)
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L___POR     0x00000000
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___S               0
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_SPARE_L___S                     0

#define PHYA_TXTD_TX_DESC_WR_SPARE_U              (0x003B044C)
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U___POR     0x00000000
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___S               0
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_TX_DESC_WR_SPARE_U___S                     0

#define PHYA_TXTD_ULD0_DESC_0_L                   (0x003B0450)
#define   PHYA_TXTD_ULD0_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD0_DESC_0_L___POR          0x01400000
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___POR 0x140
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD0_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD0_DESC_0_L___S                          0

#define PHYA_TXTD_ULD0_DESC_0_U                   (0x003B0454)
#define   PHYA_TXTD_ULD0_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD0_DESC_0_U___POR          0x01010100
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD0_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD0_DESC_0_U___S                          0

#define PHYA_TXTD_ULD0_DESC_1_L                   (0x003B0458)
#define   PHYA_TXTD_ULD0_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD0_DESC_1_L___POR          0x01000100
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___POR 0x1
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___POR 0x01
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD0_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD0_DESC_1_L___S                          0

#define PHYA_TXTD_ULD0_DESC_1_U                   (0x003B045C)
#define   PHYA_TXTD_ULD0_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD0_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD0_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD0_DESC_1_U___S                          0

#define PHYA_TXTD_ULD1_DESC_0_L                   (0x003B0460)
#define   PHYA_TXTD_ULD1_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD1_DESC_0_L___POR          0x01400040
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___POR 0x140
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___POR 0x040
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD1_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD1_DESC_0_L___S                          0

#define PHYA_TXTD_ULD1_DESC_0_U                   (0x003B0464)
#define   PHYA_TXTD_ULD1_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD1_DESC_0_U___POR          0x01010102
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD1_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD1_DESC_0_U___S                          0

#define PHYA_TXTD_ULD1_DESC_1_L                   (0x003B0468)
#define   PHYA_TXTD_ULD1_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD1_DESC_1_L___POR          0x00010300
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___POR 0x1
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___POR 0x03
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD1_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD1_DESC_1_L___S                          0

#define PHYA_TXTD_ULD1_DESC_1_U                   (0x003B046C)
#define   PHYA_TXTD_ULD1_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD1_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD1_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD1_DESC_1_U___S                          0

#define PHYA_TXTD_ULD2_DESC_0_L                   (0x003B0470)
#define   PHYA_TXTD_ULD2_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD2_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD2_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD2_DESC_0_L___S                          0

#define PHYA_TXTD_ULD2_DESC_0_U                   (0x003B0474)
#define   PHYA_TXTD_ULD2_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD2_DESC_0_U___POR          0x01010102
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD2_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD2_DESC_0_U___S                          0

#define PHYA_TXTD_ULD2_DESC_1_L                   (0x003B0478)
#define   PHYA_TXTD_ULD2_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD2_DESC_1_L___POR          0x00000300
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___POR 0x03
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD2_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD2_DESC_1_L___S                          0

#define PHYA_TXTD_ULD2_DESC_1_U                   (0x003B047C)
#define   PHYA_TXTD_ULD2_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD2_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD2_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD2_DESC_1_U___S                          0

#define PHYA_TXTD_ULD3_DESC_0_L                   (0x003B0480)
#define   PHYA_TXTD_ULD3_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD3_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD3_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD3_DESC_0_L___S                          0

#define PHYA_TXTD_ULD3_DESC_0_U                   (0x003B0484)
#define   PHYA_TXTD_ULD3_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD3_DESC_0_U___POR          0x01010002
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD3_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD3_DESC_0_U___S                          0

#define PHYA_TXTD_ULD3_DESC_1_L                   (0x003B0488)
#define   PHYA_TXTD_ULD3_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD3_DESC_1_L___POR          0x00000300
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___POR 0x03
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD3_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD3_DESC_1_L___S                          0

#define PHYA_TXTD_ULD3_DESC_1_U                   (0x003B048C)
#define   PHYA_TXTD_ULD3_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD3_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD3_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD3_DESC_1_U___S                          0

#define PHYA_TXTD_ULD4_DESC_0_L                   (0x003B0490)
#define   PHYA_TXTD_ULD4_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD4_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD4_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD4_DESC_0_L___S                          0

#define PHYA_TXTD_ULD4_DESC_0_U                   (0x003B0494)
#define   PHYA_TXTD_ULD4_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD4_DESC_0_U___POR          0x02010102
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD4_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD4_DESC_0_U___S                          0

#define PHYA_TXTD_ULD4_DESC_1_L                   (0x003B0498)
#define   PHYA_TXTD_ULD4_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD4_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD4_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD4_DESC_1_L___S                          0

#define PHYA_TXTD_ULD4_DESC_1_U                   (0x003B049C)
#define   PHYA_TXTD_ULD4_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD4_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD4_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD4_DESC_1_U___S                          0

#define PHYA_TXTD_ULD5_DESC_0_L                   (0x003B04A0)
#define   PHYA_TXTD_ULD5_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD5_DESC_0_L___POR          0x00A00000
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD5_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD5_DESC_0_L___S                          0

#define PHYA_TXTD_ULD5_DESC_0_U                   (0x003B04A4)
#define   PHYA_TXTD_ULD5_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD5_DESC_0_U___POR          0x02010100
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD5_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD5_DESC_0_U___S                          0

#define PHYA_TXTD_ULD5_DESC_1_L                   (0x003B04A8)
#define   PHYA_TXTD_ULD5_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD5_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD5_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD5_DESC_1_L___S                          0

#define PHYA_TXTD_ULD5_DESC_1_U                   (0x003B04AC)
#define   PHYA_TXTD_ULD5_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD5_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD5_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD5_DESC_1_U___S                          0

#define PHYA_TXTD_ULD6_DESC_0_L                   (0x003B04B0)
#define   PHYA_TXTD_ULD6_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD6_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD6_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD6_DESC_0_L___S                          0

#define PHYA_TXTD_ULD6_DESC_0_U                   (0x003B04B4)
#define   PHYA_TXTD_ULD6_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD6_DESC_0_U___POR          0x02010102
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD6_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD6_DESC_0_U___S                          0

#define PHYA_TXTD_ULD6_DESC_1_L                   (0x003B04B8)
#define   PHYA_TXTD_ULD6_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD6_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD6_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD6_DESC_1_L___S                          0

#define PHYA_TXTD_ULD6_DESC_1_U                   (0x003B04BC)
#define   PHYA_TXTD_ULD6_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD6_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD6_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD6_DESC_1_U___S                          0

#define PHYA_TXTD_ULD7_DESC_0_L                   (0x003B04C0)
#define   PHYA_TXTD_ULD7_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD7_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD7_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD7_DESC_0_L___S                          0

#define PHYA_TXTD_ULD7_DESC_0_U                   (0x003B04C4)
#define   PHYA_TXTD_ULD7_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD7_DESC_0_U___POR          0x02010102
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD7_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD7_DESC_0_U___S                          0

#define PHYA_TXTD_ULD7_DESC_1_L                   (0x003B04C8)
#define   PHYA_TXTD_ULD7_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD7_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD7_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD7_DESC_1_L___S                          0

#define PHYA_TXTD_ULD7_DESC_1_U                   (0x003B04CC)
#define   PHYA_TXTD_ULD7_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD7_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD7_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD7_DESC_1_U___S                          0

#define PHYA_TXTD_ULD8_DESC_0_L                   (0x003B04D0)
#define   PHYA_TXTD_ULD8_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD8_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD8_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD8_DESC_0_L___S                          0

#define PHYA_TXTD_ULD8_DESC_0_U                   (0x003B04D4)
#define   PHYA_TXTD_ULD8_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD8_DESC_0_U___POR          0x02010102
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___POR 0x1
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD8_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD8_DESC_0_U___S                          0

#define PHYA_TXTD_ULD8_DESC_1_L                   (0x003B04D8)
#define   PHYA_TXTD_ULD8_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD8_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD8_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD8_DESC_1_L___S                          0

#define PHYA_TXTD_ULD8_DESC_1_U                   (0x003B04DC)
#define   PHYA_TXTD_ULD8_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD8_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD8_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD8_DESC_1_U___S                          0

#define PHYA_TXTD_ULD9_DESC_0_L                   (0x003B04E0)
#define   PHYA_TXTD_ULD9_DESC_0_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD9_DESC_0_L___POR          0x00A00060
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___POR 0x0A0
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___POR 0x060
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD9_DESC_0_L___M            0x0FFF0FFF   
#define   PHYA_TXTD_ULD9_DESC_0_L___S                          0

#define PHYA_TXTD_ULD9_DESC_0_U                   (0x003B04E4)
#define   PHYA_TXTD_ULD9_DESC_0_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD9_DESC_0_U___POR          0x02010002
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___POR 0x2
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD9_DESC_0_U___M            0x0F0F0F0F   
#define   PHYA_TXTD_ULD9_DESC_0_U___S                          0

#define PHYA_TXTD_ULD9_DESC_1_L                   (0x003B04E8)
#define   PHYA_TXTD_ULD9_DESC_1_L___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD9_DESC_1_L___POR          0x00000000
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD9_DESC_1_L___M            0x01011F1F   
#define   PHYA_TXTD_ULD9_DESC_1_L___S                          0

#define PHYA_TXTD_ULD9_DESC_1_U                   (0x003B04EC)
#define   PHYA_TXTD_ULD9_DESC_1_U___RWC             QCSR_REG_RW    
#define   PHYA_TXTD_ULD9_DESC_1_U___POR          0x00000000
#define   PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD9_DESC_1_U___M            0x00000007   
#define   PHYA_TXTD_ULD9_DESC_1_U___S                          0

#define PHYA_TXTD_ULD10_DESC_0_L                  (0x003B04F0)
#define   PHYA_TXTD_ULD10_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD10_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD10_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD10_DESC_0_L___S                         0

#define PHYA_TXTD_ULD10_DESC_0_U                  (0x003B04F4)
#define   PHYA_TXTD_ULD10_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD10_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD10_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD10_DESC_0_U___S                         0

#define PHYA_TXTD_ULD10_DESC_1_L                  (0x003B04F8)
#define   PHYA_TXTD_ULD10_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD10_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD10_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD10_DESC_1_L___S                         0

#define PHYA_TXTD_ULD10_DESC_1_U                  (0x003B04FC)
#define   PHYA_TXTD_ULD10_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD10_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD10_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD10_DESC_1_U___S                         0

#define PHYA_TXTD_ULD11_DESC_0_L                  (0x003B0500)
#define   PHYA_TXTD_ULD11_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD11_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD11_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD11_DESC_0_L___S                         0

#define PHYA_TXTD_ULD11_DESC_0_U                  (0x003B0504)
#define   PHYA_TXTD_ULD11_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD11_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD11_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD11_DESC_0_U___S                         0

#define PHYA_TXTD_ULD11_DESC_1_L                  (0x003B0508)
#define   PHYA_TXTD_ULD11_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD11_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD11_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD11_DESC_1_L___S                         0

#define PHYA_TXTD_ULD11_DESC_1_U                  (0x003B050C)
#define   PHYA_TXTD_ULD11_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD11_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD11_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD11_DESC_1_U___S                         0

#define PHYA_TXTD_ULD12_DESC_0_L                  (0x003B0510)
#define   PHYA_TXTD_ULD12_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD12_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD12_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD12_DESC_0_L___S                         0

#define PHYA_TXTD_ULD12_DESC_0_U                  (0x003B0514)
#define   PHYA_TXTD_ULD12_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD12_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD12_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD12_DESC_0_U___S                         0

#define PHYA_TXTD_ULD12_DESC_1_L                  (0x003B0518)
#define   PHYA_TXTD_ULD12_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD12_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD12_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD12_DESC_1_L___S                         0

#define PHYA_TXTD_ULD12_DESC_1_U                  (0x003B051C)
#define   PHYA_TXTD_ULD12_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD12_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD12_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD12_DESC_1_U___S                         0

#define PHYA_TXTD_ULD13_DESC_0_L                  (0x003B0520)
#define   PHYA_TXTD_ULD13_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD13_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD13_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD13_DESC_0_L___S                         0

#define PHYA_TXTD_ULD13_DESC_0_U                  (0x003B0524)
#define   PHYA_TXTD_ULD13_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD13_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD13_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD13_DESC_0_U___S                         0

#define PHYA_TXTD_ULD13_DESC_1_L                  (0x003B0528)
#define   PHYA_TXTD_ULD13_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD13_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD13_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD13_DESC_1_L___S                         0

#define PHYA_TXTD_ULD13_DESC_1_U                  (0x003B052C)
#define   PHYA_TXTD_ULD13_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD13_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD13_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD13_DESC_1_U___S                         0

#define PHYA_TXTD_ULD14_DESC_0_L                  (0x003B0530)
#define   PHYA_TXTD_ULD14_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD14_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD14_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD14_DESC_0_L___S                         0

#define PHYA_TXTD_ULD14_DESC_0_U                  (0x003B0534)
#define   PHYA_TXTD_ULD14_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD14_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD14_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD14_DESC_0_U___S                         0

#define PHYA_TXTD_ULD14_DESC_1_L                  (0x003B0538)
#define   PHYA_TXTD_ULD14_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD14_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD14_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD14_DESC_1_L___S                         0

#define PHYA_TXTD_ULD14_DESC_1_U                  (0x003B053C)
#define   PHYA_TXTD_ULD14_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD14_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD14_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD14_DESC_1_U___S                         0

#define PHYA_TXTD_ULD15_DESC_0_L                  (0x003B0540)
#define   PHYA_TXTD_ULD15_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD15_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD15_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD15_DESC_0_L___S                         0

#define PHYA_TXTD_ULD15_DESC_0_U                  (0x003B0544)
#define   PHYA_TXTD_ULD15_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD15_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD15_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD15_DESC_0_U___S                         0

#define PHYA_TXTD_ULD15_DESC_1_L                  (0x003B0548)
#define   PHYA_TXTD_ULD15_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD15_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD15_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD15_DESC_1_L___S                         0

#define PHYA_TXTD_ULD15_DESC_1_U                  (0x003B054C)
#define   PHYA_TXTD_ULD15_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD15_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD15_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD15_DESC_1_U___S                         0

#define PHYA_TXTD_ULD16_DESC_0_L                  (0x003B0550)
#define   PHYA_TXTD_ULD16_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD16_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD16_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD16_DESC_0_L___S                         0

#define PHYA_TXTD_ULD16_DESC_0_U                  (0x003B0554)
#define   PHYA_TXTD_ULD16_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD16_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD16_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD16_DESC_0_U___S                         0

#define PHYA_TXTD_ULD16_DESC_1_L                  (0x003B0558)
#define   PHYA_TXTD_ULD16_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD16_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD16_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD16_DESC_1_L___S                         0

#define PHYA_TXTD_ULD16_DESC_1_U                  (0x003B055C)
#define   PHYA_TXTD_ULD16_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD16_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD16_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD16_DESC_1_U___S                         0

#define PHYA_TXTD_ULD17_DESC_0_L                  (0x003B0560)
#define   PHYA_TXTD_ULD17_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD17_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD17_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD17_DESC_0_L___S                         0

#define PHYA_TXTD_ULD17_DESC_0_U                  (0x003B0564)
#define   PHYA_TXTD_ULD17_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD17_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD17_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD17_DESC_0_U___S                         0

#define PHYA_TXTD_ULD17_DESC_1_L                  (0x003B0568)
#define   PHYA_TXTD_ULD17_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD17_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD17_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD17_DESC_1_L___S                         0

#define PHYA_TXTD_ULD17_DESC_1_U                  (0x003B056C)
#define   PHYA_TXTD_ULD17_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD17_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD17_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD17_DESC_1_U___S                         0

#define PHYA_TXTD_ULD18_DESC_0_L                  (0x003B0570)
#define   PHYA_TXTD_ULD18_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD18_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD18_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD18_DESC_0_L___S                         0

#define PHYA_TXTD_ULD18_DESC_0_U                  (0x003B0574)
#define   PHYA_TXTD_ULD18_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD18_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD18_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD18_DESC_0_U___S                         0

#define PHYA_TXTD_ULD18_DESC_1_L                  (0x003B0578)
#define   PHYA_TXTD_ULD18_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD18_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD18_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD18_DESC_1_L___S                         0

#define PHYA_TXTD_ULD18_DESC_1_U                  (0x003B057C)
#define   PHYA_TXTD_ULD18_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD18_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD18_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD18_DESC_1_U___S                         0

#define PHYA_TXTD_ULD19_DESC_0_L                  (0x003B0580)
#define   PHYA_TXTD_ULD19_DESC_0_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD19_DESC_0_L___POR         0x00000000
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___POR 0x000
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___POR 0x000
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___S              16
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___M 0x00000FFF
#define   PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___S               0
#define   PHYA_TXTD_ULD19_DESC_0_L___M           0x0FFF0FFF   
#define   PHYA_TXTD_ULD19_DESC_0_L___S                         0

#define PHYA_TXTD_ULD19_DESC_0_U                  (0x003B0584)
#define   PHYA_TXTD_ULD19_DESC_0_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD19_DESC_0_U___POR         0x00010000
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___S              24
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___S              16
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___M 0x00000F00
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___S               8
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___M 0x0000000F
#define   PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___S               0
#define   PHYA_TXTD_ULD19_DESC_0_U___M           0x0F0F0F0F   
#define   PHYA_TXTD_ULD19_DESC_0_U___S                         0

#define PHYA_TXTD_ULD19_DESC_1_L                  (0x003B0588)
#define   PHYA_TXTD_ULD19_DESC_1_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD19_DESC_1_L___POR         0x00000000
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___POR 0x00
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___POR 0x00
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___M 0x01000000
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___S              24
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___M 0x00010000
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___S              16
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___M 0x00001F00
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___S               8
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___M 0x0000001F
#define   PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___S               0
#define   PHYA_TXTD_ULD19_DESC_1_L___M           0x01011F1F   
#define   PHYA_TXTD_ULD19_DESC_1_L___S                         0

#define PHYA_TXTD_ULD19_DESC_1_U                  (0x003B058C)
#define   PHYA_TXTD_ULD19_DESC_1_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_ULD19_DESC_1_U___POR         0x00000000
#define   PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___POR 0x0
#define   PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___M 0x00000007
#define   PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___S               0
#define   PHYA_TXTD_ULD19_DESC_1_U___M           0x00000007   
#define   PHYA_TXTD_ULD19_DESC_1_U___S                         0

#define PHYA_TXTD_FW_DYN_CTRL_0_L                 (0x003B0590)
#define   PHYA_TXTD_FW_DYN_CTRL_0_L___RWC           QCSR_REG_RW    
#define   PHYA_TXTD_FW_DYN_CTRL_0_L___POR        0x00000000
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___POR 0x0
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___POR 0x0
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___M 0x00000100
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___S               8
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___M 0x00000001
#define   PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___S               0
#define   PHYA_TXTD_FW_DYN_CTRL_0_L___M          0x00000101   
#define   PHYA_TXTD_FW_DYN_CTRL_0_L___S                        0

#define PHYA_TXTD_FW_DYN_CTRL_1_L                 (0x003B0598)
#define   PHYA_TXTD_FW_DYN_CTRL_1_L___RWC           QCSR_REG_RW    
#define   PHYA_TXTD_FW_DYN_CTRL_1_L___POR        0x00000003
#define   PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___POR 0x3
#define   PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___M 0x00000003
#define   PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___S               0
#define   PHYA_TXTD_FW_DYN_CTRL_1_L___M          0x00000003   
#define   PHYA_TXTD_FW_DYN_CTRL_1_L___S                        0

#define PHYA_TXTD_TX_VSRC_L                       (0x003B05A0)
#define   PHYA_TXTD_TX_VSRC_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXTD_TX_VSRC_L___POR              0xAAAAAAAB
#define   PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___POR 0xAAAAAAAB
#define   PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___M 0xFFFFFFFF
#define   PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___S               0
#define   PHYA_TXTD_TX_VSRC_L___M                0xFFFFFFFF   
#define   PHYA_TXTD_TX_VSRC_L___S                              0

#define PHYA_TXTD_CFO_CTRL_L                      (0x003B05A8)
#define   PHYA_TXTD_CFO_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_TXTD_CFO_CTRL_L___POR             0x00000000
#define   PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___POR 0x0
#define   PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___M 0x00000001
#define   PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___S               0
#define   PHYA_TXTD_CFO_CTRL_L___M               0x00000001   
#define   PHYA_TXTD_CFO_CTRL_L___S                             0

#define PHYA_TXTD_CFO_CTRL_U                      (0x003B05AC)
#define   PHYA_TXTD_CFO_CTRL_U___RWC                QCSR_REG_RW    
#define   PHYA_TXTD_CFO_CTRL_U___POR             0x00000000
#define   PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___POR 0x00000
#define   PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___M 0x000FFFFF
#define   PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___S               0
#define   PHYA_TXTD_CFO_CTRL_U___M               0x000FFFFF   
#define   PHYA_TXTD_CFO_CTRL_U___S                             0

#define PHYA_TXTD_POWER_SCALING0_L                (0x003B05B0)
#define   PHYA_TXTD_POWER_SCALING0_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_POWER_SCALING0_L___POR       0x00400040
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___M 0x3FFF0000
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___S              16
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___M 0x00003FFF
#define   PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___S               0
#define   PHYA_TXTD_POWER_SCALING0_L___M         0x3FFF3FFF   
#define   PHYA_TXTD_POWER_SCALING0_L___S                       0

#define PHYA_TXTD_POWER_SCALING0_U                (0x003B05B4)
#define   PHYA_TXTD_POWER_SCALING0_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_POWER_SCALING0_U___POR       0x00400040
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___M 0x3FFF0000
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___S              16
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___M 0x00003FFF
#define   PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___S               0
#define   PHYA_TXTD_POWER_SCALING0_U___M         0x3FFF3FFF   
#define   PHYA_TXTD_POWER_SCALING0_U___S                       0

#define PHYA_TXTD_POWER_SCALING1_L                (0x003B05B8)
#define   PHYA_TXTD_POWER_SCALING1_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_POWER_SCALING1_L___POR       0x00400040
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___M 0x3FFF0000
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___S              16
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___M 0x00003FFF
#define   PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___S               0
#define   PHYA_TXTD_POWER_SCALING1_L___M         0x3FFF3FFF   
#define   PHYA_TXTD_POWER_SCALING1_L___S                       0

#define PHYA_TXTD_POWER_SCALING1_U                (0x003B05BC)
#define   PHYA_TXTD_POWER_SCALING1_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_POWER_SCALING1_U___POR       0x00400040
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___POR 0x0040
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___M 0x3FFF0000
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___S              16
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___M 0x00003FFF
#define   PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___S               0
#define   PHYA_TXTD_POWER_SCALING1_U___M         0x3FFF3FFF   
#define   PHYA_TXTD_POWER_SCALING1_U___S                       0

#define PHYA_TXTD_PRETXFIR_CTRL_L                 (0x003B05C0)
#define   PHYA_TXTD_PRETXFIR_CTRL_L___RWC           QCSR_REG_RW    
#define   PHYA_TXTD_PRETXFIR_CTRL_L___POR        0x00000000
#define   PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___POR 0x0
#define   PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___M 0x00000003
#define   PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___S               0
#define   PHYA_TXTD_PRETXFIR_CTRL_L___M          0x00000003   
#define   PHYA_TXTD_PRETXFIR_CTRL_L___S                        0

#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L             (0x003B05C8)
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L___POR    0x00000048
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___POR 0x48
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___M 0x0000007F
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___S               0
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L___M      0x0000007F   
#define   PHYA_TXTD_HEAVY_CLIP_FACTOR_L___S                    0

#define PHYA_TXTD_PWR_COMP_L                      (0x003B05D0)
#define   PHYA_TXTD_PWR_COMP_L___RWC                QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_L___POR             0x00000084
#define   PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___POR 0x84
#define   PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___S               0
#define   PHYA_TXTD_PWR_COMP_L___M               0x000000FF   
#define   PHYA_TXTD_PWR_COMP_L___S                             0

#define PHYA_TXTD_PKT_START_WR_SPARE_L            (0x003B05D8)
#define   PHYA_TXTD_PKT_START_WR_SPARE_L___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_PKT_START_WR_SPARE_L___POR   0x00000000
#define   PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___S               0
#define   PHYA_TXTD_PKT_START_WR_SPARE_L___M     0xFFFFFFFF   
#define   PHYA_TXTD_PKT_START_WR_SPARE_L___S                   0

#define PHYA_TXTD_PKT_START_WR_SPARE_U            (0x003B05DC)
#define   PHYA_TXTD_PKT_START_WR_SPARE_U___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_PKT_START_WR_SPARE_U___POR   0x00000000
#define   PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___S               0
#define   PHYA_TXTD_PKT_START_WR_SPARE_U___M     0xFFFFFFFF   
#define   PHYA_TXTD_PKT_START_WR_SPARE_U___S                   0

#define PHYA_TXTD_PKT_END_CTRL_0_L                (0x003B05E0)
#define   PHYA_TXTD_PKT_END_CTRL_0_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_CTRL_0_L___POR       0x0000000A
#define   PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___POR 0x0000000A
#define   PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___S               0
#define   PHYA_TXTD_PKT_END_CTRL_0_L___M         0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_CTRL_0_L___S                       0

#define PHYA_TXTD_PKT_END_CTRL_0_U                (0x003B05E4)
#define   PHYA_TXTD_PKT_END_CTRL_0_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_CTRL_0_U___POR       0x0000000A
#define   PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___POR 0x0000000A
#define   PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___S               0
#define   PHYA_TXTD_PKT_END_CTRL_0_U___M         0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_CTRL_0_U___S                       0

#define PHYA_TXTD_PKT_END_CTRL_1_L                (0x003B05E8)
#define   PHYA_TXTD_PKT_END_CTRL_1_L___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_CTRL_1_L___POR       0x00000040
#define   PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___POR 0x00000040
#define   PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___S               0
#define   PHYA_TXTD_PKT_END_CTRL_1_L___M         0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_CTRL_1_L___S                       0

#define PHYA_TXTD_PKT_END_CTRL_1_U                (0x003B05EC)
#define   PHYA_TXTD_PKT_END_CTRL_1_U___RWC          QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_CTRL_1_U___POR       0x00001900
#define   PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___POR 0x19
#define   PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___POR 0x0
#define   PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___M 0x00007F00
#define   PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___S               8
#define   PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___M 0x00000001
#define   PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___S               0
#define   PHYA_TXTD_PKT_END_CTRL_1_U___M         0x00007F01   
#define   PHYA_TXTD_PKT_END_CTRL_1_U___S                       0

#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L          (0x003B05F0)
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___RWC    QCSR_REG_RW    
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___POR 0x00000002
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___POR 0x2
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___M 0x0000000F
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___S               0
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___M   0x0000000F   
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___S                 0

#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U          (0x003B05F4)
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___RWC    QCSR_REG_RW    
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___POR 0x00000003
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___POR 0x3
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___M 0x0000000F
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___S               0
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___M   0x0000000F   
#define   PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___S                 0

#define PHYA_TXTD_TXTD_START_WR_SPARE_L           (0x003B05F8)
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L___RWC     QCSR_REG_RW    
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L___POR  0x00000000
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___S               0
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L___M    0xFFFFFFFF   
#define   PHYA_TXTD_TXTD_START_WR_SPARE_L___S                  0

#define PHYA_TXTD_TXTD_START_WR_SPARE_U           (0x003B05FC)
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U___RWC     QCSR_REG_RW    
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U___POR  0x00000000
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___S               0
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U___M    0xFFFFFFFF   
#define   PHYA_TXTD_TXTD_START_WR_SPARE_U___S                  0

#define PHYA_TXTD_TXTD_START_RD_SPARE_L           (0x003B0600)
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L___RWC     QCSR_REG_RO    
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L___POR  0x00000000
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___S               0
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L___M    0xFFFFFFFF   
#define   PHYA_TXTD_TXTD_START_RD_SPARE_L___S                  0

#define PHYA_TXTD_TXTD_START_RD_SPARE_U           (0x003B0604)
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U___RWC     QCSR_REG_RO    
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U___POR  0x00000000
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___S               0
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U___M    0xFFFFFFFF   
#define   PHYA_TXTD_TXTD_START_RD_SPARE_U___S                  0

#define PHYA_TXTD_SYM_WR_SPARE_L                  (0x003B0608)
#define   PHYA_TXTD_SYM_WR_SPARE_L___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_SYM_WR_SPARE_L___POR         0x00000000
#define   PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___S               0
#define   PHYA_TXTD_SYM_WR_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_SYM_WR_SPARE_L___S                         0

#define PHYA_TXTD_SYM_WR_SPARE_U                  (0x003B060C)
#define   PHYA_TXTD_SYM_WR_SPARE_U___RWC            QCSR_REG_RW    
#define   PHYA_TXTD_SYM_WR_SPARE_U___POR         0x00000000
#define   PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___S               0
#define   PHYA_TXTD_SYM_WR_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_SYM_WR_SPARE_U___S                         0

#define PHYA_TXTD_SYM_RD_L                        (0x003B0610)
#define   PHYA_TXTD_SYM_RD_L___RWC                  QCSR_REG_RO    
#define   PHYA_TXTD_SYM_RD_L___POR               0x00000000
#define   PHYA_TXTD_SYM_RD_L__CURR_DESC___POR    0x00
#define   PHYA_TXTD_SYM_RD_L__CURR_DESC___M      0x0000001F
#define   PHYA_TXTD_SYM_RD_L__CURR_DESC___S                    0
#define   PHYA_TXTD_SYM_RD_L___M                 0x0000001F   
#define   PHYA_TXTD_SYM_RD_L___S                               0

#define PHYA_TXTD_SYM_RD_SPARE_L                  (0x003B0618)
#define   PHYA_TXTD_SYM_RD_SPARE_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_SYM_RD_SPARE_L___POR         0x00000000
#define   PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___S               0
#define   PHYA_TXTD_SYM_RD_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_SYM_RD_SPARE_L___S                         0

#define PHYA_TXTD_SYM_RD_SPARE_U                  (0x003B061C)
#define   PHYA_TXTD_SYM_RD_SPARE_U___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_SYM_RD_SPARE_U___POR         0x00000000
#define   PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___S               0
#define   PHYA_TXTD_SYM_RD_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_SYM_RD_SPARE_U___S                         0

#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L            (0x003B0620)
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L___POR   0x00000000
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___S               0
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L___M     0xFFFFFFFF   
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_L___S                   0

#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U            (0x003B0624)
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U___RWC      QCSR_REG_RW    
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U___POR   0x00000000
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___S               0
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U___M     0xFFFFFFFF   
#define   PHYA_TXTD_MULTI_SYM_WR_SPARE_U___S                   0

#define PHYA_TXTD_MULTI_SYM_RD_L                  (0x003B0628)
#define   PHYA_TXTD_MULTI_SYM_RD_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_MULTI_SYM_RD_L___POR         0x00000000
#define   PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___POR 0x00
#define   PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___M 0x0000001F
#define   PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___S               0
#define   PHYA_TXTD_MULTI_SYM_RD_L___M           0x0000001F   
#define   PHYA_TXTD_MULTI_SYM_RD_L___S                         0

#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L            (0x003B0630)
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L___RWC      QCSR_REG_RO    
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L___POR   0x00000000
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___S               0
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L___M     0xFFFFFFFF   
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_L___S                   0

#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U            (0x003B0634)
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U___RWC      QCSR_REG_RO    
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U___POR   0x00000000
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___S               0
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U___M     0xFFFFFFFF   
#define   PHYA_TXTD_MULTI_SYM_RD_SPARE_U___S                   0

#define PHYA_TXTD_PRE_DATA_WR_SPARE_L             (0x003B0638)
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L___POR    0x00000000
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___S               0
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L___M      0xFFFFFFFF   
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_L___S                    0

#define PHYA_TXTD_PRE_DATA_WR_SPARE_U             (0x003B063C)
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U___POR    0x00000000
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___S               0
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U___M      0xFFFFFFFF   
#define   PHYA_TXTD_PRE_DATA_WR_SPARE_U___S                    0

#define PHYA_TXTD_PRE_DATA_RD_L                   (0x003B0640)
#define   PHYA_TXTD_PRE_DATA_RD_L___RWC             QCSR_REG_RO    
#define   PHYA_TXTD_PRE_DATA_RD_L___POR          0x00000000
#define   PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___POR 0x00
#define   PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___M 0x0000001F
#define   PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___S               0
#define   PHYA_TXTD_PRE_DATA_RD_L___M            0x0000001F   
#define   PHYA_TXTD_PRE_DATA_RD_L___S                          0

#define PHYA_TXTD_PRE_DATA_RD_SPARE_L             (0x003B0648)
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L___POR    0x00000000
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___S               0
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L___M      0xFFFFFFFF   
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_L___S                    0

#define PHYA_TXTD_PRE_DATA_RD_SPARE_U             (0x003B064C)
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U___POR    0x00000000
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___S               0
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U___M      0xFFFFFFFF   
#define   PHYA_TXTD_PRE_DATA_RD_SPARE_U___S                    0

#define PHYA_TXTD_PKT_DATA_WR_SPARE_L             (0x003B0650)
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L___POR    0x00000000
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___S               0
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L___M      0xFFFFFFFF   
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_L___S                    0

#define PHYA_TXTD_PKT_DATA_WR_SPARE_U             (0x003B0654)
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U___POR    0x00000000
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___S               0
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U___M      0xFFFFFFFF   
#define   PHYA_TXTD_PKT_DATA_WR_SPARE_U___S                    0

#define PHYA_TXTD_PKT_DATA_RD_SPARE_L             (0x003B0658)
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L___POR    0x00000000
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___S               0
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L___M      0xFFFFFFFF   
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_L___S                    0

#define PHYA_TXTD_PKT_DATA_RD_SPARE_U             (0x003B065C)
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U___POR    0x00000000
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___S               0
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U___M      0xFFFFFFFF   
#define   PHYA_TXTD_PKT_DATA_RD_SPARE_U___S                    0

#define PHYA_TXTD_PKT_END_WR_SPARE_L              (0x003B0660)
#define   PHYA_TXTD_PKT_END_WR_SPARE_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_WR_SPARE_L___POR     0x00000000
#define   PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___S               0
#define   PHYA_TXTD_PKT_END_WR_SPARE_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_WR_SPARE_L___S                     0

#define PHYA_TXTD_PKT_END_WR_SPARE_U              (0x003B0664)
#define   PHYA_TXTD_PKT_END_WR_SPARE_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PKT_END_WR_SPARE_U___POR     0x00000000
#define   PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___S               0
#define   PHYA_TXTD_PKT_END_WR_SPARE_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_WR_SPARE_U___S                     0

#define PHYA_TXTD_PKT_END_RD_0_L                  (0x003B0668)
#define   PHYA_TXTD_PKT_END_RD_0_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_0_L___POR         0x00000000
#define   PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___S               0
#define   PHYA_TXTD_PKT_END_RD_0_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_0_L___S                         0

#define PHYA_TXTD_PKT_END_RD_0_U                  (0x003B066C)
#define   PHYA_TXTD_PKT_END_RD_0_U___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_0_U___POR         0x00000000
#define   PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___S               0
#define   PHYA_TXTD_PKT_END_RD_0_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_0_U___S                         0

#define PHYA_TXTD_PKT_END_RD_1_L                  (0x003B0670)
#define   PHYA_TXTD_PKT_END_RD_1_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_1_L___POR         0x00000000
#define   PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___S               0
#define   PHYA_TXTD_PKT_END_RD_1_L___M           0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_1_L___S                         0

#define PHYA_TXTD_PKT_END_RD_1_U                  (0x003B0674)
#define   PHYA_TXTD_PKT_END_RD_1_U___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_1_U___POR         0x00000000
#define   PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___S               0
#define   PHYA_TXTD_PKT_END_RD_1_U___M           0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_1_U___S                         0

#define PHYA_TXTD_PKT_END_RD_2_L                  (0x003B0678)
#define   PHYA_TXTD_PKT_END_RD_2_L___RWC            QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_2_L___POR         0x00000000
#define   PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___POR 0x00
#define   PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___M 0x0000001F
#define   PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___S               0
#define   PHYA_TXTD_PKT_END_RD_2_L___M           0x0000001F   
#define   PHYA_TXTD_PKT_END_RD_2_L___S                         0

#define PHYA_TXTD_PKT_END_RD_SPARE_L              (0x003B0680)
#define   PHYA_TXTD_PKT_END_RD_SPARE_L___RWC        QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_SPARE_L___POR     0x00000000
#define   PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___S               0
#define   PHYA_TXTD_PKT_END_RD_SPARE_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_SPARE_L___S                     0

#define PHYA_TXTD_PKT_END_RD_SPARE_U              (0x003B0684)
#define   PHYA_TXTD_PKT_END_RD_SPARE_U___RWC        QCSR_REG_RO    
#define   PHYA_TXTD_PKT_END_RD_SPARE_U___POR     0x00000000
#define   PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___S               0
#define   PHYA_TXTD_PKT_END_RD_SPARE_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_PKT_END_RD_SPARE_U___S                     0

#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0        (0x003B0800)
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___POR 0x0
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___M 0x1F000000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___S              24
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___M 0x001F0000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___S              16
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___M 0x00001F00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___S               8
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___M 0x00000001
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___S               0
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___M 0x1F1F1F01   
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___S               0

#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1        (0x003B0C00)
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___POR 0x00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___POR 0x0
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___M 0x1F000000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___S              24
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___M 0x001F0000
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___S              16
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___M 0x00001F00
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___S               8
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___M 0x00000001
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___S               0
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___M 0x1F1F1F01   
#define   PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___S               0

#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0           (0x003B0808)
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___POR  0x00000000
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___POR 0x0
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___M 0x00000007
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___S               0
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___M    0x00000007   
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___S                  0

#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1           (0x003B0C08)
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___POR  0x00000000
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___POR 0x0
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___M 0x00000007
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___S               0
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___M    0x00000007   
#define   PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___S                  0

#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0   (0x003B0810)
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___POR 0x0
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___M 0x00000001
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___S               0
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___M 0x00000001   
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___S               0

#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1   (0x003B0C10)
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___POR 0x0
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___M 0x00000001
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___S               0
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___M 0x00000001   
#define   PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___S               0

#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0 (0x003B0818)
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___S               0
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___S               0

#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1 (0x003B0C18)
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___S               0
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___S               0

#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0 (0x003B081C)
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___S               0
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___S               0

#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1 (0x003B0C1C)
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___S               0
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___S               0

#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0         (0x003B0820)
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___RWC   QCSR_REG_RO    
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___POR 0x00000000
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___S               0
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___M  0xFFFFFFFF   
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___S                0

#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1         (0x003B0C20)
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___RWC   QCSR_REG_RO    
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___POR 0x00000000
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___S               0
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___M  0xFFFFFFFF   
#define   PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___S                0

#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0           (0x003B0828)
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0___RWC     QCSR_REG_RO    
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0___POR  0x00000000
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___POR 0x0000
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___M 0x001FFFE0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___S               5
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___M 0x00000010
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___S               4
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___M 0x00000008
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___S               3
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___M 0x00000004
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___S               2
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___M 0x00000002
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___S               1
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___M 0x00000001
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___S               0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0___M    0x001FFFFF   
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B0___S                  0

#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1           (0x003B0C28)
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1___RWC     QCSR_REG_RO    
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1___POR  0x00000000
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___POR 0x0000
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___POR 0x0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___M 0x001FFFE0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___S               5
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___M 0x00000010
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___S               4
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___M 0x00000008
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___S               3
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___M 0x00000004
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___S               2
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___M 0x00000002
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___S               1
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___M 0x00000001
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___S               0
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1___M    0x001FFFFF   
#define   PHYA_TXTD_CHN_ERROR_STATUS_L_B1___S                  0

#define PHYA_TXTD_CHN_ERROR_MASK_L_B0             (0x003B0830)
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0___POR    0x001FFFFF
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___POR 0xFFFF
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___M 0x001FFFE0
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___S               5
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___M 0x00000010
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___S               4
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___M 0x00000008
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___S               3
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___M 0x00000004
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___S               2
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___M 0x00000002
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___S               1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___M 0x00000001
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___S               0
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0___M      0x001FFFFF   
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B0___S                    0

#define PHYA_TXTD_CHN_ERROR_MASK_L_B1             (0x003B0C30)
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1___POR    0x001FFFFF
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___POR 0xFFFF
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___POR 0x1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___M 0x001FFFE0
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___S               5
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___M 0x00000010
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___S               4
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___M 0x00000008
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___S               3
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___M 0x00000004
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___S               2
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___M 0x00000002
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___S               1
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___M 0x00000001
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___S               0
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1___M      0x001FFFFF   
#define   PHYA_TXTD_CHN_ERROR_MASK_L_B1___S                    0

#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0      (0x003B0838)
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___S               0
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___S               0

#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1      (0x003B0C38)
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___S               0
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___S               0

#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0      (0x003B083C)
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___S               0
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___S               0

#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1      (0x003B0C3C)
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___S               0
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___S               0

#define PHYA_TXTD_CHN_STATUS_CHN_L_B0             (0x003B0840)
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0___POR    0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___S               0
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0___M      0xFFFFFFFF   
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B0___S                    0

#define PHYA_TXTD_CHN_STATUS_CHN_L_B1             (0x003B0C40)
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1___POR    0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___S               0
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1___M      0xFFFFFFFF   
#define   PHYA_TXTD_CHN_STATUS_CHN_L_B1___S                    0

#define PHYA_TXTD_CHN_STATUS_CHN_U_B0             (0x003B0844)
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0___POR    0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___S               0
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0___M      0xFFFFFFFF   
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B0___S                    0

#define PHYA_TXTD_CHN_STATUS_CHN_U_B1             (0x003B0C44)
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1___RWC       QCSR_REG_RO    
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1___POR    0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___S               0
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1___M      0xFFFFFFFF   
#define   PHYA_TXTD_CHN_STATUS_CHN_U_B1___S                    0

#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0       (0x003B0848)
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___S               0
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___S               0

#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1       (0x003B0C48)
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___S               0
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___S               0

#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0       (0x003B084C)
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___S               0
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___S               0

#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1       (0x003B0C4C)
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___RWC QCSR_REG_RW    
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___POR 0x00000000
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___M 0xFFFFFFFF
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___S               0
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___M 0xFFFFFFFF   
#define   PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___S               0

#define PHYA_TXTD_HCF_SETS_0_L                    (0x003B5000)
#define   PHYA_TXTD_HCF_SETS_0_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_0_L___POR           0x4949494B
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___POR 0x4B
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___S              24
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___S              16
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___S               8
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___S               0
#define   PHYA_TXTD_HCF_SETS_0_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_0_L___S                           0

#define PHYA_TXTD_HCF_SETS_0_U                    (0x003B5004)
#define   PHYA_TXTD_HCF_SETS_0_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_0_U___POR           0x49494948
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___POR 0x49
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___POR 0x48
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___S              24
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___S              16
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___S               8
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___S               0
#define   PHYA_TXTD_HCF_SETS_0_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_0_U___S                           0

#define PHYA_TXTD_HCF_SETS_1_L                    (0x003B5008)
#define   PHYA_TXTD_HCF_SETS_1_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_1_L___POR           0x49494946
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___POR 0x46
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___S              24
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___S              16
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___S               8
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___S               0
#define   PHYA_TXTD_HCF_SETS_1_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_1_L___S                           0

#define PHYA_TXTD_HCF_SETS_1_U                    (0x003B500C)
#define   PHYA_TXTD_HCF_SETS_1_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_1_U___POR           0x49494946
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___POR 0x49
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___POR 0x46
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___S              24
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___S              16
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___S               8
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___S               0
#define   PHYA_TXTD_HCF_SETS_1_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_1_U___S                           0

#define PHYA_TXTD_HCF_SETS_2_L                    (0x003B5010)
#define   PHYA_TXTD_HCF_SETS_2_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_2_L___POR           0x36333431
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___POR 0x36
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___POR 0x33
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___POR 0x34
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___POR 0x31
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___S              24
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___S              16
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___S               8
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___S               0
#define   PHYA_TXTD_HCF_SETS_2_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_2_L___S                           0

#define PHYA_TXTD_HCF_SETS_2_U                    (0x003B5014)
#define   PHYA_TXTD_HCF_SETS_2_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_2_U___POR           0x36333231
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___POR 0x36
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___POR 0x33
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___POR 0x32
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___POR 0x31
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___S              24
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___S              16
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___S               8
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___S               0
#define   PHYA_TXTD_HCF_SETS_2_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_2_U___S                           0

#define PHYA_TXTD_HCF_SETS_3_L                    (0x003B5018)
#define   PHYA_TXTD_HCF_SETS_3_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_3_L___POR           0x36333230
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___POR 0x36
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___POR 0x33
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___POR 0x32
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___POR 0x30
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___S              24
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___S              16
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___S               8
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___S               0
#define   PHYA_TXTD_HCF_SETS_3_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_3_L___S                           0

#define PHYA_TXTD_HCF_SETS_3_U                    (0x003B501C)
#define   PHYA_TXTD_HCF_SETS_3_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_3_U___POR           0x36333230
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___POR 0x36
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___POR 0x33
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___POR 0x32
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___POR 0x30
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___S              24
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___S              16
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___S               8
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___S               0
#define   PHYA_TXTD_HCF_SETS_3_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_3_U___S                           0

#define PHYA_TXTD_HCF_SETS_4_L                    (0x003B5020)
#define   PHYA_TXTD_HCF_SETS_4_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_4_L___POR           0x3E3A4B3E
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___POR 0x3E
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___POR 0x3A
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___POR 0x4B
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___POR 0x3E
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___S              24
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___S              16
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___S               8
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___S               0
#define   PHYA_TXTD_HCF_SETS_4_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_4_L___S                           0

#define PHYA_TXTD_HCF_SETS_4_U                    (0x003B5024)
#define   PHYA_TXTD_HCF_SETS_4_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_4_U___POR           0x4B3E3A4B
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___POR 0x4B
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___POR 0x3E
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___POR 0x3A
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___POR 0x4B
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___S              24
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___S              16
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___S               8
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___S               0
#define   PHYA_TXTD_HCF_SETS_4_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_4_U___S                           0

#define PHYA_TXTD_HCF_SETS_5_L                    (0x003B5028)
#define   PHYA_TXTD_HCF_SETS_5_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_5_L___POR           0x3A4B3E3A
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___POR 0x3A
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___POR 0x4B
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___POR 0x3E
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___POR 0x3A
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___S              24
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___S              16
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___S               8
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___S               0
#define   PHYA_TXTD_HCF_SETS_5_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_5_L___S                           0

#define PHYA_TXTD_HCF_SETS_5_U                    (0x003B502C)
#define   PHYA_TXTD_HCF_SETS_5_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_5_U___POR           0x282A3128
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___POR 0x28
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___POR 0x2A
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___POR 0x31
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___POR 0x28
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___S              24
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___S              16
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___S               8
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___S               0
#define   PHYA_TXTD_HCF_SETS_5_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_5_U___S                           0

#define PHYA_TXTD_HCF_SETS_6_L                    (0x003B5030)
#define   PHYA_TXTD_HCF_SETS_6_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_6_L___POR           0x31282A31
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___POR 0x31
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___POR 0x28
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___POR 0x2A
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___POR 0x31
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___S              24
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___S              16
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___S               8
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___S               0
#define   PHYA_TXTD_HCF_SETS_6_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_6_L___S                           0

#define PHYA_TXTD_HCF_SETS_6_U                    (0x003B5034)
#define   PHYA_TXTD_HCF_SETS_6_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_6_U___POR           0x2A31282A
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___POR 0x2A
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___POR 0x31
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___POR 0x28
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___POR 0x2A
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___S              24
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___S              16
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___S               8
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___S               0
#define   PHYA_TXTD_HCF_SETS_6_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_6_U___S                           0

#define PHYA_TXTD_HCF_SETS_7_L                    (0x003B5038)
#define   PHYA_TXTD_HCF_SETS_7_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_7_L___POR           0x49554969
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___POR 0x49
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___POR 0x55
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___POR 0x49
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___POR 0x69
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___S              24
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___S              16
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___S               8
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___S               0
#define   PHYA_TXTD_HCF_SETS_7_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_7_L___S                           0

#define PHYA_TXTD_HCF_SETS_7_U                    (0x003B503C)
#define   PHYA_TXTD_HCF_SETS_7_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_7_U___POR           0x49554969
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___POR 0x49
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___POR 0x55
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___POR 0x49
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___POR 0x69
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___S              24
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___S              16
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___S               8
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___S               0
#define   PHYA_TXTD_HCF_SETS_7_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_7_U___S                           0

#define PHYA_TXTD_HCF_SETS_8_L                    (0x003B5040)
#define   PHYA_TXTD_HCF_SETS_8_L___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_8_L___POR           0x33493349
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___POR 0x33
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___POR 0x49
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___POR 0x33
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___POR 0x49
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___S              24
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___S              16
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___S               8
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___S               0
#define   PHYA_TXTD_HCF_SETS_8_L___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_8_L___S                           0

#define PHYA_TXTD_HCF_SETS_8_U                    (0x003B5044)
#define   PHYA_TXTD_HCF_SETS_8_U___RWC              QCSR_REG_RW    
#define   PHYA_TXTD_HCF_SETS_8_U___POR           0x33493349
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___POR 0x33
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___POR 0x49
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___POR 0x33
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___POR 0x49
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___M 0x7F000000
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___S              24
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___M 0x007F0000
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___S              16
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___M 0x00007F00
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___S               8
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___M 0x0000007F
#define   PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___S               0
#define   PHYA_TXTD_HCF_SETS_8_U___M             0x7F7F7F7F   
#define   PHYA_TXTD_HCF_SETS_8_U___S                           0

#define PHYA_TXTD_PWR_COMP_SETS_0_L               (0x003B5048)
#define   PHYA_TXTD_PWR_COMP_SETS_0_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_0_L___POR      0x79506B96
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___POR 0x79
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___POR 0x50
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___POR 0x6B
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___POR 0x96
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_0_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_0_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_0_U               (0x003B504C)
#define   PHYA_TXTD_PWR_COMP_SETS_0_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_0_U___POR      0x5D863F51
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___POR 0x5D
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___POR 0x86
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___POR 0x3F
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___POR 0x51
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_0_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_0_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_1_L               (0x003B5050)
#define   PHYA_TXTD_PWR_COMP_SETS_1_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_1_L___POR      0x4E5D864E
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___POR 0x4E
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___POR 0x5D
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___POR 0x86
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___POR 0x4E
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_1_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_1_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_1_U               (0x003B5054)
#define   PHYA_TXTD_PWR_COMP_SETS_1_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_1_U___POR      0x864E5D86
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___POR 0x86
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___POR 0x4E
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___POR 0x5D
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___POR 0x86
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_1_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_1_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_2_L               (0x003B5058)
#define   PHYA_TXTD_PWR_COMP_SETS_2_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_2_L___POR      0x55894E5D
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___POR 0x55
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___POR 0x89
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___POR 0x4E
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___POR 0x5D
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_2_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_2_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_2_U               (0x003B505C)
#define   PHYA_TXTD_PWR_COMP_SETS_2_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_2_U___POR      0x495B8941
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___POR 0x49
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___POR 0x5B
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___POR 0x89
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_2_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_2_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_3_L               (0x003B5060)
#define   PHYA_TXTD_PWR_COMP_SETS_3_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_3_L___POR      0x874D6387
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___POR 0x87
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___POR 0x4D
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___POR 0x63
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___POR 0x87
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_3_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_3_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_3_U               (0x003B5064)
#define   PHYA_TXTD_PWR_COMP_SETS_3_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_3_U___POR      0x58875771
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___POR 0x58
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___POR 0x87
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___POR 0x57
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___POR 0x71
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_3_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_3_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_4_L               (0x003B5068)
#define   PHYA_TXTD_PWR_COMP_SETS_4_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_4_L___POR      0x4A638C41
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___POR 0x4A
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___POR 0x63
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___POR 0x8C
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_4_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_4_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_4_U               (0x003B506C)
#define   PHYA_TXTD_PWR_COMP_SETS_4_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_4_U___POR      0x8C415887
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___POR 0x8C
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___POR 0x58
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___POR 0x87
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_4_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_4_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_5_L               (0x003B5070)
#define   PHYA_TXTD_PWR_COMP_SETS_5_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_5_L___POR      0x559A4A63
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___POR 0x55
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___POR 0x9A
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___POR 0x4A
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___POR 0x63
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_5_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_5_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_5_U               (0x003B5074)
#define   PHYA_TXTD_PWR_COMP_SETS_5_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_5_U___POR      0x495D9742
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___POR 0x49
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___POR 0x5D
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___POR 0x97
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___POR 0x42
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_5_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_5_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_6_L               (0x003B5078)
#define   PHYA_TXTD_PWR_COMP_SETS_6_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_6_L___POR      0x9738469A
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___POR 0x97
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___POR 0x38
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___POR 0x46
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___POR 0x9A
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_6_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_6_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_6_U               (0x003B507C)
#define   PHYA_TXTD_PWR_COMP_SETS_6_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_6_U___POR      0x469A3D4D
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___POR 0x46
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___POR 0x9A
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___POR 0x3D
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___POR 0x4D
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_6_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_6_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_7_L               (0x003B5080)
#define   PHYA_TXTD_PWR_COMP_SETS_7_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_7_L___POR      0x3D4D9738
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___POR 0x3D
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___POR 0x4D
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___POR 0x97
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___POR 0x38
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_7_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_7_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_7_U               (0x003B5084)
#define   PHYA_TXTD_PWR_COMP_SETS_7_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_7_U___POR      0x883C4C7B
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___POR 0x88
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___POR 0x3C
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___POR 0x4C
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___POR 0x7B
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_7_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_7_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_8_L               (0x003B5088)
#define   PHYA_TXTD_PWR_COMP_SETS_8_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_8_L___POR      0x4C9A4152
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___POR 0x4C
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___POR 0x9A
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___POR 0x52
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_8_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_8_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_8_U               (0x003B508C)
#define   PHYA_TXTD_PWR_COMP_SETS_8_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_8_U___POR      0x4152AD3C
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___POR 0x52
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___POR 0xAD
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___POR 0x3C
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_8_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_8_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_9_L               (0x003B5090)
#define   PHYA_TXTD_PWR_COMP_SETS_9_L___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_9_L___POR      0x8F41538F
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___POR 0x8F
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___POR 0x53
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___POR 0x8F
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_9_L___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_9_L___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_9_U               (0x003B5094)
#define   PHYA_TXTD_PWR_COMP_SETS_9_U___RWC         QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_9_U___POR      0x538F5F6C
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___POR 0x53
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___POR 0x8F
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___POR 0x5F
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___POR 0x6C
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_9_U___M        0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_9_U___S                      0

#define PHYA_TXTD_PWR_COMP_SETS_10_L              (0x003B5098)
#define   PHYA_TXTD_PWR_COMP_SETS_10_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_10_L___POR     0x5F6C8F41
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___POR 0x5F
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___POR 0x6C
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___POR 0x8F
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_10_L___M       0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_10_L___S                     0

#define PHYA_TXTD_PWR_COMP_SETS_10_U              (0x003B509C)
#define   PHYA_TXTD_PWR_COMP_SETS_10_U___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_10_U___POR     0x8B3D4C86
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___POR 0x8B
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___POR 0x3D
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___POR 0x4C
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___POR 0x86
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___M 0xFF000000
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___S              24
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___M 0x00FF0000
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___S              16
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_10_U___M       0xFFFFFFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_10_U___S                     0

#define PHYA_TXTD_PWR_COMP_SETS_11_L              (0x003B50A0)
#define   PHYA_TXTD_PWR_COMP_SETS_11_L___RWC        QCSR_REG_RW    
#define   PHYA_TXTD_PWR_COMP_SETS_11_L___POR     0x00004153
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___POR 0x41
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___POR 0x53
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___M 0x0000FF00
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___S               8
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___M 0x000000FF
#define   PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___S               0
#define   PHYA_TXTD_PWR_COMP_SETS_11_L___M       0x0000FFFF   
#define   PHYA_TXTD_PWR_COMP_SETS_11_L___S                     0

#define PHYA_TXTD_DUMMY_L                         (0x003B7FF8)
#define   PHYA_TXTD_DUMMY_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXTD_DUMMY_L___POR                0x00000000
#define   PHYA_TXTD_DUMMY_L__DUMMY___POR         0x0
#define   PHYA_TXTD_DUMMY_L__DUMMY___M           0x00000001
#define   PHYA_TXTD_DUMMY_L__DUMMY___S                         0
#define   PHYA_TXTD_DUMMY_L___M                  0x00000001   
#define   PHYA_TXTD_DUMMY_L___S                                0

#define PHYA_TXBF_ECO_CONTROL_L                   (0x003C0000)
#define   PHYA_TXBF_ECO_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_TXBF_ECO_CONTROL_L___POR          0x00000000
#define   PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___M  0xFFFFFFFF
#define   PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___S                0
#define   PHYA_TXBF_ECO_CONTROL_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_ECO_CONTROL_L___S                          0

#define PHYA_TXBF_ECO_CONTROL_U                   (0x003C0004)
#define   PHYA_TXBF_ECO_CONTROL_U___RWC             QCSR_REG_RW    
#define   PHYA_TXBF_ECO_CONTROL_U___POR          0x00000000
#define   PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___POR 0x00000000
#define   PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___M   0xFFFFFFFF
#define   PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___S                 0
#define   PHYA_TXBF_ECO_CONTROL_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_ECO_CONTROL_U___S                          0

#define PHYA_TXBF_ECO_STATUS_L                    (0x003C0008)
#define   PHYA_TXBF_ECO_STATUS_L___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_ECO_STATUS_L___POR           0x00000000
#define   PHYA_TXBF_ECO_STATUS_L__ECO_STAT___POR 0x00000000
#define   PHYA_TXBF_ECO_STATUS_L__ECO_STAT___M   0xFFFFFFFF
#define   PHYA_TXBF_ECO_STATUS_L__ECO_STAT___S                 0
#define   PHYA_TXBF_ECO_STATUS_L___M             0xFFFFFFFF   
#define   PHYA_TXBF_ECO_STATUS_L___S                           0

#define PHYA_TXBF_CONFIG_CONFIG_L                 (0x003C0010)
#define   PHYA_TXBF_CONFIG_CONFIG_L___RWC           QCSR_REG_RW    
#define   PHYA_TXBF_CONFIG_CONFIG_L___POR        0x00000000
#define   PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___POR 0x0
#define   PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___M 0x00000001
#define   PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___S               0
#define   PHYA_TXBF_CONFIG_CONFIG_L___M          0x00000001   
#define   PHYA_TXBF_CONFIG_CONFIG_L___S                        0

#define PHYA_TXBF_ERROR_CODE_L                    (0x003C0018)
#define   PHYA_TXBF_ERROR_CODE_L___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_CODE_L___POR           0x00000000
#define   PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___POR 0x00000000
#define   PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_TXBF_ERROR_CODE_L___M             0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_CODE_L___S                           0

#define PHYA_TXBF_ERROR_STATUS_L                  (0x003C0020)
#define   PHYA_TXBF_ERROR_STATUS_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_STATUS_L___POR         0x00000000
#define   PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___M 0x80000000
#define   PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___S              31
#define   PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___M 0x40000000
#define   PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___S              30
#define   PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___M 0x20000000
#define   PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___S              29
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___M 0x10000000
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___S              28
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___M 0x08000000
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___S              27
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___M 0x04000000
#define   PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___S              26
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___M 0x02000000
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___S              25
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___M 0x01000000
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___S              24
#define   PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___M 0x00800000
#define   PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___S              23
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___M 0x00400000
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___S              22
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___M 0x00200000
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___S              21
#define   PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___M 0x00100000
#define   PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___S              20
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___M 0x00080000
#define   PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___S              19
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___M 0x00040000
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___S              18
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___M 0x00020000
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___S              17
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___M 0x00010000
#define   PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___S              16
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___M 0x00008000
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___S              15
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___M 0x00004000
#define   PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___S              14
#define   PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___M 0x00002000
#define   PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___S              13
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___M 0x00001000
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___S              12
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___M 0x00000800
#define   PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___S              11
#define   PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___M 0x00000400
#define   PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___S              10
#define   PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___M 0x00000200
#define   PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___S               9
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___M 0x00000100
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___S               8
#define   PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___M 0x00000080
#define   PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___S               7
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___M 0x00000040
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___S               6
#define   PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___M 0x00000020
#define   PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___S               5
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___M 0x00000010
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___S               4
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___M 0x00000008
#define   PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___S               3
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___M 0x00000004
#define   PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___S               2
#define   PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___M 0x00000002
#define   PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___S               1
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___M 0x00000001
#define   PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___S               0
#define   PHYA_TXBF_ERROR_STATUS_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_STATUS_L___S                         0

#define PHYA_TXBF_ERROR_STATUS_U                  (0x003C0024)
#define   PHYA_TXBF_ERROR_STATUS_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_STATUS_U___POR         0x00000000
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___POR 0x0
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___M 0x00000100
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___S               8
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___M 0x00000080
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___S               7
#define   PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___M 0x00000040
#define   PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___S               6
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___M 0x00000020
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___S               5
#define   PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___M 0x00000010
#define   PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___S               4
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___M 0x00000008
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___S               3
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___M 0x00000004
#define   PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___S               2
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___M 0x00000002
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___S               1
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___M 0x00000001
#define   PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___S               0
#define   PHYA_TXBF_ERROR_STATUS_U___M           0x000001FF   
#define   PHYA_TXBF_ERROR_STATUS_U___S                         0

#define PHYA_TXBF_ERROR_MASK_L                    (0x003C0028)
#define   PHYA_TXBF_ERROR_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_TXBF_ERROR_MASK_L___POR           0xFFFFFFFF
#define   PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___M 0x80000000
#define   PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___S              31
#define   PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___M 0x40000000
#define   PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___S              30
#define   PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___M 0x20000000
#define   PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___S              29
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___M 0x10000000
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___S              28
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___M 0x08000000
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___S              27
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___M 0x04000000
#define   PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___S              26
#define   PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___M 0x02000000
#define   PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___S              25
#define   PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___M 0x01000000
#define   PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___S              24
#define   PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___M 0x00800000
#define   PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___S              23
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___M 0x00400000
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___S              22
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___M 0x00200000
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___S              21
#define   PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___M 0x00100000
#define   PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___S              20
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___M 0x00080000
#define   PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___S              19
#define   PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___M 0x00040000
#define   PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___S              18
#define   PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___M 0x00020000
#define   PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___S              17
#define   PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___M 0x00010000
#define   PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___S              16
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___M 0x00008000
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___S              15
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___M 0x00004000
#define   PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___S              14
#define   PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___M 0x00002000
#define   PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___S              13
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___M 0x00001000
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___S              12
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___M 0x00000800
#define   PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___S              11
#define   PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___M 0x00000400
#define   PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___S              10
#define   PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___M 0x00000200
#define   PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___S               9
#define   PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___M 0x00000100
#define   PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___S               8
#define   PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___M 0x00000080
#define   PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___S               7
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___M 0x00000040
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___S               6
#define   PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___M 0x00000020
#define   PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___S               5
#define   PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___M 0x00000010
#define   PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___S               4
#define   PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___M 0x00000008
#define   PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___S               3
#define   PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___M 0x00000004
#define   PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___S               2
#define   PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___M 0x00000002
#define   PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___S               1
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___M 0x00000001
#define   PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___S               0
#define   PHYA_TXBF_ERROR_MASK_L___M             0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_MASK_L___S                           0

#define PHYA_TXBF_ERROR_MASK_U                    (0x003C002C)
#define   PHYA_TXBF_ERROR_MASK_U___RWC              QCSR_REG_RW    
#define   PHYA_TXBF_ERROR_MASK_U___POR           0x000001FF
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___POR 0x1
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___M 0x00000100
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___S               8
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000080
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___S               7
#define   PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000040
#define   PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___S               6
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000020
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___S               5
#define   PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___M 0x00000010
#define   PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___S               4
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___M 0x00000008
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___S               3
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___M 0x00000004
#define   PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___S               2
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___M 0x00000002
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___S               1
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___M 0x00000001
#define   PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___S               0
#define   PHYA_TXBF_ERROR_MASK_U___M             0x000001FF   
#define   PHYA_TXBF_ERROR_MASK_U___S                           0

#define PHYA_TXBF_PHYDBG_TXBF_0_L                 (0x003C0030)
#define   PHYA_TXBF_PHYDBG_TXBF_0_L___RWC           QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_0_L___POR        0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___POR 0x00
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___POR 0x0
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___M 0x0000FF00
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___S               8
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___M 0x00000001
#define   PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_0_L___M          0x0000FF01   
#define   PHYA_TXBF_PHYDBG_TXBF_0_L___S                        0

#define PHYA_TXBF_PHYDBG_TXBF_10_L                (0x003C0038)
#define   PHYA_TXBF_PHYDBG_TXBF_10_L___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_10_L___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_10_L___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_10_L___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_10_U                (0x003C003C)
#define   PHYA_TXBF_PHYDBG_TXBF_10_U___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_10_U___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_10_U___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_10_U___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_11_L                (0x003C0040)
#define   PHYA_TXBF_PHYDBG_TXBF_11_L___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_11_L___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_11_L___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_11_L___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_11_U                (0x003C0044)
#define   PHYA_TXBF_PHYDBG_TXBF_11_U___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_11_U___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_11_U___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_11_U___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_12_L                (0x003C0048)
#define   PHYA_TXBF_PHYDBG_TXBF_12_L___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_12_L___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_12_L___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_12_L___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_12_U                (0x003C004C)
#define   PHYA_TXBF_PHYDBG_TXBF_12_U___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_12_U___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_12_U___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_12_U___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_13_L                (0x003C0050)
#define   PHYA_TXBF_PHYDBG_TXBF_13_L___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_13_L___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_13_L___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_13_L___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_13_U                (0x003C0054)
#define   PHYA_TXBF_PHYDBG_TXBF_13_U___RWC          QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_13_U___POR       0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___POR 0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___M 0xFFFFFFFF
#define   PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_13_U___M         0xFFFFFFFF   
#define   PHYA_TXBF_PHYDBG_TXBF_13_U___S                       0

#define PHYA_TXBF_PHYDBG_TXBF_2_L                 (0x003C0058)
#define   PHYA_TXBF_PHYDBG_TXBF_2_L___RWC           QCSR_REG_RW    
#define   PHYA_TXBF_PHYDBG_TXBF_2_L___POR        0x00000000
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___POR 0x0000
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___POR 0x00
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___M 0xFFFF0000
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___S              16
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___M 0x000000FF
#define   PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___S               0
#define   PHYA_TXBF_PHYDBG_TXBF_2_L___M          0xFFFF00FF   
#define   PHYA_TXBF_PHYDBG_TXBF_2_L___S                        0

#define PHYA_TXBF_CFG_0_L                         (0x003C0060)
#define   PHYA_TXBF_CFG_0_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_0_L___POR                0x00000000
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___POR 0x0
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___POR 0x0
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___POR 0x0
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___POR   0x0
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___M 0x01000000
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___S              24
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___M 0x00010000
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___S              16
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___M 0x00000100
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___S               8
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___M     0x00000001
#define   PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___S                   0
#define   PHYA_TXBF_CFG_0_L___M                  0x01010101   
#define   PHYA_TXBF_CFG_0_L___S                                0

#define PHYA_TXBF_CFG_0_U                         (0x003C0064)
#define   PHYA_TXBF_CFG_0_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_0_U___POR                0x01000000
#define   PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___POR 0x1
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___POR 0x0
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___POR 0x0
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___POR 0x0
#define   PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___M 0x01000000
#define   PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___S              24
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___M 0x00010000
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___S              16
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___M 0x00000100
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___S               8
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___M 0x00000001
#define   PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___S               0
#define   PHYA_TXBF_CFG_0_U___M                  0x01010101   
#define   PHYA_TXBF_CFG_0_U___S                                0

#define PHYA_TXBF_CFG_1_L                         (0x003C0068)
#define   PHYA_TXBF_CFG_1_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_1_L___POR                0x00001400
#define   PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___POR 0x00001400
#define   PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_1_L___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_1_L___S                                0

#define PHYA_TXBF_CFG_1_U                         (0x003C006C)
#define   PHYA_TXBF_CFG_1_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_1_U___POR                0x00001400
#define   PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___POR 0x00001400
#define   PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_1_U___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_1_U___S                                0

#define PHYA_TXBF_CFG_2_L                         (0x003C0070)
#define   PHYA_TXBF_CFG_2_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_2_L___POR                0x00001400
#define   PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___POR 0x00001400
#define   PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_2_L___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_2_L___S                                0

#define PHYA_TXBF_CFG_2_U                         (0x003C0074)
#define   PHYA_TXBF_CFG_2_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_2_U___POR                0x00001400
#define   PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___POR 0x00001400
#define   PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_2_U___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_2_U___S                                0

#define PHYA_TXBF_CFG_3_L                         (0x003C0078)
#define   PHYA_TXBF_CFG_3_L___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_3_L___POR                0x00000200
#define   PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___POR 0x00000200
#define   PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_3_L___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_3_L___S                                0

#define PHYA_TXBF_CFG_3_U                         (0x003C007C)
#define   PHYA_TXBF_CFG_3_U___RWC                   QCSR_REG_RW    
#define   PHYA_TXBF_CFG_3_U___POR                0x00001400
#define   PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___POR 0x00001400
#define   PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___S               0
#define   PHYA_TXBF_CFG_3_U___M                  0xFFFFFFFF   
#define   PHYA_TXBF_CFG_3_U___S                                0

#define PHYA_TXBF_TXBF_0_L                        (0x003C0080)
#define   PHYA_TXBF_TXBF_0_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_0_L___POR               0x00010100
#define   PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___POR 0x0
#define   PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___POR 0x1
#define   PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___POR 0x1
#define   PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___POR 0x0
#define   PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___M 0x01000000
#define   PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___S              24
#define   PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___M 0x00010000
#define   PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___S              16
#define   PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___M 0x00000100
#define   PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___S               8
#define   PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___M 0x00000001
#define   PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___S               0
#define   PHYA_TXBF_TXBF_0_L___M                 0x01010101   
#define   PHYA_TXBF_TXBF_0_L___S                               0

#define PHYA_TXBF_TXBF_0_U                        (0x003C0084)
#define   PHYA_TXBF_TXBF_0_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_0_U___POR               0x00040100
#define   PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___POR 0x0
#define   PHYA_TXBF_TXBF_0_U__TXBF_BETA___POR    0x04
#define   PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___POR 0x1
#define   PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___POR 0x0
#define   PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___M 0x03000000
#define   PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___S              24
#define   PHYA_TXBF_TXBF_0_U__TXBF_BETA___M      0x001F0000
#define   PHYA_TXBF_TXBF_0_U__TXBF_BETA___S                   16
#define   PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___M 0x00000100
#define   PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___S               8
#define   PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___M 0x00000001
#define   PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___S               0
#define   PHYA_TXBF_TXBF_0_U___M                 0x031F0101   
#define   PHYA_TXBF_TXBF_0_U___S                               0

#define PHYA_TXBF_TXBF_1_L                        (0x003C0088)
#define   PHYA_TXBF_TXBF_1_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_1_L___POR               0x00000000
#define   PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___S               0
#define   PHYA_TXBF_TXBF_1_L___M                 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_1_L___S                               0

#define PHYA_TXBF_TXBF_1_U                        (0x003C008C)
#define   PHYA_TXBF_TXBF_1_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_1_U___POR               0x00000000
#define   PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___S               0
#define   PHYA_TXBF_TXBF_1_U___M                 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_1_U___S                               0

#define PHYA_TXBF_TXBF_2_L                        (0x003C0090)
#define   PHYA_TXBF_TXBF_2_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_2_L___POR               0x00010001
#define   PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___POR 0x0
#define   PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___POR 0x1
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___POR 0x0
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___POR 0x1
#define   PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___M 0x01000000
#define   PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___S              24
#define   PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___M 0x00010000
#define   PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___S              16
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___M 0x00000100
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___S               8
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___M 0x00000001
#define   PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___S               0
#define   PHYA_TXBF_TXBF_2_L___M                 0x01010101   
#define   PHYA_TXBF_TXBF_2_L___S                               0

#define PHYA_TXBF_TXBF_2_U                        (0x003C0094)
#define   PHYA_TXBF_TXBF_2_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_2_U___POR               0x00000000
#define   PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___POR 0x0
#define   PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___M 0x00000007
#define   PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___S               0
#define   PHYA_TXBF_TXBF_2_U___M                 0x00000007   
#define   PHYA_TXBF_TXBF_2_U___S                               0

#define PHYA_TXBF_TXBF_30_L                       (0x003C0098)
#define   PHYA_TXBF_TXBF_30_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_30_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___S               0
#define   PHYA_TXBF_TXBF_30_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_30_L___S                              0

#define PHYA_TXBF_TXBF_30_U                       (0x003C009C)
#define   PHYA_TXBF_TXBF_30_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_30_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___S               0
#define   PHYA_TXBF_TXBF_30_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_30_U___S                              0

#define PHYA_TXBF_TXBF_31_L                       (0x003C00A0)
#define   PHYA_TXBF_TXBF_31_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_31_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___S               0
#define   PHYA_TXBF_TXBF_31_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_31_L___S                              0

#define PHYA_TXBF_TXBF_31_U                       (0x003C00A4)
#define   PHYA_TXBF_TXBF_31_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_31_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___S               0
#define   PHYA_TXBF_TXBF_31_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_31_U___S                              0

#define PHYA_TXBF_TXBF_32_L                       (0x003C00A8)
#define   PHYA_TXBF_TXBF_32_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_32_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___S               0
#define   PHYA_TXBF_TXBF_32_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_32_L___S                              0

#define PHYA_TXBF_TXBF_32_U                       (0x003C00AC)
#define   PHYA_TXBF_TXBF_32_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_32_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___S               0
#define   PHYA_TXBF_TXBF_32_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_32_U___S                              0

#define PHYA_TXBF_TXBF_40_L                       (0x003C00B0)
#define   PHYA_TXBF_TXBF_40_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_40_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___S               0
#define   PHYA_TXBF_TXBF_40_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_40_L___S                              0

#define PHYA_TXBF_TXBF_40_U                       (0x003C00B4)
#define   PHYA_TXBF_TXBF_40_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_40_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___S               0
#define   PHYA_TXBF_TXBF_40_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_40_U___S                              0

#define PHYA_TXBF_TXBF_41_L                       (0x003C00B8)
#define   PHYA_TXBF_TXBF_41_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_41_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___S               0
#define   PHYA_TXBF_TXBF_41_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_41_L___S                              0

#define PHYA_TXBF_TXBF_41_U                       (0x003C00BC)
#define   PHYA_TXBF_TXBF_41_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_41_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___S               0
#define   PHYA_TXBF_TXBF_41_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_41_U___S                              0

#define PHYA_TXBF_TXBF_42_L                       (0x003C00C0)
#define   PHYA_TXBF_TXBF_42_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_42_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___S               0
#define   PHYA_TXBF_TXBF_42_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_42_L___S                              0

#define PHYA_TXBF_TXBF_42_U                       (0x003C00C4)
#define   PHYA_TXBF_TXBF_42_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_42_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___S               0
#define   PHYA_TXBF_TXBF_42_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_42_U___S                              0

#define PHYA_TXBF_TXBF_50_L                       (0x003C00C8)
#define   PHYA_TXBF_TXBF_50_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_50_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___S               0
#define   PHYA_TXBF_TXBF_50_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_50_L___S                              0

#define PHYA_TXBF_TXBF_50_U                       (0x003C00CC)
#define   PHYA_TXBF_TXBF_50_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_50_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___S               0
#define   PHYA_TXBF_TXBF_50_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_50_U___S                              0

#define PHYA_TXBF_TXBF_51_L                       (0x003C00D0)
#define   PHYA_TXBF_TXBF_51_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_51_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___S               0
#define   PHYA_TXBF_TXBF_51_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_51_L___S                              0

#define PHYA_TXBF_TXBF_51_U                       (0x003C00D4)
#define   PHYA_TXBF_TXBF_51_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_51_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___S               0
#define   PHYA_TXBF_TXBF_51_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_51_U___S                              0

#define PHYA_TXBF_TXBF_52_L                       (0x003C00D8)
#define   PHYA_TXBF_TXBF_52_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_52_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___S               0
#define   PHYA_TXBF_TXBF_52_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_52_L___S                              0

#define PHYA_TXBF_TXBF_52_U                       (0x003C00DC)
#define   PHYA_TXBF_TXBF_52_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_52_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___S               0
#define   PHYA_TXBF_TXBF_52_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_52_U___S                              0

#define PHYA_TXBF_TXBF_60_L                       (0x003C00E0)
#define   PHYA_TXBF_TXBF_60_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_60_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___S               0
#define   PHYA_TXBF_TXBF_60_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_60_L___S                              0

#define PHYA_TXBF_TXBF_60_U                       (0x003C00E4)
#define   PHYA_TXBF_TXBF_60_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_60_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___S               0
#define   PHYA_TXBF_TXBF_60_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_60_U___S                              0

#define PHYA_TXBF_TXBF_61_L                       (0x003C00E8)
#define   PHYA_TXBF_TXBF_61_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_61_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___S               0
#define   PHYA_TXBF_TXBF_61_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_61_L___S                              0

#define PHYA_TXBF_TXBF_61_U                       (0x003C00EC)
#define   PHYA_TXBF_TXBF_61_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_61_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___S               0
#define   PHYA_TXBF_TXBF_61_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_61_U___S                              0

#define PHYA_TXBF_TXBF_62_L                       (0x003C00F0)
#define   PHYA_TXBF_TXBF_62_L___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_62_L___POR              0x00000000
#define   PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___S               0
#define   PHYA_TXBF_TXBF_62_L___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_62_L___S                              0

#define PHYA_TXBF_TXBF_62_U                       (0x003C00F4)
#define   PHYA_TXBF_TXBF_62_U___RWC                 QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_62_U___POR              0x00000000
#define   PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___POR 0x00000000
#define   PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___S               0
#define   PHYA_TXBF_TXBF_62_U___M                0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_62_U___S                              0

#define PHYA_TXBF_TXBF_7_L                        (0x003C00F8)
#define   PHYA_TXBF_TXBF_7_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_7_L___POR               0x00000100
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___POR 0x1
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___POR 0x0
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___M 0x00000100
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___S               8
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___M 0x0000000F
#define   PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___S               0
#define   PHYA_TXBF_TXBF_7_L___M                 0x0000010F   
#define   PHYA_TXBF_TXBF_7_L___S                               0

#define PHYA_TXBF_TXBF_7_U                        (0x003C00FC)
#define   PHYA_TXBF_TXBF_7_U___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_7_U___POR               0x00000014
#define   PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___POR 0x00014
#define   PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___M 0x000FFFFF
#define   PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___S               0
#define   PHYA_TXBF_TXBF_7_U___M                 0x000FFFFF   
#define   PHYA_TXBF_TXBF_7_U___S                               0

#define PHYA_TXBF_TXBF_8_L                        (0x003C0100)
#define   PHYA_TXBF_TXBF_8_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_8_L___POR               0x00000000
#define   PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___POR 0x0
#define   PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___POR 0x0
#define   PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___M 0x00000100
#define   PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___S               8
#define   PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___M 0x00000001
#define   PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___S               0
#define   PHYA_TXBF_TXBF_8_L___M                 0x00000101   
#define   PHYA_TXBF_TXBF_8_L___S                               0

#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n(n) (0x003C0108+0x8*(n))
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_nMIN 0    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_nMAX 0    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_ELEM 1    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___RWC     QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___POR  0x00000000
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___S               0
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___M    0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___S                  0
#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0           (0x003C0108)
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0___RWC     QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0__TXBF_TONE_MAP_LUT_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0__TXBF_TONE_MAP_LUT_0___S               0

#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n(n) (0x003C010C+0x8*(n))
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_nMIN 0    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_nMAX 0    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_ELEM 1    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___RWC     QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___POR  0x00000000
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___S               0
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___M    0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___S                  0
#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0           (0x003C010C)
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0___RWC     QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0__TXBF_TONE_MAP_LUT_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0__TXBF_TONE_MAP_LUT_1___S               0

#define PHYA_TXBF_VSMOOTH_COEFF_0_L               (0x003C1108)
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L___POR      0x110C1704
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___POR 0x11
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___POR 0x0C
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___POR 0x17
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___POR 0x04
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___M 0xFF000000
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___S              24
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___M 0x00FF0000
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___S              16
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___M 0x0000FF00
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___S               8
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___M 0x000000FF
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L___M        0xFFFFFFFF   
#define   PHYA_TXBF_VSMOOTH_COEFF_0_L___S                      0

#define PHYA_TXBF_VSMOOTH_COEFF_0_U               (0x003C110C)
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U___POR      0x00000011
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___POR 0x11
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___M 0x000000FF
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U___M        0x000000FF   
#define   PHYA_TXBF_VSMOOTH_COEFF_0_U___S                      0

#define PHYA_TXBF_VSMOOTH_COEFF_1_L               (0x003C1110)
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L___POR      0x271301EF
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___POR 0x27
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___POR 0x13
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___POR 0x01
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___POR 0xEF
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___M 0xFF000000
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___S              24
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___M 0x00FF0000
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___S              16
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___M 0x0000FF00
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___S               8
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___M 0x000000FF
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L___M        0xFFFFFFFF   
#define   PHYA_TXBF_VSMOOTH_COEFF_1_L___S                      0

#define PHYA_TXBF_VSMOOTH_COEFF_1_U               (0x003C1114)
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U___POR      0x0000002F
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___POR 0x2F
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___M 0x000000FF
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U___M        0x000000FF   
#define   PHYA_TXBF_VSMOOTH_COEFF_1_U___S                      0

#define PHYA_TXBF_VSMOOTH_COEFF_2_L               (0x003C1118)
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L___POR      0x02710000
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___POR 0x0271
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___POR 0x0
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___M 0xFFFF0000
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___S              16
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___M 0x00000001
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L___M        0xFFFF0001   
#define   PHYA_TXBF_VSMOOTH_COEFF_2_L___S                      0

#define PHYA_TXBF_VSMOOTH_COEFF_2_U               (0x003C111C)
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U___RWC         QCSR_REG_RW    
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U___POR      0x00000280
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___POR 0x00000280
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___M 0xFFFFFFFF
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___S               0
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U___M        0xFFFFFFFF   
#define   PHYA_TXBF_VSMOOTH_COEFF_2_U___S                      0

#define PHYA_TXBF_FW_DMA_L                        (0x003C1120)
#define   PHYA_TXBF_FW_DMA_L___RWC                  QCSR_REG_RW    
#define   PHYA_TXBF_FW_DMA_L___POR               0x00000000
#define   PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___POR 0x0
#define   PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___POR  0x0
#define   PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___M 0x00000100
#define   PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___S               8
#define   PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___M    0x00000001
#define   PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___S                  0
#define   PHYA_TXBF_FW_DMA_L___M                 0x00000101   
#define   PHYA_TXBF_FW_DMA_L___S                               0

#define PHYA_TXBF_HW_ACC_RST_L                    (0x003C1128)
#define   PHYA_TXBF_HW_ACC_RST_L___RWC              QCSR_REG_WO    
#define   PHYA_TXBF_HW_ACC_RST_L___POR           0x00000000
#define   PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___POR 0x0
#define   PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___POR 0x0
#define   PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___POR 0x0
#define   PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___M 0x00010000
#define   PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___S              16
#define   PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___M 0x00000100
#define   PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___S               8
#define   PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___M 0x00000001
#define   PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___S               0
#define   PHYA_TXBF_HW_ACC_RST_L___M             0x00010101   
#define   PHYA_TXBF_HW_ACC_RST_L___S                           0

#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n(n) (0x003C1130+0x8*(n))
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_nMIN 0    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_nMAX 0    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_ELEM 1    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___POR 0x00000000
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___S               0
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___M  0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___S                0
#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0         (0x003C1130)
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0__TXBF_WEIGHTS_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0__TXBF_WEIGHTS_MEMORY_0___S               0

#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n(n) (0x003C1134+0x8*(n))
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_nMIN 0    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_nMAX 0    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_ELEM 1    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___POR 0x00000000
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___S               0
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___M  0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___S                0
#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0         (0x003C1134)
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0__TXBF_WEIGHTS_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0__TXBF_WEIGHTS_MEMORY_1___S               0

#define PHYA_TXBF_TXBF_CV_MEMORY_L_n(n)  (0x003D9130+0x8*(n))
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n_nMIN 0    
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n_nMAX 0    
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n_ELEM 1    
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n___RWC        QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n___POR     0x00000000
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___S               0
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n___M       0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_n___S                     0
#define PHYA_TXBF_TXBF_CV_MEMORY_L_0              (0x003D9130)
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_0___RWC        QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_0__TXBF_CV_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_CV_MEMORY_L_0__TXBF_CV_MEMORY_0___S               0

#define PHYA_TXBF_TXBF_CV_MEMORY_U_n(n)  (0x003D9134+0x8*(n))
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n_nMIN 0    
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n_nMAX 0    
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n_ELEM 1    
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n___RWC        QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n___POR     0x00000000
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___S               0
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n___M       0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_n___S                     0
#define PHYA_TXBF_TXBF_CV_MEMORY_U_0              (0x003D9134)
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_0___RWC        QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_0__TXBF_CV_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_CV_MEMORY_U_0__TXBF_CV_MEMORY_1___S               0

#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n(n) (0x003E5050+0x8*(n))
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_nMIN 0    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_nMAX 0    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_ELEM 1    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___POR 0x00000000
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___S               0
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___M  0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___S                0
#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0         (0x003E5050)
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0__TXBF_SCRATCH_MEMORY_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0__TXBF_SCRATCH_MEMORY_0___S               0

#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n(n) (0x003E5054+0x8*(n))
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_nMIN 0    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_nMAX 0    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_ELEM 1    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___POR 0x00000000
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___S               0
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___M  0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___S                0
#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0         (0x003E5054)
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0__TXBF_SCRATCH_MEMORY_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0__TXBF_SCRATCH_MEMORY_1___S               0

#define PHYA_TXBF_PUBLIC_SPARE_L                  (0x003FB050)
#define   PHYA_TXBF_PUBLIC_SPARE_L___RWC            QCSR_REG_RW    
#define   PHYA_TXBF_PUBLIC_SPARE_L___POR         0x00000000
#define   PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S               0
#define   PHYA_TXBF_PUBLIC_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_PUBLIC_SPARE_L___S                         0

#define PHYA_TXBF_PUBLIC_SPARE_U                  (0x003FB054)
#define   PHYA_TXBF_PUBLIC_SPARE_U___RWC            QCSR_REG_RW    
#define   PHYA_TXBF_PUBLIC_SPARE_U___POR         0x00000000
#define   PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S               0
#define   PHYA_TXBF_PUBLIC_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_PUBLIC_SPARE_U___S                         0

#define PHYA_TXBF_PRIVATE_SPARE_L                 (0x003FB058)
#define   PHYA_TXBF_PRIVATE_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_TXBF_PRIVATE_SPARE_L___POR        0x00000000
#define   PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S               0
#define   PHYA_TXBF_PRIVATE_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_TXBF_PRIVATE_SPARE_L___S                        0

#define PHYA_TXBF_PRIVATE_SPARE_U                 (0x003FB05C)
#define   PHYA_TXBF_PRIVATE_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_TXBF_PRIVATE_SPARE_U___POR        0x00000000
#define   PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S               0
#define   PHYA_TXBF_PRIVATE_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_TXBF_PRIVATE_SPARE_U___S                        0

#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n(n) (0x003FB060+0x8*(n))
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_nMIN 0    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_nMAX 0    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_ELEM 1    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___RWC QCSR_REG_RO    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___POR 0x00000000
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___POR 0x00000000
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___S               0
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___M 0xFFFFFFFF   
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___S               0
#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0       (0x003FB060)
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0___RWC QCSR_REG_RO    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0__PREFETCH_CV_DESC_FIFO_0___M 0xFFFFFFFF
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0__PREFETCH_CV_DESC_FIFO_0___S               0

#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n(n) (0x003FB064+0x8*(n))
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_nMIN 0    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_nMAX 0    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_ELEM 1    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___RWC QCSR_REG_RO    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___POR 0x00000000
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___POR 0x00000000
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___S               0
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___M 0xFFFFFFFF   
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___S               0
#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0       (0x003FB064)
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0___RWC QCSR_REG_RO    
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0__PREFETCH_CV_DESC_FIFO_1___M 0xFFFFFFFF
#define   PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0__PREFETCH_CV_DESC_FIFO_1___S               0

#define PHYA_TXBF_ERROR_EVENT_RD_0_L              (0x003FB160)
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_0_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_0_U              (0x003FB164)
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_0_U___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_1_L              (0x003FB168)
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_1_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_1_U              (0x003FB16C)
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_1_U___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_20_L             (0x003FB170)
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L___POR    0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L___M      0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_20_L___S                    0

#define PHYA_TXBF_ERROR_EVENT_RD_20_U             (0x003FB174)
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U___POR    0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U___M      0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_20_U___S                    0

#define PHYA_TXBF_ERROR_EVENT_RD_21_L             (0x003FB178)
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L___POR    0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L___M      0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_21_L___S                    0

#define PHYA_TXBF_ERROR_EVENT_RD_21_U             (0x003FB17C)
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U___POR    0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U___M      0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_21_U___S                    0

#define PHYA_TXBF_ERROR_EVENT_RD_3_L              (0x003FB180)
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___POR 0x0
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___M 0x0000000F
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L___M       0x0000000F   
#define   PHYA_TXBF_ERROR_EVENT_RD_3_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_4_L              (0x003FB1A8)
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_4_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_4_U              (0x003FB1AC)
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___M 0x3F000000
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___S              24
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___M 0x003F0000
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___S              16
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___M 0x00003F00
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___S               8
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___M 0x0000003F
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U___M       0x3F3F3F3F   
#define   PHYA_TXBF_ERROR_EVENT_RD_4_U___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_5_L              (0x003FB1B0)
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___POR 0x00
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___M 0x3F000000
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___S              24
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___M 0x003F0000
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___S              16
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___M 0x00003F00
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___S               8
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___M 0x0000003F
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L___M       0x3F3F3F3F   
#define   PHYA_TXBF_ERROR_EVENT_RD_5_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_6_L              (0x003FB1B8)
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_6_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_6_U              (0x003FB1BC)
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_6_U___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_7_L              (0x003FB1C0)
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_7_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_7_U              (0x003FB1C4)
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___POR 0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___M 0xFFFFFFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_7_U___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_8_L              (0x003FB1C8)
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___POR 0x0
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___M 0x00000003
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L___M       0x00000003   
#define   PHYA_TXBF_ERROR_EVENT_RD_8_L___S                     0

#define PHYA_TXBF_ERROR_EVENT_RD_9_L              (0x003FB1D0)
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L___RWC        QCSR_REG_RO    
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___POR 0x0000
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___POR 0x0000
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___M 0xFFFF0000
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___S              16
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___M 0x0000FFFF
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___S               0
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L___M       0xFFFFFFFF   
#define   PHYA_TXBF_ERROR_EVENT_RD_9_L___S                     0

#define PHYA_TXBF_USER_ERROR_EVENT_RD_L           (0x003FB1D8)
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L___RWC     QCSR_REG_RO    
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L___POR  0x00000000
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___POR 0x00000000
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___M 0xFFFFFFFF
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___S               0
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L___M    0xFFFFFFFF   
#define   PHYA_TXBF_USER_ERROR_EVENT_RD_L___S                  0

#define PHYA_TXBF_DEBUG_RD_00_L                   (0x003FB270)
#define   PHYA_TXBF_DEBUG_RD_00_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_00_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___S               0
#define   PHYA_TXBF_DEBUG_RD_00_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_00_L___S                          0

#define PHYA_TXBF_DEBUG_RD_00_U                   (0x003FB274)
#define   PHYA_TXBF_DEBUG_RD_00_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_00_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___S               0
#define   PHYA_TXBF_DEBUG_RD_00_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_00_U___S                          0

#define PHYA_TXBF_DEBUG_RD_01_L                   (0x003FB278)
#define   PHYA_TXBF_DEBUG_RD_01_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_01_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___S               0
#define   PHYA_TXBF_DEBUG_RD_01_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_01_L___S                          0

#define PHYA_TXBF_DEBUG_RD_01_U                   (0x003FB27C)
#define   PHYA_TXBF_DEBUG_RD_01_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_01_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___S               0
#define   PHYA_TXBF_DEBUG_RD_01_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_01_U___S                          0

#define PHYA_TXBF_DEBUG_RD_02_L                   (0x003FB280)
#define   PHYA_TXBF_DEBUG_RD_02_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_02_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___S               0
#define   PHYA_TXBF_DEBUG_RD_02_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_02_L___S                          0

#define PHYA_TXBF_DEBUG_RD_02_U                   (0x003FB284)
#define   PHYA_TXBF_DEBUG_RD_02_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_02_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___S               0
#define   PHYA_TXBF_DEBUG_RD_02_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_02_U___S                          0

#define PHYA_TXBF_DEBUG_RD_03_L                   (0x003FB288)
#define   PHYA_TXBF_DEBUG_RD_03_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_03_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___S               0
#define   PHYA_TXBF_DEBUG_RD_03_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_03_L___S                          0

#define PHYA_TXBF_DEBUG_RD_03_U                   (0x003FB28C)
#define   PHYA_TXBF_DEBUG_RD_03_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_03_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___S               0
#define   PHYA_TXBF_DEBUG_RD_03_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_03_U___S                          0

#define PHYA_TXBF_DEBUG_RD_04_L                   (0x003FB290)
#define   PHYA_TXBF_DEBUG_RD_04_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_04_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___S               0
#define   PHYA_TXBF_DEBUG_RD_04_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_04_L___S                          0

#define PHYA_TXBF_DEBUG_RD_04_U                   (0x003FB294)
#define   PHYA_TXBF_DEBUG_RD_04_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_04_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___S               0
#define   PHYA_TXBF_DEBUG_RD_04_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_04_U___S                          0

#define PHYA_TXBF_DEBUG_RD_05_L                   (0x003FB298)
#define   PHYA_TXBF_DEBUG_RD_05_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_05_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___S               0
#define   PHYA_TXBF_DEBUG_RD_05_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_05_L___S                          0

#define PHYA_TXBF_DEBUG_RD_05_U                   (0x003FB29C)
#define   PHYA_TXBF_DEBUG_RD_05_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_05_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___S               0
#define   PHYA_TXBF_DEBUG_RD_05_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_05_U___S                          0

#define PHYA_TXBF_DEBUG_RD_06_L                   (0x003FB2A0)
#define   PHYA_TXBF_DEBUG_RD_06_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_06_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___S               0
#define   PHYA_TXBF_DEBUG_RD_06_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_06_L___S                          0

#define PHYA_TXBF_DEBUG_RD_06_U                   (0x003FB2A4)
#define   PHYA_TXBF_DEBUG_RD_06_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_06_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___S               0
#define   PHYA_TXBF_DEBUG_RD_06_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_06_U___S                          0

#define PHYA_TXBF_DEBUG_RD_07_L                   (0x003FB2A8)
#define   PHYA_TXBF_DEBUG_RD_07_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_07_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___S               0
#define   PHYA_TXBF_DEBUG_RD_07_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_07_L___S                          0

#define PHYA_TXBF_DEBUG_RD_07_U                   (0x003FB2AC)
#define   PHYA_TXBF_DEBUG_RD_07_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_07_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___S               0
#define   PHYA_TXBF_DEBUG_RD_07_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_07_U___S                          0

#define PHYA_TXBF_DEBUG_RD_08_L                   (0x003FB2B0)
#define   PHYA_TXBF_DEBUG_RD_08_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_08_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___S               0
#define   PHYA_TXBF_DEBUG_RD_08_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_08_L___S                          0

#define PHYA_TXBF_DEBUG_RD_08_U                   (0x003FB2B4)
#define   PHYA_TXBF_DEBUG_RD_08_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_08_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___S               0
#define   PHYA_TXBF_DEBUG_RD_08_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_08_U___S                          0

#define PHYA_TXBF_DEBUG_RD_09_L                   (0x003FB2B8)
#define   PHYA_TXBF_DEBUG_RD_09_L___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_09_L___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___S               0
#define   PHYA_TXBF_DEBUG_RD_09_L___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_09_L___S                          0

#define PHYA_TXBF_DEBUG_RD_09_U                   (0x003FB2BC)
#define   PHYA_TXBF_DEBUG_RD_09_U___RWC             QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_09_U___POR          0x00000000
#define   PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___S               0
#define   PHYA_TXBF_DEBUG_RD_09_U___M            0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_09_U___S                          0

#define PHYA_TXBF_DEBUG_RD_010_L                  (0x003FB2C0)
#define   PHYA_TXBF_DEBUG_RD_010_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_010_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___S               0
#define   PHYA_TXBF_DEBUG_RD_010_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_010_L___S                         0

#define PHYA_TXBF_DEBUG_RD_010_U                  (0x003FB2C4)
#define   PHYA_TXBF_DEBUG_RD_010_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_010_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___S               0
#define   PHYA_TXBF_DEBUG_RD_010_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_010_U___S                         0

#define PHYA_TXBF_DEBUG_RD_011_L                  (0x003FB2C8)
#define   PHYA_TXBF_DEBUG_RD_011_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_011_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___S               0
#define   PHYA_TXBF_DEBUG_RD_011_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_011_L___S                         0

#define PHYA_TXBF_DEBUG_RD_011_U                  (0x003FB2CC)
#define   PHYA_TXBF_DEBUG_RD_011_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_011_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___S               0
#define   PHYA_TXBF_DEBUG_RD_011_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_011_U___S                         0

#define PHYA_TXBF_DEBUG_RD_012_L                  (0x003FB2D0)
#define   PHYA_TXBF_DEBUG_RD_012_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_012_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___S               0
#define   PHYA_TXBF_DEBUG_RD_012_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_012_L___S                         0

#define PHYA_TXBF_DEBUG_RD_012_U                  (0x003FB2D4)
#define   PHYA_TXBF_DEBUG_RD_012_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_012_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___S               0
#define   PHYA_TXBF_DEBUG_RD_012_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_012_U___S                         0

#define PHYA_TXBF_DEBUG_RD_013_L                  (0x003FB2D8)
#define   PHYA_TXBF_DEBUG_RD_013_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_013_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___S               0
#define   PHYA_TXBF_DEBUG_RD_013_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_013_L___S                         0

#define PHYA_TXBF_DEBUG_RD_013_U                  (0x003FB2DC)
#define   PHYA_TXBF_DEBUG_RD_013_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_013_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___S               0
#define   PHYA_TXBF_DEBUG_RD_013_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_013_U___S                         0

#define PHYA_TXBF_DEBUG_RD_014_L                  (0x003FB2E0)
#define   PHYA_TXBF_DEBUG_RD_014_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_014_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___S               0
#define   PHYA_TXBF_DEBUG_RD_014_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_014_L___S                         0

#define PHYA_TXBF_DEBUG_RD_014_U                  (0x003FB2E4)
#define   PHYA_TXBF_DEBUG_RD_014_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_014_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___S               0
#define   PHYA_TXBF_DEBUG_RD_014_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_014_U___S                         0

#define PHYA_TXBF_DEBUG_RD_015_L                  (0x003FB2E8)
#define   PHYA_TXBF_DEBUG_RD_015_L___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_015_L___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___S               0
#define   PHYA_TXBF_DEBUG_RD_015_L___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_015_L___S                         0

#define PHYA_TXBF_DEBUG_RD_015_U                  (0x003FB2EC)
#define   PHYA_TXBF_DEBUG_RD_015_U___RWC            QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_015_U___POR         0x00000000
#define   PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___POR 0x00000000
#define   PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___M 0xFFFFFFFF
#define   PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___S               0
#define   PHYA_TXBF_DEBUG_RD_015_U___M           0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_015_U___S                         0

#define PHYA_TXBF_DEBUG_RD_1_L                    (0x003FB2F0)
#define   PHYA_TXBF_DEBUG_RD_1_L___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_1_L___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___POR 0x0
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___POR 0x0
#define   PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___POR 0x0
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___M 0x00010000
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___S              16
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___M 0x00000100
#define   PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___S               8
#define   PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___M 0x00000001
#define   PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___S               0
#define   PHYA_TXBF_DEBUG_RD_1_L___M             0x00010101   
#define   PHYA_TXBF_DEBUG_RD_1_L___S                           0

#define PHYA_TXBF_DEBUG_RD_1_U                    (0x003FB2F4)
#define   PHYA_TXBF_DEBUG_RD_1_U___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_1_U___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___M 0x03FF0000
#define   PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___S              16
#define   PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___M 0x000003FF
#define   PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___S               0
#define   PHYA_TXBF_DEBUG_RD_1_U___M             0x03FF03FF   
#define   PHYA_TXBF_DEBUG_RD_1_U___S                           0

#define PHYA_TXBF_DEBUG_RD_2_L                    (0x003FB2F8)
#define   PHYA_TXBF_DEBUG_RD_2_L___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_2_L___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___POR 0x00
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___M 0x007F0000
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___S              16
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___M 0x000003FF
#define   PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___S               0
#define   PHYA_TXBF_DEBUG_RD_2_L___M             0x007F03FF   
#define   PHYA_TXBF_DEBUG_RD_2_L___S                           0

#define PHYA_TXBF_DEBUG_RD_2_U                    (0x003FB2FC)
#define   PHYA_TXBF_DEBUG_RD_2_U___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_2_U___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___M 0x03FF0000
#define   PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___S              16
#define   PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___M 0x000003FF
#define   PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___S               0
#define   PHYA_TXBF_DEBUG_RD_2_U___M             0x03FF03FF   
#define   PHYA_TXBF_DEBUG_RD_2_U___S                           0

#define PHYA_TXBF_DEBUG_RD_3_L                    (0x003FB300)
#define   PHYA_TXBF_DEBUG_RD_3_L___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_3_L___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___POR 0x0000
#define   PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___POR 0x0000
#define   PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___M 0xFFFF0000
#define   PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___S              16
#define   PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___M 0x0000FFFF
#define   PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___S               0
#define   PHYA_TXBF_DEBUG_RD_3_L___M             0xFFFFFFFF   
#define   PHYA_TXBF_DEBUG_RD_3_L___S                           0

#define PHYA_TXBF_DEBUG_RD_3_U                    (0x003FB304)
#define   PHYA_TXBF_DEBUG_RD_3_U___RWC              QCSR_REG_RO    
#define   PHYA_TXBF_DEBUG_RD_3_U___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___POR 0x000
#define   PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___M 0x000003FF
#define   PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___S               0
#define   PHYA_TXBF_DEBUG_RD_3_U___M             0x000003FF   
#define   PHYA_TXBF_DEBUG_RD_3_U___S                           0

#define PHYA_TXBF_FSM_L                           (0x003FB308)
#define   PHYA_TXBF_FSM_L___RWC                     QCSR_REG_RO    
#define   PHYA_TXBF_FSM_L___POR                  0x00000000
#define   PHYA_TXBF_FSM_L__AC_INTERPS_STATE___POR 0x0
#define   PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___POR 0x0
#define   PHYA_TXBF_FSM_L__POWER_WTG_STATE___POR 0x0
#define   PHYA_TXBF_FSM_L__INTERPV_STATE___POR   0x0
#define   PHYA_TXBF_FSM_L__AC_INTERPS_STATE___M  0x03000000
#define   PHYA_TXBF_FSM_L__AC_INTERPS_STATE___S               24
#define   PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___M 0x00030000
#define   PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___S              16
#define   PHYA_TXBF_FSM_L__POWER_WTG_STATE___M   0x00000700
#define   PHYA_TXBF_FSM_L__POWER_WTG_STATE___S                 8
#define   PHYA_TXBF_FSM_L__INTERPV_STATE___M     0x00000003
#define   PHYA_TXBF_FSM_L__INTERPV_STATE___S                   0
#define   PHYA_TXBF_FSM_L___M                    0x03030703   
#define   PHYA_TXBF_FSM_L___S                                  0

#define PHYA_TXBF_FSM_U                           (0x003FB30C)
#define   PHYA_TXBF_FSM_U___RWC                     QCSR_REG_RO    
#define   PHYA_TXBF_FSM_U___POR                  0x00000000
#define   PHYA_TXBF_FSM_U__BF_PARAMS_STATE___POR 0x0
#define   PHYA_TXBF_FSM_U__BF_PARAMS_STATE___M   0x0000000F
#define   PHYA_TXBF_FSM_U__BF_PARAMS_STATE___S                 0
#define   PHYA_TXBF_FSM_U___M                    0x0000000F   
#define   PHYA_TXBF_FSM_U___S                                  0

#define PHYA_TXBF_ERROR_EVENT_WR_0_L              (0x003FB310)
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L___RWC        QCSR_REG_WO    
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___POR 0x0
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___M 0x00000001
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___S               0
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L___M       0x00000001   
#define   PHYA_TXBF_ERROR_EVENT_WR_0_L___S                     0

#define PHYA_TXBF_DEBUG_RD_4_L                    (0x003FB318)
#define   PHYA_TXBF_DEBUG_RD_4_L___RWC              QCSR_REG_WO    
#define   PHYA_TXBF_DEBUG_RD_4_L___POR           0x00000000
#define   PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___POR 0x00
#define   PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___POR 0x0
#define   PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___M 0x0000FF00
#define   PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___S               8
#define   PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___M 0x0000000F
#define   PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___S               0
#define   PHYA_TXBF_DEBUG_RD_4_L___M             0x0000FF0F   
#define   PHYA_TXBF_DEBUG_RD_4_L___S                           0

#define PHYA_TXBF_ERROR_EVENT_WR_1_L              (0x003FB320)
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L___RWC        QCSR_REG_WO    
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L___POR     0x00000000
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___POR 0x0
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___M 0x00000001
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___S               0
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L___M       0x00000001   
#define   PHYA_TXBF_ERROR_EVENT_WR_1_L___S                     0

#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L             (0x003FB328)
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L___RWC       QCSR_REG_RW    
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L___POR    0x00000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___POR 0x0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___POR 0x0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___M 0x00000100
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___S               8
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___M 0x00000001
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___S               0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L___M      0x00000101   
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_L___S                    0

#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L       (0x003FB378)
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___POR 0x0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___M 0x00000001
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___S               0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___M 0x00000001   
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___S               0

#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U       (0x003FB37C)
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___M 0xFFFFFFFF
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___S               0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___S               0

#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L       (0x003FB380)
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___M 0xFFFFFFFF
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___S               0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___S               0

#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U       (0x003FB384)
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___M 0xFFFFFFFF
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___S               0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___S               0

#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L       (0x003FB388)
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___POR 0x00000000
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___M 0xFFFFFFFF
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___S               0
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___S               0

#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L         (0x003FB6F0)
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___POR 0x00000000
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___POR 0x00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___POR 0x00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___M 0x00003F00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___S               8
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___M 0x0000003F
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___S               0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___M  0x00003F3F   
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___S                0

#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L         (0x003FB6F8)
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___POR 0x00000000
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___M 0x00000F00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___S               8
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___M 0x0000000F
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___S               0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___M  0x00000F0F   
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___S                0

#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L         (0x003FB700)
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___POR 0x00000000
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___M 0x00000700
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___S               8
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___M 0x00000007
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___S               0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___M  0x00000707   
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___S                0

#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L           (0x003FBA68)
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___RWC     QCSR_REG_WO    
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___POR  0x00000000
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___POR 0x0
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___POR 0x0
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___M 0x00000100
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___S               8
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___M 0x00000001
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___S               0
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___M    0x00000101   
#define   PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___S                  0

#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L          (0x003FBA70)
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___S               0
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___S                 0

#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U          (0x003FBA74)
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___S               0
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___S                 0

#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L       (0x003FBA78)
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___POR 0x00000000
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___POR 0x00
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___POR 0x00
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___POR 0x0
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___POR 0x0
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___M 0x7F000000
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___S              24
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___M 0x00FF0000
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___S              16
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___M 0x00000300
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___S               8
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___M 0x00000001
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___S               0
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___M 0x7FFF0301   
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___S               0

#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U       (0x003FBA7C)
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___POR 0x00000000
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___POR 0x00
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___POR 0x0
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___M 0x0000FF00
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___S               8
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___M 0x00000001
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___S               0
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___M 0x0000FF01   
#define   PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___S               0

#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L         (0x003FBA80)
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___POR 0x00000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___POR 0x0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___POR 0x0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___POR 0x00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___POR 0x0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___M 0x07000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___S              24
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___M 0x00070000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___S              16
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___M 0x00007F00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___S               8
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___M 0x00000001
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___S               0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___M  0x07077F01   
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___S                0

#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U         (0x003FBA84)
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___POR 0x00000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___POR 0x00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___M 0x000000FF
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___S               0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___M  0x000000FF   
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___S                0

#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L         (0x003FBA88)
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___POR 0x00000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___POR 0x00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___POR 0x00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___M 0x00003F00
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___S               8
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___M 0x0000003F
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___S               0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___M  0x00003F3F   
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___S                0

#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L         (0x003FBA90)
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___RWC   QCSR_REG_RW    
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___POR 0x00000000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___POR 0x0000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___POR 0x0000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___M 0xFFFF0000
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___S              16
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___M 0x0000FFFF
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___S               0
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___M  0xFFFFFFFF   
#define   PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___S                0

#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L       (0x003FBF20)
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___POR 0x00000000
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___POR 0x0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___M 0x00000100
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___S               8
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___M 0x00000007
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___S               0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___M 0x00000107   
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___S               0

#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L       (0x003FBF28)
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___POR 0x00000000
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___POR 0x00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___POR 0x00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___M 0x0000FF00
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___S               8
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___M 0x000000FF
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___S               0
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___M 0x0000FFFF   
#define   PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___S               0

#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L        (0x003FC170)
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___RWC  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___S               0
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___S               0

#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U        (0x003FC174)
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___RWC  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___S               0
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___S               0

#define PHYA_TXBF_TXBF_PARAMS__RD_0_L             (0x003FC178)
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L___POR    0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___POR 0x0
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___M 0x00000001
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___S               0
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L___M      0x00000001   
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_L___S                    0

#define PHYA_TXBF_TXBF_PARAMS__RD_0_U             (0x003FC17C)
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U___POR    0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___S               0
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U___M      0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS__RD_0_U___S                    0

#define PHYA_TXBF_TXBF_PARAMS__RD_1_L             (0x003FC180)
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L___POR    0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___S               0
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L___M      0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_L___S                    0

#define PHYA_TXBF_TXBF_PARAMS__RD_1_U             (0x003FC184)
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U___RWC       QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U___POR    0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___S               0
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U___M      0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS__RD_1_U___S                    0

#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L        (0x003FC188)
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___RWC  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___S               0
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___S               0

#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U        (0x003FC18C)
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___RWC  QCSR_REG_RW    
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___S               0
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___S               0

#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L (0x003FC190)
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___POR 0x00400000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___POR 0x0040
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___POR 0x0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___M 0xFFFF0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___S              16
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___M 0x0000FFFF
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___S               0
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___S               0

#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U (0x003FC194)
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___POR 0x00200010
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___POR 0x0020
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___POR 0x0010
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___M 0xFFFF0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___S              16
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___M 0x0000FFFF
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___S               0
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___S               0

#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L (0x003FC198)
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___POR 0x00400000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___POR 0x0040
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___POR 0x0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___M 0xFFFF0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___S              16
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___M 0x0000FFFF
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___S               0
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___S               0

#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U (0x003FC19C)
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___POR 0x00200010
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___POR 0x0020
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___POR 0x0010
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___M 0xFFFF0000
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___S              16
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___M 0x0000FFFF
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___S               0
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___S               0

#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n(n) (0x003FC630+0x8*(n))
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_nMIN 0    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_nMAX 0    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_ELEM 1    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___RWC QCSR_REG_RW    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___POR 0x00000000
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___POR 0x00000000
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___M 0xFFFFFFFF
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___S               0
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___M 0xFFFFFFFF   
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___S               0
#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0 (0x003FC630)
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0___RWC QCSR_REG_RW    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0__DDR_DEST_ADDR_0___M 0xFFFFFFFF
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0__DDR_DEST_ADDR_0___S               0

#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n(n) (0x003FC634+0x8*(n))
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_nMIN 0    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_nMAX 0    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_ELEM 1    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___RWC QCSR_REG_RW    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___POR 0x00000000
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___POR 0x00000000
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___M 0xFFFFFFFF
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___S               0
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___M 0xFFFFFFFF   
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___S               0
#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0 (0x003FC634)
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0___RWC QCSR_REG_RW    
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0__DDR_DEST_ADDR_1___M 0xFFFFFFFF
#define   PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0__DDR_DEST_ADDR_1___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L    (0x003FD030)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U    (0x003FD034)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___S               0

#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L (0x003FD038)
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___POR 0x00000000
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___POR 0x00
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___POR 0x0
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___M 0x00003F00
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___S               8
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___M 0x00000001
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___S               0
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___M 0x00003F01   
#define   PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L (0x003FD040)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___M 0x07FF0000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___M 0x00000001
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___M 0x07FF0001   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U (0x003FD044)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___POR 0x00
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___M 0x7F000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___S              24
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___M 0x00070000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___M 0x000007FF
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___M 0x7F0707FF   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L (0x003FD048)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___M 0x00000700
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___S               8
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___M 0x00000007
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___M 0x00000707   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L (0x003FD050)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___M 0x07FF0000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___M 0x00000001
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___M 0x07FF0001   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U (0x003FD054)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___POR 0x00
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___M 0x7F000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___S              24
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___M 0x00070000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___M 0x000007FF
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___M 0x7F0707FF   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L (0x003FD058)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___M 0x00000700
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___S               8
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___M 0x00000007
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___M 0x00000707   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L (0x003FD060)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___M 0x07FF0000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___M 0x00000001
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___M 0x07FF0001   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U (0x003FD064)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___POR 0x00
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___M 0x7F000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___S              24
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___M 0x00070000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___M 0x000007FF
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___M 0x7F0707FF   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L (0x003FD068)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___M 0x00000700
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___S               8
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___M 0x00000007
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___M 0x00000707   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L (0x003FD070)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___M 0x07FF0000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___M 0x00000001
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___M 0x07FF0001   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U (0x003FD074)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___POR 0x00
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___M 0x7F000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___S              24
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___M 0x00070000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___M 0x000007FF
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___M 0x7F0707FF   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L (0x003FD078)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___M 0x00000700
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___S               8
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___M 0x00000007
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___M 0x00000707   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L (0x003FD080)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___M 0x07FF0000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___M 0x00000001
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___M 0x07FF0001   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___S               0

#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U (0x003FD084)
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___POR 0x00000000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___POR 0x0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___POR 0x000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___M 0x00070000
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___S              16
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___M 0x000007FF
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___S               0
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___M 0x000707FF   
#define   PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L  (0x003FDAA8)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U  (0x003FDAAC)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L       (0x003FDAB0)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U       (0x003FDAB4)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L       (0x003FDAB8)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U       (0x003FDABC)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L       (0x003FDAC0)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U       (0x003FDAC4)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L       (0x003FDAC8)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U       (0x003FDACC)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L       (0x003FDAD0)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U       (0x003FDAD4)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L       (0x003FDAD8)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___S               0

#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U       (0x003FDADC)
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___POR 0x00000000
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___M 0xFFFFFFFF
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___S               0
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___S               0

#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L (0x003FDAE0)
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___M 0x01000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___S              24
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___M 0x00030000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___S              16
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___M 0x00000700
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___S               8
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___M 0x00000007
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___S               0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___M 0x01030707   
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___S               0

#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U (0x003FDAE4)
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___POR 0x0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___M 0x00000300
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___S               8
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___M 0x00000001
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___S               0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___M 0x00000301   
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___S               0

#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L (0x003FDAE8)
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___M 0xFFFFFFFF
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___S               0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___S               0

#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U (0x003FDAEC)
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___RWC QCSR_REG_RO    
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___M 0xFFFFFFFF
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___S               0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___S               0

#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L (0x003FDAF0)
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___RWC QCSR_REG_RO    
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___POR 0x00000000
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___M 0xFFFFFFFF
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___S               0
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___S               0

#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L        (0x003FDE58)
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___RWC  QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___S               0
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___S               0

#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U        (0x003FDE5C)
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___RWC  QCSR_REG_RO    
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___POR 0x00000000
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___S               0
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___M 0xFFFFFFFF   
#define   PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___S               0

#define PHYA_DEMFRONT_0_RESET_CTRL_L              (0x00400000)
#define   PHYA_DEMFRONT_0_RESET_CTRL_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RESET_CTRL_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___POR 0x0
#define   PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___M 0x00000001
#define   PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___S               0
#define   PHYA_DEMFRONT_0_RESET_CTRL_L___M       0x00000001   
#define   PHYA_DEMFRONT_0_RESET_CTRL_L___S                     0

#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L          (0x00400008)
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___S               0
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___S                 0

#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U          (0x0040000C)
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___POR 0x00000000
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___S               0
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___S                 0

#define PHYA_DEMFRONT_0_EVENT_STATUS_L            (0x00400010)
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L___POR   0x000000C4
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___M 0x00008000
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___S              15
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___M 0x00004000
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___S              14
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___M 0x00002000
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___S              13
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___M 0x00001000
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___S              12
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___M 0x00000800
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___S              11
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___M 0x00000400
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___S              10
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___M 0x00000100
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___S               8
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___M 0x00000080
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___S               7
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___M 0x00000040
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___S               6
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___M 0x00000020
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___S               5
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___M 0x00000010
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___S               4
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___M 0x00000008
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___S               3
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___M 0x00000004
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___S               2
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L___M     0x0000FDFF   
#define   PHYA_DEMFRONT_0_EVENT_STATUS_L___S                   0

#define PHYA_DEMFRONT_0_EVENT_MASK_L              (0x00400018)
#define   PHYA_DEMFRONT_0_EVENT_MASK_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_EVENT_MASK_L___POR     0x0000FDFF
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___M 0x00008000
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___S              15
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___M 0x00004000
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___S              14
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___M 0x00002000
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___S              13
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___M 0x00001000
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___S              12
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___M 0x00000800
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___S              11
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___M 0x00000400
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___S              10
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___M 0x00000100
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___S               8
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___M 0x00000080
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___S               7
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___M 0x00000040
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___S               6
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___M 0x00000020
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___S               5
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___M 0x00000010
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___S               4
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___M 0x00000008
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___S               3
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___M 0x00000004
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___S               2
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_DEMFRONT_0_EVENT_MASK_L___M       0x0000FDFF   
#define   PHYA_DEMFRONT_0_EVENT_MASK_L___S                     0

#define PHYA_DEMFRONT_0_ERROR_MASK_L              (0x00400020)
#define   PHYA_DEMFRONT_0_ERROR_MASK_L___RWC        QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_ERROR_MASK_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___POR 0x00
#define   PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___M 0x0000003F
#define   PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___S               0
#define   PHYA_DEMFRONT_0_ERROR_MASK_L___M       0x0000003F   
#define   PHYA_DEMFRONT_0_ERROR_MASK_L___S                     0

#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L      (0x00400028)
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___M 0x80000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___S              31
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___M 0x40000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___S              30
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___M 0x10000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___S              28
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___M 0x08000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___S              27
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___M 0x04000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___S              26
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___M 0x01000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___S              24
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___M 0x00800000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___S              23
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___M 0x00400000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___S              22
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___M 0x00200000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___S              21
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___M 0x00100000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___S              20
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___M 0x00080000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___S              19
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___M 0x00010000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___S              16
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___M 0x00008000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___S              15
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___M 0x00004000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___S              14
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___M 0x00002000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___S              13
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___M 0x00001000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___S              12
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___M 0x00000800
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___S              11
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___M 0x00000400
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___S              10
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___M 0x00000200
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___S               9
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___M 0x00000100
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___S               8
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___M 0x00000040
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___S               6
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___M 0x00000020
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___S               5
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___M 0x00000010
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___S               4
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___M 0x00000008
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___S               3
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___M 0x00000004
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___S               2
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___M 0x00000002
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___S               1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___M 0x00000001
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___S               0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___M 0xDDF9FF7F   
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___S               0

#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U      (0x0040002C)
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___M 0x80000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___S              31
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___M 0x40000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___S              30
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___M 0x20000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___S              29
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___M 0x10000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___S              28
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___M 0x08000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___S              27
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___M 0x04000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___S              26
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___M 0x02000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___S              25
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___M 0x01000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___S              24
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___M 0x00800000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___S              23
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___M 0x00400000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___S              22
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___M 0x00200000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___S              21
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___M 0x00100000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___S              20
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___M 0x00080000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___S              19
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___M 0x00040000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___S              18
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___M 0x00020000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___S              17
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___M 0x00010000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___S              16
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___M 0x00008000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___S              15
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___M 0x00004000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___S              14
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___M 0x00002000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___S              13
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___M 0x00001000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___S              12
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___M 0x00000800
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___S              11
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___M 0x00000400
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___S              10
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___M 0x00000200
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___S               9
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___M 0x00000100
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___S               8
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___M 0x00000080
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___S               7
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___M 0x00000010
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___S               4
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___M 0x00000008
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___S               3
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___M 0x00000004
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___S               2
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___M 0x00000002
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___S               1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___M 0x00000001
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___S               0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___M 0xFFFFFF9F   
#define   PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___S               0

#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L        (0x00400030)
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___POR 0xDDF9FF7F
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___M 0x80000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___S              31
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___M 0x40000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___S              30
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___M 0x10000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___S              28
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___M 0x08000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___S              27
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___M 0x04000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___S              26
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___M 0x01000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___S              24
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___M 0x00800000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___S              23
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___M 0x00400000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___S              22
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___M 0x00200000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___S              21
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___M 0x00100000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___S              20
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___M 0x00080000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___S              19
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___M 0x00010000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___S              16
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___M 0x00008000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___S              15
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___M 0x00004000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___S              14
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___M 0x00002000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___S              13
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___M 0x00001000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___S              12
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___M 0x00000800
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___S              11
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___M 0x00000400
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___S              10
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___M 0x00000200
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___S               9
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___M 0x00000100
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___S               8
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___M 0x00000040
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___S               6
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___M 0x00000020
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___S               5
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___M 0x00000010
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___S               4
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___M 0x00000008
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___S               3
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___M 0x00000004
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___S               2
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___M 0x00000002
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___S               1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___M 0x00000001
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___S               0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___M 0xDDF9FF7F   
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___S               0

#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U        (0x00400034)
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___POR 0xFFFFFF9F
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___M 0x80000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___S              31
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___M 0x40000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___S              30
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___M 0x20000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___S              29
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___M 0x10000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___S              28
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___M 0x08000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___S              27
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___M 0x04000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___S              26
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___M 0x02000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___S              25
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___M 0x01000000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___S              24
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___M 0x00800000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___S              23
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___M 0x00400000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___S              22
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___M 0x00200000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___S              21
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___M 0x00100000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___S              20
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___M 0x00080000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___S              19
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___M 0x00040000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___S              18
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___M 0x00020000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___S              17
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___M 0x00010000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___S              16
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___M 0x00008000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___S              15
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___M 0x00004000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___S              14
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___M 0x00002000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___S              13
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___M 0x00001000
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___S              12
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___M 0x00000800
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___S              11
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000400
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___S              10
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000200
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___S               9
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000100
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___S               8
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000080
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___S               7
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___M 0x00000010
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___S               4
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___M 0x00000008
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___S               3
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___M 0x00000004
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___S               2
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___M 0x00000002
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___S               1
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___M 0x00000001
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___S               0
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___M 0xFFFFFF9F   
#define   PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L    (0x00400038)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___POR 0x01000034
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___POR 0x1
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___POR 0x034
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___M 0x07000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___M 0x001F0000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___M 0x000003FF
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___M 0x071F03FF   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U    (0x0040003C)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___POR 0x00640000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___POR 0x064
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___M 0x01FF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___M 0x01FF0007   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L    (0x00400040)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___POR 0xFFE6FFE6
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___POR 0xFFE6
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___POR 0xFFE6
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L    (0x00400048)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___POR 0x00010100
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___POR 0x1
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___POR 0x1
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___M 0x0F000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___M 0x0F010101   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U    (0x0040004C)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___POR 0x00001003
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___POR 0x10
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___POR 0x03
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___M 0x0F000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___M 0x00070000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___M 0x00003F00
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___M 0x0000001F
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___M 0x0F073F1F   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L    (0x00400050)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___POR 0x000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___M 0x000003FF
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___M 0x010103FF   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U    (0x00400054)
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___M 0x01010101   
#define   PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L             (0x00400058)
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L___POR    0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___POR 0x01
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___M 0xFF000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___M 0x00FF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_L___S                    0

#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U             (0x0040005C)
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___M 0xFF000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___M 0x00FF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_CMD_U___S                    0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L          (0x00400060)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___POR 0xFFF9FFEB
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___POR 0xFFF9
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___POR 0xFFEB
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U          (0x00400064)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___POR 0x00150007
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___POR 0x0015
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___POR 0x0007
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L          (0x00400068)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U          (0x0040006C)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L          (0x00400070)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U          (0x00400074)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L          (0x00400078)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___S                 0

#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U          (0x0040007C)
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___S                 0

#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L (0x00400080)
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___M 0x07000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___S              24
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___S              16
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___M 0x00000F00
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___S               8
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___M 0x0000003F
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___M 0x07010F3F   
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U (0x00400084)
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___S               0

#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L (0x00400088)
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___M 0x07000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___S              24
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___M 0x00000F00
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___M 0x0000003F
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___M 0x07010F3F   
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U (0x0040008C)
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L       (0x004000A0)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U       (0x004000A4)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L       (0x004000D0)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U       (0x004000D4)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L    (0x004000D8)
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___M 0x00000001   
#define   PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L       (0x004000E0)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U       (0x004000E4)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L      (0x004000E8)
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___M 0x00000101   
#define   PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___S               0

#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L (0x004000F0)
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___M 0x00000700
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___M 0x00000707   
#define   PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L (0x00400100)
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___M 0x07000000
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___S              24
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___M 0x00070000
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___S              16
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___M 0x00000700
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___S               0

#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U (0x00400104)
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___M 0x00000700
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___S               8
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___M 0x00000007
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___S               0
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___M 0x00000707   
#define   PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L       (0x00400108)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U       (0x0040010C)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L  (0x00400110)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U  (0x00400114)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L  (0x00400118)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U  (0x0040011C)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L   (0x00400128)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___POR 0x00040000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___POR 0x4
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___M 0x00070000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___M 0x01070000   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___S              16

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U   (0x0040012C)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___M 0x0101FFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L   (0x00400130)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U   (0x00400134)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L   (0x00400138)
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___M 0x00000001   
#define   PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L     (0x00400140)
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___M 0x01010101   
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U     (0x00400144)
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___M 0x00000001   
#define   PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L   (0x00400148)
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___M 0x01000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___M 0x00010000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___M 0x0000001F
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___M 0x0101011F   
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U   (0x0040014C)
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___POR 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___POR 0x000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___POR 0x1
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___M 0x03FF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___M 0x00000003
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___M 0x03FF0103   
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L   (0x00400150)
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___M 0x0000000F
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___M 0xFFFF010F   
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U   (0x00400154)
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L       (0x00400158)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U       (0x0040015C)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L       (0x00400160)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L       (0x00400168)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L       (0x00400170)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___M 0x00000101   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L       (0x00400178)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___M 0x3FFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___M 0x00003FFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___M 0x3FFF3FFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L       (0x00400180)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___M 0x3FFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___M 0x00003FFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___M 0x3FFF3FFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L       (0x00400188)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___M 0x00000300
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___M 0x00000003
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___M 0x00000303   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L       (0x00400198)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___M 0x00000100
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___M 0x00000001
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___M 0x00000101   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U        (0x004001A4)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L        (0x004001A8)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U        (0x004001AC)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L        (0x004001B0)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U        (0x004001B4)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___M 0x000000FF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___M 0xFFFF00FF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L        (0x004001B8)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___M 0x000F0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___M 0x000FFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L        (0x004001C0)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U        (0x004001C4)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L        (0x004001C8)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___POR 0x00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___M 0x00FF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___M 0x00FFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U        (0x004001CC)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___POR 0x0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___S               0

#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L          (0x004001D0)
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___POR 0x0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___M 0x0F000000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___S              24
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___M 0x00030000
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___S              16
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___M 0x00000F00
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___S               8
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___M 0x00000003
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___M   0x0F030F03   
#define   PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___S                 0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L       (0x004001D8)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U       (0x004001DC)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L       (0x004001E0)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___S               0

#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U       (0x004001E4)
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___S               0

#define PHYA_DEMFRONT_0_USER_SPARE_0_L            (0x004001E8)
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_0_L___S                   0

#define PHYA_DEMFRONT_0_USER_SPARE_0_U            (0x004001EC)
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_0_U___S                   0

#define PHYA_DEMFRONT_0_RU_BD_EVM0_L              (0x004001F0)
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM0_U              (0x004001F4)
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM0_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM1_L              (0x004001F8)
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM1_U              (0x004001FC)
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM1_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM2_L              (0x00400200)
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM2_U              (0x00400204)
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM2_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM3_L              (0x00400208)
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM3_U              (0x0040020C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM3_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM4_L              (0x00400210)
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM4_U              (0x00400214)
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM4_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM5_L              (0x00400218)
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM5_U              (0x0040021C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM5_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM6_L              (0x00400220)
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM6_U              (0x00400224)
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM6_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM7_L              (0x00400228)
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM7_U              (0x0040022C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM7_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM8_L              (0x00400230)
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM8_U              (0x00400234)
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM8_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM9_L              (0x00400238)
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_L___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM9_U              (0x0040023C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM9_U___S                     0

#define PHYA_DEMFRONT_0_RU_BD_EVM10_L             (0x00400240)
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM10_U             (0x00400244)
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM10_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM11_L             (0x00400248)
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM11_U             (0x0040024C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM11_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM12_L             (0x00400250)
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM12_U             (0x00400254)
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM12_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM13_L             (0x00400258)
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM13_U             (0x0040025C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM13_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM14_L             (0x00400260)
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM14_U             (0x00400264)
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM14_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM15_L             (0x00400268)
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_EVM15_U             (0x0040026C)
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___S               0
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_RU_BD_EVM15_U___S                    0

#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L             (0x00400270)
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L___RWC       QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___M 0x0FFF0000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___M 0x00000FFF
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L___M      0x0FFF0FFF   
#define   PHYA_DEMFRONT_0_RU_BD_QRE_0_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L             (0x00400278)
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L___RWC       QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___M 0x0FFF0000
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___M 0x00000FFF
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L___M      0x0FFF0FFF   
#define   PHYA_DEMFRONT_0_RU_BD_QRE_1_L___S                    0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L           (0x004003F0)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___POR 0x0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___M 0x00000001
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___M    0x00000001   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L           (0x004003F8)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___S               8
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L           (0x00400400)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___S               8
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L           (0x00400408)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___POR 0x00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___S               8
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L           (0x00400410)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L           (0x00400418)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L           (0x00400420)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L           (0x00400428)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L           (0x00400430)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L           (0x00400438)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___S                  0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L          (0x00400440)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___RWC    QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___M   0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___S                 0

#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L          (0x00400448)
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___RWC    QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___POR 0x000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___M 0x07FF0000
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___S              16
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___M 0x000007FF
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___S               0
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___M   0x07FF07FF   
#define   PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___S                 0

#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n(n) (0x004004B8+0x8*(n))
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n___POR   0x00000000
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___S               0
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_n___S                   0
#define PHYA_DEMFRONT_0_SDF_BUFFER_L_0            (0x004004B8)
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_0___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_0__SDF_BUFFER_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SDF_BUFFER_L_0__SDF_BUFFER_0___S               0

#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n(n) (0x004004BC+0x8*(n))
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n___POR   0x00000000
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___S               0
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_n___S                   0
#define PHYA_DEMFRONT_0_SDF_BUFFER_U_0            (0x004004BC)
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_0___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_0__SDF_BUFFER_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SDF_BUFFER_U_0__SDF_BUFFER_1___S               0

#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L           (0x004004C0)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___M 0x03000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L___M    0x03010101   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U           (0x004004C4)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U___POR  0x00000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___M 0x3F000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___M 0x003F0000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___M 0x000000FF
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U___M    0x3F3FFFFF   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L           (0x004004C8)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___M 0x01000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L___M    0x01010101   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U           (0x004004CC)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U___POR  0x00000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___M 0x07000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U___M    0x07010101   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_1_U___S                  0

#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L           (0x004004D0)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L___POR  0x01000002
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___POR 0x2
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___M 0x01000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___M 0x0000000F
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L___M    0x0101010F   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_L___S                  0

#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U           (0x004004D4)
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U___POR  0x04010101
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___POR 0x4
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___POR 0x1
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___M 0x0F000000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___S              24
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___S              16
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___S               8
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___S               0
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U___M    0x0F010101   
#define   PHYA_DEMFRONT_0_SYM_CONTROL_2_U___S                  0

#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L           (0x004004D8)
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L___POR  0x30000000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___POR 0x30
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___M 0x3F000000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___S              24
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___M 0x00010000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___S              16
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___M 0x00000001
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___S               0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L___M    0x3F010001   
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U           (0x004004DC)
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U___POR  0x00003000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___POR 0x30
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___M 0x01000000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___S              24
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___M 0x00010000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___S              16
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___M 0x00003F00
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___S               8
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___M 0x00000001
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___S               0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U___M    0x01013F01   
#define   PHYA_DEMFRONT_0_MRC_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L           (0x004004E0)
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L___POR  0x08000000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___POR 0x8
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___POR 0x0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___M 0x0F000000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___S              24
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___M 0x00010000
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___S              16
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___M 0x00000300
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___S               8
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___M 0x00000001
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___S               0
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L___M    0x0F010301   
#define   PHYA_DEMFRONT_0_MRC_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_0_USER_SPARE_1_L            (0x004004E8)
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_1_L___S                   0

#define PHYA_DEMFRONT_0_USER_SPARE_1_U            (0x004004EC)
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_1_U___S                   0

#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L       (0x004004F0)
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___POR 0x0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___POR 0x0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___POR 0x0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___POR 0x0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___M 0x01000000
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___S              24
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___M 0x00010000
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___S              16
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___M 0x00000100
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___S               8
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___M 0x00000001
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___S               0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___M 0x01010101   
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___S               0

#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U       (0x004004F4)
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___POR 0x0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___M 0x00000001
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___S               0
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___M 0x00000001   
#define   PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___S               0

#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L      (0x004004F8)
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L      (0x00400500)
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U      (0x00400504)
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L      (0x00400508)
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L      (0x00400510)
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L      (0x00400518)
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U      (0x0040051C)
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L      (0x00400520)
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L      (0x00400528)
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L      (0x00400530)
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U      (0x00400534)
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L      (0x00400538)
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L      (0x00400540)
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L      (0x00400548)
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U      (0x0040054C)
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L      (0x00400550)
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L      (0x00400558)
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L      (0x00400560)
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U      (0x00400564)
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L      (0x00400568)
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L      (0x00400570)
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L      (0x00400578)
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U      (0x0040057C)
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L      (0x00400580)
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L      (0x00400588)
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L      (0x00400590)
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U      (0x00400594)
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L      (0x00400598)
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L      (0x004005A0)
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L      (0x004005A8)
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U      (0x004005AC)
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L      (0x004005B0)
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L           (0x004005B8)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L___POR  0x02000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___POR 0x2
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___M 0x03000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___M 0x00070000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___M 0x00000F00
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___M 0x00000003
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L___M    0x03070F03   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U           (0x004005BC)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___M 0x01000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___M 0x00000100
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U___M    0x01010101   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L           (0x004005C0)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L___POR  0x02000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___POR 0x200
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___M 0x03FF0000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___M 0x00000300
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L___M    0x03FF0301   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U           (0x004005C4)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___M 0x01000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___M 0x00000100
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U___M    0x01010101   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_1_U___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L           (0x004005C8)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___M 0x01000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___M 0x00000100
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L___M    0x01010101   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_L___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U           (0x004005CC)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___M 0x07000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___M 0x00000100
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U___M    0x07010101   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_2_U___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L           (0x004005D0)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___M 0x03000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___M 0x00000700
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L___M    0x03010701   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_L___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U           (0x004005D4)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U___POR  0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___POR 0x1
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___POR 0x000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___M 0x0F000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___M 0x000003FF
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U___M    0x0F0103FF   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_3_U___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L           (0x004005D8)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L___POR  0x00000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___POR 0x0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___M 0x00030000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___M 0x00000300
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___S               8
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___M 0x00000001
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L___M    0x00030301   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_L___S                  0

#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U           (0x004005DC)
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U___POR  0x01010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___POR 0x1
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___POR 0x1
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___POR 0x000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___M 0x01000000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___S              24
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___M 0x00010000
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___S              16
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___M 0x000003FF
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___S               0
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U___M    0x010103FF   
#define   PHYA_DEMFRONT_0_CHE_CONTROL_4_U___S                  0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L       (0x004005E0)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___POR 0x000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___POR 0x0000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___M 0x03FF0000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___M 0x00007FFF
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___M 0x03FF7FFF   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U       (0x004005E4)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___POR 0x0000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___M 0x00000001
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___M 0xFFFF0001   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L       (0x004005E8)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U       (0x004005EC)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___M 0x01000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___S              24
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___M 0x00000300
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___S               8
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___M 0x00000001
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___M 0x01010301   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L       (0x004005F0)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___POR 0x00000300
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___POR 0x3
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___M 0x01000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___S              24
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___M 0x00000300
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___S               8
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___M 0x00000001
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___M 0x01010301   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U       (0x004005F4)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___M 0x00000100
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___S               8
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___M 0x00000001
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___M 0x00010101   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L       (0x004005F8)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___POR 0x000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___M 0x01000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___S              24
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___M 0x000003FF
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___M 0x010103FF   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U       (0x004005FC)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___POR 0x000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___M 0x01000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___S              24
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___M 0x000003FF
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___M 0x010103FF   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L       (0x00400600)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___POR 0x00
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___POR 0x0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___M 0x01000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___S              24
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___M 0x00010000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___S              16
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___M 0x00001F00
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___S               8
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___M 0x00000001
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___M 0x01011F01   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___S               0

#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U       (0x00400604)
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___POR 0x00000000
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___S               0
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___S               0

#define PHYA_DEMFRONT_0_USER_SPARE_2_L            (0x00400608)
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_2_L___S                   0

#define PHYA_DEMFRONT_0_USER_SPARE_2_U            (0x0040060C)
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_2_U___S                   0

#define PHYA_DEMFRONT_0_DCN_CONTROL_L             (0x00400610)
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L___POR    0x00000100
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___POR 0x1
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___POR 0x0
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___M 0x00030000
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___S              16
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___M 0x00000100
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___S               8
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___M 0x00000001
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___S               0
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L___M      0x00030101   
#define   PHYA_DEMFRONT_0_DCN_CONTROL_L___S                    0

#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L        (0x00400618)
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___M 0x00000100
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___S               8
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___S               0
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___M 0x00000101   
#define   PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___S               0

#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L         (0x00400620)
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___RWC   QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___M 0x000000FF
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___S               0
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___M  0x000000FF   
#define   PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___S                0

#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L     (0x00400628)
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___POR 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___POR 0xFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___POR 0xFFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___M 0x0FFF0000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___S              16
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___S               0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L     (0x00400630)
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___S               0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U     (0x00400634)
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___S               0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L     (0x00400638)
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___POR 0x0000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___M 0x01000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___S              24
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___M 0x00010000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___S              16
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___S               0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___M 0x0101FFFF   
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U     (0x0040063C)
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___POR 0x00
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___POR 0x0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___M 0xFF000000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___S              24
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___M 0x00FF0000
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___S              16
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___S               8
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___M 0x00000001
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___S               0
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___M 0xFFFFFF01   
#define   PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L        (0x00400640)
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___POR 0x00000080
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___POR 0x000
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___POR 0x00
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___POR 0x80
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___M 0x03FF0000
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___S              16
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___S               8
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___S               0
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___M 0x03FFFFFF   
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___S               0

#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L        (0x00400648)
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___POR 0x00000080
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___POR 0x000
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___POR 0x00
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___POR 0x80
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___M 0x03FF0000
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___S              16
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___S               8
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___M 0x000000FF
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___S               0
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___M 0x03FFFFFF   
#define   PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___S               0

#define PHYA_DEMFRONT_0_NOISE_PWR_0_L             (0x00400660)
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___POR 0x0
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___POR 0x0
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___POR 0x0
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___M 0x00010000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___S              16
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___M 0x00000100
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___S               8
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___M 0x00000001
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___S               0
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L___M      0x00010101   
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_L___S                    0

#define PHYA_DEMFRONT_0_NOISE_PWR_0_U             (0x00400664)
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___POR 0x000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___S              16
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___M 0x000003FF
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___S               0
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U___M      0xFFFF03FF   
#define   PHYA_DEMFRONT_0_NOISE_PWR_0_U___S                    0

#define PHYA_DEMFRONT_0_NOISE_PWR_1_L             (0x00400668)
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___S              16
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___S               0
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_L___S                    0

#define PHYA_DEMFRONT_0_NOISE_PWR_1_U             (0x0040066C)
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U___POR    0x00000000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___POR 0x0
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___POR 0x00
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___POR 0x00
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___POR 0x00
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___M 0x0F000000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___S              24
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___M 0x003F0000
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___S              16
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___M 0x00003F00
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___S               8
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___M 0x000000FF
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___S               0
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U___M      0x0F3F3FFF   
#define   PHYA_DEMFRONT_0_NOISE_PWR_1_U___S                    0

#define PHYA_DEMFRONT_0_USER_SPARE_3_L            (0x00400670)
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_3_L___S                   0

#define PHYA_DEMFRONT_0_USER_SPARE_3_U            (0x00400674)
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U___POR   0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_USER_SPARE_3_U___S                   0

#define PHYA_DEMFRONT_0_SCSR_CHE0_L               (0x00400678)
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE0_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE1_L               (0x00400680)
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE1_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE2_L               (0x00400688)
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE2_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE3_L               (0x00400690)
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE3_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE4_L               (0x00400698)
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE4_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE5_L               (0x004006A0)
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE5_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE6_L               (0x004006A8)
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE6_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_CHE7_L               (0x004006B0)
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L___M        0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_CHE7_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_LLR_0_L              (0x004006B8)
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___S               0
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L___M       0x00000001   
#define   PHYA_DEMFRONT_0_SCSR_LLR_0_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_LLR_1_L              (0x004006C0)
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___S               0
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L___M       0x00000001   
#define   PHYA_DEMFRONT_0_SCSR_LLR_1_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_LLR_2_L              (0x004006C8)
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L___POR     0x00007F01
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___POR 0x7F
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___S               8
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___S               0
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L___M       0x0000FF01   
#define   PHYA_DEMFRONT_0_SCSR_LLR_2_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_DLMU_L               (0x004006D0)
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___S              24
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___M 0x000F0000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___S              16
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___M 0x00000F00
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___S               8
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___M 0x0000003F
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___S               0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L___M        0x070F0F3F   
#define   PHYA_DEMFRONT_0_SCSR_DLMU_L___S                      0

#define PHYA_DEMFRONT_0_SCSR_DLMU_U               (0x004006D4)
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U___POR      0x00000000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___M 0x03000000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___S              24
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___S              16
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___S               8
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___S               0
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U___M        0x03070701   
#define   PHYA_DEMFRONT_0_SCSR_DLMU_U___S                      0

#define PHYA_DEMFRONT_0_CBFG_CFG_0_L              (0x004006D8)
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___M 0x07000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___S              24
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___M 0x00030000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___M 0x00000300
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___M 0x00000001
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L___M       0x07030301   
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_0_U              (0x004006DC)
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___M 0x07000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___S              24
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___M 0x00070000
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___M 0x00000100
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___M 0x00000001
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U___M       0x07070101   
#define   PHYA_DEMFRONT_0_CBFG_CFG_0_U___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_1_L              (0x004006E0)
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L___POR     0x000A0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___POR 0xA
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___M 0x3F000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___S              24
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___M 0x000F0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___M 0x00003F00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___M 0x0000003F
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L___M       0x3F0F3F3F   
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_1_U              (0x004006E4)
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U___POR     0x000C0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___POR 0x0C
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___M 0x00FF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___M 0x0000FF00
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___M 0x000000FF
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U___M       0x00FFFFFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_1_U___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_2_L              (0x004006E8)
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___POR 0x000
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___POR 0x000
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___M 0x03FF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___M 0x000003FF
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L___M       0x03FF03FF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_2_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_3_L              (0x004006F0)
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___M 0x0000FF00
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___M 0x000000FF
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_3_U              (0x004006F4)
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U___POR     0x00000E00
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___POR 0x000
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___POR 0x0E
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___M 0x0FFF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___M 0x00001F00
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___M 0x0000000F
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U___M       0x0FFF1F0F   
#define   PHYA_DEMFRONT_0_CBFG_CFG_3_U___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_4_L              (0x004006F8)
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___POR 0x000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___M 0x1FFF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___M 0x00000FFF
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L___M       0x1FFF0FFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_4_U              (0x004006FC)
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___M 0x1FFF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___M 0x00001FFF
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U___M       0x1FFF1FFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_4_U___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_5_L              (0x00400700)
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___M 0x1FFF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___M 0x00001FFF
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L___M       0x1FFF1FFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG_5_U              (0x00400704)
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U___POR     0x00150000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___POR 0x00
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___POR 0x15
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___POR 0x0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___M 0xFF000000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___S              24
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___M 0x00FF0000
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___M 0x00001FFF
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U___M       0xFFFF1FFF   
#define   PHYA_DEMFRONT_0_CBFG_CFG_5_U___S                     0

#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L      (0x00400708)
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___POR 0x00010000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___POR 0x0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___POR 0x1
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___POR 0x0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___POR 0x0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___M 0x01000000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___S              24
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___M 0x00010000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___S              16
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___M 0x00000F00
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___S               8
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___M 0x00000007
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___S               0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___M 0x01010F07   
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U      (0x0040070C)
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___POR 0xFFFF0000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___POR 0xFFFF
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___S              16
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___M 0x00000100
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___S               8
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___M 0xFFFF0100   
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___S               8

#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L      (0x00400710)
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___POR 0x00050100
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___POR 0x5
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___POR 0x1
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___POR 0x0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___M 0x00070000
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___S              16
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___M 0x00000100
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___S               8
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___M 0x00000001
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___S               0
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___M 0x00070101   
#define   PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SCSR_MRC_0_L              (0x00400718)
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L___POR     0x01070100
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___POR 0x7
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___M 0x01000000
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___S              24
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___S              16
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___M 0x00000300
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___S               8
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___M 0x00000003
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___S               0
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L___M       0x01070303   
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_MRC_0_U              (0x0040071C)
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U___POR     0x02580107
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___POR 0x0258
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___POR 0x7
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___S              16
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___S               8
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___S               0
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U___M       0xFFFF0107   
#define   PHYA_DEMFRONT_0_SCSR_MRC_0_U___S                     0

#define PHYA_DEMFRONT_0_SCSR_MRC_1_L              (0x00400720)
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L___POR     0x00000001
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___S               0
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L___M       0x00000001   
#define   PHYA_DEMFRONT_0_SCSR_MRC_1_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_MRC_2_L              (0x00400728)
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___M 0x00001F00
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___M 0x0000001F
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L___M       0x00001F1F   
#define   PHYA_DEMFRONT_0_SCSR_MRC_2_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_PTC_0_L              (0x00400730)
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___S              24
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___S              16
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___S               8
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___S               0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L___M       0x07070701   
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_PTC_0_U              (0x00400734)
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U___POR     0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___POR 0x1FF
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___M 0x01000000
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___S              24
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___M 0x00010000
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___S              16
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___S               0
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U___M       0x010101FF   
#define   PHYA_DEMFRONT_0_SCSR_PTC_0_U___S                     0

#define PHYA_DEMFRONT_0_SCSR_PTC_1_L              (0x00400738)
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L___POR     0x03000001
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___S              24
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___M 0x00010000
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___S              16
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___S               8
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___S               0
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L___M       0x07010101   
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_PTC_1_U              (0x0040073C)
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U___POR     0x00070302
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___POR 0x007
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___POR 0x03
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___M 0x03FF0000
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___S              16
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___M 0x00001F00
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___S               8
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___S               0
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U___M       0x03FF1F07   
#define   PHYA_DEMFRONT_0_SCSR_PTC_1_U___S                     0

#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L        (0x00400740)
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L        (0x00400748)
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U        (0x0040074C)
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L        (0x00400750)
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L        (0x00400758)
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U        (0x0040075C)
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L        (0x00400760)
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L        (0x00400768)
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U        (0x0040076C)
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L        (0x00400770)
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L        (0x00400778)
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U        (0x0040077C)
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L        (0x00400780)
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L        (0x00400788)
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U        (0x0040078C)
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L        (0x00400790)
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L        (0x00400798)
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U        (0x0040079C)
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L        (0x004007A0)
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L        (0x004007A8)
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U        (0x004007AC)
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L        (0x004007B0)
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L        (0x004007B8)
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___S              24
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___S              16
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___S               8
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U        (0x004007BC)
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___S               0
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_0_PTC_CONTROL_L             (0x004007C0)
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L___POR    0x00044E05
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___POR 0x004
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___POR 0x4E05
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___M 0x03FF0000
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___S              16
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___M 0x00007FFF
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___S               0
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L___M      0x03FF7FFF   
#define   PHYA_DEMFRONT_0_PTC_CONTROL_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_QRE_0_L              (0x004007C8)
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___M 0x0000000F
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___S               0
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L___M       0x0000000F   
#define   PHYA_DEMFRONT_0_SCSR_QRE_0_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_QRE_1_L              (0x004007D0)
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___M 0x0000000F
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___S               0
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L___M       0x0000000F   
#define   PHYA_DEMFRONT_0_SCSR_QRE_1_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_QRE_2_L              (0x004007D8)
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___POR 0x000
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___M 0x000001FF
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___S               0
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L___M       0x000001FF   
#define   PHYA_DEMFRONT_0_SCSR_QRE_2_L___S                     0

#define PHYA_DEMFRONT_0_SCSR_QRE_3_L              (0x004007E0)
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L___RWC        QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L___POR     0x00000000
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___M 0x00003F00
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___M 0x0000003F
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L___M       0x00003F3F   
#define   PHYA_DEMFRONT_0_SCSR_QRE_3_L___S                     0

#define PHYA_DEMFRONT_0_CBFG_CFG1_L               (0x00400830)
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L___POR      0x00000000
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___M 0x00010000
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___S              16
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___M 0x00000100
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___S               8
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___M 0x00000001
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___S               0
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L___M        0x00010101   
#define   PHYA_DEMFRONT_0_CBFG_CFG1_L___S                      0

#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L     (0x00400840)
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___POR 0x0
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___M 0x00000001
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___S               0
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___M 0x00000001   
#define   PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___S               0

#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L      (0x00400848)
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___POR 0x00000001
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___POR 0x1
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___M 0x00000001
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___S               0
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___M 0x00000001   
#define   PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___S               0

#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L             (0x00400850)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___M 0x01000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___M 0x00010000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L___M      0x01010101   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U             (0x00400854)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U___POR    0x00010100
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___M 0x03000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___M 0x00010000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U___M      0x03010100   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_0_U___S                    8

#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L             (0x00400858)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L___POR    0x01010202
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U             (0x0040085C)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U___POR    0x02010101
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_1_U___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L             (0x00400860)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L___POR    0x02020303
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U             (0x00400864)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U___POR    0x03010102
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_2_U___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L             (0x00400868)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L___POR    0x02020202
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U             (0x0040086C)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U___POR    0x02010102
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_3_U___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L             (0x00400870)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L___POR    0x03030303
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_L___S                    0

#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U             (0x00400874)
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U___POR    0x03020203
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___POR 0x2
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___POR 0x3
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___S              24
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___S              16
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___S               8
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___S               0
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U___M      0x07070707   
#define   PHYA_DEMFRONT_0_SCSR_CTRL_4_U___S                    0

#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L      (0x00400DA0)
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___POR 0x0020000C
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___POR 0x020
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___POR 0x0C
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___M 0x03FF0000
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___S              16
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___M 0x0000001F
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___M 0x03FF001F   
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U      (0x00400DA4)
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___POR 0x00070100
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___POR 0x007
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___M 0x03FF0000
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___S              16
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___S               8
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___M 0x03FF0100   
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___S               8

#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L      (0x00400DA8)
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___POR 0x00000106
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___POR 0x1
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___POR 0x06
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___M 0x00030000
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___S              16
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___M 0x00000100
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___S               8
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___M 0x0000007F
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___S               0
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___M 0x0003017F   
#define   PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L      (0x00400DB0)
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___POR 0x0
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___POR 0x00
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___M 0x01000000
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___S              24
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___M 0x00FF0000
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___S              16
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___M 0x0000FF00
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___S               8
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___M 0x000000FF
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___S               0
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___M 0x01FFFFFF   
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___S               0

#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U      (0x00400DB4)
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___RWC QCSR_REG_RO    
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___POR 0x00000000
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___S               0
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___S               0

#define PHYA_DEMFRONT_0_DC_MEM_L_n(n)    (0x00400DB8+0x8*(n))
#define   PHYA_DEMFRONT_0_DC_MEM_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_DC_MEM_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_DC_MEM_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_DC_MEM_L_n___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DC_MEM_L_n___POR       0x00000000
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___POR 0x0000
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___POR 0x0000
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___S              16
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___S               0
#define   PHYA_DEMFRONT_0_DC_MEM_L_n___M         0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_DC_MEM_L_n___S                       0
#define PHYA_DEMFRONT_0_DC_MEM_L_0                (0x00400DB8)
#define   PHYA_DEMFRONT_0_DC_MEM_L_0___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_1___S              16
#define   PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_0___S               0

#define PHYA_DEMFRONT_0_DC_MEM_U_n(n)    (0x00400DBC+0x8*(n))
#define   PHYA_DEMFRONT_0_DC_MEM_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_DC_MEM_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_DC_MEM_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_DC_MEM_U_n___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DC_MEM_U_n___POR       0x00000000
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___POR 0x0000
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___POR 0x0000
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___S              16
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___S               0
#define   PHYA_DEMFRONT_0_DC_MEM_U_n___M         0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_DC_MEM_U_n___S                       0
#define PHYA_DEMFRONT_0_DC_MEM_U_0                (0x00400DBC)
#define   PHYA_DEMFRONT_0_DC_MEM_U_0___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_3___S              16
#define   PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_2___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n(n) (0x004015B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0       (0x004015B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n(n) (0x004015BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0       (0x004015BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n(n) (0x004035B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0     (0x004035B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n(n) (0x004035BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0     (0x004035BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n(n) (0x004055B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0    (0x004055B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n(n) (0x004055BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0    (0x004055BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n(n) (0x004075B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0    (0x004075B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n(n) (0x004075BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0    (0x004075BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n(n) (0x004095B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0       (0x004095B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n(n) (0x004095BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0       (0x004095BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n(n) (0x0040B5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0     (0x0040B5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n(n) (0x0040B5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0     (0x0040B5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n(n) (0x0040D5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0    (0x0040D5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n(n) (0x0040D5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0    (0x0040D5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n(n) (0x0040F5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0    (0x0040F5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n(n) (0x0040F5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0    (0x0040F5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n(n) (0x004115B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0       (0x004115B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n(n) (0x004115BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0       (0x004115BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n(n) (0x004135B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0     (0x004135B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n(n) (0x004135BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0     (0x004135BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n(n) (0x004155B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0    (0x004155B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n(n) (0x004155BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0    (0x004155BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n(n) (0x004175B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0    (0x004175B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n(n) (0x004175BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0    (0x004175BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n(n) (0x004195B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0       (0x004195B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n(n) (0x004195BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0       (0x004195BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n(n) (0x0041B5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0     (0x0041B5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n(n) (0x0041B5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0     (0x0041B5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n(n) (0x0041D5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0    (0x0041D5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n(n) (0x0041D5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0    (0x0041D5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n(n) (0x0041F5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0    (0x0041F5B8)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___S               0

#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n(n) (0x0041F5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___S               0
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___S               0
#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0    (0x0041F5BC)
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n(n) (0x004215B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0       (0x004215B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n(n) (0x004215BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0       (0x004215BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n(n) (0x004235B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0     (0x004235B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n(n) (0x004235BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0     (0x004235BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n(n) (0x004255B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0    (0x004255B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n(n) (0x004255BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0    (0x004255BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n(n) (0x004275B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0       (0x004275B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n(n) (0x004275BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0       (0x004275BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n(n) (0x004295B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0     (0x004295B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n(n) (0x004295BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0     (0x004295BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n(n) (0x0042B5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0    (0x0042B5B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n(n) (0x0042B5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0    (0x0042B5BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n(n) (0x0042D5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0       (0x0042D5B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n(n) (0x0042D5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0       (0x0042D5BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n(n) (0x0042F5B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0     (0x0042F5B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n(n) (0x0042F5BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0     (0x0042F5BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n(n) (0x004315B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0    (0x004315B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n(n) (0x004315BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0    (0x004315BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n(n) (0x004335B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0       (0x004335B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n(n) (0x004335BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0       (0x004335BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n(n) (0x004355B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0     (0x004355B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n(n) (0x004355BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0     (0x004355BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n(n) (0x004375B8+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0    (0x004375B8)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___S               0

#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n(n) (0x004375BC+0x8*(n))
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___S               0
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___S               0
#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0    (0x004375BC)
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___S               0

#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L      (0x004395D0)
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___S               0
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___S               0

#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L      (0x004395D8)
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___S               0
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n(n) (0x004415E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0          (0x004415E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n(n) (0x004415E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0          (0x004415E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n(n) (0x004435E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0          (0x004435E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n(n) (0x004435E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0          (0x004435E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n(n) (0x004455E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0          (0x004455E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n(n) (0x004455E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0          (0x004455E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n(n) (0x004475E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0          (0x004475E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n(n) (0x004475E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0          (0x004475E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n(n) (0x004495E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0          (0x004495E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n(n) (0x004495E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0          (0x004495E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n(n) (0x0044B5E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0          (0x0044B5E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n(n) (0x0044B5E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0          (0x0044B5E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n(n) (0x0044D5E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0          (0x0044D5E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n(n) (0x0044D5E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0          (0x0044D5E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n(n) (0x0044F5E0+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0          (0x0044F5E0)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___S               0

#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n(n) (0x0044F5E4+0x8*(n))
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___POR 0x00000000
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___S               0
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___S                 0
#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0          (0x0044F5E4)
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___S               0

#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L            (0x004615E0)
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___POR   0x00000000
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___POR 0x0
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___M 0x00000001
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___S               0
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___M     0x00000001   
#define   PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___S                   0

#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n(n) (0x004615E8+0x8*(n))
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___POR 0x0000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___S               0
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___S               0
#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0        (0x004615E8)
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___S               0

#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n(n) (0x004615EC+0x8*(n))
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___POR 0x0000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___S               0
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___S               0
#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0        (0x004615EC)
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___S               0

#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n(n) (0x00461868+0x8*(n))
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___POR 0x0000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___S               0
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___S               0
#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0        (0x00461868)
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___S               0

#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n(n) (0x0046186C+0x8*(n))
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___POR 0x0000000
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___S               0
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___S               0
#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0        (0x0046186C)
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___S               0

#define PHYA_PHYRF_ECO_CONTROL_L                  (0x00480000)
#define   PHYA_PHYRF_ECO_CONTROL_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ECO_CONTROL_L___POR         0x00000000
#define   PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF
#define   PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___S               0
#define   PHYA_PHYRF_ECO_CONTROL_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_ECO_CONTROL_L___S                         0

#define PHYA_PHYRF_ECO_CONTROL_U                  (0x00480004)
#define   PHYA_PHYRF_ECO_CONTROL_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ECO_CONTROL_U___POR         0x00000000
#define   PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___POR 0x00000000
#define   PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___M  0xFFFFFFFF
#define   PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___S                0
#define   PHYA_PHYRF_ECO_CONTROL_U___M           0xFFFFFFFF   
#define   PHYA_PHYRF_ECO_CONTROL_U___S                         0

#define PHYA_PHYRF_ECO_STATUS_L                   (0x00480008)
#define   PHYA_PHYRF_ECO_STATUS_L___RWC             QCSR_REG_RO    
#define   PHYA_PHYRF_ECO_STATUS_L___POR          0x00000000
#define   PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___POR 0x00000000
#define   PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___M  0xFFFFFFFF
#define   PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___S                0
#define   PHYA_PHYRF_ECO_STATUS_L___M            0xFFFFFFFF   
#define   PHYA_PHYRF_ECO_STATUS_L___S                          0

#define PHYA_PHYRF_EVENT_STATUS_L                 (0x00480010)
#define   PHYA_PHYRF_EVENT_STATUS_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_EVENT_STATUS_L___POR        0x00040000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___POR 0x1
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___M 0x00800000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___S              23
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___M 0x00400000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___S              22
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___M 0x00200000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___S              21
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___M 0x00100000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___S              20
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___M 0x00080000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___S              19
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___M 0x00040000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___S              18
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___M 0x00020000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___S              17
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___M 0x00010000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___S              16
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___M 0x00008000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___S              15
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___M 0x00004000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___S              14
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___M 0x00002000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___S              13
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___M 0x00001000
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___S              12
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___M 0x00000800
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___S              11
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___M 0x00000400
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___S              10
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___M 0x00000200
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___S               9
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___M 0x00000100
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___S               8
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___M 0x00000080
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___S               7
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___M 0x00000040
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___S               6
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___M 0x00000020
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___S               5
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___M 0x00000010
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___S               4
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___M 0x00000008
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___S               3
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___M 0x00000004
#define   PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___S               2
#define   PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_PHYRF_EVENT_STATUS_L___M          0x00FFFFFF   
#define   PHYA_PHYRF_EVENT_STATUS_L___S                        0

#define PHYA_PHYRF_EVENT_MASK_L                   (0x00480018)
#define   PHYA_PHYRF_EVENT_MASK_L___RWC             QCSR_REG_RW    
#define   PHYA_PHYRF_EVENT_MASK_L___POR          0x00FFFFFF
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___M 0x00800000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___S              23
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___M 0x00400000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___S              22
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___M 0x00200000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___S              21
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___M 0x00100000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___S              20
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___M 0x00080000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___S              19
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___M 0x00040000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___S              18
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___M 0x00020000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___S              17
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___M 0x00010000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___S              16
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___M 0x00008000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___S              15
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___M 0x00004000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___S              14
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___M 0x00002000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___S              13
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___M 0x00001000
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___S              12
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___M 0x00000800
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___S              11
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___M 0x00000400
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___S              10
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___M 0x00000200
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___S               9
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___M 0x00000100
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___S               8
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___M 0x00000080
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___S               7
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___M 0x00000040
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___S               6
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___M 0x00000020
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___S               5
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___M 0x00000010
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___S               4
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___M 0x00000008
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___S               3
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___M 0x00000004
#define   PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___S               2
#define   PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_PHYRF_EVENT_MASK_L___M            0x00FFFFFF   
#define   PHYA_PHYRF_EVENT_MASK_L___S                          0

#define PHYA_PHYRF_ERROR_CODE_L                   (0x00480020)
#define   PHYA_PHYRF_ERROR_CODE_L___RWC             QCSR_REG_RO    
#define   PHYA_PHYRF_ERROR_CODE_L___POR          0x00000000
#define   PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___POR 0x0
#define   PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___M 0x0000000F
#define   PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_PHYRF_ERROR_CODE_L___M            0x0000000F   
#define   PHYA_PHYRF_ERROR_CODE_L___S                          0

#define PHYA_PHYRF_ERROR_STATUS_L                 (0x00480028)
#define   PHYA_PHYRF_ERROR_STATUS_L___RWC           QCSR_REG_RO    
#define   PHYA_PHYRF_ERROR_STATUS_L___POR        0x00000000
#define   PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___POR 0x0
#define   PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___M 0x00002000
#define   PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___S              13
#define   PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___M 0x00001000
#define   PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___S              12
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___M 0x00000800
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___S              11
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___M 0x00000400
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___S              10
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___M 0x00000200
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___S               9
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___M 0x00000100
#define   PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___S               8
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___M 0x00000080
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___S               7
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___M 0x00000040
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___S               6
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___M 0x00000020
#define   PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___S               5
#define   PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___M 0x00000010
#define   PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___S               4
#define   PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___M 0x00000008
#define   PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___S               3
#define   PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___M 0x00000004
#define   PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___S               2
#define   PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___M 0x00000002
#define   PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___S               1
#define   PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___M 0x00000001
#define   PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___S               0
#define   PHYA_PHYRF_ERROR_STATUS_L___M          0x00003FFF   
#define   PHYA_PHYRF_ERROR_STATUS_L___S                        0

#define PHYA_PHYRF_ERROR_MASK_L                   (0x00480030)
#define   PHYA_PHYRF_ERROR_MASK_L___RWC             QCSR_REG_RW    
#define   PHYA_PHYRF_ERROR_MASK_L___POR          0x00003FFF
#define   PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___POR 0x1
#define   PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___M 0x00002000
#define   PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___S              13
#define   PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___M 0x00001000
#define   PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___S              12
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___M 0x00000800
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___S              11
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___M 0x00000400
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___S              10
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___M 0x00000200
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___S               9
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___M 0x00000100
#define   PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___S               8
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___M 0x00000080
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___S               7
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___M 0x00000040
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___S               6
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___M 0x00000020
#define   PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___S               5
#define   PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___M 0x00000010
#define   PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___S               4
#define   PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___M 0x00000008
#define   PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___S               3
#define   PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___M 0x00000004
#define   PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___S               2
#define   PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___M 0x00000002
#define   PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___S               1
#define   PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___M 0x00000001
#define   PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___S               0
#define   PHYA_PHYRF_ERROR_MASK_L___M            0x00003FFF   
#define   PHYA_PHYRF_ERROR_MASK_L___S                          0

#define PHYA_PHYRF_TIMESTAMP_0_L                  (0x00480038)
#define   PHYA_PHYRF_TIMESTAMP_0_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TIMESTAMP_0_L___POR         0x00000000
#define   PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___POR 0x00000000
#define   PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___M 0xFFFFFFFF
#define   PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___S               0
#define   PHYA_PHYRF_TIMESTAMP_0_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TIMESTAMP_0_L___S                         0

#define PHYA_PHYRF_TIMESTAMP_0_U                  (0x0048003C)
#define   PHYA_PHYRF_TIMESTAMP_0_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TIMESTAMP_0_U___POR         0x00010100
#define   PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___POR 0x1
#define   PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___POR 0x1
#define   PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___POR 0x0
#define   PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___M 0x000F0000
#define   PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___S              16
#define   PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___M 0x00000100
#define   PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___S               8
#define   PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___M 0x00000001
#define   PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___S               0
#define   PHYA_PHYRF_TIMESTAMP_0_U___M           0x000F0101   
#define   PHYA_PHYRF_TIMESTAMP_0_U___S                         0

#define PHYA_PHYRF_TIMESTAMP_1_L                  (0x00480040)
#define   PHYA_PHYRF_TIMESTAMP_1_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TIMESTAMP_1_L___POR         0x0000FFFF
#define   PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___POR 0x0000FFFF
#define   PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___M 0xFFFFFFFF
#define   PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___S               0
#define   PHYA_PHYRF_TIMESTAMP_1_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TIMESTAMP_1_L___S                         0

#define PHYA_PHYRF_ASF_CTRL_L                     (0x00480048)
#define   PHYA_PHYRF_ASF_CTRL_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_ASF_CTRL_L___POR            0x00000700
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___POR 0x1
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___POR 0x1
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___POR 0x1
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___POR 0x0
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___POR 0x0
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___M 0x00000400
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___S              10
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___M 0x00000200
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___S               9
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___M 0x00000100
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___S               8
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___M 0x000000F0
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___S               4
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___M 0x0000000F
#define   PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___S               0
#define   PHYA_PHYRF_ASF_CTRL_L___M              0x000007FF   
#define   PHYA_PHYRF_ASF_CTRL_L___S                            0

#define PHYA_PHYRF_ADCFIFO_CTRL_L                 (0x00480050)
#define   PHYA_PHYRF_ADCFIFO_CTRL_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_ADCFIFO_CTRL_L___POR        0x00E40100
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___POR 0xE4
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___POR 0x1
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___POR 0x0
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___M 0x00FF0000
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___S              16
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___M 0x00000100
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___S               8
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___M 0x00000001
#define   PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___S               0
#define   PHYA_PHYRF_ADCFIFO_CTRL_L___M          0x00FF0101   
#define   PHYA_PHYRF_ADCFIFO_CTRL_L___S                        0

#define PHYA_PHYRF_TX_VHT160_MODE_L               (0x00480058)
#define   PHYA_PHYRF_TX_VHT160_MODE_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TX_VHT160_MODE_L___POR      0x00000000
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___POR 0x0
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___POR 0x0
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___POR 0x0
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___M 0x000F0000
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___S              16
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___M 0x00000300
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___S               8
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___M 0x00000003
#define   PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___S               0
#define   PHYA_PHYRF_TX_VHT160_MODE_L___M        0x000F0303   
#define   PHYA_PHYRF_TX_VHT160_MODE_L___S                      0

#define PHYA_PHYRF_ADCSAT_L                       (0x00480060)
#define   PHYA_PHYRF_ADCSAT_L___RWC                 QCSR_REG_RW    
#define   PHYA_PHYRF_ADCSAT_L___POR              0x00320001
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___POR 0x032
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___POR 0x001
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___M 0x07FF0000
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___S              16
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___M 0x000007FF
#define   PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___S               0
#define   PHYA_PHYRF_ADCSAT_L___M                0x07FF07FF   
#define   PHYA_PHYRF_ADCSAT_L___S                              0

#define PHYA_PHYRF_ADCSAT_U                       (0x00480064)
#define   PHYA_PHYRF_ADCSAT_U___RWC                 QCSR_REG_RW    
#define   PHYA_PHYRF_ADCSAT_U___POR              0x07F00002
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___POR  0x7F0
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___POR 0x00
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___POR 0x2
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___M    0x07FF0000
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___S                 16
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___M  0x00007F00
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___S                8
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___M 0x00000003
#define   PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___S               0
#define   PHYA_PHYRF_ADCSAT_U___M                0x07FF7F03   
#define   PHYA_PHYRF_ADCSAT_U___S                              0

#define PHYA_PHYRF_RFCTRL_0_L                     (0x00480068)
#define   PHYA_PHYRF_RFCTRL_0_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_0_L___POR            0x00000000
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___POR 0x0
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___POR 0x0
#define   PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___POR 0x0
#define   PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___POR   0x0
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___M 0x0F000000
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___S              24
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___M 0x000F0000
#define   PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___S              16
#define   PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___M 0x00000100
#define   PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___S               8
#define   PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___M     0x00000001
#define   PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___S                   0
#define   PHYA_PHYRF_RFCTRL_0_L___M              0x0F0F0101   
#define   PHYA_PHYRF_RFCTRL_0_L___S                            0

#define PHYA_PHYRF_RFCTRL_0_U                     (0x0048006C)
#define   PHYA_PHYRF_RFCTRL_0_U___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_0_U___POR            0x00000000
#define   PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___POR 0x0000
#define   PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___POR 0x0
#define   PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___POR 0x00
#define   PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___M 0x3FFF0000
#define   PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___S              16
#define   PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___M 0x00000100
#define   PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___S               8
#define   PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___M 0x000000FF
#define   PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___S               0
#define   PHYA_PHYRF_RFCTRL_0_U___M              0x3FFF01FF   
#define   PHYA_PHYRF_RFCTRL_0_U___S                            0

#define PHYA_PHYRF_RFCTRL_1_L                     (0x00480070)
#define   PHYA_PHYRF_RFCTRL_1_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_1_L___POR            0x00140100
#define   PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___POR 0x0
#define   PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___POR 0x14
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___POR 0x01
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___POR 0x00
#define   PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___M 0x01000000
#define   PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___S              24
#define   PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___M 0x00FF0000
#define   PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___S              16
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___M 0x0000FF00
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___S               8
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___M 0x000000FF
#define   PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___S               0
#define   PHYA_PHYRF_RFCTRL_1_L___M              0x01FFFFFF   
#define   PHYA_PHYRF_RFCTRL_1_L___S                            0

#define PHYA_PHYRF_RFCTRL_1_U                     (0x00480074)
#define   PHYA_PHYRF_RFCTRL_1_U___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_1_U___POR            0xFFFF0000
#define   PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___POR 0xFF
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___POR 0xFF
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___POR  0x0
#define   PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___POR  0x0
#define   PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___M 0xFF000000
#define   PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___S              24
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___M 0x00FF0000
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___S              16
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___M    0x00000700
#define   PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___S                  8
#define   PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___M    0x00000007
#define   PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___S                  0
#define   PHYA_PHYRF_RFCTRL_1_U___M              0xFFFF0707   
#define   PHYA_PHYRF_RFCTRL_1_U___S                            0

#define PHYA_PHYRF_RFCTRL_2_L                     (0x00480078)
#define   PHYA_PHYRF_RFCTRL_2_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_2_L___POR            0x00000A00
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___POR 0x0
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___POR 0xA
#define   PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___POR 0x0
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___M 0x00030000
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___S              16
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___M 0x00000F00
#define   PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___S               8
#define   PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___M 0x00000001
#define   PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___S               0
#define   PHYA_PHYRF_RFCTRL_2_L___M              0x00030F01   
#define   PHYA_PHYRF_RFCTRL_2_L___S                            0

#define PHYA_PHYRF_RFCTRL_2_U                     (0x0048007C)
#define   PHYA_PHYRF_RFCTRL_2_U___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_2_U___POR            0xFFFF1E00
#define   PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___POR 0xFFFF
#define   PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___POR 0x1E00
#define   PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___M 0xFFFF0000
#define   PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___S              16
#define   PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___M 0x0000FFFF
#define   PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___S               0
#define   PHYA_PHYRF_RFCTRL_2_U___M              0xFFFFFFFF   
#define   PHYA_PHYRF_RFCTRL_2_U___S                            0

#define PHYA_PHYRF_RFCTRL_3_L                     (0x00480080)
#define   PHYA_PHYRF_RFCTRL_3_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_3_L___POR            0x00000000
#define   PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___POR 0x00000000
#define   PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___S               0
#define   PHYA_PHYRF_RFCTRL_3_L___M              0xFFFFFFFF   
#define   PHYA_PHYRF_RFCTRL_3_L___S                            0

#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L        (0x00480088)
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___POR 0x0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___M 0x00004000
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___S              14
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___M 0x00002000
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___S              13
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___M 0x00001000
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___S              12
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___M 0x00000800
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___S              11
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___M 0x00000400
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___S              10
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___M 0x00000200
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___S               9
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___M 0x00000100
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___S               8
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___M 0x00000080
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___S               7
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___M 0x00000040
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___S               6
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___M 0x00000020
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___S               5
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___M 0x00000010
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___S               4
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___M 0x00000008
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___S               3
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___M 0x00000004
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___S               2
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___M 0x00000002
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___S               1
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___M 0x00000001
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___S               0
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___M 0x00007FFF   
#define   PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___S               0

#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L            (0x00480090)
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___POR   0x01000100
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___POR 0x1
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___POR 0x1
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___M 0x01000000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___S              24
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___M 0x00010000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___S              16
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___M 0x00000100
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___S               8
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___M 0x00000001
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___S               0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___M     0x01010101   
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___S                   0

#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U            (0x00480094)
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___POR   0x00000000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___M 0x01000000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___S              24
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___M 0x00010000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___S              16
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___M 0x00000300
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___S               8
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___M 0x00000007
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___S               0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___M     0x01010307   
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___S                   0

#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L            (0x00480098)
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___POR   0x00200000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___POR 0x0020
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___POR 0x0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___M 0xFFFF0000
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___S              16
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___M 0x00000001
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___S               0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___M     0xFFFF0001   
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___S                   0

#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U            (0x0048009C)
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___POR   0x00000BB8
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___POR 0xBB8
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___M 0x00000FFF
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___S               0
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___M     0x00000FFF   
#define   PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___S                   0

#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L       (0x004800A0)
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___S               0
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___S               0

#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U       (0x004800A4)
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___S               0
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___S               0

#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L       (0x004800A8)
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___S               0
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___S               0

#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U       (0x004800AC)
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___S               0
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___S               0

#define PHYA_PHYRF_TX_TIMING_1_L                  (0x004800B0)
#define   PHYA_PHYRF_TX_TIMING_1_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TX_TIMING_1_L___POR         0x14080000
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___POR 0x14
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___POR 0x08
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___M 0xFF000000
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___S              24
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___M 0x00FF0000
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___S              16
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___M 0x0000FF00
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___S               8
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___M 0x000000FF
#define   PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___S               0
#define   PHYA_PHYRF_TX_TIMING_1_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TX_TIMING_1_L___S                         0

#define PHYA_PHYRF_TX_TIMING_1_U                  (0x004800B4)
#define   PHYA_PHYRF_TX_TIMING_1_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TX_TIMING_1_U___POR         0x0C402800
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___POR 0x0C
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___POR 0x40
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___POR 0x28
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___M 0xFF000000
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___S              24
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___M 0x00FF0000
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___S              16
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___M 0x0000FF00
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___S               8
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___M 0x000000FF
#define   PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___S               0
#define   PHYA_PHYRF_TX_TIMING_1_U___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TX_TIMING_1_U___S                         0

#define PHYA_PHYRF_TX_TIMING_2_L                  (0x004800B8)
#define   PHYA_PHYRF_TX_TIMING_2_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TX_TIMING_2_L___POR         0x28002820
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___POR 0x28
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___POR 0x28
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___POR 0x20
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___M 0xFF000000
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___S              24
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___M 0x00FF0000
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___S              16
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___M 0x0000FF00
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___S               8
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___M 0x000000FF
#define   PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___S               0
#define   PHYA_PHYRF_TX_TIMING_2_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TX_TIMING_2_L___S                         0

#define PHYA_PHYRF_TX_TIMING_2_U                  (0x004800BC)
#define   PHYA_PHYRF_TX_TIMING_2_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TX_TIMING_2_U___POR         0x00000004
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___POR 0x00
#define   PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___POR 0x04
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___M 0xFF000000
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___S              24
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___M 0x00FF0000
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___S              16
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___M 0x0000FF00
#define   PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___S               8
#define   PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___M 0x000000FF
#define   PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___S               0
#define   PHYA_PHYRF_TX_TIMING_2_U___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TX_TIMING_2_U___S                         0

#define PHYA_PHYRF_TX_TS_CTRL_L                   (0x004800C0)
#define   PHYA_PHYRF_TX_TS_CTRL_L___RWC             QCSR_REG_RW    
#define   PHYA_PHYRF_TX_TS_CTRL_L___POR          0x7FFFFFFF
#define   PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___POR 0x7FFFFFFF
#define   PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___M 0xFFFFFFFF
#define   PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___S               0
#define   PHYA_PHYRF_TX_TS_CTRL_L___M            0xFFFFFFFF   
#define   PHYA_PHYRF_TX_TS_CTRL_L___S                          0

#define PHYA_PHYRF_TXCORR_CTRL_L                  (0x004800C8)
#define   PHYA_PHYRF_TXCORR_CTRL_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TXCORR_CTRL_L___POR         0x00000000
#define   PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___POR  0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___POR 0x0
#define   PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___M 0x00003800
#define   PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___S              11
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___M 0x00000400
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___S              10
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___M 0x00000200
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___S               9
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___M 0x00000100
#define   PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___S               8
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___M 0x00000080
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___S               7
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___M 0x00000040
#define   PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___S               6
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___M   0x00000020
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___S                 5
#define   PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___M 0x00000010
#define   PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___S               4
#define   PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___M    0x0000000E
#define   PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___S                  1
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___M 0x00000001
#define   PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___S               0
#define   PHYA_PHYRF_TXCORR_CTRL_L___M           0x00003FFF   
#define   PHYA_PHYRF_TXCORR_CTRL_L___S                         0

#define PHYA_PHYRF_TXCORR_CTRL_U                  (0x004800CC)
#define   PHYA_PHYRF_TXCORR_CTRL_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TXCORR_CTRL_U___POR         0x00000000
#define   PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___POR 0x00000000
#define   PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___S               0
#define   PHYA_PHYRF_TXCORR_CTRL_U___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TXCORR_CTRL_U___S                         0

#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L             (0x004800D0)
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L___POR    0x00000000
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___POR 0x000
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___M 0x00020000
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___S              17
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___M 0x00010000
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___S              16
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___M 0x0000FFC0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___S               6
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___M 0x00000020
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___S               5
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___M 0x00000018
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___S               3
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___M 0x00000004
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___S               2
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___M 0x00000002
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___S               1
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___M 0x00000001
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___S               0
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L___M      0x0003FFFF   
#define   PHYA_PHYRF_TXCORR_OVRD_CTRL_L___S                    0

#define PHYA_PHYRF_PAPRD_RATE_MASK_L              (0x004800D8)
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L___POR     0x7FFFFFFF
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___POR 0x7FFFFFFF
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___M 0x7FFFFFFF
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___S               0
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L___M       0x7FFFFFFF   
#define   PHYA_PHYRF_PAPRD_RATE_MASK_L___S                     0

#define PHYA_PHYRF_PREEMP_MASK_L                  (0x004800E0)
#define   PHYA_PHYRF_PREEMP_MASK_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_MASK_L___POR         0x00000000
#define   PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___M 0x7FFFFFFF
#define   PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___S               0
#define   PHYA_PHYRF_PREEMP_MASK_L___M           0x7FFFFFFF   
#define   PHYA_PHYRF_PREEMP_MASK_L___S                         0

#define PHYA_PHYRF_PDC_CTRL_L                     (0x004800E8)
#define   PHYA_PHYRF_PDC_CTRL_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_CTRL_L___POR            0x00020001
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___POR 0x2
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___POR 0x1
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___M 0x00030000
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___S              16
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___M 0x00000100
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___S               8
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___M 0x00000001
#define   PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___S               0
#define   PHYA_PHYRF_PDC_CTRL_L___M              0x00030101   
#define   PHYA_PHYRF_PDC_CTRL_L___S                            0

#define PHYA_PHYRF_PDC_CTRL_U                     (0x004800EC)
#define   PHYA_PHYRF_PDC_CTRL_U___RWC               QCSR_REG_RO    
#define   PHYA_PHYRF_PDC_CTRL_U___POR            0x00000000
#define   PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___POR 0x00000000
#define   PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___S               0
#define   PHYA_PHYRF_PDC_CTRL_U___M              0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_CTRL_U___S                            0

#define PHYA_PHYRF_PDC_GAP_THR_L                  (0x004800F0)
#define   PHYA_PHYRF_PDC_GAP_THR_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_GAP_THR_L___POR         0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___POR 0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___S               0
#define   PHYA_PHYRF_PDC_GAP_THR_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_GAP_THR_L___S                         0

#define PHYA_PHYRF_PDC_GAP_THR_U                  (0x004800F4)
#define   PHYA_PHYRF_PDC_GAP_THR_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_GAP_THR_U___POR         0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___POR 0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___S               0
#define   PHYA_PHYRF_PDC_GAP_THR_U___M           0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_GAP_THR_U___S                         0

#define PHYA_PHYRF_PDC_GAP_THR_MAX_L              (0x004800F8)
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L___POR     0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___POR 0x00000000
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___S               0
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_GAP_THR_MAX_L___S                     0

#define PHYA_PHYRF_PDC_COMP_START_L               (0x00480100)
#define   PHYA_PHYRF_PDC_COMP_START_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_COMP_START_L___POR      0x00000000
#define   PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___POR 0x00000000
#define   PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___S               0
#define   PHYA_PHYRF_PDC_COMP_START_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_COMP_START_L___S                      0

#define PHYA_PHYRF_IMP_CTRL_L                     (0x00480108)
#define   PHYA_PHYRF_IMP_CTRL_L___RWC               QCSR_REG_RW    
#define   PHYA_PHYRF_IMP_CTRL_L___POR            0x00000088
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___POR 0x2
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___POR 0x0
#define   PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___POR 0x0
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___POR 0x2
#define   PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___POR 0x0
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___POR 0x0
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___M 0x000000C0
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___S               6
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___M 0x00000020
#define   PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___S               5
#define   PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___M 0x00000010
#define   PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___S               4
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___M 0x0000000C
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___S               2
#define   PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___M 0x00000002
#define   PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___S               1
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___M 0x00000001
#define   PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___S               0
#define   PHYA_PHYRF_IMP_CTRL_L___M              0x000000FF   
#define   PHYA_PHYRF_IMP_CTRL_L___S                            0

#define PHYA_PHYRF_TXTDC_DEBUG_L                  (0x00480110)
#define   PHYA_PHYRF_TXTDC_DEBUG_L___RWC            QCSR_REG_RO    
#define   PHYA_PHYRF_TXTDC_DEBUG_L___POR         0x00000000
#define   PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___POR 0x00000000
#define   PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___S               0
#define   PHYA_PHYRF_TXTDC_DEBUG_L___M           0xFFFFFFFF   
#define   PHYA_PHYRF_TXTDC_DEBUG_L___S                         0

#define PHYA_PHYRF_TXTDC_DEBUG_U                  (0x00480114)
#define   PHYA_PHYRF_TXTDC_DEBUG_U___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TXTDC_DEBUG_U___POR         0x0000000F
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___POR 0x0
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___POR 0x0
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___POR 0x0
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___POR 0x0
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___POR 0xF
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___M 0x00001800
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___S              11
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___M 0x00000600
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___S               9
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___M 0x00000180
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___S               7
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___M 0x00000070
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___S               4
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___M 0x0000000F
#define   PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___S               0
#define   PHYA_PHYRF_TXTDC_DEBUG_U___M           0x00001FFF   
#define   PHYA_PHYRF_TXTDC_DEBUG_U___S                         0

#define PHYA_PHYRF_RXCORR_CTRL_0_L                (0x00480118)
#define   PHYA_PHYRF_RXCORR_CTRL_0_L___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_CTRL_0_L___POR       0x00000000
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___M 0x01000000
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___S              24
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___M 0x00010000
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___S              16
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___M 0x00000100
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___S               8
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___M 0x00000001
#define   PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___S               0
#define   PHYA_PHYRF_RXCORR_CTRL_0_L___M         0x01010101   
#define   PHYA_PHYRF_RXCORR_CTRL_0_L___S                       0

#define PHYA_PHYRF_RXCORR_CTRL_0_U                (0x0048011C)
#define   PHYA_PHYRF_RXCORR_CTRL_0_U___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_CTRL_0_U___POR       0x02020000
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___POR 0x2
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___POR 0x2
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___M 0x03000000
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___S              24
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___M 0x00030000
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___S              16
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___M 0x00000100
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___S               8
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___M 0x00000001
#define   PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___S               0
#define   PHYA_PHYRF_RXCORR_CTRL_0_U___M         0x03030101   
#define   PHYA_PHYRF_RXCORR_CTRL_0_U___S                       0

#define PHYA_PHYRF_RXCORR_CTRL_1_L                (0x00480120)
#define   PHYA_PHYRF_RXCORR_CTRL_1_L___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_CTRL_1_L___POR       0x00000400
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___POR 0x4
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___M 0x01000000
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___S              24
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___M 0x00010000
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___S              16
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___M 0x00000F00
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___S               8
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___M 0x00000001
#define   PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___S               0
#define   PHYA_PHYRF_RXCORR_CTRL_1_L___M         0x01010F01   
#define   PHYA_PHYRF_RXCORR_CTRL_1_L___S                       0

#define PHYA_PHYRF_RXCORR_CTRL_1_U                (0x00480124)
#define   PHYA_PHYRF_RXCORR_CTRL_1_U___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_CTRL_1_U___POR       0x00000000
#define   PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___POR 0x0
#define   PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___M 0x00000001
#define   PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___S               0
#define   PHYA_PHYRF_RXCORR_CTRL_1_U___M         0x00000001   
#define   PHYA_PHYRF_RXCORR_CTRL_1_U___S                       0

#define PHYA_PHYRF_RXXBAR_L                       (0x00480128)
#define   PHYA_PHYRF_RXXBAR_L___RWC                 QCSR_REG_RW    
#define   PHYA_PHYRF_RXXBAR_L___POR              0x00FAC688
#define   PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___POR 0xFAC688
#define   PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___M  0x00FFFFFF
#define   PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___S                0
#define   PHYA_PHYRF_RXXBAR_L___M                0x00FFFFFF   
#define   PHYA_PHYRF_RXXBAR_L___S                              0

#define PHYA_PHYRF_TXXBAR_L                       (0x00480130)
#define   PHYA_PHYRF_TXXBAR_L___RWC                 QCSR_REG_RW    
#define   PHYA_PHYRF_TXXBAR_L___POR              0x01F58D10
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___POR 0xFAC688
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___M 0x01FFFFFE
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___S               1
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___M 0x00000001
#define   PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___S               0
#define   PHYA_PHYRF_TXXBAR_L___M                0x01FFFFFF   
#define   PHYA_PHYRF_TXXBAR_L___S                              0

#define PHYA_PHYRF_TPC_GEN_CTRL_L                 (0x00480138)
#define   PHYA_PHYRF_TPC_GEN_CTRL_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GEN_CTRL_L___POR        0x05439E00
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___POR 0x0A
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___POR 0x10
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___POR 0x1
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___POR 0x1
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___POR 0x1
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___POR 0x0F
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___M 0x7F800000
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___S              23
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___M 0x007C0000
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___S              18
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___M 0x00020000
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___S              17
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___M 0x00010000
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___S              16
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___M 0x00008000
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___S              15
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___M 0x00007E00
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___S               9
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___M 0x00000100
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___S               8
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___M 0x00000080
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___S               7
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___M 0x00000078
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___S               3
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___M 0x00000004
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___S               2
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___M 0x00000002
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___S               1
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___M 0x00000001
#define   PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___S               0
#define   PHYA_PHYRF_TPC_GEN_CTRL_L___M          0x7FFFFFFF   
#define   PHYA_PHYRF_TPC_GEN_CTRL_L___S                        0

#define PHYA_PHYRF_TPC_GEN_CTRL_U                 (0x0048013C)
#define   PHYA_PHYRF_TPC_GEN_CTRL_U___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GEN_CTRL_U___POR        0x0000020A
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___POR 0x00
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___POR 0x1
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___POR 0x0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___POR 0x0A
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___M 0x0FC00000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___S              22
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___M 0x00300000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___S              20
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___M 0x00080000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___S              19
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___M 0x00070000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___S              16
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___M 0x00008000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___S              15
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___M 0x00004000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___S              14
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___M 0x00002000
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___S              13
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___M 0x00001E00
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___S               9
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___M 0x00000100
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___S               8
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___M 0x000000FF
#define   PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___S               0
#define   PHYA_PHYRF_TPC_GEN_CTRL_U___M          0x0FFFFFFF   
#define   PHYA_PHYRF_TPC_GEN_CTRL_U___S                        0

#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L              (0x00480140)
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L___POR     0x00800190
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___POR 0x80
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___POR 0x0064
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___S              16
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___M 0x0000FFFC
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___S               2
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___M 0x00000002
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___S               1
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___M 0x00000001
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___S               0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L___M       0x00FFFFFF   
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_L___S                     0

#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U              (0x00480144)
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U___POR     0x01210000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___POR 0x04
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___POR 0x1
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___POR 0x08
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___POR 0x000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___M 0x0FC00000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___S              22
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___M 0x00200000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___S              21
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___M 0x001FE000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___S              13
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___M 0x00001000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___S              12
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___M 0x00000800
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___S              11
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___M 0x00000400
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___S              10
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___M 0x000003FF
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___S               0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U___M       0x0FFFFFFF   
#define   PHYA_PHYRF_TPC_CLPC_CTRL_0_U___S                     0

#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L              (0x00480148)
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L___POR     0x41044088
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___POR 0x0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___POR 0x20
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___POR 0x20
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___POR 0x1
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___POR 0x04
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___POR 0x02
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___POR 0x08
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___M 0x80000000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___S              31
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___M 0x7E000000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___S              25
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___M 0x01F80000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___S              19
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___M 0x00040000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___S              18
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___M 0x0003F000
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___S              12
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___M 0x00000FC0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___S               6
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___M 0x0000003F
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___S               0
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CLPC_CTRL_1_L___S                     0

#define PHYA_PHYRF_TPC_OLPC_CTRL_L                (0x00480150)
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L___POR       0x00000000
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___POR 0x0000
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___POR 0x0
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___POR 0x00
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___POR 0x00
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___M 0x0FFFF000
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___S              12
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___M 0x00000800
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___S              11
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___M 0x000007E0
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___S               5
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___M 0x0000001F
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___S               0
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L___M         0x0FFFFFFF   
#define   PHYA_PHYRF_TPC_OLPC_CTRL_L___S                       0

#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L        (0x00480158)
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___POR 0x00000C00
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___POR 0x00
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___POR 0x00
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___POR 0x1
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___POR 0x1
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___POR 0x0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___POR 0x0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___POR 0x0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___POR 0x0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___M 0x0FF00000
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___S              20
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___M 0x000FF000
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___S              12
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___M 0x00000800
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___S              11
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___M 0x00000400
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___S              10
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___M 0x00000200
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___S               9
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___M 0x00000100
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___S               8
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___M 0x000000F0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___S               4
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___M 0x0000000F
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___S               0
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___M 0x0FFFFFFF   
#define   PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___S               0

#define PHYA_PHYRF_TPC_FORCE_CTRL_L               (0x00480160)
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___POR 0x00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___POR 0x00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___POR 0x0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___M 0x0F000000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___S              24
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___M 0x00800000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___S              23
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___M 0x00400000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___S              22
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___M 0x00200000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___S              21
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___M 0x00100000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___S              20
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___M 0x00080000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___S              19
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___M 0x00040000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___S              18
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___M 0x00020000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___S              17
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___M 0x0001FE00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___S               9
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___M 0x000001FE
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___S               1
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___M 0x00000001
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___S               0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L___M        0x0FFFFFFF   
#define   PHYA_PHYRF_TPC_FORCE_CTRL_L___S                      0

#define PHYA_PHYRF_TPC_FORCE_CTRL_U               (0x00480164)
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U___POR      0x00000000
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___POR 0x00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___POR 0x00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___M 0x0000FF00
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___S               8
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___M 0x000000FF
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___S               0
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U___M        0x0000FFFF   
#define   PHYA_PHYRF_TPC_FORCE_CTRL_U___S                      0

#define PHYA_PHYRF_TPC_DAC_BO_0_L                 (0x00480168)
#define   PHYA_PHYRF_TPC_DAC_BO_0_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_0_L___POR        0x0000022C
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___POR 0x08
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___POR 0x2C
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___M 0x00000FC0
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___S               6
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_0_L___M          0x00000FFF   
#define   PHYA_PHYRF_TPC_DAC_BO_0_L___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_1_L                 (0x00480170)
#define   PHYA_PHYRF_TPC_DAC_BO_1_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_1_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___M 0x3F000000
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___S              24
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_1_L___M          0x3F3F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_1_L___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_1_U                 (0x00480174)
#define   PHYA_PHYRF_TPC_DAC_BO_1_U___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_1_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_1_U___M          0x003F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_1_U___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_2_L                 (0x00480178)
#define   PHYA_PHYRF_TPC_DAC_BO_2_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_2_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___M 0x3F000000
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___S              24
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_2_L___M          0x3F3F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_2_L___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_2_U                 (0x0048017C)
#define   PHYA_PHYRF_TPC_DAC_BO_2_U___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_2_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_2_U___M          0x003F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_2_U___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_3_L                 (0x00480180)
#define   PHYA_PHYRF_TPC_DAC_BO_3_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_3_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___M 0x3F000000
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___S              24
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_3_L___M          0x3F3F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_3_L___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_3_U                 (0x00480184)
#define   PHYA_PHYRF_TPC_DAC_BO_3_U___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_3_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_3_U___M          0x003F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_3_U___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_4_L                 (0x00480188)
#define   PHYA_PHYRF_TPC_DAC_BO_4_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_4_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___M 0x3F000000
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___S              24
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_4_L___M          0x3F3F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_4_L___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_4_U                 (0x0048018C)
#define   PHYA_PHYRF_TPC_DAC_BO_4_U___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_4_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___M 0x003F0000
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___S              16
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___M 0x00003F00
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___S               8
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_4_U___M          0x003F3F3F   
#define   PHYA_PHYRF_TPC_DAC_BO_4_U___S                        0

#define PHYA_PHYRF_TPC_DAC_BO_5_L                 (0x00480190)
#define   PHYA_PHYRF_TPC_DAC_BO_5_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DAC_BO_5_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___POR 0x00
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___M 0x00000FC0
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___S               6
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___M 0x0000003F
#define   PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___S               0
#define   PHYA_PHYRF_TPC_DAC_BO_5_L___M          0x00000FFF   
#define   PHYA_PHYRF_TPC_DAC_BO_5_L___S                        0

#define PHYA_PHYRF_TPC_GLUT_IDX_0_L               (0x00480198)
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_0_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_1_L               (0x004801A0)
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_1_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_2_L               (0x004801A8)
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_2_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_3_L               (0x004801B0)
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_3_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_4_L               (0x004801B8)
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_4_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_5_L               (0x004801C0)
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_5_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_6_L               (0x004801C8)
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_6_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_7_L               (0x004801D0)
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___M 0x0F000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___S              24
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___M 0x000F0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___S              16
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___M 0x00000F00
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___S               8
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L___M        0x0F0F0F0F   
#define   PHYA_PHYRF_TPC_GLUT_IDX_7_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_IDX_8_L               (0x004801D8)
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___POR 0x0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___M 0x003C0000
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___S              18
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___M 0x0003C000
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___S              14
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___M 0x00003C00
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___S              10
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___M 0x000003C0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___S               6
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___M 0x00000020
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___S               5
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___M 0x00000010
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___S               4
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___M 0x0000000F
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___S               0
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L___M        0x003FFFFF   
#define   PHYA_PHYRF_TPC_GLUT_IDX_8_L___S                      0

#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L            (0x004801E0)
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L___POR   0x00000000
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___POR 0x00
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___POR 0x00
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___POR 0x00
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___POR 0x00
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___M 0x3F000000
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___S              24
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___M 0x00FF0000
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___S              16
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___M 0x0000FF00
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___S               8
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___M 0x000000FF
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___S               0
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L___M     0x3FFFFFFF   
#define   PHYA_PHYRF_TPC_GLUT_SETTINGS_L___S                   0

#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L    (0x004801E8)
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___POR 0x00EC143C
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___POR 0xEC
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___POR 0x14
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___POR 0x3C
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___M 0x00FF0000
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___S              16
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___M 0x0000FF00
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___S               8
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___M 0x000000FF
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___S               0
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___M 0x00FFFFFF   
#define   PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___S               0

#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L        (0x004801F0)
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___POR 0x00000000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___M 0xFF000000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___S              24
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___M 0x00FF0000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___S              16
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___M 0x0000FF00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___S               8
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___M 0x000000FF
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___S               0
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___S               0

#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U        (0x004801F4)
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___POR 0x00000000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___POR 0x00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___M 0xFF000000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___S              24
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___M 0x00FF0000
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___S              16
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___M 0x0000FF00
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___S               8
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___M 0x000000FF
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___S               0
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___S               0

#define PHYA_PHYRF_TPC_STAT_L                     (0x004801F8)
#define   PHYA_PHYRF_TPC_STAT_L___RWC               QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_STAT_L___POR            0x00000000
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___POR 0x0
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___POR 0x0
#define   PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___POR 0x0000
#define   PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___POR 0x00
#define   PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___POR 0x0
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___M 0xF0000000
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___S              28
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___M 0x0F000000
#define   PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___S              24
#define   PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___M 0x00FFF800
#define   PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___S              11
#define   PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___M 0x000007F0
#define   PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___S               4
#define   PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___M 0x0000000F
#define   PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___S               0
#define   PHYA_PHYRF_TPC_STAT_L___M              0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_STAT_L___S                            0

#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L            (0x00480200)
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L___RWC      QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L___POR   0x00000000
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___POR 0x0
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___M 0x00000003
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___S               0
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L___M     0x00000003   
#define   PHYA_PHYRF_TPC_STAT_SELF_CAL_L___S                   0

#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L         (0x00480208)
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___POR 0x00000000
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___POR 0x00
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___M 0x000000FF
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___S               0
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___M  0x000000FF   
#define   PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___S                0

#define PHYA_PHYRF_TPC_MU_L                       (0x00480210)
#define   PHYA_PHYRF_TPC_MU_L___RWC                 QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_MU_L___POR              0x00000000
#define   PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___POR 0x0
#define   PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___M 0x00000001
#define   PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___S               0
#define   PHYA_PHYRF_TPC_MU_L___M                0x00000001   
#define   PHYA_PHYRF_TPC_MU_L___S                              0

#define PHYA_PHYRF_TPC_RST_CTRL_L                 (0x00480218)
#define   PHYA_PHYRF_TPC_RST_CTRL_L___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_RST_CTRL_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___POR 0x0
#define   PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___M 0x00000001
#define   PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___S               0
#define   PHYA_PHYRF_TPC_RST_CTRL_L___M          0x00000001   
#define   PHYA_PHYRF_TPC_RST_CTRL_L___S                        0

#define PHYA_PHYRF_TPC_RECORDER_CTRL_L            (0x00480220)
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L___POR   0x00000000
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___POR 0x00
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___POR 0x00
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___POR 0x0
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___POR 0x0
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___M 0x0003FC00
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___S              10
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___M 0x000003FC
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___S               2
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___M 0x00000002
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___S               1
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___M 0x00000001
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___S               0
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L___M     0x0003FFFF   
#define   PHYA_PHYRF_TPC_RECORDER_CTRL_L___S                   0

#define PHYA_PHYRF_TPC_DBG_BUS0_L                 (0x00480228)
#define   PHYA_PHYRF_TPC_DBG_BUS0_L___RWC           QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_DBG_BUS0_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___S               0
#define   PHYA_PHYRF_TPC_DBG_BUS0_L___M          0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_DBG_BUS0_L___S                        0

#define PHYA_PHYRF_TPC_DBG_BUS0_U                 (0x0048022C)
#define   PHYA_PHYRF_TPC_DBG_BUS0_U___RWC           QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_DBG_BUS0_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___S               0
#define   PHYA_PHYRF_TPC_DBG_BUS0_U___M          0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_DBG_BUS0_U___S                        0

#define PHYA_PHYRF_TPC_DBG_BUS1_L                 (0x00480230)
#define   PHYA_PHYRF_TPC_DBG_BUS1_L___RWC           QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_DBG_BUS1_L___POR        0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___S               0
#define   PHYA_PHYRF_TPC_DBG_BUS1_L___M          0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_DBG_BUS1_L___S                        0

#define PHYA_PHYRF_TPC_DBG_BUS1_U                 (0x00480234)
#define   PHYA_PHYRF_TPC_DBG_BUS1_U___RWC           QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_DBG_BUS1_U___POR        0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___S               0
#define   PHYA_PHYRF_TPC_DBG_BUS1_U___M          0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_DBG_BUS1_U___S                        0

#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L             (0x00480238)
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___POR    0x00000000
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___POR 0x0
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___POR 0x0
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___POR 0x0
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___M 0x00000004
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___S               2
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___M 0x00000002
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___S               1
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___M 0x00000001
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___S               0
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___M      0x00000007   
#define   PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___S                    0

#define PHYA_PHYRF_TPC_DCSR_ERROR_L               (0x00480240)
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L___POR      0x00000000
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___POR 0x0
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___M 0x00000001
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___S               0
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L___M        0x00000001   
#define   PHYA_PHYRF_TPC_DCSR_ERROR_L___S                      0

#define PHYA_PHYRF_TPC_DCSR_BT_L                  (0x00480248)
#define   PHYA_PHYRF_TPC_DCSR_BT_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_DCSR_BT_L___POR         0x00000000
#define   PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___POR 0x0
#define   PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___M 0x00000001
#define   PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___S               0
#define   PHYA_PHYRF_TPC_DCSR_BT_L___M           0x00000001   
#define   PHYA_PHYRF_TPC_DCSR_BT_L___S                         0

#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n(n)  (0x00480250+0x8*(n))
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n_nMIN 0    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n_nMAX 0    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n_ELEM 1    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___S               0
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_n___S                     0
#define PHYA_PHYRF_TPC_ALUT_SRAM_L_0              (0x00480250)
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_0__TPC_ALUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_ALUT_SRAM_L_0__TPC_ALUT_0___S               0

#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n(n)  (0x00480254+0x8*(n))
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n_nMIN 0    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n_nMAX 0    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n_ELEM 1    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___S               0
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_n___S                     0
#define PHYA_PHYRF_TPC_ALUT_SRAM_U_0              (0x00480254)
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_0__TPC_ALUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_ALUT_SRAM_U_0__TPC_ALUT_1___S               0

#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n(n)  (0x00480550+0x8*(n))
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n_nMIN 0    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n_nMAX 0    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n_ELEM 1    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___S               0
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_n___S                     0
#define PHYA_PHYRF_TPC_GLUT_SRAM_L_0              (0x00480550)
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_0__TPC_GLUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_GLUT_SRAM_L_0__TPC_GLUT_0___S               0

#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n(n)  (0x00480554+0x8*(n))
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n_nMIN 0    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n_nMAX 0    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n_ELEM 1    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___S               0
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_n___S                     0
#define PHYA_PHYRF_TPC_GLUT_SRAM_U_0              (0x00480554)
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_0__TPC_GLUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_GLUT_SRAM_U_0__TPC_GLUT_1___S               0

#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n(n)  (0x00480B50+0x8*(n))
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n_nMIN 0    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n_nMAX 0    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n_ELEM 1    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___S               0
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_n___S                     0
#define PHYA_PHYRF_TPC_PLUT_SRAM_L_0              (0x00480B50)
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_0__TPC_PLUT_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_PLUT_SRAM_L_0__TPC_PLUT_0___S               0

#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n(n)  (0x00480B54+0x8*(n))
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n_nMIN 0    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n_nMAX 0    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n_ELEM 1    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n___POR     0x00000000
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___S               0
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n___M       0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_n___S                     0
#define PHYA_PHYRF_TPC_PLUT_SRAM_U_0              (0x00480B54)
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_0__TPC_PLUT_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_PLUT_SRAM_U_0__TPC_PLUT_1___S               0

#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n(n) (0x00481750+0x8*(n))
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_nMIN 0    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_nMAX 0    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_ELEM 1    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___POR   0x00000000
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___POR 0x00000000
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___S               0
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___S                   0
#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0            (0x00481750)
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0__TPC_TXCAL_TABLE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0__TPC_TXCAL_TABLE_0___S               0

#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n(n) (0x00481754+0x8*(n))
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_nMIN 0    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_nMAX 0    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_ELEM 1    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___POR   0x00000000
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___POR 0x00000000
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___S               0
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___S                   0
#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0            (0x00481754)
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0__TPC_TXCAL_TABLE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0__TPC_TXCAL_TABLE_1___S               0

#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L              (0x00481890)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L___POR     0x0000D3C0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___POR 0x1
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___POR 0xA
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___POR 0x3C0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___M 0x0FC00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___S              22
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___M 0x003F0000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___S              16
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___M 0x00008000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___S              15
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___M 0x00007800
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___S              11
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___M 0x000007FF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L___M       0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_L___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U              (0x00481894)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U___POR     0xE6B9A000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___POR 0x39A
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___POR 0x39A
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___M 0xFFC00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___S              22
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___M 0x003FF000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___S              12
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___M 0x00000FC0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___S               6
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___M 0x0000003F
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_0_U___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L              (0x00481898)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L___POR     0x01E07B9A
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___POR 0x01E
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___POR 0x01E
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___POR 0x39A
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___M 0x3FF00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___S              20
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___M 0x000FFC00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___S              10
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___M 0x000003FF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L___M       0x3FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_L___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U              (0x0048189C)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U___POR     0x00068DB9
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___POR 0x00068DB9
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___M 0x3FFFFFFF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U___M       0x3FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_1_U___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L              (0x004818A0)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L___POR     0x00800096
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___POR 0x008
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___POR 0x00096
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___M 0xFFF00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___S              20
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___M 0x000FFFFF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_L___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U              (0x004818A4)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U___POR     0x03E8001E
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___POR 0x3E8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___POR 0x001E
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___M 0x0FFF0000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___S              16
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___M 0x0000FFFF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U___M       0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_2_U___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L              (0x004818A8)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L___POR     0x983E83E8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___POR 0x4
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___POR 0x1
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___POR 0x4
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___POR 0x3E8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___POR 0x3E8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___M 0xE0000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___S              29
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___M 0x10000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___S              28
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___M 0x0E000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___S              25
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___M 0x01000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___S              24
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___M 0x00C00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___S              22
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___M 0x003FF000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___S              12
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___M 0x00000FFF
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_L___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U              (0x004818AC)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U___POR     0x02144440
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___POR 0x8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___POR 0x0A
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___POR 0x04
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___POR 0x1
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___POR 0x1
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___M 0xF8000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___S              27
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___M 0x04000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___S              26
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___M 0x03C00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___S              22
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___M 0x003E0000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___S              17
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___M 0x0001F000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___S              12
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___M 0x00000C00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___S              10
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___M 0x00000300
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___S               8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___M 0x00000080
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___S               7
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___M 0x00000040
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___S               6
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___M 0x00000030
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___S               4
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___M 0x0000000C
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___S               2
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___M 0x00000002
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___S               1
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___M 0x00000001
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_3_U___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L              (0x004818B0)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L___POR     0x09608000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___POR 0x096
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___POR 0x10
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___POR 0x00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___M 0x3FF00000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___S              20
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___M 0x00080000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___S              19
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___M 0x0007F800
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___S              11
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___M 0x000007F8
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___S               3
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___M 0x00000007
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L___M       0x3FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_L___S                     0

#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U              (0x004818B4)
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U___POR     0x00000FD5
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___POR 0x0000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___POR 0x7
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___POR 0x7
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___POR 0x15
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___M 0x40000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___S              30
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___M 0x20000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___S              29
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___M 0x10000000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___S              28
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___M 0x0FFFF000
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___S              12
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___M 0x00000E00
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___S               9
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___M 0x000001C0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___S               6
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___M 0x0000003F
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___S               0
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U___M       0x7FFFFFFF   
#define   PHYA_PHYRF_CAL_MEAS_CTRL_4_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L               (0x004818B8)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U               (0x004818BC)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_0_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L               (0x004818C0)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U               (0x004818C4)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_1_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L               (0x004818C8)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U               (0x004818CC)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_2_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L               (0x004818D0)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U               (0x004818D4)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_3_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L               (0x004818D8)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U               (0x004818DC)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_4_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L               (0x004818E0)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U               (0x004818E4)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_5_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L               (0x004818E8)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U               (0x004818EC)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_6_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L               (0x004818F0)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U               (0x004818F4)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_7_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L               (0x004818F8)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U               (0x004818FC)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_8_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L               (0x00481900)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_L___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U               (0x00481904)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U___POR      0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_9_U___S                      0

#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L              (0x00481908)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U              (0x0048190C)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_10_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L              (0x00481910)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U              (0x00481914)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_11_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L              (0x00481918)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U              (0x0048191C)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_12_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L              (0x00481920)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U              (0x00481924)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_13_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L              (0x00481928)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U              (0x0048192C)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_14_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L              (0x00481930)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U              (0x00481934)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_15_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L              (0x00481938)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L___POR     0x80408000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___POR 0x1
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___POR 0x00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___POR 0x40
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___POR 0x00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___M 0x80000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___S              31
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___M 0x7F800000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___S              23
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___M 0x007F0000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___S              16
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___M 0x0000F800
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___S              11
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___M 0x00000780
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___S               7
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___M 0x00000040
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___S               6
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___M 0x0000003F
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U              (0x0048193C)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U___POR     0x00000006
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___POR 0x00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___POR 0x00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___POR 0x00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___POR 0x06
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___M 0x80000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___S              31
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___M 0x40000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___S              30
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___M 0x3FC00000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___S              22
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___M 0x003FC000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___S              14
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___M 0x00003FC0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___S               6
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___M 0x0000003F
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_16_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L              (0x00481940)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L___POR     0x00009200
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___POR 0x000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___POR 0x012
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___POR 0x1
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___POR 0x000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___M 0xFFE00000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___S              21
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___M 0x00100000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___S              20
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___M 0x000FF800
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___S              11
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___M 0x00000400
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___S              10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___M 0x00000200
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___S               9
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___M 0x000001FF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U              (0x00481944)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U___POR     0x10101020
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___POR 0x20
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___M 0xFF000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___S              24
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___M 0x00FF0000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___S              16
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___M 0x0000FF00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___S               8
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___M 0x000000FF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_17_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L              (0x00481948)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L___POR     0x10101010
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___M 0xFF000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___S              24
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___M 0x00FF0000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___S              16
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___M 0x0000FF00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___S               8
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___M 0x000000FF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U              (0x0048194C)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___POR 0x000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___POR 0x000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___POR 0x000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___M 0x3FF00000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___S              20
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___M 0x000FFC00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___S              10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___M 0x000003FF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U___M       0x3FFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_18_U___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L              (0x00481950)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L___POR     0x661043C0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___POR 0x3
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___POR 0x3
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___POR 0x1
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___POR 0x0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___POR 0x10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___POR 0x3C0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___M 0x60000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___S              29
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___M 0x10000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___S              28
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___M 0x0E000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___S              25
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___M 0x01000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___S              24
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___M 0x00800000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___S              23
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___M 0x00600000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___S              21
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___M 0x00100000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___S              20
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___M 0x00080000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___S              19
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___M 0x00040000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___S              18
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___M 0x0003FC00
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___S              10
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___M 0x000003FF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L___M       0x7FFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_L___S                     0

#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U              (0x00481954)
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U___POR     0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___POR 0x00000000
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___S               0
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_SEQ_CTRL_19_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L              (0x00481958)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L___POR     0x043177DC
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___POR 0x21
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___POR 0x22
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___POR 0x3B
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___POR 0x3B
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___POR 0x4
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___M 0x07E00000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___S              21
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___M 0x001F8000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___S              15
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___M 0x00007E00
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___S               9
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___M 0x000001F8
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___S               3
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___M 0x00000007
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L___M       0x07FFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_L___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U              (0x0048195C)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U___POR     0x0DBEF2A1
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___POR 0x36
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___POR 0x3E
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___POR 0xF
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___POR 0x0A
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___POR 0x21
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___M 0x0FC00000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___S              22
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___M 0x003F0000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___S              16
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___M 0x0000F000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___S              12
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___M 0x00000FC0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___S               6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___M 0x0000003F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U___M       0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_0_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L              (0x00481960)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L___POR     0x0330201A
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___POR 0x06
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___POR 0x1
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___POR 0x4
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___POR 0x4
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___POR 0x1A
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___M 0x1F800000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___S              23
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___M 0x00600000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___S              21
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___M 0x001C0000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___S              18
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___M 0x00030000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___S              16
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___M 0x00008000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___S              15
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___M 0x00007800
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___S              11
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___M 0x00000600
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___S               9
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___M 0x000001E0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___S               5
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___M 0x0000001F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L___M       0x1FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_L___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U              (0x00481964)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U___POR     0x0080BF90
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___POR 0x101
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___POR 0x0FE
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___POR 0x10
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___M 0x00FF8000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___S              15
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___M 0x00007FC0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___S               6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___M 0x0000003F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U___M       0x00FFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_1_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L              (0x00481968)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L___POR     0x1F88A01E
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___POR 0x0F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___POR 0x31
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___POR 0x0A
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___POR 0x01E
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___M 0xFE000000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___S              25
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___M 0x01F80000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___S              19
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___M 0x0007F000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___S              12
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___M 0x00000800
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___S              11
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___M 0x00000400
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___S              10
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___M 0x000003FF
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_L___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U              (0x0048196C)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U___POR     0x1AF1F7F7
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___POR 0x6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___POR 0x2
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___POR 0xF1
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___POR 0xF7
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___POR 0xF7
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___M 0x3C000000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___S              26
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___M 0x03000000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___S              24
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___M 0x00FF0000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___S              16
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___M 0x0000FF00
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___S               8
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___M 0x000000FF
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U___M       0x3FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_2_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L              (0x00481970)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L___POR     0x20334D34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___POR 0x10
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___POR 0x06
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___M 0x7E000000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___S              25
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___M 0x01F80000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___S              19
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___M 0x00040000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___S              18
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___M 0x0003F000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___S              12
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___M 0x00000FC0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___S               6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___M 0x0000003F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L___M       0x7FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_L___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U              (0x00481974)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U___POR     0x009E02FE
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___POR 0x027
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___POR 0x101
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___POR 0x0FE
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___M 0x0FFC0000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___S              18
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___M 0x0003FE00
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___S               9
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___M 0x000001FF
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U___M       0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_3_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L              (0x00481978)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L___POR     0x1EFEE531
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___POR 0xF7
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___POR 0xF7
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___POR 0x14
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___POR 0x31
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___M 0x1FE00000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___S              21
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___M 0x001FE000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___S              13
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___M 0x00001FC0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___S               6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___M 0x0000003F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L___M       0x1FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_L___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U              (0x0048197C)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U___POR     0x1A68D0F1
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___POR 0x6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___POR 0x2
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___POR 0x0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___POR 0xF1
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___M 0x1F800000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___S              23
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___M 0x007E0000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___S              17
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___M 0x0001E000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___S              13
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___M 0x00001800
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___S              11
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___M 0x00000700
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___S               8
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___M 0x000000FF
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U___M       0x1FFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_4_U___S                     0

#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L              (0x00481980)
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L___POR     0x00000034
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___POR 0x0000000
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___POR 0x34
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___M 0xFFFFFFC0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___S               6
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___M 0x0000003F
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___S               0
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_GAIN_CTRL_5_L___S                     0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L  (0x00481988)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___S               0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U  (0x0048198C)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___S               0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L  (0x00481990)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___S               0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U  (0x00481994)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___S               0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L  (0x00481998)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___S               0

#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U  (0x0048199C)
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___POR 0x00000000
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___M 0xFFFFFFFF
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___S               0
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L     (0x004819A0)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U     (0x004819A4)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L     (0x004819A8)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U     (0x004819AC)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L     (0x004819B0)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U     (0x004819B4)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L     (0x004819B8)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U     (0x004819BC)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L     (0x004819C0)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U     (0x004819C4)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L     (0x004819C8)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U     (0x004819CC)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L     (0x004819D0)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U     (0x004819D4)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L     (0x004819D8)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___S               0

#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U     (0x004819DC)
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___S               0

#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L (0x004819E0)
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___POR 0x0
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___M 0x00000001
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___S               0
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___M 0x00000001   
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___S               0

#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U (0x004819E4)
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___S               0
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___S               0

#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L (0x004819E8)
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___POR 0x000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___POR 0x000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___M 0x03FF0000
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___S              16
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___M 0x000003FF
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___S               0
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___M 0x03FF03FF   
#define   PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___S               0

#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L         (0x004819F0)
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___S               0
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___S                0

#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U         (0x004819F4)
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___S               0
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___S                0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L     (0x004819F8)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U     (0x004819FC)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L     (0x00481A00)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U     (0x00481A04)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L     (0x00481A08)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U     (0x00481A0C)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L     (0x00481A10)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U     (0x00481A14)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L     (0x00481A18)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U     (0x00481A1C)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L     (0x00481A20)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U     (0x00481A24)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L     (0x00481A28)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U     (0x00481A2C)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L     (0x00481A30)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___S               0

#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U     (0x00481A34)
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___S               0
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___S               0

#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L (0x00481A38)
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___POR 0x0
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___M 0x00000001
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___S               0
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___M 0x00000001   
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___S               0

#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U (0x00481A3C)
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___S               0
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___S               0

#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L (0x00481A40)
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___POR 0x000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___POR 0x000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___M 0x03FF0000
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___S              16
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___M 0x000003FF
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___S               0
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___M 0x03FF03FF   
#define   PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___S               0

#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L         (0x00481A48)
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___S               0
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___S                0

#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U         (0x00481A4C)
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___POR 0x00000000
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___S               0
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___S                0

#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L            (0x00481A50)
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___POR   0x00000008
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___POR 0x000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___POR 0x00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___POR 0x008
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___M 0x1FF80000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___S              19
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___M 0x00040000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___S              18
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___M 0x0003FC00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___S              10
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___M 0x000003FF
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___S               0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___M     0x1FFFFFFF   
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___S                   0

#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U            (0x00481A54)
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___POR   0x00000000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___POR 0x00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___POR 0x000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___POR 0x00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___M 0x08000000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___S              27
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___M 0x07F80000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___S              19
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___M 0x0007FE00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___S               9
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___M 0x00000100
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___S               8
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___M 0x000000FF
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___S               0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___M     0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___S                   0

#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L            (0x00481A58)
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___POR   0x00800000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___POR 0x002
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___POR 0x0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___POR 0x00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___POR 0x000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___M 0xFFC00000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___S              22
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___M 0x00200000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___S              21
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___M 0x00180000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___S              19
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___M 0x00040000
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___S              18
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___M 0x0003FC00
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___S              10
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___M 0x000003FF
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___S               0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___M     0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___S                   0

#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U            (0x00481A5C)
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___POR   0x00000002
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___POR 0x002
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___M 0x000003FF
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___S               0
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___M     0x000003FF   
#define   PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___S                   0

#define PHYA_PHYRF_CAL_RADIO_CTRL_L               (0x00481A60)
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L___POR      0x01C3C00F
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___POR 0x7
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___POR 0xF
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___POR 0xF
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___M 0xC0000000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___S              30
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___M 0x30000000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___S              28
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___M 0x0C000000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___S              26
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___M 0x03C00000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___S              22
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___M 0x00200000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___S              21
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___M 0x00100000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___S              20
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___M 0x000C0000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___S              18
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___M 0x0003C000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___S              14
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___M 0x00003000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___S              12
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___M 0x00000C00
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___S              10
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___M 0x00000300
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___S               8
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___M 0x000000F0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___S               4
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___M 0x0000000F
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___S               0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L___M        0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_RADIO_CTRL_L___S                      0

#define PHYA_PHYRF_CAL_RADIO_CTRL_U               (0x00481A64)
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U___POR      0x00000A00
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___POR 0x1
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___POR 0x100
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___POR 0x0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___M 0x00001000
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___S              12
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___M 0x00000800
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___S              11
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___M 0x000007FE
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___S               1
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___M 0x00000001
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___S               0
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U___M        0x00001FFF   
#define   PHYA_PHYRF_CAL_RADIO_CTRL_U___S                      0

#define PHYA_PHYRF_CAL_CHAIN_SELECT_L             (0x00481A68)
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L___POR    0x0093B13F
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___POR 0x93
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___POR 0xB1
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___POR 0x0
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___POR 0x1
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___POR 0x1
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___POR 0xF
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___M 0x00FF0000
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___S              16
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___M 0x0000FF00
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___S               8
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___M 0x000000C0
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___S               6
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___M 0x00000020
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___S               5
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___M 0x00000010
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___S               4
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___M 0x0000000F
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___S               0
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L___M      0x00FFFFFF   
#define   PHYA_PHYRF_CAL_CHAIN_SELECT_L___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_0_L             (0x00481A70)
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___POR 0x00
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___POR 0x00
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___POR 0x0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___M 0x07800000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___S              23
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___M 0x00780000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___S              19
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___M 0x00040000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___S              18
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___M 0x0003FC00
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___S              10
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___M 0x000003F8
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___S               3
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___M 0x00000004
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___S               2
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___M 0x00000002
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___S               1
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___M 0x00000001
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L___M      0x07FFFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_L___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_0_U             (0x00481A74)
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___POR 0x00
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___POR 0x00000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___M 0x01F00000
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___S              20
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___M 0x000FFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U___M      0x01FFFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_0_U___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_1_L             (0x00481A78)
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___POR 0x000
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___POR 0x000
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___M 0x00FFF000
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___S              12
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___M 0x00000FFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L___M      0x00FFFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_L___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_1_U             (0x00481A7C)
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U___POR    0x0007FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___POR 0x07FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___M 0x007FFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U___M      0x007FFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_1_U___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_2_L             (0x00481A80)
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L___POR    0x0007FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___POR 0x07FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___M 0x007FFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L___M      0x007FFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_L___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_2_U             (0x00481A84)
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U___POR    0x0007FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___POR 0x07FFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___M 0x007FFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U___M      0x007FFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_2_U___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_3_L             (0x00481A88)
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___POR 0x000
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___M 0x00000FFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L___M      0x00000FFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_L___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_3_U             (0x00481A8C)
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___POR 0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_3_U___S                    0

#define PHYA_PHYRF_CAL_STATUS_DBG_4_L             (0x00481A90)
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L___POR    0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___POR 0x00000000
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___S               0
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_STATUS_DBG_4_L___S                    0

#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L            (0x00481A98)
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___POR   0x0000A198
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___POR 0x000
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___POR 0x14
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___POR 0x3
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___POR 0x3
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___POR 0x0
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___POR 0x0
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___M 0x0FFE0000
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___S              17
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___M 0x0001F800
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___S              11
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___M 0x00000780
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___S               7
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___M 0x00000078
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___S               3
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___M 0x00000006
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___S               1
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___M 0x00000001
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___S               0
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___M     0x0FFFFFFF   
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___S                   0

#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U            (0x00481A9C)
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___POR   0x00000000
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___POR 0x000
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___POR 0x000
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___M 0x003FF800
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___S              11
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___M 0x000007FF
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___S               0
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___M     0x003FFFFF   
#define   PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___S                   0

#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L             (0x00481AA0)
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___POR    0x00000000
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___POR 0x00000000
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___S               0
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___S                    0

#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n(n) (0x00481AA8+0x8*(n))
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMIN 0    
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMAX 0    
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_ELEM 1    
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___POR   0x00000000
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___M 0x00003FFF
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___S               0
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___M     0x00003FFF   
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___S                   0
#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0            (0x00481AA8)
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___M 0x00003FFF
#define   PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___S               0

#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n(n) (0x00481AB0+0x8*(n))
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMIN 0    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMAX 0    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_ELEM 1    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___POR   0x00000000
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___POR 0x00000000
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___S               0
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___S                   0
#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0            (0x00481AB0)
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___S               0

#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n(n) (0x00481AB4+0x8*(n))
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMIN 0    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMAX 0    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_ELEM 1    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___POR   0x00000000
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___POR 0x00000000
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___S               0
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___S                   0
#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0            (0x00481AB4)
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___S               0

#define PHYA_PHYRF_PHYDBG_MODE_L                  (0x00481AD0)
#define   PHYA_PHYRF_PHYDBG_MODE_L___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_MODE_L___POR         0x00000000
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___POR 0x0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___M 0x0003C000
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___S              14
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___M 0x00002000
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___S              13
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___M 0x00001000
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___S              12
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___M 0x00000800
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___S              11
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___M 0x00000600
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___S               9
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___M 0x00000100
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___S               8
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___M 0x000000F0
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___S               4
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___M 0x0000000F
#define   PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___S               0
#define   PHYA_PHYRF_PHYDBG_MODE_L___M           0x0003FFFF   
#define   PHYA_PHYRF_PHYDBG_MODE_L___S                         0

#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L             (0x00481AD8)
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L___POR    0x00000000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___POR 0x00000000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___S               0
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_L___S                    0

#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U             (0x00481ADC)
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U___POR    0x00000000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___POR 0x00000000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___S               0
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U___M      0xFFFFFFFF   
#define   PHYA_PHYRF_PHYDBG_TRIGGER_0_U___S                    0

#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L             (0x00481AE0)
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L___POR    0x00000000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___POR 0x00
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___POR 0x00
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___POR 0x00
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___M 0x00FF0000
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___S              16
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___M 0x0000FF00
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___S               8
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___M 0x000000FF
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___S               0
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L___M      0x00FFFFFF   
#define   PHYA_PHYRF_PHYDBG_TRIGGER_1_L___S                    0

#define PHYA_PHYRF_PHYDBG_PLAYBACK_L              (0x00481AE8)
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L___POR     0x00000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___M 0xFFFF0000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___S              16
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___M 0x0000FFFF
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___S               0
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_L___S                     0

#define PHYA_PHYRF_PHYDBG_PLAYBACK_U              (0x00481AEC)
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U___POR     0x10000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___POR 0x0
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___POR 0x0
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___POR 0x8
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___POR 0x0
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___POR 0x00
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___M 0x40000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___S              30
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___M 0x20000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___S              29
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___M 0x1E000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___S              25
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___M 0x01000000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___S              24
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___M 0x00FF0000
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___S              16
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___M 0x0000FFFF
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___S               0
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U___M       0x7FFFFFFF   
#define   PHYA_PHYRF_PHYDBG_PLAYBACK_U___S                     0

#define PHYA_PHYRF_PHYDBG_CAPTURE_L               (0x00481AF0)
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L___POR      0x00000000
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___M 0x07FFF800
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___S              11
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___M 0x00000400
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___S              10
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___M 0x00000200
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___S               9
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___M 0x00000180
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___S               7
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___M 0x00000070
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___S               4
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___M 0x0000000F
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___S               0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L___M        0x07FFFFFF   
#define   PHYA_PHYRF_PHYDBG_CAPTURE_L___S                      0

#define PHYA_PHYRF_PHYDBG_CAPTURE_U               (0x00481AF4)
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U___POR      0x00000000
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___POR 0x0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___POR 0x0000
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___M 0x00004000
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___S              14
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___M 0x00003FFF
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___S               0
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U___M        0x00007FFF   
#define   PHYA_PHYRF_PHYDBG_CAPTURE_U___S                      0

#define PHYA_PHYRF_PHYRF_WDOG_L                   (0x00481AF8)
#define   PHYA_PHYRF_PHYRF_WDOG_L___RWC             QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_WDOG_L___POR          0x00000000
#define   PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___S               0
#define   PHYA_PHYRF_PHYRF_WDOG_L___M            0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_WDOG_L___S                          0

#define PHYA_PHYRF_PHYRF_WDOG_U                   (0x00481AFC)
#define   PHYA_PHYRF_PHYRF_WDOG_U___RWC             QCSR_REG_RO    
#define   PHYA_PHYRF_PHYRF_WDOG_U___POR          0x00000000
#define   PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___S               0
#define   PHYA_PHYRF_PHYRF_WDOG_U___M            0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_WDOG_U___S                          0

#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L            (0x00481B00)
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___POR   0x30C08030
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___POR 0x18
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___POR 0x18
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___POR 0x04
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___POR 0x1
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___POR 0x1
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___M 0x7E000000
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___S              25
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___M 0x01F80000
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___S              19
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___M 0x0007E000
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___S              13
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___M 0x00001C00
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___S              10
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___M 0x00000200
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___S               9
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___M 0x00000100
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___S               8
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___M 0x00000080
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___S               7
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___M 0x00000040
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___S               6
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___M 0x00000020
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___S               5
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___M 0x00000010
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___S               4
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___M 0x00000008
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___S               3
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___M 0x00000004
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___S               2
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___M 0x00000002
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___S               1
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___M 0x00000001
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___M     0x7FFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___S                   0

#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U            (0x00481B04)
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___POR   0x4FDFC298
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___POR 0x13F
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___POR 0x7F
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___POR 0x0A
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___POR 0x18
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___M 0x7FC00000
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___S              22
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___M 0x003FC000
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___S              14
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___M 0x00003FC0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___S               6
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___M 0x0000003F
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___M     0x7FFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___S                   0

#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L           (0x00481B08)
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___POR  0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___POR 0x0
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___M 0x00000001
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___M    0x00000001   
#define   PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___S                  0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L          (0x00481B10)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L         (0x00481B18)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U         (0x00481B1C)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L         (0x00481B20)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U         (0x00481B24)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L         (0x00481B28)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U         (0x00481B2C)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L         (0x00481B30)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U         (0x00481B34)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___RWC   QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___M  0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___S                0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L          (0x00481B38)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U          (0x00481B3C)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L          (0x00481B40)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U          (0x00481B44)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L          (0x00481B48)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U          (0x00481B4C)
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___M   0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___S                 0

#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L             (0x00481B50)
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L___POR    0x00000801
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___POR 0x00000801
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_L___S                    0

#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U             (0x00481B54)
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U___POR    0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___POR 0x00000000
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___S               0
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U___M      0xFFFFFFFF   
#define   PHYA_PHYRF_SYNTH_SWITCH_DBG_U___S                    0

#define PHYA_PHYRF_OCL_CONFIG_L                   (0x00481B58)
#define   PHYA_PHYRF_OCL_CONFIG_L___RWC             QCSR_REG_RW    
#define   PHYA_PHYRF_OCL_CONFIG_L___POR          0x0000000A
#define   PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___POR 0x0A
#define   PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___M 0x0000003F
#define   PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___S               0
#define   PHYA_PHYRF_OCL_CONFIG_L___M            0x0000003F   
#define   PHYA_PHYRF_OCL_CONFIG_L___S                          0

#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L           (0x00481B60)
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___S                  0

#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U           (0x00481B64)
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___S                  0

#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L (0x00481B68)
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___S               0
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___S               0

#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L          (0x00481B70)
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___S                 0

#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U          (0x00481B74)
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___S                 0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L           (0x00481B78)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___S                  0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U           (0x00481B7C)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___S                  0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L           (0x00481B80)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___S                  0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U           (0x00481B84)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___S                  0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L           (0x00481B88)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___POR  0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___S                  0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L       (0x00481B90)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___S               0

#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U       (0x00481B94)
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L       (0x00481B98)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U       (0x00481B9C)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L       (0x00481BA0)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U       (0x00481BA4)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L       (0x00481BA8)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U       (0x00481BAC)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L       (0x00481BB0)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U       (0x00481BB4)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___S               0

#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L       (0x00481BB8)
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___S               0
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___S               0

#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L      (0x00481BC0)
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___S               0
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___S               0

#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n(n) (0x00481C00+0x8*(n))
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n_nMIN 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n_nMAX 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n_ELEM 1    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n___POR    0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___POR 0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___S               0
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_n___S                    0
#define PHYA_PHYRF_CAL_INFO_MEM_0_L_0             (0x00481C00)
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_0__CAL_INFO_MEM_0_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_0_L_0__CAL_INFO_MEM_0_0___S               0

#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n(n) (0x00481C04+0x8*(n))
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n_nMIN 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n_nMAX 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n_ELEM 1    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n___POR    0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___POR 0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___S               0
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_n___S                    0
#define PHYA_PHYRF_CAL_INFO_MEM_0_U_0             (0x00481C04)
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_0__CAL_INFO_MEM_0_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_0_U_0__CAL_INFO_MEM_0_1___S               0

#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n(n) (0x00485C00+0x8*(n))
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n_nMIN 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n_nMAX 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n_ELEM 1    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n___POR    0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___POR 0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___S               0
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_n___S                    0
#define PHYA_PHYRF_CAL_INFO_MEM_1_L_0             (0x00485C00)
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_0__CAL_INFO_MEM_1_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_1_L_0__CAL_INFO_MEM_1_0___S               0

#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n(n) (0x00485C04+0x8*(n))
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n_nMIN 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n_nMAX 0    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n_ELEM 1    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n___POR    0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___POR 0x00000000
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___S               0
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n___M      0xFFFFFFFF   
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_n___S                    0
#define PHYA_PHYRF_CAL_INFO_MEM_1_U_0             (0x00485C04)
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_0__CAL_INFO_MEM_1_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_CAL_INFO_MEM_1_U_0__CAL_INFO_MEM_1_1___S               0

#define PHYA_PHYRF_RX_FRAME_CTRL_0_L              (0x00489C00)
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L___POR     0x00000000
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___POR 0x00000000
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___M 0xFFFFFFFF
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___S               0
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L___M       0xFFFFFFFF   
#define   PHYA_PHYRF_RX_FRAME_CTRL_0_L___S                     0

#define PHYA_PHYRF_RX_FRAME_CTRL_1_L              (0x00489C08)
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L___POR     0x00000000
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___POR 0x0
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___M 0x00000001
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___S               0
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L___M       0x00000001   
#define   PHYA_PHYRF_RX_FRAME_CTRL_1_L___S                     0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L          (0x00489C10)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___POR 0x0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___M 0x00000001
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___M   0x00000001   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___S                 0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L          (0x00489C18)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___POR 0x00
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___M 0x000000FF
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___M   0x000000FF   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___S                 0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L          (0x00489C20)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___POR 0x00
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___M 0x0000007F
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___M   0x0000007F   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___S                 0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L          (0x00489C28)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___POR 0x0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___M 0x00000003
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___M   0x00000003   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___S                 0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L          (0x00489C30)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___POR 0x00
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___M 0x0000007F
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___M   0x0000007F   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___S                 0

#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L          (0x00489C38)
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___POR 0x00000000
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___POR 0x0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___M 0x00000003
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___S               0
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___M   0x00000003   
#define   PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___S                 0

#define PHYA_PHYRF_RTT_FAC_CORRECTION_L           (0x00489C40)
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L___POR  0x00000000
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___POR 0x000000
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___M 0x00FFFFFF
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___S               0
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L___M    0x00FFFFFF   
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_L___S                  0

#define PHYA_PHYRF_RTT_FAC_CORRECTION_U           (0x00489C44)
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U___POR  0x00000000
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___POR 0x0
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___M 0x00000001
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___S               0
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U___M    0x00000001   
#define   PHYA_PHYRF_RTT_FAC_CORRECTION_U___S                  0

#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L        (0x00489C48)
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___RWC  QCSR_REG_RO    
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___POR 0x00000000
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___POR 0x00000000
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___M 0xFFFFFFFF
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___S               0
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___M 0xFFFFFFFF   
#define   PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___S               0

#define PHYA_PHYRF_TX_FRAME_CTRL_0_L              (0x00489C50)
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___POR 0x0000
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___M 0x0000FFFF
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L___M       0x0000FFFF   
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_L___S                     0

#define PHYA_PHYRF_TX_FRAME_CTRL_0_U              (0x00489C54)
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___POR 0x0000
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___M 0x0000FFFF
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U___M       0x0000FFFF   
#define   PHYA_PHYRF_TX_FRAME_CTRL_0_U___S                     0

#define PHYA_PHYRF_TX_FRAME_CTRL_1_L              (0x00489C58)
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___POR 0x0
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___M 0x00000001
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L___M       0x00000001   
#define   PHYA_PHYRF_TX_FRAME_CTRL_1_L___S                     0

#define PHYA_PHYRF_TX_FRAME_CTRL_2_L              (0x00489C60)
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___POR 0x0000
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___M 0x0000FFFF
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L___M       0x0000FFFF   
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_L___S                     0

#define PHYA_PHYRF_TX_FRAME_CTRL_2_U              (0x00489C64)
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___POR 0x0000
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___M 0x0000FFFF
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U___M       0x0000FFFF   
#define   PHYA_PHYRF_TX_FRAME_CTRL_2_U___S                     0

#define PHYA_PHYRF_TX_FRAME_CTRL_3_L              (0x00489C68)
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L___POR     0x00000000
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___POR 0x0
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___M 0x00000001
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___S               0
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L___M       0x00000001   
#define   PHYA_PHYRF_TX_FRAME_CTRL_3_L___S                     0

#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L             (0x00489C70)
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___POR    0x00000000
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___POR 0x0
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___POR 0x0
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___M 0x00000002
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___S               1
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___M 0x00000001
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___S               0
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___M      0x00000003   
#define   PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___S                    0

#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L             (0x00489C78)
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L___POR    0x00000000
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___POR 0x00000000
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___M 0xFFFFFFFF
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___S               0
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_TS_TIMER0_CTRL_0_L___S                    0

#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L             (0x00489C80)
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L___POR    0x00000000
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___POR 0x0
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___M 0x00000001
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___S               0
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L___M      0x00000001   
#define   PHYA_PHYRF_TS_TIMER0_CTRL_1_L___S                    0

#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L             (0x00489C88)
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L___POR    0x00000000
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___POR 0x00000000
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___M 0xFFFFFFFF
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___S               0
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L___M      0xFFFFFFFF   
#define   PHYA_PHYRF_TS_TIMER1_CTRL_0_L___S                    0

#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L             (0x00489C90)
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L___POR    0x00000000
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___POR 0x0
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___M 0x00000001
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___S               0
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L___M      0x00000001   
#define   PHYA_PHYRF_TS_TIMER1_CTRL_1_L___S                    0

#define PHYA_PHYRF_PAPRD_CTRL_L_B0                (0x00490000)
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0___POR       0x001F8000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___POR 0x3F
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___M 0x7F800000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___S              23
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___M 0x007F8000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___S              15
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___M 0x00004000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___S              14
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___M 0x00003FC0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___S               6
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___M 0x0000003E
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___S               1
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___M 0x00000001
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0___M         0x7FFFFFFF   
#define   PHYA_PHYRF_PAPRD_CTRL_L_B0___S                       0

#define PHYA_PHYRF_PAPRD_CTRL_L_B1                (0x00498000)
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1___POR       0x001F8000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___POR 0x3F
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___M 0x7F800000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___S              23
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___M 0x007F8000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___S              15
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___M 0x00004000
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___S              14
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___M 0x00003FC0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___S               6
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___M 0x0000003E
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___S               1
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___M 0x00000001
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1___M         0x7FFFFFFF   
#define   PHYA_PHYRF_PAPRD_CTRL_L_B1___S                       0

#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0           (0x00490008)
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___POR  0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___M 0x00002000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___S              13
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___M 0x00001000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___S              12
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___M 0x00000FF0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___S               4
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___M 0x00000008
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___S               3
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___M 0x00000004
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___S               2
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___M 0x00000002
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___S               1
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___M 0x00000001
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___M    0x00003FFF   
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___S                  0

#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1           (0x00498008)
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___POR  0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___POR 0x00
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___POR 0x0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___M 0x00002000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___S              13
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___M 0x00001000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___S              12
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___M 0x00000FF0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___S               4
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___M 0x00000008
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___S               3
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___M 0x00000004
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___S               2
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___M 0x00000002
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___S               1
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___M 0x00000001
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___M    0x00003FFF   
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___S                  0

#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0           (0x0049000C)
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___POR  0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___M 0xFFFFFFFF
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___S                  0

#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1           (0x0049800C)
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___POR  0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___M 0xFFFFFFFF
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___S               0
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___M    0xFFFFFFFF   
#define   PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___S                  0

#define PHYA_PHYRF_EDPD_CTRL_0_L_B0               (0x00490010)
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0___POR      0x04030000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___POR 0x4
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___POR 0x3
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___S              16
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_0_L_B1               (0x00498010)
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1___POR      0x04030000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___POR 0x4
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___POR 0x3
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___S              16
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_0_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_0_U_B0               (0x00490014)
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0___POR      0x04030605
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___POR 0x4
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___POR 0x3
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___POR 0x5
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___M 0x07000000
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___M 0x00070000
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___S              16
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___M 0x00000007
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0___M        0x07070707   
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_0_U_B1               (0x00498014)
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1___POR      0x04030605
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___POR 0x4
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___POR 0x3
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___POR 0x5
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___M 0x07000000
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___M 0x00070000
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___S              16
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___M 0x00000007
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1___M        0x07070707   
#define   PHYA_PHYRF_EDPD_CTRL_0_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_1_L_B0               (0x00490018)
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0___POR      0x08000008
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___S              24
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___S               8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___S               0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_1_L_B1               (0x00498018)
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1___POR      0x08000008
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___S              24
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___S               8
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___S               0
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_1_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_1_U_B0               (0x0049001C)
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0___POR      0x00020108
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___POR 0x2
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___M 0x00070000
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0___M        0x0F07070F   
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_1_U_B1               (0x0049801C)
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1___POR      0x00020108
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___POR 0x2
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___POR 0x8
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___M 0x00070000
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1___M        0x0F07070F   
#define   PHYA_PHYRF_EDPD_CTRL_1_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_2_L_B0               (0x00490020)
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0___POR      0x00000201
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___POR 0x2
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000007
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___S               0
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0___M        0x00000707   
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_2_L_B1               (0x00498020)
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1___POR      0x00000201
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___POR 0x2
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000700
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___S               8
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000007
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___S               0
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1___M        0x00000707   
#define   PHYA_PHYRF_EDPD_CTRL_2_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_2_U_B0               (0x00490024)
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0___POR      0x000080BE
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___POR 0x080BE
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___M 0x0003FFFF
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0___M        0x0003FFFF   
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_2_U_B1               (0x00498024)
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1___POR      0x000080BE
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___POR 0x080BE
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___M 0x0003FFFF
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___S               0
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1___M        0x0003FFFF   
#define   PHYA_PHYRF_EDPD_CTRL_2_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_3_L_B0               (0x00490028)
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0___POR      0x00012416
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___POR 0x12416
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___M 0x0003FFFF
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___S               0
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0___M        0x0003FFFF   
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_3_L_B1               (0x00498028)
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1___POR      0x00012416
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___POR 0x12416
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___M 0x0003FFFF
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___S               0
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1___M        0x0003FFFF   
#define   PHYA_PHYRF_EDPD_CTRL_3_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_4_L_B0               (0x00490030)
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0___POR      0x06060606
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_4_L_B1               (0x00498030)
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1___POR      0x06060606
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_4_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_4_U_B0               (0x00490034)
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0___POR      0x06060606
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_4_U_B1               (0x00498034)
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1___POR      0x06060606
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___POR 0x6
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___M 0x0F000000
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___M 0x000F0000
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___M 0x00000F00
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___M 0x0000000F
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1___M        0x0F0F0F0F   
#define   PHYA_PHYRF_EDPD_CTRL_4_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_5_L_B0               (0x00490038)
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_5_L_B1               (0x00498038)
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_5_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_5_U_B0               (0x0049003C)
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_5_U_B1               (0x0049803C)
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_5_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_6_L_B0               (0x00490040)
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_6_L_B1               (0x00498040)
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_6_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_6_U_B0               (0x00490044)
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_6_U_B1               (0x00498044)
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1___POR      0x00000000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___POR 0x0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___M 0x01000000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___M 0x00010000
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1___M        0x01010101   
#define   PHYA_PHYRF_EDPD_CTRL_6_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_7_L_B0               (0x00490048)
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0___POR      0x80808080
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___M 0xFF000000
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___M 0x00FF0000
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___M 0x0000FF00
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___M 0x000000FF
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0___M        0xFFFFFFFF   
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_7_L_B1               (0x00498048)
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1___POR      0x80808080
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___M 0xFF000000
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___S              24
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___M 0x00FF0000
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___S              16
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___M 0x0000FF00
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___S               8
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___M 0x000000FF
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___S               0
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1___M        0xFFFFFFFF   
#define   PHYA_PHYRF_EDPD_CTRL_7_L_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_7_U_B0               (0x0049004C)
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0___POR      0x80808080
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___M 0xFF000000
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___M 0x00FF0000
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___M 0x0000FF00
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___M 0x000000FF
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0___M        0xFFFFFFFF   
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_7_U_B1               (0x0049804C)
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1___POR      0x80808080
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___POR 0x80
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___M 0xFF000000
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___S              24
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___M 0x00FF0000
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___S              16
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___M 0x0000FF00
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___S               8
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___M 0x000000FF
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___S               0
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1___M        0xFFFFFFFF   
#define   PHYA_PHYRF_EDPD_CTRL_7_U_B1___S                      0

#define PHYA_PHYRF_EDPD_CTRL_8_L_B0               (0x00490050)
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0___POR      0xFFFF0101
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___POR 0xFFFF
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___M 0xFFFF0000
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___S              16
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___S               8
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___S               0
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0___M        0xFFFF0101   
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B0___S                      0

#define PHYA_PHYRF_EDPD_CTRL_8_L_B1               (0x00498050)
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1___POR      0xFFFF0101
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___POR 0xFFFF
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___POR 0x1
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___M 0xFFFF0000
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___S              16
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___M 0x00000100
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___S               8
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___M 0x00000001
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___S               0
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1___M        0xFFFF0101   
#define   PHYA_PHYRF_EDPD_CTRL_8_L_B1___S                      0

#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0          (0x00490058)
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___POR 0x00
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___M 0x000000FF
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___S               0
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___M   0x000000FF   
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___S                 0

#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1          (0x00498058)
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___POR 0x00
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___M 0x000000FF
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___S               0
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___M   0x000000FF   
#define   PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___S                 0

#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0          (0x00490060)
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___M 0x3F000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___S              24
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___M 0x003F0000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___S              16
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___M 0x00003F00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___S               8
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___M 0x0000003F
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___S               0
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___M   0x3F3F3F3F   
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___S                 0

#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1          (0x00498060)
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___M 0x3F000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___S              24
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___M 0x003F0000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___S              16
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___M 0x00003F00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___S               8
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___M 0x0000003F
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___S               0
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___M   0x3F3F3F3F   
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___S                 0

#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0          (0x00490064)
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___M 0x3F000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___S              24
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___M 0x003F0000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___S              16
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___M 0x00003F00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___S               8
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___M 0x0000003F
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___S               0
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___M   0x3F3F3F3F   
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___S                 0

#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1          (0x00498064)
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___POR 0x00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___M 0x3F000000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___S              24
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___M 0x003F0000
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___S              16
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___M 0x00003F00
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___S               8
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___M 0x0000003F
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___S               0
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___M   0x3F3F3F3F   
#define   PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___S                 0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0   (0x00490068)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1   (0x00498068)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0   (0x0049006C)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1   (0x0049806C)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0   (0x00490070)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1   (0x00498070)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0   (0x00490074)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___S               0

#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1   (0x00498074)
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___POR 0x000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___M 0x03FF0000
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___S              16
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___M 0x000003FF
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___S               0
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___M 0x03FF03FF   
#define   PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___S               0

#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0         (0x00490078)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1         (0x00498078)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0         (0x0049007C)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1         (0x0049807C)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0         (0x00490080)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1         (0x00498080)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0         (0x00490084)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1         (0x00498084)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___M 0x0FFF0000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___S              16
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___M  0x0FFF0FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0         (0x00490088)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___M  0x00000FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___S                0

#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1         (0x00498088)
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___POR 0x000
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___M 0x00000FFF
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___S               0
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___M  0x00000FFF   
#define   PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___S                0

#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0              (0x00490090)
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0___POR     0x0000ABCD
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___POR 0x0ABCD
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1              (0x00498090)
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1___POR     0x0000ABCD
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___POR 0x0ABCD
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_0_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0              (0x00490094)
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1              (0x00498094)
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_0_U_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0              (0x00490098)
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1              (0x00498098)
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_1_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0              (0x0049009C)
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0___POR     0x0000AB73
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___POR 0x0AB73
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1              (0x0049809C)
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1___POR     0x0000AB73
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___POR 0x0AB73
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_1_U_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0              (0x004900A0)
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1              (0x004980A0)
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_2_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0              (0x004900A4)
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1              (0x004980A4)
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_2_U_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0              (0x004900A8)
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0___POR     0x0000AB73
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___POR 0x0AB73
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1              (0x004980A8)
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1___POR     0x0000AB73
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___POR 0x0AB73
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_3_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0              (0x004900AC)
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1              (0x004980AC)
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_3_U_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0              (0x004900B0)
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1              (0x004980B0)
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___POR 0x00000
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___M 0x0003FFFF
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1___M       0x0003FFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_4_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0              (0x004900B4)
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___POR 0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1              (0x004980B4)
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___POR 0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_4_U_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0              (0x004900B8)
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___POR 0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1              (0x004980B8)
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1___POR     0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___POR 0x00000000
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___M 0xFFFFFFFF
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1___M       0xFFFFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_5_L_B1___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0              (0x004900BC)
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0___POR     0x00100000
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___POR 0x10
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___POR 0x00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___POR 0x00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___M 0x00FF0000
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___S              16
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___M 0x0000FF00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___S               8
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___M 0x000000FF
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0___M       0x00FFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B0___S                     0

#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1              (0x004980BC)
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1___POR     0x00100000
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___POR 0x10
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___POR 0x00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___POR 0x00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___M 0x00FF0000
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___S              16
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___M 0x0000FF00
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___S               8
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___M 0x000000FF
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___S               0
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1___M       0x00FFFFFF   
#define   PHYA_PHYRF_PDC_NCHAIN_5_U_B1___S                     0

#define PHYA_PHYRF_RXCORR_COEFF_L_B0              (0x004900C0)
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0___POR     0x00000000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0___M       0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_COEFF_L_B0___S                     0

#define PHYA_PHYRF_RXCORR_COEFF_L_B1              (0x004980C0)
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1___POR     0x00000000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1___M       0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_COEFF_L_B1___S                     0

#define PHYA_PHYRF_RXCORR_COEFF_U_B0              (0x004900C4)
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0___POR     0x00000000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0___M       0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_COEFF_U_B0___S                     0

#define PHYA_PHYRF_RXCORR_COEFF_U_B1              (0x004980C4)
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1___POR     0x00000000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1___M       0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_COEFF_U_B1___S                     0

#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0          (0x004900C8)
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___M   0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___S                 0

#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1          (0x004980C8)
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___M   0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___S                 0

#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0          (0x004900CC)
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___POR 0x00000000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___M   0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___S                 0

#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1          (0x004980CC)
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___POR 0x00000000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___POR 0x000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___M 0x01FF0000
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___S              16
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___M 0x000001FF
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___S               0
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___M   0x01FF01FF   
#define   PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___S                 0

#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0            (0x004900D0)
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___M 0x03000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___S              24
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___M 0x000F0000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___S              16
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___M 0x00000100
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___S               8
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___M 0x00000001
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0___M     0x030F0101   
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B0___S                   0

#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1            (0x004980D0)
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___M 0x03000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___S              24
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___M 0x000F0000
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___S              16
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___M 0x00000100
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___S               8
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___M 0x00000001
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1___M     0x030F0101   
#define   PHYA_PHYRF_RXCORR_FORCE_0_L_B1___S                   0

#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0            (0x004900D4)
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___POR 0x00
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___M 0xFF000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___S              24
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___M 0x00010000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___S              16
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___M 0x00000100
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___S               8
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___M 0x00000001
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0___M     0xFF010101   
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B0___S                   0

#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1            (0x004980D4)
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___POR 0x00
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___POR 0x0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___M 0xFF000000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___S              24
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___M 0x00010000
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___S              16
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___M 0x00000100
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___S               8
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___M 0x00000001
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1___M     0xFF010101   
#define   PHYA_PHYRF_RXCORR_FORCE_0_U_B1___S                   0

#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0            (0x004900D8)
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___POR 0x00
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___M 0x000000FF
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0___M     0x000000FF   
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B0___S                   0

#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1            (0x004980D8)
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1___POR   0x00000000
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___POR 0x00
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___M 0x000000FF
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___S               0
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1___M     0x000000FF   
#define   PHYA_PHYRF_RXCORR_FORCE_1_L_B1___S                   0

#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n(n) (0x004900E0+0x8*(n))
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___S               0
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___M 0x3FFF3FFF   
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___S               0
#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0       (0x004900E0)
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_Q_EVEN___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_Q_EVEN___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_I_EVEN___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_I_EVEN___S               0

#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n(n) (0x004980E0+0x8*(n))
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___S               0
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___M 0x3FFF3FFF   
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___S               0
#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0       (0x004980E0)
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_Q_EVEN___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_Q_EVEN___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_I_EVEN___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_I_EVEN___S               0

#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n(n) (0x004900E4+0x8*(n))
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___S               0
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___M 0x3FFF3FFF   
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___S               0
#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0       (0x004900E4)
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_Q_ODD___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_Q_ODD___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_I_ODD___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_I_ODD___S               0

#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n(n) (0x004980E4+0x8*(n))
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___POR 0x0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___S               0
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___M 0x3FFF3FFF   
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___S               0
#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0       (0x004980E4)
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_Q_ODD___M 0x3FFF0000
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_Q_ODD___S              16
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_I_ODD___M 0x00003FFF
#define   PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_I_ODD___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n(n) (0x004908E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0 (0x004908E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n(n) (0x004988E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0 (0x004988E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n(n) (0x004908E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0 (0x004908E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n(n) (0x004988E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0 (0x004988E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n(n) (0x00490CE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0 (0x00490CE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n(n) (0x00498CE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0 (0x00498CE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n(n) (0x00490CE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0 (0x00490CE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n(n) (0x00498CE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0 (0x00498CE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n(n) (0x004910E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0 (0x004910E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n(n) (0x004990E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0 (0x004990E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_0___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n(n) (0x004910E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0 (0x004910E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n(n) (0x004990E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0 (0x004990E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_0___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n(n) (0x004914E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0 (0x004914E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n(n) (0x004994E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0 (0x004994E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_1___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n(n) (0x004914E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0 (0x004914E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n(n) (0x004994E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0 (0x004994E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_1___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n(n) (0x004918E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0  (0x004918E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__BASE_Q_OR_I_ABSX3___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__BASE_Q_OR_I_ABSX3___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__LOWER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__LOWER_Q_OR_I_ABSX3___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n(n) (0x004998E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0  (0x004998E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__BASE_Q_OR_I_ABSX3___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__BASE_Q_OR_I_ABSX3___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__LOWER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__LOWER_Q_OR_I_ABSX3___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n(n) (0x004918E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0  (0x004918E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX3___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n(n) (0x004998E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0  (0x004998E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX3___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX3___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n(n) (0x00491CE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0  (0x00491CE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__BASE_Q_OR_I_ABSX4___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__BASE_Q_OR_I_ABSX4___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__LOWER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__LOWER_Q_OR_I_ABSX4___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n(n) (0x00499CE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0  (0x00499CE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__BASE_Q_OR_I_ABSX4___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__BASE_Q_OR_I_ABSX4___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__LOWER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__LOWER_Q_OR_I_ABSX4___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n(n) (0x00491CE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0  (0x00491CE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX4___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n(n) (0x00499CE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0  (0x00499CE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX4___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX4___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n(n) (0x004920E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0 (0x004920E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ5___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ5___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n(n) (0x0049A0E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0 (0x0049A0E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ5___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ5___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n(n) (0x004920E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0 (0x004920E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ5___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n(n) (0x0049A0E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0 (0x0049A0E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ5___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n(n) (0x004924E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0 (0x004924E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ6___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ6___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n(n) (0x0049A4E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0 (0x0049A4E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ6___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ6___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n(n) (0x004924E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0 (0x004924E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ6___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n(n) (0x0049A4E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0 (0x0049A4E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ6___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n(n) (0x004928E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0 (0x004928E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ7___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ7___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n(n) (0x0049A8E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0 (0x0049A8E0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ7___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ7___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n(n) (0x004928E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0 (0x004928E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ7___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n(n) (0x0049A8E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0 (0x0049A8E4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ7___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n(n) (0x00492CE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0 (0x00492CE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ8___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ8___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n(n) (0x0049ACE0+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___POR 0x0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___M 0x3FFF03FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0 (0x0049ACE0)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ8___S              16
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ8___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n(n) (0x00492CE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0 (0x00492CE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ8___S               0

#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n(n) (0x0049ACE4+0x8*(n))
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___POR 0x000
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___S               0
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___M 0x000003FF   
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0 (0x0049ACE4)
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF
#define   PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ8___S               0

#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n(n) (0x004930E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___S               0
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___M 0x0FFF0FFF   
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___S               0
#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0       (0x004930E0)
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_Q_EVEN___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_Q_EVEN___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_I_EVEN___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_I_EVEN___S               0

#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n(n) (0x0049B0E0+0x8*(n))
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___S               0
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___M 0x0FFF0FFF   
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___S               0
#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0       (0x0049B0E0)
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_Q_EVEN___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_Q_EVEN___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_I_EVEN___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_I_EVEN___S               0

#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n(n) (0x004930E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___S               0
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___M 0x0FFF0FFF   
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___S               0
#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0       (0x004930E4)
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_Q_ODD___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_Q_ODD___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_I_ODD___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_I_ODD___S               0

#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n(n) (0x0049B0E4+0x8*(n))
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___POR 0x000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___S               0
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___M 0x0FFF0FFF   
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___S               0
#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0       (0x0049B0E4)
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_Q_ODD___M 0x0FFF0000
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_Q_ODD___S              16
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_I_ODD___M 0x00000FFF
#define   PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_I_ODD___S               0

#define PHYA_PHYRF_CL_TAB_L_B0_n(n)      (0x004931A0+0x8*(n))
#define   PHYA_PHYRF_CL_TAB_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_CL_TAB_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_CL_TAB_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_CL_TAB_L_B0_n___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_L_B0_n___POR         0x00000000
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___S              16
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___S               0
#define   PHYA_PHYRF_CL_TAB_L_B0_n___M           0x07FF07FF   
#define   PHYA_PHYRF_CL_TAB_L_B0_n___S                         0
#define PHYA_PHYRF_CL_TAB_L_B0_0                  (0x004931A0)
#define   PHYA_PHYRF_CL_TAB_L_B0_0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_Q_EVEN___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_Q_EVEN___S              16
#define   PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_I_EVEN___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_I_EVEN___S               0

#define PHYA_PHYRF_CL_TAB_L_B1_n(n)      (0x0049B1A0+0x8*(n))
#define   PHYA_PHYRF_CL_TAB_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_CL_TAB_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_CL_TAB_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_CL_TAB_L_B1_n___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_L_B1_n___POR         0x00000000
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___S              16
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___S               0
#define   PHYA_PHYRF_CL_TAB_L_B1_n___M           0x07FF07FF   
#define   PHYA_PHYRF_CL_TAB_L_B1_n___S                         0
#define PHYA_PHYRF_CL_TAB_L_B1_0                  (0x0049B1A0)
#define   PHYA_PHYRF_CL_TAB_L_B1_0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_Q_EVEN___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_Q_EVEN___S              16
#define   PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_I_EVEN___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_I_EVEN___S               0

#define PHYA_PHYRF_CL_TAB_U_B0_n(n)      (0x004931A4+0x8*(n))
#define   PHYA_PHYRF_CL_TAB_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_CL_TAB_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_CL_TAB_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_CL_TAB_U_B0_n___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_U_B0_n___POR         0x00000000
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___POR 0x000
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___S              16
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___S               0
#define   PHYA_PHYRF_CL_TAB_U_B0_n___M           0x07FF07FF   
#define   PHYA_PHYRF_CL_TAB_U_B0_n___S                         0
#define PHYA_PHYRF_CL_TAB_U_B0_0                  (0x004931A4)
#define   PHYA_PHYRF_CL_TAB_U_B0_0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_Q_ODD___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_Q_ODD___S              16
#define   PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_I_ODD___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_I_ODD___S               0

#define PHYA_PHYRF_CL_TAB_U_B1_n(n)      (0x0049B1A4+0x8*(n))
#define   PHYA_PHYRF_CL_TAB_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_CL_TAB_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_CL_TAB_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_CL_TAB_U_B1_n___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_U_B1_n___POR         0x00000000
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___POR 0x000
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___S              16
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___S               0
#define   PHYA_PHYRF_CL_TAB_U_B1_n___M           0x07FF07FF   
#define   PHYA_PHYRF_CL_TAB_U_B1_n___S                         0
#define PHYA_PHYRF_CL_TAB_U_B1_0                  (0x0049B1A4)
#define   PHYA_PHYRF_CL_TAB_U_B1_0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_Q_ODD___M 0x07FF0000
#define   PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_Q_ODD___S              16
#define   PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_I_ODD___M 0x000007FF
#define   PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_I_ODD___S               0

#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n(n) (0x004932A0+0x8*(n))
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___POR   0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___POR 0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___S               0
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___S                   0
#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_0            (0x004932A0)
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_0__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B0_0__TX_IQCOEFF_0_31BIT___S               0

#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n(n) (0x0049B2A0+0x8*(n))
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___POR   0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___POR 0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___S               0
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___M     0xFFFFFFFF   
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___S                   0
#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_0            (0x0049B2A0)
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_0__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_L_B1_0__TX_IQCOEFF_0_31BIT___S               0

#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n(n) (0x004932A4+0x8*(n))
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___POR   0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___POR 0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___S               0
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___M     0x7FFFFFFF   
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___S                   0
#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_0            (0x004932A4)
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_0__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B0_0__TX_IQCOEFF_32_62BIT___S               0

#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n(n) (0x0049B2A4+0x8*(n))
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___POR   0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___POR 0x00000000
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___S               0
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___M     0x7FFFFFFF   
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___S                   0
#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_0            (0x0049B2A4)
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_0__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF
#define   PHYA_PHYRF_TXIQCORR_MEM_U_B1_0__TX_IQCOEFF_32_62BIT___S               0

#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0          (0x004938A0)
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___POR 0x00000000
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___S               0
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___M   0xFFFFFFFF   
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___S                 0

#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1          (0x0049B8A0)
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___POR 0x00000000
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___S               0
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___M   0xFFFFFFFF   
#define   PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___S                 0

#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x004938A8+0x8*(n))
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x004938A8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x004938B0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x004938B8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x004938C0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x004938C8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x004938D0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x004938D8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x004938E0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049B8A8+0x8*(n))
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049B8A8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049B8B0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049B8B8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049B8C0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049B8C8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049B8D0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049B8D8)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049B8E0)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x004938AC+0x8*(n))
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x004938AC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x004938B4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x004938BC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x004938C4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x004938CC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x004938D4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x004938DC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x004938E4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049B8AC+0x8*(n))
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049B8AC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049B8B4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049B8BC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049B8C4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049B8CC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049B8D4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049B8DC)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049B8E4)
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x004938E8+0x8*(n))
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x004938E8)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x004938F0)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x004938F8)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x00493900)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x00493908)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x00493910)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x00493918)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x00493920)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049B8E8+0x8*(n))
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049B8E8)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049B8F0)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049B8F8)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049B900)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049B908)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049B910)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049B918)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049B920)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x004938EC+0x8*(n))
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x004938EC)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x004938F4)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x004938FC)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x00493904)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x0049390C)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x00493914)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x0049391C)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x00493924)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049B8EC+0x8*(n))
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049B8EC)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049B8F4)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049B8FC)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049B904)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049B90C)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049B914)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049B91C)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049B924)
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n(n) (0x00493928+0x8*(n))
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___S               0
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___S               0
#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0     (0x00493928)
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0__RXIQ_CORR_COEFF_MEM_0___S               0

#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n(n) (0x0049B928+0x8*(n))
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___S               0
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___S               0
#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0     (0x0049B928)
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0__RXIQ_CORR_COEFF_MEM_0___S               0

#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n(n) (0x0049392C+0x8*(n))
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___S               0
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___S               0
#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0     (0x0049392C)
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0__RXIQ_CORR_COEFF_MEM_1___S               0

#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n(n) (0x0049B92C+0x8*(n))
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___POR 0x00000000
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___S               0
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___S               0
#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0     (0x0049B92C)
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0__RXIQ_CORR_COEFF_MEM_1___S               0

#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x00494328+0x8*(n))
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x00494328)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x00494330)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x00494338)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x00494340)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x00494348)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x00494350)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x00494358)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x00494360)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049C328+0x8*(n))
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049C328)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049C330)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049C338)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049C340)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049C348)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049C350)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049C358)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049C360)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S               0

#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x0049432C+0x8*(n))
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x0049432C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x00494334)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x0049433C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x00494344)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x0049434C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x00494354)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x0049435C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x00494364)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049C32C+0x8*(n))
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF   
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049C32C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049C334)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049C33C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049C344)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049C34C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049C354)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049C35C)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0
#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049C364)
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S              16
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF
#define   PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0 (0x00494368)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1 (0x0049C368)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0 (0x0049436C)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1 (0x0049C36C)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0 (0x00494370)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1 (0x0049C370)
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___S              24
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___S              16
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___S               8
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___S               0
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0  (0x00494378)
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___M 0x7F000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___S              24
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___S              16
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___S               8
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___S               0
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___M 0x7FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1  (0x0049C378)
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___M 0x7F000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___S              24
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___S              16
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___S               8
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___S               0
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___M 0x7FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0 (0x00494380)
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___S               8
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___S               0
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1 (0x0049C380)
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___S               8
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___S               0
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0       (0x00494388)
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___M 0x00000001
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___S               0
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___M 0x00000001   
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1       (0x0049C388)
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___M 0x00000001
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___S               0
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___M 0x00000001   
#define   PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0        (0x00494390)
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___S              24
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___M 0x00FC0000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___S              18
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___M 0x0003FC00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___S              10
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___M 0x00000200
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___S               9
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___M 0x000001FE
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___S               1
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___M 0x00000001
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___S               0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1        (0x0049C390)
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___M 0xFF000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___S              24
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___M 0x00FC0000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___S              18
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___M 0x0003FC00
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___S              10
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___M 0x00000200
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___S               9
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___M 0x000001FE
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___S               1
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___M 0x00000001
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___S               0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0        (0x00494394)
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___M 0x000000F0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___S               4
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___S               0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___M 0x000000FF   
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___S               0

#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1        (0x0049C394)
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___M 0x000000F0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___S               4
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___S               0
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___M 0x000000FF   
#define   PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0 (0x00494398)
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___M 0x00FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1 (0x0049C398)
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___M 0x00FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_MU_L_B0                (0x004943A0)
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0___POR       0x00000000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___M 0x003FF000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___S              12
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___M 0x00000FF0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___S               4
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___S               0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0___M         0x003FFFFF   
#define   PHYA_PHYRF_TPC_CHN_MU_L_B0___S                       0

#define PHYA_PHYRF_TPC_CHN_MU_L_B1                (0x0049C3A0)
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1___POR       0x00000000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___M 0x003FF000
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___S              12
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___M 0x00000FF0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___S               4
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___S               0
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1___M         0x003FFFFF   
#define   PHYA_PHYRF_TPC_CHN_MU_L_B1___S                       0

#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0    (0x004943A8)
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___POR 0x0000007F
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___POR 0x7F
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___M 0x000000FF   
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1    (0x0049C3A8)
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___POR 0x0000007F
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___POR 0x7F
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___M 0x000000FF   
#define   PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0     (0x004943B0)
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___M 0x07F80000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___S              19
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___M 0x0007FE00
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___S               9
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___M 0x000001FF
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___M 0x07FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1     (0x0049C3B0)
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___M 0x07F80000
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___S              19
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___M 0x0007FE00
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___S               9
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___M 0x000001FF
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___M 0x07FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0   (0x004943B8)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___M 0x3C000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___S              26
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___M 0x03C00000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___S              22
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___M 0x003F0000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___M 0x3FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1   (0x0049C3B8)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___M 0x3C000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___S              26
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___M 0x03C00000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___S              22
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___M 0x003F0000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___M 0x3FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0   (0x004943BC)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___M 0x000003F0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___S               4
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___M 0x000003FF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1   (0x0049C3BC)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___M 0x000003F0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___S               4
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___M 0x000003FF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0    (0x004943C0)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___M 0x1FF80000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___S              19
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___M 0x0007FE00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___S               9
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___M 0x000001FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___M 0x1FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1    (0x0049C3C0)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___POR 0x000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___M 0x1FF80000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___S              19
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___M 0x0007FE00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___S               9
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___M 0x000001FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___M 0x1FFFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0 (0x004943C8)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___M 0x00003000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___S              12
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___M 0x00000FC0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___S               6
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___M 0x00000020
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___S               5
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___M 0x00000010
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___S               4
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___M 0x00003FFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1 (0x0049C3C8)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___M 0x00003000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___S              12
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___M 0x00000FC0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___S               6
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___M 0x00000020
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___S               5
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___M 0x00000010
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___S               4
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___M 0x0000000F
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___M 0x00003FFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0 (0x004943D0)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___M 0x04000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___S              26
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___S              25
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___S              24
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___M 0x07FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___S               0

#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1 (0x0049C3D0)
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___POR 0x00000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___POR 0x00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___M 0x04000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___S              26
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___S              25
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___S              24
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___M 0x00FF0000
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___S              16
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___S               8
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___S               0
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___M 0x07FFFFFF   
#define   PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n(n) (0x004943D8+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0        (0x004943D8)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0__RESDC_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0__RESDC_0___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n(n) (0x0049C3D8+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0        (0x0049C3D8)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0__RESDC_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0__RESDC_0___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n(n) (0x004943DC+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0        (0x004943DC)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0__RESDC_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0__RESDC_1___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n(n) (0x0049C3DC+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0        (0x0049C3DC)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0__RESDC_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0__RESDC_1___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n(n) (0x00494BD8+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___POR 0x000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___M 0x00FFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0        (0x00494BD8)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0__XLNA_RXIQCORR_0___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0__XLNA_RXIQCORR_0___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n(n) (0x0049CBD8+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___POR 0x000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___M 0x00FFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0        (0x0049CBD8)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0__XLNA_RXIQCORR_0___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0__XLNA_RXIQCORR_0___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n(n) (0x00494BDC+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___POR 0x000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___M 0x00FFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0        (0x00494BDC)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0__XLNA_RXIQCORR_1___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0__XLNA_RXIQCORR_1___S               0

#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n(n) (0x0049CBDC+0x8*(n))
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_nMIN 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_nMAX 0    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_ELEM 1    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___POR 0x000000
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___S               0
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___M 0x00FFFFFF   
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___S               0
#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0        (0x0049CBDC)
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0__XLNA_RXIQCORR_1___M 0x00FFFFFF
#define   PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0__XLNA_RXIQCORR_1___S               0

#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0 (0x00494FD8)
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___POR 0x00
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___M 0xFF000000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___S              24
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___M 0x00030000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___S              16
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___M 0x00000300
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___S               8
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___M 0x00000001
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___S               0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___M 0xFF030301   
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___S               0

#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1 (0x0049CFD8)
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___POR 0x00
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___POR 0x0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___M 0xFF000000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___S              24
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___M 0x00030000
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___S              16
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___M 0x00000300
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___S               8
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___M 0x00000001
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___S               0
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___M 0xFF030301   
#define   PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___S               0

#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0          (0x00494FE0)
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___M 0xFF000000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___S              24
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___M 0x00FF0000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___S              16
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___M 0x0000FF00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___S               8
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___M 0x000000FF
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___S               0
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___M   0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___S                 0

#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1          (0x0049CFE0)
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___POR 0x00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___M 0xFF000000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___S              24
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___M 0x00FF0000
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___S              16
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___M 0x0000FF00
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___S               8
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___M 0x000000FF
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___S               0
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___M   0xFFFFFFFF   
#define   PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___S                 0

#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0           (0x00494FE8)
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___POR  0x00000000
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___POR 0x0
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___M 0x00000001
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___S               0
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___M    0x00000001   
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___S                  0

#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1           (0x0049CFE8)
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___POR  0x00000000
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___POR 0x0
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___M 0x00000001
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___S               0
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___M    0x00000001   
#define   PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___S                  0

#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0        (0x00494FF0)
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___POR 0x00001000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___POR 0x100
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___M 0x00030000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___S              16
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___M 0x0000C000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___S              14
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___M 0x00003FF0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___S               4
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___M 0x0000000C
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___S               2
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___M 0x00000002
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___S               1
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___M 0x00000001
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___S               0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___M 0x0003FFFF   
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___S               0

#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1        (0x0049CFF0)
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___POR 0x00001000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___POR 0x100
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___POR 0x0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___M 0x00030000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___S              16
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___M 0x0000C000
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___S              14
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___M 0x00003FF0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___S               4
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___M 0x0000000C
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___S               2
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___M 0x00000002
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___S               1
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___M 0x00000001
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___S               0
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___M 0x0003FFFF   
#define   PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0             (0x00494FF8)
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0___POR    0x09000627
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___POR 0x8
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___POR 0x00
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___POR 0x3
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___POR 0x3
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___M 0x08000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___S              27
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___M 0x04000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___S              26
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___M 0x02000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___S              25
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___M 0x01E00000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___S              21
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___M 0x00180000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___S              19
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___M 0x0007F800
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___S              11
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___M 0x00000600
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___S               9
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___M 0x00000100
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___S               8
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___M 0x00000080
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___S               7
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___M 0x00000060
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___S               5
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___M 0x0000001E
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___S               1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___M 0x00000001
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___S               0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0___M      0x0FFFFFFF   
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B0___S                    0

#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1             (0x0049CFF8)
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1___POR    0x09000627
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___POR 0x8
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___POR 0x00
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___POR 0x3
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___POR 0x0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___POR 0x3
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___POR 0x1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___M 0x08000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___S              27
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___M 0x04000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___S              26
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___M 0x02000000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___S              25
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___M 0x01E00000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___S              21
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___M 0x00180000
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___S              19
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___M 0x0007F800
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___S              11
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___M 0x00000600
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___S               9
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___M 0x00000100
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___S               8
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___M 0x00000080
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___S               7
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___M 0x00000060
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___S               5
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___M 0x0000001E
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___S               1
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___M 0x00000001
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___S               0
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1___M      0x0FFFFFFF   
#define   PHYA_PHYRF_RF_BUS_CONFIG_L_B1___S                    0

#define PHYA_PHYRF_RF_BUS_STATUS_L_B0             (0x00495000)
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0___POR    0x00000000
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___POR 0x0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___POR 0x00
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___POR 0x0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___M 0x00000200
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___S               9
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___M 0x000001F0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___S               4
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___M 0x0000000F
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___S               0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0___M      0x000003FF   
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B0___S                    0

#define PHYA_PHYRF_RF_BUS_STATUS_L_B1             (0x0049D000)
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1___RWC       QCSR_REG_RO    
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1___POR    0x00000000
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___POR 0x0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___POR 0x00
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___POR 0x0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___M 0x00000200
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___S               9
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___M 0x000001F0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___S               4
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___M 0x0000000F
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___S               0
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1___M      0x000003FF   
#define   PHYA_PHYRF_RF_BUS_STATUS_L_B1___S                    0

#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0         (0x00495008)
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___M 0x00400000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___S              22
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___M 0x00200000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___S              21
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___M 0x00100000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___S              20
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___M 0x00080000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___S              19
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___M 0x00040000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___S              18
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___M 0x00020000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___S              17
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___M 0x00010000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___S              16
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___M 0x00008000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___S              15
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___M 0x00004000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___S              14
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___M 0x00002000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___S              13
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___M 0x00001000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___S              12
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___M 0x00000800
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___S              11
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___M 0x00000400
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___S              10
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___M 0x00000200
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___S               9
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___M 0x00000100
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___S               8
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___M 0x00000080
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___S               7
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___M 0x00000040
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___S               6
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___M 0x00000020
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___S               5
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___M 0x00000010
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___S               4
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___M 0x00000008
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___S               3
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___M 0x00000004
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___S               2
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___M 0x00000002
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___S               1
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___M 0x00000001
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___S               0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___M  0x007FFFFF   
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___S                0

#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1         (0x0049D008)
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___RWC   QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___POR 0x0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___M 0x00400000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___S              22
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___M 0x00200000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___S              21
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___M 0x00100000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___S              20
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___M 0x00080000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___S              19
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___M 0x00040000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___S              18
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___M 0x00020000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___S              17
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___M 0x00010000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___S              16
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___M 0x00008000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___S              15
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___M 0x00004000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___S              14
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___M 0x00002000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___S              13
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___M 0x00001000
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___S              12
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___M 0x00000800
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___S              11
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___M 0x00000400
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___S              10
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___M 0x00000200
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___S               9
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___M 0x00000100
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___S               8
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___M 0x00000080
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___S               7
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___M 0x00000040
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___S               6
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___M 0x00000020
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___S               5
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___M 0x00000010
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___S               4
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___M 0x00000008
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___S               3
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___M 0x00000004
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___S               2
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___M 0x00000002
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___S               1
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___M 0x00000001
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___S               0
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___M  0x007FFFFF   
#define   PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___S                0

#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0       (0x00495010)
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___S               0
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1       (0x0049D010)
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___S               0
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0          (0x00495018)
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___S               0
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___M   0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___S                 0

#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1          (0x0049D018)
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___S               0
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___M   0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___S                 0

#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0   (0x00495020)
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1   (0x0049D020)
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0 (0x00495028)
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1 (0x0049D028)
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0  (0x00495030)
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___S               0
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1  (0x0049D030)
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___S               0
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0 (0x00495038)
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___S               0
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1 (0x0049D038)
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___S               0
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0 (0x00495040)
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1 (0x0049D040)
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0 (0x00495048)
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1 (0x0049D048)
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0 (0x00495050)
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1 (0x0049D050)
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0 (0x00495058)
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1 (0x0049D058)
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0 (0x00495060)
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1 (0x0049D060)
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0 (0x00495068)
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1 (0x0049D068)
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0 (0x00495070)
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1 (0x0049D070)
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0 (0x00495078)
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___S               0

#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1 (0x0049D078)
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___POR 0x00000000
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___S               0
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___S               0

#define PHYA_PHYRF_ARB_CTRL_L_B0                  (0x00495080)
#define   PHYA_PHYRF_ARB_CTRL_L_B0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CTRL_L_B0___POR         0x00000000
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___M 0x00008000
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___S              15
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___M 0x00004000
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___S              14
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___M 0x00002000
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___S              13
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___M 0x00001000
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___S              12
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___M 0x00000800
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___S              11
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___M 0x00000400
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___S              10
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___M 0x00000200
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___S               9
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___M 0x00000100
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___S               8
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___M 0x00000080
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___S               7
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___M 0x00000040
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___S               6
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___M 0x00000020
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___S               5
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___M 0x00000010
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___S               4
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___M 0x00000008
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___S               3
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___M 0x00000004
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___S               2
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___M 0x00000002
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___S               1
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___M 0x00000001
#define   PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___S               0
#define   PHYA_PHYRF_ARB_CTRL_L_B0___M           0x0000FFFF   
#define   PHYA_PHYRF_ARB_CTRL_L_B0___S                         0

#define PHYA_PHYRF_ARB_CTRL_L_B1                  (0x0049D080)
#define   PHYA_PHYRF_ARB_CTRL_L_B1___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CTRL_L_B1___POR         0x00000000
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___M 0x00008000
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___S              15
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___M 0x00004000
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___S              14
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___M 0x00002000
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___S              13
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___M 0x00001000
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___S              12
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___M 0x00000800
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___S              11
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___M 0x00000400
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___S              10
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___M 0x00000200
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___S               9
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___M 0x00000100
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___S               8
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___M 0x00000080
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___S               7
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___M 0x00000040
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___S               6
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___M 0x00000020
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___S               5
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___M 0x00000010
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___S               4
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___M 0x00000008
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___S               3
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___M 0x00000004
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___S               2
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___M 0x00000002
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___S               1
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___M 0x00000001
#define   PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___S               0
#define   PHYA_PHYRF_ARB_CTRL_L_B1___M           0x0000FFFF   
#define   PHYA_PHYRF_ARB_CTRL_L_B1___S                         0

#define PHYA_PHYRF_ARB_STATUS_L_B0                (0x00495088)
#define   PHYA_PHYRF_ARB_STATUS_L_B0___RWC          QCSR_REG_RO    
#define   PHYA_PHYRF_ARB_STATUS_L_B0___POR       0x00000000
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___M 0x00010000
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___S              16
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___M 0x0000F000
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___S              12
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___M 0x00000F00
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___S               8
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___M 0x000000F0
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___S               4
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___M 0x0000000F
#define   PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___S               0
#define   PHYA_PHYRF_ARB_STATUS_L_B0___M         0x0001FFFF   
#define   PHYA_PHYRF_ARB_STATUS_L_B0___S                       0

#define PHYA_PHYRF_ARB_STATUS_L_B1                (0x0049D088)
#define   PHYA_PHYRF_ARB_STATUS_L_B1___RWC          QCSR_REG_RO    
#define   PHYA_PHYRF_ARB_STATUS_L_B1___POR       0x00000000
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___POR 0x0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___M 0x00010000
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___S              16
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___M 0x0000F000
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___S              12
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___M 0x00000F00
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___S               8
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___M 0x000000F0
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___S               4
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___M 0x0000000F
#define   PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___S               0
#define   PHYA_PHYRF_ARB_STATUS_L_B1___M         0x0001FFFF   
#define   PHYA_PHYRF_ARB_STATUS_L_B1___S                       0

#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0              (0x00495090)
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0___POR     0x00000000
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___POR 0x00
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___M 0x000000FF
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___S               0
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0___M       0x000000FF   
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B0___S                     0

#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1              (0x0049D090)
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1___POR     0x00000000
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___POR 0x00
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___M 0x000000FF
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___S               0
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1___M       0x000000FF   
#define   PHYA_PHYRF_ARB_CMD_CTRL_L_B1___S                     0

#define PHYA_PHYRF_ARB_DATA_L_B0                  (0x00495098)
#define   PHYA_PHYRF_ARB_DATA_L_B0___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_DATA_L_B0___POR         0x00000000
#define   PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___POR 0x00000
#define   PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___M 0x0003FFFF
#define   PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___S               0
#define   PHYA_PHYRF_ARB_DATA_L_B0___M           0x0003FFFF   
#define   PHYA_PHYRF_ARB_DATA_L_B0___S                         0

#define PHYA_PHYRF_ARB_DATA_L_B1                  (0x0049D098)
#define   PHYA_PHYRF_ARB_DATA_L_B1___RWC            QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_DATA_L_B1___POR         0x00000000
#define   PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___POR 0x00000
#define   PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___M 0x0003FFFF
#define   PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___S               0
#define   PHYA_PHYRF_ARB_DATA_L_B1___M           0x0003FFFF   
#define   PHYA_PHYRF_ARB_DATA_L_B1___S                         0

#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0             (0x004950A0)
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___POR    0x00000000
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___POR 0x0
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___M 0x00000001
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___S               0
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___M      0x00000001   
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___S                    0

#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1             (0x0049D0A0)
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___POR    0x00000000
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___POR 0x0
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___M 0x00000001
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___S               0
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___M      0x00000001   
#define   PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___S                    0

#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0        (0x004950A8)
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___M 0x00000100
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___S               8
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___S               0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___M 0x00000101   
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___S               0

#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1        (0x0049D0A8)
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___M 0x00000100
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___S               8
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___S               0
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___M 0x00000101   
#define   PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___S               0

#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0        (0x004950B0)
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___M 0x00000010
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___S               4
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___M 0x00000008
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___S               3
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___M 0x00000004
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___S               2
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___M 0x00000002
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___S               1
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___S               0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___M 0x0000001F   
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___S               0

#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1        (0x0049D0B0)
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___POR 0x0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___M 0x00000010
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___S               4
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___M 0x00000008
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___S               3
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___M 0x00000004
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___S               2
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___M 0x00000002
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___S               1
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___S               0
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___M 0x0000001F   
#define   PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___S               0

#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0          (0x004950B8)
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___M 0x00E00000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___S              21
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___M 0x001C0000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___S              18
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___M 0x00038000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___S              15
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___M 0x00007000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___S              12
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___M 0x00000E00
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___S               9
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___M 0x000001C0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___S               6
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___M 0x00000038
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___S               3
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___M 0x00000007
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___S               0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___M   0x00FFFFFF   
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___S                 0

#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1          (0x0049D0B8)
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___RWC    QCSR_REG_RO    
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___POR 0x0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___M 0x00E00000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___S              21
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___M 0x001C0000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___S              18
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___M 0x00038000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___S              15
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___M 0x00007000
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___S              12
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___M 0x00000E00
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___S               9
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___M 0x000001C0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___S               6
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___M 0x00000038
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___S               3
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___M 0x00000007
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___S               0
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___M   0x00FFFFFF   
#define   PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___S                 0

#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0       (0x004950C0)
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___POR 0x00
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___M 0x0000003F
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___S               0
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___M 0x0000003F   
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___S               0

#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1       (0x0049D0C0)
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___POR 0x00
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___M 0x0000003F
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___S               0
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___M 0x0000003F   
#define   PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___S               0

#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0       (0x004950C8)
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___M 0x00000080
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___S               7
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___M 0x00000040
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___S               6
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___M 0x00000020
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___S               5
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___M 0x00000010
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___S               4
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___M 0x00000008
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___S               3
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___M 0x00000004
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___S               2
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___M 0x00000002
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___S               1
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___M 0x00000001
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___S               0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___M 0x000000FF   
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___S               0

#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1       (0x0049D0C8)
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___POR 0x0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___M 0x00000080
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___S               7
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___M 0x00000040
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___S               6
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___M 0x00000020
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___S               5
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___M 0x00000010
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___S               4
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___M 0x00000008
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___S               3
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___M 0x00000004
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___S               2
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___M 0x00000002
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___S               1
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___M 0x00000001
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___S               0
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___M 0x000000FF   
#define   PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___S               0

#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0             (0x004950D0)
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___POR    0x00000000
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___POR 0x000
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___M 0x000007FF
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___S               0
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___M      0x000007FF   
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___S                    0

#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1             (0x0049D0D0)
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___POR    0x00000000
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___POR 0x000
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___M 0x000007FF
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___S               0
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___M      0x000007FF   
#define   PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___S                    0

#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0             (0x004950D8)
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___POR    0x00000000
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___POR 0x000
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___M 0x000007FF
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___S               0
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___M      0x000007FF   
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___S                    0

#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1             (0x0049D0D8)
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___POR    0x00000000
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___POR 0x000
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___M 0x000007FF
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___S               0
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___M      0x000007FF   
#define   PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___S                    0

#define PHYA_PHYRF_RFAPB_STATUS_L_B0              (0x004950E0)
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0___POR     0x00000000
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___POR 0x0
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___M 0x00000007
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___S               0
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0___M       0x00000007   
#define   PHYA_PHYRF_RFAPB_STATUS_L_B0___S                     0

#define PHYA_PHYRF_RFAPB_STATUS_L_B1              (0x0049D0E0)
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1___POR     0x00000000
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___POR 0x0
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___M 0x00000007
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___S               0
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1___M       0x00000007   
#define   PHYA_PHYRF_RFAPB_STATUS_L_B1___S                     0

#define PHYA_PHYRF_ERR_CONDS_L_B0                 (0x004950E8)
#define   PHYA_PHYRF_ERR_CONDS_L_B0___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_ERR_CONDS_L_B0___POR        0x00000000
#define   PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___POR 0x0
#define   PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___M 0x00000001
#define   PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___S               0
#define   PHYA_PHYRF_ERR_CONDS_L_B0___M          0x00000001   
#define   PHYA_PHYRF_ERR_CONDS_L_B0___S                        0

#define PHYA_PHYRF_ERR_CONDS_L_B1                 (0x0049D0E8)
#define   PHYA_PHYRF_ERR_CONDS_L_B1___RWC           QCSR_REG_RW    
#define   PHYA_PHYRF_ERR_CONDS_L_B1___POR        0x00000000
#define   PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___POR 0x0
#define   PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___M 0x00000001
#define   PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___S               0
#define   PHYA_PHYRF_ERR_CONDS_L_B1___M          0x00000001   
#define   PHYA_PHYRF_ERR_CONDS_L_B1___S                        0

#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0            (0x004950F0)
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___POR   0x00000000
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___POR 0x000
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___M 0x000007FF
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___S               0
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___M     0x000007FF   
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___S                   0

#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1            (0x0049D0F0)
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___POR   0x00000000
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___POR 0x000
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___M 0x000007FF
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___S               0
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___M     0x000007FF   
#define   PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___S                   0

#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0             (0x004950F8)
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___POR    0x00000000
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___M      0x0000FFFF   
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___S                    0

#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1             (0x0049D0F8)
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___POR    0x00000000
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___M      0x0000FFFF   
#define   PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___S                    0

#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0             (0x00495100)
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___POR    0x00000000
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___M      0x0000FFFF   
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___S                    0

#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1             (0x0049D100)
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___POR    0x00000000
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___M      0x0000FFFF   
#define   PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___S                    0

#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0            (0x00495108)
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___POR   0x00000000
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___M     0x0000FFFF   
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___S                   0

#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1            (0x0049D108)
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___POR   0x00000000
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___S               0
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___M     0x0000FFFF   
#define   PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___S                   0

#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0             (0x00495110)
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___POR    0x00000000
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___S               0
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___M      0x0000FFFF   
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___S                    0

#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1             (0x0049D110)
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___RWC       QCSR_REG_RW    
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___POR    0x00000000
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___POR 0x0000
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___S               0
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___M      0x0000FFFF   
#define   PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___S                    0

#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0            (0x00495118)
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___POR   0x00000000
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___M 0x00010000
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___S              16
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___M 0x00000100
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___S               8
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___M 0x00000001
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___S               0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___M     0x00010101   
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___S                   0

#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1            (0x0049D118)
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___POR   0x00000000
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___POR 0x0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___M 0x00010000
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___S              16
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___M 0x00000100
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___S               8
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___M 0x00000001
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___S               0
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___M     0x00010101   
#define   PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___S                   0

#define PHYA_PHYRF_RF_REG_CMD_L_B0                (0x00495120)
#define   PHYA_PHYRF_RF_REG_CMD_L_B0___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_CMD_L_B0___POR       0x00000000
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___M 0x00000100
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___S               8
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___M 0x00000001
#define   PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___S               0
#define   PHYA_PHYRF_RF_REG_CMD_L_B0___M         0x00000101   
#define   PHYA_PHYRF_RF_REG_CMD_L_B0___S                       0

#define PHYA_PHYRF_RF_REG_CMD_L_B1                (0x0049D120)
#define   PHYA_PHYRF_RF_REG_CMD_L_B1___RWC          QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_CMD_L_B1___POR       0x00000000
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___M 0x00000100
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___S               8
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___M 0x00000001
#define   PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___S               0
#define   PHYA_PHYRF_RF_REG_CMD_L_B1___M         0x00000101   
#define   PHYA_PHYRF_RF_REG_CMD_L_B1___S                       0

#define PHYA_PHYRF_RF_REG_ADDR_L_B0               (0x00495128)
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0___POR      0x00000000
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___POR 0x0000
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___M 0x0000FFFF
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___S               0
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0___M        0x0000FFFF   
#define   PHYA_PHYRF_RF_REG_ADDR_L_B0___S                      0

#define PHYA_PHYRF_RF_REG_ADDR_L_B1               (0x0049D128)
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1___RWC         QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1___POR      0x00000000
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___POR 0x0000
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___M 0x0000FFFF
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___S               0
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1___M        0x0000FFFF   
#define   PHYA_PHYRF_RF_REG_ADDR_L_B1___S                      0

#define PHYA_PHYRF_RF_REG_WDATA_L_B0              (0x00495130)
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0___POR     0x00000000
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___S               0
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0___M       0xFFFFFFFF   
#define   PHYA_PHYRF_RF_REG_WDATA_L_B0___S                     0

#define PHYA_PHYRF_RF_REG_WDATA_L_B1              (0x0049D130)
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1___RWC        QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1___POR     0x00000000
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___S               0
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1___M       0xFFFFFFFF   
#define   PHYA_PHYRF_RF_REG_WDATA_L_B1___S                     0

#define PHYA_PHYRF_RF_REG_RDATA_L_B0              (0x00495138)
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0___POR     0x00000000
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___S               0
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0___M       0xFFFFFFFF   
#define   PHYA_PHYRF_RF_REG_RDATA_L_B0___S                     0

#define PHYA_PHYRF_RF_REG_RDATA_L_B1              (0x0049D138)
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1___RWC        QCSR_REG_RO    
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1___POR     0x00000000
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___M 0xFFFFFFFF
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___S               0
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1___M       0xFFFFFFFF   
#define   PHYA_PHYRF_RF_REG_RDATA_L_B1___S                     0

#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0          (0x00495140)
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___M 0x00000001
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___S               0
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___M   0x00000001   
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___S                 0

#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1          (0x0049D140)
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___POR 0x0
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___M 0x00000001
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___S               0
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___M   0x00000001   
#define   PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___S                 0

#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0        (0x00495148)
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___S               0

#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1        (0x0049D148)
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___S               0

#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0        (0x00495150)
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___S               0

#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1        (0x0049D150)
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___S               0

#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0           (0x00495158)
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___S                  0

#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1           (0x0049D158)
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___S                  0

#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0        (0x00495160)
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___S               0

#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1        (0x0049D160)
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___RWC  QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___S               0

#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0          (0x00495168)
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___S                 0

#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1          (0x0049D168)
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___S                 0

#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0          (0x00495170)
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___S                 0

#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1          (0x0049D170)
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___S                 0

#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0            (0x00495178)
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0___POR   0x00000000
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0___M     0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B0___S                   0

#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1            (0x0049D178)
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1___RWC      QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1___POR   0x00000000
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1___M     0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_MODE_L_B1___S                   0

#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0           (0x00495180)
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___S                  0

#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1           (0x0049D180)
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___S                  0

#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0           (0x00495188)
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___S                  0

#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1           (0x0049D188)
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___S                  0

#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0           (0x00495190)
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___S                  0

#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1           (0x0049D190)
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___S                  0

#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0          (0x00495198)
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___S                 0

#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1          (0x0049D198)
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___RWC    QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___POR 0x00000000
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___M   0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___S                 0

#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0           (0x004951A0)
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___S                  0

#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1           (0x0049D1A0)
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___RWC     QCSR_REG_RW    
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___POR  0x00000000
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___POR 0x0000
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___M 0x0000FFFF
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___S               0
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___M    0x0000FFFF   
#define   PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___S                  0

#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0  (0x004951A8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___POR 0x000003FF
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___M 0x00000200
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___S               9
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___M 0x00000100
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___S               8
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___M 0x00000080
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___S               7
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___M 0x00000040
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___S               6
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___M 0x00000020
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___S               5
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___M 0x00000010
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___S               4
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___M 0x00000008
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___S               3
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___M 0x00000004
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___S               2
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___M 0x00000002
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___S               1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___M 0x00000001
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___M 0x000003FF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1  (0x0049D1A8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___POR 0x000003FF
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___POR 0x1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___M 0x00000200
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___S               9
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___M 0x00000100
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___S               8
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___M 0x00000080
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___S               7
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___M 0x00000040
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___S               6
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___M 0x00000020
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___S               5
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___M 0x00000010
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___S               4
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___M 0x00000008
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___S               3
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___M 0x00000004
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___S               2
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___M 0x00000002
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___S               1
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___M 0x00000001
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___M 0x000003FF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0 (0x004951B0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1 (0x0049D1B0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0 (0x004951B8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1 (0x0049D1B8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0 (0x004951C0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1 (0x0049D1C0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0 (0x004951C8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1 (0x0049D1C8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0 (0x004951D0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1 (0x0049D1D0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0 (0x004951D8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1 (0x0049D1D8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0 (0x004951E0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1 (0x0049D1E0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0 (0x004951E8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1 (0x0049D1E8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0 (0x004951F0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1 (0x0049D1F0)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0 (0x004951F8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___S               0

#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1 (0x0049D1F8)
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___POR 0x00000000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___POR 0x0000
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___M 0x0000FFFF
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___S               0
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___M 0x0000FFFF   
#define   PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___S               0

#define PHYA_PHYRF_CMD_CAPTURE_L_B0               (0x00495200)
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0___RWC         QCSR_REG_RO    
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0___POR      0x00000F0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___POR 0x0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___POR 0x0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___M 0x00001F00
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___S               8
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___M 0x0000001F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___S               0
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0___M        0x00001F1F   
#define   PHYA_PHYRF_CMD_CAPTURE_L_B0___S                      0

#define PHYA_PHYRF_CMD_CAPTURE_L_B1               (0x0049D200)
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1___RWC         QCSR_REG_RO    
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1___POR      0x00000F0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___POR 0x0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___POR 0x0F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___M 0x00001F00
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___S               8
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___M 0x0000001F
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___S               0
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1___M        0x00001F1F   
#define   PHYA_PHYRF_CMD_CAPTURE_L_B1___S                      0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0  (0x00495208)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___POR 0x00000001
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___POR 0x1
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___M 0x01000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___S              24
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___M 0x00010000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___S              16
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___M 0x00000100
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___S               8
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___M 0x01010101   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1  (0x0049D208)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___POR 0x00000001
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___POR 0x1
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___M 0x01000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___S              24
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___M 0x00010000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___S              16
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___M 0x00000100
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___S               8
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___M 0x00000001
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___M 0x01010101   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0  (0x00495210)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___M 0x00100000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___S              20
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___M 0x00080000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___S              19
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___M 0x00040000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___S              18
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___M 0x0003F000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___M 0x00000FC0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___M 0x0000003F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___M 0x001FFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1  (0x0049D210)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___POR 0x00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___M 0x00100000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___S              20
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___M 0x00080000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___S              19
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___M 0x00040000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___S              18
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___M 0x0003F000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___M 0x00000FC0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___M 0x0000003F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___M 0x001FFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n(n) (0x00495218+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___POR 0x0000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S               4
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0 (0x00495218)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S               4
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n(n) (0x0049D218+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___POR 0x0000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S               4
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0 (0x0049D218)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S               4
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n(n) (0x00495220+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___POR 0x00000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0 (0x00495220)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n(n) (0x0049D220+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___POR 0x00000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0 (0x0049D220)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n(n) (0x00495228+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___POR 0x00000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S              15
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0 (0x00495228)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S              15
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S               0

#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n(n) (0x0049D228+0x8*(n))
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___POR 0x00000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___POR 0x0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S              15
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S               0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___S               0
#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0 (0x0049D228)
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S              15
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S              12
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S               9
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S               6
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S               3
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007
#define   PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S               0

#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n(n) (0x00495230+0x8*(n))
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_nMIN 0    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_nMAX 0    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_ELEM 1    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___POR 0x00000000
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___POR 0x00000000
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___S               0
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___S               0
#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0 (0x00495230)
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0__POST_WSI_WRITE_DEBUG_BUS___S               0

#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n(n) (0x0049D230+0x8*(n))
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_nMIN 0    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_nMAX 0    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_ELEM 1    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___POR 0x00000000
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___POR 0x00000000
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___S               0
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___M 0xFFFFFFFF   
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___S               0
#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0 (0x0049D230)
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0___RWC QCSR_REG_RO    
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF
#define   PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0__POST_WSI_WRITE_DEBUG_BUS___S               0

#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0      (0x00495238)
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___S               0

#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1      (0x0049D238)
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___S               0

#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0      (0x0049523C)
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___S               0

#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1      (0x0049D23C)
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___S               0

#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0 (0x00495240)
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___S               0
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___S               0

#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1 (0x0049D240)
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___S               0
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___S               0

#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0     (0x00495248)
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___S               0

#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1     (0x0049D248)
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___S               0
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___S               0

#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0     (0x0049524C)
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___S               0

#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1     (0x0049D24C)
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___RWC QCSR_REG_RW    
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___S               0
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___M 0xFFFFFFFF   
#define   PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___S               0

#define PHYA_ROBE_PMI_RESET_CTRL_L                (0x004B0000)
#define   PHYA_ROBE_PMI_RESET_CTRL_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_PMI_RESET_CTRL_L___POR       0x00000000
#define   PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___POR 0x0
#define   PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___POR 0x0
#define   PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___POR 0x0
#define   PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___M 0x00000004
#define   PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___S               2
#define   PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___M 0x00000002
#define   PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___S               1
#define   PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___M 0x00000001
#define   PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___S               0
#define   PHYA_ROBE_PMI_RESET_CTRL_L___M         0x00000007   
#define   PHYA_ROBE_PMI_RESET_CTRL_L___S                       0

#define PHYA_ROBE_PMI_CTRL_L                      (0x004B0008)
#define   PHYA_ROBE_PMI_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CTRL_L___POR             0x00000000
#define   PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___POR 0x00000000
#define   PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___S               0
#define   PHYA_ROBE_PMI_CTRL_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CTRL_L___S                             0

#define PHYA_ROBE_PMI_CFG_L                       (0x004B0010)
#define   PHYA_ROBE_PMI_CFG_L___RWC                 QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CFG_L___POR              0x00000000
#define   PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___POR 0x00000000
#define   PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___M   0xFFFFFFFF
#define   PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___S                 0
#define   PHYA_ROBE_PMI_CFG_L___M                0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CFG_L___S                              0

#define PHYA_ROBE_PMI_STAT_L                      (0x004B0018)
#define   PHYA_ROBE_PMI_STAT_L___RWC                QCSR_REG_RO    
#define   PHYA_ROBE_PMI_STAT_L___POR             0x00000000
#define   PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___POR 0x00000000
#define   PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___S               0
#define   PHYA_ROBE_PMI_STAT_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_PMI_STAT_L___S                             0

#define PHYA_ROBE_PMI_EVENT_STATUS_L              (0x004B0020)
#define   PHYA_ROBE_PMI_EVENT_STATUS_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_PMI_EVENT_STATUS_L___POR     0x00000000
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___M 0x00000020
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___S               5
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___M 0x00000010
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___S               4
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___M 0x00000008
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___S               3
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___M 0x00000004
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___S               2
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___M 0x00000002
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___S               1
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___M 0x00000001
#define   PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___S               0
#define   PHYA_ROBE_PMI_EVENT_STATUS_L___M       0x0000003F   
#define   PHYA_ROBE_PMI_EVENT_STATUS_L___S                     0

#define PHYA_ROBE_PMI_EVENT_MASK_L                (0x004B0028)
#define   PHYA_ROBE_PMI_EVENT_MASK_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_PMI_EVENT_MASK_L___POR       0x0000003F
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___M 0x00000020
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___S               5
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___M 0x00000010
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___S               4
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___M 0x00000008
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___S               3
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___M 0x00000004
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___S               2
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___M 0x00000002
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___S               1
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___S               0
#define   PHYA_ROBE_PMI_EVENT_MASK_L___M         0x0000003F   
#define   PHYA_ROBE_PMI_EVENT_MASK_L___S                       0

#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L     (0x004B0030)
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___RWC QCSR_REG_RO    
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___POR 0x00000000
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___POR 0x0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___M 0x00000800
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___S              11
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___M 0x00000400
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___S              10
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___M 0x00000200
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___S               9
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___M 0x00000100
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___S               8
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___M 0x00000080
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___S               7
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___M 0x00000040
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___S               6
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___M 0x00000020
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___S               5
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___M 0x00000010
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___S               4
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___M 0x00000008
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___S               3
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___M 0x00000004
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___S               2
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___M 0x00000002
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___S               1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___M 0x00000001
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___S               0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___M 0x00000FFF   
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___S               0

#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L     (0x004B0038)
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___POR 0x00000FFF
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___POR 0x1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___M 0x00000800
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___S              11
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___M 0x00000400
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___S              10
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___M 0x00000200
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___S               9
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___M 0x00000100
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___S               8
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___M 0x00000080
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___S               7
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___M 0x00000040
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___S               6
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___M 0x00000020
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___S               5
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___M 0x00000010
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___S               4
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___M 0x00000008
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___S               3
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___M 0x00000004
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___S               2
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___M 0x00000002
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___S               1
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___M 0x00000001
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___S               0
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___M 0x00000FFF   
#define   PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___S               0

#define PHYA_ROBE_PMI_CODE_L                      (0x004B0040)
#define   PHYA_ROBE_PMI_CODE_L___RWC                QCSR_REG_RO    
#define   PHYA_ROBE_PMI_CODE_L___POR             0x00000100
#define   PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___POR 0x1
#define   PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___POR 0x00
#define   PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___M 0x00000100
#define   PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___S               8
#define   PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___M 0x0000001F
#define   PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___S               0
#define   PHYA_ROBE_PMI_CODE_L___M               0x0000011F   
#define   PHYA_ROBE_PMI_CODE_L___S                             0

#define PHYA_ROBE_PMI_INFO_L                      (0x004B0048)
#define   PHYA_ROBE_PMI_INFO_L___RWC                QCSR_REG_RO    
#define   PHYA_ROBE_PMI_INFO_L___POR             0x00000000
#define   PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___POR 0x00000000
#define   PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___S               0
#define   PHYA_ROBE_PMI_INFO_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_PMI_INFO_L___S                             0

#define PHYA_ROBE_PMI_STATUS_L                    (0x004B0050)
#define   PHYA_ROBE_PMI_STATUS_L___RWC              QCSR_REG_RW    
#define   PHYA_ROBE_PMI_STATUS_L___POR           0x00000000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___POR 0x0
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___M 0x00040000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___S              18
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___M 0x00020000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___S              17
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___M 0x00010000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___S              16
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___M 0x00008000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___S              15
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___M 0x00004000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___S              14
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___M 0x00002000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___S              13
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___M 0x00001000
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___S              12
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___M 0x00000800
#define   PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___S              11
#define   PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___M 0x00000400
#define   PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___S              10
#define   PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___M 0x00000200
#define   PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___S               9
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___M 0x00000100
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___S               8
#define   PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___M 0x00000080
#define   PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___S               7
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___M 0x00000040
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___S               6
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___M 0x00000020
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___S               5
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___M 0x00000010
#define   PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___S               4
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___M 0x00000008
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___S               3
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___M 0x00000004
#define   PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___S               2
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___M 0x00000002
#define   PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___S               1
#define   PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___M 0x00000001
#define   PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___S               0
#define   PHYA_ROBE_PMI_STATUS_L___M             0x0007FFFF   
#define   PHYA_ROBE_PMI_STATUS_L___S                           0

#define PHYA_ROBE_PMI_MASK_L                      (0x004B0058)
#define   PHYA_ROBE_PMI_MASK_L___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_PMI_MASK_L___POR             0x0007FFFF
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___M 0x00040000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___S              18
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___M 0x00020000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___S              17
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___M 0x00010000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___S              16
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___M 0x00008000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___S              15
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___M 0x00004000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___S              14
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___M 0x00002000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___S              13
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___M 0x00001000
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___S              12
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___M 0x00000800
#define   PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___S              11
#define   PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___M 0x00000400
#define   PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___S              10
#define   PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___M 0x00000200
#define   PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___S               9
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___M 0x00000100
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___S               8
#define   PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___M 0x00000080
#define   PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___S               7
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___M 0x00000040
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___S               6
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___M 0x00000020
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___S               5
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___M 0x00000010
#define   PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___S               4
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___M 0x00000008
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___S               3
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___M 0x00000004
#define   PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___S               2
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___M 0x00000002
#define   PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___S               1
#define   PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___M 0x00000001
#define   PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___S               0
#define   PHYA_ROBE_PMI_MASK_L___M               0x0007FFFF   
#define   PHYA_ROBE_PMI_MASK_L___S                             0

#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n(n) (0x004B0060+0x8*(n))
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_nMIN 0    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_nMAX 0    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_ELEM 1    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___RWC QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___POR 0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___POR 0x0000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___POR 0x0
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___POR 0x0
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___M 0xFFFF0000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___S              16
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___M 0x00000300
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___S               8
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___M 0x00000003
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___S               0
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___M 0xFFFF0303   
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___S               0
#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0       (0x004B0060)
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0___RWC QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_DWORDS_RECEIVED___M 0xFFFF0000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_DWORDS_RECEIVED___S              16
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_END_FLAG___M 0x00000300
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_END_FLAG___S               8
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_TAG_FLAG___M 0x00000003
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_TAG_FLAG___S               0

#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U         (0x004B0064)
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___RWC   QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___POR 0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___POR 0x0000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___M 0x00010000
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___S              16
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___M 0x0000FFFF
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___S               0
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___M  0x0001FFFF   
#define   PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___S                0

#define PHYA_ROBE_PMI_IP_LAST_TAG_L               (0x004B0068)
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L___POR      0x00000000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___POR 0x000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___POR 0x000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___M 0x01FF0000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___S              16
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___M 0x000001FF
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___S               0
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L___M        0x01FF01FF   
#define   PHYA_ROBE_PMI_IP_LAST_TAG_L___S                      0

#define PHYA_ROBE_PMI_IP_LAST_TAG_U               (0x004B006C)
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U___POR      0x00000000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___POR 0x000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___POR 0x000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___M 0x01FF0000
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___S              16
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___M 0x000001FF
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___S               0
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U___M        0x01FF01FF   
#define   PHYA_ROBE_PMI_IP_LAST_TAG_U___S                      0

#define PHYA_ROBE_PMI_OP_TLV_STATUS_L             (0x004B0070)
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L___RWC       QCSR_REG_RO    
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L___POR    0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___POR 0x0000
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___POR 0x0000
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___M 0xFFFF0000
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___S              16
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___M 0x0000FFFF
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___S               0
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L___M      0xFFFFFFFF   
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_L___S                    0

#define PHYA_ROBE_PMI_OP_TLV_STATUS_U             (0x004B0074)
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U___RWC       QCSR_REG_RO    
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U___POR    0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___M 0x00000001
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___S               0
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U___M      0x00000001   
#define   PHYA_ROBE_PMI_OP_TLV_STATUS_U___S                    0

#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L            (0x004B0078)
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L___RWC      QCSR_REG_RO    
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L___POR   0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___POR 0x000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___POR 0x000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___M 0x01FF0000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___S              16
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___M 0x000001FF
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___S               0
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L___M     0x01FF01FF   
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_L___S                   0

#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U            (0x004B007C)
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U___RWC      QCSR_REG_RO    
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U___POR   0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___POR 0x000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___POR 0x000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___M 0x01FF0000
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___S              16
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___M 0x000001FF
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___S               0
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U___M     0x01FF01FF   
#define   PHYA_ROBE_PMI_OP_TLV_HISTORY_U___S                   0

#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L          (0x004B0080)
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___POR 0x0
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___M 0x00000003
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___S               0
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___M   0x00000003   
#define   PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___S                 0

#define PHYA_ROBE_PMI_DEBUG_STATE_L               (0x004B0088)
#define   PHYA_ROBE_PMI_DEBUG_STATE_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_PMI_DEBUG_STATE_L___POR      0x00000000
#define   PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___POR 0x00000000
#define   PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___S               0
#define   PHYA_ROBE_PMI_DEBUG_STATE_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_PMI_DEBUG_STATE_L___S                      0

#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L       (0x004B0090)
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___POR 0x000001FF
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___POR 0x0000
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___POR 0x1FF
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___M 0xFFFF0000
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___S              16
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___M 0x000001FF
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___S               0
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___M 0xFFFF01FF   
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___S               0

#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L       (0x004B0098)
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___RWC QCSR_REG_RO    
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___POR 0x000
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___M 0x00000FFF
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___S               0
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___M 0x00000FFF   
#define   PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___S               0

#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L         (0x004B00A0)
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___POR 0x0
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___POR 0x00
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___M 0x00000100
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___S               8
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___M 0x000000FF
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___S               0
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___M  0x000001FF   
#define   PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___S                0

#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L           (0x004B00A8)
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___RWC     QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___POR  0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___S               0
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___M    0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___S                  0

#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U           (0x004B00AC)
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___RWC     QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___POR  0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___S               0
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___M    0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___S                  0

#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L          (0x004B00B0)
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___S               0
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___S                 0

#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U          (0x004B00B4)
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___S               0
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___S                 0

#define PHYA_ROBE_PMI_CRC_CHK_CFG_L               (0x004B00B8)
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L___POR      0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___POR 0x00
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___M 0x3F000000
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___S              24
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___M 0x00030000
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___S              16
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___M 0x00000100
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___S               8
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___M 0x00000001
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L___M        0x3F030101   
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_L___S                      0

#define PHYA_ROBE_PMI_CRC_CHK_CFG_U               (0x004B00BC)
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U___POR      0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CRC_CHK_CFG_U___S                      0

#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L         (0x004B00C0)
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___POR 0x0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___M 0xFFFF0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___S              16
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___M 0x00000001
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___M  0xFFFF0001   
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___S                0

#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U         (0x004B00C4)
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___POR 0x0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___POR 0x0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___M 0xFFFF0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___S              16
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___M 0x0000FFFF
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___S                0

#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L         (0x004B00C8)
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___POR 0x0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___POR 0x0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___M 0xFFFF0000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___S              16
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___M 0x0000FFFF
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___S                0

#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U         (0x004B00CC)
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___M 0x00000003
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___M  0x00000003   
#define   PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___S                0

#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L          (0x004B00D0)
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___S               0
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___S                 0

#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U          (0x004B00D4)
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___S               0
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___S                 0

#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L         (0x004B00D8)
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___S               0
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___S                0

#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U         (0x004B00DC)
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___RWC   QCSR_REG_RW    
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___S               0
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___S                0

#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L             (0x004B00E0)
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L___RWC       QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L___POR    0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___POR 0x0000
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___M 0x0000FFFF
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___S               0
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L___M      0x0000FFFF   
#define   PHYA_ROBE_PMI_IP_TLV_LENGTH_L___S                    0

#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n(n) (0x004B00E8+0x8*(n))
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n___RWC       QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n___POR    0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___POR 0x0000
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___POR 0x0000
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___M 0xFFFF0000
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___S              16
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___M 0x0000FFFF
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___S               0
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n___M      0xFFFFFFFF   
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_n___S                    0
#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0             (0x004B00E8)
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_0___RWC       QCSR_REG_RO    
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_1___M 0xFFFF0000
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_1___S              16
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_0___M 0x0000FFFF
#define   PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_0___S               0

#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L           (0x004B00F0)
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___RWC     QCSR_REG_RW    
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___POR  0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___S               0
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___M    0xFFFFFFFF   
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___S                  0

#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U           (0x004B00F4)
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___RWC     QCSR_REG_RW    
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___POR  0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___S               0
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___M    0xFFFFFFFF   
#define   PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___S                  0

#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n(n) (0x004B00F8+0x8*(n))
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_nMIN 0    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_nMAX 0    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_ELEM 1    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___RWC   QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___S               0
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___S                0
#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0         (0x004B00F8)
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0___RWC   QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0__OP_TLV_DATA_NCF_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0__OP_TLV_DATA_NCF_0___S               0

#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n(n) (0x004B00FC+0x8*(n))
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_nMIN 0    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_nMAX 0    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_ELEM 1    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___RWC   QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___S               0
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___M  0xFFFFFFFF   
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___S                0
#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0         (0x004B00FC)
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0___RWC   QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0__OP_TLV_DATA_NCF_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0__OP_TLV_DATA_NCF_1___S               0

#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n(n) (0x004B0118+0x8*(n))
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___RWC    QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___S               0
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___S                 0
#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0          (0x004B0118)
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0___RWC    QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0__OP_TLV_DATA_CF_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0__OP_TLV_DATA_CF_0___S               0

#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n(n) (0x004B011C+0x8*(n))
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_nMIN 0    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_nMAX 0    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_ELEM 1    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___RWC    QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___POR 0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___S               0
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___M   0xFFFFFFFF   
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___S                 0
#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0          (0x004B011C)
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0___RWC    QCSR_REG_WO    
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0__OP_TLV_DATA_CF_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0__OP_TLV_DATA_CF_1___S               0

#define PHYA_ROBE_PMI_OP_TLV_CFG_L                (0x004B0138)
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L___POR       0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___M 0x01000000
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___S              24
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___M 0x000F0000
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___S              16
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___M 0x00000100
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___S               8
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___M 0x00000001
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___S               0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L___M         0x010F0101   
#define   PHYA_ROBE_PMI_OP_TLV_CFG_L___S                       0

#define PHYA_ROBE_PMI_OP_TLV_CFG_U                (0x004B013C)
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U___POR       0x00000003
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___POR 0x3
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___M 0x07000000
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___S              24
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___M 0x00010000
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___S              16
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___M 0x00000100
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___S               8
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___M 0x00000003
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___S               0
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U___M         0x07010103   
#define   PHYA_ROBE_PMI_OP_TLV_CFG_U___S                       0

#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L             (0x004B0140)
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L___POR    0x00000000
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___POR 0x00
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___POR 0x0
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___M 0x00003F00
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___S               8
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___M 0x00000007
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___S               0
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L___M      0x00003F07   
#define   PHYA_ROBE_PMI_OP_TLV_PARAMS_L___S                    0

#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n(n) (0x004B0148+0x8*(n))
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___RWC      QCSR_REG_WO    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___POR   0x00000000
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___POR 0x00000000
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___S               0
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___M     0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___S                   0
#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_0            (0x004B0148)
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_0___RWC      QCSR_REG_WO    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_0__CBF_DMA_DATA_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_L_0__CBF_DMA_DATA_0___S               0

#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n(n) (0x004B014C+0x8*(n))
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_nMIN 0    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_nMAX 0    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_ELEM 1    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___RWC      QCSR_REG_WO    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___POR   0x00000000
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___POR 0x00000000
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___S               0
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___M     0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___S                   0
#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_0            (0x004B014C)
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_0___RWC      QCSR_REG_WO    
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_0__CBF_DMA_DATA_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CBF_DMA_DATA_U_0__CBF_DMA_DATA_1___S               0

#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L       (0x004B0168)
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___POR 0x00080400
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___POR 0x08
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___POR 0x0400
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___M 0x00FF0000
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___S              16
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___M 0x00003FFF
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___S               0
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___M 0x00FF3FFF   
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___S               0

#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U       (0x004B016C)
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___RWC QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___POR 0x00000000
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___POR 0x00
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___POR 0x0000
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___M 0x01000000
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___S              24
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___M 0x003F0000
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___S              16
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___M 0x00003FFF
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___S               0
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___M 0x013F3FFF   
#define   PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___S               0

#define PHYA_ROBE_PMI_CBF_CONTROLS_L              (0x004B0170)
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L___POR     0x00000000
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___POR 0x0
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___POR 0x0
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___M 0x00000002
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___S               1
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___M 0x00000001
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___S               0
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L___M       0x00000003   
#define   PHYA_ROBE_PMI_CBF_CONTROLS_L___S                     0

#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L            (0x004B0178)
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___RWC      QCSR_REG_RO    
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___POR   0x00000000
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___POR 0x0000
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___M 0x00003FFF
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___S               0
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___M     0x00003FFF   
#define   PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___S                   0

#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L        (0x004B0180)
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___M 0xFFFFFFFF
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___S               0

#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U        (0x004B0184)
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___POR 0x00000000
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___POR 0x0
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___M 0x00010000
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___S              16
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___M 0x00000100
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___S               8
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___M 0x00000001
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___S               0
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___M 0x00010101   
#define   PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___S               0

#define PHYA_ROBE_ECO_CTRL_L                      (0x004B0188)
#define   PHYA_ROBE_ECO_CTRL_L___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_ECO_CTRL_L___POR             0x00000000
#define   PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___POR   0x00000000
#define   PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___M     0xFFFFFFFF
#define   PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___S                   0
#define   PHYA_ROBE_ECO_CTRL_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_ECO_CTRL_L___S                             0

#define PHYA_ROBE_ECO_CTRL_U                      (0x004B018C)
#define   PHYA_ROBE_ECO_CTRL_U___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_ECO_CTRL_U___POR             0x00000000
#define   PHYA_ROBE_ECO_CTRL_U__ECO_CFG___POR    0x00000000
#define   PHYA_ROBE_ECO_CTRL_U__ECO_CFG___M      0xFFFFFFFF
#define   PHYA_ROBE_ECO_CTRL_U__ECO_CFG___S                    0
#define   PHYA_ROBE_ECO_CTRL_U___M               0xFFFFFFFF   
#define   PHYA_ROBE_ECO_CTRL_U___S                             0

#define PHYA_ROBE_ECO_STAT_L                      (0x004B0190)
#define   PHYA_ROBE_ECO_STAT_L___RWC                QCSR_REG_RO    
#define   PHYA_ROBE_ECO_STAT_L___POR             0x00000000
#define   PHYA_ROBE_ECO_STAT_L__ECO_STAT___POR   0x00000000
#define   PHYA_ROBE_ECO_STAT_L__ECO_STAT___M     0xFFFFFFFF
#define   PHYA_ROBE_ECO_STAT_L__ECO_STAT___S                   0
#define   PHYA_ROBE_ECO_STAT_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_ECO_STAT_L___S                             0

#define PHYA_ROBE_EVENT_STATUS_L                  (0x004B0198)
#define   PHYA_ROBE_EVENT_STATUS_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_EVENT_STATUS_L___POR         0x00000004
#define   PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___POR 0x1
#define   PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___M 0x00000040
#define   PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___S               6
#define   PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___M 0x00000020
#define   PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___S               5
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___M 0x00000010
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___S               4
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___M 0x00000008
#define   PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___S               3
#define   PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___M 0x00000004
#define   PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___S               2
#define   PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_ROBE_EVENT_STATUS_L___M           0x0000007F   
#define   PHYA_ROBE_EVENT_STATUS_L___S                         0

#define PHYA_ROBE_EVENT_MASK_L                    (0x004B01A0)
#define   PHYA_ROBE_EVENT_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_ROBE_EVENT_MASK_L___POR           0x0000007F
#define   PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___M 0x00000040
#define   PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___S               6
#define   PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___M 0x00000020
#define   PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___S               5
#define   PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___M 0x00000010
#define   PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___S               4
#define   PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___M 0x00000008
#define   PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___S               3
#define   PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___M 0x00000004
#define   PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___S               2
#define   PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_ROBE_EVENT_MASK_L___M             0x0000007F   
#define   PHYA_ROBE_EVENT_MASK_L___S                           0

#define PHYA_ROBE_ERROR_CODE_L                    (0x004B01A8)
#define   PHYA_ROBE_ERROR_CODE_L___RWC              QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_CODE_L___POR           0x00000000
#define   PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___POR 0x00
#define   PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___M 0x0000003F
#define   PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___S               0
#define   PHYA_ROBE_ERROR_CODE_L___M             0x0000003F   
#define   PHYA_ROBE_ERROR_CODE_L___S                           0

#define PHYA_ROBE_ERROR_INFO_L                    (0x004B01B0)
#define   PHYA_ROBE_ERROR_INFO_L___RWC              QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_INFO_L___POR           0x00000000
#define   PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___POR 0x00000000
#define   PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___M 0xFFFFFFFF
#define   PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___S               0
#define   PHYA_ROBE_ERROR_INFO_L___M             0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_INFO_L___S                           0

#define PHYA_ROBE_ERROR_STATUS_L                  (0x004B01B8)
#define   PHYA_ROBE_ERROR_STATUS_L___RWC            QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_STATUS_L___POR         0x00000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___M 0x80000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___S              31
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___M 0x40000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___S              30
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___M 0x20000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___S              29
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___M 0x10000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___S              28
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___M 0x08000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___S              27
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___M 0x04000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___S              26
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___M 0x02000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___S              25
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___M 0x01000000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___S              24
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___M 0x00800000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___S              23
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___M 0x00400000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___S              22
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___M 0x00200000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___S              21
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___M 0x00100000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___S              20
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___M 0x00080000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___S              19
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___M 0x00040000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___S              18
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___M 0x00020000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___S              17
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___M 0x00010000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___S              16
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___M 0x00008000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___S              15
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___M 0x00004000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___S              14
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___M 0x00002000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___S              13
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___M 0x00001000
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___S              12
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___M 0x00000800
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___S              11
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___M 0x00000400
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___S              10
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___M 0x00000200
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___S               9
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___M 0x00000100
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___S               8
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___M 0x00000080
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___S               7
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___M 0x00000040
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___S               6
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___M 0x00000020
#define   PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___S               5
#define   PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___M 0x00000010
#define   PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___S               4
#define   PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___M 0x00000008
#define   PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___S               3
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___M 0x00000004
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___S               2
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___M 0x00000002
#define   PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___S               1
#define   PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___M 0x00000001
#define   PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___S               0
#define   PHYA_ROBE_ERROR_STATUS_L___M           0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_STATUS_L___S                         0

#define PHYA_ROBE_ERROR_MASK_L                    (0x004B01C0)
#define   PHYA_ROBE_ERROR_MASK_L___RWC              QCSR_REG_RW    
#define   PHYA_ROBE_ERROR_MASK_L___POR           0xFFFFFFFF
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___M 0x80000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___S              31
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___M 0x40000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___S              30
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___M 0x20000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___S              29
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___M 0x10000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___S              28
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___M 0x08000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___S              27
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___M 0x04000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___S              26
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___M 0x02000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___S              25
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___M 0x01000000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___S              24
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___M 0x00800000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___S              23
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___M 0x00400000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___S              22
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___M 0x00200000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___S              21
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___M 0x00100000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___S              20
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___M 0x00080000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___S              19
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___M 0x00040000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___S              18
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___M 0x00020000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___S              17
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___M 0x00010000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___S              16
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___M 0x00008000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___S              15
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___M 0x00004000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___S              14
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___M 0x00002000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___S              13
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___M 0x00001000
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___S              12
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___M 0x00000800
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___S              11
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___M 0x00000400
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___S              10
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___M 0x00000200
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___S               9
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___M 0x00000100
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___S               8
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___M 0x00000080
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___S               7
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___M 0x00000040
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___S               6
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___M 0x00000020
#define   PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___S               5
#define   PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___M 0x00000010
#define   PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___S               4
#define   PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___M 0x00000008
#define   PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___S               3
#define   PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___M 0x00000004
#define   PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___S               2
#define   PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___M 0x00000002
#define   PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___S               1
#define   PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___M 0x00000001
#define   PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___S               0
#define   PHYA_ROBE_ERROR_MASK_L___M             0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_MASK_L___S                           0

#define PHYA_ROBE_DEBUG_STATUS_0_L                (0x004B01C8)
#define   PHYA_ROBE_DEBUG_STATUS_0_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_0_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___S               0
#define   PHYA_ROBE_DEBUG_STATUS_0_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_0_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_0_U                (0x004B01CC)
#define   PHYA_ROBE_DEBUG_STATUS_0_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_0_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___S               0
#define   PHYA_ROBE_DEBUG_STATUS_0_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_0_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_1_L                (0x004B01D0)
#define   PHYA_ROBE_DEBUG_STATUS_1_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_1_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_1_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_1_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_1_U                (0x004B01D4)
#define   PHYA_ROBE_DEBUG_STATUS_1_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_1_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_1_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_1_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_2_L                (0x004B01D8)
#define   PHYA_ROBE_DEBUG_STATUS_2_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_2_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___S               0
#define   PHYA_ROBE_DEBUG_STATUS_2_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_2_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_30_L               (0x004B01E0)
#define   PHYA_ROBE_DEBUG_STATUS_30_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_30_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_30_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_30_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_30_U               (0x004B01E4)
#define   PHYA_ROBE_DEBUG_STATUS_30_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_30_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_30_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_30_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_31_L               (0x004B01E8)
#define   PHYA_ROBE_DEBUG_STATUS_31_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_31_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_31_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_31_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_31_U               (0x004B01EC)
#define   PHYA_ROBE_DEBUG_STATUS_31_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_31_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_31_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_31_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_40_L               (0x004B01F0)
#define   PHYA_ROBE_DEBUG_STATUS_40_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_40_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_40_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_40_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_40_U               (0x004B01F4)
#define   PHYA_ROBE_DEBUG_STATUS_40_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_40_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_40_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_40_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_41_L               (0x004B01F8)
#define   PHYA_ROBE_DEBUG_STATUS_41_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_41_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_41_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_41_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_41_U               (0x004B01FC)
#define   PHYA_ROBE_DEBUG_STATUS_41_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_41_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_41_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_41_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_50_L               (0x004B0200)
#define   PHYA_ROBE_DEBUG_STATUS_50_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_50_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_50_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_50_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_50_U               (0x004B0204)
#define   PHYA_ROBE_DEBUG_STATUS_50_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_50_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_50_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_50_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_51_L               (0x004B0208)
#define   PHYA_ROBE_DEBUG_STATUS_51_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_51_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_51_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_51_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_51_U               (0x004B020C)
#define   PHYA_ROBE_DEBUG_STATUS_51_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_51_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_51_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_51_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_6_L                (0x004B0210)
#define   PHYA_ROBE_DEBUG_STATUS_6_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_6_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_6_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_6_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_6_U                (0x004B0214)
#define   PHYA_ROBE_DEBUG_STATUS_6_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_6_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_6_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_6_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_7_L                (0x004B0218)
#define   PHYA_ROBE_DEBUG_STATUS_7_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_7_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___S               0
#define   PHYA_ROBE_DEBUG_STATUS_7_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_7_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_7_U                (0x004B021C)
#define   PHYA_ROBE_DEBUG_STATUS_7_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_7_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___S               0
#define   PHYA_ROBE_DEBUG_STATUS_7_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_7_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_8_L                (0x004B0220)
#define   PHYA_ROBE_DEBUG_STATUS_8_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_8_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___S               0
#define   PHYA_ROBE_DEBUG_STATUS_8_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_8_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_8_U                (0x004B0224)
#define   PHYA_ROBE_DEBUG_STATUS_8_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_8_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___S               0
#define   PHYA_ROBE_DEBUG_STATUS_8_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_8_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_9_L                (0x004B0228)
#define   PHYA_ROBE_DEBUG_STATUS_9_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_9_L___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___POR 0x0
#define   PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___M 0x00000001
#define   PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___S               0
#define   PHYA_ROBE_DEBUG_STATUS_9_L___M         0x00000001   
#define   PHYA_ROBE_DEBUG_STATUS_9_L___S                       0

#define PHYA_ROBE_DEBUG_STATUS_9_U                (0x004B022C)
#define   PHYA_ROBE_DEBUG_STATUS_9_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_9_U___POR       0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___S               0
#define   PHYA_ROBE_DEBUG_STATUS_9_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_9_U___S                       0

#define PHYA_ROBE_DEBUG_STATUS_10_L               (0x004B0230)
#define   PHYA_ROBE_DEBUG_STATUS_10_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_10_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___POR 0x000
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___POR 0x000
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___M 0x03FF0000
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___S              16
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___M 0x000003FF
#define   PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___S               0
#define   PHYA_ROBE_DEBUG_STATUS_10_L___M        0x03FF03FF   
#define   PHYA_ROBE_DEBUG_STATUS_10_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_10_U               (0x004B0234)
#define   PHYA_ROBE_DEBUG_STATUS_10_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_10_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___POR 0x000
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___POR 0x000
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___M 0x03FF0000
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___S              16
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___M 0x000003FF
#define   PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___S               0
#define   PHYA_ROBE_DEBUG_STATUS_10_U___M        0x03FF03FF   
#define   PHYA_ROBE_DEBUG_STATUS_10_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_11_L               (0x004B0238)
#define   PHYA_ROBE_DEBUG_STATUS_11_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_11_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___M 0xFFFF0000
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___S              16
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___M 0x0000FFFF
#define   PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___S               0
#define   PHYA_ROBE_DEBUG_STATUS_11_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_11_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_11_U               (0x004B023C)
#define   PHYA_ROBE_DEBUG_STATUS_11_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_11_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___M 0xFFFF0000
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___S              16
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___M 0x0000FFFF
#define   PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___S               0
#define   PHYA_ROBE_DEBUG_STATUS_11_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_11_U___S                      0

#define PHYA_ROBE_DEBUG_STATUS_12_L               (0x004B0240)
#define   PHYA_ROBE_DEBUG_STATUS_12_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_12_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___POR 0x0000
#define   PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___M 0xFFFF0000
#define   PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___S              16
#define   PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___M 0x0000FFFF
#define   PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___S               0
#define   PHYA_ROBE_DEBUG_STATUS_12_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_12_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_13_L               (0x004B0248)
#define   PHYA_ROBE_DEBUG_STATUS_13_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_13_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___S               0
#define   PHYA_ROBE_DEBUG_STATUS_13_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_13_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_13_U               (0x004B024C)
#define   PHYA_ROBE_DEBUG_STATUS_13_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_13_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___S               0
#define   PHYA_ROBE_DEBUG_STATUS_13_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_13_U___S                      0

#define PHYA_ROBE_PUBLIC_SPARE_L                  (0x004B0250)
#define   PHYA_ROBE_PUBLIC_SPARE_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_PUBLIC_SPARE_L___POR         0x00000000
#define   PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___S               0
#define   PHYA_ROBE_PUBLIC_SPARE_L___M           0xFFFFFFFF   
#define   PHYA_ROBE_PUBLIC_SPARE_L___S                         0

#define PHYA_ROBE_PUBLIC_SPARE_U                  (0x004B0254)
#define   PHYA_ROBE_PUBLIC_SPARE_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_PUBLIC_SPARE_U___POR         0x00000000
#define   PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___S               0
#define   PHYA_ROBE_PUBLIC_SPARE_U___M           0xFFFFFFFF   
#define   PHYA_ROBE_PUBLIC_SPARE_U___S                         0

#define PHYA_ROBE_GEN_CONTROL_0_L                 (0x004B0258)
#define   PHYA_ROBE_GEN_CONTROL_0_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_GEN_CONTROL_0_L___POR        0x00000004
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___POR 0x4
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___M 0x01000000
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___S              24
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___M 0x00010000
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___S              16
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___M 0x00000100
#define   PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___S               8
#define   PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___M 0x00000007
#define   PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___S               0
#define   PHYA_ROBE_GEN_CONTROL_0_L___M          0x01010107   
#define   PHYA_ROBE_GEN_CONTROL_0_L___S                        0

#define PHYA_ROBE_GEN_CONTROL_0_U                 (0x004B025C)
#define   PHYA_ROBE_GEN_CONTROL_0_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_GEN_CONTROL_0_U___POR        0x00000000
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___M 0x01000000
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___S              24
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___M 0x00010000
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___S              16
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___M 0x00000100
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___S               8
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___M 0x00000001
#define   PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___S               0
#define   PHYA_ROBE_GEN_CONTROL_0_U___M          0x01010101   
#define   PHYA_ROBE_GEN_CONTROL_0_U___S                        0

#define PHYA_ROBE_GEN_CONTROL_1_L                 (0x004B0260)
#define   PHYA_ROBE_GEN_CONTROL_1_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_GEN_CONTROL_1_L___POR        0x01020100
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___POR 0x1
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___POR 0x2
#define   PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___POR 0x1
#define   PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___POR 0x0
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___M 0x01000000
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___S              24
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___M 0x00030000
#define   PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___S              16
#define   PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___M 0x00000300
#define   PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___S               8
#define   PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___M 0x00000001
#define   PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___S               0
#define   PHYA_ROBE_GEN_CONTROL_1_L___M          0x01030301   
#define   PHYA_ROBE_GEN_CONTROL_1_L___S                        0

#define PHYA_ROBE_ROBE_HW_CONTROL_0_L             (0x004B0268)
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L___POR    0x01010101
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___M 0x01000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___M 0x00010000
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___M 0x00000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___M 0x00000001
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L___M      0x01010101   
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_0_U             (0x004B026C)
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U___POR    0x010100FA
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___POR 0x00FA
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___M 0x0F000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___M 0x000F0000
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___M 0x0000FFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U___M      0x0F0FFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_0_U___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_1_L             (0x004B0270)
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L___POR    0x02000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___POR 0x2
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___POR 0x00
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___M 0x03000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___M 0x00010000
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___M 0x00000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___M 0x0000003F
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L___M      0x0301013F   
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_1_U             (0x004B0274)
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___M 0x01000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___M 0x00010000
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___M 0x00000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___M 0x00000001
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U___M      0x01010101   
#define   PHYA_ROBE_ROBE_HW_CONTROL_1_U___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_2_L             (0x004B0278)
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_2_U             (0x004B027C)
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_2_U___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_3_L             (0x004B0280)
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_3_U             (0x004B0284)
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_3_U___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_4_L             (0x004B0288)
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_4_U             (0x004B028C)
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U___POR    0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___POR 0x00000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U___M      0xFFFFFFFF   
#define   PHYA_ROBE_ROBE_HW_CONTROL_4_U___S                    0

#define PHYA_ROBE_HE_STNDRD_0_L                   (0x004B0290)
#define   PHYA_ROBE_HE_STNDRD_0_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_0_L___POR          0x00180000
#define   PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___POR 0x00180000
#define   PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_0_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_0_L___S                          0

#define PHYA_ROBE_HE_STNDRD_0_U                   (0x004B0294)
#define   PHYA_ROBE_HE_STNDRD_0_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_0_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_0_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_0_U___S                          0

#define PHYA_ROBE_HE_STNDRD_1_L                   (0x004B0298)
#define   PHYA_ROBE_HE_STNDRD_1_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_1_L___POR          0x00180000
#define   PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___POR 0x00180000
#define   PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_1_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_1_L___S                          0

#define PHYA_ROBE_HE_STNDRD_1_U                   (0x004B029C)
#define   PHYA_ROBE_HE_STNDRD_1_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_1_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_1_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_1_U___S                          0

#define PHYA_ROBE_HE_STNDRD_2_L                   (0x004B02A0)
#define   PHYA_ROBE_HE_STNDRD_2_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_2_L___POR          0x00038000
#define   PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___POR 0x00038000
#define   PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_2_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_2_L___S                          0

#define PHYA_ROBE_HE_STNDRD_2_U                   (0x004B02A4)
#define   PHYA_ROBE_HE_STNDRD_2_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_2_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_2_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_2_U___S                          0

#define PHYA_ROBE_HE_STNDRD_3_L                   (0x004B02A8)
#define   PHYA_ROBE_HE_STNDRD_3_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_3_L___POR          0x00180000
#define   PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___POR 0x00180000
#define   PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_3_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_3_L___S                          0

#define PHYA_ROBE_HE_STNDRD_3_U                   (0x004B02AC)
#define   PHYA_ROBE_HE_STNDRD_3_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_3_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_3_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_3_U___S                          0

#define PHYA_ROBE_HE_STNDRD_4_L                   (0x004B02B0)
#define   PHYA_ROBE_HE_STNDRD_4_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_4_L___POR          0x00180000
#define   PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___POR 0x00180000
#define   PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_4_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_4_L___S                          0

#define PHYA_ROBE_HE_STNDRD_4_U                   (0x004B02B4)
#define   PHYA_ROBE_HE_STNDRD_4_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_4_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_4_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_4_U___S                          0

#define PHYA_ROBE_HE_STNDRD_5_L                   (0x004B02B8)
#define   PHYA_ROBE_HE_STNDRD_5_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_5_L___POR          0x00018000
#define   PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___POR 0x00018000
#define   PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___S               0
#define   PHYA_ROBE_HE_STNDRD_5_L___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_5_L___S                          0

#define PHYA_ROBE_HE_STNDRD_5_U                   (0x004B02BC)
#define   PHYA_ROBE_HE_STNDRD_5_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_HE_STNDRD_5_U___POR          0x00000000
#define   PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___POR 0x00000000
#define   PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___S               0
#define   PHYA_ROBE_HE_STNDRD_5_U___M            0xFFFFFFFF   
#define   PHYA_ROBE_HE_STNDRD_5_U___S                          0

#define PHYA_ROBE_NUM_HESIGB_THR_0_L              (0x004B02C0)
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L___POR     0x04020200
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___POR 0x04
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___POR 0x02
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___POR 0x02
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___POR 0x00
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___M 0xFF000000
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___S              24
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___M 0x00FF0000
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___S              16
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___M 0x0000FF00
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___S               8
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___M 0x000000FF
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___S               0
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L___M       0xFFFFFFFF   
#define   PHYA_ROBE_NUM_HESIGB_THR_0_L___S                     0

#define PHYA_ROBE_NUM_HESIGB_THR_0_U              (0x004B02C4)
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U___POR     0x01000F06
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___POR 0x1
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___POR 0x00
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___POR 0x0F
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___POR 0x06
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___M 0x01000000
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___S              24
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___M 0x00FF0000
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___S              16
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___M 0x0000FF00
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___S               8
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___M 0x000000FF
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___S               0
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U___M       0x01FFFFFF   
#define   PHYA_ROBE_NUM_HESIGB_THR_0_U___S                     0

#define PHYA_ROBE_NUM_HESIGB_THR_1_L              (0x004B02C8)
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L___POR     0x0F040400
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___POR 0x0F
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___POR 0x04
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___POR 0x04
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___POR 0x00
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___M 0xFF000000
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___S              24
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___M 0x00FF0000
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___S              16
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___M 0x0000FF00
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___S               8
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___M 0x000000FF
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___S               0
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L___M       0xFFFFFFFF   
#define   PHYA_ROBE_NUM_HESIGB_THR_1_L___S                     0

#define PHYA_ROBE_NUM_HESIGB_THR_1_U              (0x004B02CC)
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U___POR     0x01000F0F
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___POR 0x1
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___POR 0x00
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___POR 0x0F
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___POR 0x0F
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___M 0x01000000
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___S              24
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___M 0x00FF0000
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___S              16
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___M 0x0000FF00
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___S               8
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___M 0x000000FF
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___S               0
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U___M       0x01FFFFFF   
#define   PHYA_ROBE_NUM_HESIGB_THR_1_U___S                     0

#define PHYA_ROBE_CG_CONTROL_0_L                  (0x004B02D0)
#define   PHYA_ROBE_CG_CONTROL_0_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_0_L___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___M 0x01000000
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___S              24
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___S              16
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___S               8
#define   PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___S               0
#define   PHYA_ROBE_CG_CONTROL_0_L___M           0x01010101   
#define   PHYA_ROBE_CG_CONTROL_0_L___S                         0

#define PHYA_ROBE_CG_CONTROL_0_U                  (0x004B02D4)
#define   PHYA_ROBE_CG_CONTROL_0_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_0_U___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___M 0x01000000
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___S              24
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___S              16
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___S               8
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___S               0
#define   PHYA_ROBE_CG_CONTROL_0_U___M           0x01010101   
#define   PHYA_ROBE_CG_CONTROL_0_U___S                         0

#define PHYA_ROBE_CG_CONTROL_1_L                  (0x004B02D8)
#define   PHYA_ROBE_CG_CONTROL_1_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_1_L___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___S              16
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___S               8
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___S               0
#define   PHYA_ROBE_CG_CONTROL_1_L___M           0x00010101   
#define   PHYA_ROBE_CG_CONTROL_1_L___S                         0

#define PHYA_ROBE_SVS_CONTROL_L                   (0x004B02E0)
#define   PHYA_ROBE_SVS_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_SVS_CONTROL_L___POR          0x00000000
#define   PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___POR 0x0
#define   PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___M 0x00000001
#define   PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___S               0
#define   PHYA_ROBE_SVS_CONTROL_L___M            0x00000001   
#define   PHYA_ROBE_SVS_CONTROL_L___S                          0

#define PHYA_ROBE_LDP_PASS_ITER_L                 (0x004B02E8)
#define   PHYA_ROBE_LDP_PASS_ITER_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_LDP_PASS_ITER_L___POR        0x01010101
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___POR 0x1
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___POR 0x1
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___POR 0x1
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___POR 0x1
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___M 0x07000000
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___S              24
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___M 0x00070000
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___S              16
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___M 0x00000700
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___S               8
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___M 0x00000007
#define   PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___S               0
#define   PHYA_ROBE_LDP_PASS_ITER_L___M          0x07070707   
#define   PHYA_ROBE_LDP_PASS_ITER_L___S                        0

#define PHYA_ROBE_WDOG_CONTROL_0_L                (0x004B02F0)
#define   PHYA_ROBE_WDOG_CONTROL_0_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_WDOG_CONTROL_0_L___POR       0x177000C8
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___POR 0x1770
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___POR 0xC8
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___M 0xFFFF0000
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___S              16
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___M 0x000000FF
#define   PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___S               0
#define   PHYA_ROBE_WDOG_CONTROL_0_L___M         0xFFFF00FF   
#define   PHYA_ROBE_WDOG_CONTROL_0_L___S                       0

#define PHYA_ROBE_WDOG_CONTROL_0_U                (0x004B02F4)
#define   PHYA_ROBE_WDOG_CONTROL_0_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_WDOG_CONTROL_0_U___POR       0xFA042010
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___POR 0xFA
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___POR 0x04
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___POR 0x20
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___POR 0x10
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___M 0xFF000000
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___S              24
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___M 0x00FF0000
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___S              16
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___M 0x0000FF00
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___S               8
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___M 0x000000FF
#define   PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___S               0
#define   PHYA_ROBE_WDOG_CONTROL_0_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_WDOG_CONTROL_0_U___S                       0

#define PHYA_ROBE_WDOG_CONTROL_1_L                (0x004B02F8)
#define   PHYA_ROBE_WDOG_CONTROL_1_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_WDOG_CONTROL_1_L___POR       0x004F0404
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___POR 0x4F
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___POR 0x04
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___POR 0x04
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___M 0x00FF0000
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___S              16
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___M 0x0000FF00
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___S               8
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___M 0x000000FF
#define   PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___S               0
#define   PHYA_ROBE_WDOG_CONTROL_1_L___M         0x00FFFFFF   
#define   PHYA_ROBE_WDOG_CONTROL_1_L___S                       0

#define PHYA_ROBE_DEBUG_CONTROL_0_L               (0x004B0300)
#define   PHYA_ROBE_DEBUG_CONTROL_0_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_0_L___POR      0x01FC0000
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___POR 0x7F
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___POR 0x0000
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___M 0x01FC0000
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___S              18
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___M 0x0003FFFC
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___S               2
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___M 0x00000002
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___S               1
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___M 0x00000001
#define   PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_0_L___M        0x01FFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_0_L___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_0_U               (0x004B0304)
#define   PHYA_ROBE_DEBUG_CONTROL_0_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_0_U___POR      0x00011770
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___POR 0x1
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___POR 0x1770
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___M 0x04000000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___S              26
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___M 0x02000000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___S              25
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___M 0x01E00000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___S              21
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___M 0x001E0000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___S              17
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___M 0x00010000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___S              16
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___M 0x00008000
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___S              15
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___M 0x00007FFF
#define   PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_0_U___M        0x07FFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_0_U___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_1_L               (0x004B0308)
#define   PHYA_ROBE_DEBUG_CONTROL_1_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_1_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___POR 0x00
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___POR 0x00
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___M 0x000C0000
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___S              18
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___M 0x00038000
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___S              15
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___M 0x00007F80
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___S               7
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___M 0x0000007F
#define   PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_1_L___M        0x000FFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_1_L___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_1_U               (0x004B030C)
#define   PHYA_ROBE_DEBUG_CONTROL_1_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_1_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___POR 0x0000
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___POR 0x0000
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___M 0xFFFF0000
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___S              16
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___M 0x0000FFFF
#define   PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_1_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_1_U___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_2_L               (0x004B0310)
#define   PHYA_ROBE_DEBUG_CONTROL_2_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_2_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___M 0x60000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___S              29
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___M 0x10000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___S              28
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___M 0x0F000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___S              24
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___M 0x00F00000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___S              20
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___M 0x000F0000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___S              16
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___M 0x0000F000
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___S              12
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___M 0x00000F00
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___S               8
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___M 0x000000F0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___S               4
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___M 0x0000000F
#define   PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_2_L___M        0x7FFFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_2_L___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_2_U               (0x004B0314)
#define   PHYA_ROBE_DEBUG_CONTROL_2_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_2_U___POR      0x00FF8000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___POR 0x1FF
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___POR 0x00
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___POR 0x00
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___M 0x40000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___S              30
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___M 0x20000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___S              29
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___M 0x18000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___S              27
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___M 0x06000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___S              25
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___M 0x01000000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___S              24
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___M 0x00FF8000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___S              15
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___M 0x00004000
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___S              14
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___M 0x00003F00
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___S               8
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___M 0x000000FC
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___S               2
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___M 0x00000003
#define   PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_2_U___M        0x7FFFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_2_U___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_3_L               (0x004B0318)
#define   PHYA_ROBE_DEBUG_CONTROL_3_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_3_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_3_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_3_L___S                      0

#define PHYA_ROBE_DEBUG_CONTROL_3_U               (0x004B031C)
#define   PHYA_ROBE_DEBUG_CONTROL_3_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_3_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_3_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_3_U___S                      0

#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n(n) (0x004B0320+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___S               0
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___S               0
#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0       (0x004B0320)
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0__BMMU_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0__BMMU_MEM_ADDR___S               0

#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n(n) (0x004B0328+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___S               0
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___S               0
#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0       (0x004B0328)
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0__BMMU_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0__BMMU_MEM_DATA_L32___S               0

#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n(n) (0x004B032C+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___S               0
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___S               0
#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0       (0x004B032C)
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0__BMMU_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0__BMMU_MEM_DATA_U32___S               0

#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n(n) (0x004B0330+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___S               0
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___S               0
#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0       (0x004B0330)
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0__LDPC_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0__LDPC_MEM_ADDR___S               0

#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n(n) (0x004B0338+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___S               0
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___S               0
#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0       (0x004B0338)
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0__LDPC_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0__LDPC_MEM_DATA_L32___S               0

#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n(n) (0x004B033C+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___S               0
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___S               0
#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0       (0x004B033C)
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0___RWC QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0__LDPC_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0__LDPC_MEM_DATA_U32___S               0

#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n(n) (0x004B0340+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___S               0
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___S               0
#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0        (0x004B0340)
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0__VIT_MEM_ADDR___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0__VIT_MEM_ADDR___S               0

#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n(n) (0x004B0348+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___S               0
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___S               0
#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0        (0x004B0348)
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0__VIT_MEM_DATA_L32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0__VIT_MEM_DATA_L32___S               0

#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n(n) (0x004B034C+0x8*(n))
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_nMIN 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_nMAX 0    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_ELEM 1    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___POR 0x00000000
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___S               0
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___M 0xFFFFFFFF   
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___S               0
#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0        (0x004B034C)
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0__VIT_MEM_DATA_U32___M 0xFFFFFFFF
#define   PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0__VIT_MEM_DATA_U32___S               0

#define PHYA_ROBE_MAX_ITER_SU_0_L                 (0x004B0350)
#define   PHYA_ROBE_MAX_ITER_SU_0_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SU_0_L___POR        0x0E0B0D10
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___POR 0x10
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_SU_0_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SU_0_L___S                        0

#define PHYA_ROBE_MAX_ITER_SU_0_U                 (0x004B0354)
#define   PHYA_ROBE_MAX_ITER_SU_0_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SU_0_U___POR        0x0B0C0E0E
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_SU_0_U___M          0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SU_0_U___S                        0

#define PHYA_ROBE_MAX_ITER_SU_1_L                 (0x004B0358)
#define   PHYA_ROBE_MAX_ITER_SU_1_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SU_1_L___POR        0x0F0D0D0C
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_SU_1_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SU_1_L___S                        0

#define PHYA_ROBE_MAX_ITER_SU_1_U                 (0x004B035C)
#define   PHYA_ROBE_MAX_ITER_SU_1_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SU_1_U___POR        0x0F0F0F0F
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_SU_1_U___M          0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SU_1_U___S                        0

#define PHYA_ROBE_MAX_ITER_MUM_0_L                (0x004B0360)
#define   PHYA_ROBE_MAX_ITER_MUM_0_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_0_L___POR       0x0E0B0D10
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___POR 0x10
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_0_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_0_L___S                       0

#define PHYA_ROBE_MAX_ITER_MUM_0_U                (0x004B0364)
#define   PHYA_ROBE_MAX_ITER_MUM_0_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_0_U___POR       0x0B0C0E0E
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_0_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_0_U___S                       0

#define PHYA_ROBE_MAX_ITER_MUM_1_L                (0x004B0368)
#define   PHYA_ROBE_MAX_ITER_MUM_1_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_1_L___POR       0x0F0D0D0C
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_1_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_1_L___S                       0

#define PHYA_ROBE_MAX_ITER_MUM_1_U                (0x004B036C)
#define   PHYA_ROBE_MAX_ITER_MUM_1_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_1_U___POR       0x0F0F0F0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_1_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_1_U___S                       0

#define PHYA_ROBE_MAX_ITER_MUO_0_L                (0x004B0370)
#define   PHYA_ROBE_MAX_ITER_MUO_0_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_0_L___POR       0x0E0B0D10
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___POR 0x10
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_0_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_0_L___S                       0

#define PHYA_ROBE_MAX_ITER_MUO_0_U                (0x004B0374)
#define   PHYA_ROBE_MAX_ITER_MUO_0_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_0_U___POR       0x0B0C0E0E
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___POR 0x0B
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___POR 0x0E
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_0_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_0_U___S                       0

#define PHYA_ROBE_MAX_ITER_MUO_1_L                (0x004B0378)
#define   PHYA_ROBE_MAX_ITER_MUO_1_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_1_L___POR       0x0F0D0D0C
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___POR 0x0D
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_1_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_1_L___S                       0

#define PHYA_ROBE_MAX_ITER_MUO_1_U                (0x004B037C)
#define   PHYA_ROBE_MAX_ITER_MUO_1_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_1_U___POR       0x0F0F0F0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___POR 0x0F
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_1_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_1_U___S                       0

#define PHYA_ROBE_MAX_ITER_LST_0_L                (0x004B0380)
#define   PHYA_ROBE_MAX_ITER_LST_0_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_LST_0_L___POR       0x0A08090C
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___POR 0x08
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___POR 0x09
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_LST_0_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_LST_0_L___S                       0

#define PHYA_ROBE_MAX_ITER_LST_0_U                (0x004B0384)
#define   PHYA_ROBE_MAX_ITER_LST_0_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_LST_0_U___POR       0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_LST_0_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_LST_0_U___S                       0

#define PHYA_ROBE_MAX_ITER_LST_1_L                (0x004B0388)
#define   PHYA_ROBE_MAX_ITER_LST_1_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_LST_1_L___POR       0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_LST_1_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_LST_1_L___S                       0

#define PHYA_ROBE_MAX_ITER_LST_1_U                (0x004B038C)
#define   PHYA_ROBE_MAX_ITER_LST_1_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_LST_1_U___POR       0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_LST_1_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_LST_1_U___S                       0

#define PHYA_ROBE_MAX_ITER_LST_2_L                (0x004B0390)
#define   PHYA_ROBE_MAX_ITER_LST_2_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_LST_2_L___POR       0x01030302
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___POR 0x01
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___POR 0x03
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___POR 0x3
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___POR 0x2
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___M 0x1F000000
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___S              24
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___M 0x001F0000
#define   PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___S              16
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___M 0x00000300
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___S               8
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___M 0x0000000F
#define   PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___S               0
#define   PHYA_ROBE_MAX_ITER_LST_2_L___M         0x1F1F030F   
#define   PHYA_ROBE_MAX_ITER_LST_2_L___S                       0

#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L       (0x004B0398)
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___POR 0x90489090
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U       (0x004B039C)
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___POR 0x30486048
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___POR 0x30
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___POR 0x60
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L       (0x004B03A0)
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___POR 0x30483048
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___POR 0x30
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___POR 0x30
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U       (0x004B03A4)
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___POR 0xFFFF3044
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___POR 0x30
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___POR 0x44
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L       (0x004B03A8)
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___POR 0x90489090
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___POR 0x48
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___POR 0x90
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U       (0x004B03AC)
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___POR 0x2C425842
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___POR 0x2C
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___POR 0x42
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___POR 0x58
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___POR 0x42
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L       (0x004B03B0)
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___POR 0x2B392C42
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___POR 0x2B
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___POR 0x39
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___POR 0x2C
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___POR 0x42
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U       (0x004B03B4)
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___RWC QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___POR 0xFFFF222F
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___POR 0x22
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___POR 0x2F
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___S               0

#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L          (0x004B03B8)
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___POR 0x783C7878
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___POR 0x78
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___POR 0x78
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___POR 0x78
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___M   0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___S                 0

#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U          (0x004B03BC)
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___POR 0x283C503C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___POR 0x28
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___POR 0x50
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___M   0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___S                 0

#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L          (0x004B03C0)
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___POR 0x283C283C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___POR 0x28
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___POR 0x28
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___M   0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___S                 0

#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U          (0x004B03C4)
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___RWC    QCSR_REG_RW    
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___POR 0xFFFF283C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___POR 0xFF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___POR 0x28
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___POR 0x3C
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___M 0xFF000000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___S              24
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___S              16
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___S               8
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___M 0x000000FF
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___S               0
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___M   0xFFFFFFFF   
#define   PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___S                 0

#define PHYA_ROBE_PRIVATE_SPARE_L                 (0x004B03C8)
#define   PHYA_ROBE_PRIVATE_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_PRIVATE_SPARE_L___POR        0x00000000
#define   PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___S               0
#define   PHYA_ROBE_PRIVATE_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_PRIVATE_SPARE_L___S                        0

#define PHYA_ROBE_PRIVATE_SPARE_U                 (0x004B03CC)
#define   PHYA_ROBE_PRIVATE_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_PRIVATE_SPARE_U___POR        0x00000000
#define   PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___S               0
#define   PHYA_ROBE_PRIVATE_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_ROBE_PRIVATE_SPARE_U___S                        0

#define PHYA_ROBE_EARLY_TERMINATE_L               (0x004B03D0)
#define   PHYA_ROBE_EARLY_TERMINATE_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_EARLY_TERMINATE_L___POR      0x00000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___M 0x80000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___S              31
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___M 0x40000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___S              30
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___M 0x20000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___S              29
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___M 0x10000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___S              28
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___M 0x08000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___S              27
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___M 0x04000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___S              26
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___M 0x02000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___S              25
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___M 0x01000000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___S              24
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___M 0x00800000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___S              23
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___M 0x00400000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___S              22
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___M 0x00200000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___S              21
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___M 0x00100000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___S              20
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___M 0x00080000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___S              19
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___M 0x00040000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___S              18
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___M 0x00020000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___S              17
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___M 0x00010000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___S              16
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___M 0x00008000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___S              15
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___M 0x00004000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___S              14
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___M 0x00002000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___S              13
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___M 0x00001000
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___S              12
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___M 0x00000800
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___S              11
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___M 0x00000400
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___S              10
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___M 0x00000200
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___S               9
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___M 0x00000100
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___S               8
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___M 0x00000080
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___S               7
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___M 0x00000040
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___S               6
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___M 0x00000020
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___S               5
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___M 0x00000010
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___S               4
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___M 0x00000008
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___S               3
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___M 0x00000004
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___S               2
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___M 0x00000002
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___S               1
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___M 0x00000001
#define   PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___S               0
#define   PHYA_ROBE_EARLY_TERMINATE_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_EARLY_TERMINATE_L___S                      0

#define PHYA_ROBE_EARLY_TERMINATE_U               (0x004B03D4)
#define   PHYA_ROBE_EARLY_TERMINATE_U___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_EARLY_TERMINATE_U___POR      0x00000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___POR 0x0
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___M 0x80000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___S              31
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___M 0x40000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___S              30
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___M 0x20000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___S              29
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___M 0x10000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___S              28
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___M 0x08000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___S              27
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___M 0x04000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___S              26
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___M 0x02000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___S              25
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___M 0x01000000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___S              24
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___M 0x00800000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___S              23
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___M 0x00400000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___S              22
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___M 0x00200000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___S              21
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___M 0x00100000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___S              20
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___M 0x00080000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___S              19
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___M 0x00040000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___S              18
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___M 0x00020000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___S              17
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___M 0x00010000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___S              16
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___M 0x00008000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___S              15
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___M 0x00004000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___S              14
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___M 0x00002000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___S              13
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___M 0x00001000
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___S              12
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___M 0x00000800
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___S              11
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___M 0x00000400
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___S              10
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___M 0x00000200
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___S               9
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___M 0x00000100
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___S               8
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___M 0x00000080
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___S               7
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___M 0x00000040
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___S               6
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___M 0x00000020
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___S               5
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___M 0x00000010
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___S               4
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___M 0x00000008
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___S               3
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___M 0x00000004
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___S               2
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___M 0x00000002
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___S               1
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___M 0x00000001
#define   PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___S               0
#define   PHYA_ROBE_EARLY_TERMINATE_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_EARLY_TERMINATE_U___S                      0

#define PHYA_ROBE_NUM_USRS_L                      (0x004B03D8)
#define   PHYA_ROBE_NUM_USRS_L___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_NUM_USRS_L___POR             0x00000000
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___POR 0x00
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___POR 0x00
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___POR 0x00
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___POR 0x00
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___M 0xFF000000
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___S              24
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___M 0x00FF0000
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___S              16
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___M 0x0000FF00
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___S               8
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___M 0x000000FF
#define   PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___S               0
#define   PHYA_ROBE_NUM_USRS_L___M               0xFFFFFFFF   
#define   PHYA_ROBE_NUM_USRS_L___S                             0

#define PHYA_ROBE_NUM_USRS_U                      (0x004B03DC)
#define   PHYA_ROBE_NUM_USRS_U___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_NUM_USRS_U___POR             0x00000000
#define   PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___POR 0x00
#define   PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___M 0x000000FF
#define   PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___S               0
#define   PHYA_ROBE_NUM_USRS_U___M               0x000000FF   
#define   PHYA_ROBE_NUM_USRS_U___S                             0

#define PHYA_ROBE_DISABLE_DECODERS_L              (0x004B03E0)
#define   PHYA_ROBE_DISABLE_DECODERS_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_DISABLE_DECODERS_L___POR     0x00000000
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___POR 0x0
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___POR 0x0
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___M 0x00000F00
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___S               8
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___M 0x0000000F
#define   PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___S               0
#define   PHYA_ROBE_DISABLE_DECODERS_L___M       0x00000F0F   
#define   PHYA_ROBE_DISABLE_DECODERS_L___S                     0

#define PHYA_ROBE_USR_TAB_RDY_L                   (0x004B03E8)
#define   PHYA_ROBE_USR_TAB_RDY_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_RDY_L___POR          0x00000000
#define   PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___POR 0x0
#define   PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___M 0x00000001
#define   PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___S               0
#define   PHYA_ROBE_USR_TAB_RDY_L___M            0x00000001   
#define   PHYA_ROBE_USR_TAB_RDY_L___S                          0

#define PHYA_ROBE_ROBE_EN_L                       (0x004B03F0)
#define   PHYA_ROBE_ROBE_EN_L___RWC                 QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_EN_L___POR              0x00000000
#define   PHYA_ROBE_ROBE_EN_L__ROBE_EN___POR     0x0
#define   PHYA_ROBE_ROBE_EN_L__ROBE_EN___M       0x00000001
#define   PHYA_ROBE_ROBE_EN_L__ROBE_EN___S                     0
#define   PHYA_ROBE_ROBE_EN_L___M                0x00000001   
#define   PHYA_ROBE_ROBE_EN_L___S                              0

#define PHYA_ROBE_FW_INITIATED_SPARE_L            (0x004B03F8)
#define   PHYA_ROBE_FW_INITIATED_SPARE_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_FW_INITIATED_SPARE_L___POR   0x00000000
#define   PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___S               0
#define   PHYA_ROBE_FW_INITIATED_SPARE_L___M     0xFFFFFFFF   
#define   PHYA_ROBE_FW_INITIATED_SPARE_L___S                   0

#define PHYA_ROBE_FW_INITIATED_SPARE_U            (0x004B03FC)
#define   PHYA_ROBE_FW_INITIATED_SPARE_U___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_FW_INITIATED_SPARE_U___POR   0x00000000
#define   PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___S               0
#define   PHYA_ROBE_FW_INITIATED_SPARE_U___M     0xFFFFFFFF   
#define   PHYA_ROBE_FW_INITIATED_SPARE_U___S                   0

#define PHYA_ROBE_SIG_DEC_RD_L                    (0x004B0400)
#define   PHYA_ROBE_SIG_DEC_RD_L___RWC              QCSR_REG_RO    
#define   PHYA_ROBE_SIG_DEC_RD_L___POR           0x00000000
#define   PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___POR 0x00000000
#define   PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___S               0
#define   PHYA_ROBE_SIG_DEC_RD_L___M             0xFFFFFFFF   
#define   PHYA_ROBE_SIG_DEC_RD_L___S                           0

#define PHYA_ROBE_SIG_DEC_RD_U                    (0x004B0404)
#define   PHYA_ROBE_SIG_DEC_RD_U___RWC              QCSR_REG_RO    
#define   PHYA_ROBE_SIG_DEC_RD_U___POR           0x00000000
#define   PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___POR 0x00000000
#define   PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___S               0
#define   PHYA_ROBE_SIG_DEC_RD_U___M             0xFFFFFFFF   
#define   PHYA_ROBE_SIG_DEC_RD_U___S                           0

#define PHYA_ROBE_SIG_DEC_SPARE_L                 (0x004B0408)
#define   PHYA_ROBE_SIG_DEC_SPARE_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_SIG_DEC_SPARE_L___POR        0x00000000
#define   PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___S               0
#define   PHYA_ROBE_SIG_DEC_SPARE_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_SIG_DEC_SPARE_L___S                        0

#define PHYA_ROBE_SIG_DEC_SPARE_U                 (0x004B040C)
#define   PHYA_ROBE_SIG_DEC_SPARE_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_SIG_DEC_SPARE_U___POR        0x00000000
#define   PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___S               0
#define   PHYA_ROBE_SIG_DEC_SPARE_U___M          0xFFFFFFFF   
#define   PHYA_ROBE_SIG_DEC_SPARE_U___S                        0

#define PHYA_ROBE_SIG_EXT_DEC_RD_L                (0x004B0410)
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L___POR       0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___POR 0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___S               0
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L___M         0xFFFFFFFF   
#define   PHYA_ROBE_SIG_EXT_DEC_RD_L___S                       0

#define PHYA_ROBE_SIG_EXT_DEC_RD_U                (0x004B0414)
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U___RWC          QCSR_REG_RO    
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U___POR       0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___POR 0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___S               0
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U___M         0xFFFFFFFF   
#define   PHYA_ROBE_SIG_EXT_DEC_RD_U___S                       0

#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L             (0x004B0418)
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L___POR    0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___S               0
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L___M      0xFFFFFFFF   
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_L___S                    0

#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U             (0x004B041C)
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U___POR    0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___S               0
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U___M      0xFFFFFFFF   
#define   PHYA_ROBE_SIG_EXT_DEC_SPARE_U___S                    0

#define PHYA_ROBE_PKT_CONTROL_L                   (0x004B0420)
#define   PHYA_ROBE_PKT_CONTROL_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_PKT_CONTROL_L___POR          0x00000001
#define   PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_L__PKT_BW___POR  0x0
#define   PHYA_ROBE_PKT_CONTROL_L__IS_SU___POR   0x1
#define   PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___M   0x01000000
#define   PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___S                24
#define   PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___M 0x00010000
#define   PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___S              16
#define   PHYA_ROBE_PKT_CONTROL_L__PKT_BW___M    0x00000300
#define   PHYA_ROBE_PKT_CONTROL_L__PKT_BW___S                  8
#define   PHYA_ROBE_PKT_CONTROL_L__IS_SU___M     0x00000001
#define   PHYA_ROBE_PKT_CONTROL_L__IS_SU___S                   0
#define   PHYA_ROBE_PKT_CONTROL_L___M            0x01010301   
#define   PHYA_ROBE_PKT_CONTROL_L___S                          0

#define PHYA_ROBE_PKT_CONTROL_U                   (0x004B0424)
#define   PHYA_ROBE_PKT_CONTROL_U___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_PKT_CONTROL_U___POR          0x00000000
#define   PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___M 0x0F000000
#define   PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___S              24
#define   PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___M 0x00030000
#define   PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___S              16
#define   PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___M 0x00000100
#define   PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___S               8
#define   PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___M 0x00000001
#define   PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___S               0
#define   PHYA_ROBE_PKT_CONTROL_U___M            0x0F030101   
#define   PHYA_ROBE_PKT_CONTROL_U___S                          0

#define PHYA_ROBE_PKT_CONTROL_LEGACY_L            (0x004B0428)
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L___POR   0x00000000
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___POR 0x0
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___M 0x00070000
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___S              16
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___M 0x00000100
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___S               8
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___M 0x00000007
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___S               0
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L___M     0x00070107   
#define   PHYA_ROBE_PKT_CONTROL_LEGACY_L___S                   0

#define PHYA_ROBE_LSIG_REL_L                      (0x004B0430)
#define   PHYA_ROBE_LSIG_REL_L___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_LSIG_REL_L___POR             0x00060005
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___POR 0x006
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___POR 0x05
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___M 0x07FF0000
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___S              16
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___M 0x000000FF
#define   PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___S               0
#define   PHYA_ROBE_LSIG_REL_L___M               0x07FF00FF   
#define   PHYA_ROBE_LSIG_REL_L___S                             0

#define PHYA_ROBE_LSIG_REL_U                      (0x004B0434)
#define   PHYA_ROBE_LSIG_REL_U___RWC                QCSR_REG_RW    
#define   PHYA_ROBE_LSIG_REL_U___POR             0x00000006
#define   PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___POR 0x06
#define   PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___M 0x000000FF
#define   PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___S               0
#define   PHYA_ROBE_LSIG_REL_U___M               0x000000FF   
#define   PHYA_ROBE_LSIG_REL_U___S                             0

#define PHYA_ROBE_SU_CONTROL_0_L                  (0x004B0438)
#define   PHYA_ROBE_SU_CONTROL_0_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_0_L___POR         0x00000030
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___POR 0x0
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___POR 0x0
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___POR 0x030
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___M   0x0F000000
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___S                24
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___M 0x00010000
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___S              16
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___M  0x000007FF
#define   PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___S                0
#define   PHYA_ROBE_SU_CONTROL_0_L___M           0x0F0107FF   
#define   PHYA_ROBE_SU_CONTROL_0_L___S                         0

#define PHYA_ROBE_SU_CONTROL_0_U                  (0x004B043C)
#define   PHYA_ROBE_SU_CONTROL_0_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_0_U___POR         0x1001010B
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___POR 0x10
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NES___POR 0x1
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___POR 0x1
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___POR 0xB
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___M  0x3F000000
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___S               24
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NES___M   0x000F0000
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NES___S                16
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___M   0x00000F00
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___S                 8
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___M 0x0000000F
#define   PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___S               0
#define   PHYA_ROBE_SU_CONTROL_0_U___M           0x3F0F0F0F   
#define   PHYA_ROBE_SU_CONTROL_0_U___S                         0

#define PHYA_ROBE_SU_CONTROL_1_L                  (0x004B0440)
#define   PHYA_ROBE_SU_CONTROL_1_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_1_L___POR         0x00010003
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___POR 0x0
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___POR 0x1
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___POR 0x0
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___POR 0x03
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___M 0x01000000
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___S              24
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___M 0x000F0000
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___S              16
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___M 0x00000700
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___S               8
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___M  0x0000001F
#define   PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___S                0
#define   PHYA_ROBE_SU_CONTROL_1_L___M           0x010F071F   
#define   PHYA_ROBE_SU_CONTROL_1_L___S                         0

#define PHYA_ROBE_SU_CONTROL_1_U                  (0x004B0444)
#define   PHYA_ROBE_SU_CONTROL_1_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_1_U___POR         0x00000000
#define   PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___POR 0x0
#define   PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___M 0x00000001
#define   PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___S               0
#define   PHYA_ROBE_SU_CONTROL_1_U___M           0x00000001   
#define   PHYA_ROBE_SU_CONTROL_1_U___S                         0

#define PHYA_ROBE_SU_CONTROL_2_L                  (0x004B0448)
#define   PHYA_ROBE_SU_CONTROL_2_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_2_L___POR         0x00000000
#define   PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___POR 0x0000000
#define   PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___M 0x03FFFFFF
#define   PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___S               0
#define   PHYA_ROBE_SU_CONTROL_2_L___M           0x03FFFFFF   
#define   PHYA_ROBE_SU_CONTROL_2_L___S                         0

#define PHYA_ROBE_SU_CONTROL_2_U                  (0x004B044C)
#define   PHYA_ROBE_SU_CONTROL_2_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_SU_CONTROL_2_U___POR         0x00800000
#define   PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___POR 0x80
#define   PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___POR 0x0000
#define   PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___M 0x00FF0000
#define   PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___S              16
#define   PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___M 0x00007FFF
#define   PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___S               0
#define   PHYA_ROBE_SU_CONTROL_2_U___M           0x00FF7FFF   
#define   PHYA_ROBE_SU_CONTROL_2_U___S                         0

#define PHYA_ROBE_SU_LDPC_CONTROL_0_L             (0x004B0450)
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L___POR    0x00000000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___POR 0x0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___POR 0x0
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___POR 0x0
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___M 0xFFFF0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___S              16
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___M 0x00000300
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___S               8
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___M 0x00000001
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___S               0
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L___M      0xFFFF0301   
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_L___S                    0

#define PHYA_ROBE_SU_LDPC_CONTROL_0_U             (0x004B0454)
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U___POR    0x00000000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___POR 0x0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___POR 0x0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___M 0xFFFF0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___S              16
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___M 0x0000FFFF
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___S               0
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U___M      0xFFFFFFFF   
#define   PHYA_ROBE_SU_LDPC_CONTROL_0_U___S                    0

#define PHYA_ROBE_SU_LDPC_CONTROL_1_L             (0x004B0458)
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L___POR    0x00000000
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___POR 0x0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___POR 0x000
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___M 0xFFFF0000
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___S              16
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___M 0x000007FF
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___S               0
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L___M      0xFFFF07FF   
#define   PHYA_ROBE_SU_LDPC_CONTROL_1_L___S                    0

#define PHYA_ROBE_HESIGB_CONTROL_0_L              (0x004B0460)
#define   PHYA_ROBE_HESIGB_CONTROL_0_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_HESIGB_CONTROL_0_L___POR     0x001F3412
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___POR 0x00
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___POR 0x1F
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___POR 0x34
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___POR 0x12
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___M 0x1F000000
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___S              24
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___M 0x00FF0000
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___S              16
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___M 0x0000FF00
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___S               8
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___M 0x000000FF
#define   PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___S               0
#define   PHYA_ROBE_HESIGB_CONTROL_0_L___M       0x1FFFFFFF   
#define   PHYA_ROBE_HESIGB_CONTROL_0_L___S                     0

#define PHYA_ROBE_HESIGB_CONTROL_0_U              (0x004B0464)
#define   PHYA_ROBE_HESIGB_CONTROL_0_U___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_HESIGB_CONTROL_0_U___POR     0x00010101
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___POR 0x00
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___POR 0x01
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___POR 0x01
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___POR 0x01
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___M 0xFF000000
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___S              24
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___M 0x00FF0000
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___S              16
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___M 0x0000FF00
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___S               8
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___M 0x000000FF
#define   PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___S               0
#define   PHYA_ROBE_HESIGB_CONTROL_0_U___M       0xFFFFFFFF   
#define   PHYA_ROBE_HESIGB_CONTROL_0_U___S                     0

#define PHYA_ROBE_HESIGB_CONTROL_1_L              (0x004B0468)
#define   PHYA_ROBE_HESIGB_CONTROL_1_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_HESIGB_CONTROL_1_L___POR     0x00000000
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___POR 0x0
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___POR 0x00
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___POR 0x00
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___M 0x00010000
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___S              16
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___M 0x0000FF00
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___S               8
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___M 0x000000FF
#define   PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___S               0
#define   PHYA_ROBE_HESIGB_CONTROL_1_L___M       0x0001FFFF   
#define   PHYA_ROBE_HESIGB_CONTROL_1_L___S                     0

#define PHYA_ROBE_DCSR_LATCH_SPARE_L              (0x004B0470)
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L___POR     0x00000000
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___POR 0x00000000
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___M 0xFFFFFFFF
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___S               0
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L___M       0xFFFFFFFF   
#define   PHYA_ROBE_DCSR_LATCH_SPARE_L___S                     0

#define PHYA_ROBE_DCSR_LATCH_SPARE_U              (0x004B0474)
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U___POR     0x00000000
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___POR 0x00000000
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___M 0xFFFFFFFF
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___S               0
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U___M       0xFFFFFFFF   
#define   PHYA_ROBE_DCSR_LATCH_SPARE_U___S                     0

#define PHYA_ROBE_USR_TAB_0_L                     (0x004B0478)
#define   PHYA_ROBE_USR_TAB_0_L___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_0_L___POR            0x00000400
#define   PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___POR 0x0
#define   PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___POR 0x0
#define   PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___POR 0x04
#define   PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___POR 0x00
#define   PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___M 0x07000000
#define   PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___S              24
#define   PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___M  0x000F0000
#define   PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___S               16
#define   PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___M 0x00001F00
#define   PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___S               8
#define   PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___M 0x0000003F
#define   PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___S               0
#define   PHYA_ROBE_USR_TAB_0_L___M              0x070F1F3F   
#define   PHYA_ROBE_USR_TAB_0_L___S                            0

#define PHYA_ROBE_USR_TAB_0_U                     (0x004B047C)
#define   PHYA_ROBE_USR_TAB_0_U___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_0_U___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___POR 0x0
#define   PHYA_ROBE_USR_TAB_0_U__USR_NCOL___POR  0x00
#define   PHYA_ROBE_USR_TAB_0_U__USR_NROW___POR  0x00
#define   PHYA_ROBE_USR_TAB_0_U__USR_MCS___POR   0x0
#define   PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___M 0x0F000000
#define   PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___S              24
#define   PHYA_ROBE_USR_TAB_0_U__USR_NCOL___M    0x003F0000
#define   PHYA_ROBE_USR_TAB_0_U__USR_NCOL___S                 16
#define   PHYA_ROBE_USR_TAB_0_U__USR_NROW___M    0x00001F00
#define   PHYA_ROBE_USR_TAB_0_U__USR_NROW___S                  8
#define   PHYA_ROBE_USR_TAB_0_U__USR_MCS___M     0x0000000F
#define   PHYA_ROBE_USR_TAB_0_U__USR_MCS___S                   0
#define   PHYA_ROBE_USR_TAB_0_U___M              0x0F3F1F0F   
#define   PHYA_ROBE_USR_TAB_0_U___S                            0

#define PHYA_ROBE_USR_TAB_1_L                     (0x004B0480)
#define   PHYA_ROBE_USR_TAB_1_L___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_1_L___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_1_L__USR_N_SC___POR  0x000
#define   PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___POR 0x0
#define   PHYA_ROBE_USR_TAB_1_L__USR_NSS___POR   0x0
#define   PHYA_ROBE_USR_TAB_1_L__USR_N_SC___M    0x07FF0000
#define   PHYA_ROBE_USR_TAB_1_L__USR_N_SC___S                 16
#define   PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___M 0x00000100
#define   PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___S               8
#define   PHYA_ROBE_USR_TAB_1_L__USR_NSS___M     0x0000000F
#define   PHYA_ROBE_USR_TAB_1_L__USR_NSS___S                   0
#define   PHYA_ROBE_USR_TAB_1_L___M              0x07FF010F   
#define   PHYA_ROBE_USR_TAB_1_L___S                            0

#define PHYA_ROBE_USR_TAB_1_U                     (0x004B0484)
#define   PHYA_ROBE_USR_TAB_1_U___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_1_U___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___POR 0x0
#define   PHYA_ROBE_USR_TAB_1_U__USR_VALID___POR 0x0
#define   PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___POR 0x0
#define   PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___POR 0x0
#define   PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___M  0x01000000
#define   PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___S               24
#define   PHYA_ROBE_USR_TAB_1_U__USR_VALID___M   0x00010000
#define   PHYA_ROBE_USR_TAB_1_U__USR_VALID___S                16
#define   PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___M 0x00000100
#define   PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___S               8
#define   PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___M  0x00000001
#define   PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___S                0
#define   PHYA_ROBE_USR_TAB_1_U___M              0x01010101   
#define   PHYA_ROBE_USR_TAB_1_U___S                            0

#define PHYA_ROBE_USR_TAB_2_L                     (0x004B0488)
#define   PHYA_ROBE_USR_TAB_2_L___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_2_L___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___POR 0x0
#define   PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___M 0x00000001
#define   PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___S               0
#define   PHYA_ROBE_USR_TAB_2_L___M              0x00000001   
#define   PHYA_ROBE_USR_TAB_2_L___S                            0

#define PHYA_ROBE_USR_TAB_2_U                     (0x004B048C)
#define   PHYA_ROBE_USR_TAB_2_U___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_2_U___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___POR 0x0000000
#define   PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___M 0x03FFFFFF
#define   PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___S               0
#define   PHYA_ROBE_USR_TAB_2_U___M              0x03FFFFFF   
#define   PHYA_ROBE_USR_TAB_2_U___S                            0

#define PHYA_ROBE_USR_TAB_3_L                     (0x004B0490)
#define   PHYA_ROBE_USR_TAB_3_L___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_3_L___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___POR 0x0000
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___POR 0x0
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___POR 0x0
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___M 0xFFFF0000
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___S              16
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___M 0x00000300
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___S               8
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___M 0x00000001
#define   PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___S               0
#define   PHYA_ROBE_USR_TAB_3_L___M              0xFFFF0301   
#define   PHYA_ROBE_USR_TAB_3_L___S                            0

#define PHYA_ROBE_USR_TAB_3_U                     (0x004B0494)
#define   PHYA_ROBE_USR_TAB_3_U___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_3_U___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___POR 0x0000
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___POR 0x0000
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___M 0xFFFF0000
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___S              16
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___M 0x0000FFFF
#define   PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___S               0
#define   PHYA_ROBE_USR_TAB_3_U___M              0xFFFFFFFF   
#define   PHYA_ROBE_USR_TAB_3_U___S                            0

#define PHYA_ROBE_USR_TAB_4_L                     (0x004B0498)
#define   PHYA_ROBE_USR_TAB_4_L___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_4_L___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___POR 0x0000
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___POR 0x000
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___M 0xFFFF0000
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___S              16
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___M 0x000007FF
#define   PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___S               0
#define   PHYA_ROBE_USR_TAB_4_L___M              0xFFFF07FF   
#define   PHYA_ROBE_USR_TAB_4_L___S                            0

#define PHYA_ROBE_USR_TAB_4_U                     (0x004B049C)
#define   PHYA_ROBE_USR_TAB_4_U___RWC               QCSR_REG_RW    
#define   PHYA_ROBE_USR_TAB_4_U___POR            0x00000000
#define   PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___POR 0x0
#define   PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___M 0x0000000F
#define   PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___S               0
#define   PHYA_ROBE_USR_TAB_4_U___M              0x0000000F   
#define   PHYA_ROBE_USR_TAB_4_U___S                            0

#define PHYA_ROBE_ERROR_V2_CODE_L                 (0x004B5000)
#define   PHYA_ROBE_ERROR_V2_CODE_L___RWC           QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_V2_CODE_L___POR        0x00000000
#define   PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___POR 0x00
#define   PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___M 0x0000007F
#define   PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___S               0
#define   PHYA_ROBE_ERROR_V2_CODE_L___M          0x0000007F   
#define   PHYA_ROBE_ERROR_V2_CODE_L___S                        0

#define PHYA_ROBE_ERROR_V2_INFO_L                 (0x004B5008)
#define   PHYA_ROBE_ERROR_V2_INFO_L___RWC           QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_V2_INFO_L___POR        0x00000000
#define   PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___POR 0x00000000
#define   PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___M 0xFFFFFFFF
#define   PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___S               0
#define   PHYA_ROBE_ERROR_V2_INFO_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_V2_INFO_L___S                        0

#define PHYA_ROBE_ERROR_V2_STATUS_L               (0x004B5010)
#define   PHYA_ROBE_ERROR_V2_STATUS_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_V2_STATUS_L___POR      0x00000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___M 0x80000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___S              31
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___M 0x40000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___S              30
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___M 0x20000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___S              29
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___M 0x10000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___S              28
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___M 0x08000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___S              27
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___M 0x04000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___S              26
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___M 0x02000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___S              25
#define   PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___M 0x01000000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___S              24
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___M 0x00800000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___S              23
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___M 0x00400000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___S              22
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___M 0x00200000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___S              21
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___M 0x00100000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___S              20
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___M 0x00080000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___S              19
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___M 0x00040000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___S              18
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___M 0x00020000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___S              17
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___M 0x00010000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___S              16
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___M 0x00008000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___S              15
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___M 0x00004000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___S              14
#define   PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___M 0x00002000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___S              13
#define   PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___M 0x00001000
#define   PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___S              12
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___M 0x00000800
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___S              11
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___M 0x00000400
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___S              10
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___M 0x00000200
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___S               9
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___M 0x00000100
#define   PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___S               8
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___M 0x00000080
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___S               7
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___M 0x00000040
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___S               6
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___M 0x00000020
#define   PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___S               5
#define   PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___M 0x00000010
#define   PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___S               4
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___M 0x00000008
#define   PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___S               3
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___M 0x00000004
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___S               2
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___M 0x00000002
#define   PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___S               1
#define   PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___M 0x00000001
#define   PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___S               0
#define   PHYA_ROBE_ERROR_V2_STATUS_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_V2_STATUS_L___S                      0

#define PHYA_ROBE_ERROR_V2_STATUS_U               (0x004B5014)
#define   PHYA_ROBE_ERROR_V2_STATUS_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_ERROR_V2_STATUS_U___POR      0x00000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___POR 0x0
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___M 0x80000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___S              31
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___M 0x40000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___S              30
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___M 0x20000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___S              29
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___M 0x10000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___S              28
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___M 0x08000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___S              27
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___M 0x04000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___S              26
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___M 0x02000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___S              25
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___M 0x01000000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___S              24
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___M 0x00800000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___S              23
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___M 0x00400000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___S              22
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___M 0x00200000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___S              21
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___M 0x00100000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___S              20
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___M 0x00080000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___S              19
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___M 0x00040000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___S              18
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___M 0x00020000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___S              17
#define   PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___M 0x00010000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___S              16
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___M 0x00008000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___S              15
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___M 0x00004000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___S              14
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___M 0x00002000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___S              13
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___M 0x00001000
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___S              12
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___M 0x00000800
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___S              11
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___M 0x00000400
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___S              10
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___M 0x00000200
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___S               9
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___M 0x00000100
#define   PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___S               8
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___M 0x00000080
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___S               7
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___M 0x00000040
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___S               6
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___M 0x00000020
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___S               5
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___M 0x00000010
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___S               4
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___M 0x00000008
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___S               3
#define   PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___M 0x00000004
#define   PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___S               2
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___M 0x00000002
#define   PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___S               1
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___M 0x00000001
#define   PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___S               0
#define   PHYA_ROBE_ERROR_V2_STATUS_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_V2_STATUS_U___S                      0

#define PHYA_ROBE_ERROR_V2_MASK_L                 (0x004B5018)
#define   PHYA_ROBE_ERROR_V2_MASK_L___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_ERROR_V2_MASK_L___POR        0xFFFFFFFF
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___M 0x80000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___S              31
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___M 0x40000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___S              30
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___M 0x20000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___S              29
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___M 0x10000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___S              28
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___M 0x08000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___S              27
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___M 0x04000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___S              26
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___M 0x02000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___S              25
#define   PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___M 0x01000000
#define   PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___S              24
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___M 0x00800000
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___S              23
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___M 0x00400000
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___S              22
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___M 0x00200000
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___S              21
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___M 0x00100000
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___S              20
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___M 0x00080000
#define   PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___S              19
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___M 0x00040000
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___S              18
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___M 0x00020000
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___S              17
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___M 0x00010000
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___S              16
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___M 0x00008000
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___S              15
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___M 0x00004000
#define   PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___S              14
#define   PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___M 0x00002000
#define   PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___S              13
#define   PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___M 0x00001000
#define   PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___S              12
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___M 0x00000800
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___S              11
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___M 0x00000400
#define   PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___S              10
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___M 0x00000200
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___S               9
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___M 0x00000100
#define   PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___S               8
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___M 0x00000080
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___S               7
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___M 0x00000040
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___S               6
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___M 0x00000020
#define   PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___S               5
#define   PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___M 0x00000010
#define   PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___S               4
#define   PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___M 0x00000008
#define   PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___S               3
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___M 0x00000004
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___S               2
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___M 0x00000002
#define   PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___S               1
#define   PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___M 0x00000001
#define   PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___S               0
#define   PHYA_ROBE_ERROR_V2_MASK_L___M          0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_V2_MASK_L___S                        0

#define PHYA_ROBE_ERROR_V2_MASK_U                 (0x004B501C)
#define   PHYA_ROBE_ERROR_V2_MASK_U___RWC           QCSR_REG_RW    
#define   PHYA_ROBE_ERROR_V2_MASK_U___POR        0xFFFFFFFF
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___POR 0x1
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___M 0x80000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___S              31
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___M 0x40000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___S              30
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___M 0x20000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___S              29
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___M 0x10000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___S              28
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___M 0x08000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___S              27
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___M 0x04000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___S              26
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___M 0x02000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___S              25
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___M 0x01000000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___S              24
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___M 0x00800000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___S              23
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___M 0x00400000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___S              22
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___M 0x00200000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___S              21
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___M 0x00100000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___S              20
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___M 0x00080000
#define   PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___S              19
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___M 0x00040000
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___S              18
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___M 0x00020000
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___S              17
#define   PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___M 0x00010000
#define   PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___S              16
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___M 0x00008000
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___S              15
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___M 0x00004000
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___S              14
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___M 0x00002000
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___S              13
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___M 0x00001000
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___S              12
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___M 0x00000800
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___S              11
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___M 0x00000400
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___S              10
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___M 0x00000200
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___S               9
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___M 0x00000100
#define   PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___S               8
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___M 0x00000080
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___S               7
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___M 0x00000040
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___S               6
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___M 0x00000020
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___S               5
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___M 0x00000010
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___S               4
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___M 0x00000008
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___S               3
#define   PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___M 0x00000004
#define   PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___S               2
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___M 0x00000002
#define   PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___S               1
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___M 0x00000001
#define   PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___S               0
#define   PHYA_ROBE_ERROR_V2_MASK_U___M          0xFFFFFFFF   
#define   PHYA_ROBE_ERROR_V2_MASK_U___S                        0

#define PHYA_ROBE_DEBUG_STATUS_14_L               (0x004B5020)
#define   PHYA_ROBE_DEBUG_STATUS_14_L___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_14_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___S               0
#define   PHYA_ROBE_DEBUG_STATUS_14_L___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_14_L___S                      0

#define PHYA_ROBE_DEBUG_STATUS_14_U               (0x004B5024)
#define   PHYA_ROBE_DEBUG_STATUS_14_U___RWC         QCSR_REG_RO    
#define   PHYA_ROBE_DEBUG_STATUS_14_U___POR      0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___POR 0x00000000
#define   PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___M 0xFFFFFFFF
#define   PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___S               0
#define   PHYA_ROBE_DEBUG_STATUS_14_U___M        0xFFFFFFFF   
#define   PHYA_ROBE_DEBUG_STATUS_14_U___S                      0

#define PHYA_ROBE_ROBE_HW_CONTROL_5_L             (0x004B5028)
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L___POR    0x00000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___POR 0x1
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___M 0x01000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___M 0x00010000
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___M 0x00000100
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___M 0x00000001
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L___M      0x01010101   
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_L___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_5_U             (0x004B502C)
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U___POR    0x02051400
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___POR 0x02
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___POR 0x05
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___POR 0x14
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___M 0x3F000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___M 0x003F0000
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___M 0x00003F00
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___M 0x00000001
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U___M      0x3F3F3F01   
#define   PHYA_ROBE_ROBE_HW_CONTROL_5_U___S                    0

#define PHYA_ROBE_ROBE_HW_CONTROL_6_L             (0x004B5030)
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L___POR    0x0F000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___POR 0x0F
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___POR 0x0
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___M 0xFF000000
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___S              24
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___M 0x00010000
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___S              16
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___M 0x00000F00
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___S               8
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___M 0x0000000F
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___S               0
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L___M      0xFF010F0F   
#define   PHYA_ROBE_ROBE_HW_CONTROL_6_L___S                    0

#define PHYA_ROBE_CG_CONTROL_2_L                  (0x004B5038)
#define   PHYA_ROBE_CG_CONTROL_2_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_2_L___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___M 0x01000000
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___S              24
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___S              16
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___S               8
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___S               0
#define   PHYA_ROBE_CG_CONTROL_2_L___M           0x01010101   
#define   PHYA_ROBE_CG_CONTROL_2_L___S                         0

#define PHYA_ROBE_CG_CONTROL_2_U                  (0x004B503C)
#define   PHYA_ROBE_CG_CONTROL_2_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_2_U___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___M 0x01000000
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___S              24
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___S              16
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___S               8
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___S               0
#define   PHYA_ROBE_CG_CONTROL_2_U___M           0x01010101   
#define   PHYA_ROBE_CG_CONTROL_2_U___S                         0

#define PHYA_ROBE_CG_CONTROL_3_L                  (0x004B5040)
#define   PHYA_ROBE_CG_CONTROL_3_L___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_3_L___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___M 0x01000000
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___S              24
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___M 0x00010000
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___S              16
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___S               8
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___S               0
#define   PHYA_ROBE_CG_CONTROL_3_L___M           0x01010101   
#define   PHYA_ROBE_CG_CONTROL_3_L___S                         0

#define PHYA_ROBE_CG_CONTROL_3_U                  (0x004B5044)
#define   PHYA_ROBE_CG_CONTROL_3_U___RWC            QCSR_REG_RW    
#define   PHYA_ROBE_CG_CONTROL_3_U___POR         0x00000000
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___POR 0x0
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___M 0x00000100
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___S               8
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___M 0x00000001
#define   PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___S               0
#define   PHYA_ROBE_CG_CONTROL_3_U___M           0x00000101   
#define   PHYA_ROBE_CG_CONTROL_3_U___S                         0

#define PHYA_ROBE_DEBUG_CONTROL_4_L               (0x004B5048)
#define   PHYA_ROBE_DEBUG_CONTROL_4_L___RWC         QCSR_REG_RW    
#define   PHYA_ROBE_DEBUG_CONTROL_4_L___POR      0x00000000
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___POR 0x00
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___POR 0x0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___M 0x003FC000
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___S              14
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___M 0x00002000
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___S              13
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___M 0x00001000
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___S              12
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___M 0x00000F00
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___S               8
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___M 0x000000F0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___S               4
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___M 0x0000000F
#define   PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___S               0
#define   PHYA_ROBE_DEBUG_CONTROL_4_L___M        0x003FFFFF   
#define   PHYA_ROBE_DEBUG_CONTROL_4_L___S                      0

#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L            (0x004B5050)
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L___POR   0x0A08090C
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___POR 0x08
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___POR 0x09
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_L___S                   0

#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U            (0x004B5054)
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_LST_0_U___S                   0

#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L            (0x004B5058)
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_L___S                   0

#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U            (0x004B505C)
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUM_LST_1_U___S                   0

#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L            (0x004B5060)
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L___POR   0x0A08090C
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___POR 0x08
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___POR 0x09
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_L___S                   0

#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U            (0x004B5064)
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_LST_0_U___S                   0

#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L            (0x004B5068)
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_L___S                   0

#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U            (0x004B506C)
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U___RWC      QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U___POR   0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U___M     0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_MUO_LST_1_U___S                   0

#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L        (0x004B5070)
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___POR 0x0A08090C
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___POR 0x08
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___POR 0x09
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___POR 0x0C
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___S              24
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___S              16
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___S               8
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___S               0
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___S               0

#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U        (0x004B5074)
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___POR 0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___S              24
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___S              16
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___S               8
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___S               0
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___S               0

#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L        (0x004B5078)
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___POR 0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___S              24
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___S              16
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___S               8
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___S               0
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___S               0

#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U        (0x004B507C)
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___RWC  QCSR_REG_RW    
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___POR 0x0A0A0A0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___POR 0x0A
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___M 0xFF000000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___S              24
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___M 0x00FF0000
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___S              16
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___M 0x0000FF00
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___S               8
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___M 0x000000FF
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___S               0
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___M 0xFFFFFFFF   
#define   PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___S               0

#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L             (0x004B5080)
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L___POR    0x01010101
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___M 0x01000000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___S              24
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___M 0x00010000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___M 0x00000100
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___S               8
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___M 0x00000001
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L___M      0x01010101   
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_L___S                    0

#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U             (0x004B5084)
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U___POR    0x01010101
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___M 0x01000000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___S              24
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___M 0x00010000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___M 0x00000100
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___S               8
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___M 0x00000001
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U___M      0x01010101   
#define   PHYA_ROBE_SIG_INTG_CHK_EN_0_U___S                    0

#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L             (0x004B5088)
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L___POR    0x01010101
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___M 0x01000000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___S              24
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___M 0x00010000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___M 0x00000100
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___S               8
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___M 0x00000001
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L___M      0x01010101   
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_L___S                    0

#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U             (0x004B508C)
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U___POR    0x01010101
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___M 0x01000000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___S              24
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___M 0x00010000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___M 0x00000100
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___S               8
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___M 0x00000001
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U___M      0x01010101   
#define   PHYA_ROBE_SIG_INTG_CHK_EN_1_U___S                    0

#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L             (0x004B5090)
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L___RWC       QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L___POR    0x01010101
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___POR 0x1
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___M 0x01000000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___S              24
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___M 0x00010000
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___M 0x00000100
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___S               8
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___M 0x00000001
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L___M      0x01010101   
#define   PHYA_ROBE_SIG_INTG_CHK_EN_2_L___S                    0

#define PHYA_ROBE_SIG_INTG_CHK_THR_L              (0x004B5098)
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L___POR     0x0FFF0000
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___POR 0xFFF
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___POR 0x000
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___M 0x0FFF0000
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___S              16
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___M 0x00000FFF
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L___M       0x0FFF0FFF   
#define   PHYA_ROBE_SIG_INTG_CHK_THR_L___S                     0

#define PHYA_ROBE_SIG_INTG_CHK_THR_U              (0x004B509C)
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U___RWC        QCSR_REG_RW    
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U___POR     0x0000001F
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___POR 0x1F
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___M 0x0000007F
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___S               0
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U___M       0x0000007F   
#define   PHYA_ROBE_SIG_INTG_CHK_THR_U___S                     0

#define PHYA_ROBE_ADV_HW_CONTROL_L                (0x004B50A0)
#define   PHYA_ROBE_ADV_HW_CONTROL_L___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_ADV_HW_CONTROL_L___POR       0x00000000
#define   PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___POR 0x0000
#define   PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___POR 0x0
#define   PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___POR 0x00
#define   PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___M 0xFFFF0000
#define   PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___S              16
#define   PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___M 0x00000100
#define   PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___S               8
#define   PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___M 0x000000FF
#define   PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___S               0
#define   PHYA_ROBE_ADV_HW_CONTROL_L___M         0xFFFF01FF   
#define   PHYA_ROBE_ADV_HW_CONTROL_L___S                       0

#define PHYA_ROBE_ADV_HW_CONTROL_U                (0x004B50A4)
#define   PHYA_ROBE_ADV_HW_CONTROL_U___RWC          QCSR_REG_RW    
#define   PHYA_ROBE_ADV_HW_CONTROL_U___POR       0x00000000
#define   PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___POR 0x0000
#define   PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___POR 0x0
#define   PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___M 0x3FFF0000
#define   PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___S              16
#define   PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___M 0x00000001
#define   PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___S               0
#define   PHYA_ROBE_ADV_HW_CONTROL_U___M         0x3FFF0001   
#define   PHYA_ROBE_ADV_HW_CONTROL_U___S                       0

#define PHYA_ROBE_ALIAS_DUMMY_L                   (0x004B7FF0)
#define   PHYA_ROBE_ALIAS_DUMMY_L___RWC             QCSR_REG_RW    
#define   PHYA_ROBE_ALIAS_DUMMY_L___POR          0x00000000
#define   PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___POR 0x0
#define   PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___M 0x00000001
#define   PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___S               0
#define   PHYA_ROBE_ALIAS_DUMMY_L___M            0x00000001   
#define   PHYA_ROBE_ALIAS_DUMMY_L___S                          0

#define PHYA_DEMFRONT_1_RESET_CTRL_L              (0x00500000)
#define   PHYA_DEMFRONT_1_RESET_CTRL_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RESET_CTRL_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___POR 0x0
#define   PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___M 0x00000001
#define   PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___S               0
#define   PHYA_DEMFRONT_1_RESET_CTRL_L___M       0x00000001   
#define   PHYA_DEMFRONT_1_RESET_CTRL_L___S                     0

#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L          (0x00500008)
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___POR 0x00000000
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___S               0
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___S                 0

#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U          (0x0050000C)
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___POR 0x00000000
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___S               0
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___S                 0

#define PHYA_DEMFRONT_1_EVENT_STATUS_L            (0x00500010)
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L___POR   0x000000C4
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___M 0x00008000
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___S              15
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___M 0x00004000
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___S              14
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___M 0x00002000
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___S              13
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___M 0x00001000
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___S              12
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___M 0x00000800
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___S              11
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___M 0x00000400
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___S              10
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___M 0x00000100
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___S               8
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___M 0x00000080
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___S               7
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___M 0x00000040
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___S               6
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___M 0x00000020
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___S               5
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___M 0x00000010
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___S               4
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___M 0x00000008
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___S               3
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___M 0x00000004
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___S               2
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___M 0x00000002
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___S               1
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___S               0
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L___M     0x0000FDFF   
#define   PHYA_DEMFRONT_1_EVENT_STATUS_L___S                   0

#define PHYA_DEMFRONT_1_EVENT_MASK_L              (0x00500018)
#define   PHYA_DEMFRONT_1_EVENT_MASK_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_EVENT_MASK_L___POR     0x0000FDFF
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___M 0x00008000
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___S              15
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___M 0x00004000
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___S              14
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___M 0x00002000
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___S              13
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___M 0x00001000
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___S              12
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___M 0x00000800
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___S              11
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___M 0x00000400
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___S              10
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___M 0x00000100
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___S               8
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___M 0x00000080
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___S               7
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___M 0x00000040
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___S               6
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___M 0x00000020
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___S               5
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___M 0x00000010
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___S               4
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___M 0x00000008
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___S               3
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___M 0x00000004
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___S               2
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___S               1
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001
#define   PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___S               0
#define   PHYA_DEMFRONT_1_EVENT_MASK_L___M       0x0000FDFF   
#define   PHYA_DEMFRONT_1_EVENT_MASK_L___S                     0

#define PHYA_DEMFRONT_1_ERROR_MASK_L              (0x00500020)
#define   PHYA_DEMFRONT_1_ERROR_MASK_L___RWC        QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_ERROR_MASK_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___POR 0x00
#define   PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___M 0x0000003F
#define   PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___S               0
#define   PHYA_DEMFRONT_1_ERROR_MASK_L___M       0x0000003F   
#define   PHYA_DEMFRONT_1_ERROR_MASK_L___S                     0

#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L      (0x00500028)
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___M 0x80000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___S              31
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___M 0x40000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___S              30
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___M 0x10000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___S              28
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___M 0x08000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___S              27
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___M 0x04000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___S              26
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___M 0x01000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___S              24
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___M 0x00800000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___S              23
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___M 0x00400000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___S              22
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___M 0x00200000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___S              21
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___M 0x00100000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___S              20
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___M 0x00080000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___S              19
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___M 0x00010000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___S              16
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___M 0x00008000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___S              15
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___M 0x00004000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___S              14
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___M 0x00002000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___S              13
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___M 0x00001000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___S              12
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___M 0x00000800
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___S              11
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___M 0x00000400
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___S              10
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___M 0x00000200
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___S               9
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___M 0x00000100
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___S               8
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___M 0x00000040
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___S               6
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___M 0x00000020
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___S               5
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___M 0x00000010
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___S               4
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___M 0x00000008
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___S               3
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___M 0x00000004
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___S               2
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___M 0x00000002
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___S               1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___M 0x00000001
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___S               0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___M 0xDDF9FF7F   
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___S               0

#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U      (0x0050002C)
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___POR 0x0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___M 0x80000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___S              31
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___M 0x40000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___S              30
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___M 0x20000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___S              29
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___M 0x10000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___S              28
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___M 0x08000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___S              27
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___M 0x04000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___S              26
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___M 0x02000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___S              25
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___M 0x01000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___S              24
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___M 0x00800000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___S              23
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___M 0x00400000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___S              22
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___M 0x00200000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___S              21
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___M 0x00100000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___S              20
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___M 0x00080000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___S              19
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___M 0x00040000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___S              18
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___M 0x00020000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___S              17
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___M 0x00010000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___S              16
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___M 0x00008000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___S              15
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___M 0x00004000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___S              14
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___M 0x00002000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___S              13
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___M 0x00001000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___S              12
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___M 0x00000800
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___S              11
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___M 0x00000400
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___S              10
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___M 0x00000200
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___S               9
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___M 0x00000100
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___S               8
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___M 0x00000080
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___S               7
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___M 0x00000010
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___S               4
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___M 0x00000008
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___S               3
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___M 0x00000004
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___S               2
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___M 0x00000002
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___S               1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___M 0x00000001
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___S               0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___M 0xFFFFFF9F   
#define   PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___S               0

#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L        (0x00500030)
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___POR 0xDDF9FF7F
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___M 0x80000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___S              31
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___M 0x40000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___S              30
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___M 0x10000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___S              28
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___M 0x08000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___S              27
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___M 0x04000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___S              26
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___M 0x01000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___S              24
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___M 0x00800000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___S              23
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___M 0x00400000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___S              22
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___M 0x00200000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___S              21
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___M 0x00100000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___S              20
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___M 0x00080000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___S              19
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___M 0x00010000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___S              16
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___M 0x00008000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___S              15
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___M 0x00004000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___S              14
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___M 0x00002000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___S              13
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___M 0x00001000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___S              12
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___M 0x00000800
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___S              11
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___M 0x00000400
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___S              10
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___M 0x00000200
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___S               9
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___M 0x00000100
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___S               8
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___M 0x00000040
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___S               6
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___M 0x00000020
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___S               5
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___M 0x00000010
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___S               4
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___M 0x00000008
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___S               3
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___M 0x00000004
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___S               2
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___M 0x00000002
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___S               1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___M 0x00000001
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___S               0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___M 0xDDF9FF7F   
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___S               0

#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U        (0x00500034)
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___POR 0xFFFFFF9F
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___POR 0x1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___M 0x80000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___S              31
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___M 0x40000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___S              30
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___M 0x20000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___S              29
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___M 0x10000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___S              28
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___M 0x08000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___S              27
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___M 0x04000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___S              26
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___M 0x02000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___S              25
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___M 0x01000000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___S              24
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___M 0x00800000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___S              23
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___M 0x00400000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___S              22
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___M 0x00200000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___S              21
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___M 0x00100000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___S              20
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___M 0x00080000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___S              19
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___M 0x00040000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___S              18
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___M 0x00020000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___S              17
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___M 0x00010000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___S              16
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___M 0x00008000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___S              15
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___M 0x00004000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___S              14
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___M 0x00002000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___S              13
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___M 0x00001000
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___S              12
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___M 0x00000800
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___S              11
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000400
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___S              10
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000200
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___S               9
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000100
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___S               8
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000080
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___S               7
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___M 0x00000010
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___S               4
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___M 0x00000008
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___S               3
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___M 0x00000004
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___S               2
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___M 0x00000002
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___S               1
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___M 0x00000001
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___S               0
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___M 0xFFFFFF9F   
#define   PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L    (0x00500038)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___POR 0x01000034
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___POR 0x1
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___POR 0x034
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___M 0x07000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___M 0x001F0000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___M 0x000003FF
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___M 0x071F03FF   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U    (0x0050003C)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___POR 0x00640000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___POR 0x064
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___M 0x01FF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___M 0x01FF0007   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L    (0x00500040)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___POR 0xFFE6FFE6
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___POR 0xFFE6
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___POR 0xFFE6
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L    (0x00500048)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___POR 0x00010100
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___POR 0x1
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___POR 0x1
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___M 0x0F000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___M 0x0F010101   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U    (0x0050004C)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___POR 0x00001003
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___POR 0x10
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___POR 0x03
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___M 0x0F000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___M 0x00070000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___M 0x00003F00
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___M 0x0000001F
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___M 0x0F073F1F   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L    (0x00500050)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___POR 0x000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___M 0x000003FF
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___M 0x010103FF   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U    (0x00500054)
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___M 0x01010101   
#define   PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L             (0x00500058)
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L___POR    0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___POR 0x01
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___M 0xFF000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___M 0x00FF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_L___S                    0

#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U             (0x0050005C)
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___M 0xFF000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___M 0x00FF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_CMD_U___S                    0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L          (0x00500060)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___POR 0xFFF9FFEB
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___POR 0xFFF9
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___POR 0xFFEB
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U          (0x00500064)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___POR 0x00150007
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___POR 0x0015
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___POR 0x0007
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L          (0x00500068)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U          (0x0050006C)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L          (0x00500070)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U          (0x00500074)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L          (0x00500078)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___S                 0

#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U          (0x0050007C)
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___S                 0

#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L (0x00500080)
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___M 0x07000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___S              24
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___S              16
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___M 0x00000F00
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___S               8
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___M 0x0000003F
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___M 0x07010F3F   
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U (0x00500084)
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___S               0

#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L (0x00500088)
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___M 0x07000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___S              24
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___M 0x00000F00
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___M 0x0000003F
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___M 0x07010F3F   
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U (0x0050008C)
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L       (0x005000A0)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U       (0x005000A4)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L       (0x005000D0)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U       (0x005000D4)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L    (0x005000D8)
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___M 0x00000001   
#define   PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L       (0x005000E0)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U       (0x005000E4)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L      (0x005000E8)
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___M 0x00000101   
#define   PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___S               0

#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L (0x005000F0)
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___M 0x00000700
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___M 0x00000707   
#define   PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L (0x00500100)
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___M 0x07000000
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___S              24
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___M 0x00070000
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___S              16
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___M 0x00000700
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___S               0

#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U (0x00500104)
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___M 0x00000700
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___S               8
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___M 0x00000007
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___S               0
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___M 0x00000707   
#define   PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L       (0x00500108)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U       (0x0050010C)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L  (0x00500110)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U  (0x00500114)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L  (0x00500118)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U  (0x0050011C)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L   (0x00500128)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___POR 0x00040000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___POR 0x4
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___M 0x00070000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___M 0x01070000   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___S              16

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U   (0x0050012C)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___M 0x0101FFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L   (0x00500130)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U   (0x00500134)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L   (0x00500138)
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___M 0x00000001   
#define   PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L     (0x00500140)
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___M 0x01010101   
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U     (0x00500144)
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___M 0x00000001   
#define   PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L   (0x00500148)
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___M 0x01000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___M 0x00010000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___M 0x0000001F
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___M 0x0101011F   
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U   (0x0050014C)
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___POR 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___POR 0x000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___POR 0x1
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___M 0x03FF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___M 0x00000003
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___M 0x03FF0103   
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L   (0x00500150)
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___M 0x0000000F
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___M 0xFFFF010F   
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U   (0x00500154)
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L       (0x00500158)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U       (0x0050015C)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L       (0x00500160)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L       (0x00500168)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L       (0x00500170)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___M 0x00000101   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L       (0x00500178)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___M 0x3FFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___M 0x00003FFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___M 0x3FFF3FFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L       (0x00500180)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___M 0x3FFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___M 0x00003FFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___M 0x3FFF3FFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L       (0x00500188)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___M 0x00000300
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___M 0x00000003
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___M 0x00000303   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L       (0x00500198)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___M 0x00000100
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___M 0x00000001
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___M 0x00000101   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U        (0x005001A4)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L        (0x005001A8)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U        (0x005001AC)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L        (0x005001B0)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U        (0x005001B4)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___M 0x000000FF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___M 0xFFFF00FF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L        (0x005001B8)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___M 0x000F0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___M 0x000FFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L        (0x005001C0)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U        (0x005001C4)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L        (0x005001C8)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___POR 0x00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___M 0x00FF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___M 0x00FFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U        (0x005001CC)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___POR 0x0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___S               0

#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L          (0x005001D0)
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___POR 0x0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___M 0x0F000000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___S              24
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___M 0x00030000
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___S              16
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___M 0x00000F00
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___S               8
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___M 0x00000003
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___M   0x0F030F03   
#define   PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___S                 0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L       (0x005001D8)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U       (0x005001DC)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L       (0x005001E0)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___S               0

#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U       (0x005001E4)
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___S               0

#define PHYA_DEMFRONT_1_USER_SPARE_0_L            (0x005001E8)
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_0_L___S                   0

#define PHYA_DEMFRONT_1_USER_SPARE_0_U            (0x005001EC)
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_0_U___S                   0

#define PHYA_DEMFRONT_1_RU_BD_EVM0_L              (0x005001F0)
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM0_U              (0x005001F4)
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM0_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM1_L              (0x005001F8)
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM1_U              (0x005001FC)
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM1_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM2_L              (0x00500200)
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM2_U              (0x00500204)
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM2_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM3_L              (0x00500208)
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM3_U              (0x0050020C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM3_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM4_L              (0x00500210)
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM4_U              (0x00500214)
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM4_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM5_L              (0x00500218)
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM5_U              (0x0050021C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM5_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM6_L              (0x00500220)
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM6_U              (0x00500224)
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM6_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM7_L              (0x00500228)
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM7_U              (0x0050022C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM7_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM8_L              (0x00500230)
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM8_U              (0x00500234)
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM8_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM9_L              (0x00500238)
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_L___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM9_U              (0x0050023C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM9_U___S                     0

#define PHYA_DEMFRONT_1_RU_BD_EVM10_L             (0x00500240)
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM10_U             (0x00500244)
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM10_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM11_L             (0x00500248)
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM11_U             (0x0050024C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM11_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM12_L             (0x00500250)
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM12_U             (0x00500254)
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM12_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM13_L             (0x00500258)
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM13_U             (0x0050025C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM13_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM14_L             (0x00500260)
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM14_U             (0x00500264)
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM14_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM15_L             (0x00500268)
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_EVM15_U             (0x0050026C)
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___S               0
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_RU_BD_EVM15_U___S                    0

#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L             (0x00500270)
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L___RWC       QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___M 0x0FFF0000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___M 0x00000FFF
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L___M      0x0FFF0FFF   
#define   PHYA_DEMFRONT_1_RU_BD_QRE_0_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L             (0x00500278)
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L___RWC       QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___M 0x0FFF0000
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___M 0x00000FFF
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L___M      0x0FFF0FFF   
#define   PHYA_DEMFRONT_1_RU_BD_QRE_1_L___S                    0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L           (0x005003F0)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___POR 0x0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___M 0x00000001
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___M    0x00000001   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L           (0x005003F8)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___S               8
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L           (0x00500400)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___S               8
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L           (0x00500408)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___POR 0x00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___S               8
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___M    0x0000FFFF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L           (0x00500410)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L           (0x00500418)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L           (0x00500420)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L           (0x00500428)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L           (0x00500430)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L           (0x00500438)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___RWC     QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___M    0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___S                  0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L          (0x00500440)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___RWC    QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___M   0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___S                 0

#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L          (0x00500448)
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___RWC    QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___POR 0x000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___M 0x07FF0000
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___S              16
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___M 0x000007FF
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___S               0
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___M   0x07FF07FF   
#define   PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___S                 0

#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n(n) (0x005004B8+0x8*(n))
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n___POR   0x00000000
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___S               0
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_n___S                   0
#define PHYA_DEMFRONT_1_SDF_BUFFER_L_0            (0x005004B8)
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_0___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_0__SDF_BUFFER_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SDF_BUFFER_L_0__SDF_BUFFER_0___S               0

#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n(n) (0x005004BC+0x8*(n))
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n___POR   0x00000000
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___S               0
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_n___S                   0
#define PHYA_DEMFRONT_1_SDF_BUFFER_U_0            (0x005004BC)
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_0___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_0__SDF_BUFFER_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SDF_BUFFER_U_0__SDF_BUFFER_1___S               0

#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L           (0x005004C0)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___M 0x03000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L___M    0x03010101   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U           (0x005004C4)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U___POR  0x00000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___M 0x3F000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___M 0x003F0000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___M 0x000000FF
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U___M    0x3F3FFFFF   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L           (0x005004C8)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___M 0x01000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L___M    0x01010101   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U           (0x005004CC)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U___POR  0x00000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___M 0x07000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U___M    0x07010101   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_1_U___S                  0

#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L           (0x005004D0)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L___POR  0x01000002
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___POR 0x2
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___M 0x01000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___M 0x0000000F
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L___M    0x0101010F   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_L___S                  0

#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U           (0x005004D4)
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U___POR  0x04010101
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___POR 0x4
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___POR 0x1
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___M 0x0F000000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___S              24
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___S              16
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___S               8
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___S               0
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U___M    0x0F010101   
#define   PHYA_DEMFRONT_1_SYM_CONTROL_2_U___S                  0

#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L           (0x005004D8)
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L___POR  0x30000000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___POR 0x30
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___M 0x3F000000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___S              24
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___M 0x00010000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___S              16
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___M 0x00000001
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___S               0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L___M    0x3F010001   
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U           (0x005004DC)
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U___POR  0x00003000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___POR 0x30
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___M 0x01000000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___S              24
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___M 0x00010000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___S              16
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___M 0x00003F00
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___S               8
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___M 0x00000001
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___S               0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U___M    0x01013F01   
#define   PHYA_DEMFRONT_1_MRC_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L           (0x005004E0)
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L___POR  0x08000000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___POR 0x8
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___POR 0x0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___M 0x0F000000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___S              24
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___M 0x00010000
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___S              16
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___M 0x00000300
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___S               8
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___M 0x00000001
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___S               0
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L___M    0x0F010301   
#define   PHYA_DEMFRONT_1_MRC_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_1_USER_SPARE_1_L            (0x005004E8)
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_1_L___S                   0

#define PHYA_DEMFRONT_1_USER_SPARE_1_U            (0x005004EC)
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_1_U___S                   0

#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L       (0x005004F0)
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___POR 0x0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___POR 0x0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___POR 0x0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___POR 0x0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___M 0x01000000
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___S              24
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___M 0x00010000
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___S              16
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___M 0x00000100
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___S               8
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___M 0x00000001
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___S               0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___M 0x01010101   
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___S               0

#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U       (0x005004F4)
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___POR 0x0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___M 0x00000001
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___S               0
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___M 0x00000001   
#define   PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___S               0

#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L      (0x005004F8)
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L      (0x00500500)
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U      (0x00500504)
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L      (0x00500508)
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L      (0x00500510)
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L      (0x00500518)
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U      (0x0050051C)
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L      (0x00500520)
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L      (0x00500528)
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L      (0x00500530)
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U      (0x00500534)
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L      (0x00500538)
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L      (0x00500540)
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L      (0x00500548)
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U      (0x0050054C)
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L      (0x00500550)
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L      (0x00500558)
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L      (0x00500560)
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U      (0x00500564)
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L      (0x00500568)
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L      (0x00500570)
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L      (0x00500578)
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U      (0x0050057C)
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L      (0x00500580)
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L      (0x00500588)
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L      (0x00500590)
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U      (0x00500594)
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L      (0x00500598)
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L      (0x005005A0)
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___POR 0x000001FF
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___POR 0x01FF
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___S               0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L      (0x005005A8)
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___M 0x07000000
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___S              24
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___M 0x00070000
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___S              16
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___M 0x00000700
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___S               8
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___M 0x07070707   
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U      (0x005005AC)
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___M 0x00000007
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___S               0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___M 0x00000007   
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L      (0x005005B0)
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___POR 0x00
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___POR 0x00
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___S               8
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___M 0x000000FF
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___S               0
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L           (0x005005B8)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L___POR  0x02000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___POR 0x2
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___M 0x03000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___M 0x00070000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___M 0x00000F00
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___M 0x00000003
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L___M    0x03070F03   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_L___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U           (0x005005BC)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___M 0x01000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___M 0x00000100
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U___M    0x01010101   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_0_U___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L           (0x005005C0)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L___POR  0x02000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___POR 0x200
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___M 0x03FF0000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___M 0x00000300
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L___M    0x03FF0301   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_L___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U           (0x005005C4)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___M 0x01000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___M 0x00000100
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U___M    0x01010101   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_1_U___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L           (0x005005C8)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___M 0x01000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___M 0x00000100
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L___M    0x01010101   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_L___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U           (0x005005CC)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___M 0x07000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___M 0x00000100
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U___M    0x07010101   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_2_U___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L           (0x005005D0)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___M 0x03000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___M 0x00000700
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L___M    0x03010701   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_L___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U           (0x005005D4)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U___POR  0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___POR 0x1
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___POR 0x000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___M 0x0F000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___M 0x000003FF
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U___M    0x0F0103FF   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_3_U___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L           (0x005005D8)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L___POR  0x00000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___POR 0x0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___M 0x00030000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___M 0x00000300
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___S               8
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___M 0x00000001
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L___M    0x00030301   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_L___S                  0

#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U           (0x005005DC)
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U___RWC     QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U___POR  0x01010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___POR 0x1
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___POR 0x1
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___POR 0x000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___M 0x01000000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___S              24
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___M 0x00010000
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___S              16
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___M 0x000003FF
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___S               0
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U___M    0x010103FF   
#define   PHYA_DEMFRONT_1_CHE_CONTROL_4_U___S                  0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L       (0x005005E0)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___POR 0x000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___POR 0x0000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___M 0x03FF0000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___M 0x00007FFF
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___M 0x03FF7FFF   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U       (0x005005E4)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___POR 0x0000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___M 0x00000001
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___M 0xFFFF0001   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L       (0x005005E8)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U       (0x005005EC)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___M 0x01000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___S              24
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___M 0x00000300
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___S               8
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___M 0x00000001
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___M 0x01010301   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L       (0x005005F0)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___POR 0x00000300
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___POR 0x3
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___M 0x01000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___S              24
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___M 0x00000300
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___S               8
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___M 0x00000001
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___M 0x01010301   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U       (0x005005F4)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___M 0x00000100
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___S               8
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___M 0x00000001
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___M 0x00010101   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L       (0x005005F8)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___POR 0x000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___M 0x01000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___S              24
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___M 0x000003FF
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___M 0x010103FF   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U       (0x005005FC)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___POR 0x000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___M 0x01000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___S              24
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___M 0x000003FF
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___M 0x010103FF   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L       (0x00500600)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___POR 0x00
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___POR 0x0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___M 0x01000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___S              24
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___M 0x00010000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___S              16
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___M 0x00001F00
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___S               8
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___M 0x00000001
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___M 0x01011F01   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___S               0

#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U       (0x00500604)
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___POR 0x00000000
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___S               0
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___S               0

#define PHYA_DEMFRONT_1_USER_SPARE_2_L            (0x00500608)
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_2_L___S                   0

#define PHYA_DEMFRONT_1_USER_SPARE_2_U            (0x0050060C)
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_2_U___S                   0

#define PHYA_DEMFRONT_1_DCN_CONTROL_L             (0x00500610)
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L___POR    0x00000100
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___POR 0x1
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___POR 0x0
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___M 0x00030000
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___S              16
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___M 0x00000100
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___S               8
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___M 0x00000001
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___S               0
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L___M      0x00030101   
#define   PHYA_DEMFRONT_1_DCN_CONTROL_L___S                    0

#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L        (0x00500618)
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___M 0x00000100
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___S               8
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___S               0
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___M 0x00000101   
#define   PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___S               0

#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L         (0x00500620)
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___RWC   QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___M 0x000000FF
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___S               0
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___M  0x000000FF   
#define   PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___S                0

#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L     (0x00500628)
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___POR 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___POR 0xFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___POR 0xFFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___M 0x0FFF0000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___S              16
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___S               0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L     (0x00500630)
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___S               0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U     (0x00500634)
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___S               0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___S               0

#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L     (0x00500638)
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___POR 0x0000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___M 0x01000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___S              24
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___M 0x00010000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___S              16
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___S               0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___M 0x0101FFFF   
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___S               0

#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U     (0x0050063C)
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___POR 0x00
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___POR 0x0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___M 0xFF000000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___S              24
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___M 0x00FF0000
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___S              16
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___S               8
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___M 0x00000001
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___S               0
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___M 0xFFFFFF01   
#define   PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___S               0

#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L        (0x00500640)
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___POR 0x00000080
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___POR 0x000
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___POR 0x00
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___POR 0x80
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___M 0x03FF0000
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___S              16
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___S               8
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___S               0
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___M 0x03FFFFFF   
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___S               0

#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L        (0x00500648)
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___POR 0x00000080
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___POR 0x000
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___POR 0x00
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___POR 0x80
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___M 0x03FF0000
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___S              16
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___S               8
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___M 0x000000FF
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___S               0
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___M 0x03FFFFFF   
#define   PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___S               0

#define PHYA_DEMFRONT_1_NOISE_PWR_0_L             (0x00500660)
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___POR 0x0
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___POR 0x0
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___POR 0x0
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___M 0x00010000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___S              16
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___M 0x00000100
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___S               8
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___M 0x00000001
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___S               0
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L___M      0x00010101   
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_L___S                    0

#define PHYA_DEMFRONT_1_NOISE_PWR_0_U             (0x00500664)
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___POR 0x000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___S              16
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___M 0x000003FF
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___S               0
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U___M      0xFFFF03FF   
#define   PHYA_DEMFRONT_1_NOISE_PWR_0_U___S                    0

#define PHYA_DEMFRONT_1_NOISE_PWR_1_L             (0x00500668)
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___POR 0x0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___S              16
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___S               0
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L___M      0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_L___S                    0

#define PHYA_DEMFRONT_1_NOISE_PWR_1_U             (0x0050066C)
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U___POR    0x00000000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___POR 0x0
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___POR 0x00
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___POR 0x00
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___POR 0x00
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___M 0x0F000000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___S              24
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___M 0x003F0000
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___S              16
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___M 0x00003F00
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___S               8
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___M 0x000000FF
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___S               0
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U___M      0x0F3F3FFF   
#define   PHYA_DEMFRONT_1_NOISE_PWR_1_U___S                    0

#define PHYA_DEMFRONT_1_USER_SPARE_3_L            (0x00500670)
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_3_L___S                   0

#define PHYA_DEMFRONT_1_USER_SPARE_3_U            (0x00500674)
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U___POR   0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___S               0
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U___M     0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_USER_SPARE_3_U___S                   0

#define PHYA_DEMFRONT_1_SCSR_CHE0_L               (0x00500678)
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE0_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE1_L               (0x00500680)
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE1_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE2_L               (0x00500688)
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE2_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE3_L               (0x00500690)
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE3_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE4_L               (0x00500698)
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE4_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE5_L               (0x005006A0)
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE5_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE6_L               (0x005006A8)
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE6_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_CHE7_L               (0x005006B0)
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L___M        0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_CHE7_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_LLR_0_L              (0x005006B8)
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___S               0
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L___M       0x00000001   
#define   PHYA_DEMFRONT_1_SCSR_LLR_0_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_LLR_1_L              (0x005006C0)
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___S               0
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L___M       0x00000001   
#define   PHYA_DEMFRONT_1_SCSR_LLR_1_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_LLR_2_L              (0x005006C8)
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L___POR     0x00007F01
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___POR 0x7F
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___S               8
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___S               0
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L___M       0x0000FF01   
#define   PHYA_DEMFRONT_1_SCSR_LLR_2_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_DLMU_L               (0x005006D0)
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___S              24
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___M 0x000F0000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___S              16
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___M 0x00000F00
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___S               8
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___M 0x0000003F
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___S               0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L___M        0x070F0F3F   
#define   PHYA_DEMFRONT_1_SCSR_DLMU_L___S                      0

#define PHYA_DEMFRONT_1_SCSR_DLMU_U               (0x005006D4)
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U___POR      0x00000000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___M 0x03000000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___S              24
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___S              16
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___S               8
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___S               0
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U___M        0x03070701   
#define   PHYA_DEMFRONT_1_SCSR_DLMU_U___S                      0

#define PHYA_DEMFRONT_1_CBFG_CFG_0_L              (0x005006D8)
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___M 0x07000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___S              24
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___M 0x00030000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___M 0x00000300
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___M 0x00000001
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L___M       0x07030301   
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_0_U              (0x005006DC)
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___M 0x07000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___S              24
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___M 0x00070000
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___M 0x00000100
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___M 0x00000001
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U___M       0x07070101   
#define   PHYA_DEMFRONT_1_CBFG_CFG_0_U___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_1_L              (0x005006E0)
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L___POR     0x000A0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___POR 0xA
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___M 0x3F000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___S              24
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___M 0x000F0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___M 0x00003F00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___M 0x0000003F
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L___M       0x3F0F3F3F   
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_1_U              (0x005006E4)
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U___POR     0x000C0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___POR 0x0C
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___M 0x00FF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___M 0x0000FF00
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___M 0x000000FF
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U___M       0x00FFFFFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_1_U___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_2_L              (0x005006E8)
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___POR 0x000
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___POR 0x000
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___M 0x03FF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___M 0x000003FF
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L___M       0x03FF03FF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_2_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_3_L              (0x005006F0)
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___M 0x0000FF00
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___M 0x000000FF
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L___M       0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_3_U              (0x005006F4)
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U___POR     0x00000E00
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___POR 0x000
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___POR 0x0E
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___M 0x0FFF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___M 0x00001F00
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___M 0x0000000F
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U___M       0x0FFF1F0F   
#define   PHYA_DEMFRONT_1_CBFG_CFG_3_U___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_4_L              (0x005006F8)
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___POR 0x000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___M 0x1FFF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___M 0x00000FFF
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L___M       0x1FFF0FFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_4_U              (0x005006FC)
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___M 0x1FFF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___M 0x00001FFF
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U___M       0x1FFF1FFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_4_U___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_5_L              (0x00500700)
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___M 0x1FFF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___M 0x00001FFF
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L___M       0x1FFF1FFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG_5_U              (0x00500704)
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U___POR     0x00150000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___POR 0x00
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___POR 0x15
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___POR 0x0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___M 0xFF000000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___S              24
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___M 0x00FF0000
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___M 0x00001FFF
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U___M       0xFFFF1FFF   
#define   PHYA_DEMFRONT_1_CBFG_CFG_5_U___S                     0

#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L      (0x00500708)
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___POR 0x00010000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___POR 0x0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___POR 0x1
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___POR 0x0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___POR 0x0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___M 0x01000000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___S              24
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___M 0x00010000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___S              16
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___M 0x00000F00
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___S               8
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___M 0x00000007
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___S               0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___M 0x01010F07   
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U      (0x0050070C)
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___POR 0xFFFF0000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___POR 0xFFFF
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___S              16
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___M 0x00000100
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___S               8
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___M 0xFFFF0100   
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___S               8

#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L      (0x00500710)
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___POR 0x00050100
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___POR 0x5
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___POR 0x1
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___POR 0x0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___M 0x00070000
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___S              16
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___M 0x00000100
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___S               8
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___M 0x00000001
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___S               0
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___M 0x00070101   
#define   PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SCSR_MRC_0_L              (0x00500718)
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L___POR     0x01070100
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___POR 0x7
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___M 0x01000000
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___S              24
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___S              16
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___M 0x00000300
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___S               8
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___M 0x00000003
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___S               0
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L___M       0x01070303   
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_MRC_0_U              (0x0050071C)
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U___POR     0x02580107
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___POR 0x0258
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___POR 0x7
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___S              16
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___S               8
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___S               0
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U___M       0xFFFF0107   
#define   PHYA_DEMFRONT_1_SCSR_MRC_0_U___S                     0

#define PHYA_DEMFRONT_1_SCSR_MRC_1_L              (0x00500720)
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L___POR     0x00000001
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___S               0
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L___M       0x00000001   
#define   PHYA_DEMFRONT_1_SCSR_MRC_1_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_MRC_2_L              (0x00500728)
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___M 0x00001F00
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___M 0x0000001F
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L___M       0x00001F1F   
#define   PHYA_DEMFRONT_1_SCSR_MRC_2_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_PTC_0_L              (0x00500730)
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___S              24
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___S              16
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___S               8
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___S               0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L___M       0x07070701   
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_PTC_0_U              (0x00500734)
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U___POR     0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___POR 0x1FF
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___M 0x01000000
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___S              24
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___M 0x00010000
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___S              16
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___S               0
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U___M       0x010101FF   
#define   PHYA_DEMFRONT_1_SCSR_PTC_0_U___S                     0

#define PHYA_DEMFRONT_1_SCSR_PTC_1_L              (0x00500738)
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L___POR     0x03000001
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___S              24
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___M 0x00010000
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___S              16
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___S               8
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___S               0
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L___M       0x07010101   
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_PTC_1_U              (0x0050073C)
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U___POR     0x00070302
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___POR 0x007
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___POR 0x03
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___M 0x03FF0000
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___S              16
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___M 0x00001F00
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___S               8
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___S               0
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U___M       0x03FF1F07   
#define   PHYA_DEMFRONT_1_SCSR_PTC_1_U___S                     0

#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L        (0x00500740)
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L        (0x00500748)
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U        (0x0050074C)
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L        (0x00500750)
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L        (0x00500758)
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U        (0x0050075C)
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L        (0x00500760)
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L        (0x00500768)
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U        (0x0050076C)
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L        (0x00500770)
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L        (0x00500778)
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U        (0x0050077C)
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L        (0x00500780)
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L        (0x00500788)
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U        (0x0050078C)
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L        (0x00500790)
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L        (0x00500798)
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U        (0x0050079C)
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L        (0x005007A0)
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L        (0x005007A8)
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U        (0x005007AC)
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L        (0x005007B0)
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___POR 0x0000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___S               0
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___M 0x0000FFFF   
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___S               0

#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L        (0x005007B8)
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___M 0x1F000000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___S              24
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___M 0x001F0000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___S              16
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___M 0x00001F00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___S               8
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___M 0x1F1F1F1F   
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___S               0

#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U        (0x005007BC)
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___POR 0x00
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___M 0x0000001F
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___S               0
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___M 0x0000001F   
#define   PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___S               0

#define PHYA_DEMFRONT_1_PTC_CONTROL_L             (0x005007C0)
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L___POR    0x00044E05
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___POR 0x004
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___POR 0x4E05
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___M 0x03FF0000
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___S              16
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___M 0x00007FFF
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___S               0
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L___M      0x03FF7FFF   
#define   PHYA_DEMFRONT_1_PTC_CONTROL_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_QRE_0_L              (0x005007C8)
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___M 0x0000000F
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___S               0
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L___M       0x0000000F   
#define   PHYA_DEMFRONT_1_SCSR_QRE_0_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_QRE_1_L              (0x005007D0)
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___M 0x0000000F
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___S               0
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L___M       0x0000000F   
#define   PHYA_DEMFRONT_1_SCSR_QRE_1_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_QRE_2_L              (0x005007D8)
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L___RWC        QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___POR 0x000
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___M 0x000001FF
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___S               0
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L___M       0x000001FF   
#define   PHYA_DEMFRONT_1_SCSR_QRE_2_L___S                     0

#define PHYA_DEMFRONT_1_SCSR_QRE_3_L              (0x005007E0)
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L___RWC        QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L___POR     0x00000000
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___M 0x00003F00
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___M 0x0000003F
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L___M       0x00003F3F   
#define   PHYA_DEMFRONT_1_SCSR_QRE_3_L___S                     0

#define PHYA_DEMFRONT_1_CBFG_CFG1_L               (0x00500830)
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L___RWC         QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L___POR      0x00000000
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___POR 0x0
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___M 0x00010000
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___S              16
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___M 0x00000100
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___S               8
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___M 0x00000001
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___S               0
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L___M        0x00010101   
#define   PHYA_DEMFRONT_1_CBFG_CFG1_L___S                      0

#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L     (0x00500840)
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___POR 0x0
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___M 0x00000001
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___S               0
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___M 0x00000001   
#define   PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___S               0

#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L      (0x00500848)
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___POR 0x00000001
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___POR 0x1
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___M 0x00000001
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___S               0
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___M 0x00000001   
#define   PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___S               0

#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L             (0x00500850)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L___POR    0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___M 0x01000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___M 0x00010000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L___M      0x01010101   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U             (0x00500854)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U___POR    0x00010100
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___M 0x03000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___M 0x00010000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U___M      0x03010100   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_0_U___S                    8

#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L             (0x00500858)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L___POR    0x01010202
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U             (0x0050085C)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U___POR    0x02010101
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_1_U___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L             (0x00500860)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L___POR    0x02020303
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U             (0x00500864)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U___POR    0x03010102
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_2_U___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L             (0x00500868)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L___POR    0x02020202
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U             (0x0050086C)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U___POR    0x02010102
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_3_U___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L             (0x00500870)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L___POR    0x03030303
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_L___S                    0

#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U             (0x00500874)
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U___RWC       QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U___POR    0x03020203
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___POR 0x2
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___POR 0x3
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___M 0x07000000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___S              24
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___M 0x00070000
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___S              16
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___M 0x00000700
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___S               8
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___M 0x00000007
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___S               0
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U___M      0x07070707   
#define   PHYA_DEMFRONT_1_SCSR_CTRL_4_U___S                    0

#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L      (0x00500DA0)
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___POR 0x0020000C
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___POR 0x020
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___POR 0x0C
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___M 0x03FF0000
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___S              16
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___M 0x0000001F
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___M 0x03FF001F   
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___S               0

#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U      (0x00500DA4)
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___POR 0x00070100
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___POR 0x007
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___M 0x03FF0000
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___S              16
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___S               8
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___M 0x03FF0100   
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___S               8

#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L      (0x00500DA8)
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___POR 0x00000106
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___POR 0x1
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___POR 0x06
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___M 0x00030000
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___S              16
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___M 0x00000100
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___S               8
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___M 0x0000007F
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___S               0
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___M 0x0003017F   
#define   PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___S               0

#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L      (0x00500DB0)
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___POR 0x0
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___POR 0x00
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___M 0x01000000
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___S              24
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___M 0x00FF0000
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___S              16
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___M 0x0000FF00
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___S               8
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___M 0x000000FF
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___S               0
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___M 0x01FFFFFF   
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___S               0

#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U      (0x00500DB4)
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___RWC QCSR_REG_RO    
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___POR 0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___POR 0x00000000
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___S               0
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___S               0

#define PHYA_DEMFRONT_1_DC_MEM_L_n(n)    (0x00500DB8+0x8*(n))
#define   PHYA_DEMFRONT_1_DC_MEM_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_DC_MEM_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_DC_MEM_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_DC_MEM_L_n___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DC_MEM_L_n___POR       0x00000000
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___POR 0x0000
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___POR 0x0000
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___S              16
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___S               0
#define   PHYA_DEMFRONT_1_DC_MEM_L_n___M         0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_DC_MEM_L_n___S                       0
#define PHYA_DEMFRONT_1_DC_MEM_L_0                (0x00500DB8)
#define   PHYA_DEMFRONT_1_DC_MEM_L_0___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_1___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_1___S              16
#define   PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_0___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_0___S               0

#define PHYA_DEMFRONT_1_DC_MEM_U_n(n)    (0x00500DBC+0x8*(n))
#define   PHYA_DEMFRONT_1_DC_MEM_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_DC_MEM_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_DC_MEM_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_DC_MEM_U_n___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DC_MEM_U_n___POR       0x00000000
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___POR 0x0000
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___POR 0x0000
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___S              16
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___S               0
#define   PHYA_DEMFRONT_1_DC_MEM_U_n___M         0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_DC_MEM_U_n___S                       0
#define PHYA_DEMFRONT_1_DC_MEM_U_0                (0x00500DBC)
#define   PHYA_DEMFRONT_1_DC_MEM_U_0___RWC          QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_3___M 0xFFFF0000
#define   PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_3___S              16
#define   PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_2___M 0x0000FFFF
#define   PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_2___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n(n) (0x005015B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0       (0x005015B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n(n) (0x005015BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0       (0x005015BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n(n) (0x005035B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0     (0x005035B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n(n) (0x005035BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0     (0x005035BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n(n) (0x005055B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0    (0x005055B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n(n) (0x005055BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0    (0x005055BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n(n) (0x005075B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0    (0x005075B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n(n) (0x005075BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0    (0x005075BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n(n) (0x005095B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0       (0x005095B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n(n) (0x005095BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0       (0x005095BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n(n) (0x0050B5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0     (0x0050B5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n(n) (0x0050B5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0     (0x0050B5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n(n) (0x0050D5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0    (0x0050D5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n(n) (0x0050D5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0    (0x0050D5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n(n) (0x0050F5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0    (0x0050F5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n(n) (0x0050F5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0    (0x0050F5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n(n) (0x005115B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0       (0x005115B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n(n) (0x005115BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0       (0x005115BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n(n) (0x005135B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0     (0x005135B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n(n) (0x005135BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0     (0x005135BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n(n) (0x005155B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0    (0x005155B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n(n) (0x005155BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0    (0x005155BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n(n) (0x005175B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0    (0x005175B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n(n) (0x005175BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0    (0x005175BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n(n) (0x005195B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0       (0x005195B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n(n) (0x005195BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0       (0x005195BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n(n) (0x0051B5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0     (0x0051B5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n(n) (0x0051B5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0     (0x0051B5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n(n) (0x0051D5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0    (0x0051D5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n(n) (0x0051D5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0    (0x0051D5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n(n) (0x0051F5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0    (0x0051F5B8)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___S               0

#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n(n) (0x0051F5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___S               0
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___S               0
#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0    (0x0051F5BC)
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n(n) (0x005215B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0       (0x005215B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n(n) (0x005215BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0       (0x005215BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n(n) (0x005235B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0     (0x005235B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n(n) (0x005235BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0     (0x005235BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n(n) (0x005255B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0    (0x005255B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n(n) (0x005255BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0    (0x005255BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n(n) (0x005275B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0       (0x005275B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n(n) (0x005275BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0       (0x005275BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n(n) (0x005295B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0     (0x005295B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n(n) (0x005295BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0     (0x005295BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n(n) (0x0052B5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0    (0x0052B5B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n(n) (0x0052B5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0    (0x0052B5BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n(n) (0x0052D5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0       (0x0052D5B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n(n) (0x0052D5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0       (0x0052D5BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n(n) (0x0052F5B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0     (0x0052F5B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n(n) (0x0052F5BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0     (0x0052F5BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n(n) (0x005315B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0    (0x005315B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n(n) (0x005315BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0    (0x005315BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n(n) (0x005335B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0       (0x005335B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n(n) (0x005335BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0       (0x005335BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n(n) (0x005355B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0     (0x005355B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n(n) (0x005355BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0     (0x005355BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n(n) (0x005375B8+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0    (0x005375B8)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___S               0

#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n(n) (0x005375BC+0x8*(n))
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___S               0
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___S               0
#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0    (0x005375BC)
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___S               0

#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L      (0x005395D0)
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___S               0
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___S               0

#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L      (0x005395D8)
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___RWC QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___S               0
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___M 0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n(n) (0x005415E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0          (0x005415E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n(n) (0x005415E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0          (0x005415E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n(n) (0x005435E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0          (0x005435E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n(n) (0x005435E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0          (0x005435E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n(n) (0x005455E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0          (0x005455E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n(n) (0x005455E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0          (0x005455E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n(n) (0x005475E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0          (0x005475E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n(n) (0x005475E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0          (0x005475E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n(n) (0x005495E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0          (0x005495E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n(n) (0x005495E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0          (0x005495E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n(n) (0x0054B5E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0          (0x0054B5E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n(n) (0x0054B5E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0          (0x0054B5E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n(n) (0x0054D5E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0          (0x0054D5E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n(n) (0x0054D5E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0          (0x0054D5E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n(n) (0x0054F5E0+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0          (0x0054F5E0)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___S               0

#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n(n) (0x0054F5E4+0x8*(n))
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___POR 0x00000000
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___S               0
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___M   0xFFFFFFFF   
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___S                 0
#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0          (0x0054F5E4)
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0___RWC    QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___M 0xFFFFFFFF
#define   PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___S               0

#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L            (0x005615E0)
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___RWC      QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___POR   0x00000000
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___POR 0x0
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___M 0x00000001
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___S               0
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___M     0x00000001   
#define   PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___S                   0

#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n(n) (0x005615E8+0x8*(n))
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___POR 0x0000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___S               0
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___S               0
#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0        (0x005615E8)
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___S               0

#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n(n) (0x005615EC+0x8*(n))
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___POR 0x0000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___S               0
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___S               0
#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0        (0x005615EC)
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___S               0

#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n(n) (0x00561868+0x8*(n))
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_nMIN 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_nMAX 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_ELEM 1    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___POR 0x0000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___S               0
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___S               0
#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0        (0x00561868)
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___S               0

#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n(n) (0x0056186C+0x8*(n))
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_nMIN 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_nMAX 0    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_ELEM 1    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___POR 0x00000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___POR 0x0000000
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___S               0
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___M 0x0FFFFFFF   
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___S               0
#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0        (0x0056186C)
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0___RWC  QCSR_REG_RW    
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___M 0x0FFFFFFF
#define   PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___S               0

#define PHYA_IRON2G_RFA_WSI_SYSCTRL               (0x005CF000)
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL___RWC         QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL___POR      0x00000000
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___S              11
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___S              10
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___S               2
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___S               1
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL___M        0x00000C07   
#define   PHYA_IRON2G_RFA_WSI_SYSCTRL___S                      0

#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK           (0x005CF004)
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___S               0
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___M    0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___S                  0

#define PHYA_IRON2G_RFA_WSI_SYS_STAT              (0x005CF008)
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT___RWC        QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT___POR     0x00000038
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___S              12
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___S               7
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___S               6
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___S               5
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___S               4
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___S               3
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___S               2
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT___M       0x0000F0FF   
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT___S                     0

#define PHYA_IRON2G_RFA_WSI_SYS_STAT1             (0x005CF00C)
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1___RWC       QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1___POR    0x00000000
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___S               8
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___S               0
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1___M      0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_SYS_STAT1___S                    0

#define PHYA_IRON2G_RFA_WSI_CHIP_ID               (0x005CF010)
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID___RWC         QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID___POR      0x00000100
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___POR 0x0100
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID___M        0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID___S                      0

#define PHYA_IRON2G_RFA_WSI_SYS_TEST              (0x005CF014)
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST___RWC        QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST___POR     0x0000ABCD
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___POR 0xABCD
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___S               0
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST___M       0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_SYS_TEST___S                     0

#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK            (0x005CF018)
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___POR   0x00000000
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___S               3
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___S               2
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___S               1
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___S               0
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___M     0x0000000F   
#define   PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___S                   0

#define PHYA_IRON2G_RFA_WSI_BOOT_MISC             (0x005CF01C)
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC___RWC       QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC___POR    0x00000000
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___S               3
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC___M      0x0000000F   
#define   PHYA_IRON2G_RFA_WSI_BOOT_MISC___S                    0

#define PHYA_IRON2G_RFA_WSI_PMU_CTRL              (0x005CF020)
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL___RWC        QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL___POR     0x00000000
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___S               8
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___S               0
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL___M       0x000003FF   
#define   PHYA_IRON2G_RFA_WSI_PMU_CTRL___S                     0

#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE          (0x005CF024)
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___S               0
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___M   0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___S                 0

#define PHYA_IRON2G_RFA_WSI_XO_SETTLE             (0x005CF028)
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE___RWC       QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE___POR    0x00000000
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE___M      0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_XO_SETTLE___S                    0

#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U             (0x005CF02C)
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U___RWC       QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U___POR    0x0000400C
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___POR 0x400C
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U___M      0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CHIP_ID_U___S                    0

#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL        (0x005CF030)
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___M 0x00000073   
#define   PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___S               0

#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE       (0x005CF034)
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___S              31
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___S              30
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___M 0x00006000
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___S              13
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___M 0x00001800
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___S              11
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___M 0x00000600
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___S               9
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___M 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___S               5
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___M 0x00000018
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___S               3
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___S               2
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___S               1
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___S               0
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___M 0xC0007FFF   
#define   PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___S               0

#define PHYA_IRON2G_RFA_WSI_CHICKEN               (0x005CF038)
#define   PHYA_IRON2G_RFA_WSI_CHICKEN___RWC         QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CHICKEN___POR      0x00000001
#define   PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___M  0x00000001
#define   PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___S                0
#define   PHYA_IRON2G_RFA_WSI_CHICKEN___M        0x00000001   
#define   PHYA_IRON2G_RFA_WSI_CHICKEN___S                      0

#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG   (0x005CF040)
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___S               0

#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG (0x005CF050)
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___POR 0x00332002
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___S              31
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___S              27
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S              20
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___S               6
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___S               3
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S               2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S               1
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___M 0xF8FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___S               0

#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1 (0x005CF054)
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___POR 0x00008060
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S              28
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S              26
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S              25
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S              24
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S              18
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S              15
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S               2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___S               0

#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2 (0x005CF058)
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___POR 0x0000222A
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___S               0

#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG (0x005CF05C)
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___POR 0x00003F3F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___POR 0x3F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___POR 0x3F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___M 0x00007F00
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___M 0x0000007F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___M 0x00007F7F   
#define   PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___S               0

#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG (0x005CF060)
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___POR 0x00222002
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___S              31
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___S              27
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S              20
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___S               6
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___S               3
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S               2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S               1
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___M 0xF8FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___S               0

#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1 (0x005CF064)
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___POR 0x00008060
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S              28
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S              26
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S              25
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S              24
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S              18
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S              15
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S               2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___S               0

#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2 (0x005CF068)
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___POR 0x0000222A
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___S               0

#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG (0x005CF070)
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___POR 0x00222002
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___S              31
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___S              27
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S              20
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S              16
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S              12
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S              11
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S              10
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___S               6
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___S               3
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S               2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S               1
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S               0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___M 0xF8FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___S               0

#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1 (0x005CF074)
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___POR 0x00008060
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S              28
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S              26
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S              25
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S              24
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S              18
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S              16
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S              15
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S              10
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S               7
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S               2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___S               0

#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2 (0x005CF078)
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___POR 0x0000222A
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S              16
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S              12
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S               8
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S               4
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S               0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___S               0

#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG (0x005CF080)
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___M 0xFC000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___S              26
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___S              24
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___S              23
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___S              22
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S              18
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___S              15
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___S              14
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S              13
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___S               6
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___S               0

#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG (0x005CF084)
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___S              31
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___S              30
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___S              29
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___S              28
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___S              27
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___S              26
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___S              24
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___S              23
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___S              22
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S              18
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___S              16
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___S              15
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___S              14
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S              13
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___S              12
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S              11
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S              10
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___S               8
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___S               7
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___S               6
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___S               5
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S               4
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S               0
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___S               0

#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG (0x005CF088)
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___S              31
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___S              30
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___S              29
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___S              28
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___S              27
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___S              26
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___S              24
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___S              23
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___S              22
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S              18
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S              17
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___S              16
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___S              15
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___S              14
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S              13
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___S              12
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S              11
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S              10
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___S               8
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___S               7
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___S               6
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___S               5
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S               4
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___S               0

#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL        (0x005CF08C)
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___POR 0x00000002
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___S               2
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___M 0x00000007   
#define   PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___S               0

#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL       (0x005CF090)
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___S              31
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___S               0
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___M 0x800000FF   
#define   PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0  (0x005CF094)
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___S               0
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___S               0

#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1  (0x005CF098)
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___S               0
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___S               0

#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA     (0x005CF09C)
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___S               0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___S               0

#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA     (0x005CF0A0)
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___S               0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___S               0

#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR      (0x005CF0A4)
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___S               0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___S               0

#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS    (0x005CF0A8)
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___S              31
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___S               2
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___S               1
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___S               0
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___M 0x80000007   
#define   PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG (0x005CF400)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___POR 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG (0x005CF404)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___POR 0x000001A0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG (0x005CF408)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___POR 0x000001A0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG (0x005CF40C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___POR 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG (0x005CF410)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___POR 0x00000180
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG (0x005CF414)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___POR 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG (0x005CF418)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___POR 0x000001A0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG (0x005CF41C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___POR 0x00000180
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG (0x005CF420)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___POR 0x000001A0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG (0x005CF424)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___POR 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG (0x005CF428)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___POR 0x00000180
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG (0x005CF42C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___POR 0x000001A0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG (0x005CF430)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___POR 0x00000180
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG (0x005CF434)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___POR 0x00000180
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___S              11
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___S               7
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___S               5
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN   (0x005CF438)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___POR 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS (0x005CF43C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS (0x005CF440)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ   (0x005CF444)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG (0x005CF448)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG (0x005CF44C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG (0x005CF450)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG (0x005CF454)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE (0x005CF458)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___S               1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL  (0x005CF45C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___POR 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG (0x005CF460)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0 (0x005CF464)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___M 0x1F000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1 (0x005CF468)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___M 0x1F000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___S              24
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___S              16
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2 (0x005CF46C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___M 0x1F000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___S              24
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___M 0x001F0000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___S              16
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___S               8
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3 (0x005CF470)
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___S               8
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___M 0x00001F1F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1 (0x005CF800)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___M 0x000000F0   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___S               4

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2 (0x005CF804)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___M 0x000000FC   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___S               2

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3 (0x005CF808)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___M 0x000000FC   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___S               2

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4 (0x005CF80C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5 (0x005CF810)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6 (0x005CF814)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0 (0x005CF818)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1 (0x005CF81C)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___S               0

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2 (0x005CF820)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___M 0x000000F0   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___S               4

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3 (0x005CF824)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___M 0x0000003C   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___S               2

#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4 (0x005CF828)
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB (0x005CFC00)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB__SERIAL_NUM_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB (0x005CFC04)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__JTAG_ID_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__SERIAL_NUM_47_32___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB (0x005CFC08)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__REFCLK_USE_TCXO___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__JTAG_ID_19_16___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB (0x005CFC0C)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB (0x005CFC10)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_08_LDO_SETTLE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_08_LDO_SETTLE___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_12_LDO_DLY___M 0x03800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_12_LDO_DLY___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_17_LDO_DLY___M 0x00700000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_17_LDO_DLY___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VLD___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VALUE___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VSEL___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__SW_CTRL_DLY___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFALDO_DLY___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFALDO_DLY___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S               3
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFA_VSEL___S               2
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD12RFA_VSEL___S               1
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD17RFA_VSEL___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB (0x005CFC14)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_VLD___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_VLD___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_TRIM___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB (0x005CFC18)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__TSENS_DBGBUS_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__TSENS_DBGBUS_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S               1
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_BLOWN_DONE___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB (0x005CFC1C)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__ATPG_JTAG_DISABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__ATPG_JTAG_DISABLE___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB (0x005CFC20)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WSI_WL_OTP_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WSI_WL_OTP_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BTC_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__ANT_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BLE_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_RET_SETTLE_TIME___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_RET_SETTLE_TIME___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_SETTLE_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_SETTLE_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB (0x005CFC24)
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S               2
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MODE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MODE___S               1
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MANU_PGM___S               0
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00 (0x005C0000)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01 (0x005C0004)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02 (0x005C0008)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03 (0x005C000C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04 (0x005C0010)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05 (0x005C0014)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06 (0x005C0018)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07 (0x005C001C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08 (0x005C0020)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09 (0x005C0024)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10 (0x005C0028)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11 (0x005C002C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12 (0x005C0030)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13 (0x005C0034)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14 (0x005C0038)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15 (0x005C003C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16 (0x005C0040)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17 (0x005C0044)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18 (0x005C0048)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19 (0x005C004C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20 (0x005C0050)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21 (0x005C0054)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22 (0x005C0058)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23 (0x005C005C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24 (0x005C0060)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25 (0x005C0064)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26 (0x005C0068)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27 (0x005C006C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28 (0x005C0070)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29 (0x005C0074)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30 (0x005C0078)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31 (0x005C007C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG    (0x005C0080)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___POR 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___POR 0xF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___S               7
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___S               6
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___M 0x000000EF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL     (0x005C0200)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___M 0x0000FFFC
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP (0x005C0204)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3 (0x005C0208)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___M 0x00007777   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2 (0x005C020C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___M 0x00007777   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1 (0x005C0210)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___M 0x00007777   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0 (0x005C0214)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___M 0x00007777   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK (0x005C0218)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___POR 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___POR 0xFFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0     (0x005C021C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___POR 0x00001070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___POR 0x3
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___S               6
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___M 0x0000000E
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___S               1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___M 0x000010FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1     (0x005C0220)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___M 0x0000FFF0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK (0x005C0224)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL (0x005C0228)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK (0x005C022C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE (0x005C0230)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK (0x005C0234)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL (0x005C0238)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK (0x005C023C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE (0x005C0240)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK (0x005C0244)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL (0x005C0248)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK (0x005C024C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE (0x005C0250)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK (0x005C0254)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL (0x005C0258)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK (0x005C025C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE (0x005C0260)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK (0x005C0264)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL (0x005C0268)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK (0x005C026C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE (0x005C0270)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK (0x005C0274)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL (0x005C0278)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___POR 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___POR 0x2
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR (0x005C027C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___M 0x00000077   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST (0x005C0280)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___S              11
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0 (0x005C0284)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1 (0x005C0288)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2 (0x005C028C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3 (0x005C0290)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER (0x005C0294)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER (0x005C0298)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___M 0x000007FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT (0x005C029C)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE (0x005C02A0)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___M 0x0000007F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___M 0x0000007F   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE (0x005C02A4)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___M 0x0000001F
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___M 0x0000001F   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT    (0x005C02A8)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___S               1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK    (0x005C02AC)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL  (0x005C02B0)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE     (0x005C02B4)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___POR 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR (0x005C02B8)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___POR 0x30001000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___POR 0x30001000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___S               0

#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0      (0x005C02BC)
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA         (0x005C5000)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___M  0x000003FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___S                0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL      (0x005C5004)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___M 0x0000001F   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1     (0x005C5008)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___M 0x0002FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2     (0x005C500C)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO      (0x005C5010)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV       (0x005C5014)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT          (0x005C5018)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___S              30
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___S              28
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT___M   0x7FFFFBFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT___S                 0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN       (0x005C501C)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___S              31
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___S              30
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___S              28
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___M 0xFFFFFBFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE   (0x005C5020)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE  (0x005C5024)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE  (0x005C5028)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE  (0x005C502C)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE  (0x005C5030)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE  (0x005C5034)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE  (0x005C5038)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7   (0x005C503C)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6   (0x005C5040)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5   (0x005C5044)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4   (0x005C5048)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3   (0x005C504C)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2   (0x005C5050)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1   (0x005C5054)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0   (0x005C5058)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1 (0x005C505C)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2 (0x005C5060)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1         (0x005C5064)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___S              31
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___S              30
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___M 0x00000600
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___M  0xEFFDFFBD   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___S                0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2         (0x005C5068)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___POR 0x00000355
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___POR 0x00000355
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___S                0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3         (0x005C506C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___POR 0x00000003
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___M  0x01FFFFDF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___S                0

#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START  (0x005C5070)
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD (0x005C5074)
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START  (0x005C5078)
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD (0x005C507C)
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1     (0x005C5080)
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2     (0x005C5084)
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1     (0x005C5088)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2     (0x005C508C)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1       (0x005C5090)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2       (0x005C5094)
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0        (0x005C50A0)
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___POR 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___POR 0xFF
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___M 0x000C0000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___M 0xFF0C000F   
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1        (0x005C50A8)
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___POR 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1     (0x005C50B0)
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___POR 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___M 0x000001F0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2     (0x005C50B4)
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___RWC QCSR_REG_WO    
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1   (0x005C50B8)
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1       (0x005C50BC)
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST     (0x005C50C0)
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___RWC QCSR_REG_WO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT          (0x005C50C4)
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___M   0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___S                 0

#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN       (0x005C50C8)
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK   (0x005C50CC)
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___POR 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK   (0x005C50E0)
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___POR 0x7FFFFBFF
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___S              30
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___S              28
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___S              15
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___S              14
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___S              13
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___S              12
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___S              11
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___M 0x7FFFFBFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_DTIM              (0x005C50EC)
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM___RWC        QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM___POR     0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM___M       0x00000001   
#define   PHYA_IRON2G_RFA_WSI_CXM_DTIM___S                     0

#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE         (0x005C5100)
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___M  0x0000001F   
#define   PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___S                0

#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG    (0x005C5104)
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT           (0x005C5108)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___M    0x00000007   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___S                  0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN        (0x005C510C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___S              31
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___M 0x80000007   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK    (0x005C5110)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___POR 0x00000007
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___M 0x00000007   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL      (0x005C5120)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___M 0x00000007   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL       (0x005C5124)
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___S              10
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___M 0x00000707   
#define   PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE  (0x005C5128)
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE      (0x005C512C)
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___POR 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2   (0x005C5130)
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___POR 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT (0x005C5134)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT (0x005C5138)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT (0x005C513C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT (0x005C5140)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT (0x005C5144)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT (0x005C5148)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT (0x005C514C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT (0x005C5150)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT (0x005C5154)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT (0x005C5158)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT (0x005C515C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT (0x005C5160)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT (0x005C5164)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT (0x005C5168)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT (0x005C516C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT (0x005C5170)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT (0x005C5174)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT (0x005C5178)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT (0x005C517C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT (0x005C5180)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT (0x005C5184)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT (0x005C5188)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT (0x005C518C)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT (0x005C5190)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN   (0x005C5194)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___S              28
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___M 0x3FFF03FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST  (0x005C5198)
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___RWC QCSR_REG_WO    
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___S              29
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___S              28
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___S              27
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___S              26
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___S              25
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___S              24
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___S              23
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___S              22
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___S              21
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___S              20
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___S              19
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___S              18
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___S              17
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___S              16
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___S               9
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___S               8
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___S               7
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___S               6
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___S               5
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___S               4
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___S               3
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___S               2
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___S               1
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___M 0x3FFF03FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___S               0

#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0           (0x005C51F0)
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___M    0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___S                  0

#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1           (0x005C51F4)
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___M    0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___S                  0

#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2           (0x005C51F8)
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___M    0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___S                  0

#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3           (0x005C51FC)
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___POR  0x00000000
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___S               0
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___M    0x000000FF   
#define   PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___S                  0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M (0x005D1000)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___POR 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___POR 0x8
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC (0x005D1004)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___POR 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___POR 0x80
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC (0x005D1008)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___POR 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___POR 0x8
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0 (0x005D100C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1 (0x005D1010)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___POR 0x0000005C
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___POR 0x5C
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2 (0x005D1014)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___POR 0x00000076
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___POR 0x76
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3 (0x005D1018)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___POR 0x0000005C
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___POR 0x5C
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0 (0x005D101C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1 (0x005D1020)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___POR 0x0000003D
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___POR 0x3D
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0 (0x005D1024)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___POR 0x0000009F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___POR 0x9F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1 (0x005D1028)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___POR 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___POR 0x20
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2 (0x005D102C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___POR 0x00000076
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___POR 0x76
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3 (0x005D1030)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___POR 0x00000089
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___POR 0x89
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0 (0x005D1034)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1 (0x005D1038)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___POR 0x0000003D
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___POR 0x3D
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2 (0x005D103C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3 (0x005D1040)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4 (0x005D1044)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___POR 0x000000AF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___POR 0xAF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0 (0x005D1048)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___POR 0x0000009F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___POR 0x9F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1 (0x005D104C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___POR 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___POR 0x20
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0 (0x005D1050)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___POR 0x0000009F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___POR 0x9F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1 (0x005D1054)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___POR 0x0000009F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___POR 0x9F
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0 (0x005D1058)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___POR 0x00000039
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___POR 0x39
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1 (0x005D105C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___POR 0x00000039
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___POR 0x39
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0 (0x005D1060)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___POR 0x000000C6
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___POR 0xC6
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1 (0x005D1064)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___POR 0x000000C6
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___POR 0xC6
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0 (0x005D1068)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___POR 0x00000079
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___POR 0x79
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1 (0x005D106C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___POR 0x00000079
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___POR 0x79
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0 (0x005D1070)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___POR 0x00000086
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___POR 0x86
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1 (0x005D1074)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___POR 0x00000086
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___POR 0x86
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA (0x005D1078)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB (0x005D107C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS (0x005D1080)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS (0x005D1084)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS (0x005D1088)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1 (0x005D108C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS (0x005D1090)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS (0x005D1094)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1 (0x005D1098)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA (0x005D109C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB (0x005D10A0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER  (0x005D10C0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M   (0x005D10C4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC    (0x005D10C8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___M 0x00000030
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___M 0x000000F8   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___S               3

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC    (0x005D10CC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___M 0x00000030
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___M 0x000000F0   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___S               4

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET (0x005D10D0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___M 0x0000003C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___M 0x00000003
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE (0x005D10D4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0 (0x005D10D8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1 (0x005D10DC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2 (0x005D10E0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3 (0x005D10E4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4 (0x005D10E8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST   (0x005D10EC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2 (0x005D10F0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___M 0x00000078
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3 (0x005D10F4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___M 0x00000033   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0 (0x005D10F8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1 (0x005D10FC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2 (0x005D1100)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3 (0x005D1104)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0 (0x005D1108)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1 (0x005D110C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2 (0x005D1110)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3 (0x005D1114)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0 (0x005D1118)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1 (0x005D111C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2 (0x005D1120)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3 (0x005D1124)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2 (0x005D1128)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3 (0x005D112C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0 (0x005D1130)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1 (0x005D1134)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2 (0x005D1138)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3 (0x005D113C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0 (0x005D1140)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1 (0x005D1144)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2 (0x005D1148)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3 (0x005D114C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0 (0x005D1150)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1 (0x005D1154)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2 (0x005D1158)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3 (0x005D115C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2 (0x005D1160)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3 (0x005D1164)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0 (0x005D1168)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1 (0x005D116C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2 (0x005D1170)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3 (0x005D1174)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0 (0x005D1178)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1 (0x005D117C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2 (0x005D1180)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3 (0x005D1184)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0 (0x005D1188)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1 (0x005D118C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2 (0x005D1190)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3 (0x005D1194)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2 (0x005D1198)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3 (0x005D119C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0 (0x005D11A0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1 (0x005D11A4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2 (0x005D11A8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3 (0x005D11AC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0 (0x005D11B0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1 (0x005D11B4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2 (0x005D11B8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3 (0x005D11BC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0 (0x005D11C0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1 (0x005D11C4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2 (0x005D11C8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3 (0x005D11CC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2 (0x005D11D0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3 (0x005D11D4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0 (0x005D11D8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1 (0x005D11DC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2 (0x005D11E0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3 (0x005D11E4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0 (0x005D11E8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1 (0x005D11EC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2 (0x005D11F0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3 (0x005D11F4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0 (0x005D11F8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1 (0x005D11FC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2 (0x005D1200)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3 (0x005D1204)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2 (0x005D1208)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3 (0x005D120C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0 (0x005D1210)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1 (0x005D1214)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2 (0x005D1218)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3 (0x005D121C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0 (0x005D1220)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1 (0x005D1224)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2 (0x005D1228)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3 (0x005D122C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0 (0x005D1230)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1 (0x005D1234)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2 (0x005D1238)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3 (0x005D123C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2 (0x005D1240)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3 (0x005D1244)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0 (0x005D1248)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___POR 0x00000084
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1 (0x005D124C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2 (0x005D1250)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3 (0x005D1254)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0 (0x005D1258)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1 (0x005D125C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2 (0x005D1260)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3 (0x005D1264)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0 (0x005D1268)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1 (0x005D126C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2 (0x005D1270)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3 (0x005D1274)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2 (0x005D1278)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3 (0x005D127C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0 (0x005D1280)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___POR 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1 (0x005D1284)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2 (0x005D1288)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3 (0x005D128C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0 (0x005D1290)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1 (0x005D1294)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2 (0x005D1298)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3 (0x005D129C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0 (0x005D12A0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1 (0x005D12A4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2 (0x005D12A8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3 (0x005D12AC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2 (0x005D12B0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3 (0x005D12B4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0 (0x005D12B8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___POR 0x00000084
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1 (0x005D12BC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2 (0x005D12C0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3 (0x005D12C4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0 (0x005D12C8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1 (0x005D12CC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2 (0x005D12D0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3 (0x005D12D4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0 (0x005D12D8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1 (0x005D12DC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2 (0x005D12E0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3 (0x005D12E4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2 (0x005D12E8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___POR 0x00000065
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___POR 0x5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3 (0x005D12EC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___M 0x000000E0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___M 0x00000018
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0 (0x005D12F0)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___POR 0x00000084
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___POR 0x2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___S               7
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___M 0x00000040
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___M 0x00000038
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___M 0x00000006
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1 (0x005D12F4)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___M 0x00000007
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2 (0x005D12F8)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___POR 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___M 0x00000010
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3 (0x005D12FC)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___S               3
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___M 0x00000004
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___S               1
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___M 0x00000001
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0 (0x005D1300)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1 (0x005D1304)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2 (0x005D1308)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3 (0x005D130C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0 (0x005D1310)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1 (0x005D1314)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2 (0x005D1318)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3 (0x005D131C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1   (0x005D1320)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___M 0x00000030
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___M 0x00000003
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2   (0x005D1324)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___POR 0x0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___S               6
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___M 0x00000030
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___S               4
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___S               2
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___M 0x00000003
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___S               0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1          (0x005D1328)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___POR 0x00000005
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___POR 0x05
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___M 0x0000003F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___M   0x0000003F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___S                 0

#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2          (0x005D132C)
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___POR 0x0000002C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___POR 0x2C
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___M 0x0000003F
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___M   0x0000003F   
#define   PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___S                 0

#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE            (0x005D1334)
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE___POR   0x00000000
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___S               0
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE___M     0x000000FF   
#define   PHYA_IRON2G_RFA_WSIM_PMU_SPARE___S                   0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0 (0x005C9B04)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0 (0x005C9B28)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1 (0x005C9B2C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2 (0x005C9B30)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3 (0x005C9B34)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4 (0x005C9B38)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5 (0x005C9B3C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6 (0x005C9B40)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7 (0x005C9B44)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT (0x005C9B48)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS (0x005C9B4C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0 (0x005C9B50)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___M 0x000000E9   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1 (0x005C9B54)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG (0x005C9B58)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES (0x005C9B5C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL (0x005C9B6C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL (0x005C9B70)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT (0x005C9B74)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER (0x005C9D00)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___POR 0x000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL (0x005C9D04)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL (0x005C9D08)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___POR 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___POR 0x1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS (0x005C9D0C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL (0x005C9D10)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR (0x005C9D14)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___POR 0x00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___M 0x0001FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS (0x005C9D18)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___M 0x00000003   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR (0x005C9D1C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ (0x005C9D20)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___M 0x00000001   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR     (0x005C9D24)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___M 0x00003E00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___M 0x0000007C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR     (0x005C9D28)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR (0x005C9D2C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___POR 0x00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___POR 0x0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___M 0x003E0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG (0x005C9D30)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG (0x005C9D34)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG (0x005C9D38)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG (0x005C9D3C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___POR 0x00000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB (0x005C7000)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB (0x005C7004)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB (0x005C7008)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB (0x005C700C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB (0x005C7010)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB (0x005C7014)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB (0x005C7018)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB (0x005C701C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__MODEL_ID___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__MODEL_ID___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__OEM_ID___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__OEM_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB (0x005C7020)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB (0x005C7024)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB (0x005C7028)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB__SERIAL_NUM_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB (0x005C702C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__JTAG_ID_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__SERIAL_NUM_47_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB (0x005C7030)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__SPARE_R6_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__SPARE_R6_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__REFCLK_USE_TCXO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__JTAG_ID_19_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB (0x005C7034)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB (0x005C7038)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___M 0x03800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___M 0x00700000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VLD___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VALUE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VSEL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__SW_CTRL_DLY___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFA_VSEL___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD12RFA_VSEL___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD17RFA_VSEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB (0x005C703C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB (0x005C7040)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_BLOWN_DONE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB (0x005C7044)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__APB2JTAG_DISABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__APB2JTAG_DISABLE___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB (0x005C7048)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BTC_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__ANT_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BLE_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB (0x005C704C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MODE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MODE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MANU_PGM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB (0x005C7050)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__LOT_ID_LOW_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__LOT_ID_LOW_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_Y___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_Y___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_X___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_X___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__WAFERID___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__WAFERID___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB (0x005C7054)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_LOW_31_8___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_LOW_31_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB (0x005C7058)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__TEST_INSERTION_MASK___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__TEST_INSERTION_MASK___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB (0x005C705C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB (0x005C7060)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB (0x005C7064)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB (0x005C7068)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__CMOS_EG_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__CMOS_EG_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__NMOS_EG_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__NMOS_EG_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB (0x005C706C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB (0x005C7070)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB (0x005C7074)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB (0x005C7078)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB (0x005C707C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RERR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RERR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB (0x005C7080)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB (0x005C7084)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB (0x005C7088)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__ATE_DVS_FLAG___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__ATE_DVS_FLAG___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__FOUNDRY_ID___M 0x003C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__FOUNDRY_ID___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__HW_BOARD_ID___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__HW_BOARD_ID___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__OTP_REVISION___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__OTP_REVISION___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB (0x005C708C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB (0x005C7090)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__CONST_PWD_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__CONST_PWD_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__UNIQUE_QA_PWD___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__UNIQUE_QA_PWD___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_RTL_KEY_VERSION___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_RTL_KEY_VERSION___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB (0x005C7094)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__PKG_ID___M 0xFE000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__PKG_ID___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB (0x005C7098)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB (0x005C709C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB (0x005C70A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB (0x005C70A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB (0x005C70A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB (0x005C70AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB (0x005C70B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB (0x005C70B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB (0x005C70B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB (0x005C70BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB (0x005C70C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB (0x005C70C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB (0x005C70C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB (0x005C70CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB (0x005C70D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB (0x005C70D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB (0x005C70D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB (0x005C70DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB (0x005C70E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB (0x005C70E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB (0x005C70E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___M 0x00003000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__WIP_FEC_ENABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__WIP_FEC_ENABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__BT_FEC_ENABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__BT_FEC_ENABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB (0x005C70EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB (0x005C70F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB (0x005C70F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB (0x005C70F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB (0x005C70FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB (0x005C7100)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB (0x005C7104)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB (0x005C7108)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB (0x005C710C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB (0x005C7110)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB (0x005C7114)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB (0x005C7118)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB (0x005C711C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB (0x005C7120)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB (0x005C7124)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB (0x005C7128)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB (0x005C712C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB (0x005C7130)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB (0x005C7134)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB (0x005C7138)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB (0x005C713C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB (0x005C7140)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB (0x005C7144)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB (0x005C7148)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB (0x005C714C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB (0x005C7150)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___M 0x003F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___M 0x00003F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB (0x005C7154)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___M 0x00003F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB (0x005C7158)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___M 0x07FC0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB (0x005C715C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___M 0x00E00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB (0x005C7160)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___M 0x07000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___M 0x00380000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___M 0x00070000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___M 0x0000001C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB (0x005C7164)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB (0x005C7168)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB (0x005C716C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB (0x005C7170)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___M 0x38000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___M 0x07000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___M 0x00380000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___M 0x00070000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___M 0x00003800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB (0x005C7174)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___M 0x001C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___M 0x00003000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___M 0x00000300
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___M 0x00000038
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB (0x005C7178)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___M 0x0F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___M 0x00007F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB (0x005C717C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB (0x005C7180)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB (0x005C7184)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB (0x005C7188)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB__OTP_MAGIC_NUMBER___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB__OTP_MAGIC_NUMBER___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB (0x005C718C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__BTUARTBAUD___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__BTUARTBAUD___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_39_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_39_47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RADIO_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RADIO_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__LC_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__LC_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__COEX_MCI_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__COEX_MCI_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_VSC___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_VSC___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_SSR___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_SSR___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_NVM___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_NVM___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_DSET___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_DSET___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HID_OFFLOAD___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HID_OFFLOAD___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HOGP_OFFLOAD___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HOGP_OFFLOAD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__F64M___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__F64M___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EDL_OVR_DBGUART___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EDL_OVR_DBGUART___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__AUTOBAUD___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__AUTOBAUD___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__PHY_MODE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__PHY_MODE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EMULATION_MODE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EMULATION_MODE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_R49_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_R49_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB (0x005C7190)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB (0x005C7194)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RFKILL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RFKILL___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB (0x005C7198)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB (0x005C719C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_LEN___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_LEN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB (0x005C71A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RBIAS_ICON_CODE___M 0x000000FC
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RBIAS_ICON_CODE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__SHA256_HW_SW___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__SHA256_HW_SW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB (0x005C71A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB (0x005C71A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB (0x005C71AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB (0x005C71B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB (0x005C71B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB (0x005C71B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_ENABLE_FLAG___M 0x000FFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_ENABLE_FLAG___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB (0x005C71BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB (0x005C71C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB (0x005C71C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB (0x005C71C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK5___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK5___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB (0x005C71CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB (0x005C71D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB (0x005C71D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB (0x005C71D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB (0x005C71DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB (0x005C71E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB (0x005C71E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB (0x005C71E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL2___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL2___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB (0x005C71EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL0___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB (0x005C71F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___M 0x30000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___M 0x0C000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_96M___M 0x03C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_96M___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_96M___M 0x00300000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_96M___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___M 0x000C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_48M___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_48M___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_48M___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_48M___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___M 0x00000300
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_38M___M 0x0000003C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_38M___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_38M___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_38M___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB (0x005C71F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__BT_FEATURE_CONTROL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__BT_FEATURE_CONTROL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB (0x005C71F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB (0x005C71FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB (0x005C7200)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB (0x005C7204)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB (0x005C7208)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB (0x005C720C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB (0x005C7210)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB (0x005C7214)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB (0x005C7218)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB (0x005C721C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB (0x005C7220)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB (0x005C7224)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB (0x005C7228)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB (0x005C722C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB (0x005C7230)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB (0x005C7234)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB (0x005C7238)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB (0x005C723C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB (0x005C7240)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB (0x005C7244)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB (0x005C7248)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB (0x005C724C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB (0x005C7250)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB (0x005C7254)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB (0x005C7258)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB (0x005C725C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB (0x005C7260)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB (0x005C7264)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB (0x005C7268)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB (0x005C726C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB (0x005C7270)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB (0x005C7274)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB (0x005C7278)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB (0x005C727C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB (0x005C7280)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB (0x005C7284)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB (0x005C7288)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB (0x005C728C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB (0x005C7290)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB (0x005C7294)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB (0x005C7298)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB (0x005C729C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB (0x005C72A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB (0x005C72A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB (0x005C72A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB (0x005C72AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB (0x005C72B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB (0x005C72B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB (0x005C72B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB (0x005C72BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB (0x005C72C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB (0x005C72C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB (0x005C72C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB (0x005C72CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB (0x005C72D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB (0x005C72D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB (0x005C72D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB (0x005C72DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB (0x005C72E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB (0x005C72E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB (0x005C72E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB (0x005C72EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB (0x005C72F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB (0x005C72F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB (0x005C72F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB (0x005C72FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB (0x005C7300)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB (0x005C7304)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB (0x005C7308)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB (0x005C730C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB (0x005C7310)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB (0x005C7314)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB (0x005C7318)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB (0x005C731C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB (0x005C7320)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB (0x005C7324)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB (0x005C7328)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB (0x005C732C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB (0x005C7330)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB (0x005C7334)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB (0x005C7338)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB (0x005C733C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB (0x005C7340)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB (0x005C7344)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB (0x005C7348)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB (0x005C734C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB (0x005C7350)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB (0x005C7354)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB (0x005C7358)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB (0x005C735C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB (0x005C7360)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB (0x005C7364)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB (0x005C7368)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB (0x005C736C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB (0x005C7370)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB (0x005C7374)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB (0x005C7378)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB (0x005C737C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB (0x005C7380)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB (0x005C7384)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB (0x005C7388)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB (0x005C738C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB (0x005C7390)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB (0x005C7394)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB (0x005C7398)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB (0x005C739C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB (0x005C73A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB (0x005C73A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB (0x005C73A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB (0x005C73AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB (0x005C73B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB (0x005C73B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB (0x005C73B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB (0x005C73BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB (0x005C73C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB (0x005C73C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB (0x005C73C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB (0x005C73CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB (0x005C73D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB (0x005C73D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB (0x005C73D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB__BTCUSMAGIC___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB__BTCUSMAGIC___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB (0x005C73DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB (0x005C73E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB (0x005C73E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB (0x005C73E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB (0x005C73EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB (0x005C73F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB (0x005C73F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY6___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY6___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB (0x005C73F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY10___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY10___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY9___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY9___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY8___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB (0x005C73FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY13___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY13___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY12___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY12___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY11___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB (0x005C7400)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY17___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY17___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY16___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY15___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY15___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY14___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB (0x005C7404)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY20___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY20___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY19___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY19___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY18___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB (0x005C7408)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY24___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY23___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY23___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY22___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY22___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY21___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB (0x005C740C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY27___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY27___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY26___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY26___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY25___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB (0x005C7410)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY31___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY31___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY30___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY30___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY29___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY29___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY28___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB (0x005C7414)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB (0x005C7418)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB (0x005C741C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB (0x005C7420)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB (0x005C7424)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB (0x005C7428)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB (0x005C742C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB (0x005C7430)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB (0x005C7434)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB (0x005C7438)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG2___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG2___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG1___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG1___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB (0x005C743C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG4___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG4___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB (0x005C7440)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG9___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG9___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG8___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG8___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG7___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG7___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG6___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG6___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB (0x005C7444)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG12___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG12___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG11___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG11___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG10___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB (0x005C7448)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG15___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG15___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG14___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG14___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG13___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB (0x005C744C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB (0x005C7450)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__RSVD_R138_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__RSVD_R138_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB (0x005C7454)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___M 0x003F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___M 0x0000FE00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB (0x005C7458)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___M 0x7E000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___M 0x01FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___M 0x0000007F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB (0x005C745C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB (0x005C7460)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB (0x005C7464)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD0___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD0___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__FEC_VALUE___M 0x7F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__FEC_VALUE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB (0x005CB000)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB (0x005CB004)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB (0x005CB008)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB (0x005CB00C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB (0x005CB010)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___M 0x0000000C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB (0x005CB014)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB (0x005CB018)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB (0x005CB01C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__MODEL_ID___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__MODEL_ID___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__OEM_ID___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__OEM_ID___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB (0x005CB020)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB (0x005CB024)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB (0x005CB028)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB__SERIAL_NUM_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB (0x005CB02C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__JTAG_ID_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__SERIAL_NUM_47_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB (0x005CB030)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__SPARE_R6_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__SPARE_R6_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__REFCLK_USE_TCXO___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__JTAG_ID_19_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB (0x005CB034)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB (0x005CB038)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___M 0x03800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___M 0x00700000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VLD___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VALUE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VSEL___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__SW_CTRL_DLY___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFA_VSEL___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD12RFA_VSEL___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD17RFA_VSEL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB (0x005CB03C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB (0x005CB040)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_BLOWN_DONE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB (0x005CB044)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__APB2JTAG_DISABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__APB2JTAG_DISABLE___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB (0x005CB048)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BTC_DISABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__ANT_DISABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BLE_DISABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB (0x005CB04C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MODE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MODE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MANU_PGM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB (0x005CB050)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__LOT_ID_LOW_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__LOT_ID_LOW_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_Y___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_Y___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_X___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_X___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__WAFERID___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__WAFERID___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB (0x005CB054)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_LOW_31_8___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_LOW_31_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB (0x005CB058)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__TEST_INSERTION_MASK___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__TEST_INSERTION_MASK___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB (0x005CB05C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB (0x005CB060)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB (0x005CB064)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB (0x005CB068)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__CMOS_EG_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__CMOS_EG_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__NMOS_EG_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__NMOS_EG_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB (0x005CB06C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB (0x005CB070)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB (0x005CB074)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB (0x005CB078)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB (0x005CB07C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RERR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RERR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB (0x005CB080)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB (0x005CB084)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB (0x005CB088)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__ATE_DVS_FLAG___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__ATE_DVS_FLAG___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__FOUNDRY_ID___M 0x003C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__FOUNDRY_ID___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__HW_BOARD_ID___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__HW_BOARD_ID___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__OTP_REVISION___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__OTP_REVISION___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB (0x005CB08C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB (0x005CB090)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__CONST_PWD_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__CONST_PWD_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__UNIQUE_QA_PWD___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__UNIQUE_QA_PWD___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_RTL_KEY_VERSION___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_RTL_KEY_VERSION___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB (0x005CB094)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__PKG_ID___M 0xFE000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__PKG_ID___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB (0x005CB098)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB (0x005CB09C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB (0x005CB0A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB (0x005CB0A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB (0x005CB0A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB (0x005CB0AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB (0x005CB0B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB (0x005CB0B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB (0x005CB0B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB (0x005CB0BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB (0x005CB0C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB (0x005CB0C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1_23_0___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1_23_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB (0x005CB0C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1_31_24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1_31_24___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB (0x005CB0CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3_15_0___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3_15_0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB (0x005CB0D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3_31_16___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3_31_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB (0x005CB0D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5_7_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5_7_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB (0x005CB0D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5_31_8___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5_31_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB (0x005CB0DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB (0x005CB0E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB (0x005CB0E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB (0x005CB0E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___M 0x00003000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__WIP_FEC_ENABLE___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__WIP_FEC_ENABLE___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__BT_FEC_ENABLE___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__BT_FEC_ENABLE___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB (0x005CB0EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B63___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B63___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B62___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B62___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B61___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B61___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B60___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B60___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B59___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B59___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B58___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B58___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B57___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B57___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B56___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B56___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB (0x005CB0F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB (0x005CB0F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB (0x005CB0F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD_57_56___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD_57_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB (0x005CB0FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB (0x005CB100)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB (0x005CB104)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB (0x005CB108)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_63_56___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_63_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB (0x005CB10C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB (0x005CB110)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB (0x005CB114)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB (0x005CB118)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB (0x005CB11C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB (0x005CB120)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB (0x005CB124)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB (0x005CB128)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB (0x005CB12C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB (0x005CB130)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB (0x005CB134)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB (0x005CB138)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB (0x005CB13C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB (0x005CB140)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB (0x005CB144)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB (0x005CB148)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___M 0x0FFFC000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB (0x005CB14C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___M 0x00FFFC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB (0x005CB150)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___M 0x003F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___M 0x00003F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___M 0x00000030
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB (0x005CB154)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___M 0x00003F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB (0x005CB158)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___M 0x07FC0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB (0x005CB15C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___M 0x00E00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___M 0x00007000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB (0x005CB160)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___M 0x07000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___M 0x00380000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___M 0x00070000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___M 0x0000001C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB (0x005CB164)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB (0x005CB168)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB (0x005CB16C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB (0x005CB170)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___M 0x38000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___M 0x07000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___M 0x00380000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___M 0x00070000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___M 0x00003800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___M 0x00000700
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___M 0x00000070
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB (0x005CB174)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___M 0x001C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___M 0x0000C000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___M 0x00003000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___M 0x00000300
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___M 0x00000038
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB (0x005CB178)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___M 0xF0000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___M 0x0F000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___M 0x00007F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB (0x005CB17C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___M 0x000F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___M 0x00000F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___M 0x000000F0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___M 0x0000000F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB (0x005CB180)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___M 0x00F00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___M 0x000003FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB (0x005CB184)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB (0x005CB188)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB__OTP_MAGIC_NUMBER___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB__OTP_MAGIC_NUMBER___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB (0x005CB18C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__BTUARTBAUD___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__BTUARTBAUD___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_39_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_39_47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RADIO_DISABLE___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RADIO_DISABLE___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__LC_DISABLE___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__LC_DISABLE___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__COEX_MCI_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__COEX_MCI_EN___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_VSC___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_VSC___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_SSR___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_SSR___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_NVM___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_NVM___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_DSET___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_DSET___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HID_OFFLOAD___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HID_OFFLOAD___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HOGP_OFFLOAD___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HOGP_OFFLOAD___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__F64M___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__F64M___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EDL_OVR_DBGUART___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EDL_OVR_DBGUART___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__AUTOBAUD___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__AUTOBAUD___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__PHY_MODE___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__PHY_MODE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EMULATION_MODE___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EMULATION_MODE___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_R49_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_R49_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB (0x005CB190)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB (0x005CB194)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__RFKILL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__RFKILL___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB (0x005CB198)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB (0x005CB19C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_LEN___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_LEN___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB (0x005CB1A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RBIAS_ICON_CODE___M 0x000000FC
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RBIAS_ICON_CODE___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__SHA256_HW_SW___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__SHA256_HW_SW___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB (0x005CB1A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB (0x005CB1A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB (0x005CB1AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB (0x005CB1B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB (0x005CB1B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB (0x005CB1B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_ENABLE_FLAG___M 0x000FFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_ENABLE_FLAG___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB (0x005CB1BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB (0x005CB1C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB (0x005CB1C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK5_7_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK5_7_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB (0x005CB1C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK5_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK5_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB (0x005CB1CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB (0x005CB1D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB (0x005CB1D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_7_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_7_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB (0x005CB1D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB (0x005CB1DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB (0x005CB1E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB (0x005CB1E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_7_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_7_0___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB (0x005CB1E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL2___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL2___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB (0x005CB1EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL0___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB (0x005CB1F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___M 0x30000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___M 0x0C000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_96M___M 0x03C00000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_96M___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_96M___M 0x00300000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_96M___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___M 0x000C0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___M 0x00030000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_48M___M 0x0000F000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_48M___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_48M___M 0x00000C00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_48M___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___M 0x00000300
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___M 0x000000C0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_38M___M 0x0000003C
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_38M___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_38M___M 0x00000003
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_38M___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB (0x005CB1F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__BT_FEATURE_CONTROL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__BT_FEATURE_CONTROL___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB (0x005CB1F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB (0x005CB1FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB (0x005CB200)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB (0x005CB204)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB (0x005CB208)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB (0x005CB20C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB (0x005CB210)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB (0x005CB214)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB (0x005CB218)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB (0x005CB21C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB (0x005CB220)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB (0x005CB224)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB (0x005CB228)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB (0x005CB22C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB (0x005CB230)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB (0x005CB234)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB (0x005CB238)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB (0x005CB23C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB (0x005CB240)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB (0x005CB244)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB (0x005CB248)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB (0x005CB24C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB (0x005CB250)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB (0x005CB254)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB (0x005CB258)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB (0x005CB25C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB (0x005CB260)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB (0x005CB264)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB (0x005CB268)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB (0x005CB26C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB (0x005CB270)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB (0x005CB274)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB (0x005CB278)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB (0x005CB27C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB (0x005CB280)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB (0x005CB284)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB (0x005CB288)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB (0x005CB28C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB (0x005CB290)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB (0x005CB294)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB (0x005CB298)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB (0x005CB29C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB (0x005CB2A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB (0x005CB2A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB (0x005CB2A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB (0x005CB2AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB (0x005CB2B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB (0x005CB2B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB (0x005CB2B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB (0x005CB2BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB (0x005CB2C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB (0x005CB2C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB (0x005CB2C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB (0x005CB2CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB (0x005CB2D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB (0x005CB2D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB (0x005CB2D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB (0x005CB2DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB (0x005CB2E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB (0x005CB2E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB (0x005CB2E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB (0x005CB2EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB (0x005CB2F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB (0x005CB2F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB (0x005CB2F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB (0x005CB2FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB (0x005CB300)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB (0x005CB304)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB (0x005CB308)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB (0x005CB30C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB (0x005CB310)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB (0x005CB314)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB (0x005CB318)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB (0x005CB31C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB (0x005CB320)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB (0x005CB324)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB (0x005CB328)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB (0x005CB32C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB (0x005CB330)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB (0x005CB334)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB (0x005CB338)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB (0x005CB33C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB (0x005CB340)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB (0x005CB344)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB (0x005CB348)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB (0x005CB34C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB (0x005CB350)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB (0x005CB354)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB (0x005CB358)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB (0x005CB35C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB (0x005CB360)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB (0x005CB364)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB (0x005CB368)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB (0x005CB36C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB (0x005CB370)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB (0x005CB374)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB (0x005CB378)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB (0x005CB37C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB (0x005CB380)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB (0x005CB384)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB (0x005CB388)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB (0x005CB38C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB (0x005CB390)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB (0x005CB394)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB (0x005CB398)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB (0x005CB39C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB (0x005CB3A0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB (0x005CB3A4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB (0x005CB3A8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB (0x005CB3AC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB (0x005CB3B0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB (0x005CB3B4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB (0x005CB3B8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB (0x005CB3BC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB (0x005CB3C0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB (0x005CB3C4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB (0x005CB3C8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB (0x005CB3CC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB (0x005CB3D0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB (0x005CB3D4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB (0x005CB3D8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB__BTCUSMAGIC___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB__BTCUSMAGIC___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB (0x005CB3DC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB (0x005CB3E0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB (0x005CB3E4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB (0x005CB3E8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB (0x005CB3EC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB (0x005CB3F0)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY3___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB (0x005CB3F4)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY6___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY6___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY5___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY5___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY4___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB (0x005CB3F8)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY10___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY10___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY9___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY9___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY8___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB (0x005CB3FC)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY13___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY13___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY12___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY12___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY11___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB (0x005CB400)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY17___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY17___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY16___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY15___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY15___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY14___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB (0x005CB404)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY20___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY20___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY19___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY19___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY18___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB (0x005CB408)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY24___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY23___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY23___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY22___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY22___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY21___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB (0x005CB40C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY27___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY27___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY26___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY26___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY25___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB (0x005CB410)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY31___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY31___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY30___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY30___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY29___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY29___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY28___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB (0x005CB414)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB (0x005CB418)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB (0x005CB41C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB (0x005CB420)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB (0x005CB424)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB (0x005CB428)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB (0x005CB42C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB (0x005CB430)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB (0x005CB434)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB (0x005CB438)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG2___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG2___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG1___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG1___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG0___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB (0x005CB43C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG5___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG5___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG4___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG4___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG3___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB (0x005CB440)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG9___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG9___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG8___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG8___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG7___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG7___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG6___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG6___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB (0x005CB444)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG12___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG12___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG11___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG11___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG10___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB (0x005CB448)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG15___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG15___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG14___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG14___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG13___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB (0x005CB44C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB (0x005CB450)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___M 0xFF000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__RSVD_R138_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__RSVD_R138_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB (0x005CB454)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___M 0x003F0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___M 0x0000FE00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___M 0x000001FF
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB (0x005CB458)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___M 0x7E000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___M 0x01FF0000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___M 0x00001F00
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___M 0x0000007F
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB (0x005CB45C)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB (0x005CB460)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B31___M 0x80000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B31___S              31
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B30___M 0x40000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B30___S              30
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B29___M 0x20000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B29___S              29
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B28___M 0x10000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B28___S              28
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B27___M 0x08000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B27___S              27
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B26___M 0x04000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B26___S              26
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B25___M 0x02000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B25___S              25
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B24___M 0x01000000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B24___S              24
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B23___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B23___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B22___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B22___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B21___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B21___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B20___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B20___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B19___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B19___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B18___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B18___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B17___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B17___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B16___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B16___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B15___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B15___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B14___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B14___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B13___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B13___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B12___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B12___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B11___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B11___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B10___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B10___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B9___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B9___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B8___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B8___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B7___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B7___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B6___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B6___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B5___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B5___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B4___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B4___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B3___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B3___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B2___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B2___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B1___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B1___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B0___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B0___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___S               0

#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB (0x005CB464)
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B55___M 0x00800000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B55___S              23
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B54___M 0x00400000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B54___S              22
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B53___M 0x00200000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B53___S              21
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B52___M 0x00100000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B52___S              20
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B51___M 0x00080000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B51___S              19
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B50___M 0x00040000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B50___S              18
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B49___M 0x00020000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B49___S              17
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B48___M 0x00010000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B48___S              16
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B47___M 0x00008000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B47___S              15
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B46___M 0x00004000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B46___S              14
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B45___M 0x00002000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B45___S              13
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B44___M 0x00001000
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B44___S              12
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B43___M 0x00000800
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B43___S              11
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B42___M 0x00000400
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B42___S              10
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B41___M 0x00000200
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B41___S               9
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B40___M 0x00000100
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B40___S               8
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B39___M 0x00000080
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B39___S               7
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B38___M 0x00000040
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B38___S               6
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B37___M 0x00000020
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B37___S               5
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B36___M 0x00000010
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B36___S               4
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B35___M 0x00000008
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B35___S               3
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B34___M 0x00000004
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B34___S               2
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B33___M 0x00000002
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B33___S               1
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B32___M 0x00000001
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B32___S               0
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___S               0

#define PHYA_IRON2G_RFA_AON_TESTREG               (0x005D4000)
#define   PHYA_IRON2G_RFA_AON_TESTREG___RWC         QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TESTREG___POR      0x1234ABCD
#define   PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_AON_TESTREG___M        0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_TESTREG___S                      0

#define PHYA_IRON2G_RFA_AON_RO_TESTREG            (0x005D4004)
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG___RWC      QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG___POR   0x8FAD7E57
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___POR 0x8FAD7E57
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___S               0
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG___M     0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_TESTREG___S                   0

#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG           (0x005D4008)
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___S              12
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___S               8
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___S               4
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___S               0
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG___M    0x0000FFFF   
#define   PHYA_IRON2G_RFA_AON_CHIP_CONFIG___S                  0

#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT          (0x005D400C)
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___S                 0

#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE           (0x005D4010)
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___S                  0

#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN        (0x005D4014)
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___S               0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___S               0

#define PHYA_IRON2G_RFA_AON_BAND_CH0              (0x005D4018)
#define   PHYA_IRON2G_RFA_AON_BAND_CH0___RWC        QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_BAND_CH0___POR     0x00000000
#define   PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_BAND_CH0___M       0x00000001   
#define   PHYA_IRON2G_RFA_AON_BAND_CH0___S                     0

#define PHYA_IRON2G_RFA_AON_BAND_CH1              (0x005D401C)
#define   PHYA_IRON2G_RFA_AON_BAND_CH1___RWC        QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_BAND_CH1___POR     0x00000000
#define   PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___S               0
#define   PHYA_IRON2G_RFA_AON_BAND_CH1___M       0x00000001   
#define   PHYA_IRON2G_RFA_AON_BAND_CH1___S                     0

#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL       (0x005D4020)
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___S               0
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___S               0

#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0     (0x005D4024)
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___S              18
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___S              16
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___S              10
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___S               8
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___S               4
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___S               2
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___S               0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___S               0

#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1     (0x005D4028)
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___S               0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___M 0x00000001   
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___S               0

#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2     (0x005D402C)
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___POR 0x00000006
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___POR 0x1
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___S               3
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___S               2
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___S               1
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___S               0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___S               0

#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3     (0x005D4030)
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___S              18
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___S               0

#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4     (0x005D4034)
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___S               6
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___S               5
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___S               4
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___S               3
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___S               2
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___S               1
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___S               0
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___M 0x0000007F   
#define   PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___S               0

#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG         (0x005D4040)
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___POR 0x00000001
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___S              15
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___S              14
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___S               0
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___M  0x0000C001   
#define   PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___S                0

#define PHYA_IRON2G_RFA_AON_AOA                   (0x005D4044)
#define   PHYA_IRON2G_RFA_AON_AOA___RWC             QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AOA___POR          0x0000007F
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___POR 0x7F
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___M 0x0000007F
#define   PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___S               0
#define   PHYA_IRON2G_RFA_AON_AOA___M            0xC000007F   
#define   PHYA_IRON2G_RFA_AON_AOA___S                          0

#define PHYA_IRON2G_RFA_AON_PM_0                  (0x005D4048)
#define   PHYA_IRON2G_RFA_AON_PM_0___RWC            QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_PM_0___POR         0x00418000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___POR 0x4
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___POR 0x1
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___M  0x80000000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___S               31
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___M 0x70000000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___S              28
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___M  0x08000000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___S               27
#define   PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___S              26
#define   PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___S              24
#define   PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___M 0x00700000
#define   PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___S              20
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___S              16
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___S              15
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___M 0x00007000
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___S              12
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___S              10
#define   PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___S               2
#define   PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___S               0
#define   PHYA_IRON2G_RFA_AON_PM_0___M           0xFF7FFC0F   
#define   PHYA_IRON2G_RFA_AON_PM_0___S                         0

#define PHYA_IRON2G_RFA_AON_RO_PM                 (0x005D404C)
#define   PHYA_IRON2G_RFA_AON_RO_PM___RWC           QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_PM___POR        0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___POR 0x0000
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___S              16
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_PM___M          0x0001FFFF   
#define   PHYA_IRON2G_RFA_AON_RO_PM___S                        0

#define PHYA_IRON2G_RFA_AON_WL_BT_CONC            (0x005D4050)
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC___POR   0x00000000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___POR 0x00
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___S              31
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___S              30
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___S              29
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___M 0x1FC00000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___S              22
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___S              15
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___S              14
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___S              13
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___S               3
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___S               0
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC___M     0xFFC0E019   
#define   PHYA_IRON2G_RFA_AON_WL_BT_CONC___S                   0

#define PHYA_IRON2G_RFA_AON_ATB                   (0x005D4054)
#define   PHYA_IRON2G_RFA_AON_ATB___RWC             QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_ATB___POR          0x00000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___S              31
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___S              30
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___S              29
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___S              28
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___S              27
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___S              26
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___S              25
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___S              24
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___S              23
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___S              22
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___S              21
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___S              20
#define   PHYA_IRON2G_RFA_AON_ATB___M            0xFFF00000   
#define   PHYA_IRON2G_RFA_AON_ATB___S                         20

#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL          (0x005D4058)
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___S              31
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___S              30
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___S              29
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___S              28
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___S              27
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___S              26
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___S              25
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___M   0xFE000000   
#define   PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___S                25

#define PHYA_IRON2G_RFA_AON_RO_DBG_0              (0x005D405C)
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0___RWC        QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0___POR     0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___S              31
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___S              30
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___S              29
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___S              28
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___S              27
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___S              26
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___S              25
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___S              24
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___S              23
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___S              22
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___S              21
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___S              20
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___S              19
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___S              18
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___S              17
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___S              16
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___S              15
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___S              14
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___S              13
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___S              12
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___S              11
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___S              10
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___S               9
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___S               8
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___S               7
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___S               6
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___S               5
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___S               4
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___S               3
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___S               2
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___S               1
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0___M       0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_AON_RO_DBG_0___S                     1

#define PHYA_IRON2G_RFA_AON_RO_DBG_1              (0x005D4060)
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1___RWC        QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1___POR     0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___S              31
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___S              30
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1___M       0xC0000000   
#define   PHYA_IRON2G_RFA_AON_RO_DBG_1___S                    30

#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0        (0x005D4064)
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___S              31
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___S              30
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___S              29
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___S              28
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___S              27
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___S              26
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___S              25
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___S              24
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___S              16
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___S              15
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___S              14
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___S              13
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___S              12
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___S              11
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___S              10
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___S               9
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___M 0xFF01FE00   
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___S               9

#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1        (0x005D4068)
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___S              28
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___S              24
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___S              20
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___S              16
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___S              12
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___S               8
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___S               8

#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0         (0x005D4080)
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___M 0x0FE00000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___S              21
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___S              20
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___S              19
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___M 0x00078000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___S              15
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___M 0x00007E00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___S               9
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___S               7
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___S               6
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___M 0x00000038
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___S               3
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___S                0

#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1         (0x005D4084)
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___M  0xE0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___S               29

#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL        (0x005D4088)
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___POR 0x80000000
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___POR 0x1
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___S              31
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___S               5
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___S               4
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___S               3
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___S               2
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___S               1
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___S               0
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___M 0x8000003F   
#define   PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0        (0x005D408C)
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___M 0xF000FFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1        (0x005D4090)
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___M 0xFF000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___S              24
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___S              16
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0         (0x005D4094)
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___M 0x0FE00000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___S              21
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___S              20
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___S              19
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___M 0x00078000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___S              15
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___M 0x00007E00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___S               9
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___S               7
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___S               6
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___M 0x00000038
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___S               3
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___S                0

#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1         (0x005D4098)
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___M  0xE0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___S               29

#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL        (0x005D409C)
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___POR 0x80000000
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___POR 0x1
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___S              31
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___S               5
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___S               4
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___S               3
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___S               2
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___S               1
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___S               0
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___M 0x8000003F   
#define   PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0        (0x005D40A0)
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___M 0xF000FFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1        (0x005D40A4)
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___M 0xFF000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___S              24
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___S              16
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___S               0

#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG           (0x005D40A8)
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___RWC     QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___M 0x0FE00000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___S              21
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___S              20
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___S              19
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___M 0x00078000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___S              15
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___M 0x00007E00
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___S               9
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___S               7
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___S               6
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___M 0x00000038
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___S               3
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___S                  0

#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1         (0x005D40AC)
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___M  0xE0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___S               29

#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0        (0x005D40B0)
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___M 0xF0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___S              28

#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG           (0x005D40B4)
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___RWC     QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___M 0x0FE00000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___S              21
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___S              20
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___S              19
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___M 0x00078000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___S              15
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___M 0x00007E00
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___S               9
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___S               8
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___S               7
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___S               6
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___M 0x00000038
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___S               3
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___S                  0

#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1         (0x005D40B8)
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___M  0xE0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___S               29

#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0        (0x005D40BC)
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___M 0xF0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___S              28

#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0         (0x005D40C0)
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___S              31
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___S              30
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___S              29
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___S              28
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___M  0xF0000000   
#define   PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___S               28

#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG        (0x005D40C4)
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___POR 0x00010000
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___POR 0x00
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___S              31
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___S              16
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___S               8
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___S               0
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___M 0x800301FF   
#define   PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___S               0

#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT    (0x005D40C8)
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___M 0x00001F00
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___S               8
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___M 0x0000001F
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___S               0
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___M 0x00001F1F   
#define   PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___S               0

#define PHYA_IRON2G_RFA_AON_LDO_EN                (0x005D4100)
#define   PHYA_IRON2G_RFA_AON_LDO_EN___RWC          QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_EN___POR       0x00000000
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___M 0xFC000000
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___S              24
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___S               8
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___S               4
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___S               2
#define   PHYA_IRON2G_RFA_AON_LDO_EN___M         0xFF00FFFC   
#define   PHYA_IRON2G_RFA_AON_LDO_EN___S                       2

#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G (0x005D4104)
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___POR 0x01940194
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___POR 0x5
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___POR 0x5
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___M 0x003C0000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___S              18
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___M 0x0000003C
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___S               2
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___M 0xFFFCFFFC   
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___S               2

#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G (0x005D4108)
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___POR 0x01940194
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___POR 0x5
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___POR 0x5
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___M 0x003C0000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___S              18
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___M 0x0000003C
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___S               2
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___M 0xFFFCFFFC   
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___S               2

#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G        (0x005D410C)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___POR 0x00800080
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___M 0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___S               6

#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G        (0x005D4110)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___POR 0x00800080
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___M 0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___S               6

#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G        (0x005D4114)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___POR 0x00A000A0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___S              21
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___S               5
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___M 0xFFE0FFE0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___S               5

#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G        (0x005D4118)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___POR 0x00A000A0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___S              21
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___S               5
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___M 0xFFE0FFE0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___S               5

#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G  (0x005D411C)
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___POR 0x01800180
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___M 0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___S               6

#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G  (0x005D4120)
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___POR 0x01800180
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___M 0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___S               6

#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G         (0x005D4124)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___POR 0x02000200
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___POR 0x4
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___POR 0x4
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___M  0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___S                6

#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G         (0x005D4128)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___POR 0x02000200
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___POR 0x4
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___POR 0x4
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___S              27
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___M 0x00000380
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___M  0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___S                6

#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC     (0x005D412C)
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___S              29
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___M 0x1C000000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___S              21
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___M 0x001C0000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___S              18
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___S              13
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___M 0x00001C00
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___S              10
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___S               5
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___M 0x0000001C
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___S               2
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___M 0xFCFCFCFC   
#define   PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___S               2

#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC            (0x005D4130)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC___POR   0x00000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___S              21
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___S              13
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___S               5
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC___M     0xD0E0E0E0   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_ADC___S                   5

#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM     (0x005D4134)
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___POR 0x03608000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___M 0x07000000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___S              24
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___M 0x00E00000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___S              21
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___M 0x00180000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___S              19
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___S              18
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___M 0x00038000
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___S              15
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___M 0xC7FF8000   
#define   PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___S              15

#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO           (0x005D4138)
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___POR  0x01802000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___S              26
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___M 0x03800000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___S              23
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___S              17
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___S              16
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___M 0x0000E000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___S              13
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___S              12
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___M    0xFFFFF000   
#define   PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___S                 12

#define PHYA_IRON2G_RFA_AON_TOP_0                 (0x005D4140)
#define   PHYA_IRON2G_RFA_AON_TOP_0___RWC           QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TOP_0___POR        0x31848948
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___POR 0x3
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___POR 0x3
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___POR 0x2
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___POR 0x2
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___POR 0x1
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___POR 0x1
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___POR 0x2
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___POR 0x2
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___S              31
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___M 0x70000000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___S              28
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___S              27
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___M 0x07800000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___S              23
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___M 0x000E0000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___S              17
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___M 0x0001C000
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___S              14
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___M 0x00003800
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___S              11
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___M 0x00000700
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___S               8
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___M 0x000000E0
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___S               5
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___M 0x0000001C
#define   PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___S               2
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___S               1
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___S               0
#define   PHYA_IRON2G_RFA_AON_TOP_0___M          0xFF8FFFFF   
#define   PHYA_IRON2G_RFA_AON_TOP_0___S                        0

#define PHYA_IRON2G_RFA_AON_TOP_1                 (0x005D4144)
#define   PHYA_IRON2G_RFA_AON_TOP_1___RWC           QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TOP_1___POR        0x0000207E
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___POR 0x1
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___POR 0x3F
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___S              18
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___S              16
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___S              13
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___S              12
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___S              11
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___S              10
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___S               9
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___S               8
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___M 0x000000FE
#define   PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___S               1
#define   PHYA_IRON2G_RFA_AON_TOP_1___M          0x3FFFFFFE   
#define   PHYA_IRON2G_RFA_AON_TOP_1___S                        1

#define PHYA_IRON2G_RFA_AON_TOP_2                 (0x005D4148)
#define   PHYA_IRON2G_RFA_AON_TOP_2___RWC           QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TOP_2___POR        0x7EFE1000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___POR 0x3F
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___POR 0x3F
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___POR 0x8
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___POR 0x1
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___M 0xFE000000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___S              25
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___M 0x01FC0000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___S              18
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___M 0x0003C000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___S              14
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___S              13
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___S              12
#define   PHYA_IRON2G_RFA_AON_TOP_2___M          0xFFFFF000   
#define   PHYA_IRON2G_RFA_AON_TOP_2___S                       12

#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS            (0x005D414C)
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS___POR   0x16000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___S              29
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___S              28
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___S              26
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___S              25
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS___M     0x77000000   
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS___S                  24

#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV         (0x005D4150)
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___S              18
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___S              16
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___S              14
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___M  0xFFFFF000   
#define   PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___S               12

#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0 (0x005D4154)
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___POR 0x016800A0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___POR 0x168
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___POR 0x0A0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___M 0x01FF0000
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___S              16
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___M 0x01FF01FF   
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___S               0

#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1 (0x005D4158)
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___POR 0x016800A0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___POR 0x168
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___POR 0x0A0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___M 0x01FF0000
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___S               0
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___M 0x01FF01FF   
#define   PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___S               0

#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0 (0x005D415C)
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___POR 0x0000012C
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___POR 0x12C
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___M 0x000001FF   
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___S               0

#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1 (0x005D4160)
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___POR 0x0000012C
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___POR 0x12C
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___S               0
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___M 0x000001FF   
#define   PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___S               0

#define PHYA_IRON2G_RFA_AON_RBIST                 (0x005D4164)
#define   PHYA_IRON2G_RFA_AON_RBIST___RWC           QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RBIST___POR        0x00000000
#define   PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___S              31
#define   PHYA_IRON2G_RFA_AON_RBIST___M          0x80000000   
#define   PHYA_IRON2G_RFA_AON_RBIST___S                       31

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0     (0x005D4180)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___POR 0x00000007
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___POR 0x07
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___M 0x07000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___S              24
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___M 0xF70000FF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1     (0x005D4184)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___POR 0x05000007
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___POR 0x5
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___POR 0x007
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___M 0x07000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___S              24
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___M 0xF70001FF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2     (0x005D4188)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___POR 0x07000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___POR 0x7
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___POR 0x000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___M 0x07000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___S              24
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___M 0xF70001FF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3     (0x005D418C)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___POR 0x00AAA080
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___POR 0xA
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___POR 0xA
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___POR 0xA
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___POR 0x1
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___S              24
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___S              20
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___S              16
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___S              12
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___S              11
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___S              10
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___S               9
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___S               8
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___S               7
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___S               6
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___S               5
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___S               4
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___S               3
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___M 0xCFFFFFF8   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___S               3

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4     (0x005D4190)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___S              25
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___S              17
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___M 0x0001FE00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___S               9
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___S               8
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___M 0xFE33FFFF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5     (0x005D4194)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___M 0x0FF00000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___S              20
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___S               8
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___M 0xDFF001FF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6     (0x005D4198)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___S              28
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___S              26
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___S              24
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___S              23
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___S              22
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___S              21
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___S              20
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___S              19
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___S              18
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___S              17
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___S              16
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___S              10
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___S               9
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___S               8
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___M 0xF7FF07FF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___S               0

#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7     (0x005D419C)
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___S              11
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___M 0x00000600
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___S               9
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___M 0x00000180
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___S               7
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___M 0x00000070
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___S               4
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___S               3
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___S               0
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___S               0

#define PHYA_IRON2G_RFA_AON_AON_SPARE_0           (0x005D41A0)
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_0___S                  0

#define PHYA_IRON2G_RFA_AON_AON_SPARE_1           (0x005D41A4)
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_AON_SPARE_1___S                  0

#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT    (0x005D41A8)
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___S              31
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___S              30
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___S              29
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___S              28
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___S              24
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___M 0xFF000000   
#define   PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___S              24

#define PHYA_IRON2G_RFA_AON_SYNTH_CFG             (0x005D41C0)
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG___RWC       QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG___POR    0x80000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___POR 0x1
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___S              31
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___S              30
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___S              29
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___S              28
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___S              27
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___S              26
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___S              24
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG___M      0xFF000000   
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG___S                   24

#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV          (0x005D41C4)
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___M   0xFFC00000   
#define   PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___S                22

#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG          (0x005D41C8)
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___M 0xE0000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___S              29
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___S              28
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___S              27
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___S              26
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___S              14
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___S              13
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___S              12
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___S              11
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___S              10
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___S               9
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___S               6
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___S               5
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___M 0x00000010
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___S               4
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___M 0x00000008
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___S               3
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___M 0x00000004
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___S               2
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___M 0x00000002
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___S               1
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___M   0xFC00FEFE   
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___S                 1

#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG          (0x005D41CC)
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___S              29
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___S              28
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___M   0xF0000000   
#define   PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___S                28

#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0        (0x005D4200)
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___POR 0x0000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___POR 0x0000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___S              16
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___S               0
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___S               0

#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1        (0x005D4204)
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___POR 0x0000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___S              16
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___S              16

#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG            (0x005D4208)
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG___POR   0x00000000
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___S               4
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___S               0
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG___M     0x000000FF   
#define   PHYA_IRON2G_RFA_AON_DRM_BT_DBG___S                   0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT      (0x005D4240)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___M 0x80000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___S              31

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0 (0x005D4244)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___POR 0xC0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___S              29

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1 (0x005D4248)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___POR 0xC0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___S              29

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0 (0x005D424C)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___POR 0xC0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___S              29

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1 (0x005D4250)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___POR 0xC0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___S              29

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES (0x005D4254)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___POR 0x00BA00BA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___M 0x01FF0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___M 0x01FF01FF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7 (0x005D4258)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___POR 0xC89D7510
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___POR 0xC
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___POR 0x8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___POR 0x9
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___POR 0xD
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___POR 0x7
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___POR 0x5
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12 (0x005D425C)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___POR 0x000642EA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___POR 0x4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___POR 0xE
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___POR 0xA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7 (0x005D4260)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___POR 0xC89D7510
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___POR 0xC
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___POR 0x8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___POR 0x9
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___POR 0xD
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___POR 0x7
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___POR 0x5
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12 (0x005D4264)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___POR 0x000642EA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___POR 0x4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___POR 0xE
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___POR 0xA
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7 (0x005D4268)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___POR 0xD9467510
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___POR 0xD
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___POR 0x9
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___POR 0x4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___POR 0x7
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___POR 0x5
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11 (0x005D426C)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___POR 0x00032CEF
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___POR 0x3
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___POR 0xC
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___POR 0xE
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___POR 0xF
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7 (0x005D4270)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___POR 0xD9467510
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___POR 0xD
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___POR 0x9
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___POR 0x4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___POR 0x7
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___POR 0x5
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11 (0x005D4274)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___POR 0x00032CEF
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___POR 0x3
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___POR 0xC
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___POR 0xE
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___POR 0xF
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___M 0x000F0000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT (0x005D4278)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___POR 0x00013DB1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___POR 0x3
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___POR 0x6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___M 0x00038000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___S              15
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___M 0x00007000
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___S               9
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___S               6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___M 0x00000038
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___S               3
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___M 0x00000007
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM (0x005D427C)
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___POR 0x00000618
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___POR 0x2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___S              10
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___S               6
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___S               2
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA    (0x005D4280)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___POR 0x000D0000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___POR 0x1
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___S              21
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___M 0x00100000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___M 0x00080000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___S              19
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___S              18
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___S              17
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___S              13
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___S              11
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___S              10
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___S               9
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___S               6
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___S               2
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___M 0x003F3FFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN (0x005D4284)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___POR 0x00BA00BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___M 0x01FF0000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___M 0x01FF01FF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79 (0x005D4288)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___POR 0x00BA00BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___POR 0x0BA
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___M 0x01FF0000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___M 0x000001FF
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___M 0x01FF01FF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE    (0x005D428C)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___M 0x00600000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___S              21
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___M 0x00180000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___S              19
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___M 0x00070000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___M 0x0000F000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___M 0x00000F00
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___M 0x000000F0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___M 0x0000000F
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA      (0x005D4290)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___S              27
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___S              26
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___S              25
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___S              23
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___S              21
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___S              21

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0 (0x005D4294)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___M 0x3C000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___S              26
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___S              25
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___S              21
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___M 0x00180000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___S              19
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___S              18
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___S              17
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___M 0x00018000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___S              15
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___S              15

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1 (0x005D4298)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___M 0x3C000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___S              26
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___M 0x02000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___S              25
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___M 0x01000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___S              23
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___M 0x00200000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___S              21
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___M 0x00180000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___S              19
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___M 0x00040000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___S              18
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___M 0x00020000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___S              17
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___M 0x00018000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___S              15
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___S              15

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0 (0x005D429C)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___S              23
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___S              22

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1 (0x005D42A0)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___M 0x20000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___S              29
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___M 0x10000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___M 0x0F000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___M 0x00800000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___S              23
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___M 0x00400000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___S              22

#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT   (0x005D42A4)
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___S              31
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___M 0x08000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___S              27
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___S              26
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___M 0xBF000000   
#define   PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___S              24

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0    (0x005D42A8)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___S              30
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___S              28
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___S              26
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___S              18
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___S              14
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___S              10
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___S               6
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___S               2
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1    (0x005D42AC)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___POR 0x0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___S              24
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___S              22
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___S              20
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___M 0x000C0000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___S              18
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___M 0x00030000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___S              16
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___M 0x0000C000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___S              14
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___M 0x00003000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___S              12
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___M 0x00000C00
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___S              10
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___M 0x00000300
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___S               8
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___M 0x000000C0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___S               6
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___M 0x00000030
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___S               4
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___M 0x0000000C
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___S               2
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___M 0x00000003
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___S               0

#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG     (0x005D42B0)
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___M 0x1FFFFFFF
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___S               0
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___S               0

#define PHYA_IRON2G_RFA_AON_COEX_COEX             (0x005D42C0)
#define   PHYA_IRON2G_RFA_AON_COEX_COEX___RWC       QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_COEX_COEX___POR    0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___S              30
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___S              28
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___S              26
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___S              24
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___S              22
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___S              20
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___M 0x00000001
#define   PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___S               0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX___M      0xFFF00001   
#define   PHYA_IRON2G_RFA_AON_COEX_COEX___S                    0

#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG         (0x005D42C4)
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___M  0xC0000000   
#define   PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___S               30

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0 (0x005D42C8)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___S              31
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___S              30
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___S              15
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___S              14
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___S              13
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___S              12
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___S              11
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___S              10
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___S               9
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___S               8
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___S               7
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___S               6
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___S               5
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___M 0xC001FFE0   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___S               5

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0 (0x005D42CC)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___M 0xFF000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___S              24
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___S               8
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___S               0

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0 (0x005D42D0)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___M 0xFF000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___S              24
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___S               8
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___S               0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___S               0

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1 (0x005D42D4)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___M 0x80000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___S              31
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___M 0x40000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___S              30
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___M 0x00010000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___M 0x00008000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___S              15
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___M 0x00004000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___S              14
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___M 0x00002000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___S              13
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___M 0x00001000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___S              12
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___M 0x00000800
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___S              11
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___M 0x00000400
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___S              10
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___M 0x00000200
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___S               9
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___M 0x00000100
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___S               8
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___M 0x00000080
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___S               7
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___M 0x00000040
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___S               6
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___M 0x00000020
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___S               5
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___M 0xC001FFE0   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___S               5

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1 (0x005D42D8)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___S               0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___M 0x00FF00FF   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___S               0

#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1 (0x005D42DC)
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___POR 0x00
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___M 0xFF000000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___S              24
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___M 0x00FF0000
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___S              16
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___M 0x000000FF
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___S               0
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___M 0xFFFF00FF   
#define   PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE          (0x005D4300)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___M 0x00010000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___S              11
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___M 0x00000400
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___S              10
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___S               9
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___M 0x00000100
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___M 0x00000020
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___S               5
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___S               4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___M 0x00000008
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___S               3
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___M 0x00000004
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___S               2
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___M 0x00000002
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___S               1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___M   0x00010F3F   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF          (0x005D4304)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___M 0x00010000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___S              11
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___M 0x00000400
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___S              10
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___S               9
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___M 0x00000100
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___M 0x00000020
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___S               5
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___S               4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___M 0x00000008
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___S               3
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___M 0x00000004
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___S               2
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___M 0x00000002
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___S               1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___M   0x00010F3F   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT          (0x005D4308)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___M 0x40000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___S              30
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___M 0x1F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___M 0x00800000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___S              23
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___M 0x00400000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___S              22
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___M 0x00200000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___S              21
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___M 0x00100000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___S              20
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___M 0x00020000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___S              17
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___M 0x00010000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___M 0x00000800
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___S              11
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___M 0x00000400
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___S              10
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___M 0x00000200
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___S               9
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___M 0x00000100
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___M 0x00000020
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___S               5
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___M 0x00000010
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___S               4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___M 0x00000008
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___S               3
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___M 0x00000004
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___S               2
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___M 0x00000002
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___S               1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___M   0xDFF30F3F   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG           (0x005D430C)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___POR  0x00042431
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___POR 0x1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___POR 0x4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___POR 0x1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___POR 0x03
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___POR 0x1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___M 0x30000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___S              28
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___M 0x03F00000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___S              20
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___S              18
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___M 0x00030000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___M 0x00003800
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___S              11
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___M 0x00000400
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___S              10
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___M 0x00000200
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___S               9
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___M 0x000001F0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___S               4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___S               1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___M    0x33F73FF3   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___S                  0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL          (0x005D4310)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___M   0x00000001   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO          (0x005D4314)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___M 0x00000040
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___S               6
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___M 0x00000020
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___S               5
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___M 0x00000010
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___S               4
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___M 0x00000004
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___S               2
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___M 0x00000002
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___S               1
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___M 0x00000001
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___M   0x00000077   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG          (0x005D4318)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___M 0x00000F00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___M 0x000000FF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___M   0x00000FFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___S                 0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL    (0x005D4340)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___M 0x000000FF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___M 0x8FFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL    (0x005D4344)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___M 0x000000FF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___M 0x8FFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL    (0x005D4348)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___M 0x000000FF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___M 0x8FFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL    (0x005D434C)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___POR 0x00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___S               8
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___M 0x000000FF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___M 0x8FFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA    (0x005D4350)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL    (0x005D4354)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___M 0x00030000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___M 0x8F03FFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA    (0x005D4358)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL    (0x005D435C)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___M 0x00030000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___M 0x8F03FFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL    (0x005D4380)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___M 0x00030000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___M 0x8F03FFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL    (0x005D4384)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___POR 0x0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___POR 0x0000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___M 0x80000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___S              31
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___S              24
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___M 0x00030000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___S              16
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___M 0x8F03FFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA    (0x005D4388)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___S               0

#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA    (0x005D438C)
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___S               0
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0 (0x005D4400)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1 (0x005D4404)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2 (0x005D4408)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3 (0x005D440C)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4 (0x005D4410)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5 (0x005D4414)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6 (0x005D4418)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7 (0x005D441C)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8 (0x005D4420)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9 (0x005D4424)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10 (0x005D4428)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11 (0x005D442C)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12 (0x005D4430)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___S               0

#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13 (0x005D4434)
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___POR 0x000000
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___S               0
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___S               0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0          (0x005D4480)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___S              14
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___M   0xFFFFC000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___S                14

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1          (0x005D4484)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___S              29
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___S              25
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___S              23
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___S              19
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___S              17
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___S              15
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___S              14
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___S              13
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___S              11
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___S              10
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___S               7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___S               6
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___S               5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___S               3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___S               2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___S               1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___S                 0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2          (0x005D4488)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___S              29
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___S              25
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___S              23
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___S              19
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___S              17
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___S              15
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___S              14
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___S              13
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___S              11
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___S              10
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___S               7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___S               6
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___S               5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___S               3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___S               2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___S               1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___S                 0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3          (0x005D448C)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___S              29
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___S              25
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___S              23
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___S              19
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___S              17
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___S              15
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___S              14
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___S              13
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___S              11
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___S              10
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___S               7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___M   0xFFFFFF80   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___S                 7

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL       (0x005D4490)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___POR 0x30000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___M 0x0C000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___M 0xFC000000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___S              26

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0          (0x005D4494)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___POR 0x87C1214C
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___POR 0x87
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___POR 0x90
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___POR 0xA6
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___M 0xFF000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___M 0x00C00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___M 0x0001FE00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___M 0x000001FE
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___S               1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___M   0xFFC1FFFE   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___S                 1

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1          (0x005D4498)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___POR 0x7DF71CF0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___POR 0x1F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___POR 0x1F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___POR 0x1C
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___POR 0x1C
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___M 0xFC000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___M 0x03F00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___S              14
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___M 0x00003F00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___M 0x000000C0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___S               6
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___M   0xFFFFFFF0   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___S                 4

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0          (0x005D449C)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___POR 0x7FDFE840
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___POR 0x1FF
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___POR 0x0FF
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___M 0xFFC00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___M 0x003FE000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___S              13
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___M 0x000001E0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___S               5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___M 0x00000018
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___S               3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___M 0x00000004
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___S               2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___M   0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___S                 2

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1          (0x005D44A0)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___POR 0x089C1100
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___M 0x0E000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___S              25
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___M 0x00E00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___M 0x001C0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___M 0x00038000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___S              15
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___M 0x00007800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___S              11
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___M 0x00000780
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___S               7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___M   0xFEFFFF80   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___S                 7

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL           (0x005D44A4)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___POR  0xD8000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___M 0xC0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___M 0x38000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___M 0x04000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___M 0x02000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___S              25
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___M    0xFE000000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___S                 25

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0         (0x005D44A8)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___POR 0x81446800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___POR 0x8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___M 0x00E00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___M 0x001C0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___M 0x00030000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___M 0x0000E000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___S              13
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___S               9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___M  0xFFFFFE00   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___S                9

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1         (0x005D44AC)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___POR 0x5A55A544
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___POR 0x5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___POR 0xA
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___POR 0x5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___POR 0x5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___POR 0xA
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___POR 0x5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___M 0x00F00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___M 0x000F0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___M 0x0000F000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___S                0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2         (0x005D44B0)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___POR 0x447777BB
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___POR 0xB
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___POR 0xB
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___M 0x00F00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___M 0x000F0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___M 0x0000F000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___S                0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3         (0x005D44B4)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___POR 0xBB000444
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___POR 0xB
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___POR 0xB
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___M 0x00E00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___S              21
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___M 0x001C0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___S              18
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___M 0x00038000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___S              15
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___S                0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4         (0x005D44B8)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___POR 0x54333000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___POR 0x5
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___M 0x00F00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___M  0xFFF77000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___S               12

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0      (0x005D44BC)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___POR 0x695A2C59
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___POR 0x45
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___POR 0x45
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___POR 0x9
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___M 0xC0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___M 0x30000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___M 0x0C000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___S              26
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___M 0x00C00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___S              22
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___M 0x00380000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___S              19
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___M 0x0007F800
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___S              11
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___M 0x000007F0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___S               0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1      (0x005D44C0)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___POR 0x71111133
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___POR 0x7
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___M 0xF0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___M 0x00F00000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___S              20
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___M 0x000F0000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___S              16
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___M 0x0000F000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___S              12
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___S               8
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___S               4
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___S               0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___S               0

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2      (0x005D44C4)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___POR 0xC0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___M 0xC0000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___S              30
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___M 0xC0000000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___S              30

#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER   (0x005D44C8)
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___POR 0x22000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___M 0x30000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___M 0x08000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___S              24
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___M 0xBB000000   
#define   PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___S              24

#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP      (0x005D44CC)
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___POR 0x00000000
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___M 0x80000000
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___S              31
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___M 0x70000000
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___S              28
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___M 0x08000000
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___S              27
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___M 0xF8000000   
#define   PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___S              27

#define PHYA_IRON2G_RFA_CLKGEN_TESTREG            (0x005D4800)
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG___POR   0x0C1036E0
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___POR 0x0C1036E0
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG___M     0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_TESTREG___S                   0

#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0          (0x005D4804)
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___POR 0x080BDD07
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___POR 0x8
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___POR 0x5
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___POR 0x7
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___POR 0x5
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___POR 0x07
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___M 0xF0000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___M 0x0F000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___M 0x00300000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___M 0x000E0000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___M 0x0001C000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___M 0x00003800
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___M 0x00000700
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___M 0x000000E0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___M 0x0000001F
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___M   0xFFBFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___S                 0

#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1          (0x005D4808)
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___POR 0xF2000010
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___POR 0xF
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___M 0xF0000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___M 0x03000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___M 0x00200000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___S              21
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___M 0x0001C000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___S               4
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___M   0xFFEFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___S                 0

#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2          (0x005D480C)
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___POR 0x30000001
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___S               2
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___M   0xFC000007   
#define   PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___S                 0

#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL         (0x005D4810)
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___M 0x00001000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___M 0x00000300
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___M 0x000000E0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___M 0x0000001F
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___M  0x00003FFF   
#define   PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___S                0

#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0            (0x005D4814)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___POR   0x00000200
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___POR 0x4
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___M 0x00000380
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___M     0xF040FFC0   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___S                   6

#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1            (0x005D4818)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___POR   0x02000128
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___POR 0x4
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___POR 0xA
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___M 0x03800000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___M 0x00000380
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___M 0x0000003C
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___S               2
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___M     0xFFC0FFFC   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___S                   2

#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL    (0x005D481C)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___POR 0x0F840F84
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___POR 0x7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___POR 0x7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___M 0x0E000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___S              25
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___M 0x01800000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___M 0x00200000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___S              21
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___M 0x001C0000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___M 0x00020000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___M 0x00000E00
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___M 0x00000180
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___M 0x00000020
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___M 0x0000001C
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___S               2
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___M 0x00000002
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___S               1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___M 0xFFFEFFFE   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___S               1

#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0          (0x005D4820)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___POR 0x01800080
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___M 0x03800000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___M 0x00000380
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___M   0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___S                 6

#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1          (0x005D4824)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___POR 0x00800180
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___M 0x03800000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___M 0x00000380
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___M   0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___S                 6

#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2          (0x005D4828)
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___POR 0x00800080
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___M 0x03800000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___M 0x00400000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___M 0x00000380
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___M   0xFFC0FFC0   
#define   PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___S                 6

#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN          (0x005D482C)
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___M 0x00000400
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___M 0x00000200
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___M 0x00000100
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___M 0x00000080
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___M 0x00000020
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___M 0x00000010
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___S               4
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___M 0x00000008
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___S               3
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___M   0xC0000FFF   
#define   PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___S                 0

#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0           (0x005D4830)
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___M    0xFFFFFF00   
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___S                  8

#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1           (0x005D4834)
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___S               4
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___S                  0

#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2           (0x005D4838)
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___POR  0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___M 0x00040000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___M 0x000000FE
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___S               1
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___M 0x00000001
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___M    0xFCFFC0FF   
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___S                  0

#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3           (0x005D483C)
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___POR  0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___S                  0

#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1          (0x005D4840)
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___S                 0

#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0      (0x005D4844)
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___S               0

#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL     (0x005D4848)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___POR 0x000018A0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___M 0x3F000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___M 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___M 0x00000180
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___M 0x00000060
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___M 0xBFFFFFE0   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___S               5

#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL     (0x005D484C)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___POR 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___M 0x3F000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___M 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___M 0x00000180
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___M 0xBFFFFF80   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___S               7

#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL     (0x005D4850)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___POR 0x00001880
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___M 0x3F000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___M 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___M 0x00000180
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___M 0xBFFFFF80   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___S               7

#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL      (0x005D4854)
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___POR 0x00001880
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___M 0x3F000000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___M 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___M 0x00000180
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___M 0xBFFFFF80   
#define   PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___S               7

#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0           (0x005D4858)
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___POR  0x0000001C
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___M 0x00000020
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___M 0x00000018
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___S               3
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___M 0x00000006
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___S               1
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___M    0x00030FFE   
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___S                  1

#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2           (0x005D485C)
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___POR  0x01C01800
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___S              25
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___M 0x01800000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___M 0x00600000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___S              21
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___M 0x00100000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___S              19
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___M 0x00001800
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___S              11
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___M    0xFFFFF800   
#define   PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___S                 11

#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0  (0x005D4860)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___POR 0x01C00000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___S              25
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___M 0x01800000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___M 0x00600000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___S              21
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___S              21

#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0         (0x005D4864)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___POR 0x00000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___M 0x0003FFFF
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___M  0x3FF7FFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___S                0

#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1         (0x005D4868)
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___POR 0x00000C00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___M 0x00FE0000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___M 0x00018000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___S              15
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___M 0x00006000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___M 0x00000200
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___M 0x00000100
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___M 0x000000C0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___M  0xFFFFFFC7   
#define   PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___S                0

#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0      (0x005D486C)
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___POR 0x01C00000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___POR 0x3
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___POR 0x2
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___S              25
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___M 0x01800000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___S              23
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___M 0x00600000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___S              21
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___S              21

#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0       (0x005D4870)
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___POR 0x00000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___M 0x0003FFFF
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___M 0x3FF7FFFF   
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___S               0

#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1       (0x005D4874)
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___POR 0x00
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___S              27
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___S              24
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___M 0x00FE0000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___S              17
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___M 0x00018000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___S              15
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___M 0x00006000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___S              13
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___S              10
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___M 0x00000200
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___S               9
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___M 0x00000007
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___M 0xFFFFFE07   
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___S               0

#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0      (0x005D4878)
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___POR 0x00000030
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___POR 0x1
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___M 0x60000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___S              29
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___S              16
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___M 0x00000100
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___S               8
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___M 0x00000080
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___S               7
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___M 0x00000040
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___S               6
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___M 0x00000020
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___S               5
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___M 0x00000010
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___S               4
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___M 0x00000008
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___S               3
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___S               2
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___M 0x00000002
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___S               1
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___M 0x00000001
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___M 0xFC3FF1FF   
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___S               0

#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1      (0x005D487C)
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___M 0xF0000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___S              28
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___S              26
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___M 0xFC000000   
#define   PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___S              26

#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0 (0x005D4880)
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___POR 0x0000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___M 0x40000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___M 0x00007FFF
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___M 0xC0007FFF   
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___S               0

#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1 (0x005D4884)
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___POR 0x0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___POR 0x0000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___M 0x80000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___S              31
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___M 0x40000000
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___S              30
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___M 0x00007FFF
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___S               0
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___M 0xC0007FFF   
#define   PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___S               0

#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0         (0x005D4C00)
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___POR 0x00001F08
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___POR 0x01F
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___POR 0x08
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___M 0x00040000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___S              18
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___M 0x00020000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___S              17
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___M 0x0001FF00
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___S               8
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___S               6
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___S               5
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___S               0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___M  0x0007FFFF   
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___S                0

#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1         (0x005D4C04)
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___POR 0x00002300
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___S              31
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___M 0x00018000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___S              15
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___M 0x00006000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___S              13
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___M 0x00001000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___S              12
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___M 0x00000800
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___S              11
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___M 0x00000700
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___S               8
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___S               0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___M  0x8001FFFF   
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___S                0

#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2         (0x005D4C08)
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___M 0x80000000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___S              31
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___M  0x80000000   
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___S               31

#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3         (0x005D4C0C)
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___POR 0x00000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___POR 0x000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___M 0xFFFFC000
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___S              14
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___M 0x00003FF0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___S               4
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___M 0x00000008
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___S               3
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___M 0x00000004
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___S               2
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___S                0

#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL           (0x005D4C10)
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___RWC     QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___POR  0x00000000
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___POR 0x00000
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___POR 0x000
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___M 0x40000000
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___S              30
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___M 0x3FFFF000
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___S              12
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___M 0x000003FF
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___S               0
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___M    0x7FFFF3FF   
#define   PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___S                  0

#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0           (0x005D5000)
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___POR  0x00001F88
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___POR 0x01F
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___POR 0x08
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___M 0x00040000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___S              18
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___M 0x00020000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___S              17
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___M 0x0001FF00
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___S               8
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___S               6
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___S               5
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___S               0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___M    0x0007FFFF   
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___S                  0

#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1           (0x005D5004)
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___POR  0x0001E300
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___POR 0x3
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___POR 0x3
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___S              31
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___M 0x00018000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___S              15
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___M 0x00006000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___S              13
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___M 0x00001000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___S              12
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___M 0x00000800
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___S              11
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___M 0x00000700
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___S               8
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___S               0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___M    0x8001FFFF   
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___S                  0

#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2           (0x005D5008)
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___POR  0x00000000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___M 0x80000000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___S              31
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___M    0x80000000   
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___S                 31

#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3           (0x005D500C)
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___POR  0x80000000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___POR 0x20000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___POR 0x000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___M 0xFFFFC000
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___S              14
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___M 0x00003FF0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___S               4
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___M 0x00000008
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___S               3
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___M 0x00000004
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___S               2
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___S                  0

#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL             (0x005D5010)
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL___RWC       QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL___POR    0x00000000
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___POR 0x00000
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___POR 0x000
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___M 0x40000000
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___S              30
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___M 0x3FFFF000
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___S              12
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___M 0x000003FF
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___S               0
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL___M      0x7FFFF3FF   
#define   PHYA_IRON2G_RFA_BBPLL_RO_DPLL___S                    0

#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN  (0x005D5400)
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___POR 0x0000000C
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___S              14
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___S              12
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___S               3
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___S               2
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___M 0x00FF5FFC   
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___S               2

#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1 (0x005D5404)
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___POR 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___S               4
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___S               3
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___S               2
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___S               1
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___S               0
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___M 0x0000001F   
#define   PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0 (0x005D6000)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___POR 0x0221D532
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___POR 0x004
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___POR 0x21D532
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1 (0x005D6004)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2 (0x005D6008)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___POR 0x0042AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___POR 0x42AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3 (0x005D600C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___POR 0x55000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___POR 0x0AA
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0 (0x005D6010)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___POR 0x116C2599
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___POR 0x9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1 (0x005D6014)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___POR 0x80680000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___M 0x00007C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___M 0xFFF87FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2 (0x005D6018)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___POR 0x400
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0 (0x005D601C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1 (0x005D6020)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___M 0xFFFF7FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2 (0x005D6024)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___M 0xFF0FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3 (0x005D6028)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4 (0x005D602C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5 (0x005D6030)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6 (0x005D6034)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___M 0x0001F800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0 (0x005D6040)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___POR 0x44A43E4A
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___M 0xFCFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1 (0x005D6044)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___POR 0xB4208000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___S              15

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS (0x005D6048)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2 (0x005D604C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___S              25

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0 (0x005D6050)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1 (0x005D6054)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2 (0x005D6058)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3 (0x005D605C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4 (0x005D6060)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5 (0x005D6064)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6 (0x005D6068)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7 (0x005D606C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8 (0x005D6070)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9 (0x005D6074)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10 (0x005D6078)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11 (0x005D607C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12 (0x005D6080)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13 (0x005D6084)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14 (0x005D6088)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15 (0x005D608C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16 (0x005D6090)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17 (0x005D6094)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18 (0x005D6098)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19 (0x005D609C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20 (0x005D60A0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21 (0x005D60A4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22 (0x005D60A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23 (0x005D60AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24 (0x005D60B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25 (0x005D60B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26 (0x005D60B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27 (0x005D60BC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28 (0x005D60C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29 (0x005D60C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30 (0x005D60C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31 (0x005D60CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST (0x005D6100)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___POR 0x06C0F998
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___S               3

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0 (0x005D6104)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___M 0xC7FF07FF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1 (0x005D6108)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2 (0x005D610C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3 (0x005D6110)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4 (0x005D6114)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5 (0x005D6118)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6 (0x005D611C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0 (0x005D6140)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___POR 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1 (0x005D6144)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2 (0x005D6148)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___S               8

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3 (0x005D614C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4 (0x005D6150)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___M 0xE00FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5 (0x005D6154)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___M 0xFF3FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6 (0x005D6158)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___POR 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___M 0x3F01FFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7 (0x005D615C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8 (0x005D6160)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___M 0x18000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0 (0x005D6180)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___POR 0xAF682022
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1 (0x005D6184)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___POR 0x8F669A44
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2 (0x005D6188)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___POR 0x6F859677
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3 (0x005D618C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___POR 0x6F851499
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4 (0x005D6190)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___POR 0xAF6820AA
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5 (0x005D6194)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___POR 0x8F669ADD
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6 (0x005D6198)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___POR 0x6F8596EE
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7 (0x005D619C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___POR 0x6F8514FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0 (0x005D61A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___POR 0x10120F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___POR 0x020
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___POR 0x048
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___POR 0x078
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1 (0x005D61AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___POR 0x5C3EE7A0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___POR 0x0B8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___POR 0x0FB
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___POR 0x13D
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2 (0x005D61B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___POR 0xBE800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___POR 0x17D
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___M 0xFF8000FE   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3 (0x005D61B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4 (0x005D61B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___M 0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___S              14

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0 (0x005D61C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___POR 0x00068000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___M 0x11CFF800   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___S              11

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1 (0x005D61C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___POR 0x0000301B
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___M 0x0000703F   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2 (0x005D61C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___POR 0x6D860000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___M 0xFF8E0002   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3 (0x005D61CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___POR 0x00300001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___M 0x00308003   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4 (0x005D61D0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___M 0x03E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___M 0xE3FE0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___S              17

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5 (0x005D61D4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6 (0x005D61D8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7 (0x005D61DC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___S              21

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0 (0x005D61E0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1 (0x005D61E4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___M 0xE0000003   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8 (0x005D61E8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___POR 0x1CA2B95C
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9 (0x005D61EC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___POR 0x1C7C6000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___S              10

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10 (0x005D61F0)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___POR 0x2210000F
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___M 0xFF1F800F   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11 (0x005D61F4)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___POR 0x03000018
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___M 0x0FFFF81F   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12 (0x005D61F8)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13 (0x005D61FC)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0 (0x005D6240)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___POR 0x091B0C00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0 (0x005D6244)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1 (0x005D6248)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1 (0x005D624C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2 (0x005D6250)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___POR 0x091B0C40
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2 (0x005D6254)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3 (0x005D6258)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3 (0x005D625C)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL (0x005D6280)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___M 0xFF800003   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO (0x005D6288)
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0 (0x005D6800)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___POR 0x0221D532
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___POR 0x004
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___POR 0x21D532
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1 (0x005D6804)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2 (0x005D6808)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___POR 0x0042AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___POR 0x42AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3 (0x005D680C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___POR 0x55000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___POR 0x0AA
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0 (0x005D6810)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___POR 0x116C2599
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___POR 0x9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1 (0x005D6814)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___POR 0x80680000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___M 0x00007C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___M 0xFFF87FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2 (0x005D6818)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___POR 0x400
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0 (0x005D681C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1 (0x005D6820)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___M 0xFFFF7FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2 (0x005D6824)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___M 0xFF0FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3 (0x005D6828)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4 (0x005D682C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5 (0x005D6830)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6 (0x005D6834)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___M 0x0001F800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0 (0x005D6840)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___POR 0x44A43E4A
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___M 0xFCFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1 (0x005D6844)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___POR 0xB4208000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___S              15

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS (0x005D6848)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2 (0x005D684C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___S              25

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0 (0x005D6850)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1 (0x005D6854)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2 (0x005D6858)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3 (0x005D685C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4 (0x005D6860)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5 (0x005D6864)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6 (0x005D6868)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7 (0x005D686C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8 (0x005D6870)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9 (0x005D6874)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10 (0x005D6878)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11 (0x005D687C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12 (0x005D6880)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13 (0x005D6884)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14 (0x005D6888)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15 (0x005D688C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16 (0x005D6890)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17 (0x005D6894)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18 (0x005D6898)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19 (0x005D689C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20 (0x005D68A0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21 (0x005D68A4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22 (0x005D68A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23 (0x005D68AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24 (0x005D68B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25 (0x005D68B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26 (0x005D68B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27 (0x005D68BC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28 (0x005D68C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29 (0x005D68C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30 (0x005D68C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31 (0x005D68CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST (0x005D6900)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___POR 0x06C0F998
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___S               3

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0 (0x005D6904)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___M 0xC7FF07FF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1 (0x005D6908)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2 (0x005D690C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3 (0x005D6910)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4 (0x005D6914)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5 (0x005D6918)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6 (0x005D691C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0 (0x005D6940)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___POR 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1 (0x005D6944)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2 (0x005D6948)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___S               8

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3 (0x005D694C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4 (0x005D6950)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___M 0xE00FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5 (0x005D6954)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___M 0xFF3FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6 (0x005D6958)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___POR 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___M 0x3F01FFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7 (0x005D695C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8 (0x005D6960)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___M 0x18000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0 (0x005D6980)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___POR 0xAF682022
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1 (0x005D6984)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___POR 0x8F669A44
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2 (0x005D6988)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___POR 0x6F859677
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3 (0x005D698C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___POR 0x6F851499
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4 (0x005D6990)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___POR 0xAF6820AA
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5 (0x005D6994)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___POR 0x8F669ADD
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6 (0x005D6998)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___POR 0x6F8596EE
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7 (0x005D699C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___POR 0x6F8514FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0 (0x005D69A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___POR 0x10120F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___POR 0x020
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___POR 0x048
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___POR 0x078
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1 (0x005D69AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___POR 0x5C3EE7A0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___POR 0x0B8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___POR 0x0FB
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___POR 0x13D
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2 (0x005D69B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___POR 0xBE800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___POR 0x17D
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___M 0xFF8000FE   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3 (0x005D69B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4 (0x005D69B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___M 0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___S              14

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0 (0x005D69C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___POR 0x00068000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___M 0x11CFF800   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___S              11

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1 (0x005D69C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___POR 0x0000301B
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___M 0x0000703F   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2 (0x005D69C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___POR 0x6D860000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___M 0xFF8E0002   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3 (0x005D69CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___POR 0x00300001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___M 0x00308003   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4 (0x005D69D0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___M 0x03E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___M 0xE3FE0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___S              17

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5 (0x005D69D4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6 (0x005D69D8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7 (0x005D69DC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___S              21

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0 (0x005D69E0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1 (0x005D69E4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___M 0xE0000003   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8 (0x005D69E8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___POR 0x1CA2B95C
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9 (0x005D69EC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___POR 0x1C7C6000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___S              10

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10 (0x005D69F0)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___POR 0x2210000F
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___M 0xFF1F800F   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11 (0x005D69F4)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___POR 0x03000018
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___M 0x0FFFF81F   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12 (0x005D69F8)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13 (0x005D69FC)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0 (0x005D6A40)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___POR 0x091B0C00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0 (0x005D6A44)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1 (0x005D6A48)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1 (0x005D6A4C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2 (0x005D6A50)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___POR 0x091B0C40
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2 (0x005D6A54)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3 (0x005D6A58)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3 (0x005D6A5C)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL (0x005D6A80)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___M 0xFF800003   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO (0x005D6A88)
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0 (0x005D7000)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___POR 0x0221D532
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___POR 0x004
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___POR 0x21D532
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1 (0x005D7004)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2 (0x005D7008)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___POR 0x0042AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___POR 0x42AAAA
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3 (0x005D700C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___POR 0x55000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___POR 0x0AA
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0 (0x005D7010)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___POR 0x116C2599
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___POR 0x9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1 (0x005D7014)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___POR 0x80680000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___M 0x00007C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___M 0xFFF87FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2 (0x005D7018)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___POR 0x400
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0 (0x005D701C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1 (0x005D7020)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___M 0xFFFF7FFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2 (0x005D7024)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___M 0xFF0FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3 (0x005D7028)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4 (0x005D702C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5 (0x005D7030)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6 (0x005D7034)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___M 0x0001F800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0 (0x005D7040)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___POR 0x44A43E4A
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___M 0xFCFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1 (0x005D7044)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___POR 0xB4208000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___S              15

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS (0x005D7048)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2 (0x005D704C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___S              25

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0 (0x005D7050)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1 (0x005D7054)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2 (0x005D7058)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3 (0x005D705C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4 (0x005D7060)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5 (0x005D7064)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6 (0x005D7068)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7 (0x005D706C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8 (0x005D7070)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9 (0x005D7074)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10 (0x005D7078)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11 (0x005D707C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12 (0x005D7080)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13 (0x005D7084)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14 (0x005D7088)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15 (0x005D708C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16 (0x005D7090)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17 (0x005D7094)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18 (0x005D7098)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19 (0x005D709C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20 (0x005D70A0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21 (0x005D70A4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22 (0x005D70A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23 (0x005D70AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24 (0x005D70B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25 (0x005D70B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26 (0x005D70B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27 (0x005D70BC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28 (0x005D70C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29 (0x005D70C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30 (0x005D70C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31 (0x005D70CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___S              28

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST (0x005D7100)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___POR 0x06C0F998
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___S               3

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0 (0x005D7104)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___M 0xC7FF07FF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1 (0x005D7108)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2 (0x005D710C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3 (0x005D7110)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4 (0x005D7114)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5 (0x005D7118)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6 (0x005D711C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0 (0x005D7140)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___POR 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1 (0x005D7144)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2 (0x005D7148)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___S               8

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3 (0x005D714C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4 (0x005D7150)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___M 0xE00FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5 (0x005D7154)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___M 0xFF3FFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6 (0x005D7158)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___POR 0x00001C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___M 0x3F01FFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7 (0x005D715C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___S              24

#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8 (0x005D7160)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___M 0x18000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___S              23

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0 (0x005D7180)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___POR 0xAF682022
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1 (0x005D7184)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___POR 0x8F669A44
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2 (0x005D7188)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___POR 0x6F859677
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3 (0x005D718C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___POR 0x6F851499
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4 (0x005D7190)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___POR 0xAF6820AA
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5 (0x005D7194)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___POR 0x8F669ADD
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6 (0x005D7198)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___POR 0x6F8596EE
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7 (0x005D719C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___POR 0x6F8514FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0 (0x005D71A8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___POR 0x10120F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___POR 0x020
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___POR 0x048
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___POR 0x078
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1 (0x005D71AC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___POR 0x5C3EE7A0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___POR 0x0B8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___POR 0x0FB
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___POR 0x13D
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___M 0x00003FE0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___S               5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___S               5

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2 (0x005D71B0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___POR 0xBE800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___POR 0x17D
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___S               2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___M 0xFF8000FE   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3 (0x005D71B4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4 (0x005D71B8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___M 0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___S              14

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0 (0x005D71C0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___POR 0x00068000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___M 0x11CFF800   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___S              11

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1 (0x005D71C4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___POR 0x0000301B
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___M 0x0000703F   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2 (0x005D71C8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___POR 0x6D860000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___M 0xFF8E0002   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___S               1

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3 (0x005D71CC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___POR 0x00300001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___M 0x00308003   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4 (0x005D71D0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___M 0x03E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___M 0xE3FE0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___S              17

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5 (0x005D71D4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6 (0x005D71D8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7 (0x005D71DC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___S              21

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0 (0x005D71E0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___POR 0x00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___S              14
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1 (0x005D71E4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___M 0xE0000003   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8 (0x005D71E8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___POR 0x1CA2B95C
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9 (0x005D71EC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___POR 0x1C7C6000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___S              31
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___S              26
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___S              10
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___S              10

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10 (0x005D71F0)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___POR 0x2210000F
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___S              18
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___S              17
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___M 0xFF1F800F   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11 (0x005D71F4)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___POR 0x03000018
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___S              22
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___S               4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S               3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___M 0x0FFFF81F   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12 (0x005D71F8)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13 (0x005D71FC)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___POR 0x007FF7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___M 0x007FF000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___S              11
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0 (0x005D7240)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___POR 0x091B0C00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0 (0x005D7244)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1 (0x005D7248)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1 (0x005D724C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2 (0x005D7250)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___POR 0x091B0C40
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2 (0x005D7254)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___POR 0x67850000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3 (0x005D7258)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___POR 0x212B8640
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___S              29
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___S              19
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___S              15
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___S              13
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___S               9
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___S               6
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___S               6

#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3 (0x005D725C)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___POR 0x38410000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___S              24
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S              20
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S              16
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___S              16

#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL (0x005D7280)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___S              27
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___S              23
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___S               1
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___M 0xFF800003   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___S               0

#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO (0x005D7288)
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___S               0
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00 (0x005D7C00)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01 (0x005D7C04)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02 (0x005D7C08)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03 (0x005D7C0C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04 (0x005D7C10)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05 (0x005D7C14)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06 (0x005D7C18)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07 (0x005D7C1C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08 (0x005D7C20)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09 (0x005D7C24)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10 (0x005D7C28)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11 (0x005D7C2C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12 (0x005D7C30)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13 (0x005D7C34)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14 (0x005D7C38)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15 (0x005D7C3C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16 (0x005D7C40)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17 (0x005D7C44)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18 (0x005D7C48)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19 (0x005D7C4C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20 (0x005D7C50)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21 (0x005D7C54)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22 (0x005D7C58)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23 (0x005D7C5C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24 (0x005D7C60)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25 (0x005D7C64)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26 (0x005D7C68)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27 (0x005D7C6C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28 (0x005D7C70)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29 (0x005D7C74)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30 (0x005D7C78)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31 (0x005D7C7C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32 (0x005D7C80)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33 (0x005D7C84)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34 (0x005D7C88)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35 (0x005D7C8C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36 (0x005D7C90)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37 (0x005D7C94)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38 (0x005D7C98)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39 (0x005D7C9C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40 (0x005D7CA0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41 (0x005D7CA4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42 (0x005D7CA8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43 (0x005D7CAC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44 (0x005D7CB0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45 (0x005D7CB4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46 (0x005D7CB8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47 (0x005D7CBC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48 (0x005D7CC0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49 (0x005D7CC4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50 (0x005D7CC8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51 (0x005D7CCC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52 (0x005D7CD0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53 (0x005D7CD4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54 (0x005D7CD8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55 (0x005D7CDC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56 (0x005D7CE0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57 (0x005D7CE4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58 (0x005D7CE8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59 (0x005D7CEC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60 (0x005D7CF0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61 (0x005D7CF4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62 (0x005D7CF8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63 (0x005D7CFC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64 (0x005D7D00)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65 (0x005D7D04)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66 (0x005D7D08)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67 (0x005D7D0C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68 (0x005D7D10)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69 (0x005D7D14)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70 (0x005D7D18)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71 (0x005D7D1C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72 (0x005D7D20)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73 (0x005D7D24)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74 (0x005D7D28)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75 (0x005D7D2C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76 (0x005D7D30)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77 (0x005D7D34)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78 (0x005D7D38)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79 (0x005D7D3C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80 (0x005D7D40)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81 (0x005D7D44)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82 (0x005D7D48)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83 (0x005D7D4C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84 (0x005D7D50)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85 (0x005D7D54)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86 (0x005D7D58)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87 (0x005D7D5C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88 (0x005D7D60)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89 (0x005D7D64)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90 (0x005D7D68)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91 (0x005D7D6C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92 (0x005D7D70)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93 (0x005D7D74)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94 (0x005D7D78)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95 (0x005D7D7C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96 (0x005D7D80)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97 (0x005D7D84)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98 (0x005D7D88)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99 (0x005D7D8C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100 (0x005D7D90)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101 (0x005D7D94)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102 (0x005D7D98)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103 (0x005D7D9C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104 (0x005D7DA0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105 (0x005D7DA4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106 (0x005D7DA8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107 (0x005D7DAC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108 (0x005D7DB0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109 (0x005D7DB4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110 (0x005D7DB8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111 (0x005D7DBC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112 (0x005D7DC0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113 (0x005D7DC4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114 (0x005D7DC8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115 (0x005D7DCC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116 (0x005D7DD0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117 (0x005D7DD4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118 (0x005D7DD8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119 (0x005D7DDC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120 (0x005D7DE0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121 (0x005D7DE4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122 (0x005D7DE8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123 (0x005D7DEC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124 (0x005D7DF0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125 (0x005D7DF4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126 (0x005D7DF8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127 (0x005D7DFC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128 (0x005D7E00)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129 (0x005D7E04)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130 (0x005D7E08)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131 (0x005D7E0C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132 (0x005D7E10)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133 (0x005D7E14)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134 (0x005D7E18)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135 (0x005D7E1C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136 (0x005D7E20)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137 (0x005D7E24)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138 (0x005D7E28)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139 (0x005D7E2C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140 (0x005D7E30)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141 (0x005D7E34)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142 (0x005D7E38)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143 (0x005D7E3C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144 (0x005D7E40)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145 (0x005D7E44)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146 (0x005D7E48)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147 (0x005D7E4C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148 (0x005D7E50)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149 (0x005D7E54)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150 (0x005D7E58)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151 (0x005D7E5C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152 (0x005D7E60)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153 (0x005D7E64)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154 (0x005D7E68)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155 (0x005D7E6C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156 (0x005D7E70)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157 (0x005D7E74)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158 (0x005D7E78)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159 (0x005D7E7C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160 (0x005D7E80)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161 (0x005D7E84)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162 (0x005D7E88)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163 (0x005D7E8C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164 (0x005D7E90)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165 (0x005D7E94)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166 (0x005D7E98)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167 (0x005D7E9C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168 (0x005D7EA0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169 (0x005D7EA4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170 (0x005D7EA8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171 (0x005D7EAC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172 (0x005D7EB0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173 (0x005D7EB4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174 (0x005D7EB8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175 (0x005D7EBC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176 (0x005D7EC0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177 (0x005D7EC4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178 (0x005D7EC8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179 (0x005D7ECC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180 (0x005D7ED0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181 (0x005D7ED4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182 (0x005D7ED8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183 (0x005D7EDC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184 (0x005D7EE0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185 (0x005D7EE4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186 (0x005D7EE8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187 (0x005D7EEC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188 (0x005D7EF0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189 (0x005D7EF4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190 (0x005D7EF8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191 (0x005D7EFC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192 (0x005D7F00)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193 (0x005D7F04)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194 (0x005D7F08)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195 (0x005D7F0C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196 (0x005D7F10)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197 (0x005D7F14)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198 (0x005D7F18)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199 (0x005D7F1C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200 (0x005D7F20)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201 (0x005D7F24)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202 (0x005D7F28)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203 (0x005D7F2C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204 (0x005D7F30)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205 (0x005D7F34)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206 (0x005D7F38)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207 (0x005D7F3C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208 (0x005D7F40)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209 (0x005D7F44)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210 (0x005D7F48)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211 (0x005D7F4C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212 (0x005D7F50)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213 (0x005D7F54)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214 (0x005D7F58)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215 (0x005D7F5C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216 (0x005D7F60)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217 (0x005D7F64)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218 (0x005D7F68)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219 (0x005D7F6C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220 (0x005D7F70)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221 (0x005D7F74)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222 (0x005D7F78)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223 (0x005D7F7C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224 (0x005D7F80)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225 (0x005D7F84)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226 (0x005D7F88)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227 (0x005D7F8C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228 (0x005D7F90)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229 (0x005D7F94)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230 (0x005D7F98)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231 (0x005D7F9C)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232 (0x005D7FA0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233 (0x005D7FA4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234 (0x005D7FA8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235 (0x005D7FAC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236 (0x005D7FB0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237 (0x005D7FB4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238 (0x005D7FB8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239 (0x005D7FBC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240 (0x005D7FC0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241 (0x005D7FC4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242 (0x005D7FC8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243 (0x005D7FCC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244 (0x005D7FD0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245 (0x005D7FD4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246 (0x005D7FD8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247 (0x005D7FDC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248 (0x005D7FE0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249 (0x005D7FE4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250 (0x005D7FE8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR (0x005D7FEC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA (0x005D7FF0)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL (0x005D7FF4)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___M 0x00000002
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___S               1
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___M 0x00000001
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___M 0x00000003   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA (0x005D7FF8)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___S               0

#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS (0x005D7FFC)
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___S               0
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS           (0x005DC000)
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___POR  0x00000444
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___POR 0x4
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___POR 0x4
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___POR 0x4
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___S              14
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___M    0x00007F77   
#define   PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0     (0x005DC004)
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___S               1
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___M 0x00000002   
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___S               1

#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1     (0x005DC008)
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___S               5
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___M 0x00000010
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2     (0x005DC00C)
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___POR 0x000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___S              10
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___M 0x00000DFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV          (0x005DC010)
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___S              14
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___M   0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___S                 0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0           (0x005DC014)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___S              17
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___M    0xFFF7FF7F   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1           (0x005DC018)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___S              29
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___S              17
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___M 0x000007C0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___S               5
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___M    0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2           (0x005DC01C)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___M    0x1FFF1FFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3           (0x005DC020)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___S               5
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___M    0x000001FF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV   (0x005DC024)
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0           (0x005DC028)
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___S               5
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___M    0xFFFF0F3F   
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1           (0x005DC02C)
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___M    0xF000FFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2           (0x005DC030)
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___S              29
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___S              26
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___S              25
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___M 0x01C00000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___S              22
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___S              21
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___M 0x00180000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___S              19
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___M 0x00038000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___S              14
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___S              10
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE         (0x005DC034)
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___S              17
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___M  0x000707FF   
#define   PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___S                0

#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0           (0x005DC038)
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1           (0x005DC03C)
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV        (0x005DC040)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___POR 0x00000046
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___S               9
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___M 0x000007F7   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV        (0x005DC044)
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___POR 0x00000066
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___S               9
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___S               6
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___M 0x000007F7   
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3           (0x005DC048)
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___M    0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0 (0x005DC04C)
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___S              31
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___S              27
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___S              19
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1 (0x005DC050)
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___S              31
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___S              27
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___S              19
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2 (0x005DC054)
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___S              31
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___S              27
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___S              24
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___S              19
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___S              15
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3 (0x005DC058)
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___S              11
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___S               7
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___S               3
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR           (0x005DC05C)
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___POR 0x0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___S              27
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___M 0x07FFFFFF
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___M    0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0       (0x005DC060)
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___M 0x00000004   
#define   PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___S               2

#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS           (0x005DC064)
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___S              20
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___S              16
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___S              12
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___S               4
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___M    0xF0777777   
#define   PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___S                  0

#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL (0x005DC068)
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0 (0x005DC06C)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1 (0x005DC070)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2 (0x005DC074)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3 (0x005DC078)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4 (0x005DC07C)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5 (0x005DC080)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6 (0x005DC084)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7 (0x005DC088)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8 (0x005DC08C)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___POR 0x00000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9 (0x005DC090)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___POR 0x00000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10 (0x005DC094)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___POR 0x00800002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11 (0x005DC098)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___POR 0x00800002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___POR 0x1
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12 (0x005DC09C)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13 (0x005DC0A0)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14 (0x005DC0A4)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___S               0

#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15 (0x005DC0A8)
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___POR 0x01000002
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___POR 0x2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___S              23
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___S              18
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___S              13
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___S               8
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___M 0x000000FC
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___S               2
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___S               0
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0       (0x005DC800)
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___POR 0x00082E00
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___POR 0x08
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___S              28
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___S              16
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___S              13
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___S               7
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___M 0x0000003C
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___S               2
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___S               1
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___M 0xF01F7FBF   
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT      (0x005DC804)
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___POR 0x0000033E
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___POR 0x3
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___POR 0x3
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___POR 0xE
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___S               4
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___M 0x000007FF   
#define   PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0           (0x005DC808)
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___M 0x00600000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___S              21
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___S              20
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___S              12
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___M    0x007F1F3F   
#define   PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___S                  0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL (0x005DC80C)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___M 0x0000003F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL (0x005DC810)
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___M 0x0000001F   
#define   PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0   (0x005DC814)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1   (0x005DC818)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2   (0x005DC81C)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3   (0x005DC820)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4   (0x005DC824)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5   (0x005DC828)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6   (0x005DC82C)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7   (0x005DC830)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8   (0x005DC834)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9   (0x005DC838)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10  (0x005DC83C)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11  (0x005DC840)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12  (0x005DC844)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13  (0x005DC848)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14  (0x005DC84C)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15  (0x005DC850)
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___S               8
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___M 0x00000F1F   
#define   PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0   (0x005DCC00)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___POR 0x70008884
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___POR 0x8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___POR 0x8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___POR 0x4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___S              28
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___M 0x00E00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___M 0x70FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1   (0x005DCC04)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET       (0x005DCC08)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___M 0x0007FBFB   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0     (0x005DCC0C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___S              27
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___M 0x07E00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___S              21
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1     (0x005DCC10)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___M 0x00380000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2     (0x005DCC14)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3     (0x005DCC18)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S              27
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4     (0x005DCC1C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S              31
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___M 0x00001FF8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___M 0xFDFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5     (0x005DCC20)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL (0x005DCC24)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x000007C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL (0x005DCC2C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0 (0x005DCC30)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1 (0x005DCC34)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2 (0x005DCC38)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3 (0x005DCC3C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4 (0x005DCC40)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5 (0x005DCC44)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6 (0x005DCC48)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7 (0x005DCC4C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8 (0x005DCC50)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9 (0x005DCC54)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10 (0x005DCC58)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11 (0x005DCC5C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12 (0x005DCC60)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13 (0x005DCC64)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14 (0x005DCC68)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15 (0x005DCC6C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0 (0x005DCC70)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1 (0x005DCC74)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2 (0x005DCC78)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3 (0x005DCC7C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4 (0x005DCC80)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5 (0x005DCC84)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6 (0x005DCC88)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7 (0x005DCC8C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8 (0x005DCC90)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9 (0x005DCC94)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10 (0x005DCC98)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11 (0x005DCC9C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12 (0x005DCCA0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13 (0x005DCCA4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14 (0x005DCCA8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15 (0x005DCCAC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0 (0x005DCCB0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1 (0x005DCCB4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2 (0x005DCCB8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3 (0x005DCCBC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4 (0x005DCCC0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5 (0x005DCCC4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6 (0x005DCCC8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7 (0x005DCCCC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8 (0x005DCCD0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9 (0x005DCCD4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10 (0x005DCCD8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11 (0x005DCCDC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12 (0x005DCCE0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13 (0x005DCCE4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14 (0x005DCCE8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15 (0x005DCCEC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0 (0x005DCCF0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1 (0x005DCCF4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2 (0x005DCCF8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3 (0x005DCCFC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4 (0x005DCD00)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5 (0x005DCD04)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6 (0x005DCD08)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7 (0x005DCD0C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8 (0x005DCD10)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9 (0x005DCD14)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10 (0x005DCD18)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11 (0x005DCD1C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12 (0x005DCD20)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13 (0x005DCD24)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14 (0x005DCD28)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15 (0x005DCD2C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0 (0x005DCD30)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1 (0x005DCD34)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2 (0x005DCD38)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3 (0x005DCD3C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4 (0x005DCD40)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5 (0x005DCD44)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6 (0x005DCD48)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7 (0x005DCD4C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8 (0x005DCD50)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9 (0x005DCD54)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10 (0x005DCD58)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11 (0x005DCD5C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12 (0x005DCD60)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13 (0x005DCD64)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14 (0x005DCD68)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15 (0x005DCD6C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0   (0x005DD000)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___POR 0x70008884
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___POR 0x8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___POR 0x8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___POR 0x4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___S              28
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___M 0x00E00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___M 0x70FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1   (0x005DD004)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET       (0x005DD008)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___M 0x0007FBFB   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0     (0x005DD00C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___S              27
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___M 0x07E00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___S              21
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1     (0x005DD010)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___M 0x00380000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2     (0x005DD014)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___S              16
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3     (0x005DD018)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S              27
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___S              19
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4     (0x005DD01C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S              31
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S              24
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___S              14
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___M 0x00001FF8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___M 0xFDFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5     (0x005DD020)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL (0x005DD024)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              17
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              11
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x000007C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL (0x005DD02C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0 (0x005DD030)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1 (0x005DD034)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2 (0x005DD038)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3 (0x005DD03C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4 (0x005DD040)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5 (0x005DD044)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6 (0x005DD048)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7 (0x005DD04C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8 (0x005DD050)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9 (0x005DD054)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10 (0x005DD058)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11 (0x005DD05C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12 (0x005DD060)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13 (0x005DD064)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14 (0x005DD068)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15 (0x005DD06C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___S               8
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___M 0x00003F3F   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0 (0x005DD070)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1 (0x005DD074)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2 (0x005DD078)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3 (0x005DD07C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4 (0x005DD080)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5 (0x005DD084)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6 (0x005DD088)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7 (0x005DD08C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8 (0x005DD090)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9 (0x005DD094)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10 (0x005DD098)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11 (0x005DD09C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12 (0x005DD0A0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13 (0x005DD0A4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14 (0x005DD0A8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15 (0x005DD0AC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___S              20
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___M 0x000F8000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___S              15
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0 (0x005DD0B0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1 (0x005DD0B4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2 (0x005DD0B8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3 (0x005DD0BC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4 (0x005DD0C0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5 (0x005DD0C4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6 (0x005DD0C8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7 (0x005DD0CC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8 (0x005DD0D0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9 (0x005DD0D4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10 (0x005DD0D8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11 (0x005DD0DC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12 (0x005DD0E0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13 (0x005DD0E4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14 (0x005DD0E8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15 (0x005DD0EC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S               9
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___S               6
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___S               4
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0 (0x005DD0F0)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1 (0x005DD0F4)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2 (0x005DD0F8)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3 (0x005DD0FC)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4 (0x005DD100)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5 (0x005DD104)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6 (0x005DD108)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7 (0x005DD10C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8 (0x005DD110)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9 (0x005DD114)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10 (0x005DD118)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11 (0x005DD11C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12 (0x005DD120)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13 (0x005DD124)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14 (0x005DD128)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15 (0x005DD12C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S              26
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___S              23
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___S              18
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S              13
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S              10
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___S               7
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S               3
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0 (0x005DD130)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1 (0x005DD134)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2 (0x005DD138)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3 (0x005DD13C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4 (0x005DD140)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5 (0x005DD144)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6 (0x005DD148)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7 (0x005DD14C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8 (0x005DD150)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9 (0x005DD154)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10 (0x005DD158)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11 (0x005DD15C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12 (0x005DD160)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13 (0x005DD164)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14 (0x005DD168)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___S               0

#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15 (0x005DD16C)
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S              22
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___S              12
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___M 0x00000FFC
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___S               2
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___S               0
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG (0x005DE800)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0 (0x005DE804)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1 (0x005DE808)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL (0x005DE80C)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___S               2
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___S               1
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___M 0x00000007   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING (0x005DE810)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S               8
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S               4
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___M 0x000001FF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET (0x005DE814)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S              24
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0 (0x005DE818)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S              24
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S              16
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1 (0x005DE81C)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S              24
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S              16
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0 (0x005DE820)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S              24
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S              16
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I (0x005DE824)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S              28
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S              18
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q (0x005DE828)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S              28
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S              18
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S              12
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG (0x005DE82C)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S              23
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S              22
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S              11
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I (0x005DE830)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q (0x005DE834)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM (0x005DE838)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___POR 0x000003FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S              29
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S              28
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S              24
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S              10
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S               0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___M 0x3F0FFFFF   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___S               0

#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL (0x005DE83C)
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___M 0x07800000   
#define   PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___S              23

#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG        (0x005DE980)
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG        (0x005DE984)
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0         (0x005DE988)
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___RWC   QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___S                0

#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1         (0x005DE98C)
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___M  0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___S                0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0         (0x005DE990)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___POR 0x00007000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___POR 0x7
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___S              12
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___M 0x00000180
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___S               7
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___S               6
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___M  0x0000F1FC   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___S                2

#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1         (0x005DE994)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___POR 0x00000010
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S              19
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S              18
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S              17
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___S               8
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S               6
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S               5
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___M  0x000FFF70   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___S                4

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1           (0x005DE998)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___S               5
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___M 0x00000010
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___M 0x0000000E
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___M    0x0000007F   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2           (0x005DE99C)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___M    0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3           (0x005DE9A0)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___POR  0x00000070
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___POR 0x7
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___S               8
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___M    0x000001FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4           (0x005DE9A4)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___RWC     QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___M    0x0000003F   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5           (0x005DE9A8)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___M    0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6           (0x005DE9AC)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___M    0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7           (0x005DE9B0)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___M    0x0000007F   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8           (0x005DE9B4)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___M    0x0000003F   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9           (0x005DE9B8)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___POR  0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___M    0x00000003   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___S                  0

#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10          (0x005DE9BC)
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___RWC    QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___M   0x00000003   
#define   PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___S                 0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00 (0x005DE9C0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01 (0x005DE9C4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02 (0x005DE9C8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03 (0x005DE9CC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04 (0x005DE9D0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05 (0x005DE9D4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06 (0x005DE9D8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07 (0x005DE9DC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08 (0x005DE9E0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09 (0x005DE9E4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10 (0x005DE9E8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11 (0x005DE9EC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12 (0x005DE9F0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13 (0x005DE9F4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14 (0x005DE9F8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15 (0x005DE9FC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16 (0x005DEA00)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17 (0x005DEA04)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18 (0x005DEA08)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19 (0x005DEA0C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20 (0x005DEA10)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21 (0x005DEA14)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22 (0x005DEA18)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23 (0x005DEA1C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24 (0x005DEA20)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25 (0x005DEA24)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26 (0x005DEA28)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27 (0x005DEA2C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28 (0x005DEA30)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29 (0x005DEA34)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30 (0x005DEA38)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31 (0x005DEA3C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00 (0x005DEA40)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01 (0x005DEA44)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02 (0x005DEA48)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03 (0x005DEA4C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04 (0x005DEA50)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05 (0x005DEA54)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06 (0x005DEA58)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07 (0x005DEA5C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08 (0x005DEA60)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09 (0x005DEA64)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10 (0x005DEA68)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11 (0x005DEA6C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12 (0x005DEA70)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13 (0x005DEA74)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14 (0x005DEA78)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15 (0x005DEA7C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16 (0x005DEA80)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17 (0x005DEA84)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18 (0x005DEA88)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19 (0x005DEA8C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20 (0x005DEA90)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21 (0x005DEA94)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22 (0x005DEA98)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23 (0x005DEA9C)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24 (0x005DEAA0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25 (0x005DEAA4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26 (0x005DEAA8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27 (0x005DEAAC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28 (0x005DEAB0)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29 (0x005DEAB4)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30 (0x005DEAB8)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___S               0

#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31 (0x005DEABC)
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___POR 0x00000020
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0 (0x005DEAC0)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1 (0x005DEAC4)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2 (0x005DEAC8)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3 (0x005DEACC)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4 (0x005DEAD0)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5 (0x005DEAD4)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6 (0x005DEAD8)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7 (0x005DEADC)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8 (0x005DEAE0)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0 (0x005DEAE4)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1 (0x005DEAE8)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2 (0x005DEAEC)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3 (0x005DEAF0)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4 (0x005DEAF4)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5 (0x005DEAF8)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6 (0x005DEAFC)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7 (0x005DEB00)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8 (0x005DEB04)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1   (0x005DEB08)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___S              30
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___S              29
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S              26
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S              15
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S              14
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___S              13
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___S              12
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___S              11
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___S               9
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S               7
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___S               5
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___S               3
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2   (0x005DEB0C)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S              31
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S              11
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___S              10
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3   (0x005DEB10)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___POR 0x000001FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___S               9
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4   (0x005DEB14)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1 (0x005DEB18)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S               3
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2 (0x005DEB1C)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S              24
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___S               8
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3 (0x005DEB20)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S              31
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S              10
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___S               4
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4 (0x005DEB24)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S               8
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL   (0x005DEB28)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___POR 0x00000004
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S               2
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___M 0x00000007   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG  (0x005DEB2C)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___S              12
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S              11
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___S               9
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___S               8
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___S               0

#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG (0x005DEB30)
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S               0
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0   (0x005DEC00)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___M 0x00003F00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___S               8

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1   (0x005DEC04)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___POR 0x7C007000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___S              31
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___S              30
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___S              29
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___S              27
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___S              26
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___M 0xFC00F003   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT (0x005DEC08)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___POR 0x1C081009
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___POR 0x1C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___POR 0x09
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0 (0x005DEC0C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___POR 0x1A1A1A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1 (0x005DEC10)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___POR 0x14141A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2 (0x005DEC14)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___POR 0x12121A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3 (0x005DEC18)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___POR 0x0A0A1410
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4 (0x005DEC1C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___POR 0x0C100E1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5 (0x005DEC20)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___POR 0x0E0E0E0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6 (0x005DEC24)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___POR 0x120E0E14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7 (0x005DEC28)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___POR 0x0E0E0C10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT (0x005DEC2C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___POR 0x17191016
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___POR 0x17
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___POR 0x19
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___POR 0x16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0 (0x005DEC30)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___POR 0x08080808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1 (0x005DEC34)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___POR 0x0E0E0808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2 (0x005DEC38)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___POR 0x05110808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___POR 0x11
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3 (0x005DEC3C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___POR 0x0A0A1410
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4 (0x005DEC40)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___POR 0x18081608
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___POR 0x18
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___POR 0x16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5 (0x005DEC44)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___POR 0x14141413
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___POR 0x13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6 (0x005DEC48)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___POR 0x0A141404
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___POR 0x04
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7 (0x005DEC4C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___POR 0x07070F10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___POR 0x0F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT (0x005DEC50)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___POR 0x1011080E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___POR 0x11
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0 (0x005DEC54)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1 (0x005DEC58)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___POR 0x03030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2 (0x005DEC5C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___POR 0x05050000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3 (0x005DEC60)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___POR 0x0C0C0208
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___POR 0x02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4 (0x005DEC64)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___POR 0x0A070800
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5 (0x005DEC68)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___POR 0x0C0C0C0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6 (0x005DEC6C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___POR 0x050C0C02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___POR 0x02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7 (0x005DEC70)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___POR 0x03030808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL       (0x005DEC74)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___POR 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___M 0x00000F0F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT (0x005DEC78)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___POR 0x999BBDCE
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___POR 0xD
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___POR 0xC
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___POR 0xE
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___S              20
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT (0x005DEC7C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___POR 0x0F0D0C0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___S              31
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___S              26
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___S              23
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___S              20
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___S              18
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___S              15
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX     (0x005DEC80)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___S               5
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___S               3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___S               1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___M 0x0000007F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0    (0x005DEC84)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___M 0x000000F3   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1    (0x005DEC88)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___M 0x0000FF00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___S               8

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV         (0x005DEC8C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___S              21
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___S              13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___M  0x003F3F00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV        (0x005DEC90)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___S              17
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___M 0x0000E000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___S              13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___S               5
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___M 0x0007FF3F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV         (0x005DEC94)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___M  0x0003FF00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0       (0x005DEC98)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1       (0x005DEC9C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE     (0x005DECA0)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0   (0x005DEE00)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___M 0x00003F00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___S               8

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1   (0x005DEE04)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___POR 0x7C007000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___S              31
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___S              30
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___S              29
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___S              27
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___S              26
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___M 0xFC00F003   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT (0x005DEE08)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___POR 0x1C081009
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___POR 0x1C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___POR 0x09
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0 (0x005DEE0C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___POR 0x1A1A1A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1 (0x005DEE10)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___POR 0x14141A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2 (0x005DEE14)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___POR 0x12121A1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3 (0x005DEE18)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___POR 0x0A0A1410
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4 (0x005DEE1C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___POR 0x0C100E1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___POR 0x1A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5 (0x005DEE20)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___POR 0x0E0E0E0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6 (0x005DEE24)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___POR 0x120E0E14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___POR 0x12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7 (0x005DEE28)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___POR 0x0E0E0C10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT (0x005DEE2C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___POR 0x17191016
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___POR 0x17
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___POR 0x19
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___POR 0x16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0 (0x005DEE30)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___POR 0x08080808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1 (0x005DEE34)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___POR 0x0E0E0808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2 (0x005DEE38)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___POR 0x05110808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___POR 0x11
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3 (0x005DEE3C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___POR 0x0A0A1410
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4 (0x005DEE40)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___POR 0x18081608
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___POR 0x18
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___POR 0x16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5 (0x005DEE44)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___POR 0x14141413
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___POR 0x13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6 (0x005DEE48)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___POR 0x0A141404
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___POR 0x14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___POR 0x04
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7 (0x005DEE4C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___POR 0x07070F10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___POR 0x0F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT (0x005DEE50)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___POR 0x1011080E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___POR 0x10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___POR 0x11
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___POR 0x0E
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0 (0x005DEE54)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1 (0x005DEE58)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___POR 0x03030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2 (0x005DEE5C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___POR 0x05050000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3 (0x005DEE60)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___POR 0x0C0C0208
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___POR 0x02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4 (0x005DEE64)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___POR 0x0A070800
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___POR 0x0A
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___POR 0x07
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5 (0x005DEE68)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___POR 0x0C0C0C0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6 (0x005DEE6C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___POR 0x050C0C02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___POR 0x05
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___POR 0x0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___POR 0x02
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7 (0x005DEE70)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___POR 0x03030808
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___POR 0x03
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___POR 0x08
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___M 0x1F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___M 0x1F1F1F1F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL       (0x005DEE74)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___POR 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___M 0x00000F0F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT (0x005DEE78)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___POR 0x999BBDCE
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___POR 0x9
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___POR 0xD
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___POR 0xC
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___POR 0xE
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___S              20
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT (0x005DEE7C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___POR 0x0F0D0C0C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___S              31
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___S              28
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___S              26
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___S              23
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___S              20
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___S              18
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___S              15
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX     (0x005DEE80)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___S               5
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___S               3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___S               1
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___M 0x0000007F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0    (0x005DEE84)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___M 0x000000F3   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1    (0x005DEE88)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___M 0x0000FF00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___S               8

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV         (0x005DEE8C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___S              21
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___M 0x001F0000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___S              13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___M  0x003F3F00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV        (0x005DEE90)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___S              17
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___M 0x0000E000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___S              13
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___S               5
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___S               2
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___M 0x0007FF3F   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV         (0x005DEE94)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___M  0x0003FF00   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0       (0x005DEE98)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1       (0x005DEE9C)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___S               0

#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE     (0x005DEEA0)
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0   (0x005DF000)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___POR 0x04280E87
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___S              31
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___S              28
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___S              27
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___S              26
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___M 0x00200000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___M 0xBC7FFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1   (0x005DF004)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___POR 0x00C30006
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___POR 0x6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___M 0x03F70777   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0     (0x005DF008)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1     (0x005DF00C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___M 0x0001FC00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___S               1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___M 0x0001FC03   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0    (0x005DF010)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___M 0xC07CFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0      (0x005DF014)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___M 0x1E000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___S              25
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___M 0x00600000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___M 0xFFE07F7F   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1      (0x005DF018)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___S              27
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___M 0x0F000000   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___S              24

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3      (0x005DF01C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___M 0x000F80F0   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___S               4

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV         (0x005DF020)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S              26
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___M  0x07F07F00   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0       (0x005DF024)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1       (0x005DF028)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE     (0x005DF02C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0 (0x005DF030)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___POR 0x00004444
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1 (0x005DF034)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___POR 0x80808080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___S              31
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___M 0x7F000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___M 0x00007F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV      (0x005DF038)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2     (0x005DF03C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___M 0x00000007   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG (0x005DF040)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___POR 0x000E0308
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___POR 0x8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___M 0x000F0F0F   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL (0x005DF044)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL (0x005DF048)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___M 0x00000077   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0 (0x005DF04C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___POR 0x40666401
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1 (0x005DF050)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___POR 0x40A26401
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2 (0x005DF054)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___POR 0x41628501
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3 (0x005DF058)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___POR 0x0002A380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4 (0x005DF05C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___POR 0x001E4380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5 (0x005DF060)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___POR 0x001E0380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6 (0x005DF064)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___POR 0x00020380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7 (0x005DF068)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___POR 0x00026380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0 (0x005DF06C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___POR 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1 (0x005DF070)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___POR 0x00000082
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2 (0x005DF074)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___POR 0x00000103
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3 (0x005DF078)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___POR 0x000000D3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4 (0x005DF07C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___POR 0x00000153
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5 (0x005DF080)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___POR 0x0000022B
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6 (0x005DF084)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___POR 0x0000027C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7 (0x005DF088)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___POR 0x00000354
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0   (0x005DF200)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___POR 0x04280E87
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___S              31
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___S              28
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___S              27
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___S              26
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___M 0x00200000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___M 0x00000600
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___M 0xBC7FFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1   (0x005DF204)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___POR 0x00C30006
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___POR 0x6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___M 0x00070000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___M 0x03F70777   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0     (0x005DF208)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1     (0x005DF20C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___M 0x0001FC00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___S               1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___M 0x0001FC03   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0    (0x005DF210)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___M 0xC07CFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0      (0x005DF214)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___M 0x1E000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___S              25
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___M 0x01800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___M 0x00600000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___M 0x00003F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___M 0xFFE07F7F   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1      (0x005DF218)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___S              27
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___M 0x0F000000   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___S              24

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3      (0x005DF21C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___M 0x000F80F0   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___S               4

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV         (0x005DF220)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S              26
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S              22
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___M  0x07F07F00   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___S                8

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0       (0x005DF224)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1       (0x005DF228)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE     (0x005DF22C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0 (0x005DF230)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___POR 0x00004444
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___S              14
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___S               6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___S               2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1 (0x005DF234)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___POR 0x80808080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___S              31
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___M 0x7F000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___S              24
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___S              23
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___M 0x00007F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV      (0x005DF238)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___S              15
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___S              12
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2     (0x005DF23C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___M 0x00000007   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG (0x005DF240)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___POR 0x000E0308
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___POR 0x8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___S              19
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___S              16
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___M 0x000F0F0F   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL (0x005DF244)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___M 0x000000FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL (0x005DF248)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___M 0x00000070
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___S               4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___M 0x00000077   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0 (0x005DF24C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___POR 0x40666401
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1 (0x005DF250)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___POR 0x40A26401
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2 (0x005DF254)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___POR 0x41628501
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3 (0x005DF258)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___POR 0x0002A380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4 (0x005DF25C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___POR 0x001E4380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5 (0x005DF260)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___POR 0x001E0380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6 (0x005DF264)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___POR 0x00020380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7 (0x005DF268)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___POR 0x00026380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___S              21
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___S              18
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___S              17
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___S              13
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___S              11
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___S              10
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S               9
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               8
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0 (0x005DF26C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___POR 0x00000001
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1 (0x005DF270)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___POR 0x00000082
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2 (0x005DF274)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___POR 0x00000103
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3 (0x005DF278)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___POR 0x000000D3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4 (0x005DF27C)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___POR 0x00000153
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5 (0x005DF280)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___POR 0x0000022B
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6 (0x005DF284)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___POR 0x0000027C
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___S               0

#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7 (0x005DF288)
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___POR 0x00000354
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___S               7
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S               5
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S               3
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S               0
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___M 0x000003FF   
#define   PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0  (0x005DFC00)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___POR 0x32D55555
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___POR 0x065
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___POR 0x555555
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1  (0x005DFC04)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___POR 0x00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___M 0x000003F0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2  (0x005DFC08)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___POR 0x0042AAAA
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___POR 0x42AAAA
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___M 0x02000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3  (0x005DFC0C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___POR 0x00005100
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___POR 0x000051
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___S               8

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0  (0x005DFC10)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___POR 0x00282680
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___M 0x00E00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___S              21
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___M 0x001C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___M 0x00000008
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___S               3
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___M 0x00000004
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___S               2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___S               1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1  (0x005DFC14)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___POR 0x04000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___POR 0x400
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___M 0x07FF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2  (0x005DFC18)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___POR 0x6002A000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___POR 0x3
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___S              29
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___M 0x00000F00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___M 0x000000F0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___M 0xF003FFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0 (0x005DFC1C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1 (0x005DFC20)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___S              11
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___M 0xFFFF7800   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___S              11

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2 (0x005DFC24)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___S              29
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___M 0x01000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00001000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00000800
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___S              11
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00000400
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___S               9
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___M 0x00000100
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___M 0x00000080
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___S               7
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___M 0x0000007F
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___M 0xFF801FFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3 (0x005DFC28)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___POR 0x000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___POR 0x000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___M 0xFF800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___M 0x007FFFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4 (0x005DFC2C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___POR 0x000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___M 0x000007FF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___M 0x000007FF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0 (0x005DFC40)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___POR 0x07D2F998
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___POR 0x7
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___POR 0xD
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___POR 0x3
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___M 0x70000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___M 0x000F0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___M 0x00002000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___M 0x00001C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___S               3
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___S               3

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0 (0x005DFC44)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___POR 0x000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___POR 0x000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___M 0x07FF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___M 0x000007FF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___M 0xC7FF07FF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1 (0x005DFC48)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2 (0x005DFC4C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___POR 0x7FFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3 (0x005DFC50)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4 (0x005DFC54)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5 (0x005DFC58)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6 (0x005DFC5C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0  (0x005DFC80)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___POR 0x00040000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___M 0x000E0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___M 0x0001C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___S               2

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1  (0x005DFC84)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___M 0xCFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2  (0x005DFC88)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___S              29
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___M 0x1FC00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___M 0xFFFFF00F   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3  (0x005DFC8C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___S              29
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___M 0x1FFC0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___M 0xFFFC3FFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4  (0x005DFC90)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___S               8
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___M 0xFFFFFFF0   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___S               4

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5  (0x005DFC94)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___M 0xFF000000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___S              24

#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6  (0x005DFC98)
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___POR 0x58000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___POR 0xB
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___M 0xF8000000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___S              27

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0  (0x005DFCC0)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___POR 0x00494800
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___M 0x00400000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___M 0x003C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___M 0x0000C000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___M 0x00003C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___M 0x00000200
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___S               9
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___S               9

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1  (0x005DFCC4)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___POR 0x0F623200
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___POR 0x7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___POR 0x4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___POR 0x4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___M 0x80000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___S              31
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___M 0x40000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___M 0x38000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___M 0x07000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___M 0x00007800
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___S              11
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___M 0x00000780
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___S               7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___M 0x00000060
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___S               5
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___S               5

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2  (0x005DFCC8)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___POR 0x62007000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___POR 0x7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___M 0xC0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___S              30
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___M 0x30000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___M 0x04000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___S              26
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___M 0x02000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___M 0x01C00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___S              22
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___M 0x00380000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___M 0x0000F000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___M 0x0000003E
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___S               1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___M 0xF7FFF03F   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3  (0x005DFCCC)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___POR 0x00000001
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___POR 0x00000001
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC (0x005DFCD0)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___POR 0x00000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___M 0x00000003
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___M 0x00000003   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___S               0

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4  (0x005DFCD4)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___POR 0x01093814
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___POR 0x3
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___POR 0x10
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___POR 0xA
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___M 0x03000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___M 0x00080000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___M 0x00040000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___M 0x00030000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___M 0x00007000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___S              12
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___M 0x00000F80
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___S               7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___S               5
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___M 0x0000001E
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___S               1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___M 0x030FFFFE   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___S               1

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5  (0x005DFCD8)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___POR 0x26100A18
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___POR 0xC
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___POR 0x4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___POR 0x3
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___M 0xE0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___S              29
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___M 0x10000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___M 0x08000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___S              27
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___M 0x07800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___M 0x00700000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___S              18
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___M 0x00003800
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___S              11
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___M 0x00000780
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___S               7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___M 0x00000040
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___M 0x00000038
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___S               3
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___M 0xFFFC7FF8   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___S               3

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6  (0x005DFCDC)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___POR 0xA6040000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___POR 0xA
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___M 0x00F00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___S              20
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___M 0x000E0000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___M 0x00010000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___S              16
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___M 0x00008000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___M 0x00004000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___S              14
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___M 0x00003C00
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___S              10
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___M 0x000003C0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___S               6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___M 0x00000030
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___S               4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___M 0xFFFFFFF0   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___S               4

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7  (0x005DFCE0)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___POR 0xB0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___POR 0xB
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___M 0xF0000000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___S              28

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0 (0x005DFD00)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___POR 0x90CAA000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___POR 0x48
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___M 0xFE000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___S              21
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___M 0x00180000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___M 0xFFFFE000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___S              13

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1 (0x005DFD04)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___POR 0x90CAA000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___POR 0x48
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___M 0xFE000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___S              21
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___M 0x00180000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___M 0xFFFFE000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___S              13

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2 (0x005DFD08)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___POR 0x90CAA000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___POR 0x48
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___M 0xFE000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___S              21
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___M 0x00180000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___M 0xFFFFE000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___S              13

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3 (0x005DFD0C)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___POR 0x90CAA000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___POR 0x48
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___POR 0x1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___M 0xFE000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___S              25
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___M 0x01E00000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___S              21
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___M 0x00180000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___M 0x00060000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___S              17
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___M 0x00018000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___M 0x00006000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___S              13
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___M 0xFFFFE000   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___S              13

#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0 (0x005DFD14)
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___POR 0x00132320
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___POR 0x2
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___POR 0x4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___POR 0x6
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___POR 0x4
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___M 0xF0000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___S              28
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___M 0x0F000000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___S              24
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___M 0x00800000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___S              23
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___M 0x00780000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___S              19
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___M 0x00078000
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___S              15
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___M 0x00007800
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___S              11
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___M 0x00000780
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___S               7
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___M 0x00000078
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___S               3
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___M 0x00000002
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___S               1
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___S               0
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___M 0xFFFFFFFB   
#define   PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG   (0x005E0000)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0        (0x005E0004)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1        (0x005E0008)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___S               6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0   (0x005E000C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1   (0x005E0010)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2   (0x005E0014)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___POR 0x0000C001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S              14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S              13
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S              11
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S              10
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___M 0xC000FF01   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0      (0x005E0018)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___M 0xFECC0000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0      (0x005E001C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___M 0xFEDC0000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET     (0x005E0020)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0 (0x005E0024)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___POR 0x06769292
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0 (0x005E0028)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___POR 0x00004142
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0   (0x005E002C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___S              29
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___S              29

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0       (0x005E0030)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0   (0x005E0034)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1   (0x005E0038)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG (0x005E003C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2        (0x005E0040)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0    (0x005E0044)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___POR 0x09200000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___M 0x0FF80007   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST    (0x005E0048)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0 (0x005E0080)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___POR 0x005078A0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1 (0x005E0084)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___POR 0xC8F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___M 0xFFFF03FF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL (0x005E0088)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___M 0x0000C000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___S              14

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0 (0x005E008C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1 (0x005E0090)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___M 0x0000FFBF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0 (0x005E0094)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0 (0x005E0098)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1 (0x005E009C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0 (0x005E00A0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___M 0x000C3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0        (0x005E00A4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___S              30

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC   (0x005E00A8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC   (0x005E00AC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___M 0x007F3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN   (0x005E00B0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___M 0x00FFFFBF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0 (0x005E00B4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1 (0x005E00B8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___M 0x7FFF3F00   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___S               8

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0        (0x005E00C0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1        (0x005E00C4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2        (0x005E00C8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3        (0x005E00CC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4        (0x005E00D0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5        (0x005E00D4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6        (0x005E00D8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7        (0x005E00DC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8        (0x005E00E0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9        (0x005E00E4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10       (0x005E00E8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11       (0x005E00EC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12       (0x005E00F0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13       (0x005E00F4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14       (0x005E00F8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15       (0x005E00FC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16       (0x005E0100)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17       (0x005E0104)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18       (0x005E0108)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19       (0x005E010C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20       (0x005E0110)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21       (0x005E0114)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22       (0x005E0118)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23       (0x005E011C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24       (0x005E0120)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25       (0x005E0124)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26       (0x005E0128)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27       (0x005E012C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28       (0x005E0130)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29       (0x005E0134)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30       (0x005E0138)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31       (0x005E013C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32       (0x005E0140)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33       (0x005E0144)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34       (0x005E0148)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35       (0x005E014C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36       (0x005E0150)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37       (0x005E0154)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38       (0x005E0158)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39       (0x005E015C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40       (0x005E0160)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41       (0x005E0164)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42       (0x005E0168)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43       (0x005E016C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44       (0x005E0170)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45       (0x005E0174)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46       (0x005E0178)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47       (0x005E017C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48       (0x005E0180)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49       (0x005E0184)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50       (0x005E0188)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51       (0x005E018C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52       (0x005E0190)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53       (0x005E0194)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54       (0x005E0198)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55       (0x005E019C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56       (0x005E01A0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57       (0x005E01A4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58       (0x005E01A8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59       (0x005E01AC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60       (0x005E01B0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61       (0x005E01B4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62       (0x005E01B8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63       (0x005E01BC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___S              26

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG    (0x005E1000)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___POR 0x44FE2111
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___POR 0x44FE2111
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL (0x005E1004)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___S              22

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0 (0x005E1008)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1 (0x005E100C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0 (0x005E1010)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___POR 0x60A25480
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1 (0x005E1014)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___POR 0x60E24480
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2 (0x005E1018)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___POR 0x601E030A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3 (0x005E101C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___POR 0x60022304
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4 (0x005E1020)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___POR 0x60022309
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5 (0x005E1024)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___POR 0x60022312
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6 (0x005E1028)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___POR 0x4002231C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7 (0x005E102C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___POR 0x00026339
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0 (0x005E1030)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1 (0x005E1034)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2 (0x005E1038)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___POR 0x14520000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3 (0x005E103C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___POR 0x1E7A0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4 (0x005E1040)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___POR 0x28930000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5 (0x005E1044)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___POR 0x3CC20000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___POR 0x1E
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6 (0x005E1048)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7 (0x005E104C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0    (0x005E1080)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___M 0x00000780
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___M 0xF07FFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT (0x005E1084)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___S              21

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1    (0x005E1088)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2    (0x005E108C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___S              28

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0 (0x005E1090)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___S               8

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1 (0x005E1094)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___M 0xFFF00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___S              20

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL (0x005E1098)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___S              25

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0 (0x005E109C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1 (0x005E10A0)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2 (0x005E10A4)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0  (0x005E10A8)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___POR 0xA201E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___M 0xE7FFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL (0x005E10AC)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0 (0x005E10B0)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___POR 0x7011C800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___M 0xF87FF800   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___S              11

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1 (0x005E10B4)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___POR 0x52000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___S              21

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2 (0x005E10B8)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___POR 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___S               3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___M 0xFFFFFFB8   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___S               3

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE (0x005E10BC)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___M 0x000000FE
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___S               1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___M 0x0003FFFE   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG    (0x005E1300)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___POR 0x33FE2111
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___POR 0x33FE2111
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL (0x005E1304)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___S              15

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0 (0x005E1308)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___POR 0x14500000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1 (0x005E130C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___POR 0x14500000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0 (0x005E1310)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1 (0x005E1314)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2 (0x005E1318)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3 (0x005E131C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4 (0x005E1320)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5 (0x005E1324)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6 (0x005E1328)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___POR 0x04811000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x009
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7 (0x005E132C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___POR 0x05811000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x00B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8 (0x005E1330)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___POR 0x06011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x00C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9 (0x005E1334)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___POR 0x09011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x012
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10 (0x005E1338)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___POR 0x0A011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x014
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11 (0x005E133C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___POR 0x0B019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x016
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12 (0x005E1340)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___POR 0x0C019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x018
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13 (0x005E1344)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___POR 0x0D019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x01A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14 (0x005E1348)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___POR 0x13019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x026
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15 (0x005E134C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___POR 0x14021000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x028
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16 (0x005E1350)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___POR 0x15031000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x02A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17 (0x005E1354)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___POR 0x19051000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x032
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18 (0x005E1358)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___POR 0x1B061000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x036
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19 (0x005E135C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___POR 0x1D861000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x03B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20 (0x005E1360)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___POR 0x25071000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x04A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21 (0x005E1364)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___POR 0x2A079000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x054
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22 (0x005E1368)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___POR 0x2D091000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x05A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23 (0x005E136C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___POR 0x358C1000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x06B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24 (0x005E1370)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___POR 0x3C0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x078
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25 (0x005E1374)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___POR 0x44951000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x089
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x2A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26 (0x005E1378)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___POR 0x50199000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x0A0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x33
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27 (0x005E137C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___POR 0x569F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x0AD
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28 (0x005E1380)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___POR 0x641F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0C8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29 (0x005E1384)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___POR 0x6E1F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0DC
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30 (0x005E1388)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___POR 0x7D9F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0FB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31 (0x005E138C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___POR 0xFE9F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x1FD
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0 (0x005E1390)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1 (0x005E1394)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2 (0x005E1398)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3 (0x005E139C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4 (0x005E13A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5 (0x005E13A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6 (0x005E13A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7 (0x005E13AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0 (0x005E13B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1 (0x005E13B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2 (0x005E13B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3 (0x005E13BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4 (0x005E13C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5 (0x005E13C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6 (0x005E13C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7 (0x005E13CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8 (0x005E13D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9 (0x005E13D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10 (0x005E13D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11 (0x005E13DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12 (0x005E13E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13 (0x005E13E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14 (0x005E13E8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15 (0x005E13EC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0 (0x005E13F0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1 (0x005E13F4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2 (0x005E13F8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3 (0x005E13FC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4 (0x005E1400)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5 (0x005E1404)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6 (0x005E1408)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7 (0x005E140C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8 (0x005E1410)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9 (0x005E1414)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10 (0x005E1418)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11 (0x005E141C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12 (0x005E1420)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13 (0x005E1424)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14 (0x005E1428)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15 (0x005E142C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0 (0x005E1430)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1 (0x005E1434)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2 (0x005E1438)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3 (0x005E143C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4 (0x005E1440)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5 (0x005E1444)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6 (0x005E1448)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7 (0x005E144C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8 (0x005E1450)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9 (0x005E1454)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10 (0x005E1458)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11 (0x005E145C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12 (0x005E1460)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13 (0x005E1464)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14 (0x005E1468)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15 (0x005E146C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0    (0x005E1470)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1    (0x005E1474)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4    (0x005E1478)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___M 0x000001E0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___M 0x3FFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5    (0x005E147C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___M 0x000FFC00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___S               2

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6    (0x005E1480)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0 (0x005E1484)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___POR 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___M 0x000FC000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___S              14

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1 (0x005E1488)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___M 0xFFF7FC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2 (0x005E148C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___M 0xFFF3FFF0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___S               4

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0 (0x005E1490)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1 (0x005E1494)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3 (0x005E1498)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___M 0x000007FE   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4 (0x005E149C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5 (0x005E14A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0 (0x005E14A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___M 0x7F000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0 (0x005E14C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___POR 0x26920D00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0 (0x005E14C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___POR 0xBC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0 (0x005E14C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1 (0x005E14CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL (0x005E14D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___S              26

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE (0x005E14D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0 (0x005E14D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___S              31

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0 (0x005E14DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___POR 0xAA000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY (0x005E14E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD (0x005E14E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___POR 0x08B80000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR (0x005E1500)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___POR 0x6C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___M 0xFDF00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___S              20

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0  (0x005E2000)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT (0x005E2004)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0 (0x005E2040)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___POR 0x000A0026
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___S               1

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1 (0x005E2044)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___POR 0x00004020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___M 0x0007FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA (0x005E2048)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0   (0x005E2080)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___POR 0x0200E8B6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___M 0x03C2FCFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1   (0x005E2084)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___POR 0x00F80204
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___M 0x00FF03FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2   (0x005E2088)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___POR 0xECA86420
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3   (0x005E208C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___M 0x000000F1   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0 (0x005E2090)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0 (0x005E2094)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___M 0xC03FFC30   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1 (0x005E2098)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___M 0x0CFFF000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___S              12

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2 (0x005E209C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___POR 0x000C1010
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___M 0x001FFF3F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3 (0x005E20A0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___POR 0x0000B880
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___M 0x1FFCFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4 (0x005E20A4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___POR 0x01010840
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___M 0x1B07FFF0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0    (0x005E20A8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___POR 0x1D186008
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___M 0x9FFFFE0F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1    (0x005E20AC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___POR 0x00000840
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___M 0x00000DFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0 (0x005E20B0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___POR 0x036E36DC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1 (0x005E20B4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2 (0x005E20B8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2    (0x005E20BC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___POR 0x68000104
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___S               1

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3    (0x005E20C0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___M 0xFFFE7FE0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___S               5

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4    (0x005E20C4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___POR 0x00000492
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5    (0x005E20C8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___S              28

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST   (0x005E20CC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___S              31

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV (0x005E20D0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___M 0x000003F0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0   (0x005E2100)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___POR 0x1B000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___M 0xFF8001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0 (0x005E2104)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___M 0xFF80001F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0 (0x005E2140)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___S              29

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0 (0x005E2144)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0    (0x005E2148)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___S              27

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0 (0x005E214C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___S              22

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1    (0x005E2180)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___POR 0x073D11C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___POR 0xC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2    (0x005E2184)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___POR 0x00900090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0 (0x005E2188)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4    (0x005E218C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___POR 0x22685349
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5    (0x005E2190)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___POR 0x004D4D4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6    (0x005E2194)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___POR 0x079E79E7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7    (0x005E2198)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___POR 0x27C27C27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0 (0x005E219C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___POR 0x00008399
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9    (0x005E21A0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0 (0x005E21A4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___POR 0x01010000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0 (0x005E21A8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0 (0x005E21AC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13   (0x005E21B0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14 (0x005E21B4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0    (0x005E4000)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1    (0x005E4004)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2    (0x005E4008)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3    (0x005E400C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4    (0x005E4010)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5    (0x005E4014)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6    (0x005E4018)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7    (0x005E401C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8    (0x005E4020)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9    (0x005E4024)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10   (0x005E4028)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11   (0x005E402C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12   (0x005E4030)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13   (0x005E4034)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14   (0x005E4038)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15   (0x005E403C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16   (0x005E4040)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17   (0x005E4044)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18   (0x005E4048)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19   (0x005E404C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20   (0x005E4050)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21   (0x005E4054)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22   (0x005E4058)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23   (0x005E405C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24   (0x005E4060)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25   (0x005E4064)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26   (0x005E4068)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27   (0x005E406C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28   (0x005E4070)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29   (0x005E4074)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30   (0x005E4078)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31   (0x005E407C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32   (0x005E4080)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33   (0x005E4084)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34   (0x005E4088)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35   (0x005E408C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36   (0x005E4090)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37   (0x005E4094)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38   (0x005E4098)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39   (0x005E409C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40   (0x005E40A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41   (0x005E40A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42   (0x005E40A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43   (0x005E40AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44   (0x005E40B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45   (0x005E40B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46   (0x005E40B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47   (0x005E40BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48   (0x005E40C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49   (0x005E40C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50   (0x005E40C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51   (0x005E40CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52   (0x005E40D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53   (0x005E40D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54   (0x005E40D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55   (0x005E40DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56   (0x005E40E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57   (0x005E40E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58   (0x005E40E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59   (0x005E40EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60   (0x005E40F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61   (0x005E40F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62   (0x005E40F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63   (0x005E40FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64   (0x005E4100)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65   (0x005E4104)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66   (0x005E4108)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67   (0x005E410C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68   (0x005E4110)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69   (0x005E4114)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70   (0x005E4118)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71   (0x005E411C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72   (0x005E4120)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73   (0x005E4124)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74   (0x005E4128)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75   (0x005E412C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76   (0x005E4130)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77   (0x005E4134)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78   (0x005E4138)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79   (0x005E413C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80   (0x005E4140)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81   (0x005E4144)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82   (0x005E4148)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83   (0x005E414C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84   (0x005E4150)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85   (0x005E4154)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86   (0x005E4158)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87   (0x005E415C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88   (0x005E4160)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89   (0x005E4164)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90   (0x005E4168)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91   (0x005E416C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92   (0x005E4170)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93   (0x005E4174)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94   (0x005E4178)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95   (0x005E417C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96   (0x005E4180)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97   (0x005E4184)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98   (0x005E4188)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99   (0x005E418C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100  (0x005E4190)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101  (0x005E4194)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102  (0x005E4198)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103  (0x005E419C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104  (0x005E41A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105  (0x005E41A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106  (0x005E41A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107  (0x005E41AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108  (0x005E41B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109  (0x005E41B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110  (0x005E41B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111  (0x005E41BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112  (0x005E41C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113  (0x005E41C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114  (0x005E41C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115  (0x005E41CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116  (0x005E41D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117  (0x005E41D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118  (0x005E41D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119  (0x005E41DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120  (0x005E41E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121  (0x005E41E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122  (0x005E41E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123  (0x005E41EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124  (0x005E41F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125  (0x005E41F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126  (0x005E41F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127  (0x005E41FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128  (0x005E4200)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129  (0x005E4204)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130  (0x005E4208)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131  (0x005E420C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132  (0x005E4210)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133  (0x005E4214)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134  (0x005E4218)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135  (0x005E421C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136  (0x005E4220)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137  (0x005E4224)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138  (0x005E4228)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139  (0x005E422C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140  (0x005E4230)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141  (0x005E4234)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142  (0x005E4238)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143  (0x005E423C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144  (0x005E4240)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145  (0x005E4244)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146  (0x005E4248)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147  (0x005E424C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148  (0x005E4250)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149  (0x005E4254)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150  (0x005E4258)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151  (0x005E425C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152  (0x005E4260)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153  (0x005E4264)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154  (0x005E4268)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155  (0x005E426C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156  (0x005E4270)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157  (0x005E4274)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158  (0x005E4278)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159  (0x005E427C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160  (0x005E4280)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161  (0x005E4284)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162  (0x005E4288)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163  (0x005E428C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164  (0x005E4290)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165  (0x005E4294)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166  (0x005E4298)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167  (0x005E429C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168  (0x005E42A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169  (0x005E42A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170  (0x005E42A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171  (0x005E42AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172  (0x005E42B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173  (0x005E42B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174  (0x005E42B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175  (0x005E42BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176  (0x005E42C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177  (0x005E42C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178  (0x005E42C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179  (0x005E42CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180  (0x005E42D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181  (0x005E42D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182  (0x005E42D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183  (0x005E42DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184  (0x005E42E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185  (0x005E42E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186  (0x005E42E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187  (0x005E42EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188  (0x005E42F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189  (0x005E42F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190  (0x005E42F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191  (0x005E42FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192  (0x005E4300)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193  (0x005E4304)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194  (0x005E4308)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195  (0x005E430C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196  (0x005E4310)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197  (0x005E4314)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198  (0x005E4318)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199  (0x005E431C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200  (0x005E4320)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201  (0x005E4324)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202  (0x005E4328)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203  (0x005E432C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204  (0x005E4330)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205  (0x005E4334)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206  (0x005E4338)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207  (0x005E433C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208  (0x005E4340)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209  (0x005E4344)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210  (0x005E4348)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211  (0x005E434C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212  (0x005E4350)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213  (0x005E4354)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214  (0x005E4358)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215  (0x005E435C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216  (0x005E4360)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217  (0x005E4364)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218  (0x005E4368)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219  (0x005E436C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220  (0x005E4370)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221  (0x005E4374)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222  (0x005E4378)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223  (0x005E437C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224  (0x005E4380)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225  (0x005E4384)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226  (0x005E4388)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227  (0x005E438C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228  (0x005E4390)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229  (0x005E4394)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230  (0x005E4398)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231  (0x005E439C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232  (0x005E43A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233  (0x005E43A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234  (0x005E43A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235  (0x005E43AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236  (0x005E43B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237  (0x005E43B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238  (0x005E43B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239  (0x005E43BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240  (0x005E43C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241  (0x005E43C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242  (0x005E43C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243  (0x005E43CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244  (0x005E43D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245  (0x005E43D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246  (0x005E43D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247  (0x005E43DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248  (0x005E43E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249  (0x005E43E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250  (0x005E43E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251  (0x005E43EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252  (0x005E43F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253  (0x005E43F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254  (0x005E43F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255  (0x005E43FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256  (0x005E4400)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257  (0x005E4404)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258  (0x005E4408)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259  (0x005E440C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260  (0x005E4410)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261  (0x005E4414)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262  (0x005E4418)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263  (0x005E441C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264  (0x005E4420)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265  (0x005E4424)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266  (0x005E4428)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267  (0x005E442C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268  (0x005E4430)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269  (0x005E4434)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270  (0x005E4438)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271  (0x005E443C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272  (0x005E4440)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273  (0x005E4444)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274  (0x005E4448)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275  (0x005E444C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276  (0x005E4450)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277  (0x005E4454)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278  (0x005E4458)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279  (0x005E445C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280  (0x005E4460)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281  (0x005E4464)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282  (0x005E4468)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283  (0x005E446C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284  (0x005E4470)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285  (0x005E4474)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286  (0x005E4478)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287  (0x005E447C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288  (0x005E4480)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289  (0x005E4484)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290  (0x005E4488)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291  (0x005E448C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292  (0x005E4490)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293  (0x005E4494)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294  (0x005E4498)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295  (0x005E449C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296  (0x005E44A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297  (0x005E44A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298  (0x005E44A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299  (0x005E44AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300  (0x005E44B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301  (0x005E44B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302  (0x005E44B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303  (0x005E44BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304  (0x005E44C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305  (0x005E44C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306  (0x005E44C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307  (0x005E44CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308  (0x005E44D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309  (0x005E44D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310  (0x005E44D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311  (0x005E44DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312  (0x005E44E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313  (0x005E44E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314  (0x005E44E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315  (0x005E44EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316  (0x005E44F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317  (0x005E44F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318  (0x005E44F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319  (0x005E44FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320  (0x005E4500)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321  (0x005E4504)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322  (0x005E4508)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323  (0x005E450C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324  (0x005E4510)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325  (0x005E4514)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326  (0x005E4518)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327  (0x005E451C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328  (0x005E4520)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329  (0x005E4524)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330  (0x005E4528)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331  (0x005E452C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332  (0x005E4530)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333  (0x005E4534)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334  (0x005E4538)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335  (0x005E453C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336  (0x005E4540)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337  (0x005E4544)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338  (0x005E4548)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339  (0x005E454C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340  (0x005E4550)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341  (0x005E4554)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342  (0x005E4558)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343  (0x005E455C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344  (0x005E4560)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345  (0x005E4564)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346  (0x005E4568)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347  (0x005E456C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348  (0x005E4570)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349  (0x005E4574)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350  (0x005E4578)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351  (0x005E457C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352  (0x005E4580)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353  (0x005E4584)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354  (0x005E4588)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355  (0x005E458C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356  (0x005E4590)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357  (0x005E4594)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358  (0x005E4598)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359  (0x005E459C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360  (0x005E45A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361  (0x005E45A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362  (0x005E45A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363  (0x005E45AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364  (0x005E45B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365  (0x005E45B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366  (0x005E45B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367  (0x005E45BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368  (0x005E45C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369  (0x005E45C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370  (0x005E45C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371  (0x005E45CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372  (0x005E45D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373  (0x005E45D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374  (0x005E45D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375  (0x005E45DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376  (0x005E45E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377  (0x005E45E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378  (0x005E45E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379  (0x005E45EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380  (0x005E45F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381  (0x005E45F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382  (0x005E45F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383  (0x005E45FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384  (0x005E4600)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385  (0x005E4604)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386  (0x005E4608)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387  (0x005E460C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388  (0x005E4610)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389  (0x005E4614)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390  (0x005E4618)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391  (0x005E461C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392  (0x005E4620)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393  (0x005E4624)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394  (0x005E4628)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395  (0x005E462C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396  (0x005E4630)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397  (0x005E4634)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398  (0x005E4638)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399  (0x005E463C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400  (0x005E4640)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401  (0x005E4644)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402  (0x005E4648)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403  (0x005E464C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404  (0x005E4650)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405  (0x005E4654)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406  (0x005E4658)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407  (0x005E465C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408  (0x005E4660)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409  (0x005E4664)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410  (0x005E4668)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411  (0x005E466C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412  (0x005E4670)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413  (0x005E4674)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414  (0x005E4678)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415  (0x005E467C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416  (0x005E4680)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417  (0x005E4684)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418  (0x005E4688)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419  (0x005E468C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420  (0x005E4690)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421  (0x005E4694)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422  (0x005E4698)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423  (0x005E469C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424  (0x005E46A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425  (0x005E46A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426  (0x005E46A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427  (0x005E46AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428  (0x005E46B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429  (0x005E46B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430  (0x005E46B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431  (0x005E46BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432  (0x005E46C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433  (0x005E46C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434  (0x005E46C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435  (0x005E46CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436  (0x005E46D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437  (0x005E46D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438  (0x005E46D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439  (0x005E46DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440  (0x005E46E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441  (0x005E46E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442  (0x005E46E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443  (0x005E46EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444  (0x005E46F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445  (0x005E46F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446  (0x005E46F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447  (0x005E46FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448  (0x005E4700)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449  (0x005E4704)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450  (0x005E4708)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451  (0x005E470C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452  (0x005E4710)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453  (0x005E4714)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454  (0x005E4718)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455  (0x005E471C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456  (0x005E4720)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457  (0x005E4724)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458  (0x005E4728)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459  (0x005E472C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460  (0x005E4730)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461  (0x005E4734)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462  (0x005E4738)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463  (0x005E473C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464  (0x005E4740)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465  (0x005E4744)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466  (0x005E4748)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467  (0x005E474C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468  (0x005E4750)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469  (0x005E4754)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470  (0x005E4758)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471  (0x005E475C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472  (0x005E4760)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473  (0x005E4764)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474  (0x005E4768)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475  (0x005E476C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476  (0x005E4770)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477  (0x005E4774)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478  (0x005E4778)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479  (0x005E477C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480  (0x005E4780)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481  (0x005E4784)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482  (0x005E4788)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483  (0x005E478C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484  (0x005E4790)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485  (0x005E4794)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486  (0x005E4798)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487  (0x005E479C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488  (0x005E47A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489  (0x005E47A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490  (0x005E47A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491  (0x005E47AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492  (0x005E47B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493  (0x005E47B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494  (0x005E47B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495  (0x005E47BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496  (0x005E47C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497  (0x005E47C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498  (0x005E47C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499  (0x005E47CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500  (0x005E47D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501  (0x005E47D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502  (0x005E47D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503  (0x005E47DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504  (0x005E47E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505  (0x005E47E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506  (0x005E47E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507  (0x005E47EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508  (0x005E47F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509  (0x005E47F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510  (0x005E47F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511  (0x005E47FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512  (0x005E4800)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513  (0x005E4804)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514  (0x005E4808)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515  (0x005E480C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516  (0x005E4810)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517  (0x005E4814)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518  (0x005E4818)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519  (0x005E481C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520  (0x005E4820)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521  (0x005E4824)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522  (0x005E4828)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523  (0x005E482C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524  (0x005E4830)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525  (0x005E4834)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526  (0x005E4838)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527  (0x005E483C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528  (0x005E4840)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529  (0x005E4844)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530  (0x005E4848)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531  (0x005E484C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532  (0x005E4850)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533  (0x005E4854)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534  (0x005E4858)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535  (0x005E485C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536  (0x005E4860)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537  (0x005E4864)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538  (0x005E4868)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539  (0x005E486C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540  (0x005E4870)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541  (0x005E4874)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542  (0x005E4878)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543  (0x005E487C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544  (0x005E4880)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545  (0x005E4884)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546  (0x005E4888)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547  (0x005E488C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548  (0x005E4890)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549  (0x005E4894)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550  (0x005E4898)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551  (0x005E489C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552  (0x005E48A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553  (0x005E48A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554  (0x005E48A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555  (0x005E48AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556  (0x005E48B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557  (0x005E48B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558  (0x005E48B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559  (0x005E48BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560  (0x005E48C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561  (0x005E48C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562  (0x005E48C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563  (0x005E48CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564  (0x005E48D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565  (0x005E48D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566  (0x005E48D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567  (0x005E48DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568  (0x005E48E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569  (0x005E48E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570  (0x005E48E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571  (0x005E48EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572  (0x005E48F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573  (0x005E48F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574  (0x005E48F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575  (0x005E48FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576  (0x005E4900)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577  (0x005E4904)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578  (0x005E4908)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579  (0x005E490C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580  (0x005E4910)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581  (0x005E4914)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582  (0x005E4918)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583  (0x005E491C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584  (0x005E4920)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585  (0x005E4924)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586  (0x005E4928)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587  (0x005E492C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588  (0x005E4930)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589  (0x005E4934)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590  (0x005E4938)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591  (0x005E493C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592  (0x005E4940)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593  (0x005E4944)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594  (0x005E4948)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595  (0x005E494C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596  (0x005E4950)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597  (0x005E4954)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598  (0x005E4958)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599  (0x005E495C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600  (0x005E4960)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601  (0x005E4964)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602  (0x005E4968)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603  (0x005E496C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604  (0x005E4970)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605  (0x005E4974)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606  (0x005E4978)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607  (0x005E497C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608  (0x005E4980)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609  (0x005E4984)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610  (0x005E4988)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611  (0x005E498C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612  (0x005E4990)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613  (0x005E4994)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614  (0x005E4998)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615  (0x005E499C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616  (0x005E49A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617  (0x005E49A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618  (0x005E49A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619  (0x005E49AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620  (0x005E49B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621  (0x005E49B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622  (0x005E49B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623  (0x005E49BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624  (0x005E49C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625  (0x005E49C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626  (0x005E49C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627  (0x005E49CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628  (0x005E49D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629  (0x005E49D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630  (0x005E49D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631  (0x005E49DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632  (0x005E49E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633  (0x005E49E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634  (0x005E49E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635  (0x005E49EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636  (0x005E49F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637  (0x005E49F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638  (0x005E49F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639  (0x005E49FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640  (0x005E4A00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641  (0x005E4A04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642  (0x005E4A08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643  (0x005E4A0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644  (0x005E4A10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645  (0x005E4A14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646  (0x005E4A18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647  (0x005E4A1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648  (0x005E4A20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649  (0x005E4A24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650  (0x005E4A28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651  (0x005E4A2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652  (0x005E4A30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653  (0x005E4A34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654  (0x005E4A38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655  (0x005E4A3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656  (0x005E4A40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657  (0x005E4A44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658  (0x005E4A48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659  (0x005E4A4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660  (0x005E4A50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661  (0x005E4A54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662  (0x005E4A58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663  (0x005E4A5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664  (0x005E4A60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665  (0x005E4A64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666  (0x005E4A68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667  (0x005E4A6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668  (0x005E4A70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669  (0x005E4A74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670  (0x005E4A78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671  (0x005E4A7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672  (0x005E4A80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673  (0x005E4A84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674  (0x005E4A88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675  (0x005E4A8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676  (0x005E4A90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677  (0x005E4A94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678  (0x005E4A98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679  (0x005E4A9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680  (0x005E4AA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681  (0x005E4AA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682  (0x005E4AA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683  (0x005E4AAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684  (0x005E4AB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685  (0x005E4AB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686  (0x005E4AB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687  (0x005E4ABC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688  (0x005E4AC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689  (0x005E4AC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690  (0x005E4AC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691  (0x005E4ACC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692  (0x005E4AD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693  (0x005E4AD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694  (0x005E4AD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695  (0x005E4ADC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696  (0x005E4AE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697  (0x005E4AE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698  (0x005E4AE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699  (0x005E4AEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700  (0x005E4AF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701  (0x005E4AF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702  (0x005E4AF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703  (0x005E4AFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704  (0x005E4B00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705  (0x005E4B04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706  (0x005E4B08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707  (0x005E4B0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708  (0x005E4B10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709  (0x005E4B14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710  (0x005E4B18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711  (0x005E4B1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712  (0x005E4B20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713  (0x005E4B24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714  (0x005E4B28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715  (0x005E4B2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716  (0x005E4B30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717  (0x005E4B34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718  (0x005E4B38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719  (0x005E4B3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720  (0x005E4B40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721  (0x005E4B44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722  (0x005E4B48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723  (0x005E4B4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724  (0x005E4B50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725  (0x005E4B54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726  (0x005E4B58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727  (0x005E4B5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728  (0x005E4B60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729  (0x005E4B64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730  (0x005E4B68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731  (0x005E4B6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732  (0x005E4B70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733  (0x005E4B74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734  (0x005E4B78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735  (0x005E4B7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736  (0x005E4B80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737  (0x005E4B84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738  (0x005E4B88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739  (0x005E4B8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740  (0x005E4B90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741  (0x005E4B94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742  (0x005E4B98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743  (0x005E4B9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744  (0x005E4BA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745  (0x005E4BA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746  (0x005E4BA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747  (0x005E4BAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748  (0x005E4BB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749  (0x005E4BB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750  (0x005E4BB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751  (0x005E4BBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752  (0x005E4BC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753  (0x005E4BC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754  (0x005E4BC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755  (0x005E4BCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756  (0x005E4BD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757  (0x005E4BD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758  (0x005E4BD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759  (0x005E4BDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760  (0x005E4BE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761  (0x005E4BE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762  (0x005E4BE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763  (0x005E4BEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764  (0x005E4BF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765  (0x005E4BF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766  (0x005E4BF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767  (0x005E4BFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768  (0x005E4C00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769  (0x005E4C04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770  (0x005E4C08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771  (0x005E4C0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772  (0x005E4C10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773  (0x005E4C14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774  (0x005E4C18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775  (0x005E4C1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776  (0x005E4C20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777  (0x005E4C24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778  (0x005E4C28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779  (0x005E4C2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780  (0x005E4C30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781  (0x005E4C34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782  (0x005E4C38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783  (0x005E4C3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784  (0x005E4C40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785  (0x005E4C44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786  (0x005E4C48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787  (0x005E4C4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788  (0x005E4C50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789  (0x005E4C54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790  (0x005E4C58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791  (0x005E4C5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792  (0x005E4C60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793  (0x005E4C64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794  (0x005E4C68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795  (0x005E4C6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796  (0x005E4C70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797  (0x005E4C74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798  (0x005E4C78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799  (0x005E4C7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800  (0x005E4C80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801  (0x005E4C84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802  (0x005E4C88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803  (0x005E4C8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804  (0x005E4C90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805  (0x005E4C94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806  (0x005E4C98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807  (0x005E4C9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808  (0x005E4CA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809  (0x005E4CA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810  (0x005E4CA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811  (0x005E4CAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812  (0x005E4CB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813  (0x005E4CB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814  (0x005E4CB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815  (0x005E4CBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816  (0x005E4CC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817  (0x005E4CC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818  (0x005E4CC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819  (0x005E4CCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820  (0x005E4CD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821  (0x005E4CD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822  (0x005E4CD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823  (0x005E4CDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824  (0x005E4CE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825  (0x005E4CE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826  (0x005E4CE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827  (0x005E4CEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828  (0x005E4CF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829  (0x005E4CF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830  (0x005E4CF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831  (0x005E4CFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832  (0x005E4D00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833  (0x005E4D04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834  (0x005E4D08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835  (0x005E4D0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836  (0x005E4D10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837  (0x005E4D14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838  (0x005E4D18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839  (0x005E4D1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840  (0x005E4D20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841  (0x005E4D24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842  (0x005E4D28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843  (0x005E4D2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844  (0x005E4D30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845  (0x005E4D34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846  (0x005E4D38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847  (0x005E4D3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848  (0x005E4D40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849  (0x005E4D44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850  (0x005E4D48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851  (0x005E4D4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852  (0x005E4D50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853  (0x005E4D54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854  (0x005E4D58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855  (0x005E4D5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856  (0x005E4D60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857  (0x005E4D64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858  (0x005E4D68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859  (0x005E4D6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860  (0x005E4D70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861  (0x005E4D74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862  (0x005E4D78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863  (0x005E4D7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864  (0x005E4D80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865  (0x005E4D84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866  (0x005E4D88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867  (0x005E4D8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868  (0x005E4D90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869  (0x005E4D94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870  (0x005E4D98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871  (0x005E4D9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872  (0x005E4DA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873  (0x005E4DA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874  (0x005E4DA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875  (0x005E4DAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876  (0x005E4DB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877  (0x005E4DB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878  (0x005E4DB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879  (0x005E4DBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880  (0x005E4DC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881  (0x005E4DC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882  (0x005E4DC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883  (0x005E4DCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884  (0x005E4DD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885  (0x005E4DD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886  (0x005E4DD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887  (0x005E4DDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888  (0x005E4DE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889  (0x005E4DE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890  (0x005E4DE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891  (0x005E4DEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892  (0x005E4DF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893  (0x005E4DF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894  (0x005E4DF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895  (0x005E4DFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896  (0x005E4E00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897  (0x005E4E04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898  (0x005E4E08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899  (0x005E4E0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900  (0x005E4E10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901  (0x005E4E14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902  (0x005E4E18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903  (0x005E4E1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904  (0x005E4E20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905  (0x005E4E24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906  (0x005E4E28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907  (0x005E4E2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908  (0x005E4E30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909  (0x005E4E34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910  (0x005E4E38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911  (0x005E4E3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912  (0x005E4E40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913  (0x005E4E44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914  (0x005E4E48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915  (0x005E4E4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916  (0x005E4E50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917  (0x005E4E54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918  (0x005E4E58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919  (0x005E4E5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920  (0x005E4E60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921  (0x005E4E64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922  (0x005E4E68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923  (0x005E4E6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924  (0x005E4E70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925  (0x005E4E74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926  (0x005E4E78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927  (0x005E4E7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928  (0x005E4E80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929  (0x005E4E84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930  (0x005E4E88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931  (0x005E4E8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932  (0x005E4E90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933  (0x005E4E94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934  (0x005E4E98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935  (0x005E4E9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936  (0x005E4EA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937  (0x005E4EA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938  (0x005E4EA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939  (0x005E4EAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940  (0x005E4EB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941  (0x005E4EB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942  (0x005E4EB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943  (0x005E4EBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944  (0x005E4EC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945  (0x005E4EC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946  (0x005E4EC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947  (0x005E4ECC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948  (0x005E4ED0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949  (0x005E4ED4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950  (0x005E4ED8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951  (0x005E4EDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952  (0x005E4EE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953  (0x005E4EE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954  (0x005E4EE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955  (0x005E4EEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956  (0x005E4EF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957  (0x005E4EF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958  (0x005E4EF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959  (0x005E4EFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960  (0x005E4F00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961  (0x005E4F04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962  (0x005E4F08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963  (0x005E4F0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964  (0x005E4F10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965  (0x005E4F14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966  (0x005E4F18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967  (0x005E4F1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968  (0x005E4F20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969  (0x005E4F24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970  (0x005E4F28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971  (0x005E4F2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972  (0x005E4F30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973  (0x005E4F34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974  (0x005E4F38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975  (0x005E4F3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976  (0x005E4F40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977  (0x005E4F44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978  (0x005E4F48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979  (0x005E4F4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980  (0x005E4F50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981  (0x005E4F54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982  (0x005E4F58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983  (0x005E4F5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984  (0x005E4F60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985  (0x005E4F64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986  (0x005E4F68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987  (0x005E4F6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988  (0x005E4F70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989  (0x005E4F74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990  (0x005E4F78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991  (0x005E4F7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992  (0x005E4F80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993  (0x005E4F84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994  (0x005E4F88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995  (0x005E4F8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996  (0x005E4F90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997  (0x005E4F94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998  (0x005E4F98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999  (0x005E4F9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000 (0x005E4FA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001 (0x005E4FA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002 (0x005E4FA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003 (0x005E4FAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004 (0x005E4FB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005 (0x005E4FB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006 (0x005E4FB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007 (0x005E4FBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008 (0x005E4FC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009 (0x005E4FC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010 (0x005E4FC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011 (0x005E4FCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012 (0x005E4FD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013 (0x005E4FD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014 (0x005E4FD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015 (0x005E4FDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016 (0x005E4FE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017 (0x005E4FE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018 (0x005E4FE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019 (0x005E4FEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020 (0x005E4FF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021 (0x005E4FF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022 (0x005E4FF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023 (0x005E4FFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0    (0x005E5000)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1    (0x005E5004)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2    (0x005E5008)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3    (0x005E500C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4    (0x005E5010)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5    (0x005E5014)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6    (0x005E5018)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7    (0x005E501C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8    (0x005E5020)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9    (0x005E5024)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10   (0x005E5028)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11   (0x005E502C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12   (0x005E5030)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13   (0x005E5034)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14   (0x005E5038)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15   (0x005E503C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16   (0x005E5040)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17   (0x005E5044)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18   (0x005E5048)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19   (0x005E504C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20   (0x005E5050)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21   (0x005E5054)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22   (0x005E5058)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23   (0x005E505C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24   (0x005E5060)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25   (0x005E5064)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26   (0x005E5068)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27   (0x005E506C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28   (0x005E5070)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29   (0x005E5074)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30   (0x005E5078)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31   (0x005E507C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32   (0x005E5080)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33   (0x005E5084)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34   (0x005E5088)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35   (0x005E508C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36   (0x005E5090)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37   (0x005E5094)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38   (0x005E5098)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39   (0x005E509C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40   (0x005E50A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41   (0x005E50A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42   (0x005E50A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43   (0x005E50AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44   (0x005E50B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45   (0x005E50B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46   (0x005E50B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47   (0x005E50BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48   (0x005E50C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49   (0x005E50C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50   (0x005E50C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51   (0x005E50CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52   (0x005E50D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53   (0x005E50D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54   (0x005E50D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55   (0x005E50DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56   (0x005E50E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57   (0x005E50E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58   (0x005E50E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59   (0x005E50EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60   (0x005E50F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61   (0x005E50F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62   (0x005E50F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63   (0x005E50FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64   (0x005E5100)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65   (0x005E5104)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66   (0x005E5108)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67   (0x005E510C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68   (0x005E5110)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69   (0x005E5114)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70   (0x005E5118)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71   (0x005E511C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72   (0x005E5120)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73   (0x005E5124)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74   (0x005E5128)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75   (0x005E512C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76   (0x005E5130)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77   (0x005E5134)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78   (0x005E5138)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79   (0x005E513C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80   (0x005E5140)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81   (0x005E5144)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82   (0x005E5148)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83   (0x005E514C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84   (0x005E5150)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85   (0x005E5154)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86   (0x005E5158)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87   (0x005E515C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88   (0x005E5160)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89   (0x005E5164)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90   (0x005E5168)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91   (0x005E516C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92   (0x005E5170)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93   (0x005E5174)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94   (0x005E5178)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95   (0x005E517C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96   (0x005E5180)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97   (0x005E5184)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98   (0x005E5188)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99   (0x005E518C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100  (0x005E5190)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101  (0x005E5194)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102  (0x005E5198)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103  (0x005E519C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104  (0x005E51A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105  (0x005E51A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106  (0x005E51A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107  (0x005E51AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108  (0x005E51B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109  (0x005E51B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110  (0x005E51B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111  (0x005E51BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112  (0x005E51C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113  (0x005E51C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114  (0x005E51C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115  (0x005E51CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116  (0x005E51D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117  (0x005E51D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118  (0x005E51D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119  (0x005E51DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120  (0x005E51E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121  (0x005E51E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122  (0x005E51E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123  (0x005E51EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124  (0x005E51F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125  (0x005E51F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126  (0x005E51F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127  (0x005E51FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128  (0x005E5200)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129  (0x005E5204)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130  (0x005E5208)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131  (0x005E520C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132  (0x005E5210)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133  (0x005E5214)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134  (0x005E5218)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135  (0x005E521C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136  (0x005E5220)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137  (0x005E5224)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138  (0x005E5228)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139  (0x005E522C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140  (0x005E5230)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141  (0x005E5234)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142  (0x005E5238)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143  (0x005E523C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144  (0x005E5240)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145  (0x005E5244)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146  (0x005E5248)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147  (0x005E524C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148  (0x005E5250)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149  (0x005E5254)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150  (0x005E5258)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151  (0x005E525C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152  (0x005E5260)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153  (0x005E5264)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154  (0x005E5268)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155  (0x005E526C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156  (0x005E5270)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157  (0x005E5274)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158  (0x005E5278)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159  (0x005E527C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160  (0x005E5280)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161  (0x005E5284)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162  (0x005E5288)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163  (0x005E528C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164  (0x005E5290)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165  (0x005E5294)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166  (0x005E5298)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167  (0x005E529C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168  (0x005E52A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169  (0x005E52A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170  (0x005E52A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171  (0x005E52AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172  (0x005E52B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173  (0x005E52B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174  (0x005E52B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175  (0x005E52BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176  (0x005E52C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177  (0x005E52C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178  (0x005E52C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179  (0x005E52CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180  (0x005E52D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181  (0x005E52D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182  (0x005E52D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183  (0x005E52DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184  (0x005E52E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185  (0x005E52E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186  (0x005E52E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187  (0x005E52EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188  (0x005E52F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189  (0x005E52F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190  (0x005E52F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191  (0x005E52FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192  (0x005E5300)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193  (0x005E5304)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194  (0x005E5308)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195  (0x005E530C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196  (0x005E5310)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197  (0x005E5314)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198  (0x005E5318)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199  (0x005E531C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200  (0x005E5320)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201  (0x005E5324)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202  (0x005E5328)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203  (0x005E532C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204  (0x005E5330)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205  (0x005E5334)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206  (0x005E5338)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207  (0x005E533C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208  (0x005E5340)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209  (0x005E5344)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210  (0x005E5348)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211  (0x005E534C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212  (0x005E5350)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213  (0x005E5354)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214  (0x005E5358)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215  (0x005E535C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216  (0x005E5360)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217  (0x005E5364)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218  (0x005E5368)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219  (0x005E536C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220  (0x005E5370)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221  (0x005E5374)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222  (0x005E5378)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223  (0x005E537C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224  (0x005E5380)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225  (0x005E5384)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226  (0x005E5388)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227  (0x005E538C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228  (0x005E5390)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229  (0x005E5394)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230  (0x005E5398)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231  (0x005E539C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232  (0x005E53A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233  (0x005E53A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234  (0x005E53A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235  (0x005E53AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236  (0x005E53B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237  (0x005E53B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238  (0x005E53B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239  (0x005E53BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240  (0x005E53C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241  (0x005E53C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242  (0x005E53C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243  (0x005E53CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244  (0x005E53D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245  (0x005E53D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246  (0x005E53D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247  (0x005E53DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248  (0x005E53E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249  (0x005E53E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250  (0x005E53E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251  (0x005E53EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252  (0x005E53F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253  (0x005E53F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254  (0x005E53F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255  (0x005E53FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0    (0x005E5800)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1    (0x005E5804)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2    (0x005E5808)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3    (0x005E580C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4    (0x005E5810)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5    (0x005E5814)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6    (0x005E5818)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7    (0x005E581C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8    (0x005E5820)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9    (0x005E5824)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10   (0x005E5828)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11   (0x005E582C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12   (0x005E5830)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13   (0x005E5834)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14   (0x005E5838)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15   (0x005E583C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16   (0x005E5840)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17   (0x005E5844)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18   (0x005E5848)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19   (0x005E584C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20   (0x005E5850)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21   (0x005E5854)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22   (0x005E5858)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23   (0x005E585C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24   (0x005E5860)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25   (0x005E5864)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26   (0x005E5868)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27   (0x005E586C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28   (0x005E5870)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29   (0x005E5874)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30   (0x005E5878)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31   (0x005E587C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32   (0x005E5880)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33   (0x005E5884)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34   (0x005E5888)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35   (0x005E588C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36   (0x005E5890)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37   (0x005E5894)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38   (0x005E5898)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39   (0x005E589C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40   (0x005E58A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41   (0x005E58A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42   (0x005E58A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43   (0x005E58AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44   (0x005E58B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45   (0x005E58B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46   (0x005E58B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47   (0x005E58BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48   (0x005E58C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49   (0x005E58C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50   (0x005E58C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51   (0x005E58CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52   (0x005E58D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53   (0x005E58D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54   (0x005E58D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55   (0x005E58DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56   (0x005E58E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57   (0x005E58E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58   (0x005E58E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59   (0x005E58EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60   (0x005E58F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61   (0x005E58F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62   (0x005E58F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63   (0x005E58FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64   (0x005E5900)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65   (0x005E5904)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66   (0x005E5908)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67   (0x005E590C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68   (0x005E5910)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69   (0x005E5914)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70   (0x005E5918)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71   (0x005E591C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72   (0x005E5920)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73   (0x005E5924)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74   (0x005E5928)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75   (0x005E592C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76   (0x005E5930)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77   (0x005E5934)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78   (0x005E5938)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79   (0x005E593C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80   (0x005E5940)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81   (0x005E5944)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82   (0x005E5948)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83   (0x005E594C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84   (0x005E5950)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85   (0x005E5954)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86   (0x005E5958)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87   (0x005E595C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88   (0x005E5960)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89   (0x005E5964)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90   (0x005E5968)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91   (0x005E596C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92   (0x005E5970)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93   (0x005E5974)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94   (0x005E5978)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95   (0x005E597C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96   (0x005E5980)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97   (0x005E5984)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98   (0x005E5988)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99   (0x005E598C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100  (0x005E5990)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101  (0x005E5994)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102  (0x005E5998)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103  (0x005E599C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104  (0x005E59A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105  (0x005E59A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106  (0x005E59A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107  (0x005E59AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108  (0x005E59B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109  (0x005E59B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110  (0x005E59B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111  (0x005E59BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112  (0x005E59C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113  (0x005E59C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114  (0x005E59C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115  (0x005E59CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116  (0x005E59D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117  (0x005E59D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118  (0x005E59D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119  (0x005E59DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120  (0x005E59E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121  (0x005E59E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122  (0x005E59E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123  (0x005E59EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124  (0x005E59F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125  (0x005E59F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126  (0x005E59F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127  (0x005E59FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0    (0x005E5C00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1    (0x005E5C04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2    (0x005E5C08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3    (0x005E5C0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4    (0x005E5C10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5    (0x005E5C14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6    (0x005E5C18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7    (0x005E5C1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8    (0x005E5C20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9    (0x005E5C24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10   (0x005E5C28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11   (0x005E5C2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12   (0x005E5C30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13   (0x005E5C34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14   (0x005E5C38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15   (0x005E5C3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16   (0x005E5C40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17   (0x005E5C44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18   (0x005E5C48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19   (0x005E5C4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20   (0x005E5C50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21   (0x005E5C54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22   (0x005E5C58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23   (0x005E5C5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24   (0x005E5C60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25   (0x005E5C64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26   (0x005E5C68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27   (0x005E5C6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28   (0x005E5C70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29   (0x005E5C74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30   (0x005E5C78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31   (0x005E5C7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32   (0x005E5C80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33   (0x005E5C84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34   (0x005E5C88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35   (0x005E5C8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36   (0x005E5C90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37   (0x005E5C94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38   (0x005E5C98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39   (0x005E5C9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40   (0x005E5CA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41   (0x005E5CA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42   (0x005E5CA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43   (0x005E5CAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44   (0x005E5CB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45   (0x005E5CB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46   (0x005E5CB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47   (0x005E5CBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48   (0x005E5CC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49   (0x005E5CC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50   (0x005E5CC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51   (0x005E5CCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52   (0x005E5CD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53   (0x005E5CD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54   (0x005E5CD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55   (0x005E5CDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56   (0x005E5CE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57   (0x005E5CE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58   (0x005E5CE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59   (0x005E5CEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60   (0x005E5CF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61   (0x005E5CF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62   (0x005E5CF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63   (0x005E5CFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64   (0x005E5D00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65   (0x005E5D04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66   (0x005E5D08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67   (0x005E5D0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68   (0x005E5D10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69   (0x005E5D14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70   (0x005E5D18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71   (0x005E5D1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72   (0x005E5D20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73   (0x005E5D24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74   (0x005E5D28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75   (0x005E5D2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76   (0x005E5D30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77   (0x005E5D34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78   (0x005E5D38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79   (0x005E5D3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80   (0x005E5D40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81   (0x005E5D44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82   (0x005E5D48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83   (0x005E5D4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84   (0x005E5D50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85   (0x005E5D54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86   (0x005E5D58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87   (0x005E5D5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88   (0x005E5D60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89   (0x005E5D64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90   (0x005E5D68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91   (0x005E5D6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92   (0x005E5D70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93   (0x005E5D74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94   (0x005E5D78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95   (0x005E5D7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96   (0x005E5D80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97   (0x005E5D84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98   (0x005E5D88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99   (0x005E5D8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100  (0x005E5D90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101  (0x005E5D94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102  (0x005E5D98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103  (0x005E5D9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104  (0x005E5DA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105  (0x005E5DA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106  (0x005E5DA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107  (0x005E5DAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108  (0x005E5DB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109  (0x005E5DB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110  (0x005E5DB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111  (0x005E5DBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112  (0x005E5DC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113  (0x005E5DC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114  (0x005E5DC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115  (0x005E5DCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116  (0x005E5DD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117  (0x005E5DD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118  (0x005E5DD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119  (0x005E5DDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120  (0x005E5DE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121  (0x005E5DE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122  (0x005E5DE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123  (0x005E5DEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124  (0x005E5DF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125  (0x005E5DF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126  (0x005E5DF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127  (0x005E5DFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG   (0x005E8000)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0        (0x005E8004)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1        (0x005E8008)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___S               6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0   (0x005E800C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1   (0x005E8010)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2   (0x005E8014)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___POR 0x0000C001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S              14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S              13
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S              11
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S              10
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___M 0xC000FF01   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0      (0x005E8018)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___M 0xFECC0000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0      (0x005E801C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___M 0xFEDC0000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET     (0x005E8020)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0 (0x005E8024)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___POR 0x06769292
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0 (0x005E8028)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___POR 0x00004142
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0   (0x005E802C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___S              29
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___S              29

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0       (0x005E8030)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0   (0x005E8034)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1   (0x005E8038)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG (0x005E803C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2        (0x005E8040)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0    (0x005E8044)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___POR 0x09200000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___M 0x0FF80007   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST    (0x005E8048)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0 (0x005E8080)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___POR 0x005078A0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1 (0x005E8084)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___POR 0xC8F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___M 0xFFFF03FF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL (0x005E8088)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___M 0x0000C000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___S              14

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0 (0x005E808C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1 (0x005E8090)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___M 0x0000FFBF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0 (0x005E8094)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0 (0x005E8098)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1 (0x005E809C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0 (0x005E80A0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___M 0x000C3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0        (0x005E80A4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___S              30

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC   (0x005E80A8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC   (0x005E80AC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___M 0x007F3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN   (0x005E80B0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___M 0x00FFFFBF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0 (0x005E80B4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1 (0x005E80B8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___M 0x7FFF3F00   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___S               8

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0        (0x005E80C0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1        (0x005E80C4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2        (0x005E80C8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3        (0x005E80CC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4        (0x005E80D0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5        (0x005E80D4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6        (0x005E80D8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7        (0x005E80DC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8        (0x005E80E0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9        (0x005E80E4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10       (0x005E80E8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11       (0x005E80EC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12       (0x005E80F0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13       (0x005E80F4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14       (0x005E80F8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15       (0x005E80FC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16       (0x005E8100)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17       (0x005E8104)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18       (0x005E8108)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19       (0x005E810C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20       (0x005E8110)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21       (0x005E8114)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22       (0x005E8118)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23       (0x005E811C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24       (0x005E8120)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25       (0x005E8124)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26       (0x005E8128)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27       (0x005E812C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28       (0x005E8130)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29       (0x005E8134)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30       (0x005E8138)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31       (0x005E813C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32       (0x005E8140)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33       (0x005E8144)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34       (0x005E8148)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35       (0x005E814C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36       (0x005E8150)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37       (0x005E8154)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38       (0x005E8158)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39       (0x005E815C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40       (0x005E8160)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41       (0x005E8164)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42       (0x005E8168)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43       (0x005E816C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44       (0x005E8170)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45       (0x005E8174)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46       (0x005E8178)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47       (0x005E817C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48       (0x005E8180)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49       (0x005E8184)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50       (0x005E8188)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51       (0x005E818C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52       (0x005E8190)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53       (0x005E8194)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54       (0x005E8198)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55       (0x005E819C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56       (0x005E81A0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57       (0x005E81A4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58       (0x005E81A8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59       (0x005E81AC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60       (0x005E81B0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61       (0x005E81B4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62       (0x005E81B8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63       (0x005E81BC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___S              26

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL   (0x005E8400)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___M 0x0F800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___S              23

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG    (0x005E8404)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB        (0x005E8408)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___M 0x00FF8000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC      (0x005E840C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___POR 0x92492400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___S              10

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0     (0x005E8410)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___POR 0x87CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1     (0x005E8414)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___POR 0x07CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2     (0x005E8418)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___POR 0x07CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3     (0x005E841C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___POR 0x07C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0      (0x005E8420)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___POR 0x7EC8AF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___POR 0x045
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1      (0x005E8424)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___POR 0x7EC9CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___POR 0x04E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2      (0x005E8428)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___POR 0x7ECAEF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___POR 0x057
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3      (0x005E842C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___POR 0x7ECC4F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___POR 0x062
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4      (0x005E8430)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___POR 0x7ECDCF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___POR 0x06E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5      (0x005E8434)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___POR 0x7ECF6F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___POR 0x07B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6      (0x005E8438)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___POR 0x7ED14F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___POR 0x08A
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7      (0x005E843C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___POR 0x7ED36F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___POR 0x09B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8      (0x005E8440)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9      (0x005E8444)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10     (0x005E8448)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11     (0x005E844C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12     (0x005E8450)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13     (0x005E8454)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14     (0x005E8458)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15     (0x005E845C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16     (0x005E8460)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17     (0x005E8464)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18     (0x005E8468)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19     (0x005E846C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20     (0x005E8470)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21     (0x005E8474)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22     (0x005E8478)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0    (0x005E847C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1    (0x005E8480)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2    (0x005E8484)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3    (0x005E8488)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0     (0x005E848C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1     (0x005E8490)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2     (0x005E8494)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3     (0x005E8498)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___POR 0x18000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___POR 0x03
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4     (0x005E849C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___POR 0x04
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5     (0x005E84A0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___POR 0x28000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6     (0x005E84A4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7     (0x005E84A8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___POR 0x38000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___POR 0x07
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8     (0x005E84AC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___POR 0x08
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9     (0x005E84B0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___POR 0x48000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___POR 0x09
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10    (0x005E84B4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11    (0x005E84B8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___POR 0x58000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___POR 0x0B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12    (0x005E84BC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13    (0x005E84C0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___POR 0x68000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___POR 0x0D
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14    (0x005E84C4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15    (0x005E84C8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___POR 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16    (0x005E84CC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___POR 0x10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17    (0x005E84D0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___POR 0x88000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___POR 0x11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18    (0x005E84D4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___POR 0x90000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19    (0x005E84D8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___POR 0x98000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___POR 0x13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20    (0x005E84DC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___POR 0xA0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21    (0x005E84E0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___POR 0xA8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___POR 0x15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22    (0x005E84E4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___POR 0xB0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___POR 0x16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0   (0x005E84E8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___M 0x0FF80000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___M 0xFFFFFFF0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___S               4

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1   (0x005E84EC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___S               8

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0    (0x005E84F0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1    (0x005E84F4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___M 0x0000FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___M 0x000000FE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV        (0x005E84F8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___S              28

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0           (0x005E84FC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___S                  0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX    (0x005E8500)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___M 0x3E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___S              25

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0   (0x005E8504)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___M 0x001FF000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___S               8

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1   (0x005E8508)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___M 0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___S              14

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0    (0x005E850C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___M 0x00FF8000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1    (0x005E8510)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___M 0x07800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___M 0x000FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___M 0x00001FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB     (0x005E8514)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT           (0x005E8518)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___POR  0x58000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___M    0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___S                 27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA           (0x005E851C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___POR  0x37000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___M    0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___S                 22

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ            (0x005E8520)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___POR   0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___M     0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___S                  27

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2           (0x005E8524)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___POR  0x00000020
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___S               3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___M    0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___S                  3

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0 (0x005E8528)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___S              16

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1 (0x005E852C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___POR 0x80426300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___POR 0x9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___S               3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___S               2

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL (0x005E8530)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___S              16

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0        (0x005E8534)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___POR 0x00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___M 0x0003FFFF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0          (0x005E8538)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___POR 0xD8049248
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___M   0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1          (0x005E853C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___POR 0x4800006C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___M 0x0003E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___M   0xFFFFE0FC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2          (0x005E8540)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___POR 0x1088B000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___M   0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___S                12

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3          (0x005E8544)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___POR 0x00005E2F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___M   0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___S                 0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4          (0x005E8548)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___POR 0x178BDCB9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___S                 0

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5          (0x005E854C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___POR 0x72E49630
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___M 0x00000F80
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___M 0x0000007C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___M   0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE      (0x005E8550)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC  (0x005E8554)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___POR 0xDADB7400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___S              10

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT   (0x005E8558)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___POR 0x00BFF234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT    (0x005E855C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___POR 0x2AC01776
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA       (0x005E8560)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___POR 0x37000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___S              22

#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ        (0x005E8564)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___S              27

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG       (0x005E8800)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___POR 0x22BB1212
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___POR 0x22BB1212
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL   (0x005E8804)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___M 0x0000007F   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG      (0x005E8808)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___S              30

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC          (0x005E880C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___M   0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___S                16

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0     (0x005E8810)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___POR 0x04040434
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___S               8
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___S               4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1     (0x005E8814)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___POR 0x5268DB71
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___S              14
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___S              11
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___S               8
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___S               5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___S               2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2     (0x005E8818)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___POR 0x2B000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___S              24

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0    (0x005E881C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1    (0x005E8820)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2    (0x005E8824)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3    (0x005E8828)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4    (0x005E882C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5    (0x005E8830)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6    (0x005E8834)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7    (0x005E8838)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8    (0x005E883C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9    (0x005E8840)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10   (0x005E8844)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11   (0x005E8848)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12   (0x005E884C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13   (0x005E8850)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14   (0x005E8854)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15   (0x005E8858)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16   (0x005E885C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17   (0x005E8860)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18   (0x005E8864)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19   (0x005E8868)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20   (0x005E886C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21   (0x005E8870)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22   (0x005E8874)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23   (0x005E8878)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24   (0x005E887C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25   (0x005E8880)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26   (0x005E8884)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27   (0x005E8888)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28   (0x005E888C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29   (0x005E8890)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30   (0x005E8894)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31   (0x005E8898)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32   (0x005E889C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33   (0x005E88A0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34   (0x005E88A4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35   (0x005E88A8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36   (0x005E88AC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37   (0x005E88B0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38   (0x005E88B4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39   (0x005E88B8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40   (0x005E88BC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41   (0x005E88C0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42   (0x005E88C4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43   (0x005E88C8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44   (0x005E88CC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45   (0x005E88D0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46   (0x005E88D4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47   (0x005E88D8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48   (0x005E88DC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49   (0x005E88E0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50   (0x005E88E4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51   (0x005E88E8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52   (0x005E88EC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53   (0x005E88F0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54   (0x005E88F4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55   (0x005E88F8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56   (0x005E88FC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57   (0x005E8900)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58   (0x005E8904)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59   (0x005E8908)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60   (0x005E890C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61   (0x005E8910)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62   (0x005E8914)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63   (0x005E8918)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0  (0x005E891C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1  (0x005E8920)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2  (0x005E8924)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3  (0x005E8928)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4  (0x005E892C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5  (0x005E8930)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6  (0x005E8934)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7  (0x005E8938)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8  (0x005E893C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9  (0x005E8940)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10 (0x005E8944)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11 (0x005E8948)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___POR 0x42400000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___POR 0x21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12 (0x005E894C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___POR 0x40200000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13 (0x005E8950)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___POR 0x10080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14 (0x005E8954)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___POR 0x08040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15 (0x005E8958)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16 (0x005E895C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___POR 0x40100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17 (0x005E8960)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___POR 0x20080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18 (0x005E8964)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___POR 0x42100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___POR 0x21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19 (0x005E8968)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___POR 0x80200000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___POR 0x40
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20 (0x005E896C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___POR 0x44100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___POR 0x22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21 (0x005E8970)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___POR 0x30100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___POR 0x18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22 (0x005E8974)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___POR 0x50100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___POR 0x28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23 (0x005E8978)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___POR 0x84100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___POR 0x42
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24 (0x005E897C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___POR 0x90100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___POR 0x48
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25 (0x005E8980)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___POR 0x88080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___POR 0x44
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26 (0x005E8984)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___POR 0x88040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___POR 0x44
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27 (0x005E8988)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___POR 0xA0040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___POR 0x50
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28 (0x005E898C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___POR 0xC8040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___POR 0x64
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29 (0x005E8990)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___POR 0xD8040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___POR 0x6C
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30 (0x005E8994)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___POR 0xF2000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___POR 0x79
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31 (0x005E8998)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___POR 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___POR 0x7F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32 (0x005E899C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33 (0x005E89A0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34 (0x005E89A4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35 (0x005E89A8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36 (0x005E89AC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37 (0x005E89B0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38 (0x005E89B4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39 (0x005E89B8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40 (0x005E89BC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41 (0x005E89C0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42 (0x005E89C4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43 (0x005E89C8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44 (0x005E89CC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45 (0x005E89D0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46 (0x005E89D4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47 (0x005E89D8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48 (0x005E89DC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49 (0x005E89E0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50 (0x005E89E4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51 (0x005E89E8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52 (0x005E89EC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53 (0x005E89F0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54 (0x005E89F4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55 (0x005E89F8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56 (0x005E89FC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57 (0x005E8A00)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58 (0x005E8A04)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59 (0x005E8A08)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60 (0x005E8A0C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61 (0x005E8A10)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62 (0x005E8A14)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63 (0x005E8A18)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0       (0x005E8A1C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___S              23

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1       (0x005E8A20)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___S              16

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0           (0x005E8A24)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___M    0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___S                 14

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT        (0x005E8A28)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___S              11
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___S               5

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0         (0x005E8A30)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___POR 0x6D55B000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___S              20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___S              15
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___S              12
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___M  0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___S               12

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE         (0x005E8A34)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___POR 0xB4000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___M  0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___S               26

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB           (0x005E8A38)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___M    0xFF800000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___S                 23

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0        (0x005E8A3C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1        (0x005E8A40)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG    (0x005E9000)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___POR 0x44FE5111
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___POR 0x44FE5111
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL (0x005E9004)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___S              22

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0 (0x005E9008)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___POR 0x8C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___POR 0xC
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1 (0x005E900C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___POR 0x30C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___POR 0xC
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0 (0x005E9010)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___POR 0x62409760
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1 (0x005E9014)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___POR 0x63009D60
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2 (0x005E9018)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___POR 0x6360A360
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___POR 0x1B
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3 (0x005E901C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___POR 0x6380A860
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___POR 0x1C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4 (0x005E9020)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___POR 0x628E9080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5 (0x005E9024)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___POR 0x62809080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6 (0x005E9028)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___POR 0x03E29880
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7 (0x005E902C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___POR 0x06209080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___POR 0x31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0 (0x005E9030)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1 (0x005E9034)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2 (0x005E9038)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___POR 0x14520000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3 (0x005E903C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___POR 0x1E7A0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4 (0x005E9040)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___POR 0x28930000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5 (0x005E9044)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___POR 0x3CC20000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___POR 0x1E
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6 (0x005E9048)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7 (0x005E904C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0    (0x005E9080)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___M 0x0003E000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___M 0x000003C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___S               2

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT (0x005E9084)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___S              26

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1    (0x005E9088)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2    (0x005E908C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___S              15

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0 (0x005E9090)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1 (0x005E9094)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___M 0xFFF00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___S              20

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL (0x005E9098)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___S              25

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0 (0x005E909C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1 (0x005E90A0)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2 (0x005E90A4)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0  (0x005E90A8)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___POR 0x20280E00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___M 0x1FC00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___M 0xFFFE1E00   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___S               9

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL (0x005E90AC)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0 (0x005E90B0)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___POR 0x520103C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___M 0x00003C00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___M 0xFFFFBFC0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___S               6

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1 (0x005E90B4)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2 (0x005E90B8)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___POR 0x00968000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE (0x005E90BC)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___POR 0x000002
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG    (0x005E9300)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___POR 0x33FE5111
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___POR 0x33FE5111
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL (0x005E9304)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___S              16

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0 (0x005E9308)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___POR 0x04101800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1 (0x005E930C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___POR 0x04101800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0 (0x005E9310)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1 (0x005E9314)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2 (0x005E9318)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3 (0x005E931C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4 (0x005E9320)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5 (0x005E9324)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6 (0x005E9328)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7 (0x005E932C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8 (0x005E9330)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9 (0x005E9334)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___POR 0x06009000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x00C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10 (0x005E9338)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___POR 0x07009000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x00E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11 (0x005E933C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___POR 0x07819000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12 (0x005E9340)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___POR 0x0A821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x015
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13 (0x005E9344)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___POR 0x0B821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x017
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14 (0x005E9348)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___POR 0x10821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x021
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15 (0x005E934C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___POR 0x11829000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x023
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16 (0x005E9350)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___POR 0x13029000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x026
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17 (0x005E9354)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___POR 0x14831000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x029
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18 (0x005E9358)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___POR 0x18831000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x031
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19 (0x005E935C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___POR 0x1B031000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x036
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20 (0x005E9360)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___POR 0x1D839000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x03B
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21 (0x005E9364)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___POR 0x24841000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x049
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22 (0x005E9368)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___POR 0x29849000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x053
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x09
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23 (0x005E936C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___POR 0x30861000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x061
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24 (0x005E9370)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___POR 0x34079000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x068
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25 (0x005E9374)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___POR 0x3A0A1000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x074
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26 (0x005E9378)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___POR 0x3E0C9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x07C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27 (0x005E937C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___POR 0x4A0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x094
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28 (0x005E9380)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___POR 0x550F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0AA
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29 (0x005E9384)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___POR 0x5E0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0BC
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30 (0x005E9388)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___POR 0x6D8F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0DB
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31 (0x005E938C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___POR 0x7F8F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0 (0x005E9390)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1 (0x005E9394)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2 (0x005E9398)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3 (0x005E939C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4 (0x005E93A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5 (0x005E93A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6 (0x005E93A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7 (0x005E93AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0 (0x005E93B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___POR 0xD02EE80E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___POR 0x007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1 (0x005E93B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___POR 0xD02EE80E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___POR 0x007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2 (0x005E93B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___POR 0xD02EE81E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3 (0x005E93BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___POR 0xD02EE81E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4 (0x005E93C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___POR 0xD02EE87E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___POR 0x03F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5 (0x005E93C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___POR 0xD02EE87E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___POR 0x03F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0 (0x005E93D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1 (0x005E93D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2 (0x005E93D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3 (0x005E93DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4 (0x005E93E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5 (0x005E93E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0 (0x005E93F0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1 (0x005E93F4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2 (0x005E93F8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3 (0x005E93FC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4 (0x005E9400)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5 (0x005E9404)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0 (0x005E9410)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___POR 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1 (0x005E9414)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___POR 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2 (0x005E9418)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___POR 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3 (0x005E941C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___POR 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4 (0x005E9420)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___POR 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5 (0x005E9424)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___POR 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0 (0x005E9430)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1 (0x005E9434)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2 (0x005E9438)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3 (0x005E943C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4 (0x005E9440)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5 (0x005E9444)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0 (0x005E9450)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___POR 0x10040000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x040
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x040
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1 (0x005E9454)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___POR 0x18050000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x060
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x050
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2 (0x005E9458)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___POR 0x18050000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x060
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x050
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3 (0x005E945C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___POR 0x1B05C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x06C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x05C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4 (0x005E9460)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___POR 0x1B05C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x06C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x05C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5 (0x005E9464)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___POR 0x1BC5F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x06F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x05F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0    (0x005E9470)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1    (0x005E9474)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2    (0x005E9478)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___M 0x0000F800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3    (0x005E947C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___M 0x000001FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4    (0x005E9480)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___M 0x00000078
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___S               3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___S               3

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5    (0x005E9484)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___M 0x07FE0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___M 0x0000FFC0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0 (0x005E9488)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___POR 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___M 0x000FC000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___S              14

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1 (0x005E948C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___M 0xFFF7FC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2 (0x005E9490)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0 (0x005E9494)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___M 0xFFFFF800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1 (0x005E9498)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2 (0x005E949C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___M 0x03E00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___S               3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3 (0x005E94A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___M 0x1FF00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___M 0x000FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4 (0x005E94A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5 (0x005E94A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___S              22

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0 (0x005E94AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___S              27

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0 (0x005E94B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___POR 0x118A0E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0 (0x005E94B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___POR 0x74000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0 (0x005E94B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1 (0x005E94BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL (0x005E94C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___S              26

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE (0x005E94C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0 (0x005E94C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___POR 0xAE000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0 (0x005E94CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___POR 0xAA000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___S              22

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY (0x005E94D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD (0x005E94D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___POR 0x08B80000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR (0x005E94D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___POR 0x6C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___M 0xFDF00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___S              20

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0  (0x005EA000)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT (0x005EA004)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0 (0x005EA040)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___POR 0x000A0026
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___S               1

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1 (0x005EA044)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___POR 0x00004020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___M 0x0007FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA (0x005EA048)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0   (0x005EA080)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___POR 0x0200E8B6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___M 0x03C2FCFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1   (0x005EA084)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___POR 0x00F80204
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___M 0x00FF03FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2   (0x005EA088)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___POR 0xECA86420
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3   (0x005EA08C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___M 0x000000F1   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0 (0x005EA090)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0 (0x005EA094)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___M 0xC03FFC30   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1 (0x005EA098)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___M 0x0CFFF000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___S              12

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2 (0x005EA09C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___POR 0x000C1010
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___M 0x001FFF3F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3 (0x005EA0A0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___POR 0x0000B880
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___M 0x1FFCFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4 (0x005EA0A4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___POR 0x01010840
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___M 0x1B07FFF0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0    (0x005EA0A8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___POR 0x1D186008
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___M 0x9FFFFE0F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1    (0x005EA0AC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___POR 0x00000840
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___M 0x00000DFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0 (0x005EA0B0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___POR 0x036E36DC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1 (0x005EA0B4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2 (0x005EA0B8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2    (0x005EA0BC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___POR 0x68000104
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___S               1

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3    (0x005EA0C0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___M 0xFFFE7FE0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___S               5

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4    (0x005EA0C4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___POR 0x00000492
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5    (0x005EA0C8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___S              28

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST   (0x005EA0CC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___S              31

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV (0x005EA0D0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___M 0x000003F0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0   (0x005EA100)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___POR 0x1B000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___M 0xFF8001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0 (0x005EA104)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___M 0xFF80001F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0 (0x005EA140)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___S              29

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0 (0x005EA144)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0    (0x005EA148)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___S              27

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0 (0x005EA14C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___S              22

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1    (0x005EA180)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___POR 0x073D11C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___POR 0xC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2    (0x005EA184)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___POR 0x00900090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0 (0x005EA188)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4    (0x005EA18C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___POR 0x22685349
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5    (0x005EA190)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___POR 0x004D4D4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6    (0x005EA194)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___POR 0x079E79E7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7    (0x005EA198)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___POR 0x27C27C27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0 (0x005EA19C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___POR 0x00008399
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9    (0x005EA1A0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0 (0x005EA1A4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___POR 0x01010000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0 (0x005EA1A8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0 (0x005EA1AC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13   (0x005EA1B0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14 (0x005EA1B4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG  (0x005EA400)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0   (0x005EA404)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1   (0x005EA408)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL    (0x005EA40C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___S               2
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___M 0x00000002
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___S               1
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___M 0x00000007   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING (0x005EA410)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S               4
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___M 0x000001FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET (0x005EA414)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0  (0x005EA418)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1  (0x005EA41C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0 (0x005EA420)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I (0x005EA424)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q (0x005EA428)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG  (0x005EA42C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S              23
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S              22
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S              11
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I (0x005EA430)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q (0x005EA434)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM (0x005EA438)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___POR 0x000003FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S              29
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S              10
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___M 0x3F0FFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL (0x005EA43C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___M 0x07800000   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___S              23

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0 (0x005EA440)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___M 0x20000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___S              29
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___M 0x18000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___S              27
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___M 0x07FC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___S               9
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1 (0x005EA444)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___M 0x07FC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___S               9
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG    (0x005EA580)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG    (0x005EA584)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0     (0x005EA588)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1     (0x005EA58C)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0     (0x005EA590)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___POR 0xC
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___S               7
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___S               6
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___M 0x001FF7FC   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___S               2

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1     (0x005EA594)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S              19
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S              18
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S               6
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S               5
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___M 0x03FFFF71   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1       (0x005EA598)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2       (0x005EA59C)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___POR 0x00000030
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3       (0x005EA5A0)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4       (0x005EA5A4)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5       (0x005EA5A8)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6       (0x005EA5AC)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___M 0x0000007F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7       (0x005EA5B0)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8       (0x005EA5B4)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9       (0x005EA5B8)
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00 (0x005EA5C0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01 (0x005EA5C4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02 (0x005EA5C8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03 (0x005EA5CC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04 (0x005EA5D0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05 (0x005EA5D4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06 (0x005EA5D8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07 (0x005EA5DC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08 (0x005EA5E0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09 (0x005EA5E4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10 (0x005EA5E8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11 (0x005EA5EC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12 (0x005EA5F0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13 (0x005EA5F4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14 (0x005EA5F8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15 (0x005EA5FC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16 (0x005EA600)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17 (0x005EA604)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18 (0x005EA608)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19 (0x005EA60C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20 (0x005EA610)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21 (0x005EA614)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22 (0x005EA618)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23 (0x005EA61C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24 (0x005EA620)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25 (0x005EA624)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26 (0x005EA628)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27 (0x005EA62C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28 (0x005EA630)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29 (0x005EA634)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30 (0x005EA638)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31 (0x005EA63C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00 (0x005EA640)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01 (0x005EA644)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02 (0x005EA648)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03 (0x005EA64C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04 (0x005EA650)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05 (0x005EA654)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06 (0x005EA658)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07 (0x005EA65C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08 (0x005EA660)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09 (0x005EA664)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10 (0x005EA668)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11 (0x005EA66C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12 (0x005EA670)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13 (0x005EA674)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14 (0x005EA678)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15 (0x005EA67C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16 (0x005EA680)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17 (0x005EA684)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18 (0x005EA688)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19 (0x005EA68C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20 (0x005EA690)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21 (0x005EA694)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22 (0x005EA698)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23 (0x005EA69C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24 (0x005EA6A0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25 (0x005EA6A4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26 (0x005EA6A8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27 (0x005EA6AC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28 (0x005EA6B0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29 (0x005EA6B4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30 (0x005EA6B8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31 (0x005EA6BC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0 (0x005EA6C0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1 (0x005EA6C4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2 (0x005EA6C8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3 (0x005EA6CC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4 (0x005EA6D0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5 (0x005EA6D4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6 (0x005EA6D8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7 (0x005EA6DC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8 (0x005EA6E0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0 (0x005EA6E4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1 (0x005EA6E8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2 (0x005EA6EC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3 (0x005EA6F0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4 (0x005EA6F4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5 (0x005EA6F8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6 (0x005EA6FC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7 (0x005EA700)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8 (0x005EA704)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1 (0x005EA708)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S              26
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S              15
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S              14
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___S              13
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S               7
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___S               5
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2 (0x005EA70C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S              31
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3 (0x005EA710)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4 (0x005EA714)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1 (0x005EA718)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2 (0x005EA71C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S              24
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3 (0x005EA720)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S              31
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4 (0x005EA724)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL (0x005EA728)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___POR 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG (0x005EA72C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG (0x005EA730)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0 (0x005EA734)
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___S              23
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___S              18
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___M 0x30B67007   
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG (0x005EA740)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0  (0x005EA744)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___POR 0xADC1ADC0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___POR 0xADC1ADC0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1     (0x005EA748)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL       (0x005EA74C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___POR 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___S              13
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___M 0x003F7FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG     (0x005EA750)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___M 0x000007FD   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS  (0x005EA754)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0    (0x005EA758)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___S              31
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___S              29
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___S              21
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___S              10

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1    (0x005EA75C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___M 0x03FE0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___M 0x00001FF0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___M 0x03FE1FF3   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2    (0x005EA760)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___M 0x0003FF07   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3    (0x005EA764)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0  (0x005EA768)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___POR 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG    (0x005EA76C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___S              25
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___M 0x0000FFF0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0 (0x005EA770)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1 (0x005EA774)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2 (0x005EA778)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0 (0x005EA77C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1 (0x005EA780)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2 (0x005EA784)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0 (0x005EA788)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1 (0x005EA78C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2 (0x005EA790)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0 (0x005EA794)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1 (0x005EA798)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2 (0x005EA79C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0 (0x005EA7A0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___POR 0x00400001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___S              21
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___M 0xFF7FFFF7   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1 (0x005EA7A4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0 (0x005EA7A8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1 (0x005EA7AC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2 (0x005EA7B0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0 (0x005EA7B4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1 (0x005EA7B8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2 (0x005EA7BC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0 (0x005EA7C0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1 (0x005EA7C4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2 (0x005EA7C8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0 (0x005EA7CC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1 (0x005EA7D0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2 (0x005EA7D4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG (0x005EA7D8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___M 0x0000000C   
#define   PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___S               2

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1 (0x005EA800)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2 (0x005EA804)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3 (0x005EA808)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4 (0x005EA80C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5 (0x005EA810)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6 (0x005EA814)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7 (0x005EA818)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1 (0x005EA840)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2 (0x005EA844)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3 (0x005EA848)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4 (0x005EA84C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5 (0x005EA850)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6 (0x005EA854)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7 (0x005EA858)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1 (0x005EA880)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2 (0x005EA884)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3 (0x005EA888)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4 (0x005EA88C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5 (0x005EA890)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6 (0x005EA894)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7 (0x005EA898)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1 (0x005EA8C0)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2 (0x005EA8C4)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3 (0x005EA8C8)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4 (0x005EA8CC)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5 (0x005EA8D0)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6 (0x005EA8D4)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7 (0x005EA8D8)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1 (0x005EA900)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2 (0x005EA904)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3 (0x005EA908)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4 (0x005EA90C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5 (0x005EA910)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6 (0x005EA914)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7 (0x005EA918)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8 (0x005EA91C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9 (0x005EA920)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10 (0x005EA924)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11 (0x005EA928)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12 (0x005EA92C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13 (0x005EA930)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14 (0x005EA934)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15 (0x005EA938)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16 (0x005EA93C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17 (0x005EA940)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18 (0x005EA944)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19 (0x005EA948)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20 (0x005EA94C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21 (0x005EA950)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22 (0x005EA954)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23 (0x005EA958)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24 (0x005EA95C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25 (0x005EA960)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26 (0x005EA964)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27 (0x005EA968)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28 (0x005EA96C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29 (0x005EA970)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30 (0x005EA974)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31 (0x005EA978)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32 (0x005EA97C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33 (0x005EA980)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34 (0x005EA984)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35 (0x005EA988)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36 (0x005EA98C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG (0x005EA990)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE (0x005EA994)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE (0x005EA998)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0 (0x005EA99C)
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___S              27
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___M 0xCF00737F   
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1 (0x005EA9A0)
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___M 0x0000000D   
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0    (0x005EC000)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1    (0x005EC004)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2    (0x005EC008)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3    (0x005EC00C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4    (0x005EC010)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5    (0x005EC014)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6    (0x005EC018)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7    (0x005EC01C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8    (0x005EC020)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9    (0x005EC024)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10   (0x005EC028)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11   (0x005EC02C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12   (0x005EC030)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13   (0x005EC034)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14   (0x005EC038)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15   (0x005EC03C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16   (0x005EC040)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17   (0x005EC044)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18   (0x005EC048)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19   (0x005EC04C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20   (0x005EC050)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21   (0x005EC054)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22   (0x005EC058)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23   (0x005EC05C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24   (0x005EC060)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25   (0x005EC064)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26   (0x005EC068)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27   (0x005EC06C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28   (0x005EC070)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29   (0x005EC074)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30   (0x005EC078)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31   (0x005EC07C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32   (0x005EC080)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33   (0x005EC084)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34   (0x005EC088)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35   (0x005EC08C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36   (0x005EC090)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37   (0x005EC094)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38   (0x005EC098)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39   (0x005EC09C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40   (0x005EC0A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41   (0x005EC0A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42   (0x005EC0A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43   (0x005EC0AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44   (0x005EC0B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45   (0x005EC0B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46   (0x005EC0B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47   (0x005EC0BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48   (0x005EC0C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49   (0x005EC0C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50   (0x005EC0C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51   (0x005EC0CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52   (0x005EC0D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53   (0x005EC0D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54   (0x005EC0D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55   (0x005EC0DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56   (0x005EC0E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57   (0x005EC0E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58   (0x005EC0E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59   (0x005EC0EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60   (0x005EC0F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61   (0x005EC0F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62   (0x005EC0F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63   (0x005EC0FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64   (0x005EC100)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65   (0x005EC104)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66   (0x005EC108)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67   (0x005EC10C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68   (0x005EC110)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69   (0x005EC114)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70   (0x005EC118)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71   (0x005EC11C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72   (0x005EC120)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73   (0x005EC124)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74   (0x005EC128)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75   (0x005EC12C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76   (0x005EC130)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77   (0x005EC134)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78   (0x005EC138)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79   (0x005EC13C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80   (0x005EC140)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81   (0x005EC144)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82   (0x005EC148)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83   (0x005EC14C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84   (0x005EC150)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85   (0x005EC154)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86   (0x005EC158)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87   (0x005EC15C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88   (0x005EC160)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89   (0x005EC164)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90   (0x005EC168)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91   (0x005EC16C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92   (0x005EC170)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93   (0x005EC174)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94   (0x005EC178)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95   (0x005EC17C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96   (0x005EC180)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97   (0x005EC184)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98   (0x005EC188)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99   (0x005EC18C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100  (0x005EC190)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101  (0x005EC194)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102  (0x005EC198)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103  (0x005EC19C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104  (0x005EC1A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105  (0x005EC1A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106  (0x005EC1A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107  (0x005EC1AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108  (0x005EC1B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109  (0x005EC1B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110  (0x005EC1B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111  (0x005EC1BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112  (0x005EC1C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113  (0x005EC1C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114  (0x005EC1C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115  (0x005EC1CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116  (0x005EC1D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117  (0x005EC1D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118  (0x005EC1D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119  (0x005EC1DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120  (0x005EC1E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121  (0x005EC1E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122  (0x005EC1E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123  (0x005EC1EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124  (0x005EC1F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125  (0x005EC1F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126  (0x005EC1F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127  (0x005EC1FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128  (0x005EC200)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129  (0x005EC204)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130  (0x005EC208)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131  (0x005EC20C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132  (0x005EC210)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133  (0x005EC214)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134  (0x005EC218)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135  (0x005EC21C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136  (0x005EC220)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137  (0x005EC224)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138  (0x005EC228)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139  (0x005EC22C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140  (0x005EC230)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141  (0x005EC234)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142  (0x005EC238)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143  (0x005EC23C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144  (0x005EC240)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145  (0x005EC244)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146  (0x005EC248)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147  (0x005EC24C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148  (0x005EC250)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149  (0x005EC254)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150  (0x005EC258)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151  (0x005EC25C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152  (0x005EC260)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153  (0x005EC264)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154  (0x005EC268)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155  (0x005EC26C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156  (0x005EC270)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157  (0x005EC274)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158  (0x005EC278)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159  (0x005EC27C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160  (0x005EC280)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161  (0x005EC284)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162  (0x005EC288)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163  (0x005EC28C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164  (0x005EC290)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165  (0x005EC294)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166  (0x005EC298)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167  (0x005EC29C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168  (0x005EC2A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169  (0x005EC2A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170  (0x005EC2A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171  (0x005EC2AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172  (0x005EC2B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173  (0x005EC2B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174  (0x005EC2B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175  (0x005EC2BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176  (0x005EC2C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177  (0x005EC2C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178  (0x005EC2C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179  (0x005EC2CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180  (0x005EC2D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181  (0x005EC2D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182  (0x005EC2D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183  (0x005EC2DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184  (0x005EC2E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185  (0x005EC2E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186  (0x005EC2E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187  (0x005EC2EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188  (0x005EC2F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189  (0x005EC2F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190  (0x005EC2F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191  (0x005EC2FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192  (0x005EC300)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193  (0x005EC304)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194  (0x005EC308)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195  (0x005EC30C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196  (0x005EC310)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197  (0x005EC314)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198  (0x005EC318)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199  (0x005EC31C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200  (0x005EC320)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201  (0x005EC324)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202  (0x005EC328)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203  (0x005EC32C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204  (0x005EC330)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205  (0x005EC334)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206  (0x005EC338)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207  (0x005EC33C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208  (0x005EC340)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209  (0x005EC344)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210  (0x005EC348)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211  (0x005EC34C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212  (0x005EC350)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213  (0x005EC354)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214  (0x005EC358)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215  (0x005EC35C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216  (0x005EC360)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217  (0x005EC364)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218  (0x005EC368)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219  (0x005EC36C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220  (0x005EC370)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221  (0x005EC374)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222  (0x005EC378)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223  (0x005EC37C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224  (0x005EC380)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225  (0x005EC384)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226  (0x005EC388)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227  (0x005EC38C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228  (0x005EC390)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229  (0x005EC394)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230  (0x005EC398)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231  (0x005EC39C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232  (0x005EC3A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233  (0x005EC3A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234  (0x005EC3A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235  (0x005EC3AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236  (0x005EC3B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237  (0x005EC3B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238  (0x005EC3B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239  (0x005EC3BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240  (0x005EC3C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241  (0x005EC3C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242  (0x005EC3C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243  (0x005EC3CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244  (0x005EC3D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245  (0x005EC3D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246  (0x005EC3D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247  (0x005EC3DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248  (0x005EC3E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249  (0x005EC3E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250  (0x005EC3E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251  (0x005EC3EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252  (0x005EC3F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253  (0x005EC3F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254  (0x005EC3F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255  (0x005EC3FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256  (0x005EC400)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257  (0x005EC404)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258  (0x005EC408)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259  (0x005EC40C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260  (0x005EC410)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261  (0x005EC414)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262  (0x005EC418)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263  (0x005EC41C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264  (0x005EC420)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265  (0x005EC424)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266  (0x005EC428)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267  (0x005EC42C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268  (0x005EC430)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269  (0x005EC434)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270  (0x005EC438)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271  (0x005EC43C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272  (0x005EC440)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273  (0x005EC444)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274  (0x005EC448)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275  (0x005EC44C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276  (0x005EC450)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277  (0x005EC454)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278  (0x005EC458)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279  (0x005EC45C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280  (0x005EC460)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281  (0x005EC464)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282  (0x005EC468)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283  (0x005EC46C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284  (0x005EC470)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285  (0x005EC474)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286  (0x005EC478)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287  (0x005EC47C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288  (0x005EC480)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289  (0x005EC484)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290  (0x005EC488)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291  (0x005EC48C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292  (0x005EC490)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293  (0x005EC494)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294  (0x005EC498)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295  (0x005EC49C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296  (0x005EC4A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297  (0x005EC4A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298  (0x005EC4A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299  (0x005EC4AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300  (0x005EC4B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301  (0x005EC4B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302  (0x005EC4B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303  (0x005EC4BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304  (0x005EC4C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305  (0x005EC4C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306  (0x005EC4C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307  (0x005EC4CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308  (0x005EC4D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309  (0x005EC4D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310  (0x005EC4D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311  (0x005EC4DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312  (0x005EC4E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313  (0x005EC4E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314  (0x005EC4E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315  (0x005EC4EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316  (0x005EC4F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317  (0x005EC4F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318  (0x005EC4F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319  (0x005EC4FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320  (0x005EC500)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321  (0x005EC504)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322  (0x005EC508)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323  (0x005EC50C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324  (0x005EC510)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325  (0x005EC514)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326  (0x005EC518)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327  (0x005EC51C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328  (0x005EC520)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329  (0x005EC524)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330  (0x005EC528)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331  (0x005EC52C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332  (0x005EC530)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333  (0x005EC534)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334  (0x005EC538)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335  (0x005EC53C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336  (0x005EC540)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337  (0x005EC544)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338  (0x005EC548)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339  (0x005EC54C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340  (0x005EC550)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341  (0x005EC554)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342  (0x005EC558)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343  (0x005EC55C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344  (0x005EC560)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345  (0x005EC564)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346  (0x005EC568)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347  (0x005EC56C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348  (0x005EC570)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349  (0x005EC574)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350  (0x005EC578)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351  (0x005EC57C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352  (0x005EC580)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353  (0x005EC584)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354  (0x005EC588)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355  (0x005EC58C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356  (0x005EC590)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357  (0x005EC594)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358  (0x005EC598)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359  (0x005EC59C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360  (0x005EC5A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361  (0x005EC5A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362  (0x005EC5A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363  (0x005EC5AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364  (0x005EC5B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365  (0x005EC5B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366  (0x005EC5B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367  (0x005EC5BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368  (0x005EC5C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369  (0x005EC5C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370  (0x005EC5C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371  (0x005EC5CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372  (0x005EC5D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373  (0x005EC5D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374  (0x005EC5D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375  (0x005EC5DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376  (0x005EC5E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377  (0x005EC5E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378  (0x005EC5E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379  (0x005EC5EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380  (0x005EC5F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381  (0x005EC5F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382  (0x005EC5F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383  (0x005EC5FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384  (0x005EC600)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385  (0x005EC604)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386  (0x005EC608)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387  (0x005EC60C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388  (0x005EC610)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389  (0x005EC614)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390  (0x005EC618)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391  (0x005EC61C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392  (0x005EC620)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393  (0x005EC624)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394  (0x005EC628)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395  (0x005EC62C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396  (0x005EC630)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397  (0x005EC634)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398  (0x005EC638)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399  (0x005EC63C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400  (0x005EC640)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401  (0x005EC644)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402  (0x005EC648)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403  (0x005EC64C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404  (0x005EC650)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405  (0x005EC654)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406  (0x005EC658)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407  (0x005EC65C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408  (0x005EC660)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409  (0x005EC664)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410  (0x005EC668)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411  (0x005EC66C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412  (0x005EC670)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413  (0x005EC674)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414  (0x005EC678)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415  (0x005EC67C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416  (0x005EC680)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417  (0x005EC684)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418  (0x005EC688)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419  (0x005EC68C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420  (0x005EC690)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421  (0x005EC694)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422  (0x005EC698)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423  (0x005EC69C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424  (0x005EC6A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425  (0x005EC6A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426  (0x005EC6A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427  (0x005EC6AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428  (0x005EC6B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429  (0x005EC6B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430  (0x005EC6B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431  (0x005EC6BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432  (0x005EC6C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433  (0x005EC6C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434  (0x005EC6C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435  (0x005EC6CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436  (0x005EC6D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437  (0x005EC6D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438  (0x005EC6D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439  (0x005EC6DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440  (0x005EC6E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441  (0x005EC6E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442  (0x005EC6E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443  (0x005EC6EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444  (0x005EC6F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445  (0x005EC6F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446  (0x005EC6F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447  (0x005EC6FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448  (0x005EC700)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449  (0x005EC704)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450  (0x005EC708)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451  (0x005EC70C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452  (0x005EC710)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453  (0x005EC714)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454  (0x005EC718)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455  (0x005EC71C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456  (0x005EC720)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457  (0x005EC724)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458  (0x005EC728)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459  (0x005EC72C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460  (0x005EC730)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461  (0x005EC734)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462  (0x005EC738)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463  (0x005EC73C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464  (0x005EC740)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465  (0x005EC744)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466  (0x005EC748)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467  (0x005EC74C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468  (0x005EC750)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469  (0x005EC754)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470  (0x005EC758)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471  (0x005EC75C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472  (0x005EC760)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473  (0x005EC764)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474  (0x005EC768)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475  (0x005EC76C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476  (0x005EC770)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477  (0x005EC774)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478  (0x005EC778)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479  (0x005EC77C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480  (0x005EC780)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481  (0x005EC784)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482  (0x005EC788)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483  (0x005EC78C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484  (0x005EC790)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485  (0x005EC794)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486  (0x005EC798)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487  (0x005EC79C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488  (0x005EC7A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489  (0x005EC7A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490  (0x005EC7A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491  (0x005EC7AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492  (0x005EC7B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493  (0x005EC7B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494  (0x005EC7B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495  (0x005EC7BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496  (0x005EC7C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497  (0x005EC7C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498  (0x005EC7C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499  (0x005EC7CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500  (0x005EC7D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501  (0x005EC7D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502  (0x005EC7D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503  (0x005EC7DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504  (0x005EC7E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505  (0x005EC7E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506  (0x005EC7E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507  (0x005EC7EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508  (0x005EC7F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509  (0x005EC7F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510  (0x005EC7F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511  (0x005EC7FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512  (0x005EC800)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513  (0x005EC804)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514  (0x005EC808)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515  (0x005EC80C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516  (0x005EC810)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517  (0x005EC814)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518  (0x005EC818)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519  (0x005EC81C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520  (0x005EC820)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521  (0x005EC824)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522  (0x005EC828)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523  (0x005EC82C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524  (0x005EC830)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525  (0x005EC834)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526  (0x005EC838)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527  (0x005EC83C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528  (0x005EC840)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529  (0x005EC844)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530  (0x005EC848)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531  (0x005EC84C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532  (0x005EC850)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533  (0x005EC854)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534  (0x005EC858)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535  (0x005EC85C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536  (0x005EC860)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537  (0x005EC864)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538  (0x005EC868)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539  (0x005EC86C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540  (0x005EC870)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541  (0x005EC874)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542  (0x005EC878)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543  (0x005EC87C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544  (0x005EC880)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545  (0x005EC884)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546  (0x005EC888)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547  (0x005EC88C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548  (0x005EC890)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549  (0x005EC894)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550  (0x005EC898)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551  (0x005EC89C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552  (0x005EC8A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553  (0x005EC8A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554  (0x005EC8A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555  (0x005EC8AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556  (0x005EC8B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557  (0x005EC8B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558  (0x005EC8B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559  (0x005EC8BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560  (0x005EC8C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561  (0x005EC8C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562  (0x005EC8C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563  (0x005EC8CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564  (0x005EC8D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565  (0x005EC8D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566  (0x005EC8D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567  (0x005EC8DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568  (0x005EC8E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569  (0x005EC8E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570  (0x005EC8E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571  (0x005EC8EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572  (0x005EC8F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573  (0x005EC8F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574  (0x005EC8F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575  (0x005EC8FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576  (0x005EC900)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577  (0x005EC904)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578  (0x005EC908)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579  (0x005EC90C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580  (0x005EC910)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581  (0x005EC914)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582  (0x005EC918)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583  (0x005EC91C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584  (0x005EC920)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585  (0x005EC924)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586  (0x005EC928)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587  (0x005EC92C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588  (0x005EC930)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589  (0x005EC934)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590  (0x005EC938)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591  (0x005EC93C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592  (0x005EC940)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593  (0x005EC944)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594  (0x005EC948)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595  (0x005EC94C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596  (0x005EC950)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597  (0x005EC954)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598  (0x005EC958)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599  (0x005EC95C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600  (0x005EC960)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601  (0x005EC964)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602  (0x005EC968)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603  (0x005EC96C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604  (0x005EC970)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605  (0x005EC974)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606  (0x005EC978)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607  (0x005EC97C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608  (0x005EC980)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609  (0x005EC984)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610  (0x005EC988)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611  (0x005EC98C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612  (0x005EC990)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613  (0x005EC994)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614  (0x005EC998)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615  (0x005EC99C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616  (0x005EC9A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617  (0x005EC9A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618  (0x005EC9A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619  (0x005EC9AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620  (0x005EC9B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621  (0x005EC9B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622  (0x005EC9B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623  (0x005EC9BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624  (0x005EC9C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625  (0x005EC9C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626  (0x005EC9C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627  (0x005EC9CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628  (0x005EC9D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629  (0x005EC9D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630  (0x005EC9D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631  (0x005EC9DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632  (0x005EC9E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633  (0x005EC9E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634  (0x005EC9E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635  (0x005EC9EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636  (0x005EC9F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637  (0x005EC9F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638  (0x005EC9F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639  (0x005EC9FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640  (0x005ECA00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641  (0x005ECA04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642  (0x005ECA08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643  (0x005ECA0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644  (0x005ECA10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645  (0x005ECA14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646  (0x005ECA18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647  (0x005ECA1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648  (0x005ECA20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649  (0x005ECA24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650  (0x005ECA28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651  (0x005ECA2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652  (0x005ECA30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653  (0x005ECA34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654  (0x005ECA38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655  (0x005ECA3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656  (0x005ECA40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657  (0x005ECA44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658  (0x005ECA48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659  (0x005ECA4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660  (0x005ECA50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661  (0x005ECA54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662  (0x005ECA58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663  (0x005ECA5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664  (0x005ECA60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665  (0x005ECA64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666  (0x005ECA68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667  (0x005ECA6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668  (0x005ECA70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669  (0x005ECA74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670  (0x005ECA78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671  (0x005ECA7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672  (0x005ECA80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673  (0x005ECA84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674  (0x005ECA88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675  (0x005ECA8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676  (0x005ECA90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677  (0x005ECA94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678  (0x005ECA98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679  (0x005ECA9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680  (0x005ECAA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681  (0x005ECAA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682  (0x005ECAA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683  (0x005ECAAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684  (0x005ECAB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685  (0x005ECAB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686  (0x005ECAB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687  (0x005ECABC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688  (0x005ECAC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689  (0x005ECAC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690  (0x005ECAC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691  (0x005ECACC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692  (0x005ECAD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693  (0x005ECAD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694  (0x005ECAD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695  (0x005ECADC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696  (0x005ECAE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697  (0x005ECAE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698  (0x005ECAE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699  (0x005ECAEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700  (0x005ECAF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701  (0x005ECAF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702  (0x005ECAF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703  (0x005ECAFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704  (0x005ECB00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705  (0x005ECB04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706  (0x005ECB08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707  (0x005ECB0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708  (0x005ECB10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709  (0x005ECB14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710  (0x005ECB18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711  (0x005ECB1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712  (0x005ECB20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713  (0x005ECB24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714  (0x005ECB28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715  (0x005ECB2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716  (0x005ECB30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717  (0x005ECB34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718  (0x005ECB38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719  (0x005ECB3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720  (0x005ECB40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721  (0x005ECB44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722  (0x005ECB48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723  (0x005ECB4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724  (0x005ECB50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725  (0x005ECB54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726  (0x005ECB58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727  (0x005ECB5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728  (0x005ECB60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729  (0x005ECB64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730  (0x005ECB68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731  (0x005ECB6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732  (0x005ECB70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733  (0x005ECB74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734  (0x005ECB78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735  (0x005ECB7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736  (0x005ECB80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737  (0x005ECB84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738  (0x005ECB88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739  (0x005ECB8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740  (0x005ECB90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741  (0x005ECB94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742  (0x005ECB98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743  (0x005ECB9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744  (0x005ECBA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745  (0x005ECBA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746  (0x005ECBA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747  (0x005ECBAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748  (0x005ECBB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749  (0x005ECBB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750  (0x005ECBB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751  (0x005ECBBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752  (0x005ECBC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753  (0x005ECBC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754  (0x005ECBC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755  (0x005ECBCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756  (0x005ECBD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757  (0x005ECBD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758  (0x005ECBD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759  (0x005ECBDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760  (0x005ECBE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761  (0x005ECBE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762  (0x005ECBE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763  (0x005ECBEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764  (0x005ECBF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765  (0x005ECBF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766  (0x005ECBF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767  (0x005ECBFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768  (0x005ECC00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769  (0x005ECC04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770  (0x005ECC08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771  (0x005ECC0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772  (0x005ECC10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773  (0x005ECC14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774  (0x005ECC18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775  (0x005ECC1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776  (0x005ECC20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777  (0x005ECC24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778  (0x005ECC28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779  (0x005ECC2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780  (0x005ECC30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781  (0x005ECC34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782  (0x005ECC38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783  (0x005ECC3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784  (0x005ECC40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785  (0x005ECC44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786  (0x005ECC48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787  (0x005ECC4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788  (0x005ECC50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789  (0x005ECC54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790  (0x005ECC58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791  (0x005ECC5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792  (0x005ECC60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793  (0x005ECC64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794  (0x005ECC68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795  (0x005ECC6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796  (0x005ECC70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797  (0x005ECC74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798  (0x005ECC78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799  (0x005ECC7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800  (0x005ECC80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801  (0x005ECC84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802  (0x005ECC88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803  (0x005ECC8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804  (0x005ECC90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805  (0x005ECC94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806  (0x005ECC98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807  (0x005ECC9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808  (0x005ECCA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809  (0x005ECCA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810  (0x005ECCA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811  (0x005ECCAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812  (0x005ECCB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813  (0x005ECCB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814  (0x005ECCB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815  (0x005ECCBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816  (0x005ECCC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817  (0x005ECCC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818  (0x005ECCC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819  (0x005ECCCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820  (0x005ECCD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821  (0x005ECCD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822  (0x005ECCD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823  (0x005ECCDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824  (0x005ECCE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825  (0x005ECCE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826  (0x005ECCE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827  (0x005ECCEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828  (0x005ECCF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829  (0x005ECCF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830  (0x005ECCF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831  (0x005ECCFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832  (0x005ECD00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833  (0x005ECD04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834  (0x005ECD08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835  (0x005ECD0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836  (0x005ECD10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837  (0x005ECD14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838  (0x005ECD18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839  (0x005ECD1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840  (0x005ECD20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841  (0x005ECD24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842  (0x005ECD28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843  (0x005ECD2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844  (0x005ECD30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845  (0x005ECD34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846  (0x005ECD38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847  (0x005ECD3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848  (0x005ECD40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849  (0x005ECD44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850  (0x005ECD48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851  (0x005ECD4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852  (0x005ECD50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853  (0x005ECD54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854  (0x005ECD58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855  (0x005ECD5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856  (0x005ECD60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857  (0x005ECD64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858  (0x005ECD68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859  (0x005ECD6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860  (0x005ECD70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861  (0x005ECD74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862  (0x005ECD78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863  (0x005ECD7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864  (0x005ECD80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865  (0x005ECD84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866  (0x005ECD88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867  (0x005ECD8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868  (0x005ECD90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869  (0x005ECD94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870  (0x005ECD98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871  (0x005ECD9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872  (0x005ECDA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873  (0x005ECDA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874  (0x005ECDA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875  (0x005ECDAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876  (0x005ECDB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877  (0x005ECDB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878  (0x005ECDB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879  (0x005ECDBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880  (0x005ECDC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881  (0x005ECDC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882  (0x005ECDC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883  (0x005ECDCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884  (0x005ECDD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885  (0x005ECDD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886  (0x005ECDD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887  (0x005ECDDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888  (0x005ECDE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889  (0x005ECDE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890  (0x005ECDE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891  (0x005ECDEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892  (0x005ECDF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893  (0x005ECDF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894  (0x005ECDF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895  (0x005ECDFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896  (0x005ECE00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897  (0x005ECE04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898  (0x005ECE08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899  (0x005ECE0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900  (0x005ECE10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901  (0x005ECE14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902  (0x005ECE18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903  (0x005ECE1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904  (0x005ECE20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905  (0x005ECE24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906  (0x005ECE28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907  (0x005ECE2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908  (0x005ECE30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909  (0x005ECE34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910  (0x005ECE38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911  (0x005ECE3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912  (0x005ECE40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913  (0x005ECE44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914  (0x005ECE48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915  (0x005ECE4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916  (0x005ECE50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917  (0x005ECE54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918  (0x005ECE58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919  (0x005ECE5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920  (0x005ECE60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921  (0x005ECE64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922  (0x005ECE68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923  (0x005ECE6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924  (0x005ECE70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925  (0x005ECE74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926  (0x005ECE78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927  (0x005ECE7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928  (0x005ECE80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929  (0x005ECE84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930  (0x005ECE88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931  (0x005ECE8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932  (0x005ECE90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933  (0x005ECE94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934  (0x005ECE98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935  (0x005ECE9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936  (0x005ECEA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937  (0x005ECEA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938  (0x005ECEA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939  (0x005ECEAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940  (0x005ECEB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941  (0x005ECEB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942  (0x005ECEB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943  (0x005ECEBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944  (0x005ECEC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945  (0x005ECEC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946  (0x005ECEC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947  (0x005ECECC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948  (0x005ECED0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949  (0x005ECED4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950  (0x005ECED8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951  (0x005ECEDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952  (0x005ECEE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953  (0x005ECEE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954  (0x005ECEE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955  (0x005ECEEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956  (0x005ECEF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957  (0x005ECEF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958  (0x005ECEF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959  (0x005ECEFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960  (0x005ECF00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961  (0x005ECF04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962  (0x005ECF08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963  (0x005ECF0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964  (0x005ECF10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965  (0x005ECF14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966  (0x005ECF18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967  (0x005ECF1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968  (0x005ECF20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969  (0x005ECF24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970  (0x005ECF28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971  (0x005ECF2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972  (0x005ECF30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973  (0x005ECF34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974  (0x005ECF38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975  (0x005ECF3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976  (0x005ECF40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977  (0x005ECF44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978  (0x005ECF48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979  (0x005ECF4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980  (0x005ECF50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981  (0x005ECF54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982  (0x005ECF58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983  (0x005ECF5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984  (0x005ECF60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985  (0x005ECF64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986  (0x005ECF68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987  (0x005ECF6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988  (0x005ECF70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989  (0x005ECF74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990  (0x005ECF78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991  (0x005ECF7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992  (0x005ECF80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993  (0x005ECF84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994  (0x005ECF88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995  (0x005ECF8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996  (0x005ECF90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997  (0x005ECF94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998  (0x005ECF98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999  (0x005ECF9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000 (0x005ECFA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001 (0x005ECFA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002 (0x005ECFA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003 (0x005ECFAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004 (0x005ECFB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005 (0x005ECFB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006 (0x005ECFB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007 (0x005ECFBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008 (0x005ECFC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009 (0x005ECFC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010 (0x005ECFC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011 (0x005ECFCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012 (0x005ECFD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013 (0x005ECFD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014 (0x005ECFD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015 (0x005ECFDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016 (0x005ECFE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017 (0x005ECFE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018 (0x005ECFE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019 (0x005ECFEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020 (0x005ECFF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021 (0x005ECFF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022 (0x005ECFF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023 (0x005ECFFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0    (0x005ED000)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1    (0x005ED004)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2    (0x005ED008)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3    (0x005ED00C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4    (0x005ED010)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5    (0x005ED014)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6    (0x005ED018)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7    (0x005ED01C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8    (0x005ED020)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9    (0x005ED024)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10   (0x005ED028)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11   (0x005ED02C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12   (0x005ED030)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13   (0x005ED034)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14   (0x005ED038)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15   (0x005ED03C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16   (0x005ED040)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17   (0x005ED044)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18   (0x005ED048)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19   (0x005ED04C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20   (0x005ED050)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21   (0x005ED054)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22   (0x005ED058)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23   (0x005ED05C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24   (0x005ED060)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25   (0x005ED064)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26   (0x005ED068)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27   (0x005ED06C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28   (0x005ED070)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29   (0x005ED074)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30   (0x005ED078)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31   (0x005ED07C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32   (0x005ED080)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33   (0x005ED084)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34   (0x005ED088)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35   (0x005ED08C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36   (0x005ED090)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37   (0x005ED094)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38   (0x005ED098)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39   (0x005ED09C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40   (0x005ED0A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41   (0x005ED0A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42   (0x005ED0A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43   (0x005ED0AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44   (0x005ED0B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45   (0x005ED0B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46   (0x005ED0B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47   (0x005ED0BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48   (0x005ED0C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49   (0x005ED0C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50   (0x005ED0C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51   (0x005ED0CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52   (0x005ED0D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53   (0x005ED0D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54   (0x005ED0D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55   (0x005ED0DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56   (0x005ED0E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57   (0x005ED0E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58   (0x005ED0E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59   (0x005ED0EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60   (0x005ED0F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61   (0x005ED0F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62   (0x005ED0F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63   (0x005ED0FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64   (0x005ED100)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65   (0x005ED104)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66   (0x005ED108)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67   (0x005ED10C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68   (0x005ED110)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69   (0x005ED114)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70   (0x005ED118)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71   (0x005ED11C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72   (0x005ED120)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73   (0x005ED124)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74   (0x005ED128)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75   (0x005ED12C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76   (0x005ED130)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77   (0x005ED134)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78   (0x005ED138)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79   (0x005ED13C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80   (0x005ED140)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81   (0x005ED144)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82   (0x005ED148)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83   (0x005ED14C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84   (0x005ED150)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85   (0x005ED154)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86   (0x005ED158)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87   (0x005ED15C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88   (0x005ED160)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89   (0x005ED164)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90   (0x005ED168)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91   (0x005ED16C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92   (0x005ED170)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93   (0x005ED174)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94   (0x005ED178)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95   (0x005ED17C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96   (0x005ED180)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97   (0x005ED184)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98   (0x005ED188)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99   (0x005ED18C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100  (0x005ED190)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101  (0x005ED194)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102  (0x005ED198)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103  (0x005ED19C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104  (0x005ED1A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105  (0x005ED1A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106  (0x005ED1A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107  (0x005ED1AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108  (0x005ED1B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109  (0x005ED1B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110  (0x005ED1B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111  (0x005ED1BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112  (0x005ED1C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113  (0x005ED1C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114  (0x005ED1C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115  (0x005ED1CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116  (0x005ED1D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117  (0x005ED1D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118  (0x005ED1D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119  (0x005ED1DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120  (0x005ED1E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121  (0x005ED1E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122  (0x005ED1E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123  (0x005ED1EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124  (0x005ED1F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125  (0x005ED1F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126  (0x005ED1F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127  (0x005ED1FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128  (0x005ED200)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129  (0x005ED204)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130  (0x005ED208)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131  (0x005ED20C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132  (0x005ED210)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133  (0x005ED214)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134  (0x005ED218)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135  (0x005ED21C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136  (0x005ED220)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137  (0x005ED224)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138  (0x005ED228)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139  (0x005ED22C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140  (0x005ED230)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141  (0x005ED234)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142  (0x005ED238)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143  (0x005ED23C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144  (0x005ED240)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145  (0x005ED244)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146  (0x005ED248)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147  (0x005ED24C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148  (0x005ED250)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149  (0x005ED254)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150  (0x005ED258)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151  (0x005ED25C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152  (0x005ED260)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153  (0x005ED264)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154  (0x005ED268)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155  (0x005ED26C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156  (0x005ED270)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157  (0x005ED274)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158  (0x005ED278)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159  (0x005ED27C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160  (0x005ED280)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161  (0x005ED284)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162  (0x005ED288)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163  (0x005ED28C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164  (0x005ED290)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165  (0x005ED294)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166  (0x005ED298)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167  (0x005ED29C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168  (0x005ED2A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169  (0x005ED2A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170  (0x005ED2A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171  (0x005ED2AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172  (0x005ED2B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173  (0x005ED2B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174  (0x005ED2B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175  (0x005ED2BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176  (0x005ED2C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177  (0x005ED2C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178  (0x005ED2C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179  (0x005ED2CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180  (0x005ED2D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181  (0x005ED2D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182  (0x005ED2D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183  (0x005ED2DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184  (0x005ED2E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185  (0x005ED2E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186  (0x005ED2E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187  (0x005ED2EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188  (0x005ED2F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189  (0x005ED2F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190  (0x005ED2F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191  (0x005ED2FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192  (0x005ED300)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193  (0x005ED304)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194  (0x005ED308)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195  (0x005ED30C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196  (0x005ED310)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197  (0x005ED314)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198  (0x005ED318)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199  (0x005ED31C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200  (0x005ED320)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201  (0x005ED324)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202  (0x005ED328)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203  (0x005ED32C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204  (0x005ED330)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205  (0x005ED334)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206  (0x005ED338)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207  (0x005ED33C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208  (0x005ED340)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209  (0x005ED344)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210  (0x005ED348)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211  (0x005ED34C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212  (0x005ED350)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213  (0x005ED354)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214  (0x005ED358)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215  (0x005ED35C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216  (0x005ED360)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217  (0x005ED364)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218  (0x005ED368)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219  (0x005ED36C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220  (0x005ED370)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221  (0x005ED374)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222  (0x005ED378)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223  (0x005ED37C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224  (0x005ED380)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225  (0x005ED384)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226  (0x005ED388)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227  (0x005ED38C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228  (0x005ED390)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229  (0x005ED394)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230  (0x005ED398)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231  (0x005ED39C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232  (0x005ED3A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233  (0x005ED3A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234  (0x005ED3A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235  (0x005ED3AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236  (0x005ED3B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237  (0x005ED3B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238  (0x005ED3B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239  (0x005ED3BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240  (0x005ED3C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241  (0x005ED3C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242  (0x005ED3C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243  (0x005ED3CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244  (0x005ED3D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245  (0x005ED3D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246  (0x005ED3D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247  (0x005ED3DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248  (0x005ED3E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249  (0x005ED3E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250  (0x005ED3E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251  (0x005ED3EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252  (0x005ED3F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253  (0x005ED3F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254  (0x005ED3F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255  (0x005ED3FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0    (0x005ED800)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1    (0x005ED804)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2    (0x005ED808)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3    (0x005ED80C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4    (0x005ED810)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5    (0x005ED814)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6    (0x005ED818)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7    (0x005ED81C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8    (0x005ED820)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9    (0x005ED824)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10   (0x005ED828)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11   (0x005ED82C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12   (0x005ED830)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13   (0x005ED834)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14   (0x005ED838)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15   (0x005ED83C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16   (0x005ED840)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17   (0x005ED844)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18   (0x005ED848)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19   (0x005ED84C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20   (0x005ED850)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21   (0x005ED854)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22   (0x005ED858)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23   (0x005ED85C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24   (0x005ED860)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25   (0x005ED864)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26   (0x005ED868)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27   (0x005ED86C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28   (0x005ED870)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29   (0x005ED874)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30   (0x005ED878)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31   (0x005ED87C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32   (0x005ED880)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33   (0x005ED884)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34   (0x005ED888)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35   (0x005ED88C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36   (0x005ED890)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37   (0x005ED894)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38   (0x005ED898)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39   (0x005ED89C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40   (0x005ED8A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41   (0x005ED8A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42   (0x005ED8A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43   (0x005ED8AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44   (0x005ED8B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45   (0x005ED8B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46   (0x005ED8B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47   (0x005ED8BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48   (0x005ED8C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49   (0x005ED8C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50   (0x005ED8C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51   (0x005ED8CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52   (0x005ED8D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53   (0x005ED8D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54   (0x005ED8D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55   (0x005ED8DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56   (0x005ED8E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57   (0x005ED8E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58   (0x005ED8E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59   (0x005ED8EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60   (0x005ED8F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61   (0x005ED8F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62   (0x005ED8F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63   (0x005ED8FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64   (0x005ED900)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65   (0x005ED904)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66   (0x005ED908)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67   (0x005ED90C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68   (0x005ED910)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69   (0x005ED914)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70   (0x005ED918)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71   (0x005ED91C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72   (0x005ED920)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73   (0x005ED924)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74   (0x005ED928)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75   (0x005ED92C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76   (0x005ED930)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77   (0x005ED934)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78   (0x005ED938)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79   (0x005ED93C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80   (0x005ED940)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81   (0x005ED944)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82   (0x005ED948)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83   (0x005ED94C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84   (0x005ED950)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85   (0x005ED954)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86   (0x005ED958)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87   (0x005ED95C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88   (0x005ED960)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89   (0x005ED964)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90   (0x005ED968)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91   (0x005ED96C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92   (0x005ED970)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93   (0x005ED974)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94   (0x005ED978)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95   (0x005ED97C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96   (0x005ED980)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97   (0x005ED984)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98   (0x005ED988)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99   (0x005ED98C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100  (0x005ED990)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101  (0x005ED994)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102  (0x005ED998)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103  (0x005ED99C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104  (0x005ED9A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105  (0x005ED9A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106  (0x005ED9A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107  (0x005ED9AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108  (0x005ED9B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109  (0x005ED9B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110  (0x005ED9B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111  (0x005ED9BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112  (0x005ED9C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113  (0x005ED9C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114  (0x005ED9C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115  (0x005ED9CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116  (0x005ED9D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117  (0x005ED9D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118  (0x005ED9D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119  (0x005ED9DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120  (0x005ED9E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121  (0x005ED9E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122  (0x005ED9E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123  (0x005ED9EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124  (0x005ED9F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125  (0x005ED9F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126  (0x005ED9F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127  (0x005ED9FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0    (0x005EDC00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1    (0x005EDC04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2    (0x005EDC08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3    (0x005EDC0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4    (0x005EDC10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5    (0x005EDC14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6    (0x005EDC18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7    (0x005EDC1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8    (0x005EDC20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9    (0x005EDC24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10   (0x005EDC28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11   (0x005EDC2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12   (0x005EDC30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13   (0x005EDC34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14   (0x005EDC38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15   (0x005EDC3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16   (0x005EDC40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17   (0x005EDC44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18   (0x005EDC48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19   (0x005EDC4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20   (0x005EDC50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21   (0x005EDC54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22   (0x005EDC58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23   (0x005EDC5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24   (0x005EDC60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25   (0x005EDC64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26   (0x005EDC68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27   (0x005EDC6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28   (0x005EDC70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29   (0x005EDC74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30   (0x005EDC78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31   (0x005EDC7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32   (0x005EDC80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33   (0x005EDC84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34   (0x005EDC88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35   (0x005EDC8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36   (0x005EDC90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37   (0x005EDC94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38   (0x005EDC98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39   (0x005EDC9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40   (0x005EDCA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41   (0x005EDCA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42   (0x005EDCA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43   (0x005EDCAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44   (0x005EDCB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45   (0x005EDCB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46   (0x005EDCB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47   (0x005EDCBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48   (0x005EDCC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49   (0x005EDCC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50   (0x005EDCC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51   (0x005EDCCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52   (0x005EDCD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53   (0x005EDCD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54   (0x005EDCD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55   (0x005EDCDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56   (0x005EDCE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57   (0x005EDCE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58   (0x005EDCE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59   (0x005EDCEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60   (0x005EDCF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61   (0x005EDCF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62   (0x005EDCF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63   (0x005EDCFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64   (0x005EDD00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65   (0x005EDD04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66   (0x005EDD08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67   (0x005EDD0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68   (0x005EDD10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69   (0x005EDD14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70   (0x005EDD18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71   (0x005EDD1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72   (0x005EDD20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73   (0x005EDD24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74   (0x005EDD28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75   (0x005EDD2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76   (0x005EDD30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77   (0x005EDD34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78   (0x005EDD38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79   (0x005EDD3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80   (0x005EDD40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81   (0x005EDD44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82   (0x005EDD48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83   (0x005EDD4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84   (0x005EDD50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85   (0x005EDD54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86   (0x005EDD58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87   (0x005EDD5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88   (0x005EDD60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89   (0x005EDD64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90   (0x005EDD68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91   (0x005EDD6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92   (0x005EDD70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93   (0x005EDD74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94   (0x005EDD78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95   (0x005EDD7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96   (0x005EDD80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97   (0x005EDD84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98   (0x005EDD88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99   (0x005EDD8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100  (0x005EDD90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101  (0x005EDD94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102  (0x005EDD98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103  (0x005EDD9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104  (0x005EDDA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105  (0x005EDDA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106  (0x005EDDA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107  (0x005EDDAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108  (0x005EDDB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109  (0x005EDDB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110  (0x005EDDB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111  (0x005EDDBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112  (0x005EDDC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113  (0x005EDDC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114  (0x005EDDC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115  (0x005EDDCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116  (0x005EDDD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117  (0x005EDDD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118  (0x005EDDD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119  (0x005EDDDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120  (0x005EDDE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121  (0x005EDDE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122  (0x005EDDE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123  (0x005EDDEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124  (0x005EDDF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125  (0x005EDDF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126  (0x005EDDF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127  (0x005EDDFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG   (0x005F0000)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0        (0x005F0004)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1        (0x005F0008)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___S               6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0   (0x005F000C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1   (0x005F0010)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2   (0x005F0014)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___POR 0x0000C001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S              14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S              13
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S              11
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S              10
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___M 0xC000FF01   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0      (0x005F0018)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___M 0xFECC0000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0      (0x005F001C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___M 0xFEDC0000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET     (0x005F0020)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0 (0x005F0024)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___POR 0x06769292
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0 (0x005F0028)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___POR 0x00004142
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0   (0x005F002C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___S              29
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___S              29

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0       (0x005F0030)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0   (0x005F0034)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1   (0x005F0038)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG (0x005F003C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2        (0x005F0040)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0    (0x005F0044)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___POR 0x09200000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___M 0x0FF80007   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST    (0x005F0048)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0 (0x005F0080)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___POR 0x005078A0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1 (0x005F0084)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___POR 0xC8F00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___M 0xFFFF03FF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL (0x005F0088)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___M 0x0000C000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___S              14

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0 (0x005F008C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1 (0x005F0090)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___M 0x0000FFBF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0 (0x005F0094)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S              25
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0 (0x005F0098)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1 (0x005F009C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0 (0x005F00A0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___M 0x000C3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0        (0x005F00A4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___S              30

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC   (0x005F00A8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC   (0x005F00AC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___M 0x007F3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN   (0x005F00B0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___S              15
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___S               7
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___M 0x00FFFFBF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0 (0x005F00B4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S              23
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S              19
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S              18
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S               4
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1 (0x005F00B8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___S              16
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___S               8
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___M 0x7FFF3F00   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___S               8

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0        (0x005F00C0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1        (0x005F00C4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2        (0x005F00C8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3        (0x005F00CC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4        (0x005F00D0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5        (0x005F00D4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6        (0x005F00D8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7        (0x005F00DC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8        (0x005F00E0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9        (0x005F00E4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10       (0x005F00E8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11       (0x005F00EC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12       (0x005F00F0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13       (0x005F00F4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14       (0x005F00F8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15       (0x005F00FC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16       (0x005F0100)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17       (0x005F0104)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18       (0x005F0108)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19       (0x005F010C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20       (0x005F0110)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21       (0x005F0114)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22       (0x005F0118)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23       (0x005F011C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24       (0x005F0120)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25       (0x005F0124)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26       (0x005F0128)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27       (0x005F012C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28       (0x005F0130)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29       (0x005F0134)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30       (0x005F0138)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31       (0x005F013C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32       (0x005F0140)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33       (0x005F0144)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34       (0x005F0148)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35       (0x005F014C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36       (0x005F0150)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37       (0x005F0154)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38       (0x005F0158)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39       (0x005F015C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40       (0x005F0160)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41       (0x005F0164)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42       (0x005F0168)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43       (0x005F016C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44       (0x005F0170)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45       (0x005F0174)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46       (0x005F0178)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47       (0x005F017C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48       (0x005F0180)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49       (0x005F0184)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50       (0x005F0188)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51       (0x005F018C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52       (0x005F0190)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53       (0x005F0194)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54       (0x005F0198)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55       (0x005F019C)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56       (0x005F01A0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57       (0x005F01A4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58       (0x005F01A8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59       (0x005F01AC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60       (0x005F01B0)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61       (0x005F01B4)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62       (0x005F01B8)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___S              26

#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63       (0x005F01BC)
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___S              26
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___S              26

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG    (0x005F1000)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___POR 0x44FE2111
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___POR 0x44FE2111
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL (0x005F1004)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___S              22

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0 (0x005F1008)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1 (0x005F100C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0 (0x005F1010)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___POR 0x60A25480
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1 (0x005F1014)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___POR 0x60E24480
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2 (0x005F1018)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___POR 0x601E030A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3 (0x005F101C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___POR 0x60022304
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4 (0x005F1020)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___POR 0x60022309
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5 (0x005F1024)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___POR 0x60022312
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6 (0x005F1028)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___POR 0x4002231C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7 (0x005F102C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___POR 0x00026339
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0 (0x005F1030)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1 (0x005F1034)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2 (0x005F1038)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___POR 0x14520000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3 (0x005F103C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___POR 0x1E7A0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4 (0x005F1040)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___POR 0x28930000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5 (0x005F1044)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___POR 0x3CC20000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___POR 0x1E
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6 (0x005F1048)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7 (0x005F104C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0    (0x005F1080)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___M 0x00000780
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___M 0xF07FFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT (0x005F1084)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___S              21

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1    (0x005F1088)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2    (0x005F108C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___S              28

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0 (0x005F1090)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___S               8

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1 (0x005F1094)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___M 0xFFF00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___S              20

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL (0x005F1098)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___S              25

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0 (0x005F109C)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___M 0xE1FFFFBF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1 (0x005F10A0)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2 (0x005F10A4)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___S              29

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0  (0x005F10A8)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___POR 0xA201E000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___M 0xE7FFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL (0x005F10AC)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0 (0x005F10B0)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___POR 0x7011C800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___M 0xF87FF800   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___S              11

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1 (0x005F10B4)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___POR 0x52000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___S              21

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2 (0x005F10B8)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___POR 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___S               3
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___M 0xFFFFFFB8   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___S               3

#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE (0x005F10BC)
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___M 0x0003FF00
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___M 0x000000FE
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___S               1
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___M 0x0003FFFE   
#define   PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG    (0x005F1300)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___POR 0x33FE2111
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___POR 0x33FE2111
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL (0x005F1304)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00078000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___S              15

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0 (0x005F1308)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___POR 0x14500000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1 (0x005F130C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___POR 0x14500000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0 (0x005F1310)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1 (0x005F1314)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2 (0x005F1318)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3 (0x005F131C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4 (0x005F1320)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5 (0x005F1324)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6 (0x005F1328)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___POR 0x04811000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x009
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7 (0x005F132C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___POR 0x05811000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x00B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8 (0x005F1330)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___POR 0x06011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x00C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9 (0x005F1334)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___POR 0x09011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x012
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10 (0x005F1338)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___POR 0x0A011000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x014
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11 (0x005F133C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___POR 0x0B019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x016
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12 (0x005F1340)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___POR 0x0C019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x018
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13 (0x005F1344)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___POR 0x0D019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x01A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14 (0x005F1348)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___POR 0x13019000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x026
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15 (0x005F134C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___POR 0x14021000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x028
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16 (0x005F1350)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___POR 0x15031000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x02A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17 (0x005F1354)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___POR 0x19051000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x032
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18 (0x005F1358)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___POR 0x1B061000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x036
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19 (0x005F135C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___POR 0x1D861000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x03B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20 (0x005F1360)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___POR 0x25071000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x04A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21 (0x005F1364)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___POR 0x2A079000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x054
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22 (0x005F1368)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___POR 0x2D091000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x05A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23 (0x005F136C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___POR 0x358C1000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x06B
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24 (0x005F1370)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___POR 0x3C0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x078
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25 (0x005F1374)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___POR 0x44951000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x089
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x2A
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26 (0x005F1378)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___POR 0x50199000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x0A0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x33
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27 (0x005F137C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___POR 0x569F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x0AD
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28 (0x005F1380)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___POR 0x641F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0C8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29 (0x005F1384)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___POR 0x6E1F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0DC
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30 (0x005F1388)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___POR 0x7D9F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0FB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31 (0x005F138C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___POR 0xFE9F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x1FD
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0 (0x005F1390)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1 (0x005F1394)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2 (0x005F1398)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3 (0x005F139C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4 (0x005F13A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5 (0x005F13A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6 (0x005F13A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7 (0x005F13AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0 (0x005F13B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1 (0x005F13B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2 (0x005F13B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3 (0x005F13BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4 (0x005F13C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5 (0x005F13C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6 (0x005F13C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7 (0x005F13CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___POR 0x302E4000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8 (0x005F13D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9 (0x005F13D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10 (0x005F13D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11 (0x005F13DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12 (0x005F13E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13 (0x005F13E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14 (0x005F13E8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15 (0x005F13EC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___POR 0x282EB000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___POR 0xB
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0 (0x005F13F0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1 (0x005F13F4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2 (0x005F13F8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3 (0x005F13FC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4 (0x005F1400)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5 (0x005F1404)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6 (0x005F1408)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7 (0x005F140C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___POR 0xC0300500
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8 (0x005F1410)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9 (0x005F1414)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10 (0x005F1418)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11 (0x005F141C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12 (0x005F1420)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13 (0x005F1424)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14 (0x005F1428)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15 (0x005F142C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___POR 0x3FCFFD80
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___M 0xFFFFFF80   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___S               7

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0 (0x005F1430)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1 (0x005F1434)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2 (0x005F1438)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3 (0x005F143C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4 (0x005F1440)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5 (0x005F1444)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6 (0x005F1448)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7 (0x005F144C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8 (0x005F1450)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9 (0x005F1454)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10 (0x005F1458)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11 (0x005F145C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12 (0x005F1460)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13 (0x005F1464)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14 (0x005F1468)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15 (0x005F146C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___POR 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0    (0x005F1470)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1    (0x005F1474)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4    (0x005F1478)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___M 0x000001E0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___M 0x3FFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5    (0x005F147C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___M 0x7FE00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___M 0x000FFC00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___S               2

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6    (0x005F1480)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0 (0x005F1484)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___POR 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___M 0x000FC000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___S              14

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1 (0x005F1488)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___M 0xFFF7FC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2 (0x005F148C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___M 0xFFF3FFF0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___S               4

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0 (0x005F1490)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1 (0x005F1494)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3 (0x005F1498)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___M 0x000007FE   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4 (0x005F149C)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5 (0x005F14A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0 (0x005F14A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___M 0x7F000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0 (0x005F14C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___POR 0x26920D00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0 (0x005F14C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___POR 0xBC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0 (0x005F14C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1 (0x005F14CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL (0x005F14D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___S              26

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE (0x005F14D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0 (0x005F14D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___S              31

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0 (0x005F14DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___POR 0xAA000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY (0x005F14E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD (0x005F14E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___POR 0x08B80000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR (0x005F1500)
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___POR 0x6C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___M 0xFDF00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___S              20

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0  (0x005F2000)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT (0x005F2004)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0 (0x005F2040)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___POR 0x000A0026
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___S               1

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1 (0x005F2044)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___POR 0x00004020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___M 0x0007FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA (0x005F2048)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0   (0x005F2080)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___POR 0x0200E8B6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___M 0x03C2FCFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1   (0x005F2084)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___POR 0x00F80204
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___M 0x00FF03FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2   (0x005F2088)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___POR 0xECA86420
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3   (0x005F208C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___M 0x000000F1   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0 (0x005F2090)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0 (0x005F2094)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___M 0xC03FFC30   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1 (0x005F2098)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___M 0x0CFFF000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___S              12

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2 (0x005F209C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___POR 0x000C1010
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___M 0x001FFF3F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3 (0x005F20A0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___POR 0x0000B880
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___M 0x1FFCFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4 (0x005F20A4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___POR 0x01010840
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___M 0x1B07FFF0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0    (0x005F20A8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___POR 0x1D186008
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___M 0x9FFFFE0F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1    (0x005F20AC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___POR 0x00000840
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___M 0x00000DFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0 (0x005F20B0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___POR 0x036E36DC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1 (0x005F20B4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2 (0x005F20B8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2    (0x005F20BC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___POR 0x68000104
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___S               1

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3    (0x005F20C0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___M 0xFFFE7FE0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___S               5

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4    (0x005F20C4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___POR 0x00000492
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5    (0x005F20C8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___S              28

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST   (0x005F20CC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___S              31

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV (0x005F20D0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___M 0x000003F0   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___S               4

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0   (0x005F2100)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___POR 0x1B000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___M 0xFF8001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0 (0x005F2104)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___M 0xFF80001F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0 (0x005F2140)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___S              29

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0 (0x005F2144)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0    (0x005F2148)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___S              27

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0 (0x005F214C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___S              22

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1    (0x005F2180)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___POR 0x073D11C0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___POR 0xC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2    (0x005F2184)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___POR 0x00900090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0 (0x005F2188)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4    (0x005F218C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___POR 0x22685349
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5    (0x005F2190)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___POR 0x004D4D4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6    (0x005F2194)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___POR 0x079E79E7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7    (0x005F2198)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___POR 0x27C27C27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0 (0x005F219C)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___POR 0x00008399
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9    (0x005F21A0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0 (0x005F21A4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___POR 0x01010000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0 (0x005F21A8)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0 (0x005F21AC)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13   (0x005F21B0)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___S               0

#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14 (0x005F21B4)
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0    (0x005F4000)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1    (0x005F4004)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2    (0x005F4008)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3    (0x005F400C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4    (0x005F4010)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5    (0x005F4014)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6    (0x005F4018)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7    (0x005F401C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8    (0x005F4020)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9    (0x005F4024)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10   (0x005F4028)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11   (0x005F402C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12   (0x005F4030)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13   (0x005F4034)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14   (0x005F4038)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15   (0x005F403C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16   (0x005F4040)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17   (0x005F4044)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18   (0x005F4048)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19   (0x005F404C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20   (0x005F4050)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21   (0x005F4054)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22   (0x005F4058)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23   (0x005F405C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24   (0x005F4060)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25   (0x005F4064)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26   (0x005F4068)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27   (0x005F406C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28   (0x005F4070)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29   (0x005F4074)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30   (0x005F4078)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31   (0x005F407C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32   (0x005F4080)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33   (0x005F4084)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34   (0x005F4088)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35   (0x005F408C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36   (0x005F4090)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37   (0x005F4094)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38   (0x005F4098)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39   (0x005F409C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40   (0x005F40A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41   (0x005F40A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42   (0x005F40A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43   (0x005F40AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44   (0x005F40B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45   (0x005F40B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46   (0x005F40B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47   (0x005F40BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48   (0x005F40C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49   (0x005F40C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50   (0x005F40C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51   (0x005F40CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52   (0x005F40D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53   (0x005F40D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54   (0x005F40D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55   (0x005F40DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56   (0x005F40E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57   (0x005F40E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58   (0x005F40E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59   (0x005F40EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60   (0x005F40F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61   (0x005F40F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62   (0x005F40F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63   (0x005F40FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64   (0x005F4100)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65   (0x005F4104)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66   (0x005F4108)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67   (0x005F410C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68   (0x005F4110)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69   (0x005F4114)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70   (0x005F4118)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71   (0x005F411C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72   (0x005F4120)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73   (0x005F4124)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74   (0x005F4128)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75   (0x005F412C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76   (0x005F4130)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77   (0x005F4134)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78   (0x005F4138)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79   (0x005F413C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80   (0x005F4140)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81   (0x005F4144)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82   (0x005F4148)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83   (0x005F414C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84   (0x005F4150)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85   (0x005F4154)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86   (0x005F4158)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87   (0x005F415C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88   (0x005F4160)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89   (0x005F4164)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90   (0x005F4168)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91   (0x005F416C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92   (0x005F4170)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93   (0x005F4174)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94   (0x005F4178)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95   (0x005F417C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96   (0x005F4180)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97   (0x005F4184)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98   (0x005F4188)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99   (0x005F418C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100  (0x005F4190)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101  (0x005F4194)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102  (0x005F4198)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103  (0x005F419C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104  (0x005F41A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105  (0x005F41A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106  (0x005F41A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107  (0x005F41AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108  (0x005F41B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109  (0x005F41B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110  (0x005F41B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111  (0x005F41BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112  (0x005F41C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113  (0x005F41C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114  (0x005F41C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115  (0x005F41CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116  (0x005F41D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117  (0x005F41D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118  (0x005F41D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119  (0x005F41DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120  (0x005F41E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121  (0x005F41E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122  (0x005F41E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123  (0x005F41EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124  (0x005F41F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125  (0x005F41F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126  (0x005F41F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127  (0x005F41FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128  (0x005F4200)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129  (0x005F4204)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130  (0x005F4208)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131  (0x005F420C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132  (0x005F4210)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133  (0x005F4214)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134  (0x005F4218)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135  (0x005F421C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136  (0x005F4220)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137  (0x005F4224)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138  (0x005F4228)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139  (0x005F422C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140  (0x005F4230)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141  (0x005F4234)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142  (0x005F4238)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143  (0x005F423C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144  (0x005F4240)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145  (0x005F4244)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146  (0x005F4248)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147  (0x005F424C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148  (0x005F4250)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149  (0x005F4254)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150  (0x005F4258)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151  (0x005F425C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152  (0x005F4260)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153  (0x005F4264)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154  (0x005F4268)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155  (0x005F426C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156  (0x005F4270)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157  (0x005F4274)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158  (0x005F4278)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159  (0x005F427C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160  (0x005F4280)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161  (0x005F4284)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162  (0x005F4288)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163  (0x005F428C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164  (0x005F4290)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165  (0x005F4294)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166  (0x005F4298)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167  (0x005F429C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168  (0x005F42A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169  (0x005F42A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170  (0x005F42A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171  (0x005F42AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172  (0x005F42B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173  (0x005F42B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174  (0x005F42B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175  (0x005F42BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176  (0x005F42C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177  (0x005F42C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178  (0x005F42C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179  (0x005F42CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180  (0x005F42D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181  (0x005F42D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182  (0x005F42D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183  (0x005F42DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184  (0x005F42E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185  (0x005F42E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186  (0x005F42E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187  (0x005F42EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188  (0x005F42F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189  (0x005F42F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190  (0x005F42F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191  (0x005F42FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192  (0x005F4300)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193  (0x005F4304)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194  (0x005F4308)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195  (0x005F430C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196  (0x005F4310)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197  (0x005F4314)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198  (0x005F4318)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199  (0x005F431C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200  (0x005F4320)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201  (0x005F4324)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202  (0x005F4328)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203  (0x005F432C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204  (0x005F4330)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205  (0x005F4334)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206  (0x005F4338)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207  (0x005F433C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208  (0x005F4340)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209  (0x005F4344)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210  (0x005F4348)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211  (0x005F434C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212  (0x005F4350)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213  (0x005F4354)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214  (0x005F4358)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215  (0x005F435C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216  (0x005F4360)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217  (0x005F4364)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218  (0x005F4368)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219  (0x005F436C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220  (0x005F4370)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221  (0x005F4374)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222  (0x005F4378)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223  (0x005F437C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224  (0x005F4380)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225  (0x005F4384)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226  (0x005F4388)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227  (0x005F438C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228  (0x005F4390)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229  (0x005F4394)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230  (0x005F4398)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231  (0x005F439C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232  (0x005F43A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233  (0x005F43A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234  (0x005F43A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235  (0x005F43AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236  (0x005F43B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237  (0x005F43B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238  (0x005F43B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239  (0x005F43BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240  (0x005F43C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241  (0x005F43C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242  (0x005F43C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243  (0x005F43CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244  (0x005F43D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245  (0x005F43D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246  (0x005F43D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247  (0x005F43DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248  (0x005F43E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249  (0x005F43E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250  (0x005F43E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251  (0x005F43EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252  (0x005F43F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253  (0x005F43F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254  (0x005F43F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255  (0x005F43FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256  (0x005F4400)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257  (0x005F4404)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258  (0x005F4408)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259  (0x005F440C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260  (0x005F4410)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261  (0x005F4414)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262  (0x005F4418)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263  (0x005F441C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264  (0x005F4420)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265  (0x005F4424)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266  (0x005F4428)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267  (0x005F442C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268  (0x005F4430)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269  (0x005F4434)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270  (0x005F4438)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271  (0x005F443C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272  (0x005F4440)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273  (0x005F4444)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274  (0x005F4448)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275  (0x005F444C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276  (0x005F4450)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277  (0x005F4454)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278  (0x005F4458)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279  (0x005F445C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280  (0x005F4460)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281  (0x005F4464)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282  (0x005F4468)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283  (0x005F446C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284  (0x005F4470)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285  (0x005F4474)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286  (0x005F4478)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287  (0x005F447C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288  (0x005F4480)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289  (0x005F4484)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290  (0x005F4488)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291  (0x005F448C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292  (0x005F4490)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293  (0x005F4494)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294  (0x005F4498)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295  (0x005F449C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296  (0x005F44A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297  (0x005F44A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298  (0x005F44A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299  (0x005F44AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300  (0x005F44B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301  (0x005F44B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302  (0x005F44B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303  (0x005F44BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304  (0x005F44C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305  (0x005F44C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306  (0x005F44C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307  (0x005F44CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308  (0x005F44D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309  (0x005F44D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310  (0x005F44D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311  (0x005F44DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312  (0x005F44E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313  (0x005F44E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314  (0x005F44E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315  (0x005F44EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316  (0x005F44F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317  (0x005F44F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318  (0x005F44F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319  (0x005F44FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320  (0x005F4500)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321  (0x005F4504)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322  (0x005F4508)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323  (0x005F450C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324  (0x005F4510)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325  (0x005F4514)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326  (0x005F4518)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327  (0x005F451C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328  (0x005F4520)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329  (0x005F4524)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330  (0x005F4528)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331  (0x005F452C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332  (0x005F4530)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333  (0x005F4534)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334  (0x005F4538)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335  (0x005F453C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336  (0x005F4540)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337  (0x005F4544)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338  (0x005F4548)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339  (0x005F454C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340  (0x005F4550)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341  (0x005F4554)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342  (0x005F4558)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343  (0x005F455C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344  (0x005F4560)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345  (0x005F4564)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346  (0x005F4568)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347  (0x005F456C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348  (0x005F4570)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349  (0x005F4574)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350  (0x005F4578)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351  (0x005F457C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352  (0x005F4580)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353  (0x005F4584)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354  (0x005F4588)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355  (0x005F458C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356  (0x005F4590)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357  (0x005F4594)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358  (0x005F4598)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359  (0x005F459C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360  (0x005F45A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361  (0x005F45A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362  (0x005F45A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363  (0x005F45AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364  (0x005F45B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365  (0x005F45B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366  (0x005F45B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367  (0x005F45BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368  (0x005F45C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369  (0x005F45C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370  (0x005F45C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371  (0x005F45CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372  (0x005F45D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373  (0x005F45D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374  (0x005F45D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375  (0x005F45DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376  (0x005F45E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377  (0x005F45E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378  (0x005F45E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379  (0x005F45EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380  (0x005F45F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381  (0x005F45F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382  (0x005F45F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383  (0x005F45FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384  (0x005F4600)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385  (0x005F4604)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386  (0x005F4608)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387  (0x005F460C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388  (0x005F4610)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389  (0x005F4614)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390  (0x005F4618)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391  (0x005F461C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392  (0x005F4620)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393  (0x005F4624)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394  (0x005F4628)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395  (0x005F462C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396  (0x005F4630)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397  (0x005F4634)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398  (0x005F4638)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399  (0x005F463C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400  (0x005F4640)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401  (0x005F4644)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402  (0x005F4648)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403  (0x005F464C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404  (0x005F4650)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405  (0x005F4654)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406  (0x005F4658)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407  (0x005F465C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408  (0x005F4660)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409  (0x005F4664)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410  (0x005F4668)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411  (0x005F466C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412  (0x005F4670)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413  (0x005F4674)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414  (0x005F4678)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415  (0x005F467C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416  (0x005F4680)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417  (0x005F4684)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418  (0x005F4688)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419  (0x005F468C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420  (0x005F4690)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421  (0x005F4694)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422  (0x005F4698)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423  (0x005F469C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424  (0x005F46A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425  (0x005F46A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426  (0x005F46A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427  (0x005F46AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428  (0x005F46B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429  (0x005F46B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430  (0x005F46B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431  (0x005F46BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432  (0x005F46C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433  (0x005F46C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434  (0x005F46C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435  (0x005F46CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436  (0x005F46D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437  (0x005F46D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438  (0x005F46D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439  (0x005F46DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440  (0x005F46E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441  (0x005F46E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442  (0x005F46E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443  (0x005F46EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444  (0x005F46F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445  (0x005F46F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446  (0x005F46F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447  (0x005F46FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448  (0x005F4700)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449  (0x005F4704)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450  (0x005F4708)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451  (0x005F470C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452  (0x005F4710)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453  (0x005F4714)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454  (0x005F4718)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455  (0x005F471C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456  (0x005F4720)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457  (0x005F4724)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458  (0x005F4728)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459  (0x005F472C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460  (0x005F4730)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461  (0x005F4734)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462  (0x005F4738)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463  (0x005F473C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464  (0x005F4740)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465  (0x005F4744)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466  (0x005F4748)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467  (0x005F474C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468  (0x005F4750)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469  (0x005F4754)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470  (0x005F4758)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471  (0x005F475C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472  (0x005F4760)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473  (0x005F4764)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474  (0x005F4768)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475  (0x005F476C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476  (0x005F4770)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477  (0x005F4774)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478  (0x005F4778)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479  (0x005F477C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480  (0x005F4780)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481  (0x005F4784)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482  (0x005F4788)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483  (0x005F478C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484  (0x005F4790)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485  (0x005F4794)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486  (0x005F4798)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487  (0x005F479C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488  (0x005F47A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489  (0x005F47A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490  (0x005F47A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491  (0x005F47AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492  (0x005F47B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493  (0x005F47B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494  (0x005F47B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495  (0x005F47BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496  (0x005F47C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497  (0x005F47C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498  (0x005F47C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499  (0x005F47CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500  (0x005F47D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501  (0x005F47D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502  (0x005F47D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503  (0x005F47DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504  (0x005F47E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505  (0x005F47E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506  (0x005F47E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507  (0x005F47EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508  (0x005F47F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509  (0x005F47F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510  (0x005F47F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511  (0x005F47FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512  (0x005F4800)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513  (0x005F4804)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514  (0x005F4808)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515  (0x005F480C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516  (0x005F4810)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517  (0x005F4814)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518  (0x005F4818)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519  (0x005F481C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520  (0x005F4820)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521  (0x005F4824)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522  (0x005F4828)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523  (0x005F482C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524  (0x005F4830)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525  (0x005F4834)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526  (0x005F4838)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527  (0x005F483C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528  (0x005F4840)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529  (0x005F4844)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530  (0x005F4848)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531  (0x005F484C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532  (0x005F4850)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533  (0x005F4854)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534  (0x005F4858)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535  (0x005F485C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536  (0x005F4860)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537  (0x005F4864)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538  (0x005F4868)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539  (0x005F486C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540  (0x005F4870)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541  (0x005F4874)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542  (0x005F4878)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543  (0x005F487C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544  (0x005F4880)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545  (0x005F4884)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546  (0x005F4888)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547  (0x005F488C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548  (0x005F4890)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549  (0x005F4894)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550  (0x005F4898)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551  (0x005F489C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552  (0x005F48A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553  (0x005F48A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554  (0x005F48A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555  (0x005F48AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556  (0x005F48B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557  (0x005F48B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558  (0x005F48B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559  (0x005F48BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560  (0x005F48C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561  (0x005F48C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562  (0x005F48C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563  (0x005F48CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564  (0x005F48D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565  (0x005F48D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566  (0x005F48D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567  (0x005F48DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568  (0x005F48E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569  (0x005F48E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570  (0x005F48E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571  (0x005F48EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572  (0x005F48F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573  (0x005F48F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574  (0x005F48F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575  (0x005F48FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576  (0x005F4900)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577  (0x005F4904)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578  (0x005F4908)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579  (0x005F490C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580  (0x005F4910)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581  (0x005F4914)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582  (0x005F4918)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583  (0x005F491C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584  (0x005F4920)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585  (0x005F4924)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586  (0x005F4928)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587  (0x005F492C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588  (0x005F4930)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589  (0x005F4934)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590  (0x005F4938)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591  (0x005F493C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592  (0x005F4940)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593  (0x005F4944)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594  (0x005F4948)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595  (0x005F494C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596  (0x005F4950)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597  (0x005F4954)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598  (0x005F4958)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599  (0x005F495C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600  (0x005F4960)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601  (0x005F4964)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602  (0x005F4968)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603  (0x005F496C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604  (0x005F4970)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605  (0x005F4974)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606  (0x005F4978)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607  (0x005F497C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608  (0x005F4980)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609  (0x005F4984)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610  (0x005F4988)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611  (0x005F498C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612  (0x005F4990)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613  (0x005F4994)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614  (0x005F4998)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615  (0x005F499C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616  (0x005F49A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617  (0x005F49A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618  (0x005F49A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619  (0x005F49AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620  (0x005F49B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621  (0x005F49B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622  (0x005F49B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623  (0x005F49BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624  (0x005F49C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625  (0x005F49C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626  (0x005F49C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627  (0x005F49CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628  (0x005F49D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629  (0x005F49D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630  (0x005F49D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631  (0x005F49DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632  (0x005F49E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633  (0x005F49E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634  (0x005F49E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635  (0x005F49EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636  (0x005F49F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637  (0x005F49F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638  (0x005F49F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639  (0x005F49FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640  (0x005F4A00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641  (0x005F4A04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642  (0x005F4A08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643  (0x005F4A0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644  (0x005F4A10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645  (0x005F4A14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646  (0x005F4A18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647  (0x005F4A1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648  (0x005F4A20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649  (0x005F4A24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650  (0x005F4A28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651  (0x005F4A2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652  (0x005F4A30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653  (0x005F4A34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654  (0x005F4A38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655  (0x005F4A3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656  (0x005F4A40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657  (0x005F4A44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658  (0x005F4A48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659  (0x005F4A4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660  (0x005F4A50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661  (0x005F4A54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662  (0x005F4A58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663  (0x005F4A5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664  (0x005F4A60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665  (0x005F4A64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666  (0x005F4A68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667  (0x005F4A6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668  (0x005F4A70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669  (0x005F4A74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670  (0x005F4A78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671  (0x005F4A7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672  (0x005F4A80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673  (0x005F4A84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674  (0x005F4A88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675  (0x005F4A8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676  (0x005F4A90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677  (0x005F4A94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678  (0x005F4A98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679  (0x005F4A9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680  (0x005F4AA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681  (0x005F4AA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682  (0x005F4AA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683  (0x005F4AAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684  (0x005F4AB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685  (0x005F4AB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686  (0x005F4AB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687  (0x005F4ABC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688  (0x005F4AC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689  (0x005F4AC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690  (0x005F4AC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691  (0x005F4ACC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692  (0x005F4AD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693  (0x005F4AD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694  (0x005F4AD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695  (0x005F4ADC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696  (0x005F4AE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697  (0x005F4AE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698  (0x005F4AE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699  (0x005F4AEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700  (0x005F4AF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701  (0x005F4AF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702  (0x005F4AF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703  (0x005F4AFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704  (0x005F4B00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705  (0x005F4B04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706  (0x005F4B08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707  (0x005F4B0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708  (0x005F4B10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709  (0x005F4B14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710  (0x005F4B18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711  (0x005F4B1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712  (0x005F4B20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713  (0x005F4B24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714  (0x005F4B28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715  (0x005F4B2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716  (0x005F4B30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717  (0x005F4B34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718  (0x005F4B38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719  (0x005F4B3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720  (0x005F4B40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721  (0x005F4B44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722  (0x005F4B48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723  (0x005F4B4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724  (0x005F4B50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725  (0x005F4B54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726  (0x005F4B58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727  (0x005F4B5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728  (0x005F4B60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729  (0x005F4B64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730  (0x005F4B68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731  (0x005F4B6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732  (0x005F4B70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733  (0x005F4B74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734  (0x005F4B78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735  (0x005F4B7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736  (0x005F4B80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737  (0x005F4B84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738  (0x005F4B88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739  (0x005F4B8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740  (0x005F4B90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741  (0x005F4B94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742  (0x005F4B98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743  (0x005F4B9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744  (0x005F4BA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745  (0x005F4BA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746  (0x005F4BA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747  (0x005F4BAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748  (0x005F4BB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749  (0x005F4BB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750  (0x005F4BB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751  (0x005F4BBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752  (0x005F4BC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753  (0x005F4BC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754  (0x005F4BC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755  (0x005F4BCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756  (0x005F4BD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757  (0x005F4BD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758  (0x005F4BD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759  (0x005F4BDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760  (0x005F4BE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761  (0x005F4BE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762  (0x005F4BE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763  (0x005F4BEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764  (0x005F4BF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765  (0x005F4BF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766  (0x005F4BF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767  (0x005F4BFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768  (0x005F4C00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769  (0x005F4C04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770  (0x005F4C08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771  (0x005F4C0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772  (0x005F4C10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773  (0x005F4C14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774  (0x005F4C18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775  (0x005F4C1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776  (0x005F4C20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777  (0x005F4C24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778  (0x005F4C28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779  (0x005F4C2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780  (0x005F4C30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781  (0x005F4C34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782  (0x005F4C38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783  (0x005F4C3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784  (0x005F4C40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785  (0x005F4C44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786  (0x005F4C48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787  (0x005F4C4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788  (0x005F4C50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789  (0x005F4C54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790  (0x005F4C58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791  (0x005F4C5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792  (0x005F4C60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793  (0x005F4C64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794  (0x005F4C68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795  (0x005F4C6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796  (0x005F4C70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797  (0x005F4C74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798  (0x005F4C78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799  (0x005F4C7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800  (0x005F4C80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801  (0x005F4C84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802  (0x005F4C88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803  (0x005F4C8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804  (0x005F4C90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805  (0x005F4C94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806  (0x005F4C98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807  (0x005F4C9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808  (0x005F4CA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809  (0x005F4CA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810  (0x005F4CA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811  (0x005F4CAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812  (0x005F4CB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813  (0x005F4CB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814  (0x005F4CB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815  (0x005F4CBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816  (0x005F4CC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817  (0x005F4CC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818  (0x005F4CC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819  (0x005F4CCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820  (0x005F4CD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821  (0x005F4CD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822  (0x005F4CD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823  (0x005F4CDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824  (0x005F4CE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825  (0x005F4CE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826  (0x005F4CE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827  (0x005F4CEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828  (0x005F4CF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829  (0x005F4CF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830  (0x005F4CF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831  (0x005F4CFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832  (0x005F4D00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833  (0x005F4D04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834  (0x005F4D08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835  (0x005F4D0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836  (0x005F4D10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837  (0x005F4D14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838  (0x005F4D18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839  (0x005F4D1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840  (0x005F4D20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841  (0x005F4D24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842  (0x005F4D28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843  (0x005F4D2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844  (0x005F4D30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845  (0x005F4D34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846  (0x005F4D38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847  (0x005F4D3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848  (0x005F4D40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849  (0x005F4D44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850  (0x005F4D48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851  (0x005F4D4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852  (0x005F4D50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853  (0x005F4D54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854  (0x005F4D58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855  (0x005F4D5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856  (0x005F4D60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857  (0x005F4D64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858  (0x005F4D68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859  (0x005F4D6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860  (0x005F4D70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861  (0x005F4D74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862  (0x005F4D78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863  (0x005F4D7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864  (0x005F4D80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865  (0x005F4D84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866  (0x005F4D88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867  (0x005F4D8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868  (0x005F4D90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869  (0x005F4D94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870  (0x005F4D98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871  (0x005F4D9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872  (0x005F4DA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873  (0x005F4DA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874  (0x005F4DA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875  (0x005F4DAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876  (0x005F4DB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877  (0x005F4DB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878  (0x005F4DB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879  (0x005F4DBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880  (0x005F4DC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881  (0x005F4DC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882  (0x005F4DC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883  (0x005F4DCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884  (0x005F4DD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885  (0x005F4DD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886  (0x005F4DD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887  (0x005F4DDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888  (0x005F4DE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889  (0x005F4DE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890  (0x005F4DE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891  (0x005F4DEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892  (0x005F4DF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893  (0x005F4DF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894  (0x005F4DF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895  (0x005F4DFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896  (0x005F4E00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897  (0x005F4E04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898  (0x005F4E08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899  (0x005F4E0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900  (0x005F4E10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901  (0x005F4E14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902  (0x005F4E18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903  (0x005F4E1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904  (0x005F4E20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905  (0x005F4E24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906  (0x005F4E28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907  (0x005F4E2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908  (0x005F4E30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909  (0x005F4E34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910  (0x005F4E38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911  (0x005F4E3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912  (0x005F4E40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913  (0x005F4E44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914  (0x005F4E48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915  (0x005F4E4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916  (0x005F4E50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917  (0x005F4E54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918  (0x005F4E58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919  (0x005F4E5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920  (0x005F4E60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921  (0x005F4E64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922  (0x005F4E68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923  (0x005F4E6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924  (0x005F4E70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925  (0x005F4E74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926  (0x005F4E78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927  (0x005F4E7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928  (0x005F4E80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929  (0x005F4E84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930  (0x005F4E88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931  (0x005F4E8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932  (0x005F4E90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933  (0x005F4E94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934  (0x005F4E98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935  (0x005F4E9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936  (0x005F4EA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937  (0x005F4EA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938  (0x005F4EA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939  (0x005F4EAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940  (0x005F4EB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941  (0x005F4EB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942  (0x005F4EB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943  (0x005F4EBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944  (0x005F4EC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945  (0x005F4EC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946  (0x005F4EC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947  (0x005F4ECC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948  (0x005F4ED0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949  (0x005F4ED4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950  (0x005F4ED8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951  (0x005F4EDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952  (0x005F4EE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953  (0x005F4EE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954  (0x005F4EE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955  (0x005F4EEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956  (0x005F4EF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957  (0x005F4EF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958  (0x005F4EF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959  (0x005F4EFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960  (0x005F4F00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961  (0x005F4F04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962  (0x005F4F08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963  (0x005F4F0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964  (0x005F4F10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965  (0x005F4F14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966  (0x005F4F18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967  (0x005F4F1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968  (0x005F4F20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969  (0x005F4F24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970  (0x005F4F28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971  (0x005F4F2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972  (0x005F4F30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973  (0x005F4F34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974  (0x005F4F38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975  (0x005F4F3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976  (0x005F4F40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977  (0x005F4F44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978  (0x005F4F48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979  (0x005F4F4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980  (0x005F4F50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981  (0x005F4F54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982  (0x005F4F58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983  (0x005F4F5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984  (0x005F4F60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985  (0x005F4F64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986  (0x005F4F68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987  (0x005F4F6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988  (0x005F4F70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989  (0x005F4F74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990  (0x005F4F78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991  (0x005F4F7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992  (0x005F4F80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993  (0x005F4F84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994  (0x005F4F88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995  (0x005F4F8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996  (0x005F4F90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997  (0x005F4F94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998  (0x005F4F98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999  (0x005F4F9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000 (0x005F4FA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001 (0x005F4FA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002 (0x005F4FA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003 (0x005F4FAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004 (0x005F4FB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005 (0x005F4FB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006 (0x005F4FB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007 (0x005F4FBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008 (0x005F4FC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009 (0x005F4FC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010 (0x005F4FC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011 (0x005F4FCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012 (0x005F4FD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013 (0x005F4FD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014 (0x005F4FD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015 (0x005F4FDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016 (0x005F4FE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017 (0x005F4FE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018 (0x005F4FE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019 (0x005F4FEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020 (0x005F4FF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021 (0x005F4FF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022 (0x005F4FF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023 (0x005F4FFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0    (0x005F5000)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1    (0x005F5004)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2    (0x005F5008)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3    (0x005F500C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4    (0x005F5010)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5    (0x005F5014)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6    (0x005F5018)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7    (0x005F501C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8    (0x005F5020)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9    (0x005F5024)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10   (0x005F5028)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11   (0x005F502C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12   (0x005F5030)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13   (0x005F5034)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14   (0x005F5038)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15   (0x005F503C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16   (0x005F5040)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17   (0x005F5044)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18   (0x005F5048)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19   (0x005F504C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20   (0x005F5050)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21   (0x005F5054)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22   (0x005F5058)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23   (0x005F505C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24   (0x005F5060)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25   (0x005F5064)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26   (0x005F5068)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27   (0x005F506C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28   (0x005F5070)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29   (0x005F5074)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30   (0x005F5078)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31   (0x005F507C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32   (0x005F5080)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33   (0x005F5084)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34   (0x005F5088)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35   (0x005F508C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36   (0x005F5090)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37   (0x005F5094)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38   (0x005F5098)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39   (0x005F509C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40   (0x005F50A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41   (0x005F50A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42   (0x005F50A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43   (0x005F50AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44   (0x005F50B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45   (0x005F50B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46   (0x005F50B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47   (0x005F50BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48   (0x005F50C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49   (0x005F50C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50   (0x005F50C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51   (0x005F50CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52   (0x005F50D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53   (0x005F50D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54   (0x005F50D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55   (0x005F50DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56   (0x005F50E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57   (0x005F50E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58   (0x005F50E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59   (0x005F50EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60   (0x005F50F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61   (0x005F50F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62   (0x005F50F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63   (0x005F50FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64   (0x005F5100)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65   (0x005F5104)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66   (0x005F5108)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67   (0x005F510C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68   (0x005F5110)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69   (0x005F5114)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70   (0x005F5118)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71   (0x005F511C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72   (0x005F5120)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73   (0x005F5124)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74   (0x005F5128)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75   (0x005F512C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76   (0x005F5130)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77   (0x005F5134)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78   (0x005F5138)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79   (0x005F513C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80   (0x005F5140)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81   (0x005F5144)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82   (0x005F5148)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83   (0x005F514C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84   (0x005F5150)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85   (0x005F5154)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86   (0x005F5158)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87   (0x005F515C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88   (0x005F5160)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89   (0x005F5164)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90   (0x005F5168)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91   (0x005F516C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92   (0x005F5170)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93   (0x005F5174)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94   (0x005F5178)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95   (0x005F517C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96   (0x005F5180)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97   (0x005F5184)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98   (0x005F5188)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99   (0x005F518C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100  (0x005F5190)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101  (0x005F5194)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102  (0x005F5198)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103  (0x005F519C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104  (0x005F51A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105  (0x005F51A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106  (0x005F51A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107  (0x005F51AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108  (0x005F51B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109  (0x005F51B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110  (0x005F51B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111  (0x005F51BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112  (0x005F51C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113  (0x005F51C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114  (0x005F51C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115  (0x005F51CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116  (0x005F51D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117  (0x005F51D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118  (0x005F51D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119  (0x005F51DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120  (0x005F51E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121  (0x005F51E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122  (0x005F51E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123  (0x005F51EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124  (0x005F51F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125  (0x005F51F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126  (0x005F51F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127  (0x005F51FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128  (0x005F5200)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129  (0x005F5204)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130  (0x005F5208)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131  (0x005F520C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132  (0x005F5210)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133  (0x005F5214)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134  (0x005F5218)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135  (0x005F521C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136  (0x005F5220)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137  (0x005F5224)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138  (0x005F5228)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139  (0x005F522C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140  (0x005F5230)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141  (0x005F5234)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142  (0x005F5238)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143  (0x005F523C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144  (0x005F5240)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145  (0x005F5244)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146  (0x005F5248)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147  (0x005F524C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148  (0x005F5250)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149  (0x005F5254)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150  (0x005F5258)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151  (0x005F525C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152  (0x005F5260)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153  (0x005F5264)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154  (0x005F5268)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155  (0x005F526C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156  (0x005F5270)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157  (0x005F5274)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158  (0x005F5278)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159  (0x005F527C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160  (0x005F5280)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161  (0x005F5284)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162  (0x005F5288)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163  (0x005F528C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164  (0x005F5290)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165  (0x005F5294)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166  (0x005F5298)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167  (0x005F529C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168  (0x005F52A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169  (0x005F52A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170  (0x005F52A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171  (0x005F52AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172  (0x005F52B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173  (0x005F52B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174  (0x005F52B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175  (0x005F52BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176  (0x005F52C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177  (0x005F52C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178  (0x005F52C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179  (0x005F52CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180  (0x005F52D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181  (0x005F52D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182  (0x005F52D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183  (0x005F52DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184  (0x005F52E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185  (0x005F52E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186  (0x005F52E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187  (0x005F52EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188  (0x005F52F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189  (0x005F52F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190  (0x005F52F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191  (0x005F52FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192  (0x005F5300)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193  (0x005F5304)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194  (0x005F5308)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195  (0x005F530C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196  (0x005F5310)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197  (0x005F5314)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198  (0x005F5318)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199  (0x005F531C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200  (0x005F5320)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201  (0x005F5324)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202  (0x005F5328)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203  (0x005F532C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204  (0x005F5330)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205  (0x005F5334)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206  (0x005F5338)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207  (0x005F533C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208  (0x005F5340)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209  (0x005F5344)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210  (0x005F5348)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211  (0x005F534C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212  (0x005F5350)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213  (0x005F5354)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214  (0x005F5358)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215  (0x005F535C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216  (0x005F5360)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217  (0x005F5364)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218  (0x005F5368)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219  (0x005F536C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220  (0x005F5370)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221  (0x005F5374)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222  (0x005F5378)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223  (0x005F537C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224  (0x005F5380)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225  (0x005F5384)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226  (0x005F5388)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227  (0x005F538C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228  (0x005F5390)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229  (0x005F5394)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230  (0x005F5398)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231  (0x005F539C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232  (0x005F53A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233  (0x005F53A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234  (0x005F53A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235  (0x005F53AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236  (0x005F53B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237  (0x005F53B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238  (0x005F53B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239  (0x005F53BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240  (0x005F53C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241  (0x005F53C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242  (0x005F53C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243  (0x005F53CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244  (0x005F53D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245  (0x005F53D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246  (0x005F53D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247  (0x005F53DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248  (0x005F53E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249  (0x005F53E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250  (0x005F53E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251  (0x005F53EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252  (0x005F53F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253  (0x005F53F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254  (0x005F53F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255  (0x005F53FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0    (0x005F5800)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1    (0x005F5804)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2    (0x005F5808)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3    (0x005F580C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4    (0x005F5810)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5    (0x005F5814)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6    (0x005F5818)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7    (0x005F581C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8    (0x005F5820)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9    (0x005F5824)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10   (0x005F5828)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11   (0x005F582C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12   (0x005F5830)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13   (0x005F5834)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14   (0x005F5838)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15   (0x005F583C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16   (0x005F5840)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17   (0x005F5844)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18   (0x005F5848)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19   (0x005F584C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20   (0x005F5850)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21   (0x005F5854)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22   (0x005F5858)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23   (0x005F585C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24   (0x005F5860)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25   (0x005F5864)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26   (0x005F5868)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27   (0x005F586C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28   (0x005F5870)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29   (0x005F5874)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30   (0x005F5878)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31   (0x005F587C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32   (0x005F5880)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33   (0x005F5884)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34   (0x005F5888)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35   (0x005F588C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36   (0x005F5890)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37   (0x005F5894)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38   (0x005F5898)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39   (0x005F589C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40   (0x005F58A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41   (0x005F58A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42   (0x005F58A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43   (0x005F58AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44   (0x005F58B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45   (0x005F58B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46   (0x005F58B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47   (0x005F58BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48   (0x005F58C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49   (0x005F58C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50   (0x005F58C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51   (0x005F58CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52   (0x005F58D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53   (0x005F58D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54   (0x005F58D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55   (0x005F58DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56   (0x005F58E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57   (0x005F58E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58   (0x005F58E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59   (0x005F58EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60   (0x005F58F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61   (0x005F58F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62   (0x005F58F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63   (0x005F58FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64   (0x005F5900)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65   (0x005F5904)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66   (0x005F5908)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67   (0x005F590C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68   (0x005F5910)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69   (0x005F5914)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70   (0x005F5918)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71   (0x005F591C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72   (0x005F5920)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73   (0x005F5924)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74   (0x005F5928)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75   (0x005F592C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76   (0x005F5930)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77   (0x005F5934)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78   (0x005F5938)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79   (0x005F593C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80   (0x005F5940)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81   (0x005F5944)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82   (0x005F5948)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83   (0x005F594C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84   (0x005F5950)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85   (0x005F5954)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86   (0x005F5958)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87   (0x005F595C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88   (0x005F5960)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89   (0x005F5964)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90   (0x005F5968)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91   (0x005F596C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92   (0x005F5970)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93   (0x005F5974)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94   (0x005F5978)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95   (0x005F597C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96   (0x005F5980)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97   (0x005F5984)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98   (0x005F5988)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99   (0x005F598C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100  (0x005F5990)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101  (0x005F5994)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102  (0x005F5998)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103  (0x005F599C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104  (0x005F59A0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105  (0x005F59A4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106  (0x005F59A8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107  (0x005F59AC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108  (0x005F59B0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109  (0x005F59B4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110  (0x005F59B8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111  (0x005F59BC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112  (0x005F59C0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113  (0x005F59C4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114  (0x005F59C8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115  (0x005F59CC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116  (0x005F59D0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117  (0x005F59D4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118  (0x005F59D8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119  (0x005F59DC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120  (0x005F59E0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121  (0x005F59E4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122  (0x005F59E8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123  (0x005F59EC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124  (0x005F59F0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125  (0x005F59F4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126  (0x005F59F8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127  (0x005F59FC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0    (0x005F5C00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1    (0x005F5C04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2    (0x005F5C08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3    (0x005F5C0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4    (0x005F5C10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5    (0x005F5C14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6    (0x005F5C18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7    (0x005F5C1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8    (0x005F5C20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9    (0x005F5C24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10   (0x005F5C28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11   (0x005F5C2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12   (0x005F5C30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13   (0x005F5C34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14   (0x005F5C38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15   (0x005F5C3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16   (0x005F5C40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17   (0x005F5C44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18   (0x005F5C48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19   (0x005F5C4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20   (0x005F5C50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21   (0x005F5C54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22   (0x005F5C58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23   (0x005F5C5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24   (0x005F5C60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25   (0x005F5C64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26   (0x005F5C68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27   (0x005F5C6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28   (0x005F5C70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29   (0x005F5C74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30   (0x005F5C78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31   (0x005F5C7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32   (0x005F5C80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33   (0x005F5C84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34   (0x005F5C88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35   (0x005F5C8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36   (0x005F5C90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37   (0x005F5C94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38   (0x005F5C98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39   (0x005F5C9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40   (0x005F5CA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41   (0x005F5CA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42   (0x005F5CA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43   (0x005F5CAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44   (0x005F5CB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45   (0x005F5CB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46   (0x005F5CB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47   (0x005F5CBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48   (0x005F5CC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49   (0x005F5CC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50   (0x005F5CC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51   (0x005F5CCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52   (0x005F5CD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53   (0x005F5CD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54   (0x005F5CD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55   (0x005F5CDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56   (0x005F5CE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57   (0x005F5CE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58   (0x005F5CE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59   (0x005F5CEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60   (0x005F5CF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61   (0x005F5CF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62   (0x005F5CF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63   (0x005F5CFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64   (0x005F5D00)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65   (0x005F5D04)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66   (0x005F5D08)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67   (0x005F5D0C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68   (0x005F5D10)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69   (0x005F5D14)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70   (0x005F5D18)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71   (0x005F5D1C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72   (0x005F5D20)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73   (0x005F5D24)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74   (0x005F5D28)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75   (0x005F5D2C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76   (0x005F5D30)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77   (0x005F5D34)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78   (0x005F5D38)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79   (0x005F5D3C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80   (0x005F5D40)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81   (0x005F5D44)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82   (0x005F5D48)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83   (0x005F5D4C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84   (0x005F5D50)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85   (0x005F5D54)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86   (0x005F5D58)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87   (0x005F5D5C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88   (0x005F5D60)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89   (0x005F5D64)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90   (0x005F5D68)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91   (0x005F5D6C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92   (0x005F5D70)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93   (0x005F5D74)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94   (0x005F5D78)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95   (0x005F5D7C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96   (0x005F5D80)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97   (0x005F5D84)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98   (0x005F5D88)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99   (0x005F5D8C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100  (0x005F5D90)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101  (0x005F5D94)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102  (0x005F5D98)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103  (0x005F5D9C)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104  (0x005F5DA0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105  (0x005F5DA4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106  (0x005F5DA8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107  (0x005F5DAC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108  (0x005F5DB0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109  (0x005F5DB4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110  (0x005F5DB8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111  (0x005F5DBC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112  (0x005F5DC0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113  (0x005F5DC4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114  (0x005F5DC8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115  (0x005F5DCC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116  (0x005F5DD0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117  (0x005F5DD4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118  (0x005F5DD8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119  (0x005F5DDC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120  (0x005F5DE0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121  (0x005F5DE4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122  (0x005F5DE8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123  (0x005F5DEC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124  (0x005F5DF0)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125  (0x005F5DF4)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126  (0x005F5DF8)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127  (0x005F5DFC)
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG   (0x005F8000)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___POR 0x0000AB80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0        (0x005F8004)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1        (0x005F8008)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___S               6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0   (0x005F800C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1   (0x005F8010)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2   (0x005F8014)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___POR 0x0000C001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S              14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S              13
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S              11
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S              10
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___M 0xC000FF01   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0      (0x005F8018)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___M 0xFECC0000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0      (0x005F801C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___M 0xFEDC0000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___S              18

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET     (0x005F8020)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0 (0x005F8024)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___POR 0x06769292
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0 (0x005F8028)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___POR 0x00004142
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___S              28
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0   (0x005F802C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___S              29
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___S              29

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0       (0x005F8030)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0   (0x005F8034)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1   (0x005F8038)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG (0x005F803C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2        (0x005F8040)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0    (0x005F8044)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___POR 0x09200000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___M 0x0FF80007   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST    (0x005F8048)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0 (0x005F8080)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___POR 0x005078A0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1 (0x005F8084)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___POR 0xC8F00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___M 0xFFFF03FF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL (0x005F8088)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___M 0x0000C000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___S              14

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0 (0x005F808C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1 (0x005F8090)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___M 0x0000FFBF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0 (0x005F8094)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S              25
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0 (0x005F8098)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___S               3
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___S               2
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___S               1
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1 (0x005F809C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0 (0x005F80A0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___M 0x000C3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0        (0x005F80A4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___S              30

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC   (0x005F80A8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___S              22
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC   (0x005F80AC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___M 0x007F3FFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN   (0x005F80B0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___S              15
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___S               7
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___M 0x00FFFFBF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0 (0x005F80B4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S              23
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S              20
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S              19
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S              18
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___S              12
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S               4
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1 (0x005F80B8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S              24
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___S              16
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___S               8
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___M 0x7FFF3F00   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___S               8

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0        (0x005F80C0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1        (0x005F80C4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2        (0x005F80C8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3        (0x005F80CC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4        (0x005F80D0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5        (0x005F80D4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6        (0x005F80D8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7        (0x005F80DC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8        (0x005F80E0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9        (0x005F80E4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10       (0x005F80E8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11       (0x005F80EC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12       (0x005F80F0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13       (0x005F80F4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14       (0x005F80F8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15       (0x005F80FC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16       (0x005F8100)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17       (0x005F8104)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18       (0x005F8108)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19       (0x005F810C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20       (0x005F8110)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21       (0x005F8114)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22       (0x005F8118)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23       (0x005F811C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24       (0x005F8120)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25       (0x005F8124)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26       (0x005F8128)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27       (0x005F812C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28       (0x005F8130)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29       (0x005F8134)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30       (0x005F8138)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31       (0x005F813C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32       (0x005F8140)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33       (0x005F8144)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34       (0x005F8148)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35       (0x005F814C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36       (0x005F8150)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37       (0x005F8154)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38       (0x005F8158)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39       (0x005F815C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40       (0x005F8160)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41       (0x005F8164)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42       (0x005F8168)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43       (0x005F816C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44       (0x005F8170)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45       (0x005F8174)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46       (0x005F8178)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47       (0x005F817C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48       (0x005F8180)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49       (0x005F8184)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50       (0x005F8188)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51       (0x005F818C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52       (0x005F8190)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53       (0x005F8194)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54       (0x005F8198)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55       (0x005F819C)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56       (0x005F81A0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57       (0x005F81A4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58       (0x005F81A8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59       (0x005F81AC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60       (0x005F81B0)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61       (0x005F81B4)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62       (0x005F81B8)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___S              26

#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63       (0x005F81BC)
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___S              26
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___S              26

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL   (0x005F8400)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___M 0x0F800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___S              23

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG    (0x005F8404)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB        (0x005F8408)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___M 0x00FF8000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC      (0x005F840C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___POR 0x92492400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___S              10

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0     (0x005F8410)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___POR 0x87CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1     (0x005F8414)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___POR 0x07CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2     (0x005F8418)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___POR 0x07CCD234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3     (0x005F841C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___POR 0x07C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___POR 0x03E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0      (0x005F8420)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___POR 0x7EC8AF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___POR 0x045
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1      (0x005F8424)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___POR 0x7EC9CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___POR 0x04E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2      (0x005F8428)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___POR 0x7ECAEF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___POR 0x057
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3      (0x005F842C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___POR 0x7ECC4F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___POR 0x062
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4      (0x005F8430)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___POR 0x7ECDCF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___POR 0x06E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5      (0x005F8434)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___POR 0x7ECF6F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___POR 0x07B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6      (0x005F8438)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___POR 0x7ED14F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___POR 0x08A
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7      (0x005F843C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___POR 0x7ED36F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___POR 0x09B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8      (0x005F8440)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9      (0x005F8444)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10     (0x005F8448)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11     (0x005F844C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12     (0x005F8450)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13     (0x005F8454)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14     (0x005F8458)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15     (0x005F845C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___POR 0x7ED5CF76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___POR 0x0AE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16     (0x005F8460)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17     (0x005F8464)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18     (0x005F8468)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19     (0x005F846C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20     (0x005F8470)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21     (0x005F8474)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22     (0x005F8478)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___POR 0x7EC00F76
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0    (0x005F847C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1    (0x005F8480)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2    (0x005F8484)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3    (0x005F8488)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0     (0x005F848C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1     (0x005F8490)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2     (0x005F8494)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3     (0x005F8498)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___POR 0x18000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___POR 0x03
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4     (0x005F849C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___POR 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___POR 0x04
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5     (0x005F84A0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___POR 0x28000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6     (0x005F84A4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___POR 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7     (0x005F84A8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___POR 0x38000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___POR 0x07
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8     (0x005F84AC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___POR 0x08
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9     (0x005F84B0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___POR 0x48000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___POR 0x09
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10    (0x005F84B4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___POR 0x50000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11    (0x005F84B8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___POR 0x58000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___POR 0x0B
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12    (0x005F84BC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___POR 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13    (0x005F84C0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___POR 0x68000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___POR 0x0D
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14    (0x005F84C4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___POR 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15    (0x005F84C8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___POR 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16    (0x005F84CC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___POR 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___POR 0x10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17    (0x005F84D0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___POR 0x88000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___POR 0x11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18    (0x005F84D4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___POR 0x90000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19    (0x005F84D8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___POR 0x98000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___POR 0x13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20    (0x005F84DC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___POR 0xA0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21    (0x005F84E0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___POR 0xA8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___POR 0x15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22    (0x005F84E4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___POR 0xB0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___POR 0x16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___S              27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0   (0x005F84E8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___M 0x0FF80000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___M 0xFFFFFFF0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___S               4

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1   (0x005F84EC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___S               8

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0    (0x005F84F0)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1    (0x005F84F4)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___M 0x0000FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___M 0x000000FE
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV        (0x005F84F8)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___S              28

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0           (0x005F84FC)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___M    0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___S                  0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX    (0x005F8500)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___M 0x3E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___S              25

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0   (0x005F8504)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___M 0x001FF000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___S               8

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1   (0x005F8508)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___M 0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___S              14

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0    (0x005F850C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___M 0x00FF8000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___M 0x00007FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1    (0x005F8510)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___M 0x07800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___M 0x000FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___M 0x00001FC0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___S               6

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB     (0x005F8514)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT           (0x005F8518)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___POR  0x58000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___M    0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___S                 27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA           (0x005F851C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___POR  0x37000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___M    0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___S                 22

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ            (0x005F8520)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___RWC      QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___POR   0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___M     0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___S                  27

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2           (0x005F8524)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___POR  0x00000020
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___S               6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___S               3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___M    0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___S                  3

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0 (0x005F8528)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___S              24
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___S              16

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1 (0x005F852C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___POR 0x80426300
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___POR 0x9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___S               3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___S               2

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL (0x005F8530)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___M 0x06000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___S              16

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0        (0x005F8534)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___POR 0x00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___M 0x0003FFFF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___S               0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0          (0x005F8538)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___POR 0xD8049248
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___M   0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1          (0x005F853C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___POR 0x4800006C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___S              19
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___M 0x0003E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___S               5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___M   0xFFFFE0FC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2          (0x005F8540)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___POR 0x1088B000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___M 0x003C0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___M   0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___S                12

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3          (0x005F8544)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___POR 0x00005E2F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___S               9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___M   0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___S                 0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4          (0x005F8548)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___POR 0x178BDCB9
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___POR 0x02F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___M 0x007FC000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___S               0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___M   0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___S                 0

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5          (0x005F854C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___POR 0x72E49630
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___POR 0x39
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___S              18
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___S              15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___S              12
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___M 0x00000F80
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___M 0x0000007C
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___S               2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___M   0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___S                 2

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE      (0x005F8550)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___S              30

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC  (0x005F8554)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___POR 0xDADB7400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___POR 0x6
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___S              26
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___S              23
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___S              20
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___S              14
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___S              11
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___S              10

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT   (0x005F8558)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___POR 0x00BFF234
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___S              30
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___S              21
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___S              17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S              10
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S               7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT    (0x005F855C)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___POR 0x2AC01776
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___S              13
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S               8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S               4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S               1
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___S               1

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA       (0x005F8560)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___POR 0x37000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___S              25
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___S              22
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___S              22

#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ        (0x005F8564)
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___POR 0x40000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___S              31
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___S              27
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___S              27

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG       (0x005F8800)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___POR 0x22BB1212
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___POR 0x22BB1212
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL   (0x005F8804)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___S               6
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___M 0x0000007F   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG      (0x005F8808)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___M 0xC0000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___S              30

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC          (0x005F880C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___RWC    QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___M   0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___S                16

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0     (0x005F8810)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___POR 0x04040434
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___S               8
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___S               4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1     (0x005F8814)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___POR 0x5268DB71
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___S              14
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___S              11
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___S               8
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___M 0x000000E0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___S               5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___S               2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2     (0x005F8818)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___POR 0x2B000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___S              24

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0    (0x005F881C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1    (0x005F8820)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2    (0x005F8824)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3    (0x005F8828)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4    (0x005F882C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5    (0x005F8830)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6    (0x005F8834)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7    (0x005F8838)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8    (0x005F883C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9    (0x005F8840)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10   (0x005F8844)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11   (0x005F8848)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12   (0x005F884C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13   (0x005F8850)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14   (0x005F8854)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15   (0x005F8858)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16   (0x005F885C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17   (0x005F8860)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18   (0x005F8864)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19   (0x005F8868)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20   (0x005F886C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21   (0x005F8870)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22   (0x005F8874)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23   (0x005F8878)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24   (0x005F887C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25   (0x005F8880)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26   (0x005F8884)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27   (0x005F8888)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28   (0x005F888C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29   (0x005F8890)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30   (0x005F8894)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31   (0x005F8898)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32   (0x005F889C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33   (0x005F88A0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34   (0x005F88A4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35   (0x005F88A8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36   (0x005F88AC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37   (0x005F88B0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38   (0x005F88B4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39   (0x005F88B8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40   (0x005F88BC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41   (0x005F88C0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42   (0x005F88C4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43   (0x005F88C8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44   (0x005F88CC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45   (0x005F88D0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46   (0x005F88D4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47   (0x005F88D8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48   (0x005F88DC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49   (0x005F88E0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50   (0x005F88E4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51   (0x005F88E8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52   (0x005F88EC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53   (0x005F88F0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54   (0x005F88F4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55   (0x005F88F8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56   (0x005F88FC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57   (0x005F8900)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58   (0x005F8904)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59   (0x005F8908)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60   (0x005F890C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61   (0x005F8910)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62   (0x005F8914)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63   (0x005F8918)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___POR 0x76000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___S              25

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0  (0x005F891C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1  (0x005F8920)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2  (0x005F8924)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3  (0x005F8928)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4  (0x005F892C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5  (0x005F8930)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6  (0x005F8934)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7  (0x005F8938)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8  (0x005F893C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9  (0x005F8940)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10 (0x005F8944)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11 (0x005F8948)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___POR 0x42400000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___POR 0x21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12 (0x005F894C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___POR 0x40200000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13 (0x005F8950)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___POR 0x10080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14 (0x005F8954)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___POR 0x08040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15 (0x005F8958)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16 (0x005F895C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___POR 0x40100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17 (0x005F8960)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___POR 0x20080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18 (0x005F8964)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___POR 0x42100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___POR 0x21
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19 (0x005F8968)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___POR 0x80200000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___POR 0x40
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20 (0x005F896C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___POR 0x44100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___POR 0x22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21 (0x005F8970)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___POR 0x30100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___POR 0x18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22 (0x005F8974)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___POR 0x50100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___POR 0x28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23 (0x005F8978)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___POR 0x84100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___POR 0x42
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24 (0x005F897C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___POR 0x90100000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___POR 0x48
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25 (0x005F8980)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___POR 0x88080000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___POR 0x44
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26 (0x005F8984)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___POR 0x88040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___POR 0x44
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27 (0x005F8988)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___POR 0xA0040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___POR 0x50
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28 (0x005F898C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___POR 0xC8040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___POR 0x64
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29 (0x005F8990)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___POR 0xD8040000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___POR 0x6C
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30 (0x005F8994)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___POR 0xF2000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___POR 0x79
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31 (0x005F8998)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___POR 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___POR 0x7F
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32 (0x005F899C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33 (0x005F89A0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34 (0x005F89A4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35 (0x005F89A8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36 (0x005F89AC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37 (0x005F89B0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38 (0x005F89B4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39 (0x005F89B8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40 (0x005F89BC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41 (0x005F89C0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42 (0x005F89C4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43 (0x005F89C8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44 (0x005F89CC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45 (0x005F89D0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46 (0x005F89D4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47 (0x005F89D8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48 (0x005F89DC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49 (0x005F89E0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50 (0x005F89E4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51 (0x005F89E8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52 (0x005F89EC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53 (0x005F89F0)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54 (0x005F89F4)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55 (0x005F89F8)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56 (0x005F89FC)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57 (0x005F8A00)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58 (0x005F8A04)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59 (0x005F8A08)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60 (0x005F8A0C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61 (0x005F8A10)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62 (0x005F8A14)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63 (0x005F8A18)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___M 0xFE000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___M 0xFFFC0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___S              18

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0       (0x005F8A1C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___M 0xFF800000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___S              23

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1       (0x005F8A20)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___M 0x7F000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___S              16

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0           (0x005F8A24)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___M    0xFFFFC000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___S                 14

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT        (0x005F8A28)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___RWC  QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___S              28
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___S              25
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___M 0x01FC0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___S              11
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___S               5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___S               5

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0         (0x005F8A30)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___POR 0x6D55B000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___S              20
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___S              18
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___S              15
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___S              12
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___M  0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___S               12

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE         (0x005F8A34)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___RWC   QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___POR 0xB4000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___M  0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___S               26

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB           (0x005F8A38)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___RWC     QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___POR  0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___S              29
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___S              26
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___M    0xFF800000   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___S                 23

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0        (0x005F8A3C)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___S               0

#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1        (0x005F8A40)
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___RWC  QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___S               0
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG    (0x005F9000)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___POR 0x44FE5111
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___POR 0x44FE5111
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL (0x005F9004)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___S              22

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0 (0x005F9008)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___POR 0x8C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___POR 0xC
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1 (0x005F900C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___POR 0x30C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___POR 0xC
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0 (0x005F9010)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___POR 0x62409760
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1 (0x005F9014)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___POR 0x63009D60
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2 (0x005F9018)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___POR 0x6360A360
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___POR 0x1B
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3 (0x005F901C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___POR 0x6380A860
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___POR 0x1C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4 (0x005F9020)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___POR 0x628E9080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0E
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5 (0x005F9024)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___POR 0x62809080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6 (0x005F9028)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___POR 0x03E29880
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x02
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7 (0x005F902C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___POR 0x06209080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___POR 0x31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0 (0x005F9030)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1 (0x005F9034)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___POR 0x0A320000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___POR 0x05
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___POR 0x06
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2 (0x005F9038)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___POR 0x14520000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3 (0x005F903C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___POR 0x1E7A0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4 (0x005F9040)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___POR 0x28930000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___POR 0x14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___POR 0x12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5 (0x005F9044)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___POR 0x3CC20000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___POR 0x1E
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___POR 0x18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6 (0x005F9048)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7 (0x005F904C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___POR 0x65A90000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___POR 0x32
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___POR 0x35
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0    (0x005F9080)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___M 0x0003E000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___M 0x00001800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___M 0x000003C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___M 0x0000001C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___M 0xFFFFFFFC   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___S               2

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT (0x005F9084)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___S              26

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1    (0x005F9088)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___S              23
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2    (0x005F908C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___M 0xFFFF8000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___S              15

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0 (0x005F9090)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1 (0x005F9094)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S              27
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___M 0xFFF00000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___S              20

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL (0x005F9098)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S              26
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___M 0xFE000000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___S              25

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0 (0x005F909C)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___M 0x1FE00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S              11
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___S               5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___M 0xFFFFFFE0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___S               5

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1 (0x005F90A0)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___S              31
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___M 0x01F80000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___S              16

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2 (0x005F90A4)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___S              19
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___S              19

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0  (0x005F90A8)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___POR 0x20280E00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___POR 0x2
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___M 0x1FC00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___S              22
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S               9
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___M 0xFFFE1E00   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___S               9

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL (0x005F90AC)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0 (0x005F90B0)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___POR 0x520103C0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___POR 0x1
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___S              30
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___S              29
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___S              25
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___S              17
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___M 0x00003C00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___S               7
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___S               6
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___M 0xFFFFBFC0   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___S               6

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1 (0x005F90B4)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___POR 0xF
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___S              20
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___S              16
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___S               4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___S               0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___S               0

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2 (0x005F90B8)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___POR 0x00968000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___POR 0x5
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___S              28
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___S              24
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___S              18
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___S              12
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___S              12

#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE (0x005F90BC)
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___POR 0x000002
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG    (0x005F9300)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___POR 0x33FE5111
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___POR 0x33FE5111
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL (0x005F9304)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___M 0xFFFF0000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___S              16

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0 (0x005F9308)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___POR 0x04101800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1 (0x005F930C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___POR 0x04101800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0 (0x005F9310)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1 (0x005F9314)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2 (0x005F9318)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3 (0x005F931C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4 (0x005F9320)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5 (0x005F9324)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6 (0x005F9328)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7 (0x005F932C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8 (0x005F9330)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9 (0x005F9334)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___POR 0x06009000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x00C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10 (0x005F9338)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___POR 0x07009000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x00E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x01
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11 (0x005F933C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___POR 0x07819000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12 (0x005F9340)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___POR 0x0A821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x015
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13 (0x005F9344)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___POR 0x0B821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x017
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14 (0x005F9348)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___POR 0x10821000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x021
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15 (0x005F934C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___POR 0x11829000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x023
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16 (0x005F9350)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___POR 0x13029000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x026
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x05
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17 (0x005F9354)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___POR 0x14831000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x029
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18 (0x005F9358)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___POR 0x18831000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x031
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19 (0x005F935C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___POR 0x1B031000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x036
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x06
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20 (0x005F9360)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___POR 0x1D839000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x03B
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21 (0x005F9364)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___POR 0x24841000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x049
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x08
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22 (0x005F9368)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___POR 0x29849000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x053
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x09
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23 (0x005F936C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___POR 0x30861000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x061
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x0C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24 (0x005F9370)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___POR 0x34079000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x068
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25 (0x005F9374)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___POR 0x3A0A1000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x074
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26 (0x005F9378)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___POR 0x3E0C9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x07C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27 (0x005F937C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___POR 0x4A0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x094
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28 (0x005F9380)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___POR 0x550F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0AA
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29 (0x005F9384)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___POR 0x5E0F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0BC
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30 (0x005F9388)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___POR 0x6D8F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0DB
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31 (0x005F938C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___POR 0x7F8F9000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x0FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x1F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0 (0x005F9390)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1 (0x005F9394)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2 (0x005F9398)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3 (0x005F939C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4 (0x005F93A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5 (0x005F93A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6 (0x005F93A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7 (0x005F93AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___S              29

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0 (0x005F93B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___POR 0xD02EE80E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___POR 0x007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1 (0x005F93B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___POR 0xD02EE80E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___POR 0x007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2 (0x005F93B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___POR 0xD02EE81E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3 (0x005F93BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___POR 0xD02EE81E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___POR 0x00F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4 (0x005F93C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___POR 0xD02EE87E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___POR 0x03F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5 (0x005F93C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___POR 0xD02EE87E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___POR 0x1A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___POR 0x03F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___M 0x000003FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0 (0x005F93D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1 (0x005F93D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2 (0x005F93D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3 (0x005F93DC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4 (0x005F93E0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5 (0x005F93E4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0 (0x005F93F0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1 (0x005F93F4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2 (0x005F93F8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3 (0x005F93FC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4 (0x005F9400)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5 (0x005F9404)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___POR 0x57000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___POR 0x0A
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0 (0x005F9410)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___POR 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1 (0x005F9414)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___POR 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2 (0x005F9418)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___POR 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3 (0x005F941C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___POR 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___POR 0x0F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4 (0x005F9420)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___POR 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5 (0x005F9424)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___POR 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___POR 0x3F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___M 0xFF000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___S              24

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0 (0x005F9430)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1 (0x005F9434)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2 (0x005F9438)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3 (0x005F943C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4 (0x005F9440)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5 (0x005F9444)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___POR 0x882E3400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0 (0x005F9450)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___POR 0x10040000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x040
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x040
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1 (0x005F9454)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___POR 0x18050000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x060
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x050
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2 (0x005F9458)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___POR 0x18050000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x060
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x050
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3 (0x005F945C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___POR 0x1B05C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x06C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x05C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4 (0x005F9460)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___POR 0x1B05C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x06C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x05C
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5 (0x005F9464)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___POR 0x1BC5F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x06F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x05F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___M 0xFFFFF000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___S              12

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0    (0x005F9470)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1    (0x005F9474)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2    (0x005F9478)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___M 0x0000F800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3    (0x005F947C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___M 0x0007FC00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___M 0x000001FE
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___S               1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___S               1

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4    (0x005F9480)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___M 0x07C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___M 0x00000078
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___S               3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___M 0xFFFFFFF8   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___S               3

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5    (0x005F9484)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___M 0x07FE0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___M 0x0000FFC0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___M 0xFFFFFFC0   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___S               6

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0 (0x005F9488)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___POR 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___M 0x000FC000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___S              14

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1 (0x005F948C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___M 0xFFF7FC00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___S              10

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2 (0x005F9490)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0 (0x005F9494)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S              18
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S              14
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00003800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___M 0xFFFFF800   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___S              11

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1 (0x005F9498)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2 (0x005F949C)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___M 0x7C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___M 0x03E00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___S              13
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___S               6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___S               3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3 (0x005F94A0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___M 0x1FF00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___M 0x000FF000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___S              10
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S               5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4 (0x005F94A4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S               9
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFE00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___S               9

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5 (0x005F94A8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___S              22

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0 (0x005F94AC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___S              27

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0 (0x005F94B0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___POR 0x118A0E00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___S              17
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___M 0x00018000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___S              15
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___S              11
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___M 0xFFFFFF00   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___S               8

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0 (0x005F94B4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___POR 0x74000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0 (0x005F94B8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1 (0x005F94BC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___POR 0x00FF00FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S              12
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S               4
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL (0x005F94C0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___POR 0x04000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___M 0xFC000000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___S              26

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE (0x005F94C4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0 (0x005F94C8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___POR 0xAE000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___S              21
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___M 0xFFE00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___S              21

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0 (0x005F94CC)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___POR 0xAA000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___POR 0x5
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___M 0x01C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___S              22

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY (0x005F94D0)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___S              16
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___S               8
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___S               0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___S               0

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD (0x005F94D4)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___POR 0x08B80000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___S              30
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___S              25
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___S              23
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___M 0x00780000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___S              19
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___M 0xFFF80000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___S              19

#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR (0x005F94D8)
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___POR 0x6C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S              29
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___S              26
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S              24
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___M 0xFDF00000   
#define   PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___S              20

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0  (0x005FA000)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___M 0x00000001   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT (0x005FA004)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0 (0x005FA040)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___POR 0x000A0026
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___S               1

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1 (0x005FA044)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___POR 0x00004020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___M 0x0007FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA (0x005FA048)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0   (0x005FA080)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___POR 0x0200E8B6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___M 0x03C2FCFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1   (0x005FA084)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___POR 0x00F80204
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___M 0x00FF03FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2   (0x005FA088)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___POR 0xECA86420
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3   (0x005FA08C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___M 0x000000F1   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0 (0x005FA090)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0 (0x005FA094)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___M 0xC03FFC30   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1 (0x005FA098)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___M 0x0CFFF000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___S              12

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2 (0x005FA09C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___POR 0x000C1010
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___M 0x001FFF3F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3 (0x005FA0A0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___POR 0x0000B880
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___M 0x1FFCFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4 (0x005FA0A4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___POR 0x01010840
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___M 0x1B07FFF0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0    (0x005FA0A8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___POR 0x1D186008
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___POR 0x8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___M 0x9FFFFE0F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1    (0x005FA0AC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___POR 0x00000840
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___M 0x00000DFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0 (0x005FA0B0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___POR 0x036E36DC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1 (0x005FA0B4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2 (0x005FA0B8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___M 0x0003FFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2    (0x005FA0BC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___POR 0x68000104
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___S              25
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S               1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___M 0xFFFFFFFE   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___S               1

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3    (0x005FA0C0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___POR 0x6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S              26
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S              20
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___M 0xFFFE7FE0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___S               5

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4    (0x005FA0C4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___POR 0x00000492
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5    (0x005FA0C8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___M 0xF0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___S              28

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST   (0x005FA0CC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___M 0x80000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___S              31

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV (0x005FA0D0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___M 0x000003F0   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___S               4

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0   (0x005FA100)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___POR 0x1B000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___M 0xFF8001FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0 (0x005FA104)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S              23
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S               4
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___M 0xFF80001F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0 (0x005FA140)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___M 0xE0000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___S              29

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0 (0x005FA144)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0    (0x005FA148)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___POR 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___M 0x78000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___M 0xF8000000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___S              27

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0 (0x005FA14C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___S              22
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___M 0xFFC00000   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___S              22

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1    (0x005FA180)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___POR 0x073D11C0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___POR 0xC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S              29
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___S              21
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2    (0x005FA184)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___POR 0x00900090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___POR 0x0090
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0 (0x005FA188)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4    (0x005FA18C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___POR 0x22685349
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___S              31
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S              28
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S              27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___M 0x00060000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5    (0x005FA190)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___POR 0x004D4D4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___POR 0x4D
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6    (0x005FA194)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___POR 0x079E79E7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___S              30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7    (0x005FA198)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___POR 0x27C27C27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0 (0x005FA19C)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___POR 0x00008399
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___S              24
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9    (0x005FA1A0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0 (0x005FA1A4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___POR 0x01010000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0 (0x005FA1A8)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S              16
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0 (0x005FA1AC)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S              17
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13   (0x005FA1B0)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___POR 0x00000001
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___POR 0x1
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___S               3
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___S               0

#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14 (0x005FA1B4)
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___POR 0x00
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S              19
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S              18
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___S              15
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___S              14
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S              13
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S              12
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S              11
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S              10
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___S               9
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___S               8
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S               7
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___S               6
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___S               5
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___S               0
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG  (0x005FA400)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0   (0x005FA404)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1   (0x005FA408)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL    (0x005FA40C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___M 0x00000004
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___S               2
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___M 0x00000002
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___S               1
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___M 0x00000007   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING (0x005FA410)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S               4
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___M 0x000001FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET (0x005FA414)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0  (0x005FA418)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1  (0x005FA41C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0 (0x005FA420)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S              16
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S               8
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___M 0x01FFF7FF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I (0x005FA424)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q (0x005FA428)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S              12
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG  (0x005FA42C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S              23
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S              22
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S              11
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I (0x005FA430)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q (0x005FA434)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___M 0x7FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM (0x005FA438)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___POR 0x000003FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S              29
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S              28
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S              24
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S              10
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___M 0x3F0FFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL (0x005FA43C)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___M 0x07800000   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___S              23

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0 (0x005FA440)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___M 0x20000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___S              29
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___M 0x18000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___S              27
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___M 0x07FC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___S               9
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___S               0

#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1 (0x005FA444)
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___POR 0x000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___M 0x07FC0000
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___S              18
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___S               9
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___S               0
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___M 0x07FFFFFF   
#define   PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG    (0x005FA580)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG    (0x005FA584)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0     (0x005FA588)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1     (0x005FA58C)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0     (0x005FA590)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___POR 0x000C5000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___POR 0xC
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___POR 0x5
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___M 0x000F0000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___M 0x0000F000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___M 0x00000200
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___S               7
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___S               6
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___M 0x001FF7FC   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___S               2

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1     (0x005FA594)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___POR 0x00000010
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___M 0x03000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___S              24
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___M 0x00C00000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S              19
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S              18
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S               6
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S               5
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___M 0x03FFFF71   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1       (0x005FA598)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2       (0x005FA59C)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___POR 0x00000030
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___POR 0x3
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___M 0x000000F0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___M 0x000001FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3       (0x005FA5A0)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4       (0x005FA5A4)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5       (0x005FA5A8)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6       (0x005FA5AC)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___M 0x0000007F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7       (0x005FA5B0)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___M 0x0000003F
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___M 0x0000003F   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8       (0x005FA5B4)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9       (0x005FA5B8)
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00 (0x005FA5C0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01 (0x005FA5C4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02 (0x005FA5C8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03 (0x005FA5CC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04 (0x005FA5D0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05 (0x005FA5D4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06 (0x005FA5D8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07 (0x005FA5DC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08 (0x005FA5E0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09 (0x005FA5E4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10 (0x005FA5E8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11 (0x005FA5EC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12 (0x005FA5F0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13 (0x005FA5F4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14 (0x005FA5F8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15 (0x005FA5FC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16 (0x005FA600)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17 (0x005FA604)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18 (0x005FA608)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19 (0x005FA60C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20 (0x005FA610)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21 (0x005FA614)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22 (0x005FA618)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23 (0x005FA61C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24 (0x005FA620)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25 (0x005FA624)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26 (0x005FA628)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27 (0x005FA62C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28 (0x005FA630)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29 (0x005FA634)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30 (0x005FA638)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31 (0x005FA63C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00 (0x005FA640)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01 (0x005FA644)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02 (0x005FA648)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03 (0x005FA64C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04 (0x005FA650)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05 (0x005FA654)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06 (0x005FA658)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07 (0x005FA65C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08 (0x005FA660)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09 (0x005FA664)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10 (0x005FA668)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11 (0x005FA66C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12 (0x005FA670)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13 (0x005FA674)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14 (0x005FA678)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15 (0x005FA67C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16 (0x005FA680)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17 (0x005FA684)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18 (0x005FA688)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19 (0x005FA68C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20 (0x005FA690)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21 (0x005FA694)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22 (0x005FA698)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23 (0x005FA69C)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24 (0x005FA6A0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25 (0x005FA6A4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26 (0x005FA6A8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27 (0x005FA6AC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28 (0x005FA6B0)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29 (0x005FA6B4)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30 (0x005FA6B8)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___S               0

#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31 (0x005FA6BC)
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___POR 0x00000020
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0 (0x005FA6C0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1 (0x005FA6C4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2 (0x005FA6C8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3 (0x005FA6CC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4 (0x005FA6D0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5 (0x005FA6D4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6 (0x005FA6D8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7 (0x005FA6DC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8 (0x005FA6E0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0 (0x005FA6E4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1 (0x005FA6E8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2 (0x005FA6EC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3 (0x005FA6F0)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4 (0x005FA6F4)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5 (0x005FA6F8)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6 (0x005FA6FC)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7 (0x005FA700)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8 (0x005FA704)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1 (0x005FA708)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S              26
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S              15
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S              14
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___S              13
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S               7
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___S               5
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___M 0x1FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2 (0x005FA70C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S              31
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3 (0x005FA710)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___POR 0x000001FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4 (0x005FA714)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1 (0x005FA718)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2 (0x005FA71C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S              24
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3 (0x005FA720)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S              31
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S              22
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___S              16
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S              10
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___S               4
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S               3
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___S               1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4 (0x005FA724)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL (0x005FA728)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___POR 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S               2
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___M 0x00000007   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG (0x005FA72C)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S              11
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___S               9
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___S               8
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___M 0x0001FFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG (0x005FA730)
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___S               0

#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0 (0x005FA734)
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___M 0x30000000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___S              28
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___S              23
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___S              20
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___S              18
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___S              17
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___S              12
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___S               0
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___M 0x30B67007   
#define   PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG (0x005FA740)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___POR 0x10000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___M 0xF0000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___S              28
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___M 0x0FFF0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0  (0x005FA744)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___POR 0xADC1ADC0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___POR 0xADC1ADC0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1     (0x005FA748)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL       (0x005FA74C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___POR 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___M 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___S              13
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___M 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___M 0x00000C00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___M 0x00000006
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___M 0x003F7FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG     (0x005FA750)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___M 0x000007FD   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS  (0x005FA754)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___M 0x00000003   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0    (0x005FA758)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___S              31
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___M 0x40000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___S              30
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___M 0x20000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___S              29
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___M 0x1F800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___S              21
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___M 0x001E0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___M 0x0000FC00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___M 0xFFFFFC00   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___S              10

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1    (0x005FA75C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___M 0x03FE0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___M 0x00001FF0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___M 0x03FE1FF3   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2    (0x005FA760)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___M 0x0000FF00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___M 0x00000007
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___M 0x0003FF07   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3    (0x005FA764)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___POR 0x000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___M 0x00FFFFFF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___M 0xFFFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0  (0x005FA768)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___POR 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___POR 0x3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___M 0x00300000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___M 0x00030000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___S              15
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___M 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___M 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___S              10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___M 0x00000040
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___M 0x00000010
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG    (0x005FA76C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___S              25
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___M 0x00380000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___M 0x0000FFF0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___M 0x0FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0 (0x005FA770)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1 (0x005FA774)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2 (0x005FA778)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0 (0x005FA77C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1 (0x005FA780)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2 (0x005FA784)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0 (0x005FA788)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1 (0x005FA78C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2 (0x005FA790)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0 (0x005FA794)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___POR 0x02020410
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___POR 0x80
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___POR 0x40
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___POR 0x20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___POR 0x10
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___M 0x03FC0000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___M 0x0003F800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___M 0x000007E0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___S               5
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1 (0x005FA798)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___POR 0x10040100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___POR 0x100
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___M 0x3FF80000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___M 0x0007FE00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___S               9
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2 (0x005FA79C)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___POR 0x00000200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___POR 0x200
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0 (0x005FA7A0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___POR 0x00400001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___POR 0x1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___M 0xFF000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___S              21
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___M 0x00100000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___S              20
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___S              19
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___S              18
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___M 0x00020000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___S              17
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___M 0x00010000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___S              16
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___M 0x0000C000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___S              14
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___M 0x00003000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___M 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___M 0x00000700
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___M 0x000000C0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___S               6
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___M 0x00000030
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___M 0xFF7FFFF7   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1 (0x005FA7A4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___M 0x00000002
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___S               1
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___M 0x0000000F   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0 (0x005FA7A8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1 (0x005FA7AC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2 (0x005FA7B0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0 (0x005FA7B4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1 (0x005FA7B8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2 (0x005FA7BC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0 (0x005FA7C0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1 (0x005FA7C4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2 (0x005FA7C8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0 (0x005FA7CC)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___M 0x01000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___M 0x00800000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___S              23
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___M 0x01FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1 (0x005FA7D0)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___M 0x00400000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___S              22
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___M 0x007FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2 (0x005FA7D4)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___POR 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___POR 0x7FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___M 0x003FF800
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___S              11
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___M 0x003FFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG (0x005FA7D8)
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___M 0x00000008
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___S               3
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___M 0x00000004
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___M 0x0000000C   
#define   PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___S               2

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1 (0x005FA800)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2 (0x005FA804)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3 (0x005FA808)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4 (0x005FA80C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5 (0x005FA810)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6 (0x005FA814)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7 (0x005FA818)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1 (0x005FA840)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2 (0x005FA844)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3 (0x005FA848)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4 (0x005FA84C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5 (0x005FA850)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6 (0x005FA854)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7 (0x005FA858)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1 (0x005FA880)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2 (0x005FA884)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3 (0x005FA888)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4 (0x005FA88C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5 (0x005FA890)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6 (0x005FA894)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7 (0x005FA898)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1 (0x005FA8C0)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2 (0x005FA8C4)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3 (0x005FA8C8)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___POR 0x00000400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___POR 0x400
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4 (0x005FA8CC)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___POR 0x00000800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___POR 0x800
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5 (0x005FA8D0)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___POR 0x00001000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___POR 0x1000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6 (0x005FA8D4)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___POR 0x00002000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___POR 0x2000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7 (0x005FA8D8)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___POR 0x00004000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___POR 0x4000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1 (0x005FA900)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2 (0x005FA904)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3 (0x005FA908)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4 (0x005FA90C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5 (0x005FA910)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6 (0x005FA914)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7 (0x005FA918)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8 (0x005FA91C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9 (0x005FA920)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10 (0x005FA924)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11 (0x005FA928)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12 (0x005FA92C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13 (0x005FA930)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14 (0x005FA934)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15 (0x005FA938)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16 (0x005FA93C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17 (0x005FA940)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18 (0x005FA944)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19 (0x005FA948)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20 (0x005FA94C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21 (0x005FA950)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22 (0x005FA954)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23 (0x005FA958)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24 (0x005FA95C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25 (0x005FA960)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26 (0x005FA964)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___M 0x000003FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___M 0x000003FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27 (0x005FA968)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___M 0x000007FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___M 0x000007FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28 (0x005FA96C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___POR 0x000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___M 0x00000FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___M 0x00000FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29 (0x005FA970)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___M 0x00001FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___M 0x00001FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30 (0x005FA974)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31 (0x005FA978)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___M 0x00007FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___M 0x00007FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32 (0x005FA97C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___M 0x00000080
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___S               7
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33 (0x005FA980)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34 (0x005FA984)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35 (0x005FA988)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36 (0x005FA98C)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___M 0x00003FFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___M 0x00003FFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG (0x005FA990)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___M 0x00FFFF00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___M 0x00FFFFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE (0x005FA994)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___POR 0x00
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___M 0x000000FF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___M 0x000000FF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE (0x005FA998)
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___RWC QCSR_REG_RO    
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___POR 0x0000
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___M 0x0000FFFF
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___M 0x0000FFFF   
#define   PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___S               0

#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0 (0x005FA99C)
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___M 0xC0000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___S              30
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___M 0x08000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___S              27
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___M 0x07000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___S              24
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___S              12
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___M 0x00000300
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___S               8
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___M 0x00000070
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___S               4
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___M 0x00000003
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___M 0xCF00737F   
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___S               0

#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1 (0x005FA9A0)
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___POR 0x0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___M 0x0000000C
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___S               2
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___M 0x00000001
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___S               0
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___M 0x0000000D   
#define   PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0    (0x005FC000)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1    (0x005FC004)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2    (0x005FC008)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3    (0x005FC00C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4    (0x005FC010)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5    (0x005FC014)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6    (0x005FC018)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7    (0x005FC01C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8    (0x005FC020)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9    (0x005FC024)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10   (0x005FC028)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11   (0x005FC02C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12   (0x005FC030)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13   (0x005FC034)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14   (0x005FC038)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15   (0x005FC03C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16   (0x005FC040)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17   (0x005FC044)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18   (0x005FC048)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19   (0x005FC04C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20   (0x005FC050)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21   (0x005FC054)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22   (0x005FC058)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23   (0x005FC05C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24   (0x005FC060)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25   (0x005FC064)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26   (0x005FC068)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27   (0x005FC06C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28   (0x005FC070)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29   (0x005FC074)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30   (0x005FC078)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31   (0x005FC07C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32   (0x005FC080)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33   (0x005FC084)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34   (0x005FC088)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35   (0x005FC08C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36   (0x005FC090)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37   (0x005FC094)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38   (0x005FC098)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39   (0x005FC09C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40   (0x005FC0A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41   (0x005FC0A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42   (0x005FC0A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43   (0x005FC0AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44   (0x005FC0B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45   (0x005FC0B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46   (0x005FC0B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47   (0x005FC0BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48   (0x005FC0C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49   (0x005FC0C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50   (0x005FC0C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51   (0x005FC0CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52   (0x005FC0D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53   (0x005FC0D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54   (0x005FC0D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55   (0x005FC0DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56   (0x005FC0E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57   (0x005FC0E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58   (0x005FC0E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59   (0x005FC0EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60   (0x005FC0F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61   (0x005FC0F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62   (0x005FC0F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63   (0x005FC0FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64   (0x005FC100)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65   (0x005FC104)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66   (0x005FC108)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67   (0x005FC10C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68   (0x005FC110)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69   (0x005FC114)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70   (0x005FC118)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71   (0x005FC11C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72   (0x005FC120)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73   (0x005FC124)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74   (0x005FC128)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75   (0x005FC12C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76   (0x005FC130)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77   (0x005FC134)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78   (0x005FC138)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79   (0x005FC13C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80   (0x005FC140)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81   (0x005FC144)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82   (0x005FC148)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83   (0x005FC14C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84   (0x005FC150)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85   (0x005FC154)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86   (0x005FC158)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87   (0x005FC15C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88   (0x005FC160)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89   (0x005FC164)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90   (0x005FC168)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91   (0x005FC16C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92   (0x005FC170)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93   (0x005FC174)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94   (0x005FC178)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95   (0x005FC17C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96   (0x005FC180)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97   (0x005FC184)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98   (0x005FC188)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99   (0x005FC18C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100  (0x005FC190)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101  (0x005FC194)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102  (0x005FC198)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103  (0x005FC19C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104  (0x005FC1A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105  (0x005FC1A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106  (0x005FC1A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107  (0x005FC1AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108  (0x005FC1B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109  (0x005FC1B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110  (0x005FC1B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111  (0x005FC1BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112  (0x005FC1C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113  (0x005FC1C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114  (0x005FC1C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115  (0x005FC1CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116  (0x005FC1D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117  (0x005FC1D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118  (0x005FC1D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119  (0x005FC1DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120  (0x005FC1E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121  (0x005FC1E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122  (0x005FC1E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123  (0x005FC1EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124  (0x005FC1F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125  (0x005FC1F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126  (0x005FC1F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127  (0x005FC1FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128  (0x005FC200)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129  (0x005FC204)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130  (0x005FC208)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131  (0x005FC20C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132  (0x005FC210)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133  (0x005FC214)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134  (0x005FC218)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135  (0x005FC21C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136  (0x005FC220)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137  (0x005FC224)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138  (0x005FC228)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139  (0x005FC22C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140  (0x005FC230)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141  (0x005FC234)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142  (0x005FC238)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143  (0x005FC23C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144  (0x005FC240)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145  (0x005FC244)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146  (0x005FC248)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147  (0x005FC24C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148  (0x005FC250)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149  (0x005FC254)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150  (0x005FC258)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151  (0x005FC25C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152  (0x005FC260)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153  (0x005FC264)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154  (0x005FC268)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155  (0x005FC26C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156  (0x005FC270)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157  (0x005FC274)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158  (0x005FC278)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159  (0x005FC27C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160  (0x005FC280)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161  (0x005FC284)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162  (0x005FC288)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163  (0x005FC28C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164  (0x005FC290)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165  (0x005FC294)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166  (0x005FC298)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167  (0x005FC29C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168  (0x005FC2A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169  (0x005FC2A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170  (0x005FC2A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171  (0x005FC2AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172  (0x005FC2B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173  (0x005FC2B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174  (0x005FC2B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175  (0x005FC2BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176  (0x005FC2C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177  (0x005FC2C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178  (0x005FC2C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179  (0x005FC2CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180  (0x005FC2D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181  (0x005FC2D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182  (0x005FC2D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183  (0x005FC2DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184  (0x005FC2E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185  (0x005FC2E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186  (0x005FC2E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187  (0x005FC2EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188  (0x005FC2F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189  (0x005FC2F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190  (0x005FC2F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191  (0x005FC2FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192  (0x005FC300)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193  (0x005FC304)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194  (0x005FC308)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195  (0x005FC30C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196  (0x005FC310)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197  (0x005FC314)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198  (0x005FC318)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199  (0x005FC31C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200  (0x005FC320)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201  (0x005FC324)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202  (0x005FC328)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203  (0x005FC32C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204  (0x005FC330)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205  (0x005FC334)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206  (0x005FC338)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207  (0x005FC33C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208  (0x005FC340)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209  (0x005FC344)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210  (0x005FC348)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211  (0x005FC34C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212  (0x005FC350)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213  (0x005FC354)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214  (0x005FC358)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215  (0x005FC35C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216  (0x005FC360)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217  (0x005FC364)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218  (0x005FC368)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219  (0x005FC36C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220  (0x005FC370)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221  (0x005FC374)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222  (0x005FC378)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223  (0x005FC37C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224  (0x005FC380)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225  (0x005FC384)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226  (0x005FC388)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227  (0x005FC38C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228  (0x005FC390)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229  (0x005FC394)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230  (0x005FC398)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231  (0x005FC39C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232  (0x005FC3A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233  (0x005FC3A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234  (0x005FC3A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235  (0x005FC3AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236  (0x005FC3B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237  (0x005FC3B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238  (0x005FC3B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239  (0x005FC3BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240  (0x005FC3C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241  (0x005FC3C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242  (0x005FC3C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243  (0x005FC3CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244  (0x005FC3D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245  (0x005FC3D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246  (0x005FC3D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247  (0x005FC3DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248  (0x005FC3E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249  (0x005FC3E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250  (0x005FC3E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251  (0x005FC3EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252  (0x005FC3F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253  (0x005FC3F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254  (0x005FC3F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255  (0x005FC3FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256  (0x005FC400)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257  (0x005FC404)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258  (0x005FC408)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259  (0x005FC40C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260  (0x005FC410)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261  (0x005FC414)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262  (0x005FC418)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263  (0x005FC41C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264  (0x005FC420)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265  (0x005FC424)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266  (0x005FC428)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267  (0x005FC42C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268  (0x005FC430)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269  (0x005FC434)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270  (0x005FC438)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271  (0x005FC43C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272  (0x005FC440)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273  (0x005FC444)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274  (0x005FC448)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275  (0x005FC44C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276  (0x005FC450)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277  (0x005FC454)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278  (0x005FC458)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279  (0x005FC45C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280  (0x005FC460)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281  (0x005FC464)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282  (0x005FC468)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283  (0x005FC46C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284  (0x005FC470)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285  (0x005FC474)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286  (0x005FC478)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287  (0x005FC47C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288  (0x005FC480)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289  (0x005FC484)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290  (0x005FC488)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291  (0x005FC48C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292  (0x005FC490)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293  (0x005FC494)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294  (0x005FC498)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295  (0x005FC49C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296  (0x005FC4A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297  (0x005FC4A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298  (0x005FC4A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299  (0x005FC4AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300  (0x005FC4B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301  (0x005FC4B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302  (0x005FC4B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303  (0x005FC4BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304  (0x005FC4C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305  (0x005FC4C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306  (0x005FC4C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307  (0x005FC4CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308  (0x005FC4D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309  (0x005FC4D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310  (0x005FC4D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311  (0x005FC4DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312  (0x005FC4E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313  (0x005FC4E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314  (0x005FC4E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315  (0x005FC4EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316  (0x005FC4F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317  (0x005FC4F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318  (0x005FC4F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319  (0x005FC4FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320  (0x005FC500)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321  (0x005FC504)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322  (0x005FC508)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323  (0x005FC50C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324  (0x005FC510)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325  (0x005FC514)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326  (0x005FC518)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327  (0x005FC51C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328  (0x005FC520)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329  (0x005FC524)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330  (0x005FC528)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331  (0x005FC52C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332  (0x005FC530)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333  (0x005FC534)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334  (0x005FC538)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335  (0x005FC53C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336  (0x005FC540)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337  (0x005FC544)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338  (0x005FC548)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339  (0x005FC54C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340  (0x005FC550)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341  (0x005FC554)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342  (0x005FC558)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343  (0x005FC55C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344  (0x005FC560)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345  (0x005FC564)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346  (0x005FC568)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347  (0x005FC56C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348  (0x005FC570)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349  (0x005FC574)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350  (0x005FC578)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351  (0x005FC57C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352  (0x005FC580)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353  (0x005FC584)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354  (0x005FC588)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355  (0x005FC58C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356  (0x005FC590)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357  (0x005FC594)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358  (0x005FC598)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359  (0x005FC59C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360  (0x005FC5A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361  (0x005FC5A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362  (0x005FC5A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363  (0x005FC5AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364  (0x005FC5B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365  (0x005FC5B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366  (0x005FC5B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367  (0x005FC5BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368  (0x005FC5C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369  (0x005FC5C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370  (0x005FC5C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371  (0x005FC5CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372  (0x005FC5D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373  (0x005FC5D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374  (0x005FC5D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375  (0x005FC5DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376  (0x005FC5E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377  (0x005FC5E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378  (0x005FC5E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379  (0x005FC5EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380  (0x005FC5F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381  (0x005FC5F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382  (0x005FC5F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383  (0x005FC5FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384  (0x005FC600)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385  (0x005FC604)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386  (0x005FC608)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387  (0x005FC60C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388  (0x005FC610)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389  (0x005FC614)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390  (0x005FC618)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391  (0x005FC61C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392  (0x005FC620)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393  (0x005FC624)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394  (0x005FC628)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395  (0x005FC62C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396  (0x005FC630)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397  (0x005FC634)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398  (0x005FC638)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399  (0x005FC63C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400  (0x005FC640)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401  (0x005FC644)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402  (0x005FC648)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403  (0x005FC64C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404  (0x005FC650)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405  (0x005FC654)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406  (0x005FC658)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407  (0x005FC65C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408  (0x005FC660)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409  (0x005FC664)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410  (0x005FC668)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411  (0x005FC66C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412  (0x005FC670)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413  (0x005FC674)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414  (0x005FC678)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415  (0x005FC67C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416  (0x005FC680)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417  (0x005FC684)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418  (0x005FC688)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419  (0x005FC68C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420  (0x005FC690)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421  (0x005FC694)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422  (0x005FC698)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423  (0x005FC69C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424  (0x005FC6A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425  (0x005FC6A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426  (0x005FC6A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427  (0x005FC6AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428  (0x005FC6B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429  (0x005FC6B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430  (0x005FC6B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431  (0x005FC6BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432  (0x005FC6C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433  (0x005FC6C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434  (0x005FC6C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435  (0x005FC6CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436  (0x005FC6D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437  (0x005FC6D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438  (0x005FC6D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439  (0x005FC6DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440  (0x005FC6E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441  (0x005FC6E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442  (0x005FC6E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443  (0x005FC6EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444  (0x005FC6F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445  (0x005FC6F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446  (0x005FC6F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447  (0x005FC6FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448  (0x005FC700)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449  (0x005FC704)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450  (0x005FC708)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451  (0x005FC70C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452  (0x005FC710)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453  (0x005FC714)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454  (0x005FC718)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455  (0x005FC71C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456  (0x005FC720)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457  (0x005FC724)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458  (0x005FC728)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459  (0x005FC72C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460  (0x005FC730)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461  (0x005FC734)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462  (0x005FC738)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463  (0x005FC73C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464  (0x005FC740)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465  (0x005FC744)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466  (0x005FC748)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467  (0x005FC74C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468  (0x005FC750)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469  (0x005FC754)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470  (0x005FC758)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471  (0x005FC75C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472  (0x005FC760)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473  (0x005FC764)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474  (0x005FC768)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475  (0x005FC76C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476  (0x005FC770)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477  (0x005FC774)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478  (0x005FC778)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479  (0x005FC77C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480  (0x005FC780)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481  (0x005FC784)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482  (0x005FC788)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483  (0x005FC78C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484  (0x005FC790)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485  (0x005FC794)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486  (0x005FC798)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487  (0x005FC79C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488  (0x005FC7A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489  (0x005FC7A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490  (0x005FC7A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491  (0x005FC7AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492  (0x005FC7B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493  (0x005FC7B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494  (0x005FC7B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495  (0x005FC7BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496  (0x005FC7C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497  (0x005FC7C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498  (0x005FC7C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499  (0x005FC7CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500  (0x005FC7D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501  (0x005FC7D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502  (0x005FC7D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503  (0x005FC7DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504  (0x005FC7E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505  (0x005FC7E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506  (0x005FC7E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507  (0x005FC7EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508  (0x005FC7F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509  (0x005FC7F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510  (0x005FC7F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511  (0x005FC7FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512  (0x005FC800)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513  (0x005FC804)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514  (0x005FC808)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515  (0x005FC80C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516  (0x005FC810)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517  (0x005FC814)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518  (0x005FC818)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519  (0x005FC81C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520  (0x005FC820)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521  (0x005FC824)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522  (0x005FC828)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523  (0x005FC82C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524  (0x005FC830)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525  (0x005FC834)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526  (0x005FC838)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527  (0x005FC83C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528  (0x005FC840)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529  (0x005FC844)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530  (0x005FC848)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531  (0x005FC84C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532  (0x005FC850)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533  (0x005FC854)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534  (0x005FC858)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535  (0x005FC85C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536  (0x005FC860)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537  (0x005FC864)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538  (0x005FC868)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539  (0x005FC86C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540  (0x005FC870)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541  (0x005FC874)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542  (0x005FC878)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543  (0x005FC87C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544  (0x005FC880)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545  (0x005FC884)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546  (0x005FC888)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547  (0x005FC88C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548  (0x005FC890)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549  (0x005FC894)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550  (0x005FC898)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551  (0x005FC89C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552  (0x005FC8A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553  (0x005FC8A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554  (0x005FC8A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555  (0x005FC8AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556  (0x005FC8B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557  (0x005FC8B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558  (0x005FC8B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559  (0x005FC8BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560  (0x005FC8C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561  (0x005FC8C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562  (0x005FC8C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563  (0x005FC8CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564  (0x005FC8D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565  (0x005FC8D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566  (0x005FC8D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567  (0x005FC8DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568  (0x005FC8E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569  (0x005FC8E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570  (0x005FC8E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571  (0x005FC8EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572  (0x005FC8F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573  (0x005FC8F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574  (0x005FC8F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575  (0x005FC8FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576  (0x005FC900)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577  (0x005FC904)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578  (0x005FC908)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579  (0x005FC90C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580  (0x005FC910)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581  (0x005FC914)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582  (0x005FC918)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583  (0x005FC91C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584  (0x005FC920)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585  (0x005FC924)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586  (0x005FC928)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587  (0x005FC92C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588  (0x005FC930)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589  (0x005FC934)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590  (0x005FC938)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591  (0x005FC93C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592  (0x005FC940)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593  (0x005FC944)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594  (0x005FC948)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595  (0x005FC94C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596  (0x005FC950)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597  (0x005FC954)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598  (0x005FC958)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599  (0x005FC95C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600  (0x005FC960)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601  (0x005FC964)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602  (0x005FC968)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603  (0x005FC96C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604  (0x005FC970)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605  (0x005FC974)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606  (0x005FC978)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607  (0x005FC97C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608  (0x005FC980)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609  (0x005FC984)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610  (0x005FC988)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611  (0x005FC98C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612  (0x005FC990)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613  (0x005FC994)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614  (0x005FC998)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615  (0x005FC99C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616  (0x005FC9A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617  (0x005FC9A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618  (0x005FC9A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619  (0x005FC9AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620  (0x005FC9B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621  (0x005FC9B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622  (0x005FC9B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623  (0x005FC9BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624  (0x005FC9C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625  (0x005FC9C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626  (0x005FC9C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627  (0x005FC9CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628  (0x005FC9D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629  (0x005FC9D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630  (0x005FC9D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631  (0x005FC9DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632  (0x005FC9E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633  (0x005FC9E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634  (0x005FC9E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635  (0x005FC9EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636  (0x005FC9F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637  (0x005FC9F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638  (0x005FC9F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639  (0x005FC9FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640  (0x005FCA00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641  (0x005FCA04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642  (0x005FCA08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643  (0x005FCA0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644  (0x005FCA10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645  (0x005FCA14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646  (0x005FCA18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647  (0x005FCA1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648  (0x005FCA20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649  (0x005FCA24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650  (0x005FCA28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651  (0x005FCA2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652  (0x005FCA30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653  (0x005FCA34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654  (0x005FCA38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655  (0x005FCA3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656  (0x005FCA40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657  (0x005FCA44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658  (0x005FCA48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659  (0x005FCA4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660  (0x005FCA50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661  (0x005FCA54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662  (0x005FCA58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663  (0x005FCA5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664  (0x005FCA60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665  (0x005FCA64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666  (0x005FCA68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667  (0x005FCA6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668  (0x005FCA70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669  (0x005FCA74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670  (0x005FCA78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671  (0x005FCA7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672  (0x005FCA80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673  (0x005FCA84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674  (0x005FCA88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675  (0x005FCA8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676  (0x005FCA90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677  (0x005FCA94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678  (0x005FCA98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679  (0x005FCA9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680  (0x005FCAA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681  (0x005FCAA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682  (0x005FCAA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683  (0x005FCAAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684  (0x005FCAB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685  (0x005FCAB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686  (0x005FCAB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687  (0x005FCABC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688  (0x005FCAC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689  (0x005FCAC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690  (0x005FCAC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691  (0x005FCACC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692  (0x005FCAD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693  (0x005FCAD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694  (0x005FCAD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695  (0x005FCADC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696  (0x005FCAE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697  (0x005FCAE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698  (0x005FCAE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699  (0x005FCAEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700  (0x005FCAF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701  (0x005FCAF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702  (0x005FCAF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703  (0x005FCAFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704  (0x005FCB00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705  (0x005FCB04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706  (0x005FCB08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707  (0x005FCB0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708  (0x005FCB10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709  (0x005FCB14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710  (0x005FCB18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711  (0x005FCB1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712  (0x005FCB20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713  (0x005FCB24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714  (0x005FCB28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715  (0x005FCB2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716  (0x005FCB30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717  (0x005FCB34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718  (0x005FCB38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719  (0x005FCB3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720  (0x005FCB40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721  (0x005FCB44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722  (0x005FCB48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723  (0x005FCB4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724  (0x005FCB50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725  (0x005FCB54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726  (0x005FCB58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727  (0x005FCB5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728  (0x005FCB60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729  (0x005FCB64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730  (0x005FCB68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731  (0x005FCB6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732  (0x005FCB70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733  (0x005FCB74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734  (0x005FCB78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735  (0x005FCB7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736  (0x005FCB80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737  (0x005FCB84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738  (0x005FCB88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739  (0x005FCB8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740  (0x005FCB90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741  (0x005FCB94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742  (0x005FCB98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743  (0x005FCB9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744  (0x005FCBA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745  (0x005FCBA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746  (0x005FCBA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747  (0x005FCBAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748  (0x005FCBB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749  (0x005FCBB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750  (0x005FCBB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751  (0x005FCBBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752  (0x005FCBC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753  (0x005FCBC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754  (0x005FCBC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755  (0x005FCBCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756  (0x005FCBD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757  (0x005FCBD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758  (0x005FCBD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759  (0x005FCBDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760  (0x005FCBE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761  (0x005FCBE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762  (0x005FCBE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763  (0x005FCBEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764  (0x005FCBF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765  (0x005FCBF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766  (0x005FCBF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767  (0x005FCBFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768  (0x005FCC00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769  (0x005FCC04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770  (0x005FCC08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771  (0x005FCC0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772  (0x005FCC10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773  (0x005FCC14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774  (0x005FCC18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775  (0x005FCC1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776  (0x005FCC20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777  (0x005FCC24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778  (0x005FCC28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779  (0x005FCC2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780  (0x005FCC30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781  (0x005FCC34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782  (0x005FCC38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783  (0x005FCC3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784  (0x005FCC40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785  (0x005FCC44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786  (0x005FCC48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787  (0x005FCC4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788  (0x005FCC50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789  (0x005FCC54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790  (0x005FCC58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791  (0x005FCC5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792  (0x005FCC60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793  (0x005FCC64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794  (0x005FCC68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795  (0x005FCC6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796  (0x005FCC70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797  (0x005FCC74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798  (0x005FCC78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799  (0x005FCC7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800  (0x005FCC80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801  (0x005FCC84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802  (0x005FCC88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803  (0x005FCC8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804  (0x005FCC90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805  (0x005FCC94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806  (0x005FCC98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807  (0x005FCC9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808  (0x005FCCA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809  (0x005FCCA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810  (0x005FCCA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811  (0x005FCCAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812  (0x005FCCB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813  (0x005FCCB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814  (0x005FCCB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815  (0x005FCCBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816  (0x005FCCC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817  (0x005FCCC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818  (0x005FCCC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819  (0x005FCCCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820  (0x005FCCD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821  (0x005FCCD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822  (0x005FCCD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823  (0x005FCCDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824  (0x005FCCE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825  (0x005FCCE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826  (0x005FCCE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827  (0x005FCCEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828  (0x005FCCF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829  (0x005FCCF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830  (0x005FCCF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831  (0x005FCCFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832  (0x005FCD00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833  (0x005FCD04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834  (0x005FCD08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835  (0x005FCD0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836  (0x005FCD10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837  (0x005FCD14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838  (0x005FCD18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839  (0x005FCD1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840  (0x005FCD20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841  (0x005FCD24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842  (0x005FCD28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843  (0x005FCD2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844  (0x005FCD30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845  (0x005FCD34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846  (0x005FCD38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847  (0x005FCD3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848  (0x005FCD40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849  (0x005FCD44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850  (0x005FCD48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851  (0x005FCD4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852  (0x005FCD50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853  (0x005FCD54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854  (0x005FCD58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855  (0x005FCD5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856  (0x005FCD60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857  (0x005FCD64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858  (0x005FCD68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859  (0x005FCD6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860  (0x005FCD70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861  (0x005FCD74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862  (0x005FCD78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863  (0x005FCD7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864  (0x005FCD80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865  (0x005FCD84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866  (0x005FCD88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867  (0x005FCD8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868  (0x005FCD90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869  (0x005FCD94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870  (0x005FCD98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871  (0x005FCD9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872  (0x005FCDA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873  (0x005FCDA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874  (0x005FCDA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875  (0x005FCDAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876  (0x005FCDB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877  (0x005FCDB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878  (0x005FCDB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879  (0x005FCDBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880  (0x005FCDC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881  (0x005FCDC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882  (0x005FCDC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883  (0x005FCDCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884  (0x005FCDD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885  (0x005FCDD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886  (0x005FCDD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887  (0x005FCDDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888  (0x005FCDE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889  (0x005FCDE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890  (0x005FCDE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891  (0x005FCDEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892  (0x005FCDF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893  (0x005FCDF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894  (0x005FCDF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895  (0x005FCDFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896  (0x005FCE00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897  (0x005FCE04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898  (0x005FCE08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899  (0x005FCE0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900  (0x005FCE10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901  (0x005FCE14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902  (0x005FCE18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903  (0x005FCE1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904  (0x005FCE20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905  (0x005FCE24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906  (0x005FCE28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907  (0x005FCE2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908  (0x005FCE30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909  (0x005FCE34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910  (0x005FCE38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911  (0x005FCE3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912  (0x005FCE40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913  (0x005FCE44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914  (0x005FCE48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915  (0x005FCE4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916  (0x005FCE50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917  (0x005FCE54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918  (0x005FCE58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919  (0x005FCE5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920  (0x005FCE60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921  (0x005FCE64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922  (0x005FCE68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923  (0x005FCE6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924  (0x005FCE70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925  (0x005FCE74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926  (0x005FCE78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927  (0x005FCE7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928  (0x005FCE80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929  (0x005FCE84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930  (0x005FCE88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931  (0x005FCE8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932  (0x005FCE90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933  (0x005FCE94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934  (0x005FCE98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935  (0x005FCE9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936  (0x005FCEA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937  (0x005FCEA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938  (0x005FCEA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939  (0x005FCEAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940  (0x005FCEB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941  (0x005FCEB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942  (0x005FCEB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943  (0x005FCEBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944  (0x005FCEC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945  (0x005FCEC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946  (0x005FCEC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947  (0x005FCECC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948  (0x005FCED0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949  (0x005FCED4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950  (0x005FCED8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951  (0x005FCEDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952  (0x005FCEE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953  (0x005FCEE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954  (0x005FCEE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955  (0x005FCEEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956  (0x005FCEF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957  (0x005FCEF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958  (0x005FCEF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959  (0x005FCEFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960  (0x005FCF00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961  (0x005FCF04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962  (0x005FCF08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963  (0x005FCF0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964  (0x005FCF10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965  (0x005FCF14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966  (0x005FCF18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967  (0x005FCF1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968  (0x005FCF20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969  (0x005FCF24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970  (0x005FCF28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971  (0x005FCF2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972  (0x005FCF30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973  (0x005FCF34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974  (0x005FCF38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975  (0x005FCF3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976  (0x005FCF40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977  (0x005FCF44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978  (0x005FCF48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979  (0x005FCF4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980  (0x005FCF50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981  (0x005FCF54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982  (0x005FCF58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983  (0x005FCF5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984  (0x005FCF60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985  (0x005FCF64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986  (0x005FCF68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987  (0x005FCF6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988  (0x005FCF70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989  (0x005FCF74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990  (0x005FCF78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991  (0x005FCF7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992  (0x005FCF80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993  (0x005FCF84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994  (0x005FCF88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995  (0x005FCF8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996  (0x005FCF90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997  (0x005FCF94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998  (0x005FCF98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999  (0x005FCF9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000 (0x005FCFA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001 (0x005FCFA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002 (0x005FCFA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003 (0x005FCFAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004 (0x005FCFB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005 (0x005FCFB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006 (0x005FCFB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007 (0x005FCFBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008 (0x005FCFC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009 (0x005FCFC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010 (0x005FCFC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011 (0x005FCFCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012 (0x005FCFD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013 (0x005FCFD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014 (0x005FCFD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015 (0x005FCFDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016 (0x005FCFE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017 (0x005FCFE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018 (0x005FCFE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019 (0x005FCFEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020 (0x005FCFF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021 (0x005FCFF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022 (0x005FCFF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023 (0x005FCFFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___M 0x000FFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0    (0x005FD000)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1    (0x005FD004)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2    (0x005FD008)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3    (0x005FD00C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4    (0x005FD010)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5    (0x005FD014)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6    (0x005FD018)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7    (0x005FD01C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8    (0x005FD020)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9    (0x005FD024)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10   (0x005FD028)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11   (0x005FD02C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12   (0x005FD030)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13   (0x005FD034)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14   (0x005FD038)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15   (0x005FD03C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16   (0x005FD040)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17   (0x005FD044)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18   (0x005FD048)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19   (0x005FD04C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20   (0x005FD050)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21   (0x005FD054)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22   (0x005FD058)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23   (0x005FD05C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24   (0x005FD060)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25   (0x005FD064)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26   (0x005FD068)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27   (0x005FD06C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28   (0x005FD070)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29   (0x005FD074)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30   (0x005FD078)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31   (0x005FD07C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32   (0x005FD080)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33   (0x005FD084)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34   (0x005FD088)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35   (0x005FD08C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36   (0x005FD090)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37   (0x005FD094)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38   (0x005FD098)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39   (0x005FD09C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40   (0x005FD0A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41   (0x005FD0A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42   (0x005FD0A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43   (0x005FD0AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44   (0x005FD0B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45   (0x005FD0B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46   (0x005FD0B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47   (0x005FD0BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48   (0x005FD0C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49   (0x005FD0C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50   (0x005FD0C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51   (0x005FD0CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52   (0x005FD0D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53   (0x005FD0D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54   (0x005FD0D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55   (0x005FD0DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56   (0x005FD0E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57   (0x005FD0E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58   (0x005FD0E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59   (0x005FD0EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60   (0x005FD0F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61   (0x005FD0F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62   (0x005FD0F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63   (0x005FD0FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64   (0x005FD100)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65   (0x005FD104)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66   (0x005FD108)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67   (0x005FD10C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68   (0x005FD110)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69   (0x005FD114)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70   (0x005FD118)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71   (0x005FD11C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72   (0x005FD120)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73   (0x005FD124)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74   (0x005FD128)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75   (0x005FD12C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76   (0x005FD130)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77   (0x005FD134)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78   (0x005FD138)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79   (0x005FD13C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80   (0x005FD140)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81   (0x005FD144)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82   (0x005FD148)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83   (0x005FD14C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84   (0x005FD150)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85   (0x005FD154)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86   (0x005FD158)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87   (0x005FD15C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88   (0x005FD160)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89   (0x005FD164)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90   (0x005FD168)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91   (0x005FD16C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92   (0x005FD170)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93   (0x005FD174)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94   (0x005FD178)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95   (0x005FD17C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96   (0x005FD180)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97   (0x005FD184)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98   (0x005FD188)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99   (0x005FD18C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100  (0x005FD190)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101  (0x005FD194)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102  (0x005FD198)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103  (0x005FD19C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104  (0x005FD1A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105  (0x005FD1A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106  (0x005FD1A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107  (0x005FD1AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108  (0x005FD1B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109  (0x005FD1B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110  (0x005FD1B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111  (0x005FD1BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112  (0x005FD1C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113  (0x005FD1C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114  (0x005FD1C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115  (0x005FD1CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116  (0x005FD1D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117  (0x005FD1D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118  (0x005FD1D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119  (0x005FD1DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120  (0x005FD1E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121  (0x005FD1E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122  (0x005FD1E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123  (0x005FD1EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124  (0x005FD1F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125  (0x005FD1F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126  (0x005FD1F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127  (0x005FD1FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128  (0x005FD200)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129  (0x005FD204)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130  (0x005FD208)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131  (0x005FD20C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132  (0x005FD210)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133  (0x005FD214)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134  (0x005FD218)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135  (0x005FD21C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136  (0x005FD220)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137  (0x005FD224)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138  (0x005FD228)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139  (0x005FD22C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140  (0x005FD230)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141  (0x005FD234)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142  (0x005FD238)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143  (0x005FD23C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144  (0x005FD240)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145  (0x005FD244)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146  (0x005FD248)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147  (0x005FD24C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148  (0x005FD250)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149  (0x005FD254)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150  (0x005FD258)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151  (0x005FD25C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152  (0x005FD260)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153  (0x005FD264)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154  (0x005FD268)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155  (0x005FD26C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156  (0x005FD270)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157  (0x005FD274)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158  (0x005FD278)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159  (0x005FD27C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160  (0x005FD280)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161  (0x005FD284)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162  (0x005FD288)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163  (0x005FD28C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164  (0x005FD290)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165  (0x005FD294)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166  (0x005FD298)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167  (0x005FD29C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168  (0x005FD2A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169  (0x005FD2A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170  (0x005FD2A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171  (0x005FD2AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172  (0x005FD2B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173  (0x005FD2B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174  (0x005FD2B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175  (0x005FD2BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176  (0x005FD2C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177  (0x005FD2C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178  (0x005FD2C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179  (0x005FD2CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180  (0x005FD2D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181  (0x005FD2D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182  (0x005FD2D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183  (0x005FD2DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184  (0x005FD2E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185  (0x005FD2E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186  (0x005FD2E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187  (0x005FD2EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188  (0x005FD2F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189  (0x005FD2F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190  (0x005FD2F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191  (0x005FD2FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192  (0x005FD300)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193  (0x005FD304)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194  (0x005FD308)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195  (0x005FD30C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196  (0x005FD310)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197  (0x005FD314)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198  (0x005FD318)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199  (0x005FD31C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200  (0x005FD320)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201  (0x005FD324)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202  (0x005FD328)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203  (0x005FD32C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204  (0x005FD330)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205  (0x005FD334)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206  (0x005FD338)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207  (0x005FD33C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208  (0x005FD340)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209  (0x005FD344)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210  (0x005FD348)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211  (0x005FD34C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212  (0x005FD350)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213  (0x005FD354)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214  (0x005FD358)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215  (0x005FD35C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216  (0x005FD360)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217  (0x005FD364)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218  (0x005FD368)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219  (0x005FD36C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220  (0x005FD370)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221  (0x005FD374)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222  (0x005FD378)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223  (0x005FD37C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224  (0x005FD380)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225  (0x005FD384)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226  (0x005FD388)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227  (0x005FD38C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228  (0x005FD390)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229  (0x005FD394)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230  (0x005FD398)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231  (0x005FD39C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232  (0x005FD3A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233  (0x005FD3A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234  (0x005FD3A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235  (0x005FD3AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236  (0x005FD3B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237  (0x005FD3B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238  (0x005FD3B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239  (0x005FD3BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240  (0x005FD3C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241  (0x005FD3C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242  (0x005FD3C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243  (0x005FD3CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244  (0x005FD3D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245  (0x005FD3D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246  (0x005FD3D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247  (0x005FD3DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248  (0x005FD3E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249  (0x005FD3E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250  (0x005FD3E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251  (0x005FD3EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252  (0x005FD3F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253  (0x005FD3F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254  (0x005FD3F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255  (0x005FD3FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___S              31
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___S              28
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___S              25
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___S              21
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___S              15
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___S               5
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___M 0xFFBFFFBF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0    (0x005FD800)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1    (0x005FD804)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2    (0x005FD808)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3    (0x005FD80C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4    (0x005FD810)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5    (0x005FD814)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6    (0x005FD818)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7    (0x005FD81C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8    (0x005FD820)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9    (0x005FD824)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10   (0x005FD828)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11   (0x005FD82C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12   (0x005FD830)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13   (0x005FD834)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14   (0x005FD838)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15   (0x005FD83C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16   (0x005FD840)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17   (0x005FD844)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18   (0x005FD848)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19   (0x005FD84C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20   (0x005FD850)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21   (0x005FD854)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22   (0x005FD858)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23   (0x005FD85C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24   (0x005FD860)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25   (0x005FD864)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26   (0x005FD868)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27   (0x005FD86C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28   (0x005FD870)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29   (0x005FD874)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30   (0x005FD878)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31   (0x005FD87C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32   (0x005FD880)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33   (0x005FD884)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34   (0x005FD888)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35   (0x005FD88C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36   (0x005FD890)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37   (0x005FD894)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38   (0x005FD898)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39   (0x005FD89C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40   (0x005FD8A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41   (0x005FD8A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42   (0x005FD8A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43   (0x005FD8AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44   (0x005FD8B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45   (0x005FD8B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46   (0x005FD8B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47   (0x005FD8BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48   (0x005FD8C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49   (0x005FD8C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50   (0x005FD8C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51   (0x005FD8CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52   (0x005FD8D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53   (0x005FD8D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54   (0x005FD8D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55   (0x005FD8DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56   (0x005FD8E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57   (0x005FD8E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58   (0x005FD8E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59   (0x005FD8EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60   (0x005FD8F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61   (0x005FD8F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62   (0x005FD8F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63   (0x005FD8FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64   (0x005FD900)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65   (0x005FD904)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66   (0x005FD908)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67   (0x005FD90C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68   (0x005FD910)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69   (0x005FD914)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70   (0x005FD918)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71   (0x005FD91C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72   (0x005FD920)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73   (0x005FD924)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74   (0x005FD928)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75   (0x005FD92C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76   (0x005FD930)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77   (0x005FD934)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78   (0x005FD938)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79   (0x005FD93C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80   (0x005FD940)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81   (0x005FD944)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82   (0x005FD948)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83   (0x005FD94C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84   (0x005FD950)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85   (0x005FD954)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86   (0x005FD958)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87   (0x005FD95C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88   (0x005FD960)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89   (0x005FD964)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90   (0x005FD968)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91   (0x005FD96C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92   (0x005FD970)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93   (0x005FD974)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94   (0x005FD978)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95   (0x005FD97C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96   (0x005FD980)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97   (0x005FD984)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98   (0x005FD988)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99   (0x005FD98C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100  (0x005FD990)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101  (0x005FD994)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102  (0x005FD998)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103  (0x005FD99C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104  (0x005FD9A0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105  (0x005FD9A4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106  (0x005FD9A8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107  (0x005FD9AC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108  (0x005FD9B0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109  (0x005FD9B4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110  (0x005FD9B8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111  (0x005FD9BC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112  (0x005FD9C0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113  (0x005FD9C4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114  (0x005FD9C8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115  (0x005FD9CC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116  (0x005FD9D0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117  (0x005FD9D4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118  (0x005FD9D8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119  (0x005FD9DC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120  (0x005FD9E0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121  (0x005FD9E4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122  (0x005FD9E8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123  (0x005FD9EC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124  (0x005FD9F0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125  (0x005FD9F4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126  (0x005FD9F8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127  (0x005FD9FC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S              16
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S               7
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___M 0x3FFF3FFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0    (0x005FDC00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1    (0x005FDC04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2    (0x005FDC08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3    (0x005FDC0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4    (0x005FDC10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5    (0x005FDC14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6    (0x005FDC18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7    (0x005FDC1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8    (0x005FDC20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9    (0x005FDC24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10   (0x005FDC28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11   (0x005FDC2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12   (0x005FDC30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13   (0x005FDC34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14   (0x005FDC38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15   (0x005FDC3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16   (0x005FDC40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17   (0x005FDC44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18   (0x005FDC48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19   (0x005FDC4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20   (0x005FDC50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21   (0x005FDC54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22   (0x005FDC58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23   (0x005FDC5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24   (0x005FDC60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25   (0x005FDC64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26   (0x005FDC68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27   (0x005FDC6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28   (0x005FDC70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29   (0x005FDC74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30   (0x005FDC78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31   (0x005FDC7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32   (0x005FDC80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33   (0x005FDC84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34   (0x005FDC88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35   (0x005FDC8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36   (0x005FDC90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37   (0x005FDC94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38   (0x005FDC98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39   (0x005FDC9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40   (0x005FDCA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41   (0x005FDCA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42   (0x005FDCA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43   (0x005FDCAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44   (0x005FDCB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45   (0x005FDCB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46   (0x005FDCB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47   (0x005FDCBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48   (0x005FDCC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49   (0x005FDCC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50   (0x005FDCC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51   (0x005FDCCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52   (0x005FDCD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53   (0x005FDCD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54   (0x005FDCD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55   (0x005FDCDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56   (0x005FDCE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57   (0x005FDCE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58   (0x005FDCE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59   (0x005FDCEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60   (0x005FDCF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61   (0x005FDCF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62   (0x005FDCF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63   (0x005FDCFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64   (0x005FDD00)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65   (0x005FDD04)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66   (0x005FDD08)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67   (0x005FDD0C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68   (0x005FDD10)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69   (0x005FDD14)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70   (0x005FDD18)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71   (0x005FDD1C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72   (0x005FDD20)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73   (0x005FDD24)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74   (0x005FDD28)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75   (0x005FDD2C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76   (0x005FDD30)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77   (0x005FDD34)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78   (0x005FDD38)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79   (0x005FDD3C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80   (0x005FDD40)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81   (0x005FDD44)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82   (0x005FDD48)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83   (0x005FDD4C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84   (0x005FDD50)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85   (0x005FDD54)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86   (0x005FDD58)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87   (0x005FDD5C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88   (0x005FDD60)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89   (0x005FDD64)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90   (0x005FDD68)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91   (0x005FDD6C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92   (0x005FDD70)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93   (0x005FDD74)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94   (0x005FDD78)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95   (0x005FDD7C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96   (0x005FDD80)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97   (0x005FDD84)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98   (0x005FDD88)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99   (0x005FDD8C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100  (0x005FDD90)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101  (0x005FDD94)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102  (0x005FDD98)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103  (0x005FDD9C)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104  (0x005FDDA0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105  (0x005FDDA4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106  (0x005FDDA8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107  (0x005FDDAC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108  (0x005FDDB0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109  (0x005FDDB4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110  (0x005FDDB8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111  (0x005FDDBC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112  (0x005FDDC0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113  (0x005FDDC4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114  (0x005FDDC8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115  (0x005FDDCC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116  (0x005FDDD0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117  (0x005FDDD4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118  (0x005FDDD8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119  (0x005FDDDC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120  (0x005FDDE0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121  (0x005FDDE4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122  (0x005FDDE8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123  (0x005FDDEC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124  (0x005FDDF0)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125  (0x005FDDF4)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126  (0x005FDDF8)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___S               0

#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127  (0x005FDDFC)
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___RWC QCSR_REG_RW    
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___POR 0x00000000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___POR 0x00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___POR 0x0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03800000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___S              23
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00700000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___S              20
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___S              19
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___S              18
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___M 0x0003F000
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___S              12
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___M 0x00000E00
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___S               9
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___M 0x000001F0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___S               4
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___M 0x0000000F
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___S               0
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___M 0x03FFFFFF   
#define   PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___S               0


#define UMAC                        (0x00A00000)

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL (0x00A20000)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___M 0x1C000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___M 0x03000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___M 0x00100000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___M 0x000FC000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___M 0x00003F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___M 0x0000007E
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___M 0x1F1FFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0 (0x00A20004)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1 (0x00A20008)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2 (0x00A2000C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3 (0x00A20010)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0   (0x00A20014)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1   (0x00A20018)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2   (0x00A2001C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3   (0x00A20020)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI        (0x00A20024)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___RWC  QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0 (0x00A20028)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1 (0x00A2002C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2 (0x00A20030)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3 (0x00A20034)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4 (0x00A20038)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5 (0x00A2003C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6 (0x00A20040)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7 (0x00A20044)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8 (0x00A20048)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9 (0x00A2004C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10 (0x00A20050)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS (0x00A20054)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL    (0x00A20058)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___POR 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___M 0x00000300
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___M 0x00001F19   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL    (0x00A2005C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___POR 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___M 0x00000300
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___M 0x00001F19   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL          (0x00A20060)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___RWC    QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___POR 0x12000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___POR 0x2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___M 0x18000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___M 0x06000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___S              25
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___M 0x01800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___M 0x0000F000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___M   0x3FFFF3FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___S                 0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2         (0x00A20064)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___POR 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___M 0x00800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___M 0x0000F000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___M  0x7FFFFE1F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3         (0x00A20068)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___M 0x000FF000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___M 0x00000FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___M  0xFF0FFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4         (0x00A2006C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___M  0x0000FF0F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5         (0x00A20070)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___POR 0xF0789C50
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___POR 0xF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___POR 0x078
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___POR 0x271
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___POR 0x10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___M 0xF0000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___M 0x0FFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___M 0x0000FFC0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___M 0x0000003F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___M  0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6         (0x00A20074)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___M 0x0FFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___M  0x0FFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1 (0x00A20078)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2 (0x00A2007C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3 (0x00A20080)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4 (0x00A20084)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1   (0x00A20088)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT   (0x00A2008C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___M 0x0000003F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1 (0x00A20090)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2 (0x00A20094)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3 (0x00A20098)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4 (0x00A2009C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5 (0x00A200A0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6 (0x00A200A4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7 (0x00A200A8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8 (0x00A200AC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9 (0x00A200B0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10 (0x00A200B4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11 (0x00A200B8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12 (0x00A200BC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD (0x00A200C0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___POR 0x00000F0F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___POR 0x0F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___POR 0x0F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___M 0x00007F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0 (0x00A200C4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1 (0x00A200C8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2 (0x00A200CC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3 (0x00A200D0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0 (0x00A200D4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1 (0x00A200D8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2 (0x00A200DC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3 (0x00A200E0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___M 0x7F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___M 0x7F7F7F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD (0x00A200E4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1 (0x00A200E8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2 (0x00A200EC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___M 0x0000001F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___M 0x0000FF1F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0 (0x00A200F0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1 (0x00A200F4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2 (0x00A200F8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3 (0x00A200FC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4 (0x00A20100)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5 (0x00A20104)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6 (0x00A20108)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7 (0x00A2010C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8 (0x00A20110)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9 (0x00A20114)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10 (0x00A20118)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD (0x00A2011C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD (0x00A20120)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20    (0x00A20124)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___M 0x0FFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___M 0x00000FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___M 0x0FFF0FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40    (0x00A20128)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___M 0x0FFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___M 0x00000FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___M 0x0FFF0FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80    (0x00A2012C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___POR 0x000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___M 0x0FFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___M 0x00000FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___M 0x0FFF0FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL (0x00A20130)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___M 0x00FFFF03   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK (0x00A20134)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE (0x00A2013C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___M 0x000000DF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL (0x00A2018C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___M 0x000000C0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___M 0x00000030
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___M 0x0000000C
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS (0x00A20190)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___POR 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___POR 0x10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX (0x00A20194)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___M 0x007FFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX (0x00A20198)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___M 0x007F0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___M 0x007FFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE (0x00A2019C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___POR 0x18000C00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___POR 0x18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___POR 0x3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___M 0x00FC0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___S              18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___M 0x00020000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___M 0x00000C00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___M 0xFFFE0C00   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___S              10

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2 (0x00A201A0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___M 0x30000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___M 0x0C000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___M 0x3C000000   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___S              26

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3 (0x00A201A4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___M 0xF0000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___M 0x01000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___M 0xF9000000   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___S              24

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4 (0x00A201A8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5 (0x00A201AC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___M 0x00000008   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___S               3

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT (0x00A201B0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7         (0x00A201DC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___RWC   QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___POR 0x00000434
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___M 0x40000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___S              30
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___M  0xF0000FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___S                0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG (0x00A201E0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___M 0x00007F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG (0x00A201E4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___M 0x00007F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___M 0x0000007F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___M 0x00007F7F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD (0x00A201EC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___POR 0x00000064
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___POR 0x064
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___M 0x000003FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___M 0x000003FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS (0x00A201F0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET (0x00A201F4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___M 0x00000007   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1 (0x00A201F8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1 (0x00A201FC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE (0x00A20200)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1 (0x00A20204)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___M 0x40000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___S              30
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___M 0xC001FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2 (0x00A20208)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___M 0x40000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___S              30
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___M 0xC001FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX (0x00A20210)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___M 0x00000007   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB (0x00A20214)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX (0x00A20218)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___M 0x8001FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1 (0x00A2021C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___M 0x04000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___M 0x02000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___S              25
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___M 0x01000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___M 0x00800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___M 0x00400000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___S              22
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___M 0x00200000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___S              21
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___M 0x00100000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___M 0x00080000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___S              19
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___M 0x00040000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___S              18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___M 0x00020000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___M 0x1FFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2 (0x00A20220)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1 (0x00A20228)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___M 0x04000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___M 0x02000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___S              25
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___M 0x01000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___M 0x00800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___M 0x00400000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___S              22
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___M 0x00200000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___S              21
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___M 0x00100000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___M 0x00080000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___S              19
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___M 0x00040000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___S              18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___M 0x00020000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___M 0x1FFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2 (0x00A2022C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN (0x00A20234)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___POR 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___M 0x00000001   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1 (0x00A20238)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___POR 0x00000003
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2 (0x00A2023C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___POR 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN (0x00A20244)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___POR 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___M 0x00000001   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR (0x00A21000)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___M 0x00001F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___M 0x00001FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY (0x00A21004)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER       (0x00A21008)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW (0x00A2100C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___M 0x07FFF800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___M 0xBFFFFAFB   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN  (0x00A21010)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___M 0x80000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___S              31
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___M 0x07FFF800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___M 0xBFFFFBFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW (0x00A21014)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___M 0x00000FFC   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___S               2

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN (0x00A21018)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___M 0x00000FFC   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___S               2

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW (0x00A2101C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___M 0x40000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___S              30
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___M 0x04000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___M 0x02000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___S              25
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___M 0x01000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___M 0x00800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00400000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___S              22
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00200000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___S              21
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00100000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00080000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___S              19
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___M 0x00040000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___S              18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___M 0x0003FFFC
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___M 0x7FFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN (0x00A21020)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___M 0x40000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___S              30
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___M 0x20000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___S              29
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x10000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x08000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___S              27
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___M 0x04000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___S              26
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___M 0x02000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___S              25
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___M 0x01000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___M 0x00800000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___S              23
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00400000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___S              22
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00200000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___S              21
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00100000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00080000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___S              19
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___M 0x00040000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___S              18
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___M 0x0003FFFC
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___M 0x7FFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS   (0x00A21024)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___M 0xF0000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___S              28
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___M 0x0FE00000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___S              21
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___M 0x001E0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___M 0x00010000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE (0x00A21028)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0 (0x00A2102C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1 (0x00A21030)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2 (0x00A21034)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3 (0x00A21038)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0 (0x00A2103C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1 (0x00A21040)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2 (0x00A21044)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3 (0x00A21048)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___M 0xFF000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___M 0x00FF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___M 0x0000FF00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___M 0x000000FF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO (0x00A2104C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0 (0x00A21050)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1 (0x00A21054)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2 (0x00A21058)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3 (0x00A2105C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0      (0x00A21060)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1      (0x00A21064)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2      (0x00A21068)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___M 0x00007FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___M 0x00007FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR (0x00A2106C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL (0x00A21070)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___M 0x000001FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT (0x00A21074)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT (0x00A21078)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT  (0x00A2107C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT (0x00A21080)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT (0x00A21084)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL (0x00A21088)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT     (0x00A2108C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT     (0x00A21090)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT (0x00A21094)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT (0x00A21098)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1 (0x00A2109C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2 (0x00A210A0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3 (0x00A210A4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4 (0x00A210A8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5 (0x00A210AC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1 (0x00A210B0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2 (0x00A210B4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH (0x00A210B8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___M 0x00001F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___M 0x0000003F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___M 0x00001F3F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL  (0x00A210BC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___POR 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___M 0x00008000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___S              15
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___M 0x00004000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___S              14
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___M 0x00002000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___S              13
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___M 0x00001000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___M 0x00000800
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___S              11
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___M 0x00000400
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___S              10
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___M 0x00000200
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___M 0x00000100
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000003F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER (0x00A210C0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0 (0x00A210C4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1 (0x00A210C8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2 (0x00A210CC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3 (0x00A210D0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN (0x00A210F0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR (0x00A210F4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___M 0x00000080
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___S               7
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___M 0x00000040
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___S               6
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___M 0x000000FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE (0x00A210F8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY (0x00A210FC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON (0x00A21110)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___POR 0x000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___M 0x00FFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___M 0x00FFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME  (0x00A21114)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___M 0x00003FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___M 0x00003FFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER (0x00A21118)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0 (0x00A2111C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___M 0x07000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___M 0x00700000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___M 0x00070000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___M 0x00007000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___M 0x00000700
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___M 0x00000070
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___M 0x00000007
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___M 0x07777777   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1 (0x00A21120)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___POR 0x01101000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___POR 0x01
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___M 0x0F000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___S              24
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___M 0x00F00000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___S              20
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___M 0x0001F000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___S              12
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___M 0x00000F00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___S               8
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___M 0x000000F0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___M 0x0000000F
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___M 0x0FF1FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A21124)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL (0x00A21128)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___M 0x00000020
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___S               5
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___M 0x00000010
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___S               4
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___M 0x00000008
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___S               3
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___M 0x00000004
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___S               2
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___M 0x00000002
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___M 0x0000003F   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1 (0x00A2112C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2 (0x00A21130)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1 (0x00A21138)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2 (0x00A2113C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1 (0x00A21144)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2 (0x00A21148)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1 (0x00A21150)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2 (0x00A21154)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1 (0x00A2115C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2 (0x00A21160)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1 (0x00A21168)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1 (0x00A2116C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1 (0x00A21170)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2 (0x00A21174)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2 (0x00A21178)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2 (0x00A2117C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1 (0x00A2118C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2 (0x00A21190)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1 (0x00A21198)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2 (0x00A2119C)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1 (0x00A211A4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2 (0x00A211A8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1 (0x00A211B0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT    (0x00A211B4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT (0x00A211B8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT (0x00A211BC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT (0x00A211C0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT (0x00A211C4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1 (0x00A211C8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS (0x00A211CC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS (0x00A211D0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL   (0x00A211D4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT (0x00A211D8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___M 0x0000FFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1 (0x00A211DC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1 (0x00A211E0)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___POR 0x0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___M 0xFFFF0000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___S              16
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___M 0x0000FFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS (0x00A211E4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___M 0x00000600
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___M 0x000001FE
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___M 0x000007FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS (0x00A211E8)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___POR 0x00
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___M 0x00000600
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___S               9
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___M 0x000001FE
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___S               1
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___M 0x00000001
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___M 0x000007FF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE (0x00A211EC)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___POR 0x0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___M 0x00000003
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___M 0x00000003   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___S               0

#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER (0x00A211F4)
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___RWC QCSR_REG_RW    
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___POR 0x00000000
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___M 0xFFFFFFFF
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___S               0
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___M 0xFFFFFFFF   
#define   UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION (0x00A22000)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___POR 0x0000004F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___POR 0x04F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___M 0x20000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___S              29
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___M 0x10000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___S              28
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___M 0x08000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___S              27
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___M 0x04000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___S              26
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___M 0x03000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___S              24
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___M 0x00F00000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___S              20
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___M 0x00060000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___S              17
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___M 0x00006000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___M 0x000003FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___M 0x3FFEFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER     (0x00A22004)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE (0x00A22008)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL (0x00A2200C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___POR 0x00000006
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___M 0x0000007F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT (0x00A22010)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___POR 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___M 0x00000001   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1 (0x00A22014)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2 (0x00A22018)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL (0x00A2201C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___POR 0x00000006
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___M 0x0000007F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT (0x00A22020)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___POR 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___M 0x00000001   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1 (0x00A22024)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2 (0x00A22028)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL (0x00A2202C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___POR 0x00000006
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___M 0x00000600
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___M 0x00000180
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___M 0x00000FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT (0x00A22030)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___POR 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1 (0x00A22034)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2 (0x00A22038)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT (0x00A2203C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___POR 0x00000606
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___M 0x000007FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1 (0x00A22040)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2 (0x00A22044)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT (0x00A22048)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___POR 0x00000606
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___M 0x000007FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1 (0x00A2204C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2 (0x00A22050)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS (0x00A22054)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___M 0x000001FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL (0x00A22058)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___POR 0x0003D004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___POR 0xF4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___POR 0x04
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___M 0x1FF00000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___S              20
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___M 0x0003FC00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___M 0x1FFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS (0x00A2205C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___M 0x0003FE00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___M 0x000FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS (0x00A22060)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___POR 0x0003D004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___POR 0xF4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___POR 0x04
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___M 0x0003FC00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___M 0x000FFDFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE (0x00A22064)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___M 0x000001FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW (0x00A22068)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION (0x00A2206C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___POR 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___POR 0x00008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___M 0x0001FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___M 0x0001FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS (0x00A22070)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY (0x00A22074)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___M 0x0000000F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___M 0x0000000F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL (0x00A22078)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT (0x00A2207C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT (0x00A22080)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___POR 0x000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___M 0x00FFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___M 0x00FFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED (0x00A22084)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE (0x00A22088)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___POR 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___POR 0x01
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___M 0x40000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___S              30
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___M 0x000003E0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___M 0x400003FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR (0x00A2208C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___M 0x00000001   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE (0x00A2209C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___M 0x00007C00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___M 0x000003E0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___M 0x00007FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE (0x00A220A0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___POR 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___M 0x00000001   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET (0x00A220A4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET (0x00A220A8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET (0x00A220AC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET (0x00A220B0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY (0x00A220B4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY (0x00A220C0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___POR 0x000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___M 0x003FF800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___M 0x000007FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___M 0x003FFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL (0x00A220C4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___POR 0x00000006
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___M 0x0000007F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL (0x00A220FC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___M 0x000003FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL (0x00A22100)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___M 0x000003FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL (0x00A22104)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00010000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              16
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00004000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              14
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00002000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___M 0x0001FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL (0x00A22108)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00010000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              16
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00004000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              14
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00002000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___M 0x0001FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL (0x00A23000)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___M 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N (0x00A23004)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___M 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE (0x00A23008)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___M 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR (0x00A2300C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___M 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS (0x00A23010)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___M 0x00000003
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY (0x00A23014)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___POR 0x000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___M 0x00FFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___M 0x00FFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY (0x00A23018)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___POR 0x000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___M 0x00FFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___M 0x00FFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT (0x00A2301C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT (0x00A23020)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE (0x00A23024)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT (0x00A23028)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x0000FF00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS (0x00A2302C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___M 0x80000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___S              31
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___M 0x40000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___S              30
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___M 0x20000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___S              29
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___M 0x10000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___S              28
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___M 0x08000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___S              27
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___M 0x04000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___S              26
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___M 0x02000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___S              25
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___M 0x01000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___S              24
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___M 0x00800000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___S              23
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___M 0x00400000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___S              22
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___M 0x00200000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___S              21
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___M 0x00100000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___S              20
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___M 0x00020000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___S              17
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___M 0x00010000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___S              16
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___M 0x00004000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___S              14
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___M 0x00002000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR (0x00A23030)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___M 0x80000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___S              31
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___M 0x40000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___S              30
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___M 0x20000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___S              29
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___M 0x10000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___S              28
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___M 0x08000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___S              27
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___M 0x04000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___S              26
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___M 0x02000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___S              25
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___M 0x01000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___S              24
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00800000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___S              23
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00400000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___S              22
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00200000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___S              21
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___M 0x00100000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___S              20
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___M 0x00020000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___S              17
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___M 0x00010000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___S              16
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___M 0x00004000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___S              14
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___M 0x00002000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE (0x00A23034)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___M 0x80000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___S              31
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___M 0x40000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___S              30
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___M 0x20000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___S              29
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___M 0x10000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___S              28
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___M 0x08000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___S              27
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___M 0x04000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___S              26
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___M 0x02000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___S              25
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___M 0x01000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___S              24
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00800000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___S              23
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00400000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___S              22
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00200000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___S              21
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___M 0x00100000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___S              20
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___M 0x00080000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___S              19
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___M 0x00040000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___S              18
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___M 0x00020000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___S              17
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___M 0x00010000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___S              16
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___M 0x00008000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___S              15
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___M 0x00004000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___S              14
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___M 0x00002000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___S              13
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT (0x00A23038)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___M 0x0000FF00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE (0x00A2303C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT (0x00A23040)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE (0x00A23044)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT (0x00A23048)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE (0x00A2304C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT (0x00A23050)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE (0x00A23054)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT (0x00A23058)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE (0x00A2305C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT (0x00A23060)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE (0x00A23064)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT (0x00A23068)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE (0x00A2306C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT (0x00A23070)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE (0x00A23074)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT (0x00A23078)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x00001FE0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___M 0x00001FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE (0x00A2307C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT (0x00A23080)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x00001FE0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___M 0x00001FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE (0x00A23084)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT (0x00A23088)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___M 0x0000001F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE (0x00A2308C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT (0x00A23090)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___M 0x0000001F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___M 0x0000001F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE (0x00A23094)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME (0x00A23098)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME (0x00A2309C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME (0x00A230A0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230A4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE (0x00A230A8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___M 0x000000FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___M 0x000001FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER (0x00A230AC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___POR 0x00181110
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___POR 0x00181110
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR (0x00A230B0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___S              17
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___M 0x0007FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL (0x00A230B4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___M 0x00000FC0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000003F
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___M 0x00000FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL (0x00A230B8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___M 0x00000003   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT (0x00A230BC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT (0x00A230C0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___POR 0x00002EE0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___POR 0x2EE0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___M 0x00003FFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___M 0x00003FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE (0x00A230C4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___M 0x0000000F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS (0x00A230C8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___M 0x0000000F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR (0x00A230CC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___M 0x0000000F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT (0x00A230D0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME (0x00A230D4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME (0x00A230D8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME (0x00A230DC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230E0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME (0x00A230E4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME (0x00A230E8)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME (0x00A230EC)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230F0)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND (0x00A230F4)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___POR 0x000003E8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___POR 0x3E8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___M 0x000003FF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___M 0x000003FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2 (0x00A23108)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___M 0x00001FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2 (0x00A2310C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___M 0x00000100
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___S               8
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___M 0x00001FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2 (0x00A23110)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___M 0x00001000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___S              12
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___M 0x00000800
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___S              11
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___M 0x00000400
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___S              10
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___M 0x00000200
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___S               9
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___M 0x00001E7F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3 (0x00A23114)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3 (0x00A23118)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3 (0x00A2311C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___M 0x00000080
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___S               7
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___M 0x00000040
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___S               6
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___M 0x00000020
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___S               5
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___M 0x00000010
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___S               4
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___M 0x000000FF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS (0x00A23120)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___POR 0x0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___M 0x00000008
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___S               3
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___M 0x00000004
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___S               2
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___M 0x00000002
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___S               1
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___M 0x00000001
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___M 0x0000000F   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT (0x00A23128)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___POR 0x000007CF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___POR 0x7CF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___M 0x00000FFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___M 0x00000FFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT (0x00A23134)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT (0x00A23138)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT (0x00A2313C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT (0x00A23140)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT (0x00A23144)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT (0x00A23148)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT (0x00A2314C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT (0x00A23150)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT (0x00A23154)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT (0x00A23158)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT (0x00A2315C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT (0x00A23160)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT (0x00A23164)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT (0x00A23168)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT (0x00A2316C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT (0x00A23170)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT (0x00A23174)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT (0x00A23178)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT (0x00A2317C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT (0x00A23180)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT (0x00A23184)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT (0x00A23188)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT (0x00A2318C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT (0x00A23190)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT (0x00A23194)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT (0x00A23198)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT (0x00A2319C)
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO    
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___POR 0x00000000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___S               0
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___M 0x0000FFFF   
#define   UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL (0x00A24000)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___M 0x000003E0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___M 0x0001FFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE (0x00A24004)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___M 0x00180000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___S              19
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___M 0x00078000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___M 0x00001800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___M 0x000007F8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___M 0x001FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL (0x00A24008)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___M 0x00000003   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG (0x00A2400C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___M 0x0000FF00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___M 0x0001FFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE (0x00A24010)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___M 0x0000001F   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL (0x00A24014)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___M 0x00000001   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0 (0x00A24018)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___POR 0x1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___M 0x000001FE
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___M 0x00001FFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1 (0x00A2401C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___POR 0x1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___M 0x000001FE
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___M 0x00001FFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1 (0x00A24020)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2 (0x00A24024)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___POR 0x00001800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___POR 0x00001800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3 (0x00A24028)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___POR 0x8C040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___POR 0x8C040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4 (0x00A2402C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1 (0x00A24030)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2 (0x00A24034)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3 (0x00A24038)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___POR 0x8C040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___POR 0x8C040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4 (0x00A2403C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1 (0x00A24040)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2 (0x00A24044)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___POR 0x00001800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___POR 0x00001800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3 (0x00A24048)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___POR 0x84040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___POR 0x84040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4 (0x00A2404C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1 (0x00A24050)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2 (0x00A24054)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___POR 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3 (0x00A24058)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___POR 0x84040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___POR 0x84040400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4 (0x00A2405C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0 (0x00A24060)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___POR 0x88800880
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___POR 0x88800880
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1 (0x00A24064)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___POR 0x88800080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___POR 0x88800080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0 (0x00A24068)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___POR 0x80008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___POR 0x80008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1 (0x00A2406C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___POR 0x80008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___POR 0x80008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0 (0x00A24070)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___POR 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___POR 0x08
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___M 0x000000FF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1 (0x00A24074)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___POR 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___POR 0x08
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___M 0x000000FF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0 (0x00A24078)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___POR 0x00001400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___POR 0x00001400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0 (0x00A2407C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___POR 0x00800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0 (0x00A24080)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___POR 0x00800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0 (0x00A24084)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___POR 0x00800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0 (0x00A24088)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___POR 0x00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0 (0x00A2408C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___POR 0x00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0 (0x00A24090)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___POR 0x00003800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___POR 0x03800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1 (0x00A24094)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___POR 0x00003000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___POR 0x00003000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___M 0xFFFFFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1 (0x00A24098)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___POR 0x00800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1 (0x00A2409C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___POR 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___POR 0x00800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1 (0x00A240A0)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___POR 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___POR 0x00400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1 (0x00A240A4)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___POR 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___POR 0x00400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1 (0x00A240A8)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___POR 0x00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1 (0x00A240AC)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___POR 0x00003800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___POR 0x03800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS (0x00A240B0)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___M 0x00000007   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS (0x00A240B4)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___M 0x00000007   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER (0x00A240B8)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___POR 0x00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___M 0x80000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___S              31
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___M 0x40000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___S              30
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___M 0x000FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___M 0xC00FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT (0x00A25000)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___RWC QCSR_REG_RO    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___M 0x00080000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___S              19
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___M 0x00040000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___S              18
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___M 0x00020000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___M 0x00000080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___S               7
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___M 0x00000040
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___M 0x00000020
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE (0x00A25004)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___M 0x00040000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___S              18
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___M 0x00020000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___M 0x00000080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___S               7
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___M 0x00000040
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___M 0x00000020
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___M 0x0007FFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY (0x00A25008)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___M 0x00040000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___S              18
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___M 0x00020000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___M 0x00000080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___S               7
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___M 0x00000040
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___M 0x00000020
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___M 0x0007FFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR (0x00A2500C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___M 0x00080000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___S              19
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___M 0x00040000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___S              18
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___M 0x00020000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___M 0x00000080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___S               7
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___M 0x00000040
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___M 0x00000020
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR (0x00A25010)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___M 0x80000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___S              31
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___M 0x800001FF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR (0x00A25014)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___RWC QCSR_REG_RO    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___M 0x000007FF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL (0x00A25018)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___M 0xF0000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___S              28
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___M 0x01000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___S              24
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___M 0x00800000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___S              23
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___M 0x00400000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___S              22
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___M 0x00200000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___S              21
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___M 0x00100000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___S              20
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___M 0xF1F0000F   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR (0x00A2501C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES (0x00A25020)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___RWC QCSR_REG_RO    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___POR 0x000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___POR 0x000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___M 0xFFE00000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___S              21
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___M 0x001FFFFF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES (0x00A25024)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___RWC QCSR_REG_RO    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___M 0x00000FC0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___M 0x0000003F
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___M 0x00000FFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE (0x00A25028)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___POR 0x000C0000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___POR 0x1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___POR 0x1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___M 0x00080000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___S              19
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___M 0x00040000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___S              18
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___M 0x00020000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___S              17
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___M 0x00010000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___M 0x00008000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___S              15
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___M 0x00004000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___S              14
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___M 0x00002000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___S              13
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___M 0x00001000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___S              12
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___M 0x00000800
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___S              11
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___M 0x00000400
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___S              10
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___M 0x00000200
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___S               9
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___M 0x00000100
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___M 0x00000080
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___S               7
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___M 0x00000040
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___S               6
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___M 0x00000020
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___S               5
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___M 0x00000010
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___S               4
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___M 0x00000008
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___S               3
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___M 0x00000004
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___S               2
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___M 0x00000002
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___S               1
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___M 0x00000001
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___M 0x000FFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE (0x00A2502C)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___M 0xFF000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___S              24
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___M 0x00FF0000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___M 0x0000FF00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK (0x00A25030)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___M 0xFF000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___S              24
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___M 0x00FF0000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___S              16
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___M 0x0000FF00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___M 0x000000FF
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___M 0xFFFFFFFF   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___S               0

#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL (0x00A25034)
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___POR 0x00000000
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___POR 0x00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___POR 0x0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___M 0x0000FF00
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___S               8
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___M 0x0000000F
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___S               0
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___M 0x0000FF0F   
#define   UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT (0x00A26000)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___POR 0x0000000A
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___POR 0x0A
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___M 0x000000FF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___M 0x000000FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT (0x00A26004)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___POR 0x000003E8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___POR 0x03E8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___M 0x00003FFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___M 0x00003FFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT (0x00A26008)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___POR 0x000003E8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___POR 0x000003E8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS (0x00A2600C)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___M 0x000000F0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___M 0x000000F0   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___S               4

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS (0x00A26010)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___M 0x000000F0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___M 0x000000F3   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP (0x00A26014)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP (0x00A26018)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP (0x00A2601C)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP (0x00A26020)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE (0x00A26024)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___POR 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___POR 0x1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___S              23
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___S              22
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___S              21
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___S              20
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S              16
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___S              15
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S              14
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S              13
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S              12
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___M 0x00FFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE (0x00A26028)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___POR 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___POR 0x1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___S              23
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___S              22
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___S              21
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___S              20
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S              16
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___S              15
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S              14
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S              13
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S              12
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___M 0x00FFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE (0x00A2602C)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___M 0x00000001   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE (0x00A26030)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___POR 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___POR 0x1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___S              23
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___S              22
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___S              21
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___S              20
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S              16
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___S              15
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S              14
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S              13
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S              12
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___M 0x00FFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS    (0x00A27000)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE    (0x00A27004)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR       (0x00A27008)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR (0x00A2700C)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S              17
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES  (0x00A27010)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___M 0xFFFFFFFF
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___M 0xFFFFFFFF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL  (0x00A27014)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___M 0xF0000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___S              28
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___M 0x01000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___S              24
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___M 0xF100000F   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS    (0x00A27018)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE (0x00A2701C)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___S               0

#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR  (0x00A27020)
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___POR 0x00000000
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___M 0x00000200
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___S               9
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___M 0x00000100
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___S               8
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___M 0x00000080
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___S               7
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___M 0x00000040
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___S               6
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___M 0x00000020
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___S               5
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___M 0x00000010
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___S               4
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___M 0x00000008
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___S               3
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___M 0x00000004
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___S               2
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___M 0x00000002
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___S               1
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___M 0x00000001
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___S               0
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___M 0x000003FF   
#define   UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR (0x00A28000)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___M 0xFFFFFFFC
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___M 0xFFFFFFFC   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___S               2

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2 (0x00A28004)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___POR 0x00
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___M 0x0000001F
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___M 0x0000001F   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES (0x00A28008)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___POR 0x00000015
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___POR 0x15
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___M 0x000000FF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___M 0x000000FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX (0x00A2800C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___POR 0x00
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___M 0x000000FF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___M 0x000001FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX (0x00A28010)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___POR 0x00
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___M 0x000000FF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___M 0x000000FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT (0x00A28014)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN (0x00A28018)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR (0x00A2801C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY (0x00A28020)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL (0x00A28024)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___M 0x00000003   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1 (0x00A28028)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0 (0x00A2802C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1 (0x00A28030)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2 (0x00A28034)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL (0x00A28038)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___M 0x0000000F   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL (0x00A2803C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___M 0x00000003   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY (0x00A28040)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE (0x00A28044)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___M 0x00000001   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS    (0x00A29000)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE    (0x00A29004)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR     (0x00A29008)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP (0x00A2900C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP (0x00A29010)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP (0x00A29014)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR (0x00A29018)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR (0x00A2901C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S              17
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES  (0x00A29020)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___M 0xFFFFFFFF
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___M 0xFFFFFFFF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL  (0x00A29024)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___M 0xF0000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___S              28
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___M 0x01000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___S              24
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___M 0xF100000F   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS    (0x00A29028)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE (0x00A2902C)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___S               0

#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR  (0x00A29030)
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___POR 0x00000000
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___POR 0x0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___M 0x00000200
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___S               9
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___M 0x00000100
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___S               8
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___M 0x00000080
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___S               7
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___M 0x00000040
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___S               6
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___M 0x00000020
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___S               5
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___M 0x00000010
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___S               4
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___M 0x00000008
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___S               3
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___M 0x00000004
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___S               2
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___M 0x00000002
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___S               1
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___M 0x00000001
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___S               0
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___M 0x000003FF   
#define   UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL  (0x00A2A000)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___M 0xE0000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___S              29
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___M 0x10000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___S              28
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___M 0x0E000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___S              25
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___M 0x01000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___S              24
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___M 0x00800000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___S              23
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___M 0x00400000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___S              22
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___M 0x00001000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___S              12
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___M 0xFFC01FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR (0x00A2A004)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___POR 0x00000026
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___M 0x000000FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT (0x00A2A008)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___POR 0x0000000F
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___POR 0x0F
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___M 0x000000FF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___M 0x000000FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL (0x00A2A00C)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___POR 0x040008FC
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___POR 0x08
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___M 0x04000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___S              26
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___M 0x03800000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___S              23
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___M 0x00400000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___S              22
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___M 0x00200000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___S              21
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___M 0x00100000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___S              20
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___M 0x000E0000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___S              17
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___M 0x00010000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___S              16
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___M 0x00008000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___S              15
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___M 0x00004000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___S              14
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___M 0x00003F00
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___M 0x07FFFFFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS (0x00A2A010)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___POR 0x000003FF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___M 0x000003FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT (0x00A2A014)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___POR 0x00000038
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___POR 0x38
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___M 0x000000FF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___M 0x000000FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL (0x00A2A018)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___M 0x80000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___S              31
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___M 0x40000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___S              30
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___M 0xC0000003   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS (0x00A2A01C)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___M 0x04000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___S              26
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___M 0x02000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___S              25
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___M 0x01C00000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___S              22
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___M 0x00380000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___S              19
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___M 0x00040000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___S              18
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___M 0x00020000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___S              17
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___M 0x00010000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___S              16
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___M 0x0000E000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___S              13
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___M 0x00001000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___S              12
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___M 0x00000700
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___M 0x000000E0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___M 0x0000000E
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___M 0x07FFFFFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE (0x00A2A020)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___M 0x00000001   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2 (0x00A2A024)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___M 0x00000700
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___M 0x000007FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2 (0x00A2A028)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___POR 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___M 0x000000E0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___M 0x000000FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS    (0x00A2B000)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE    (0x00A2B004)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR       (0x00A2B008)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP (0x00A2B00C)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP (0x00A2B010)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR (0x00A2B014)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S              17
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES  (0x00A2B018)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___POR 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___POR 0x1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___M 0x00000300
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___M 0x000000C0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___M 0x00000030
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___M 0x0000000F
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___M 0x000003FF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL  (0x00A2B01C)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___M 0xF0000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___S              28
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___M 0x01000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___S              24
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___M 0xF100000F   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS    (0x00A2B020)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___RWC QCSR_REG_RO    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE (0x00A2B024)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___S               0

#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR  (0x00A2B028)
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW    
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___POR 0x00000000
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___POR 0x0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___M 0x00000800
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___S              11
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___M 0x00000400
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___S              10
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___M 0x00000200
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___S               9
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___M 0x00000100
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___S               8
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___M 0x00000080
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___S               7
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___M 0x00000040
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___S               6
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___M 0x00000020
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___S               5
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___M 0x00000010
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___S               4
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___M 0x00000008
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___S               3
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___M 0x00000004
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___S               2
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___M 0x00000002
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___S               1
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___M 0x00000001
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___S               0
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___M 0x00000FFF   
#define   UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___S               0

#define UMAC_TRACER_R0_CONTROL                    (0x00A30000)
#define   UMAC_TRACER_R0_CONTROL___RWC              QCSR_REG_RW    
#define   UMAC_TRACER_R0_CONTROL___POR           0x00000000
#define   UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___POR 0x0
#define   UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___M 0x00002000
#define   UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___S              13
#define   UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___M 0x00001000
#define   UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___S              12
#define   UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___M 0x00000C00
#define   UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___S              10
#define   UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___M 0x00000300
#define   UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___S               8
#define   UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___M 0x00000010
#define   UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___S               4
#define   UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___M 0x00000002
#define   UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___S               1
#define   UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___M 0x00000001
#define   UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___S               0
#define   UMAC_TRACER_R0_CONTROL___M             0x00003F13   
#define   UMAC_TRACER_R0_CONTROL___S                           0

#define UMAC_TRACER_R0_BUF_INIT                   (0x00A30004)
#define   UMAC_TRACER_R0_BUF_INIT___RWC             QCSR_REG_RW    
#define   UMAC_TRACER_R0_BUF_INIT___POR          0x00000000
#define   UMAC_TRACER_R0_BUF_INIT__VALUE___POR   0x0
#define   UMAC_TRACER_R0_BUF_INIT__VALUE___M     0x00000001
#define   UMAC_TRACER_R0_BUF_INIT__VALUE___S                   0
#define   UMAC_TRACER_R0_BUF_INIT___M            0x00000001   
#define   UMAC_TRACER_R0_BUF_INIT___S                          0

#define UMAC_TRACER_R0_ADDR                       (0x00A30008)
#define   UMAC_TRACER_R0_ADDR___RWC                 QCSR_REG_RW    
#define   UMAC_TRACER_R0_ADDR___POR              0x00000000
#define   UMAC_TRACER_R0_ADDR__END_VALUE___POR   0x0000
#define   UMAC_TRACER_R0_ADDR__START_VALUE___POR 0x0000
#define   UMAC_TRACER_R0_ADDR__END_VALUE___M     0x3FFF0000
#define   UMAC_TRACER_R0_ADDR__END_VALUE___S                  16
#define   UMAC_TRACER_R0_ADDR__START_VALUE___M   0x00003FFF
#define   UMAC_TRACER_R0_ADDR__START_VALUE___S                 0
#define   UMAC_TRACER_R0_ADDR___M                0x3FFF3FFF   
#define   UMAC_TRACER_R0_ADDR___S                              0

#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL           (0x00A3000C)
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL___RWC     QCSR_REG_RW    
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL___POR  0x00000000
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___S              30
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___S               0
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL___M    0xFFFFFFFF   
#define   UMAC_TRACER_R0_WFT_CAPTURE_CTRL___S                  0

#define UMAC_TRACER_R0_WFT_STATE_CTRL             (0x00A30010)
#define   UMAC_TRACER_R0_WFT_STATE_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TRACER_R0_WFT_STATE_CTRL___POR    0x00000000
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_WFT_STATE_CTRL___M      0xFFFF001F   
#define   UMAC_TRACER_R0_WFT_STATE_CTRL___S                    0

#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0       (0x00A30014)
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___S              30
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___S               0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___M 0xFFFFFFFF   
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___S               0

#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0         (0x00A30018)
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___POR 0x00000000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___M  0xFFFF001F   
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___S                0

#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0          (0x00A3001C)
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___RWC    QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___M   0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___S                 0

#define UMAC_TRACER_R0_TS_TRIG_IX_0               (0x00A30020)
#define   UMAC_TRACER_R0_TS_TRIG_IX_0___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_IX_0___POR      0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_IX_0___M        0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_IX_0___S                      0

#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1       (0x00A30024)
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___S              30
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___S               0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___M 0xFFFFFFFF   
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___S               0

#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1         (0x00A30028)
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___POR 0x00000000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___M  0xFFFF001F   
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___S                0

#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1          (0x00A3002C)
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___RWC    QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___M   0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___S                 0

#define UMAC_TRACER_R0_TS_TRIG_IX_1               (0x00A30030)
#define   UMAC_TRACER_R0_TS_TRIG_IX_1___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_IX_1___POR      0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_IX_1___M        0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_IX_1___S                      0

#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2       (0x00A30034)
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___S              30
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___S               0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___M 0xFFFFFFFF   
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___S               0

#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2         (0x00A30038)
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___POR 0x00000000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___M  0xFFFF001F   
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___S                0

#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2          (0x00A3003C)
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___RWC    QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___M   0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___S                 0

#define UMAC_TRACER_R0_TS_TRIG_IX_2               (0x00A30040)
#define   UMAC_TRACER_R0_TS_TRIG_IX_2___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_IX_2___POR      0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_IX_2___M        0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_IX_2___S                      0

#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3       (0x00A30044)
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___S              30
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___S               0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___M 0xFFFFFFFF   
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___S               0

#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3         (0x00A30048)
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___POR 0x00000000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___M  0xFFFF001F   
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___S                0

#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3          (0x00A3004C)
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___RWC    QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___M   0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___S                 0

#define UMAC_TRACER_R0_TS_TRIG_IX_3               (0x00A30050)
#define   UMAC_TRACER_R0_TS_TRIG_IX_3___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_IX_3___POR      0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_IX_3___M        0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_IX_3___S                      0

#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4       (0x00A30054)
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___POR 0x0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___POR 0x00000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___M 0xC0000000
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___S              30
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___S               0
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___M 0xFFFFFFFF   
#define   UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___S               0

#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4         (0x00A30058)
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___POR 0x00000000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___POR 0x0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___POR 0x00
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___M 0xFFFF0000
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___S              16
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___M 0x0000001F
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___S               0
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___M  0xFFFF001F   
#define   UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___S                0

#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4          (0x00A3005C)
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___RWC    QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___M   0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___S                 0

#define UMAC_TRACER_R0_TS_TRIG_IX_4               (0x00A30060)
#define   UMAC_TRACER_R0_TS_TRIG_IX_4___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_TS_TRIG_IX_4___POR      0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___S               0
#define   UMAC_TRACER_R0_TS_TRIG_IX_4___M        0x3FFFFFFF   
#define   UMAC_TRACER_R0_TS_TRIG_IX_4___S                      0

#define UMAC_TRACER_R0_CPU_ADDR                   (0x00A30064)
#define   UMAC_TRACER_R0_CPU_ADDR___RWC             QCSR_REG_RW    
#define   UMAC_TRACER_R0_CPU_ADDR___POR          0x00000000
#define   UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___M 0xFFFFFFFF
#define   UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___S               0
#define   UMAC_TRACER_R0_CPU_ADDR___M            0xFFFFFFFF   
#define   UMAC_TRACER_R0_CPU_ADDR___S                          0

#define UMAC_TRACER_R0_CPU_DATA                   (0x00A30068)
#define   UMAC_TRACER_R0_CPU_DATA___RWC             QCSR_REG_RO    
#define   UMAC_TRACER_R0_CPU_DATA___POR          0x00000000
#define   UMAC_TRACER_R0_CPU_DATA__VALUE___POR   0x00000000
#define   UMAC_TRACER_R0_CPU_DATA__VALUE___M     0xFFFFFFFF
#define   UMAC_TRACER_R0_CPU_DATA__VALUE___S                   0
#define   UMAC_TRACER_R0_CPU_DATA___M            0xFFFFFFFF   
#define   UMAC_TRACER_R0_CPU_DATA___S                          0

#define UMAC_TRACER_R0_STATUS_0                   (0x00A3006C)
#define   UMAC_TRACER_R0_STATUS_0___RWC             QCSR_REG_RO    
#define   UMAC_TRACER_R0_STATUS_0___POR          0x00000000
#define   UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___POR 0x0
#define   UMAC_TRACER_R0_STATUS_0__BUF_FULL___POR 0x0
#define   UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___M 0x00000002
#define   UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___S               1
#define   UMAC_TRACER_R0_STATUS_0__BUF_FULL___M  0x00000001
#define   UMAC_TRACER_R0_STATUS_0__BUF_FULL___S                0
#define   UMAC_TRACER_R0_STATUS_0___M            0x00000003   
#define   UMAC_TRACER_R0_STATUS_0___S                          0

#define UMAC_TRACER_R0_STATUS_1                   (0x00A30070)
#define   UMAC_TRACER_R0_STATUS_1___RWC             QCSR_REG_RO    
#define   UMAC_TRACER_R0_STATUS_1___POR          0x00000000
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___POR 0x0000
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___POR 0x0000
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___M 0x3FFF0000
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___S              16
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___M 0x00003FFF
#define   UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___S               0
#define   UMAC_TRACER_R0_STATUS_1___M            0x3FFF3FFF   
#define   UMAC_TRACER_R0_STATUS_1___S                          0

#define UMAC_TRACER_R0_STATUS_2                   (0x00A30074)
#define   UMAC_TRACER_R0_STATUS_2___RWC             QCSR_REG_RO    
#define   UMAC_TRACER_R0_STATUS_2___POR          0x00000000
#define   UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___POR 0x00
#define   UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___POR 0x0
#define   UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___POR 0x0
#define   UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___M 0x00001F00
#define   UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___S               8
#define   UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___M 0x00000070
#define   UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___S               4
#define   UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___M 0x00000007
#define   UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___S               0
#define   UMAC_TRACER_R0_STATUS_2___M            0x00001F77   
#define   UMAC_TRACER_R0_STATUS_2___S                          0

#define UMAC_TRACER_R0_STATUS_3                   (0x00A30078)
#define   UMAC_TRACER_R0_STATUS_3___RWC             QCSR_REG_RO    
#define   UMAC_TRACER_R0_STATUS_3___POR          0x00000000
#define   UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___POR 0x00000000
#define   UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___M 0x3FFFFFFF
#define   UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___S               0
#define   UMAC_TRACER_R0_STATUS_3___M            0x3FFFFFFF   
#define   UMAC_TRACER_R0_STATUS_3___S                          0

#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL         (0x00A3007C)
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___RWC   QCSR_REG_RW    
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___POR 0x00000000
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___POR 0x00000000
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___M 0xFFFFFFFF
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___S               0
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___M  0xFFFFFFFF   
#define   UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___S                0

#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL     (0x00A30080)
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___POR 0x00000000
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___POR 0x0
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___M 0x00000001
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___S               0
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___M 0x00000001   
#define   UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___S               0

#define UMAC_TRACER_R0_LANE_SWAP                  (0x00A30084)
#define   UMAC_TRACER_R0_LANE_SWAP___RWC            QCSR_REG_RW    
#define   UMAC_TRACER_R0_LANE_SWAP___POR         0x0000000F
#define   UMAC_TRACER_R0_LANE_SWAP__SEL___POR    0x0F
#define   UMAC_TRACER_R0_LANE_SWAP__SEL___M      0x0000001F
#define   UMAC_TRACER_R0_LANE_SWAP__SEL___S                    0
#define   UMAC_TRACER_R0_LANE_SWAP___M           0x0000001F   
#define   UMAC_TRACER_R0_LANE_SWAP___S                         0

#define UMAC_TRACER_R0_CLK_GATE_DISABLE           (0x00A30088)
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE___RWC     QCSR_REG_RW    
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE___POR  0x00000000
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___POR 0x0
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___POR 0x0000000
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___POR 0x0
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___POR 0x0
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___M 0x40000000
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___S              30
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFFC
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___S               2
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000002
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___S               1
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___M 0x00000001
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___S               0
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE___M    0xFFFFFFFF   
#define   UMAC_TRACER_R0_CLK_GATE_DISABLE___S                  0

#define UMAC_TRACER_R0_TIME_STAMP                 (0x00A3008C)
#define   UMAC_TRACER_R0_TIME_STAMP___RWC           QCSR_REG_RW    
#define   UMAC_TRACER_R0_TIME_STAMP___POR        0x00000000
#define   UMAC_TRACER_R0_TIME_STAMP__SEL___POR   0x0
#define   UMAC_TRACER_R0_TIME_STAMP__SEL___M     0x00000001
#define   UMAC_TRACER_R0_TIME_STAMP__SEL___S                   0
#define   UMAC_TRACER_R0_TIME_STAMP___M          0x00000001   
#define   UMAC_TRACER_R0_TIME_STAMP___S                        0

#define UMAC_TRACER_R0_CSS_RTL_VERSION            (0x00A30090)
#define   UMAC_TRACER_R0_CSS_RTL_VERSION___RWC      QCSR_REG_RO    
#define   UMAC_TRACER_R0_CSS_RTL_VERSION___POR   0x00000000
#define   UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___POR 0x00000000
#define   UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___M 0xFFFFFFFF
#define   UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___S               0
#define   UMAC_TRACER_R0_CSS_RTL_VERSION___M     0xFFFFFFFF   
#define   UMAC_TRACER_R0_CSS_RTL_VERSION___S                   0

#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR       (0x00A30094)
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO    
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x000
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x00000FFF
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___S               0
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___M 0x00000FFF   
#define   UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___S               0

#define UMAC_TRACER_R0_INT_CTRL                   (0x00A30098)
#define   UMAC_TRACER_R0_INT_CTRL___RWC             QCSR_REG_RW    
#define   UMAC_TRACER_R0_INT_CTRL___POR          0x00000000
#define   UMAC_TRACER_R0_INT_CTRL__MODE___POR    0x0
#define   UMAC_TRACER_R0_INT_CTRL__ENABLE___POR  0x0
#define   UMAC_TRACER_R0_INT_CTRL__MODE___M      0x00000002
#define   UMAC_TRACER_R0_INT_CTRL__MODE___S                    1
#define   UMAC_TRACER_R0_INT_CTRL__ENABLE___M    0x00000001
#define   UMAC_TRACER_R0_INT_CTRL__ENABLE___S                  0
#define   UMAC_TRACER_R0_INT_CTRL___M            0x00000003   
#define   UMAC_TRACER_R0_INT_CTRL___S                          0

#define UMAC_TRACER_R0_INT_TRIG_STATE             (0x00A3009C)
#define   UMAC_TRACER_R0_INT_TRIG_STATE___RWC       QCSR_REG_RW    
#define   UMAC_TRACER_R0_INT_TRIG_STATE___POR    0x00000001
#define   UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___M 0x00000007
#define   UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___S               0
#define   UMAC_TRACER_R0_INT_TRIG_STATE___M      0x00000007   
#define   UMAC_TRACER_R0_INT_TRIG_STATE___S                    0

#define UMAC_TRACER_R0_INT_TRIG_PATTERN           (0x00A300A0)
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN___RWC     QCSR_REG_RW    
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN___POR  0x11111111
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___POR 0x1
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___M 0x70000000
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___S              28
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___M 0x07000000
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___S              24
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___M 0x00700000
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___S              20
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___M 0x00070000
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___S              16
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___M 0x00007000
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___S              12
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___M 0x00000700
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___S               8
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___M 0x00000070
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___S               4
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___M 0x00000007
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___S               0
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN___M    0x77777777   
#define   UMAC_TRACER_R0_INT_TRIG_PATTERN___S                  0

#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK (0x00A300A4)
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___POR 0x00000000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___POR 0x0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___M 0x00020000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___S              17
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___M 0x00010000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___S              16
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___M 0x00008000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___S              15
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___M 0x00004000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___S              14
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___M 0x00002000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___S              13
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___M 0x00001000
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___S              12
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___M 0x00000800
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___S              11
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___M 0x00000400
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___S              10
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___M 0x00000200
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___S               9
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___M 0x00000100
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___S               8
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___M 0x00000080
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___S               7
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___M 0x00000040
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___S               6
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___M 0x00000020
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___S               5
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___M 0x00000010
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___S               4
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___M 0x00000008
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___S               3
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___M 0x00000004
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___S               2
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___M 0x00000002
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___S               1
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___M 0x00000001
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___S               0
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___M 0x0003FFFF   
#define   UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___S               0

#define UMAC_TRACER_R0_INTR_BITMASK               (0x00A300A8)
#define   UMAC_TRACER_R0_INTR_BITMASK___RWC         QCSR_REG_RW    
#define   UMAC_TRACER_R0_INTR_BITMASK___POR      0x00000000
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___POR 0x0
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___POR 0x0
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___POR 0x0
#define   UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___POR 0x0
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___M 0x00000008
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___S               3
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___M 0x00000004
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___S               2
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___M 0x00000002
#define   UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___S               1
#define   UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___M 0x00000001
#define   UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___S               0
#define   UMAC_TRACER_R0_INTR_BITMASK___M        0x0000000F   
#define   UMAC_TRACER_R0_INTR_BITMASK___S                      0

#define UMAC_TRACER_R0_VID0                       (0x00A300AC)
#define   UMAC_TRACER_R0_VID0___RWC                 QCSR_REG_RW    
#define   UMAC_TRACER_R0_VID0___POR              0x00000000
#define   UMAC_TRACER_R0_VID0__CXC2___POR        0x0
#define   UMAC_TRACER_R0_VID0__TCL___POR         0x0
#define   UMAC_TRACER_R0_VID0__WBM___POR         0x0
#define   UMAC_TRACER_R0_VID0__TQM___POR         0x0
#define   UMAC_TRACER_R0_VID0__REO___POR         0x0
#define   UMAC_TRACER_R0_VID0__CXC___POR         0x0
#define   UMAC_TRACER_R0_VID0__CE___POR          0x0
#define   UMAC_TRACER_R0_VID0__MODULE_EN___POR   0x0
#define   UMAC_TRACER_R0_VID0__CXC2___M          0xF0000000
#define   UMAC_TRACER_R0_VID0__CXC2___S                       28
#define   UMAC_TRACER_R0_VID0__TCL___M           0x0F000000
#define   UMAC_TRACER_R0_VID0__TCL___S                        24
#define   UMAC_TRACER_R0_VID0__WBM___M           0x00F00000
#define   UMAC_TRACER_R0_VID0__WBM___S                        20
#define   UMAC_TRACER_R0_VID0__TQM___M           0x000F0000
#define   UMAC_TRACER_R0_VID0__TQM___S                        16
#define   UMAC_TRACER_R0_VID0__REO___M           0x0000F000
#define   UMAC_TRACER_R0_VID0__REO___S                        12
#define   UMAC_TRACER_R0_VID0__CXC___M           0x00000F00
#define   UMAC_TRACER_R0_VID0__CXC___S                         8
#define   UMAC_TRACER_R0_VID0__CE___M            0x000000F0
#define   UMAC_TRACER_R0_VID0__CE___S                          4
#define   UMAC_TRACER_R0_VID0__MODULE_EN___M     0x00000001
#define   UMAC_TRACER_R0_VID0__MODULE_EN___S                   0
#define   UMAC_TRACER_R0_VID0___M                0xFFFFFFF1   
#define   UMAC_TRACER_R0_VID0___S                              0

#define UMAC_TRACER_R0_VID0_EXT                   (0x00A300B0)
#define   UMAC_TRACER_R0_VID0_EXT___RWC             QCSR_REG_RW    
#define   UMAC_TRACER_R0_VID0_EXT___POR          0x00000000
#define   UMAC_TRACER_R0_VID0_EXT__PHY_B___POR   0x0
#define   UMAC_TRACER_R0_VID0_EXT__PHY_A___POR   0x0
#define   UMAC_TRACER_R0_VID0_EXT__TQM2___POR    0x0
#define   UMAC_TRACER_R0_VID0_EXT__REO2___POR    0x0
#define   UMAC_TRACER_R0_VID0_EXT__WBM2___POR    0x0
#define   UMAC_TRACER_R0_VID0_EXT__TCL_1___POR   0x0
#define   UMAC_TRACER_R0_VID0_EXT__PHY_B___M     0x00F00000
#define   UMAC_TRACER_R0_VID0_EXT__PHY_B___S                  20
#define   UMAC_TRACER_R0_VID0_EXT__PHY_A___M     0x000F0000
#define   UMAC_TRACER_R0_VID0_EXT__PHY_A___S                  16
#define   UMAC_TRACER_R0_VID0_EXT__TQM2___M      0x0000F000
#define   UMAC_TRACER_R0_VID0_EXT__TQM2___S                   12
#define   UMAC_TRACER_R0_VID0_EXT__REO2___M      0x00000F00
#define   UMAC_TRACER_R0_VID0_EXT__REO2___S                    8
#define   UMAC_TRACER_R0_VID0_EXT__WBM2___M      0x000000F0
#define   UMAC_TRACER_R0_VID0_EXT__WBM2___S                    4
#define   UMAC_TRACER_R0_VID0_EXT__TCL_1___M     0x0000000F
#define   UMAC_TRACER_R0_VID0_EXT__TCL_1___S                   0
#define   UMAC_TRACER_R0_VID0_EXT___M            0x00FFFFFF   
#define   UMAC_TRACER_R0_VID0_EXT___S                          0

#define UMAC_TRACER_R0_INTR_STATUS                (0x00A300B4)
#define   UMAC_TRACER_R0_INTR_STATUS___RWC          QCSR_REG_RW    
#define   UMAC_TRACER_R0_INTR_STATUS___POR       0x00000000
#define   UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___POR 0x0
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___POR 0x0
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___POR 0x0
#define   UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___POR 0x0
#define   UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___M 0x00000008
#define   UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___S               3
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___M 0x00000004
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___S               2
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___M 0x00000002
#define   UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___S               1
#define   UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___M 0x00000001
#define   UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___S               0
#define   UMAC_TRACER_R0_INTR_STATUS___M         0x0000000F   
#define   UMAC_TRACER_R0_INTR_STATUS___S                       0

#define UMAC_TRACER_R0_STM_EVENTS_SEL             (0x00A300B8)
#define   UMAC_TRACER_R0_STM_EVENTS_SEL___RWC       QCSR_REG_RW    
#define   UMAC_TRACER_R0_STM_EVENTS_SEL___POR    0x00000000
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___POR 0x00
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___POR 0x0
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___POR 0x0000000
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___M 0xFC000000
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___S              26
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___M 0x02000000
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___S              25
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___M 0x01FFFFFF
#define   UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___S               0
#define   UMAC_TRACER_R0_STM_EVENTS_SEL___M      0xFFFFFFFF   
#define   UMAC_TRACER_R0_STM_EVENTS_SEL___S                    0

#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL (0x00A300BC)
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___POR 0x00000000
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___M 0x00000200
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___S               9
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___M 0x00000100
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___S               8
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___M 0x00000080
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___S               7
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___M 0x00000070
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___S               4
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___M 0x00000008
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___S               3
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___M 0x00000007
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___S               0
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___M 0x000003FF   
#define   UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___S               0

#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL (0x00A300C0)
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___POR 0x00000000
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___POR 0x00
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___M 0x0000001F
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___S               0
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___M 0x0000001F   
#define   UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___S               0

#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL (0x00A300C4)
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___POR 0x00000000
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___S               1
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___S               0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___M 0x0000000F   
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___S               0

#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL (0x00A300C8)
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___POR 0x00000000
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___S               1
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___S               0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___M 0x0000000F   
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___S               0

#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL (0x00A300CC)
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___POR 0x00000000
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___S               1
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___S               0
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___M 0x0000000F   
#define   UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___S               0

#define UMAC_TRACER_R0_CLK_TESTBUS_OUT            (0x00A300D0)
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT___RWC      QCSR_REG_RW    
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT___POR   0x00000000
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___POR 0x0
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___M 0x00000001
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___S               0
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT___M     0x00000001   
#define   UMAC_TRACER_R0_CLK_TESTBUS_OUT___S                   0

#define UMAC_TRACER_R0_SS_ID                      (0x00A300D4)
#define   UMAC_TRACER_R0_SS_ID___RWC                QCSR_REG_RW    
#define   UMAC_TRACER_R0_SS_ID___POR             0x00039E40
#define   UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___POR 0x0
#define   UMAC_TRACER_R0_SS_ID__WCMN_MISC___POR  0x0
#define   UMAC_TRACER_R0_SS_ID__UMAC_DBG___POR   0x3
#define   UMAC_TRACER_R0_SS_ID__PHY2___POR       0x2
#define   UMAC_TRACER_R0_SS_ID__PHY1___POR       0x1
#define   UMAC_TRACER_R0_SS_ID__UMAC___POR       0x3
#define   UMAC_TRACER_R0_SS_ID__LMAC3___POR      0x2
#define   UMAC_TRACER_R0_SS_ID__LMAC2___POR      0x1
#define   UMAC_TRACER_R0_SS_ID__LMAC1___POR      0x0
#define   UMAC_TRACER_R0_SS_ID__ENABLE___POR     0x0
#define   UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___M 0x00100000
#define   UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___S              20
#define   UMAC_TRACER_R0_SS_ID__WCMN_MISC___M    0x000C0000
#define   UMAC_TRACER_R0_SS_ID__WCMN_MISC___S                 18
#define   UMAC_TRACER_R0_SS_ID__UMAC_DBG___M     0x00030000
#define   UMAC_TRACER_R0_SS_ID__UMAC_DBG___S                  16
#define   UMAC_TRACER_R0_SS_ID__PHY2___M         0x0000C000
#define   UMAC_TRACER_R0_SS_ID__PHY2___S                      14
#define   UMAC_TRACER_R0_SS_ID__PHY1___M         0x00003000
#define   UMAC_TRACER_R0_SS_ID__PHY1___S                      12
#define   UMAC_TRACER_R0_SS_ID__UMAC___M         0x00000C00
#define   UMAC_TRACER_R0_SS_ID__UMAC___S                      10
#define   UMAC_TRACER_R0_SS_ID__LMAC3___M        0x00000300
#define   UMAC_TRACER_R0_SS_ID__LMAC3___S                      8
#define   UMAC_TRACER_R0_SS_ID__LMAC2___M        0x000000C0
#define   UMAC_TRACER_R0_SS_ID__LMAC2___S                      6
#define   UMAC_TRACER_R0_SS_ID__LMAC1___M        0x00000030
#define   UMAC_TRACER_R0_SS_ID__LMAC1___S                      4
#define   UMAC_TRACER_R0_SS_ID__ENABLE___M       0x00000001
#define   UMAC_TRACER_R0_SS_ID__ENABLE___S                     0
#define   UMAC_TRACER_R0_SS_ID___M               0x001FFFF1   
#define   UMAC_TRACER_R0_SS_ID___S                             0

#define UMAC_TRACER_R0_SPARE_BIT                  (0x00A300D8)
#define   UMAC_TRACER_R0_SPARE_BIT___RWC            QCSR_REG_RW    
#define   UMAC_TRACER_R0_SPARE_BIT___POR         0x00000000
#define   UMAC_TRACER_R0_SPARE_BIT__ENABLE___POR 0x0000
#define   UMAC_TRACER_R0_SPARE_BIT__ENABLE___M   0x0000FFFF
#define   UMAC_TRACER_R0_SPARE_BIT__ENABLE___S                 0
#define   UMAC_TRACER_R0_SPARE_BIT___M           0x0000FFFF   
#define   UMAC_TRACER_R0_SPARE_BIT___S                         0

#define UMAC_WBM_R0_GENERAL_ENABLE                (0x00A34000)
#define   UMAC_WBM_R0_GENERAL_ENABLE___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R0_GENERAL_ENABLE___POR       0x00000060
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___POR 0x1
#define   UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___POR 0x1
#define   UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___POR 0x0
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___M 0x00000080
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___S               7
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___M 0x00000040
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___S               6
#define   UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___M 0x00000020
#define   UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___S               5
#define   UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___M 0x00000010
#define   UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___S               4
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___M 0x00000008
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___S               3
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___M 0x00000004
#define   UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___S               2
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___M 0x00000002
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___S               1
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___M 0x00000001
#define   UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___S               0
#define   UMAC_WBM_R0_GENERAL_ENABLE___M         0x000000FF   
#define   UMAC_WBM_R0_GENERAL_ENABLE___S                       0

#define UMAC_WBM_R0_RELEASE_RING_ENABLE           (0x00A34004)
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE___POR  0x00000000
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___M 0x00000080
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___S               7
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___S               6
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___M 0x00000020
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___S               5
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___M 0x00000010
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___S               4
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___M 0x00000008
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___S               3
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___M 0x00000004
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___S               2
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___M 0x00000002
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___S               1
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___M 0x00000001
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___S               0
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE___M    0x000000FF   
#define   UMAC_WBM_R0_RELEASE_RING_ENABLE___S                  0

#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE       (0x00A34008)
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___POR 0x00000000
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___M 0x00000020
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___S               5
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___M 0x00000010
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___S               4
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___M 0x00000008
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___S               3
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___M 0x00000004
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___S               2
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___M 0x00000002
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___S               1
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___M 0x00000001
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___S               0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___M 0x0000003F   
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___S               0

#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE         (0x00A3400C)
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE___POR 0x00000000
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___S               6
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___M 0x00000020
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___S               5
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___M 0x00000010
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___S               4
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___M 0x00000008
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___S               3
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___M 0x00000004
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___S               2
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___M 0x00000002
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___S               1
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___M 0x00000001
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___S               0
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE___M  0x0000007F   
#define   UMAC_WBM_R0_LINK_DESC_RING_ENABLE___S                0

#define UMAC_WBM_R0_MISC_RING_ENABLE              (0x00A34010)
#define   UMAC_WBM_R0_MISC_RING_ENABLE___RWC        QCSR_REG_RW    
#define   UMAC_WBM_R0_MISC_RING_ENABLE___POR     0x0000003F
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___POR 0x1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___M 0x00000020
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___S               5
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___M 0x00000010
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___S               4
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___M 0x00000008
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___S               3
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___M 0x00000004
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___S               2
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___M 0x00000002
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___S               1
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___M 0x00000001
#define   UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___S               0
#define   UMAC_WBM_R0_MISC_RING_ENABLE___M       0x0000003F   
#define   UMAC_WBM_R0_MISC_RING_ENABLE___S                     0

#define UMAC_WBM_R0_RELEASE_RING_STATUS           (0x00A34014)
#define   UMAC_WBM_R0_RELEASE_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_WBM_R0_RELEASE_RING_STATUS___POR  0x00000000
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___M 0x00000080
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___S               7
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___M 0x00000040
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___S               6
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___M 0x00000020
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___S               5
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___M 0x00000010
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___S               4
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___M 0x00000008
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___S               3
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___M 0x00000004
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___S               2
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___M 0x00000002
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___S               1
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___M 0x00000001
#define   UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___S               0
#define   UMAC_WBM_R0_RELEASE_RING_STATUS___M    0x000000FF   
#define   UMAC_WBM_R0_RELEASE_RING_STATUS___S                  0

#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS       (0x00A34018)
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___M 0x00000020
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___S               5
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___M 0x00000010
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___S               4
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___M 0x00000008
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___S               3
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___M 0x00000004
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___S               2
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___M 0x00000002
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___S               1
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___M 0x00000001
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___S               0
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___M 0x0000003F   
#define   UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___S               0

#define UMAC_WBM_R0_LINK_DESC_RING_STATUS         (0x00A3401C)
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS___RWC   QCSR_REG_RO    
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___M 0x00000040
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___S               6
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___M 0x00000020
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___S               5
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___M 0x00000010
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___S               4
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___M 0x00000008
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___S               3
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___M 0x00000004
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___S               2
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___M 0x00000002
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___S               1
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___M 0x00000001
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___S               0
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS___M  0x0000007F   
#define   UMAC_WBM_R0_LINK_DESC_RING_STATUS___S                0

#define UMAC_WBM_R0_MISC_RING_STATUS              (0x00A34020)
#define   UMAC_WBM_R0_MISC_RING_STATUS___RWC        QCSR_REG_RO    
#define   UMAC_WBM_R0_MISC_RING_STATUS___POR     0x00000000
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___POR 0x0
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___M 0x00000200
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___S               9
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___M 0x00000100
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___S               8
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___M 0x00000080
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___S               7
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___M 0x00000040
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___S               6
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___M 0x00000020
#define   UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___S               5
#define   UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___M 0x00000010
#define   UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___S               4
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___M 0x00000008
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___S               3
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___M 0x00000004
#define   UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___S               2
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___M 0x00000002
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___S               1
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___M 0x00000001
#define   UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___S               0
#define   UMAC_WBM_R0_MISC_RING_STATUS___M       0x000003FF   
#define   UMAC_WBM_R0_MISC_RING_STATUS___S                     0

#define UMAC_WBM_R0_RELEASE_RING_FLUSH            (0x00A34024)
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH___POR   0x00000000
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___POR 0x0
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___POR 0x000
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___M 0x00010000
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___S              16
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___M 0x00002000
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___S              13
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___M 0x00001000
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___S              12
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___M 0x00000FFF
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___S               0
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH___M     0x00013FFF   
#define   UMAC_WBM_R0_RELEASE_RING_FLUSH___S                   0

#define UMAC_WBM_R0_IDLE_STATUS                   (0x00A34028)
#define   UMAC_WBM_R0_IDLE_STATUS___RWC             QCSR_REG_RO    
#define   UMAC_WBM_R0_IDLE_STATUS___POR          0x00000000
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___M 0x00008000
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___S              15
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___M 0x00004000
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___S              14
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___M 0x00002000
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___S              13
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___M 0x00001000
#define   UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___S              12
#define   UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000800
#define   UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___S              11
#define   UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000400
#define   UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___S              10
#define   UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000200
#define   UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___S               9
#define   UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000100
#define   UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___S               8
#define   UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000080
#define   UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___S               7
#define   UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000040
#define   UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___S               6
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___M 0x00000020
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___S               5
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___M 0x00000010
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___S               4
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___M 0x00000008
#define   UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___S               3
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___M 0x00000004
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___S               2
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___M 0x00000002
#define   UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___S               1
#define   UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___M 0x00000001
#define   UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___S               0
#define   UMAC_WBM_R0_IDLE_STATUS___M            0x0000FFFF   
#define   UMAC_WBM_R0_IDLE_STATUS___S                          0

#define UMAC_WBM_R0_IDLE_SEQUENCE                 (0x00A3402C)
#define   UMAC_WBM_R0_IDLE_SEQUENCE___RWC           QCSR_REG_RO    
#define   UMAC_WBM_R0_IDLE_SEQUENCE___POR        0x00000000
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___POR 0x0
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___POR 0x0
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___M 0x00000020
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___S               5
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___M 0x00000010
#define   UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___S               4
#define   UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___M 0x0000000F
#define   UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___S               0
#define   UMAC_WBM_R0_IDLE_SEQUENCE___M          0x0000003F   
#define   UMAC_WBM_R0_IDLE_SEQUENCE___S                        0

#define UMAC_WBM_R0_MSDU_PARSER_CONTROL           (0x00A34030)
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL___POR  0x00000000
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___POR 0x0
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___POR 0x0
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___POR 0x0
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___M 0x00000004
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___S               2
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___M 0x00000002
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___S               1
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___M 0x00000001
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___S               0
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL___M    0x00000007   
#define   UMAC_WBM_R0_MSDU_PARSER_CONTROL___S                  0

#define UMAC_WBM_R0_MSDU_PARSER_STATUS            (0x00A34034)
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS___POR   0x00000441
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___POR 0x0
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___POR 0x1
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___POR 0x1
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___POR 0x0
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___POR 0x01
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___M 0x00000800
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___S              11
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___M 0x00000400
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___S              10
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___M 0x000003C0
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___S               6
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___M 0x00000020
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___S               5
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___M 0x0000001F
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___S               0
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS___M     0x00000FFF   
#define   UMAC_WBM_R0_MSDU_PARSER_STATUS___S                   0

#define UMAC_WBM_R0_MISC_CONTROL                  (0x00A34038)
#define   UMAC_WBM_R0_MISC_CONTROL___RWC            QCSR_REG_RW    
#define   UMAC_WBM_R0_MISC_CONTROL___POR         0x000000C0
#define   UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___POR 0x00000030
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___POR 0x0
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___POR 0x0
#define   UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___M 0xFFFFFFFC
#define   UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___S               2
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___M 0x00000002
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___S               1
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___M 0x00000001
#define   UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___S               0
#define   UMAC_WBM_R0_MISC_CONTROL___M           0xFFFFFFFF   
#define   UMAC_WBM_R0_MISC_CONTROL___S                         0

#define UMAC_WBM_R0_WATCHDOG_TIMEOUT              (0x00A3403C)
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT___RWC        QCSR_REG_RW    
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT___POR     0x00000000
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___POR 0x0
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___POR 0x000
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___M 0x00003000
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___S              12
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___M 0x00000FFF
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___S               0
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT___M       0x00003FFF   
#define   UMAC_WBM_R0_WATCHDOG_TIMEOUT___S                     0

#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE        (0x00A34040)
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___RWC  QCSR_REG_RO    
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___POR 0x00000000
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___POR 0x00000
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___POR 0x0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___M 0x80000000
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___S              31
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___M 0x40000000
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___S              30
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___M 0x30000000
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___S              28
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___M 0x0FFFFF00
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___S               8
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___M 0x000000C0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___S               6
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___M 0x00000038
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___S               3
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___M 0x00000007
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___S               0
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___S               0

#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR          (0x00A34044)
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR___RWC    QCSR_REG_RO    
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___POR 0x0
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___POR 0x00000
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___M 0x00060000
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___S              17
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___M 0x0001FFFF
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___S               0
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR___M   0x0007FFFF   
#define   UMAC_WBM_R0_INVALID_APB_ACC_ADDR___S                 0

#define UMAC_WBM_R0_IDLE_LIST_CONTROL             (0x00A34048)
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL___RWC       QCSR_REG_RW    
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL___POR    0x00000010
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___POR 0x004
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___POR 0x0
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___POR 0x0
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___M 0x000007FC
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___S               2
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___M 0x00000002
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___S               1
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___M 0x00000001
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___S               0
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL___M      0x000007FF   
#define   UMAC_WBM_R0_IDLE_LIST_CONTROL___S                    0

#define UMAC_WBM_R0_IDLE_LIST_SIZE                (0x00A3404C)
#define   UMAC_WBM_R0_IDLE_LIST_SIZE___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R0_IDLE_LIST_SIZE___POR       0x00020002
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___POR 0x0002
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___POR 0x0002
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___M 0xFFFF0000
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___S              16
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___M 0x0000FFFF
#define   UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___S               0
#define   UMAC_WBM_R0_IDLE_LIST_SIZE___M         0xFFFFFFFF   
#define   UMAC_WBM_R0_IDLE_LIST_SIZE___S                       0

#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB   (0x00A34050)
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB   (0x00A34054)
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___POR 0x000000
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___M 0xFFFFFF00
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___S               8
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB (0x00A34058)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB (0x00A3405C)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___POR 0x000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___M 0xFFFFFF00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___S               8
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 (0x00A34060)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 (0x00A34064)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___POR 0x0000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___M 0x001FFF00
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___S               8
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___M 0x001FFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 (0x00A34068)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 (0x00A3406C)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___POR 0x0000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___M 0x001FFF00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___S               8
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___M 0x001FFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 (0x00A34070)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 (0x00A34074)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___POR 0x0000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___M 0x001FFF00
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___S               8
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___M 0x001FFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 (0x00A34078)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___S               0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 (0x00A3407C)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___POR 0x0000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___M 0x001FFF00
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___S               8
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___M 0x001FFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP          (0x00A34080)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___M   0x000FFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___S                 0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP    (0x00A34084)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___M 0x000FFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___S               0

#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP          (0x00A34088)
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___S               0
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___M   0x000FFFFF   
#define   UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___S                 0

#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP    (0x00A3408C)
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___POR 0x00000000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___S               0
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___M 0x000FFFFF   
#define   UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___S               0

#define UMAC_WBM_R0_CLK_GATE_CTRL                 (0x00A34090)
#define   UMAC_WBM_R0_CLK_GATE_CTRL___RWC           QCSR_REG_RW    
#define   UMAC_WBM_R0_CLK_GATE_CTRL___POR        0x00020000
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___POR 0x1
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___POR 0x0
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___POR 0x0000
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___M 0x00020000
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___S              17
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___M 0x00010000
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___S              16
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___M 0x0000FFFF
#define   UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___S               0
#define   UMAC_WBM_R0_CLK_GATE_CTRL___M          0x0003FFFF   
#define   UMAC_WBM_R0_CLK_GATE_CTRL___S                        0

#define UMAC_WBM_R0_GXI_TESTBUS_LOWER             (0x00A34094)
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER___RWC       QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER___POR    0x00000000
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER___M      0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_TESTBUS_LOWER___S                    0

#define UMAC_WBM_R0_GXI_TESTBUS_UPPER             (0x00A34098)
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER___RWC       QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER___POR    0x00000000
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___S               0
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER___M      0x000000FF   
#define   UMAC_WBM_R0_GXI_TESTBUS_UPPER___S                    0

#define UMAC_WBM_R0_GXI_SM_STATES_IX_0            (0x00A3409C)
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0___RWC      QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0___POR   0x00000211
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S               9
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S               4
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S               0
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0___M     0x00000FFF   
#define   UMAC_WBM_R0_GXI_SM_STATES_IX_0___S                   0

#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK         (0x00A340A0)
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___M  0x00000001   
#define   UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___S                0

#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE        (0x00A340A4)
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S              11
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S              10
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S               9
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S               8
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S               7
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S               6
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S               5
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S               4
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S               3
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S               2
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S               1
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___S               0
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF   
#define   UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___S               0

#define UMAC_WBM_R0_GXI_GXI_ERR_INTS              (0x00A340A8)
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS___RWC        QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS___POR     0x00000000
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S              24
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S              16
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S               8
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S               0
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS___M       0x01010101   
#define   UMAC_WBM_R0_GXI_GXI_ERR_INTS___S                     0

#define UMAC_WBM_R0_GXI_GXI_ERR_STATS             (0x00A340AC)
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS___RWC       QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS___POR    0x00000000
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S              16
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S               8
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S               0
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS___M      0x003F3F3F   
#define   UMAC_WBM_R0_GXI_GXI_ERR_STATS___S                    0

#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL       (0x00A340B0)
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S              24
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S               8
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S               0
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F   
#define   UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___S               0

#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL       (0x00A340B4)
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S              24
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S               8
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S               0
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F   
#define   UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___S               0

#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL          (0x00A340B8)
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S              27
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S              26
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S              25
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S              24
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S              23
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S              20
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S              17
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S               9
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S               1
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S               0
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___M   0x0FFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___S                 0

#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL          (0x00A340BC)
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S              16
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S               0
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___M   0xFFFF0001   
#define   UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___S                 0

#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS           (0x00A340C0)
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___POR  0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S               0
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___M    0x0000FFFF   
#define   UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___S                  0

#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS         (0x00A340C4)
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___RWC   QCSR_REG_RO    
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S              16
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S               0
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___M  0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___S                0

#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL       (0x00A340C8)
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___S               0

#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL       (0x00A340CC)
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___S               0

#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A340D0)
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A340D4)
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A340D8)
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A340DC)
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL    (0x00A340E0)
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S              15
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S               8
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S               7
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S               0
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F   
#define   UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB     (0x00A340E4)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB     (0x00A340E8)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_ID           (0x00A340EC)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID___M    0x000000FF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_ID___S                  0

#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS       (0x00A340F0)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC         (0x00A340F4)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC___M  0x003FFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MISC___S                0

#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB  (0x00A34100)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB  (0x00A34104)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A34114)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34118)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS (0x00A3411C)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34120)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A34124)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34128)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB (0x00A3412C)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB (0x00A34130)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA    (0x00A34134)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34138)
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB     (0x00A3413C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB     (0x00A34140)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_ID           (0x00A34144)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID___M    0x000000FF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_ID___S                  0

#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS       (0x00A34148)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC         (0x00A3414C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC___M  0x003FFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MISC___S                0

#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB  (0x00A34158)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB  (0x00A3415C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A3416C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34170)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS (0x00A34174)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34178)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A3417C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34180)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB (0x00A34184)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB (0x00A34188)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA    (0x00A3418C)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34190)
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB     (0x00A34194)
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB     (0x00A34198)
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_ID           (0x00A3419C)
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID___M    0x000000FF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_ID___S                  0

#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS       (0x00A341A0)
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_MISC         (0x00A341A4)
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC___M  0x003FFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_MISC___S                0

#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB  (0x00A341B0)
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB  (0x00A341B4)
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A341C4)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A341C8)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS (0x00A341CC)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A341D0)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A341D4)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A341D8)
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB (0x00A341DC)
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB (0x00A341E0)
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA    (0x00A341E4)
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET (0x00A341E8)
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB      (0x00A341EC)
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB      (0x00A341F0)
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_ID            (0x00A341F4)
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID___POR   0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID___M     0x000000FF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_ID___S                   0

#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS        (0x00A341F8)
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_MISC          (0x00A341FC)
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC___M   0x003FFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_MISC___S                 0

#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB   (0x00A34208)
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB   (0x00A3420C)
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A3421C)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34220)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS (0x00A34224)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34228)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A3422C)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34230)
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB (0x00A34234)
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB (0x00A34238)
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA     (0x00A3423C)
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34240)
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB      (0x00A34244)
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB      (0x00A34248)
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_ID            (0x00A3424C)
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID___POR   0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID___M     0x000000FF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_ID___S                   0

#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS        (0x00A34250)
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_MISC          (0x00A34254)
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC___M   0x003FFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_MISC___S                 0

#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB   (0x00A34260)
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB   (0x00A34264)
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A34274)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34278)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS (0x00A3427C)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34280)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A34284)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34288)
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB (0x00A3428C)
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB (0x00A34290)
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA     (0x00A34294)
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34298)
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB  (0x00A3429C)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB  (0x00A342A0)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID        (0x00A342A4)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___M 0x000000FF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS    (0x00A342A8)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC      (0x00A342AC)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___M 0x003FFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB (0x00A342B8)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB (0x00A342BC)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A342CC)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A342D0)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS (0x00A342D4)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A342D8)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A342DC)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A342E0)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB (0x00A342E4)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB (0x00A342E8)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA (0x00A342EC)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET (0x00A342F0)
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB     (0x00A343A4)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB     (0x00A343A8)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID           (0x00A343AC)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___M    0x0000FFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___S                  0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS       (0x00A343B0)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC         (0x00A343B4)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___M  0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___S                0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB  (0x00A343B8)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB  (0x00A343BC)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP (0x00A343C8)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS (0x00A343CC)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER (0x00A343D0)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB (0x00A343EC)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB (0x00A343F0)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA    (0x00A343F4)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET (0x00A343F8)
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB      (0x00A343FC)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB      (0x00A34400)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID            (0x00A34404)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID___POR   0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID___M     0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_ID___S                   0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS        (0x00A34408)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC          (0x00A3440C)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___M   0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___S                 0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB   (0x00A34410)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB   (0x00A34414)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP (0x00A34420)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS (0x00A34424)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34428)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB (0x00A34444)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB (0x00A34448)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA     (0x00A3444C)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET (0x00A34450)
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB      (0x00A34454)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB      (0x00A34458)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID            (0x00A3445C)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID___POR   0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID___M     0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_ID___S                   0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS        (0x00A34460)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC          (0x00A34464)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___M   0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___S                 0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB   (0x00A34468)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB   (0x00A3446C)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP (0x00A34478)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS (0x00A3447C)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34480)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB (0x00A3449C)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB (0x00A344A0)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA     (0x00A344A4)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET (0x00A344A8)
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB  (0x00A344AC)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB  (0x00A344B0)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID        (0x00A344B4)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS    (0x00A344B8)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC      (0x00A344BC)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB (0x00A344C0)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB (0x00A344C4)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP (0x00A344D0)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS (0x00A344D4)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER (0x00A344D8)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB (0x00A344F4)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB (0x00A344F8)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA (0x00A344FC)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET (0x00A34500)
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB    (0x00A345B4)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB    (0x00A345B8)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID          (0x00A345BC)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___M   0x0000FFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___S                 0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS      (0x00A345C0)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC        (0x00A345C4)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB (0x00A345C8)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB (0x00A345CC)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP (0x00A345D8)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS (0x00A345DC)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER (0x00A345E0)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB (0x00A345FC)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB (0x00A34600)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA   (0x00A34604)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET (0x00A34608)
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB    (0x00A3460C)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB    (0x00A34610)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID          (0x00A34614)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID___M   0x0000FFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_ID___S                 0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS      (0x00A34618)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC        (0x00A3461C)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB (0x00A34620)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB (0x00A34624)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP (0x00A34630)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS (0x00A34634)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34638)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB (0x00A34654)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB (0x00A34658)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA   (0x00A3465C)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET (0x00A34660)
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB     (0x00A34664)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB     (0x00A34668)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID           (0x00A3466C)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID___M    0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_ID___S                  0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS       (0x00A34670)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC         (0x00A34674)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___M  0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___S                0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB  (0x00A34678)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB  (0x00A3467C)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP (0x00A34688)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS (0x00A3468C)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34690)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB (0x00A346AC)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB (0x00A346B0)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA    (0x00A346B4)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET (0x00A346B8)
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB     (0x00A346BC)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB     (0x00A346C0)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID           (0x00A346C4)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID___POR  0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID___M    0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_ID___S                  0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS       (0x00A346C8)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC         (0x00A346CC)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___M  0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___S                0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB  (0x00A346D0)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB  (0x00A346D4)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP (0x00A346E0)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS (0x00A346E4)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER (0x00A346E8)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB (0x00A34704)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB (0x00A34708)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA    (0x00A3470C)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET (0x00A34710)
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB (0x00A34714)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB (0x00A34718)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID       (0x00A3471C)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS   (0x00A34720)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC     (0x00A34724)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB (0x00A34728)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB (0x00A3472C)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP (0x00A34738)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS (0x00A3473C)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34740)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB (0x00A3475C)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB (0x00A34760)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA (0x00A34764)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET (0x00A34768)
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB    (0x00A3481C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB    (0x00A34820)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID          (0x00A34824)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___M   0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___S                 0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS      (0x00A34828)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC        (0x00A3482C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB (0x00A34830)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB (0x00A34834)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB (0x00A34838)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB (0x00A3483C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP (0x00A34840)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS (0x00A34844)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34848)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A3484C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A34850)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS (0x00A34854)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A34858)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A3485C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A34860)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB (0x00A34864)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB (0x00A34868)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA   (0x00A3486C)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET (0x00A34870)
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB   (0x00A34874)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB   (0x00A34878)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID         (0x00A3487C)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___M  0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___S                0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS     (0x00A34880)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC       (0x00A34884)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB (0x00A34888)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB (0x00A3488C)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB (0x00A34890)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB (0x00A34894)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP (0x00A34898)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS (0x00A3489C)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER (0x00A348A0)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A348A4)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A348A8)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS (0x00A348AC)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A348B0)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A348B4)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A348B8)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB (0x00A348BC)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB (0x00A348C0)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA  (0x00A348C4)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET (0x00A348C8)
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB  (0x00A348CC)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB  (0x00A348D0)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID        (0x00A348D4)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS    (0x00A348D8)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC      (0x00A348DC)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB (0x00A348E0)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB (0x00A348E4)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP (0x00A348F0)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS (0x00A348F4)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A348F8)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB (0x00A34914)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB (0x00A34918)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA (0x00A3491C)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34920)
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB (0x00A34924)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB (0x00A34928)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID       (0x00A3492C)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS   (0x00A34930)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC     (0x00A34934)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB (0x00A34938)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB (0x00A3493C)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34948)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS (0x00A3494C)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34950)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB (0x00A3496C)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB (0x00A34970)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA (0x00A34974)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34978)
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB (0x00A3497C)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB (0x00A34980)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID       (0x00A34984)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS   (0x00A34988)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC     (0x00A3498C)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB (0x00A34990)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB (0x00A34994)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP (0x00A349A0)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS (0x00A349A4)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A349A8)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB (0x00A349C4)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB (0x00A349C8)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA (0x00A349CC)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET (0x00A349D0)
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB (0x00A349D4)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB (0x00A349D8)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID       (0x00A349DC)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS   (0x00A349E0)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC     (0x00A349E4)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB (0x00A349E8)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB (0x00A349EC)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP (0x00A349F8)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS (0x00A349FC)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34A00)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB (0x00A34A1C)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB (0x00A34A20)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA (0x00A34A24)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34A28)
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB (0x00A34A2C)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB (0x00A34A30)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID       (0x00A34A34)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS   (0x00A34A38)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC     (0x00A34A3C)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB (0x00A34A40)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB (0x00A34A44)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34A50)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS (0x00A34A54)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34A58)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB (0x00A34A74)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB (0x00A34A78)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA (0x00A34A7C)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34A80)
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB (0x00A34A84)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB (0x00A34A88)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID       (0x00A34A8C)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS   (0x00A34A90)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC     (0x00A34A94)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB (0x00A34A98)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB (0x00A34A9C)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34AA8)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS (0x00A34AAC)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34AB0)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB (0x00A34ACC)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB (0x00A34AD0)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA (0x00A34AD4)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34AD8)
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_WBM_R1_END_OF_TEST_CHECK             (0x00A36000)
#define   UMAC_WBM_R1_END_OF_TEST_CHECK___RWC       QCSR_REG_RW    
#define   UMAC_WBM_R1_END_OF_TEST_CHECK___POR    0x00000000
#define   UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_WBM_R1_END_OF_TEST_CHECK___M      0x00000001   
#define   UMAC_WBM_R1_END_OF_TEST_CHECK___S                    0

#define UMAC_WBM_R1_TESTBUS_CTRL                  (0x00A36004)
#define   UMAC_WBM_R1_TESTBUS_CTRL___RWC            QCSR_REG_RW    
#define   UMAC_WBM_R1_TESTBUS_CTRL___POR         0x00000000
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___POR 0x00
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___POR 0x00
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___M 0x00001F00
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___S               8
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___M 0x0000003F
#define   UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___S               0
#define   UMAC_WBM_R1_TESTBUS_CTRL___M           0x00001F3F   
#define   UMAC_WBM_R1_TESTBUS_CTRL___S                         0

#define UMAC_WBM_R1_TESTBUS_LOWER                 (0x00A36008)
#define   UMAC_WBM_R1_TESTBUS_LOWER___RWC           QCSR_REG_RO    
#define   UMAC_WBM_R1_TESTBUS_LOWER___POR        0x00000000
#define   UMAC_WBM_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_WBM_R1_TESTBUS_LOWER__VALUE___M   0xFFFFFFFF
#define   UMAC_WBM_R1_TESTBUS_LOWER__VALUE___S                 0
#define   UMAC_WBM_R1_TESTBUS_LOWER___M          0xFFFFFFFF   
#define   UMAC_WBM_R1_TESTBUS_LOWER___S                        0

#define UMAC_WBM_R1_TESTBUS_HIGHER                (0x00A3600C)
#define   UMAC_WBM_R1_TESTBUS_HIGHER___RWC          QCSR_REG_RO    
#define   UMAC_WBM_R1_TESTBUS_HIGHER___POR       0x00000000
#define   UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___POR 0x00
#define   UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___M  0x000000FF
#define   UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___S                0
#define   UMAC_WBM_R1_TESTBUS_HIGHER___M         0x000000FF   
#define   UMAC_WBM_R1_TESTBUS_HIGHER___S                       0

#define UMAC_WBM_R1_SM_STATES_IX_0                (0x00A36010)
#define   UMAC_WBM_R1_SM_STATES_IX_0___RWC          QCSR_REG_RO    
#define   UMAC_WBM_R1_SM_STATES_IX_0___POR       0x00000000
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___M 0x60000000
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___S              29
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___M 0x18000000
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___S              27
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___M 0x06000000
#define   UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___S              25
#define   UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___M 0x01800000
#define   UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___S              23
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___M 0x00600000
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___S              21
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___M 0x00180000
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___S              19
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___M 0x00060000
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___S              17
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___M 0x00018000
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___S              15
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___M 0x00007000
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___S              12
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___M 0x00000C00
#define   UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___S              10
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___M 0x00000380
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___S               7
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___M 0x00000060
#define   UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___S               5
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___M 0x0000001C
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___S               2
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___M 0x00000003
#define   UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___S               0
#define   UMAC_WBM_R1_SM_STATES_IX_0___M         0x7FFFFFFF   
#define   UMAC_WBM_R1_SM_STATES_IX_0___S                       0

#define UMAC_WBM_R1_SM_STATES_IX_1                (0x00A36014)
#define   UMAC_WBM_R1_SM_STATES_IX_1___RWC          QCSR_REG_RO    
#define   UMAC_WBM_R1_SM_STATES_IX_1___POR       0x00000000
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___POR 0x0
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___M 0xC0000000
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___S              30
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___M 0x20000000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___S              29
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___M 0x10000000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___S              28
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___M 0x0E000000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___S              25
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___M 0x01C00000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___S              22
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___M 0x00380000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___S              19
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___M 0x00070000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___S              16
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___M 0x0000E000
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___S              13
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___M 0x00001C00
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___S              10
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___M 0x00000380
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___S               7
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___M 0x00000070
#define   UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___S               4
#define   UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___M 0x0000000C
#define   UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___S               2
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___M 0x00000003
#define   UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___S               0
#define   UMAC_WBM_R1_SM_STATES_IX_1___M         0xFFFFFFFF   
#define   UMAC_WBM_R1_SM_STATES_IX_1___S                       0

#define UMAC_WBM_R1_EVENTMASK_IX_0                (0x00A36018)
#define   UMAC_WBM_R1_EVENTMASK_IX_0___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R1_EVENTMASK_IX_0___POR       0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_0__MASK___M   0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_0__MASK___S                 0
#define   UMAC_WBM_R1_EVENTMASK_IX_0___M         0xFFFFFFFF   
#define   UMAC_WBM_R1_EVENTMASK_IX_0___S                       0

#define UMAC_WBM_R1_EVENTMASK_IX_1                (0x00A3601C)
#define   UMAC_WBM_R1_EVENTMASK_IX_1___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R1_EVENTMASK_IX_1___POR       0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_1__MASK___M   0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_1__MASK___S                 0
#define   UMAC_WBM_R1_EVENTMASK_IX_1___M         0xFFFFFFFF   
#define   UMAC_WBM_R1_EVENTMASK_IX_1___S                       0

#define UMAC_WBM_R1_EVENTMASK_IX_2                (0x00A36020)
#define   UMAC_WBM_R1_EVENTMASK_IX_2___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R1_EVENTMASK_IX_2___POR       0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_2__MASK___M   0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_2__MASK___S                 0
#define   UMAC_WBM_R1_EVENTMASK_IX_2___M         0xFFFFFFFF   
#define   UMAC_WBM_R1_EVENTMASK_IX_2___S                       0

#define UMAC_WBM_R1_EVENTMASK_IX_3                (0x00A36024)
#define   UMAC_WBM_R1_EVENTMASK_IX_3___RWC          QCSR_REG_RW    
#define   UMAC_WBM_R1_EVENTMASK_IX_3___POR       0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_3__MASK___M   0xFFFFFFFF
#define   UMAC_WBM_R1_EVENTMASK_IX_3__MASK___S                 0
#define   UMAC_WBM_R1_EVENTMASK_IX_3___M         0xFFFFFFFF   
#define   UMAC_WBM_R1_EVENTMASK_IX_3___S                       0

#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL     (0x00A36028)
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define UMAC_WBM_R2_PPE_RELEASE_RING_HP           (0x00A37000)
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_PPE_RELEASE_RING_HP___S                  0

#define UMAC_WBM_R2_PPE_RELEASE_RING_TP           (0x00A37004)
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_PPE_RELEASE_RING_TP___S                  0

#define UMAC_WBM_R2_TQM_RELEASE_RING_HP           (0x00A37008)
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_TQM_RELEASE_RING_HP___S                  0

#define UMAC_WBM_R2_TQM_RELEASE_RING_TP           (0x00A3700C)
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_TQM_RELEASE_RING_TP___S                  0

#define UMAC_WBM_R2_REO_RELEASE_RING_HP           (0x00A37010)
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_REO_RELEASE_RING_HP___S                  0

#define UMAC_WBM_R2_REO_RELEASE_RING_TP           (0x00A37014)
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_REO_RELEASE_RING_TP___S                  0

#define UMAC_WBM_R2_SW_RELEASE_RING_HP            (0x00A37018)
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP___POR   0x00000000
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP___M     0x0000FFFF   
#define   UMAC_WBM_R2_SW_RELEASE_RING_HP___S                   0

#define UMAC_WBM_R2_SW_RELEASE_RING_TP            (0x00A3701C)
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP___POR   0x00000000
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP___M     0x0000FFFF   
#define   UMAC_WBM_R2_SW_RELEASE_RING_TP___S                   0

#define UMAC_WBM_R2_FW_RELEASE_RING_HP            (0x00A37020)
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP___POR   0x00000000
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP___M     0x0000FFFF   
#define   UMAC_WBM_R2_FW_RELEASE_RING_HP___S                   0

#define UMAC_WBM_R2_FW_RELEASE_RING_TP            (0x00A37024)
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP___POR   0x00000000
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP___M     0x0000FFFF   
#define   UMAC_WBM_R2_FW_RELEASE_RING_TP___S                   0

#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP        (0x00A37028)
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___M 0x0000FFFF   
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP        (0x00A3702C)
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___M 0x0000FFFF   
#define   UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP           (0x00A37040)
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___S                  0

#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP           (0x00A37044)
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___S                  0

#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP            (0x00A37048)
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP___POR   0x00000000
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP___M     0x0000FFFF   
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_HP___S                   0

#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP            (0x00A3704C)
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP___POR   0x00000000
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP___M     0x0000FFFF   
#define   UMAC_WBM_R2_WBM2SW_BUF_RING_TP___S                   0

#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP            (0x00A37050)
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP___POR   0x00000000
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP___M     0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_HP___S                   0

#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP            (0x00A37054)
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP___POR   0x00000000
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP___M     0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_BUF_RING_TP___S                   0

#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP        (0x00A37058)
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___S               0

#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP        (0x00A3705C)
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___S               0

#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP          (0x00A37070)
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___S                 0

#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP          (0x00A37074)
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___S                 0

#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP          (0x00A37078)
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_HP___S                 0

#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP          (0x00A3707C)
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM2REO_LINK_RING_TP___S                 0

#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP           (0x00A37080)
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_HP___S                  0

#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP           (0x00A37084)
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2SW_LINK_RING_TP___S                  0

#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP           (0x00A37088)
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_HP___S                  0

#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP           (0x00A3708C)
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP___POR  0x00000000
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP___M    0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_LINK_RING_TP___S                  0

#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP       (0x00A37090)
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___S               0

#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP       (0x00A37094)
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___S               0

#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP          (0x00A370A8)
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___S                 0

#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP          (0x00A370AC)
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___RWC    QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___M   0x0000FFFF   
#define   UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___S                 0

#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP         (0x00A370B0)
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___M  0x0000FFFF   
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___S                0

#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP         (0x00A370B4)
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___RWC   QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___M  0x0000FFFF   
#define   UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___S                0

#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP        (0x00A370B8)
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP        (0x00A370BC)
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___RWC  QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___M 0x0000FFFF   
#define   UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP       (0x00A370C0)
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP       (0x00A370C4)
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP       (0x00A370C8)
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP       (0x00A370CC)
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP       (0x00A370D0)
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP       (0x00A370D4)
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP       (0x00A370D8)
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP       (0x00A370DC)
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___S               0

#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP       (0x00A370E0)
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___S               0

#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP       (0x00A370E4)
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___POR 0x00000000
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___M 0x000FFFFF   
#define   UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___S               0

#define UMAC_REO_R0_GENERAL_ENABLE                (0x00A38000)
#define   UMAC_REO_R0_GENERAL_ENABLE___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_GENERAL_ENABLE___POR       0x03000150
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___POR 0x6
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___POR 0x1
#define   UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___POR 0x5
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___POR 0x0
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___M 0x80000000
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___S              31
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___M 0x40000000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___S              30
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___M 0x20000000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___S              29
#define   UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___M 0x10000000
#define   UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___S              28
#define   UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___M 0x08000000
#define   UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___S              27
#define   UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___M 0x07800000
#define   UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___S              23
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___M 0x00400000
#define   UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___S              22
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___M 0x00200000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___S              21
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___M 0x00100000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___S              20
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___M 0x00080000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___S              19
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___M 0x00040000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___S              18
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___M 0x00020000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___S              17
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___M 0x00010000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___S              16
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___M 0x00008000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___S              15
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___M 0x00004000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___S              14
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___M 0x00002000
#define   UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___S              13
#define   UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___M 0x00001000
#define   UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___S              12
#define   UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___M 0x00000E00
#define   UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___S               9
#define   UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___M 0x00000100
#define   UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___S               8
#define   UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___M 0x000000F0
#define   UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___S               4
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___M 0x00000008
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___S               3
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___M 0x00000004
#define   UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___S               2
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___M 0x00000002
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___S               1
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___M 0x00000001
#define   UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___S               0
#define   UMAC_REO_R0_GENERAL_ENABLE___M         0xFFFFFFFF   
#define   UMAC_REO_R0_GENERAL_ENABLE___S                       0

#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0    (0x00A38004)
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___POR 0x76543210
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___POR 0x7
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___POR 0x5
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___POR 0x4
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___POR 0x3
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___POR 0x2
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___POR 0x1
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___POR 0x0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___S              28
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___S              24
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___S              20
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___S              16
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___S              12
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___S               8
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___S               4
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___S               0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___S               0

#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1    (0x00A38008)
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___S              28
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___S              24
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___S              20
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___S              16
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___S              12
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___S               8
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___S               4
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___S               0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___S               0

#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2    (0x00A3800C)
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___S              28
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___S              24
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___S              20
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___S              16
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___S              12
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___S               8
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___S               4
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___S               0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___S               0

#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3    (0x00A38010)
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___S              28
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___S              24
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___S              20
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___S              16
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___S              12
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___S               8
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___S               4
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___S               0
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___S               0

#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 (0x00A38014)
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___POR 0x76543210
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___POR 0x7
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___POR 0x5
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___POR 0x4
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___POR 0x3
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___POR 0x2
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___POR 0x1
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___POR 0x0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___S              28
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___S              24
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___S              20
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___S              16
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___S              12
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___S               8
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___S               4
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___S               0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___S               0

#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 (0x00A38018)
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___S              28
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___S              24
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___S              20
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___S              16
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___S              12
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___S               8
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___S               4
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___S               0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___S               0

#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 (0x00A3801C)
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___S              28
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___S              24
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___S              20
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___S              16
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___S              12
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___S               8
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___S               4
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___S               0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___S               0

#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 (0x00A38020)
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___POR 0x66666666
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___POR 0x6
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___M 0xF0000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___S              28
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___M 0x0F000000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___S              24
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___M 0x00F00000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___S              20
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___M 0x000F0000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___S              16
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___M 0x0000F000
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___S              12
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___M 0x00000F00
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___S               8
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___M 0x000000F0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___S               4
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___M 0x0000000F
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___S               0
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___M 0xFFFFFFFF   
#define   UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___S               0

#define UMAC_REO_R0_TIMESTAMP                     (0x00A38024)
#define   UMAC_REO_R0_TIMESTAMP___RWC               QCSR_REG_RW    
#define   UMAC_REO_R0_TIMESTAMP___POR            0x00000000
#define   UMAC_REO_R0_TIMESTAMP__TIMESTAMP___POR 0x00000000
#define   UMAC_REO_R0_TIMESTAMP__TIMESTAMP___M   0xFFFFFFFF
#define   UMAC_REO_R0_TIMESTAMP__TIMESTAMP___S                 0
#define   UMAC_REO_R0_TIMESTAMP___M              0xFFFFFFFF   
#define   UMAC_REO_R0_TIMESTAMP___S                            0

#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 (0x00A38028)
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___POR 0x55555555
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___M 0xF0000000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___S              28
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___M 0x0F000000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___S              24
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___M 0x00F00000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___S              20
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___M 0x000F0000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___S              16
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___M 0x0000F000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___S              12
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___M 0x00000F00
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___S               8
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___M 0x000000F0
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___S               4
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___M 0x0000000F
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___S               0
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___S               0

#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 (0x00A3802C)
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___POR 0x55555555
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___POR 0x5
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___M 0xF0000000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___S              28
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___M 0x0F000000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___S              24
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___M 0x00F00000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___S              20
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___M 0x000F0000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___S              16
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___M 0x0000F000
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___S              12
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___M 0x00000F00
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___S               8
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___M 0x000000F0
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___S               4
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___M 0x0000000F
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___S               0
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___S               0

#define UMAC_REO_R0_IDLE_REQ_CTRL                 (0x00A38030)
#define   UMAC_REO_R0_IDLE_REQ_CTRL___RWC           QCSR_REG_RW    
#define   UMAC_REO_R0_IDLE_REQ_CTRL___POR        0x00000003
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___POR 0x1
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___POR 0x1
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___M 0x00000002
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___S               1
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___M 0x00000001
#define   UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___S               0
#define   UMAC_REO_R0_IDLE_REQ_CTRL___M          0x00000003   
#define   UMAC_REO_R0_IDLE_REQ_CTRL___S                        0

#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB      (0x00A38034)
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB      (0x00A38038)
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_ID            (0x00A3803C)
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID___POR   0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID___M     0x000000FF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_ID___S                   0

#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS        (0x00A38040)
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_STATUS___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_MISC          (0x00A38044)
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC___POR 0x00000080
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC___M   0x003FFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_MISC___S                 0

#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB   (0x00A38050)
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB   (0x00A38054)
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 (0x00A38064)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 (0x00A38068)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS (0x00A3806C)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER (0x00A38070)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER (0x00A38074)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS (0x00A38078)
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB (0x00A3807C)
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB (0x00A38080)
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA     (0x00A38084)
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET (0x00A38088)
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB    (0x00A3808C)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB    (0x00A38090)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_ID          (0x00A38094)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID___M   0x000000FF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_ID___S                 0

#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS      (0x00A38098)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC        (0x00A3809C)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC___POR 0x00000080
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC___M 0x003FFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MISC___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB (0x00A380A8)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB (0x00A380AC)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A380BC)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A380C0)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS (0x00A380C4)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A380C8)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A380CC)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A380D0)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB (0x00A380D4)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB (0x00A380D8)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA   (0x00A380DC)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET (0x00A380E0)
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB         (0x00A380E4)
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB         (0x00A380E8)
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO_CMD_RING_ID               (0x00A380EC)
#define   UMAC_REO_R0_REO_CMD_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_ID___M        0x000000FF   
#define   UMAC_REO_R0_REO_CMD_RING_ID___S                      0

#define UMAC_REO_R0_REO_CMD_RING_STATUS           (0x00A380F0)
#define   UMAC_REO_R0_REO_CMD_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO_CMD_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO_CMD_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_STATUS___S                  0

#define UMAC_REO_R0_REO_CMD_RING_MISC             (0x00A380F4)
#define   UMAC_REO_R0_REO_CMD_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_MISC___M      0x003FFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_MISC___S                    0

#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB      (0x00A38100)
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB      (0x00A38104)
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 (0x00A38114)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 (0x00A38118)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS (0x00A3811C)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER (0x00A38120)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER (0x00A38124)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS (0x00A38128)
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB    (0x00A3812C)
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB    (0x00A38130)
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA        (0x00A38134)
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET  (0x00A38138)
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_SW2REO_RING_BASE_LSB          (0x00A3813C)
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_BASE_LSB___S                 0

#define UMAC_REO_R0_SW2REO_RING_BASE_MSB          (0x00A38140)
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB___M   0x00FFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_BASE_MSB___S                 0

#define UMAC_REO_R0_SW2REO_RING_ID                (0x00A38144)
#define   UMAC_REO_R0_SW2REO_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_ID___POR       0x00000000
#define   UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_SW2REO_RING_ID___M         0x000000FF   
#define   UMAC_REO_R0_SW2REO_RING_ID___S                       0

#define UMAC_REO_R0_SW2REO_RING_STATUS            (0x00A38148)
#define   UMAC_REO_R0_SW2REO_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO_RING_STATUS___POR   0x00000000
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_SW2REO_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_STATUS___S                   0

#define UMAC_REO_R0_SW2REO_RING_MISC              (0x00A3814C)
#define   UMAC_REO_R0_SW2REO_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_MISC___POR     0x00000080
#define   UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_SW2REO_RING_MISC___M       0x003FFFFF   
#define   UMAC_REO_R0_SW2REO_RING_MISC___S                     0

#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB       (0x00A38158)
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___S               0

#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB       (0x00A3815C)
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 (0x00A3816C)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 (0x00A38170)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS (0x00A38174)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER (0x00A38178)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER (0x00A3817C)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS (0x00A38180)
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB     (0x00A38184)
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB     (0x00A38188)
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA         (0x00A3818C)
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO_RING_MSI1_DATA___S                0

#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET   (0x00A38190)
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB         (0x00A38194)
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_BASE_LSB___S                0

#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB         (0x00A38198)
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_BASE_MSB___S                0

#define UMAC_REO_R0_SW2REO1_RING_ID               (0x00A3819C)
#define   UMAC_REO_R0_SW2REO1_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_ID___M        0x000000FF   
#define   UMAC_REO_R0_SW2REO1_RING_ID___S                      0

#define UMAC_REO_R0_SW2REO1_RING_STATUS           (0x00A381A0)
#define   UMAC_REO_R0_SW2REO1_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO1_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_SW2REO1_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_STATUS___S                  0

#define UMAC_REO_R0_SW2REO1_RING_MISC             (0x00A381A4)
#define   UMAC_REO_R0_SW2REO1_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_MISC___M      0x003FFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_MISC___S                    0

#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB      (0x00A381B0)
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___S               0

#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB      (0x00A381B4)
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 (0x00A381C4)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 (0x00A381C8)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS (0x00A381CC)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER (0x00A381D0)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER (0x00A381D4)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS (0x00A381D8)
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB    (0x00A381DC)
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB    (0x00A381E0)
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA        (0x00A381E4)
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET  (0x00A381E8)
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB         (0x00A381EC)
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB         (0x00A381F0)
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW1_RING_ID               (0x00A381F4)
#define   UMAC_REO_R0_REO2SW1_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW1_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW1_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW1_RING_STATUS           (0x00A381F8)
#define   UMAC_REO_R0_REO2SW1_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW1_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW1_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW1_RING_MISC             (0x00A381FC)
#define   UMAC_REO_R0_REO2SW1_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW1_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB      (0x00A38200)
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB      (0x00A38204)
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP (0x00A38210)
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS (0x00A38214)
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER (0x00A38218)
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB    (0x00A38234)
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB    (0x00A38238)
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA        (0x00A3823C)
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET  (0x00A38240)
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB         (0x00A38244)
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB         (0x00A38248)
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW2_RING_ID               (0x00A3824C)
#define   UMAC_REO_R0_REO2SW2_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW2_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW2_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW2_RING_STATUS           (0x00A38250)
#define   UMAC_REO_R0_REO2SW2_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW2_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW2_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW2_RING_MISC             (0x00A38254)
#define   UMAC_REO_R0_REO2SW2_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW2_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB      (0x00A38258)
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB      (0x00A3825C)
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP (0x00A38268)
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS (0x00A3826C)
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER (0x00A38270)
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB    (0x00A3828C)
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB    (0x00A38290)
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA        (0x00A38294)
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET  (0x00A38298)
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB         (0x00A3829C)
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB         (0x00A382A0)
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW3_RING_ID               (0x00A382A4)
#define   UMAC_REO_R0_REO2SW3_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW3_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW3_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW3_RING_STATUS           (0x00A382A8)
#define   UMAC_REO_R0_REO2SW3_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW3_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW3_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW3_RING_MISC             (0x00A382AC)
#define   UMAC_REO_R0_REO2SW3_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW3_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB      (0x00A382B0)
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB      (0x00A382B4)
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP (0x00A382C0)
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS (0x00A382C4)
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER (0x00A382C8)
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB    (0x00A382E4)
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB    (0x00A382E8)
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA        (0x00A382EC)
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET  (0x00A382F0)
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB         (0x00A382F4)
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB         (0x00A382F8)
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW4_RING_ID               (0x00A382FC)
#define   UMAC_REO_R0_REO2SW4_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW4_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW4_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW4_RING_STATUS           (0x00A38300)
#define   UMAC_REO_R0_REO2SW4_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW4_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW4_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW4_RING_MISC             (0x00A38304)
#define   UMAC_REO_R0_REO2SW4_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW4_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB      (0x00A38308)
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB      (0x00A3830C)
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP (0x00A38318)
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS (0x00A3831C)
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER (0x00A38320)
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB    (0x00A3833C)
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB    (0x00A38340)
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA        (0x00A38344)
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET  (0x00A38348)
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB         (0x00A3834C)
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB         (0x00A38350)
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW5_RING_ID               (0x00A38354)
#define   UMAC_REO_R0_REO2SW5_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW5_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW5_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW5_RING_STATUS           (0x00A38358)
#define   UMAC_REO_R0_REO2SW5_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW5_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW5_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW5_RING_MISC             (0x00A3835C)
#define   UMAC_REO_R0_REO2SW5_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW5_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB      (0x00A38360)
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB      (0x00A38364)
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP (0x00A38370)
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS (0x00A38374)
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER (0x00A38378)
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB    (0x00A38394)
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB    (0x00A38398)
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA        (0x00A3839C)
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET  (0x00A383A0)
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB         (0x00A383A4)
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB         (0x00A383A8)
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2SW6_RING_ID               (0x00A383AC)
#define   UMAC_REO_R0_REO2SW6_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2SW6_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2SW6_RING_ID___S                      0

#define UMAC_REO_R0_REO2SW6_RING_STATUS           (0x00A383B0)
#define   UMAC_REO_R0_REO2SW6_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW6_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2SW6_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2SW6_RING_MISC             (0x00A383B4)
#define   UMAC_REO_R0_REO2SW6_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2SW6_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_MISC___S                    0

#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB      (0x00A383B8)
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB      (0x00A383BC)
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP (0x00A383C8)
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS (0x00A383CC)
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER (0x00A383D0)
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB    (0x00A383EC)
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB    (0x00A383F0)
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA        (0x00A383F4)
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET  (0x00A383F8)
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB         (0x00A383FC)
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_BASE_LSB___S                0

#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB         (0x00A38400)
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_BASE_MSB___S                0

#define UMAC_REO_R0_REO2TCL_RING_ID               (0x00A38404)
#define   UMAC_REO_R0_REO2TCL_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_ID___POR      0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2TCL_RING_ID___M        0x0000FFFF   
#define   UMAC_REO_R0_REO2TCL_RING_ID___S                      0

#define UMAC_REO_R0_REO2TCL_RING_STATUS           (0x00A38408)
#define   UMAC_REO_R0_REO2TCL_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_REO2TCL_RING_STATUS___POR  0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2TCL_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_STATUS___S                  0

#define UMAC_REO_R0_REO2TCL_RING_MISC             (0x00A3840C)
#define   UMAC_REO_R0_REO2TCL_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_MISC___POR    0x00000080
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2TCL_RING_MISC___M      0x03FFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_MISC___S                    0

#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB      (0x00A38410)
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB      (0x00A38414)
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP (0x00A38420)
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS (0x00A38424)
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER (0x00A38428)
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB    (0x00A38444)
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB    (0x00A38448)
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA        (0x00A3844C)
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET  (0x00A38450)
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO2FW_RING_BASE_LSB          (0x00A38454)
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_BASE_LSB___S                 0

#define UMAC_REO_R0_REO2FW_RING_BASE_MSB          (0x00A38458)
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB___M   0x0FFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_BASE_MSB___S                 0

#define UMAC_REO_R0_REO2FW_RING_ID                (0x00A3845C)
#define   UMAC_REO_R0_REO2FW_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_ID___POR       0x00000000
#define   UMAC_REO_R0_REO2FW_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO2FW_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO2FW_RING_ID___M         0x0000FFFF   
#define   UMAC_REO_R0_REO2FW_RING_ID___S                       0

#define UMAC_REO_R0_REO2FW_RING_STATUS            (0x00A38460)
#define   UMAC_REO_R0_REO2FW_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_REO_R0_REO2FW_RING_STATUS___POR   0x00000000
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO2FW_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_STATUS___S                   0

#define UMAC_REO_R0_REO2FW_RING_MISC              (0x00A38464)
#define   UMAC_REO_R0_REO2FW_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_MISC___POR     0x00000080
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO2FW_RING_MISC___M       0x03FFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_MISC___S                     0

#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB       (0x00A38468)
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB       (0x00A3846C)
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP (0x00A38478)
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS (0x00A3847C)
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER (0x00A38480)
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB     (0x00A3849C)
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB     (0x00A384A0)
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA         (0x00A384A4)
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_REO_R0_REO2FW_RING_MSI1_DATA___S                0

#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET   (0x00A384A8)
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB     (0x00A384AC)
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB     (0x00A384B0)
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_ID           (0x00A384B4)
#define   UMAC_REO_R0_REO_RELEASE_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_ID___POR  0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_ID___M    0x0000FFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_ID___S                  0

#define UMAC_REO_R0_REO_RELEASE_RING_STATUS       (0x00A384B8)
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_STATUS___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_MISC         (0x00A384BC)
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC___M  0x03FFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_MISC___S                0

#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB  (0x00A384C0)
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB  (0x00A384C4)
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP (0x00A384D0)
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS (0x00A384D4)
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A384D8)
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB (0x00A384F4)
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB (0x00A384F8)
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA    (0x00A384FC)
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET (0x00A38500)
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB      (0x00A38504)
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB      (0x00A38508)
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_ID            (0x00A3850C)
#define   UMAC_REO_R0_REO_STATUS_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_ID___POR   0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___S               8
#define   UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_ID___M     0x0000FFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_ID___S                   0

#define UMAC_REO_R0_REO_STATUS_RING_STATUS        (0x00A38510)
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_STATUS___S               0

#define UMAC_REO_R0_REO_STATUS_RING_MISC          (0x00A38514)
#define   UMAC_REO_R0_REO_STATUS_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_MISC___POR 0x00000080
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___S              22
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_MISC___M   0x03FFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_MISC___S                 0

#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB   (0x00A38518)
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB   (0x00A3851C)
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP (0x00A38528)
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS (0x00A3852C)
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER (0x00A38530)
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB (0x00A3854C)
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB (0x00A38550)
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___S               0

#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA     (0x00A38554)
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___S               0

#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET (0x00A38558)
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_REO_R0_WATCHDOG_TIMEOUT              (0x00A3855C)
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT___RWC        QCSR_REG_RW    
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT___POR     0x00000000
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___POR 0x0
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___POR 0x000
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___M 0x00003000
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___S              12
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___M 0x00000FFF
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___S               0
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT___M       0x00003FFF   
#define   UMAC_REO_R0_WATCHDOG_TIMEOUT___S                     0

#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0   (0x00A38560)
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___POR 0x00000000
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___POR 0x00000000
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___M 0xFFFFFFFF
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___S               0
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___S               0

#define UMAC_REO_R0_AGING_THRESHOLD_IX_0          (0x00A38564)
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0___POR 0x000186A0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___POR 0x000186A0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___S               0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_0___S                 0

#define UMAC_REO_R0_AGING_THRESHOLD_IX_1          (0x00A38568)
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1___POR 0x000186A0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___POR 0x000186A0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___S               0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_1___S                 0

#define UMAC_REO_R0_AGING_THRESHOLD_IX_2          (0x00A3856C)
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2___POR 0x00009C40
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___POR 0x00009C40
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___S               0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_2___S                 0

#define UMAC_REO_R0_AGING_THRESHOLD_IX_3          (0x00A38570)
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3___POR 0x00009C40
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___POR 0x00009C40
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___S               0
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_THRESHOLD_IX_3___S                 0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0    (0x00A38574)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0    (0x00A38578)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0    (0x00A3857C)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0    (0x00A38580)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1    (0x00A38584)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1    (0x00A38588)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1    (0x00A3858C)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1    (0x00A38590)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2    (0x00A38594)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2    (0x00A38598)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2    (0x00A3859C)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2    (0x00A385A0)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3    (0x00A385A4)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___S               0

#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3    (0x00A385A8)
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3    (0x00A385AC)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___M 0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___S               0

#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3    (0x00A385B0)
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___POR 0x00
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___S               0
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___M 0x000000FF   
#define   UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___S               0

#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0         (0x00A385B4)
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___POR 0x0000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___M 0x0000FFFF
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___S               0
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___M  0x0000FFFF   
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___S                0

#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1         (0x00A385B8)
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___POR 0x0000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___M 0x0000FFFF
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___S               0
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___M  0x0000FFFF   
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___S                0

#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2         (0x00A385BC)
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___POR 0x0000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___M 0x0000FFFF
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___S               0
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___M  0x0000FFFF   
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___S                0

#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3         (0x00A385C0)
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___POR 0x0000
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___M 0x0000FFFF
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___S               0
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___M  0x0000FFFF   
#define   UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___S                0

#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0          (0x00A385C4)
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___S               0
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_0___S                 0

#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1          (0x00A385C8)
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___S               0
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_1___S                 0

#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2          (0x00A385CC)
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___S               0
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_2___S                 0

#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3          (0x00A385D0)
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___POR 0x00000000
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___M 0xFFFFFFFF
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___S               0
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AGING_TIMESTAMP_IX_3___S                 0

#define UMAC_REO_R0_AGING_CONTROL                 (0x00A385D4)
#define   UMAC_REO_R0_AGING_CONTROL___RWC           QCSR_REG_RW    
#define   UMAC_REO_R0_AGING_CONTROL___POR        0x00000000
#define   UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___POR 0x00
#define   UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___M 0x0000001F
#define   UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___S               0
#define   UMAC_REO_R0_AGING_CONTROL___M          0x0000001F   
#define   UMAC_REO_R0_AGING_CONTROL___S                        0

#define UMAC_REO_R0_MISC_CTL                      (0x00A385D8)
#define   UMAC_REO_R0_MISC_CTL___RWC                QCSR_REG_RW    
#define   UMAC_REO_R0_MISC_CTL___POR             0x000C0000
#define   UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___POR 0x6
#define   UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___POR 0x0
#define   UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___POR 0x0
#define   UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___POR 0x0000
#define   UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___M 0x001E0000
#define   UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___S              17
#define   UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___M 0x00010000
#define   UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___S              16
#define   UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___M 0x00008000
#define   UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___S              15
#define   UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___M 0x00007FFF
#define   UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___S               0
#define   UMAC_REO_R0_MISC_CTL___M               0x001FFFFF   
#define   UMAC_REO_R0_MISC_CTL___S                             0

#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD         (0x00A385DC)
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___POR 0xFFFFFFFF
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___POR 0xFFFFFFFF
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___M 0xFFFFFFFF
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___S               0
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___M  0xFFFFFFFF   
#define   UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___S                0

#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0          (0x00A385E0)
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___M 0xFFFFFFFF
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___S               0
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_0___S                 0

#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1          (0x00A385E4)
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___M 0xFFFFFFFF
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___S               0
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_1___S                 0

#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2          (0x00A385E8)
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___M 0xFFFFFFFF
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___S               0
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_2___S                 0

#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3          (0x00A385EC)
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3___RWC    QCSR_REG_RO    
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___POR 0x00000000
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___M 0xFFFFFFFF
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___S               0
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3___M   0xFFFFFFFF   
#define   UMAC_REO_R0_AC_BUFFERS_USED_IX_3___S                 0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 (0x00A385F0)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___POR 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___POR 0xFFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 (0x00A385F4)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___POR 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___POR 0xFFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 (0x00A385F8)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___POR 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___POR 0xFFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL (0x00A385FC)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___POR 0x03FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___POR 0x3FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___M 0x03FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___M 0x03FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0   (0x00A38600)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___POR 0x00000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___POR 0x000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1   (0x00A38604)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___POR 0x00000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___POR 0x000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2   (0x00A38608)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___POR 0x00000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___POR 0x000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___M 0x00FFFFFF
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___M 0x00FFFFFF   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___S               0

#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL   (0x00A3860C)
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___POR 0x00000000
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___POR 0x0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___M 0x00000001
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___S               0
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___M 0x00000001   
#define   UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 (0x00A38610)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 (0x00A38614)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___POR 0x00
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___M 0x000000FF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 (0x00A38618)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 (0x00A3861C)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___POR 0x00
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___M 0x000000FF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 (0x00A38620)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___M 0xFFFFFFFF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 (0x00A38624)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___POR 0x00
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___M 0x000000FF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 (0x00A38628)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___M 0xFFFFFFFF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___M 0xFFFFFFFF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 (0x00A3862C)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___RWC QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___POR 0x00
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___M 0x000000FF
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___M 0x000000FF   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___S               0

#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO         (0x00A38630)
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___POR 0x00000000
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___POR 0x0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___POR 0x0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___M 0x00000010
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___S               4
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___M 0x0000000F
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___S               0
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___M  0x0000001F   
#define   UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___S                0

#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG (0x00A38634)
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG (0x00A38638)
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG (0x00A3863C)
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG (0x00A38640)
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG (0x00A38644)
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG (0x00A38648)
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG (0x00A3864C)
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG (0x00A38650)
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S              16
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S               0
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F   
#define   UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___S               0

#define UMAC_REO_R0_GXI_TESTBUS_LOWER             (0x00A38654)
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER___RWC       QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER___POR    0x00000000
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER___M      0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_TESTBUS_LOWER___S                    0

#define UMAC_REO_R0_GXI_TESTBUS_UPPER             (0x00A38658)
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER___RWC       QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER___POR    0x00000000
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___S               0
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER___M      0x000000FF   
#define   UMAC_REO_R0_GXI_TESTBUS_UPPER___S                    0

#define UMAC_REO_R0_GXI_SM_STATES_IX_0            (0x00A3865C)
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0___RWC      QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0___POR   0x00000211
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S               9
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S               4
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S               0
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0___M     0x00000FFF   
#define   UMAC_REO_R0_GXI_SM_STATES_IX_0___S                   0

#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK         (0x00A38660)
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK___M  0x00000001   
#define   UMAC_REO_R0_GXI_END_OF_TEST_CHECK___S                0

#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE        (0x00A38664)
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___RWC  QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S              11
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S              10
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S               9
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S               8
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S               7
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S               6
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S               5
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S               4
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S               3
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S               2
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S               1
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___S               0
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF   
#define   UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___S               0

#define UMAC_REO_R0_GXI_GXI_ERR_INTS              (0x00A38668)
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS___RWC        QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS___POR     0x00000000
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S              24
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S              16
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S               8
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S               0
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS___M       0x01010101   
#define   UMAC_REO_R0_GXI_GXI_ERR_INTS___S                     0

#define UMAC_REO_R0_GXI_GXI_ERR_STATS             (0x00A3866C)
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS___RWC       QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS___POR    0x00000000
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S              16
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S               8
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S               0
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS___M      0x003F3F3F   
#define   UMAC_REO_R0_GXI_GXI_ERR_STATS___S                    0

#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL       (0x00A38670)
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S              24
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S               8
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S               0
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F   
#define   UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___S               0

#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL       (0x00A38674)
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S              24
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S               8
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S               0
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F   
#define   UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___S               0

#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL          (0x00A38678)
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S              27
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S              26
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S              25
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S              24
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S              23
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S              20
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S              17
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S               9
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S               1
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S               0
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL___M   0x0FFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_MISC_CONTROL___S                 0

#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL          (0x00A3867C)
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S              16
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S               0
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___M   0xFFFF0001   
#define   UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___S                 0

#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS           (0x00A38680)
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS___POR  0x00000000
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S               0
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS___M    0x0000FFFF   
#define   UMAC_REO_R0_GXI_GXI_WDOG_STATUS___S                  0

#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS         (0x00A38684)
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___RWC   QCSR_REG_RO    
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S              16
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S               0
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___M  0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___S                0

#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL       (0x00A38688)
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___S               0

#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL       (0x00A3868C)
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___S               0

#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A38690)
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A38694)
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A38698)
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A3869C)
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL    (0x00A386A0)
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW    
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S              15
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S               8
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S               7
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S               0
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F   
#define   UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___S               0

#define UMAC_REO_R0_CACHE_CTL_CONFIG              (0x00A386A4)
#define   UMAC_REO_R0_CACHE_CTL_CONFIG___RWC        QCSR_REG_RW    
#define   UMAC_REO_R0_CACHE_CTL_CONFIG___POR     0x008608FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___POR 0x00
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___POR 0x1
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___POR 0x1
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___POR 0x1
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___POR 0x04
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___POR 0x0FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___M 0xFF000000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___S              24
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___M 0x00800000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___S              23
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___M 0x00400000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___S              22
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___M 0x00200000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___S              21
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___M 0x00100000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___S              20
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___M 0x00080000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___S              19
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___M 0x00040000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___S              18
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___M 0x00020000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___S              17
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___M 0x0001FE00
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___S               9
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___M 0x000001FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___S               0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG___M       0xFFFFFFFF   
#define   UMAC_REO_R0_CACHE_CTL_CONFIG___S                     0

#define UMAC_REO_R0_CACHE_CTL_CONTROL             (0x00A386A8)
#define   UMAC_REO_R0_CACHE_CTL_CONTROL___RWC       QCSR_REG_RW    
#define   UMAC_REO_R0_CACHE_CTL_CONTROL___POR    0x00000000
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___POR 0x0
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___M 0x00000002
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___S               1
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___M 0x00000001
#define   UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___S               0
#define   UMAC_REO_R0_CACHE_CTL_CONTROL___M      0x00000003   
#define   UMAC_REO_R0_CACHE_CTL_CONTROL___S                    0

#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET          (0x00A386AC)
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET___RWC    QCSR_REG_RW    
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET___POR 0x01F808FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___POR 0xFC
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___POR 0x04
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___POR 0x0FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___M 0x01FE0000
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___S              17
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___M 0x0001FE00
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___S               9
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___M 0x000001FF
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___S               0
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET___M   0x01FFFFFF   
#define   UMAC_REO_R0_CACHE_CTL_CONFIG_SET___S                 0

#define UMAC_REO_R0_CACHE_CTL_SET_SIZE            (0x00A386B0)
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE___RWC      QCSR_REG_RW    
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE___POR   0x000000F0
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___POR 0x0F0
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___M 0x000001FF
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___S               0
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE___M     0x000001FF   
#define   UMAC_REO_R0_CACHE_CTL_SET_SIZE___S                   0

#define UMAC_REO_R0_CLK_GATE_CTRL                 (0x00A386B4)
#define   UMAC_REO_R0_CLK_GATE_CTRL___RWC           QCSR_REG_RW    
#define   UMAC_REO_R0_CLK_GATE_CTRL___POR        0x00000400
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___POR 0x0
#define   UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___POR 0x1
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___POR 0x000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___M 0x00040000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___S              18
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___M 0x00020000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___S              17
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___M 0x00010000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___S              16
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___M 0x00008000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___S              15
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___M 0x00004000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___S              14
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___M 0x00002000
#define   UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___S              13
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___M 0x00001000
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___S              12
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___M 0x00000800
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___S              11
#define   UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___M 0x00000400
#define   UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___S              10
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___M 0x000003FF
#define   UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___S               0
#define   UMAC_REO_R0_CLK_GATE_CTRL___M          0x0007FFFF   
#define   UMAC_REO_R0_CLK_GATE_CTRL___S                        0

#define UMAC_REO_R0_EVENTMASK_IX_0                (0x00A386B8)
#define   UMAC_REO_R0_EVENTMASK_IX_0___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_EVENTMASK_IX_0___POR       0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_0__MASK___POR 0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_0__MASK___M   0xFFFFFFFF
#define   UMAC_REO_R0_EVENTMASK_IX_0__MASK___S                 0
#define   UMAC_REO_R0_EVENTMASK_IX_0___M         0xFFFFFFFF   
#define   UMAC_REO_R0_EVENTMASK_IX_0___S                       0

#define UMAC_REO_R0_EVENTMASK_IX_1                (0x00A386BC)
#define   UMAC_REO_R0_EVENTMASK_IX_1___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_EVENTMASK_IX_1___POR       0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_1__MASK___POR 0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_1__MASK___M   0xFFFFFFFF
#define   UMAC_REO_R0_EVENTMASK_IX_1__MASK___S                 0
#define   UMAC_REO_R0_EVENTMASK_IX_1___M         0xFFFFFFFF   
#define   UMAC_REO_R0_EVENTMASK_IX_1___S                       0

#define UMAC_REO_R0_EVENTMASK_IX_2                (0x00A386C0)
#define   UMAC_REO_R0_EVENTMASK_IX_2___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_EVENTMASK_IX_2___POR       0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_2__MASK___POR 0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_2__MASK___M   0xFFFFFFFF
#define   UMAC_REO_R0_EVENTMASK_IX_2__MASK___S                 0
#define   UMAC_REO_R0_EVENTMASK_IX_2___M         0xFFFFFFFF   
#define   UMAC_REO_R0_EVENTMASK_IX_2___S                       0

#define UMAC_REO_R0_EVENTMASK_IX_3                (0x00A386C4)
#define   UMAC_REO_R0_EVENTMASK_IX_3___RWC          QCSR_REG_RW    
#define   UMAC_REO_R0_EVENTMASK_IX_3___POR       0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_3__MASK___POR 0x00000000
#define   UMAC_REO_R0_EVENTMASK_IX_3__MASK___M   0xFFFFFFFF
#define   UMAC_REO_R0_EVENTMASK_IX_3__MASK___S                 0
#define   UMAC_REO_R0_EVENTMASK_IX_3___M         0xFFFFFFFF   
#define   UMAC_REO_R0_EVENTMASK_IX_3___S                       0

#define UMAC_REO_R1_MISC_DEBUG_CTRL               (0x00A3A000)
#define   UMAC_REO_R1_MISC_DEBUG_CTRL___RWC         QCSR_REG_RW    
#define   UMAC_REO_R1_MISC_DEBUG_CTRL___POR      0x100771F0
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___POR 0x0
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___POR 0x0
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___POR 0x100
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___POR 0x1DC
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___POR 0x1F0
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___M 0x80000000
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___S              31
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___M 0x40000000
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___S              30
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___M 0x3FF00000
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___S              20
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___M 0x000FFC00
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___S              10
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___M 0x000003FF
#define   UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___S               0
#define   UMAC_REO_R1_MISC_DEBUG_CTRL___M        0xFFFFFFFF   
#define   UMAC_REO_R1_MISC_DEBUG_CTRL___S                      0

#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL          (0x00A3A004)
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___RWC    QCSR_REG_RW    
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___POR 0x003FF03F
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___POR 0x3FF
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___POR 0x03F
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___M 0x00FFF000
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___S              12
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___M 0x00000FFF
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___S               0
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___M   0x00FFFFFF   
#define   UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___S                 0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL       (0x00A3A008)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___POR 0x00000800
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___POR 0x1
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___POR 0x0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___POR 0x0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___M 0x00000800
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___S              11
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___M 0x00000400
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___M 0x00000200
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___S               9
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___M 0x000001FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___M 0x00000FFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT     (0x00A3A00C)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___M 0xFFFFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___M 0xFFFFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT    (0x00A3A010)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___POR 0x000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___M 0x00FFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___M 0x00FFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW (0x00A3A014)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___M 0xFFFFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___M 0xFFFFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH (0x00A3A018)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___M 0xFFFFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___M 0xFFFFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM           (0x00A3A01C)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM___RWC     QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM___POR  0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___POR 0x0000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___M 0x01FFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM___M    0x01FFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_STM___S                  0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST     (0x00A3A020)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___M 0x0007FC00
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___M 0x000003FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___M 0x0007FFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1    (0x00A3A024)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___M 0x0007FC00
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___M 0x000003FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___M 0x0007FFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2    (0x00A3A028)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___M 0x0007FC00
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___M 0x000003FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___M 0x0007FFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3    (0x00A3A02C)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___M 0x0007FC00
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___M 0x000003FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___M 0x0007FFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW (0x00A3A030)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___M 0xFFFFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH (0x00A3A034)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___M 0xFFFFFFFF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___M 0xFFFFFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___S               0

#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER (0x00A3A038)
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___POR 0x000
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___M 0x000FFC00
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___S              10
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___M 0x000003FF
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___S               0
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___M 0x000FFFFF   
#define   UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___S               0

#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK   (0x00A3A03C)
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001   
#define   UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___S               0

#define UMAC_REO_R1_END_OF_TEST_CHECK             (0x00A3A040)
#define   UMAC_REO_R1_END_OF_TEST_CHECK___RWC       QCSR_REG_RW    
#define   UMAC_REO_R1_END_OF_TEST_CHECK___POR    0x00000000
#define   UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_REO_R1_END_OF_TEST_CHECK___M      0x00000001   
#define   UMAC_REO_R1_END_OF_TEST_CHECK___S                    0

#define UMAC_REO_R1_SM_ALL_IDLE                   (0x00A3A044)
#define   UMAC_REO_R1_SM_ALL_IDLE___RWC             QCSR_REG_RO    
#define   UMAC_REO_R1_SM_ALL_IDLE___POR          0x00000001
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___POR 0x0
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___POR 0x0
#define   UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___POR 0x1
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___M 0x00000004
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___S               2
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___M 0x00000002
#define   UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___S               1
#define   UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___M 0x00000001
#define   UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___S               0
#define   UMAC_REO_R1_SM_ALL_IDLE___M            0x00000007   
#define   UMAC_REO_R1_SM_ALL_IDLE___S                          0

#define UMAC_REO_R1_TESTBUS_CTRL                  (0x00A3A048)
#define   UMAC_REO_R1_TESTBUS_CTRL___RWC            QCSR_REG_RW    
#define   UMAC_REO_R1_TESTBUS_CTRL___POR         0x00000000
#define   UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00
#define   UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000007F
#define   UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   UMAC_REO_R1_TESTBUS_CTRL___M           0x0000007F   
#define   UMAC_REO_R1_TESTBUS_CTRL___S                         0

#define UMAC_REO_R1_TESTBUS_LOWER                 (0x00A3A04C)
#define   UMAC_REO_R1_TESTBUS_LOWER___RWC           QCSR_REG_RO    
#define   UMAC_REO_R1_TESTBUS_LOWER___POR        0x00000000
#define   UMAC_REO_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_REO_R1_TESTBUS_LOWER__VALUE___M   0xFFFFFFFF
#define   UMAC_REO_R1_TESTBUS_LOWER__VALUE___S                 0
#define   UMAC_REO_R1_TESTBUS_LOWER___M          0xFFFFFFFF   
#define   UMAC_REO_R1_TESTBUS_LOWER___S                        0

#define UMAC_REO_R1_TESTBUS_HIGHER                (0x00A3A050)
#define   UMAC_REO_R1_TESTBUS_HIGHER___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_TESTBUS_HIGHER___POR       0x00000000
#define   UMAC_REO_R1_TESTBUS_HIGHER__VALUE___POR 0x00
#define   UMAC_REO_R1_TESTBUS_HIGHER__VALUE___M  0x000000FF
#define   UMAC_REO_R1_TESTBUS_HIGHER__VALUE___S                0
#define   UMAC_REO_R1_TESTBUS_HIGHER___M         0x000000FF   
#define   UMAC_REO_R1_TESTBUS_HIGHER___S                       0

#define UMAC_REO_R1_SM_STATES_IX_0                (0x00A3A054)
#define   UMAC_REO_R1_SM_STATES_IX_0___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_0___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_0___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_0___S                       0

#define UMAC_REO_R1_SM_STATES_IX_1                (0x00A3A058)
#define   UMAC_REO_R1_SM_STATES_IX_1___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_1___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_1___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_1___S                       0

#define UMAC_REO_R1_SM_STATES_IX_2                (0x00A3A05C)
#define   UMAC_REO_R1_SM_STATES_IX_2___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_2___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_2___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_2___S                       0

#define UMAC_REO_R1_SM_STATES_IX_3                (0x00A3A060)
#define   UMAC_REO_R1_SM_STATES_IX_3___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_3___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_3___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_3___S                       0

#define UMAC_REO_R1_SM_STATES_IX_4                (0x00A3A064)
#define   UMAC_REO_R1_SM_STATES_IX_4___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_4___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_4___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_4___S                       0

#define UMAC_REO_R1_SM_STATES_IX_5                (0x00A3A068)
#define   UMAC_REO_R1_SM_STATES_IX_5___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_5___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_5___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_5___S                       0

#define UMAC_REO_R1_SM_STATES_IX_6                (0x00A3A06C)
#define   UMAC_REO_R1_SM_STATES_IX_6___RWC          QCSR_REG_RO    
#define   UMAC_REO_R1_SM_STATES_IX_6___POR       0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___POR 0x00000000
#define   UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___S               0
#define   UMAC_REO_R1_SM_STATES_IX_6___M         0xFFFFFFFF   
#define   UMAC_REO_R1_SM_STATES_IX_6___S                       0

#define UMAC_REO_R1_IDLE_STATES_IX_0              (0x00A3A070)
#define   UMAC_REO_R1_IDLE_STATES_IX_0___RWC        QCSR_REG_RO    
#define   UMAC_REO_R1_IDLE_STATES_IX_0___POR     0x00000000
#define   UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___POR 0x00000000
#define   UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___M 0xFFFFFFFF
#define   UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___S               0
#define   UMAC_REO_R1_IDLE_STATES_IX_0___M       0xFFFFFFFF   
#define   UMAC_REO_R1_IDLE_STATES_IX_0___S                     0

#define UMAC_REO_R1_INVALID_APB_ACCESS            (0x00A3A074)
#define   UMAC_REO_R1_INVALID_APB_ACCESS___RWC      QCSR_REG_RW    
#define   UMAC_REO_R1_INVALID_APB_ACCESS___POR   0x00000000
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___POR 0x0
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___POR 0x00000
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___M 0x00060000
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___S              17
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___M 0x0001FFFF
#define   UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___S               0
#define   UMAC_REO_R1_INVALID_APB_ACCESS___M     0x0007FFFF   
#define   UMAC_REO_R1_INVALID_APB_ACCESS___S                   0

#define UMAC_REO_R2_RXDMA2REO0_RING_HP            (0x00A3B000)
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP___POR   0x00000000
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP___M     0x0000FFFF   
#define   UMAC_REO_R2_RXDMA2REO0_RING_HP___S                   0

#define UMAC_REO_R2_RXDMA2REO0_RING_TP            (0x00A3B004)
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP___POR   0x00000000
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP___M     0x0000FFFF   
#define   UMAC_REO_R2_RXDMA2REO0_RING_TP___S                   0

#define UMAC_REO_R2_WBM2REO_LINK_RING_HP          (0x00A3B008)
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP___RWC    QCSR_REG_RW    
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP___POR 0x00000000
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP___M   0x0000FFFF   
#define   UMAC_REO_R2_WBM2REO_LINK_RING_HP___S                 0

#define UMAC_REO_R2_WBM2REO_LINK_RING_TP          (0x00A3B00C)
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP___RWC    QCSR_REG_RW    
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP___POR 0x00000000
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP___M   0x0000FFFF   
#define   UMAC_REO_R2_WBM2REO_LINK_RING_TP___S                 0

#define UMAC_REO_R2_REO_CMD_RING_HP               (0x00A3B010)
#define   UMAC_REO_R2_REO_CMD_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO_CMD_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO_CMD_RING_HP___M        0x0000FFFF   
#define   UMAC_REO_R2_REO_CMD_RING_HP___S                      0

#define UMAC_REO_R2_REO_CMD_RING_TP               (0x00A3B014)
#define   UMAC_REO_R2_REO_CMD_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO_CMD_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO_CMD_RING_TP___M        0x0000FFFF   
#define   UMAC_REO_R2_REO_CMD_RING_TP___S                      0

#define UMAC_REO_R2_SW2REO_RING_HP                (0x00A3B018)
#define   UMAC_REO_R2_SW2REO_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_REO_R2_SW2REO_RING_HP___POR       0x00000000
#define   UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_SW2REO_RING_HP___M         0x0000FFFF   
#define   UMAC_REO_R2_SW2REO_RING_HP___S                       0

#define UMAC_REO_R2_SW2REO_RING_TP                (0x00A3B01C)
#define   UMAC_REO_R2_SW2REO_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_REO_R2_SW2REO_RING_TP___POR       0x00000000
#define   UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_SW2REO_RING_TP___M         0x0000FFFF   
#define   UMAC_REO_R2_SW2REO_RING_TP___S                       0

#define UMAC_REO_R2_SW2REO1_RING_HP               (0x00A3B020)
#define   UMAC_REO_R2_SW2REO1_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_SW2REO1_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_SW2REO1_RING_HP___M        0x0000FFFF   
#define   UMAC_REO_R2_SW2REO1_RING_HP___S                      0

#define UMAC_REO_R2_SW2REO1_RING_TP               (0x00A3B024)
#define   UMAC_REO_R2_SW2REO1_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_SW2REO1_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_SW2REO1_RING_TP___M        0x0000FFFF   
#define   UMAC_REO_R2_SW2REO1_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW1_RING_HP               (0x00A3B028)
#define   UMAC_REO_R2_REO2SW1_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW1_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW1_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW1_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW1_RING_TP               (0x00A3B02C)
#define   UMAC_REO_R2_REO2SW1_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW1_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW1_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW1_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW2_RING_HP               (0x00A3B030)
#define   UMAC_REO_R2_REO2SW2_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW2_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW2_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW2_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW2_RING_TP               (0x00A3B034)
#define   UMAC_REO_R2_REO2SW2_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW2_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW2_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW2_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW3_RING_HP               (0x00A3B038)
#define   UMAC_REO_R2_REO2SW3_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW3_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW3_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW3_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW3_RING_TP               (0x00A3B03C)
#define   UMAC_REO_R2_REO2SW3_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW3_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW3_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW3_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW4_RING_HP               (0x00A3B040)
#define   UMAC_REO_R2_REO2SW4_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW4_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW4_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW4_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW4_RING_TP               (0x00A3B044)
#define   UMAC_REO_R2_REO2SW4_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW4_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW4_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW4_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW5_RING_HP               (0x00A3B048)
#define   UMAC_REO_R2_REO2SW5_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW5_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW5_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW5_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW5_RING_TP               (0x00A3B04C)
#define   UMAC_REO_R2_REO2SW5_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW5_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW5_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW5_RING_TP___S                      0

#define UMAC_REO_R2_REO2SW6_RING_HP               (0x00A3B050)
#define   UMAC_REO_R2_REO2SW6_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW6_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2SW6_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW6_RING_HP___S                      0

#define UMAC_REO_R2_REO2SW6_RING_TP               (0x00A3B054)
#define   UMAC_REO_R2_REO2SW6_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2SW6_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2SW6_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2SW6_RING_TP___S                      0

#define UMAC_REO_R2_REO2TCL_RING_HP               (0x00A3B058)
#define   UMAC_REO_R2_REO2TCL_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2TCL_RING_HP___POR      0x00000000
#define   UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2TCL_RING_HP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2TCL_RING_HP___S                      0

#define UMAC_REO_R2_REO2TCL_RING_TP               (0x00A3B05C)
#define   UMAC_REO_R2_REO2TCL_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_REO_R2_REO2TCL_RING_TP___POR      0x00000000
#define   UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2TCL_RING_TP___M        0x000FFFFF   
#define   UMAC_REO_R2_REO2TCL_RING_TP___S                      0

#define UMAC_REO_R2_REO2FW_RING_HP                (0x00A3B060)
#define   UMAC_REO_R2_REO2FW_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_REO_R2_REO2FW_RING_HP___POR       0x00000000
#define   UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO2FW_RING_HP___M         0x000FFFFF   
#define   UMAC_REO_R2_REO2FW_RING_HP___S                       0

#define UMAC_REO_R2_REO2FW_RING_TP                (0x00A3B064)
#define   UMAC_REO_R2_REO2FW_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_REO_R2_REO2FW_RING_TP___POR       0x00000000
#define   UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO2FW_RING_TP___M         0x000FFFFF   
#define   UMAC_REO_R2_REO2FW_RING_TP___S                       0

#define UMAC_REO_R2_REO_RELEASE_RING_HP           (0x00A3B068)
#define   UMAC_REO_R2_REO_RELEASE_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_REO_R2_REO_RELEASE_RING_HP___POR  0x00000000
#define   UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO_RELEASE_RING_HP___M    0x0000FFFF   
#define   UMAC_REO_R2_REO_RELEASE_RING_HP___S                  0

#define UMAC_REO_R2_REO_RELEASE_RING_TP           (0x00A3B06C)
#define   UMAC_REO_R2_REO_RELEASE_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_REO_R2_REO_RELEASE_RING_TP___POR  0x00000000
#define   UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO_RELEASE_RING_TP___M    0x0000FFFF   
#define   UMAC_REO_R2_REO_RELEASE_RING_TP___S                  0

#define UMAC_REO_R2_REO_STATUS_RING_HP            (0x00A3B070)
#define   UMAC_REO_R2_REO_STATUS_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_REO_R2_REO_STATUS_RING_HP___POR   0x00000000
#define   UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___S               0
#define   UMAC_REO_R2_REO_STATUS_RING_HP___M     0x0000FFFF   
#define   UMAC_REO_R2_REO_STATUS_RING_HP___S                   0

#define UMAC_REO_R2_REO_STATUS_RING_TP            (0x00A3B074)
#define   UMAC_REO_R2_REO_STATUS_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_REO_R2_REO_STATUS_RING_TP___POR   0x00000000
#define   UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___S               0
#define   UMAC_REO_R2_REO_STATUS_RING_TP___M     0x0000FFFF   
#define   UMAC_REO_R2_REO_STATUS_RING_TP___S                   0

#define UMAC_TQM_R0_CONTROL                       (0x00A3C000)
#define   UMAC_TQM_R0_CONTROL___RWC                 QCSR_REG_RW    
#define   UMAC_TQM_R0_CONTROL___POR              0x00000012
#define   UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___POR 0x1
#define   UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___POR 0x0
#define   UMAC_TQM_R0_CONTROL__STAT_RING_SEL___POR 0x0
#define   UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___POR 0x1
#define   UMAC_TQM_R0_CONTROL__ENABLE___POR      0x0
#define   UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___M 0x00000010
#define   UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___S               4
#define   UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___M 0x00000008
#define   UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___S               3
#define   UMAC_TQM_R0_CONTROL__STAT_RING_SEL___M 0x00000004
#define   UMAC_TQM_R0_CONTROL__STAT_RING_SEL___S               2
#define   UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___M 0x00000002
#define   UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___S               1
#define   UMAC_TQM_R0_CONTROL__ENABLE___M        0x00000001
#define   UMAC_TQM_R0_CONTROL__ENABLE___S                      0
#define   UMAC_TQM_R0_CONTROL___M                0x0000001F   
#define   UMAC_TQM_R0_CONTROL___S                              0

#define UMAC_TQM_R0_PAUSE_CONTROL                 (0x00A3C004)
#define   UMAC_TQM_R0_PAUSE_CONTROL___RWC           QCSR_REG_RW    
#define   UMAC_TQM_R0_PAUSE_CONTROL___POR        0x00000003
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___POR 0x0
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___POR 0x1
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___POR 0x1
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___M 0x00000004
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___S               2
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___M 0x00000002
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___S               1
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___M 0x00000001
#define   UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___S               0
#define   UMAC_TQM_R0_PAUSE_CONTROL___M          0x00000007   
#define   UMAC_TQM_R0_PAUSE_CONTROL___S                        0

#define UMAC_TQM_R0_MISC_CONTROL                  (0x00A3C008)
#define   UMAC_TQM_R0_MISC_CONTROL___RWC            QCSR_REG_RW    
#define   UMAC_TQM_R0_MISC_CONTROL___POR         0x00000010
#define   UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___POR 0x0
#define   UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___POR 0x0
#define   UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___POR 0x10
#define   UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___M 0x00000200
#define   UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___S               9
#define   UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___M 0x00000100
#define   UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___S               8
#define   UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___M 0x000000FF
#define   UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___S               0
#define   UMAC_TQM_R0_MISC_CONTROL___M           0x000003FF   
#define   UMAC_TQM_R0_MISC_CONTROL___S                         0

#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL (0x00A3C00C)
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___POR 0x0000020A
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___POR 0x1
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___POR 0x0
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___POR 0x0A
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___M 0x00000200
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___S               9
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___M 0x00000100
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___S               8
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___M 0x000000FF
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___S               0
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___M 0x000003FF   
#define   UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB         (0x00A3C010)
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___S                0

#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB         (0x00A3C014)
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___S                0

#define UMAC_TQM_R0_TCL2TQM_RING_ID               (0x00A3C018)
#define   UMAC_TQM_R0_TCL2TQM_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_ID___POR      0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_ID___M        0x000000FF   
#define   UMAC_TQM_R0_TCL2TQM_RING_ID___S                      0

#define UMAC_TQM_R0_TCL2TQM_RING_STATUS           (0x00A3C01C)
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS___POR  0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_STATUS___S                  0

#define UMAC_TQM_R0_TCL2TQM_RING_MISC             (0x00A3C020)
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC___POR    0x00000080
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC___M      0x003FFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_MISC___S                    0

#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB      (0x00A3C02C)
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB      (0x00A3C030)
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C040)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C044)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS (0x00A3C048)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C04C)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C050)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C054)
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB    (0x00A3C058)
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB    (0x00A3C05C)
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA        (0x00A3C060)
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET  (0x00A3C064)
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB          (0x00A3C068)
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___S                 0

#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB          (0x00A3C06C)
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___M   0x00FFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___S                 0

#define UMAC_TQM_R0_SW2TQM_RING_ID                (0x00A3C070)
#define   UMAC_TQM_R0_SW2TQM_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_ID___POR       0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_ID___M         0x000000FF   
#define   UMAC_TQM_R0_SW2TQM_RING_ID___S                       0

#define UMAC_TQM_R0_SW2TQM_RING_STATUS            (0x00A3C074)
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS___POR   0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_STATUS___S                   0

#define UMAC_TQM_R0_SW2TQM_RING_MISC              (0x00A3C078)
#define   UMAC_TQM_R0_SW2TQM_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_MISC___POR     0x00000080
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_MISC___M       0x003FFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_MISC___S                     0

#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB       (0x00A3C084)
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB       (0x00A3C088)
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C098)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C09C)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS (0x00A3C0A0)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C0A4)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C0A8)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C0AC)
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB     (0x00A3C0B0)
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB     (0x00A3C0B4)
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA         (0x00A3C0B8)
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___S                0

#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET   (0x00A3C0BC)
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB          (0x00A3C0C0)
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___S                 0

#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB          (0x00A3C0C4)
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___M   0x00FFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___S                 0

#define UMAC_TQM_R0_FW2TQM_RING_ID                (0x00A3C0C8)
#define   UMAC_TQM_R0_FW2TQM_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_ID___POR       0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_ID___M         0x000000FF   
#define   UMAC_TQM_R0_FW2TQM_RING_ID___S                       0

#define UMAC_TQM_R0_FW2TQM_RING_STATUS            (0x00A3C0CC)
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS___POR   0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_STATUS___S                   0

#define UMAC_TQM_R0_FW2TQM_RING_MISC              (0x00A3C0D0)
#define   UMAC_TQM_R0_FW2TQM_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_MISC___POR     0x00000080
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_MISC___M       0x003FFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_MISC___S                     0

#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB       (0x00A3C0DC)
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB       (0x00A3C0E0)
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C0F0)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C0F4)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS (0x00A3C0F8)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C0FC)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C100)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C104)
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB     (0x00A3C108)
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB     (0x00A3C10C)
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA         (0x00A3C110)
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___S                0

#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET   (0x00A3C114)
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB          (0x00A3C118)
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___S                 0

#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB          (0x00A3C11C)
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___M   0x00FFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___S                 0

#define UMAC_TQM_R0_SW_CMD_RING_ID                (0x00A3C120)
#define   UMAC_TQM_R0_SW_CMD_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_ID___POR       0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_ID___M         0x000000FF   
#define   UMAC_TQM_R0_SW_CMD_RING_ID___S                       0

#define UMAC_TQM_R0_SW_CMD_RING_STATUS            (0x00A3C124)
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS___POR   0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_STATUS___S                   0

#define UMAC_TQM_R0_SW_CMD_RING_MISC              (0x00A3C128)
#define   UMAC_TQM_R0_SW_CMD_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_MISC___POR     0x00000080
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_MISC___M       0x003FFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_MISC___S                     0

#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB       (0x00A3C134)
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB       (0x00A3C138)
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C148)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C14C)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS (0x00A3C150)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER (0x00A3C154)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER (0x00A3C158)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS (0x00A3C15C)
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB     (0x00A3C160)
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB     (0x00A3C164)
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA         (0x00A3C168)
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___S                0

#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET   (0x00A3C16C)
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB         (0x00A3C170)
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___S                0

#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB         (0x00A3C174)
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___S                0

#define UMAC_TQM_R0_SW_CMD1_RING_ID               (0x00A3C178)
#define   UMAC_TQM_R0_SW_CMD1_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_ID___POR      0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_ID___M        0x000000FF   
#define   UMAC_TQM_R0_SW_CMD1_RING_ID___S                      0

#define UMAC_TQM_R0_SW_CMD1_RING_STATUS           (0x00A3C17C)
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS___POR  0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_STATUS___S                  0

#define UMAC_TQM_R0_SW_CMD1_RING_MISC             (0x00A3C180)
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC___POR    0x00000080
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC___M      0x003FFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_MISC___S                    0

#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB      (0x00A3C18C)
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB      (0x00A3C190)
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C1A0)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C1A4)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS (0x00A3C1A8)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER (0x00A3C1AC)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER (0x00A3C1B0)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS (0x00A3C1B4)
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB    (0x00A3C1B8)
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB    (0x00A3C1BC)
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA        (0x00A3C1C0)
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET  (0x00A3C1C4)
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB        (0x00A3C1C8)
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB        (0x00A3C1CC)
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_ID              (0x00A3C1D0)
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID___POR     0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID___M       0x000000FF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_ID___S                     0

#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS          (0x00A3C1D4)
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS___RWC    QCSR_REG_RO    
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS___M   0xFFFFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_STATUS___S                 0

#define UMAC_TQM_R0_SCH2TQM0_RING_MISC            (0x00A3C1D8)
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC___RWC      QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC___POR   0x00000080
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC___M     0x003FFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_MISC___S                   0

#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB     (0x00A3C1E4)
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB     (0x00A3C1E8)
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C1F8)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C1FC)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS (0x00A3C200)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER (0x00A3C204)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER (0x00A3C208)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS (0x00A3C20C)
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET (0x00A3C21C)
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB    (0x00A3C2D0)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB    (0x00A3C2D4)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID          (0x00A3C2D8)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___M   0x000000FF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___S                 0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS      (0x00A3C2DC)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC        (0x00A3C2E0)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___POR 0x00000080
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___M 0x003FFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB (0x00A3C2EC)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB (0x00A3C2F0)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C300)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C304)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS (0x00A3C308)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A3C30C)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A3C310)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A3C314)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB (0x00A3C318)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB (0x00A3C31C)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA   (0x00A3C320)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET (0x00A3C324)
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB     (0x00A3C328)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB     (0x00A3C32C)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_ID           (0x00A3C330)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID___POR  0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___S               8
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID___M    0x0000FFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_ID___S                  0

#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS       (0x00A3C334)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC         (0x00A3C338)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC___POR 0x00000080
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC___M  0x03FFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MISC___S                0

#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB  (0x00A3C33C)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB  (0x00A3C340)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP (0x00A3C34C)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS (0x00A3C350)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A3C354)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB (0x00A3C370)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB (0x00A3C374)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA    (0x00A3C378)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET (0x00A3C37C)
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB      (0x00A3C380)
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB      (0x00A3C384)
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_ID            (0x00A3C388)
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID___RWC      QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID___POR   0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___S               8
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID___M     0x0000FFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_ID___S                   0

#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS        (0x00A3C38C)
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS___RWC  QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_STATUS___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_MISC          (0x00A3C390)
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC___POR 0x00000080
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC___M   0x03FFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_MISC___S                 0

#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB   (0x00A3C394)
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB   (0x00A3C398)
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP (0x00A3C3A4)
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS (0x00A3C3A8)
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER (0x00A3C3AC)
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB (0x00A3C3C8)
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB (0x00A3C3CC)
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA     (0x00A3C3D0)
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET (0x00A3C3D4)
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB     (0x00A3C3D8)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB     (0x00A3C3DC)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_ID           (0x00A3C3E0)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID___POR  0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___S               8
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID___M    0x0000FFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_ID___S                  0

#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS       (0x00A3C3E4)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC         (0x00A3C3E8)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC___POR 0x00000080
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC___M  0x03FFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MISC___S                0

#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB  (0x00A3C3EC)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB  (0x00A3C3F0)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP (0x00A3C3FC)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS (0x00A3C400)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A3C404)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB (0x00A3C420)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB (0x00A3C424)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA    (0x00A3C428)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___S               0

#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET (0x00A3C42C)
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TQM_R0_GXI_TESTBUS_LOWER             (0x00A3C430)
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER___POR    0x00000000
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER___M      0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_TESTBUS_LOWER___S                    0

#define UMAC_TQM_R0_GXI_TESTBUS_UPPER             (0x00A3C434)
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER___POR    0x00000000
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___S               0
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER___M      0x000000FF   
#define   UMAC_TQM_R0_GXI_TESTBUS_UPPER___S                    0

#define UMAC_TQM_R0_GXI_SM_STATES_IX_0            (0x00A3C438)
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0___POR   0x00000211
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S               9
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S               4
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S               0
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0___M     0x00000FFF   
#define   UMAC_TQM_R0_GXI_SM_STATES_IX_0___S                   0

#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK         (0x00A3C43C)
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___M  0x00000001   
#define   UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___S                0

#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE        (0x00A3C440)
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S              11
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S              10
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S               9
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S               8
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S               7
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S               6
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S               5
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S               4
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S               3
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S               2
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S               1
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___S               0
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF   
#define   UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___S               0

#define UMAC_TQM_R0_GXI_GXI_ERR_INTS              (0x00A3C444)
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS___RWC        QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS___POR     0x00000000
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S              24
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S              16
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S               8
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S               0
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS___M       0x01010101   
#define   UMAC_TQM_R0_GXI_GXI_ERR_INTS___S                     0

#define UMAC_TQM_R0_GXI_GXI_ERR_STATS             (0x00A3C448)
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS___POR    0x00000000
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S              16
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S               8
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S               0
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS___M      0x003F3F3F   
#define   UMAC_TQM_R0_GXI_GXI_ERR_STATS___S                    0

#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL       (0x00A3C44C)
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S              24
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S               8
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S               0
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F   
#define   UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___S               0

#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL       (0x00A3C450)
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S              24
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S               8
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S               0
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F   
#define   UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___S               0

#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL          (0x00A3C454)
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S              27
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S              26
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S              25
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S              24
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S              23
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S              20
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S              17
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S               9
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S               1
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S               0
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___M   0x0FFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___S                 0

#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL          (0x00A3C458)
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S              16
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S               0
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___M   0xFFFF0001   
#define   UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___S                 0

#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS           (0x00A3C45C)
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___POR  0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S               0
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___M    0x0000FFFF   
#define   UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___S                  0

#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS         (0x00A3C460)
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___RWC   QCSR_REG_RO    
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S              16
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S               0
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___M  0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___S                0

#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL       (0x00A3C464)
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___S               0

#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL       (0x00A3C468)
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___S               0

#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A3C46C)
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A3C470)
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A3C474)
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A3C478)
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL    (0x00A3C47C)
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S              15
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S               8
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S               7
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S               0
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F   
#define   UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___S               0

#define UMAC_TQM_R0_CACHE_CTL_CONFIG              (0x00A3C480)
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG___POR     0x008608FF
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___POR 0x00
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___POR 0x1
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___POR 0x1
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___POR 0x1
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___POR 0x04
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___POR 0x0FF
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___M 0xFF000000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___S              24
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___M 0x00800000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___S              23
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___M 0x00400000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___S              22
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___M 0x00200000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___S              21
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___M 0x00100000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___S              20
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___M 0x00080000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___S              19
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___M 0x00040000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___S              18
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___M 0x00020000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___S              17
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___M 0x0001FE00
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___S               9
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___M 0x000001FF
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___S               0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG___M       0xFFFFFFFF   
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG___S                     0

#define UMAC_TQM_R0_CACHE_CTL_CONTROL             (0x00A3C484)
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL___RWC       QCSR_REG_RW    
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL___POR    0x00000000
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___POR 0x0
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___M 0x00000002
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___S               1
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___M 0x00000001
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___S               0
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL___M      0x00000003   
#define   UMAC_TQM_R0_CACHE_CTL_CONTROL___S                    0

#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET          (0x00A3C488)
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___POR 0x00000000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___POR 0x0000000
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___M 0x01FFFFFF
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___S               0
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___M   0x01FFFFFF   
#define   UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___S                 0

#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE            (0x00A3C48C)
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE___RWC      QCSR_REG_RW    
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE___POR   0x000000F0
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___POR 0x0F0
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___M 0x000001FF
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___S               0
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE___M     0x000001FF   
#define   UMAC_TQM_R0_CACHE_CTL_SET_SIZE___S                   0

#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH          (0x00A3C490)
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___POR 0x10004710
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___POR 0x10
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___POR 0x04
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___POR 0x1C
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___POR 0x10
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___M 0x3F000000
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___S              24
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___M 0x0003F000
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___S              12
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___M 0x00000FC0
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___S               6
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___M 0x0000003F
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___S               0
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___M   0x3F03FFFF   
#define   UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___S                 0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0   (0x00A3C494)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___POR 0x002F0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___POR 0x02F
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___POR 0x000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1   (0x00A3C498)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___POR 0x005F0030
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___POR 0x05F
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___POR 0x030
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2   (0x00A3C49C)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___POR 0x008F0060
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___POR 0x08F
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___POR 0x060
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3   (0x00A3C4A0)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___POR 0x00BF0090
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___POR 0x0BF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___POR 0x090
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4   (0x00A3C4A4)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___POR 0x01370120
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___POR 0x137
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___POR 0x120
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8   (0x00A3C4B0)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___POR 0x00EF00C0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___POR 0x0EF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___POR 0x0C0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___S               0

#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9   (0x00A3C4B4)
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___POR 0x011F00F0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___POR 0x11F
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___POR 0x0F0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___M 0x01FF0000
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___S              16
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___M 0x000001FF
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___S               0
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___M 0x01FF01FF   
#define   UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___S               0

#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION       (0x00A3C4B8)
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION___POR 0x00001441
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___POR 0x1
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___POR 0x4
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___POR 0x41
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___M 0x00001000
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___S              12
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___M 0x00000F00
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___S               8
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___M 0x0000007F
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___S               0
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION___M 0x00001F7F   
#define   UMAC_TQM_R0_STATUS_BUFFER_PARTITION___S               0

#define UMAC_TQM_R0_WATCHDOG                      (0x00A3C4BC)
#define   UMAC_TQM_R0_WATCHDOG___RWC                QCSR_REG_RW    
#define   UMAC_TQM_R0_WATCHDOG___POR             0x00002710
#define   UMAC_TQM_R0_WATCHDOG__STATUS___POR     0x0000
#define   UMAC_TQM_R0_WATCHDOG__LIMIT___POR      0x2710
#define   UMAC_TQM_R0_WATCHDOG__STATUS___M       0x7FFF0000
#define   UMAC_TQM_R0_WATCHDOG__STATUS___S                    16
#define   UMAC_TQM_R0_WATCHDOG__LIMIT___M        0x0000FFFF
#define   UMAC_TQM_R0_WATCHDOG__LIMIT___S                      0
#define   UMAC_TQM_R0_WATCHDOG___M               0x7FFFFFFF   
#define   UMAC_TQM_R0_WATCHDOG___S                             0

#define UMAC_TQM_R0_TESTBUS_CTRL                  (0x00A3C4C0)
#define   UMAC_TQM_R0_TESTBUS_CTRL___RWC            QCSR_REG_RW    
#define   UMAC_TQM_R0_TESTBUS_CTRL___POR         0x00000000
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___POR 0x0
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___POR 0x00
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___POR 0x00
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___M 0x0000E000
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___S              13
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___M 0x00001F00
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___S               8
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___M 0x0000003F
#define   UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___S               0
#define   UMAC_TQM_R0_TESTBUS_CTRL___M           0x0000FF3F   
#define   UMAC_TQM_R0_TESTBUS_CTRL___S                         0

#define UMAC_TQM_R0_TESTBUS_LOWER                 (0x00A3C4C4)
#define   UMAC_TQM_R0_TESTBUS_LOWER___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_TESTBUS_LOWER___POR        0x00000000
#define   UMAC_TQM_R0_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_TESTBUS_LOWER__VALUE___M   0xFFFFFFFF
#define   UMAC_TQM_R0_TESTBUS_LOWER__VALUE___S                 0
#define   UMAC_TQM_R0_TESTBUS_LOWER___M          0xFFFFFFFF   
#define   UMAC_TQM_R0_TESTBUS_LOWER___S                        0

#define UMAC_TQM_R0_TESTBUS_UPPER                 (0x00A3C4C8)
#define   UMAC_TQM_R0_TESTBUS_UPPER___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_TESTBUS_UPPER___POR        0x00000000
#define   UMAC_TQM_R0_TESTBUS_UPPER__VALUE___POR 0x00
#define   UMAC_TQM_R0_TESTBUS_UPPER__VALUE___M   0x000000FF
#define   UMAC_TQM_R0_TESTBUS_UPPER__VALUE___S                 0
#define   UMAC_TQM_R0_TESTBUS_UPPER___M          0x000000FF   
#define   UMAC_TQM_R0_TESTBUS_UPPER___S                        0

#define UMAC_TQM_R0_EVENTMASK_IX_0                (0x00A3C4CC)
#define   UMAC_TQM_R0_EVENTMASK_IX_0___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_EVENTMASK_IX_0___POR       0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_0__MASK___M   0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_0__MASK___S                 0
#define   UMAC_TQM_R0_EVENTMASK_IX_0___M         0xFFFFFFFF   
#define   UMAC_TQM_R0_EVENTMASK_IX_0___S                       0

#define UMAC_TQM_R0_EVENTMASK_IX_1                (0x00A3C4D0)
#define   UMAC_TQM_R0_EVENTMASK_IX_1___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_EVENTMASK_IX_1___POR       0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_1__MASK___M   0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_1__MASK___S                 0
#define   UMAC_TQM_R0_EVENTMASK_IX_1___M         0xFFFFFFFF   
#define   UMAC_TQM_R0_EVENTMASK_IX_1___S                       0

#define UMAC_TQM_R0_EVENTMASK_IX_2                (0x00A3C4D4)
#define   UMAC_TQM_R0_EVENTMASK_IX_2___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_EVENTMASK_IX_2___POR       0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_2__MASK___M   0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_2__MASK___S                 0
#define   UMAC_TQM_R0_EVENTMASK_IX_2___M         0xFFFFFFFF   
#define   UMAC_TQM_R0_EVENTMASK_IX_2___S                       0

#define UMAC_TQM_R0_EVENTMASK_IX_3                (0x00A3C4D8)
#define   UMAC_TQM_R0_EVENTMASK_IX_3___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_EVENTMASK_IX_3___POR       0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_3__MASK___M   0xFFFFFFFF
#define   UMAC_TQM_R0_EVENTMASK_IX_3__MASK___S                 0
#define   UMAC_TQM_R0_EVENTMASK_IX_3___M         0xFFFFFFFF   
#define   UMAC_TQM_R0_EVENTMASK_IX_3___S                       0

#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL     (0x00A3C4DC)
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define UMAC_TQM_R0_END_OF_TEST_CHECK             (0x00A3C4E0)
#define   UMAC_TQM_R0_END_OF_TEST_CHECK___RWC       QCSR_REG_RW    
#define   UMAC_TQM_R0_END_OF_TEST_CHECK___POR    0x00000000
#define   UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TQM_R0_END_OF_TEST_CHECK___M      0x00000001   
#define   UMAC_TQM_R0_END_OF_TEST_CHECK___S                    0

#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR          (0x00A3C4E4)
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR___RWC    QCSR_REG_RO    
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x00000
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x0001FFFF
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___S               0
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR___M   0x0001FFFF   
#define   UMAC_TQM_R0_INVALID_APB_ACC_ADDR___S                 0

#define UMAC_TQM_R0_SM_STATES_IX0                 (0x00A3C4E8)
#define   UMAC_TQM_R0_SM_STATES_IX0___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_SM_STATES_IX0___POR        0x00000000
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___M 0x1E000000
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___S              25
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___M 0x01E00000
#define   UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___S              21
#define   UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___M 0x00180000
#define   UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___S              19
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___M 0x00078000
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___S              15
#define   UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___M 0x00007C00
#define   UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___S              10
#define   UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___M 0x000003E0
#define   UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___S               5
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___M 0x0000001F
#define   UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___S               0
#define   UMAC_TQM_R0_SM_STATES_IX0___M          0x1FFFFFFF   
#define   UMAC_TQM_R0_SM_STATES_IX0___S                        0

#define UMAC_TQM_R0_SM_STATES_IX1                 (0x00A3C4EC)
#define   UMAC_TQM_R0_SM_STATES_IX1___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_SM_STATES_IX1___POR        0x00000000
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___M 0xC0000000
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___S              30
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___M 0x30000000
#define   UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___S              28
#define   UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___M 0x0F800000
#define   UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___S              23
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___M 0x007C0000
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___S              18
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___M 0x0003F000
#define   UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___S              12
#define   UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___M 0x00000E00
#define   UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___S               9
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___M 0x000001F0
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___S               4
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___M 0x0000000F
#define   UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___S               0
#define   UMAC_TQM_R0_SM_STATES_IX1___M          0xFFFFFFFF   
#define   UMAC_TQM_R0_SM_STATES_IX1___S                        0

#define UMAC_TQM_R0_SM_STATES_IX2                 (0x00A3C4F0)
#define   UMAC_TQM_R0_SM_STATES_IX2___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_SM_STATES_IX2___POR        0x00000000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___POR 0x00000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___M 0x80000000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___S              31
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___M 0x70000000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___S              28
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___M 0x0F000000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___S              24
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___M 0x00F00000
#define   UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___S              20
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___M 0x000C0000
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___S              18
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___M 0x0003FFFF
#define   UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___S               0
#define   UMAC_TQM_R0_SM_STATES_IX2___M          0xFFFFFFFF   
#define   UMAC_TQM_R0_SM_STATES_IX2___S                        0

#define UMAC_TQM_R0_SM_STATES_IX3                 (0x00A3C4F4)
#define   UMAC_TQM_R0_SM_STATES_IX3___RWC           QCSR_REG_RO    
#define   UMAC_TQM_R0_SM_STATES_IX3___POR        0x00000000
#define   UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___POR 0x00
#define   UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___POR 0x0
#define   UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___M 0x00000F80
#define   UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___S               7
#define   UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___M 0x00000060
#define   UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___S               5
#define   UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___M 0x0000001C
#define   UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___S               2
#define   UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___M 0x00000003
#define   UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___S               0
#define   UMAC_TQM_R0_SM_STATES_IX3___M          0x00000FFF   
#define   UMAC_TQM_R0_SM_STATES_IX3___S                        0

#define UMAC_TQM_R0_MISC_CFG                      (0x00A3C4F8)
#define   UMAC_TQM_R0_MISC_CFG___RWC                QCSR_REG_RW    
#define   UMAC_TQM_R0_MISC_CFG___POR             0x00006FE0
#define   UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___POR 0x1
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___POR 0x0
#define   UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___M 0x00800000
#define   UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___S              23
#define   UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___M 0x00400000
#define   UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___S              22
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___M 0x00200000
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___S              21
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___M 0x00100000
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___S              20
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___M 0x00080000
#define   UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___S              19
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___M 0x00040000
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___S              18
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___M 0x00020000
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___S              17
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___M 0x00010000
#define   UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___S              16
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___M 0x00008000
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___S              15
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___M 0x00004000
#define   UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___S              14
#define   UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___M 0x00002000
#define   UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___S              13
#define   UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___M 0x00001000
#define   UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___S              12
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___M 0x00000800
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___S              11
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___M 0x00000400
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___S              10
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___M 0x00000200
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___S               9
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___M 0x00000100
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___S               8
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___M 0x00000080
#define   UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___S               7
#define   UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___M 0x00000040
#define   UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___S               6
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___M 0x00000020
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___S               5
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___M 0x00000010
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___S               4
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___M 0x00000008
#define   UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___S               3
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___M 0x00000004
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___S               2
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___M 0x00000002
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___S               1
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___M 0x00000001
#define   UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___S               0
#define   UMAC_TQM_R0_MISC_CFG___M               0x00FFFFFF   
#define   UMAC_TQM_R0_MISC_CFG___S                             0

#define UMAC_TQM_R0_CLKGATE_CTRL                  (0x00A3C4FC)
#define   UMAC_TQM_R0_CLKGATE_CTRL___RWC            QCSR_REG_RW    
#define   UMAC_TQM_R0_CLKGATE_CTRL___POR         0x80000000
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___POR 0x1
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___POR 0x0
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___M 0x80000000
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___S              31
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___M 0x01000000
#define   UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___S              24
#define   UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___M 0x00040000
#define   UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___S              18
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___M 0x00020000
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___S              17
#define   UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___M 0x00010000
#define   UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___S              16
#define   UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___M 0x00008000
#define   UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___S              15
#define   UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___M 0x00004000
#define   UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___S              14
#define   UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___M 0x00002000
#define   UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___S              13
#define   UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___M 0x00001000
#define   UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___S              12
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___M 0x00000800
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___S              11
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___M 0x00000400
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___S              10
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___M 0x00000200
#define   UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___S               9
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___M 0x00000100
#define   UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___S               8
#define   UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___M 0x00000080
#define   UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___S               7
#define   UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___M 0x00000040
#define   UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___S               6
#define   UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___M 0x00000020
#define   UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___S               5
#define   UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___M 0x00000010
#define   UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___S               4
#define   UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___M 0x00000008
#define   UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___S               3
#define   UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___M 0x00000004
#define   UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___S               2
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___M 0x00000002
#define   UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___S               1
#define   UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___M 0x00000001
#define   UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___S               0
#define   UMAC_TQM_R0_CLKGATE_CTRL___M           0x8107FFFF   
#define   UMAC_TQM_R0_CLKGATE_CTRL___S                         0

#define UMAC_TQM_R0_FLUSH_CONTROL_0               (0x00A3C500)
#define   UMAC_TQM_R0_FLUSH_CONTROL_0___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R0_FLUSH_CONTROL_0___POR      0x00000000
#define   UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___POR 0x0
#define   UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___M 0x00000001
#define   UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___S               0
#define   UMAC_TQM_R0_FLUSH_CONTROL_0___M        0x00000001   
#define   UMAC_TQM_R0_FLUSH_CONTROL_0___S                      0

#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0  (0x00A3C50C)
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___POR 0x00000000
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___S               0
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___S               0

#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0  (0x00A3C510)
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___POR 0x00000000
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___POR 0x00
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___M 0x000000FF
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___S               0
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___M 0x000000FF   
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___S               0

#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0        (0x00A3C524)
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___RWC  QCSR_REG_RW    
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___POR 0x00000000
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___POR 0x00000000
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___S               0
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0      (0x00A3C530)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___POR 0x00000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___POR 0x000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___M 0x00FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1      (0x00A3C534)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___POR 0x00000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___POR 0x000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___M 0x00FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2      (0x00A3C538)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___POR 0x00000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___POR 0x000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___M 0x00FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0    (0x00A3C53C)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___POR 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___POR 0xFFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___M 0x80000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___S              31
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___M 0x40000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___S              30
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___M 0x20000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___S              29
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___M 0x10000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___S              28
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___M 0xF0FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1    (0x00A3C540)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___POR 0x00000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___POR 0x000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___M 0x80000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___S              31
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___M 0x40000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___S              30
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___M 0x20000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___S              29
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___M 0x10000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___S              28
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___M 0xF0FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2    (0x00A3C544)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___POR 0x00000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___POR 0x000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___M 0x80000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___S              31
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___M 0x40000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___S              30
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___M 0x20000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___S              29
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___M 0x10000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___S              28
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___M 0x00FFFFFF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___M 0xF0FFFFFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___S               0

#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD (0x00A3C548)
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___POR 0x00000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___POR 0x0
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___POR 0x0
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___POR 0x0
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___POR 0x0000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___M 0x80000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___S              31
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___M 0x40000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___S              30
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___M 0x20000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___S              29
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___M 0x10000000
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___S              28
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___M 0x03FFFFFF
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___S               0
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___M 0xF3FFFFFF   
#define   UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___S               0

#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL (0x00A3C54C)
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___POR 0x00FF0000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0FF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___POR 0x0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___POR 0x000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___M 0x80000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___S              31
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___M 0x40000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___S              30
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___M 0x20000000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___S              29
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___M 0x03FF0000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___S              16
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___M 0x00001000
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___S              12
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___M 0x00000800
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___S              11
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___M 0x00000400
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___S              10
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___M 0x000003FF
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___S               0
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___M 0xE3FF1FFF   
#define   UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___S               0

#define UMAC_TQM_R0_DESC_PTR_RELEASE              (0x00A3C550)
#define   UMAC_TQM_R0_DESC_PTR_RELEASE___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R0_DESC_PTR_RELEASE___POR     0x00001F40
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___POR 0x1F
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___POR 0x40
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___M 0x0000FF00
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___S               8
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___M 0x000000FF
#define   UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___S               0
#define   UMAC_TQM_R0_DESC_PTR_RELEASE___M       0x0000FFFF   
#define   UMAC_TQM_R0_DESC_PTR_RELEASE___S                     0

#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS (0x00A3C554)
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS (0x00A3C558)
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x0000
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFFE
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___S               1
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS (0x00A3C55C)
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS (0x00A3C560)
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS (0x00A3C564)
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___M 0x0000FFE1   
#define   UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS (0x00A3C568)
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS (0x00A3C56C)
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS (0x00A3C570)
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS (0x00A3C574)
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___POR 0x00000000
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___S               5
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___S               1
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___S               0
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___M 0x0000FFFF   
#define   UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___S               0

#define UMAC_TQM_R0_ERROR_STATUS_1                (0x00A3C578)
#define   UMAC_TQM_R0_ERROR_STATUS_1___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R0_ERROR_STATUS_1___POR       0x00000000
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___POR 0x0
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___M 0x00000080
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___S               7
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___M 0x00000040
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___S               6
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___M 0x00000020
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___S               5
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___M 0x00000010
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___S               4
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___M 0x00000008
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___S               3
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___M 0x00000004
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___S               2
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___M 0x00000002
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___S               1
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___M 0x00000001
#define   UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___S               0
#define   UMAC_TQM_R0_ERROR_STATUS_1___M         0x000000FF   
#define   UMAC_TQM_R0_ERROR_STATUS_1___S                       0

#define UMAC_TQM_R0_TLV_IF                        (0x00A3C57C)
#define   UMAC_TQM_R0_TLV_IF___RWC                  QCSR_REG_RW    
#define   UMAC_TQM_R0_TLV_IF___POR               0x00000000
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___POR 0x0
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___POR 0x0
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___POR 0x0
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___M 0x00000004
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___S               2
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___M 0x00000002
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___S               1
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___M 0x00000001
#define   UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___S               0
#define   UMAC_TQM_R0_TLV_IF___M                 0x00000007   
#define   UMAC_TQM_R0_TLV_IF___S                               0

#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP       (0x00A3C580)
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___POR 0x00000000
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___POR 0x00000000
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___M 0xFFFFFFFF
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___S               0
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___M 0xFFFFFFFF   
#define   UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___S               0

#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n(n) (0x00A3C584+0x4*(n))
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_nMIN 0    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_nMAX 2    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_ELEM 3    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___POR 0x00000000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___POR 0x0000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___POR 0x000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___M 0x0FFFF000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___S              12
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___M 0x00000FFF
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___S               0
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___M 0x0FFFFFFF   
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___S               0
#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0 (0x00A3C584)
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__MPDU_QUEUE_DEPTH___M 0x0FFFF000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__MPDU_QUEUE_DEPTH___S              12
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__SEQUENCE_NUMBER___M 0x00000FFF
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__SEQUENCE_NUMBER___S               0
#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1 (0x00A3C588)
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__MPDU_QUEUE_DEPTH___M 0x0FFFF000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__MPDU_QUEUE_DEPTH___S              12
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__SEQUENCE_NUMBER___M 0x00000FFF
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__SEQUENCE_NUMBER___S               0
#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2 (0x00A3C58C)
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2___RWC QCSR_REG_RO    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__MPDU_QUEUE_DEPTH___M 0x0FFFF000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__MPDU_QUEUE_DEPTH___S              12
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__SEQUENCE_NUMBER___M 0x00000FFF
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__SEQUENCE_NUMBER___S               0

#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0    (0x00A3C618)
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___POR 0x00000000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___POR 0x000000
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___POR 0x00
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___POR 0x0
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___M 0x7FFFFF80
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___S               7
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___M 0x0000007E
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___S               1
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___M 0x00000001
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___S               0
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___M 0x7FFFFFFF   
#define   UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___S               0

#define UMAC_TQM_R0_SPARE                         (0x00A3C74C)
#define   UMAC_TQM_R0_SPARE___RWC                   QCSR_REG_RW    
#define   UMAC_TQM_R0_SPARE___POR                0x00000000
#define   UMAC_TQM_R0_SPARE__SPAREBITS___POR     0x00000000
#define   UMAC_TQM_R0_SPARE__SPAREBITS___M       0xFFFFFFFF
#define   UMAC_TQM_R0_SPARE__SPAREBITS___S                     0
#define   UMAC_TQM_R0_SPARE___M                  0xFFFFFFFF   
#define   UMAC_TQM_R0_SPARE___S                                0

#define UMAC_TQM_R0_SPEAR                         (0x00A3C750)
#define   UMAC_TQM_R0_SPEAR___RWC                   QCSR_REG_RW    
#define   UMAC_TQM_R0_SPEAR___POR                0x00000000
#define   UMAC_TQM_R0_SPEAR__SPEAR___POR         0x00000000
#define   UMAC_TQM_R0_SPEAR__SPEAR___M           0xFFFFFFFF
#define   UMAC_TQM_R0_SPEAR__SPEAR___S                         0
#define   UMAC_TQM_R0_SPEAR___M                  0xFFFFFFFF   
#define   UMAC_TQM_R0_SPEAR___S                                0

#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH       (0x00A3C754)
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___RWC QCSR_REG_RW    
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___POR 0x00000001
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___POR 0x0
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___POR 0x0
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___POR 0x0
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___POR 0x0
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___POR 0x1
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___M 0x00000010
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___S               4
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___M 0x00000008
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___S               3
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___M 0x00000004
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___S               2
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___M 0x00000002
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___S               1
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___M 0x00000001
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___S               0
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___M 0x0000001F   
#define   UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL       (0x00A3E000)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___POR 0x00000800
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___POR 0x1
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___POR 0x0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___POR 0x0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___M 0x00000800
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___S              11
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___M 0x00000400
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___M 0x00000200
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___S               9
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___M 0x000001FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___M 0x00000FFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT     (0x00A3E004)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___M 0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___M 0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT    (0x00A3E008)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___POR 0x000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___M 0x00FFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___M 0x00FFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW (0x00A3E00C)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___M 0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___M 0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH (0x00A3E010)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___M 0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___M 0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM           (0x00A3E014)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___POR  0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___POR 0x0000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___M 0x01FFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___M    0x01FFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___S                  0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST     (0x00A3E018)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___M 0x0007FC00
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___M 0x000003FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___M 0x0007FFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1    (0x00A3E01C)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___M 0x0007FC00
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___M 0x000003FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___M 0x0007FFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2    (0x00A3E020)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___M 0x0007FC00
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___M 0x000003FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___M 0x0007FFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3    (0x00A3E024)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___M 0x0007FC00
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___M 0x000003FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___M 0x0007FFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW (0x00A3E028)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___M 0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH (0x00A3E02C)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___M 0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___S               0

#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER (0x00A3E030)
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___POR 0x000
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___M 0x000FFC00
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___S              10
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___M 0x000003FF
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___S               0
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___M 0x000FFFFF   
#define   UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___S               0

#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK   (0x00A3E034)
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001   
#define   UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___S               0

#define UMAC_TQM_R1_PREFETCH_BUF                  (0x00A3E038)
#define   UMAC_TQM_R1_PREFETCH_BUF___RWC            QCSR_REG_RW    
#define   UMAC_TQM_R1_PREFETCH_BUF___POR         0x00000000
#define   UMAC_TQM_R1_PREFETCH_BUF__ADDR___POR   0x000
#define   UMAC_TQM_R1_PREFETCH_BUF__ADDR___M     0x00000FFC
#define   UMAC_TQM_R1_PREFETCH_BUF__ADDR___S                   2
#define   UMAC_TQM_R1_PREFETCH_BUF___M           0x00000FFC   
#define   UMAC_TQM_R1_PREFETCH_BUF___S                         2

#define UMAC_TQM_R1_PREFETCH_BUF_DATA             (0x00A3E03C)
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA___POR    0x00000000
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___S               0
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA___M      0xFFFFFFFF   
#define   UMAC_TQM_R1_PREFETCH_BUF_DATA___S                    0

#define UMAC_TQM_R1_CACHE_BUF                     (0x00A3E040)
#define   UMAC_TQM_R1_CACHE_BUF___RWC               QCSR_REG_RW    
#define   UMAC_TQM_R1_CACHE_BUF___POR            0x00000000
#define   UMAC_TQM_R1_CACHE_BUF__ADDR___POR      0x0000
#define   UMAC_TQM_R1_CACHE_BUF__ADDR___M        0x0000FFFC
#define   UMAC_TQM_R1_CACHE_BUF__ADDR___S                      2
#define   UMAC_TQM_R1_CACHE_BUF___M              0x0000FFFC   
#define   UMAC_TQM_R1_CACHE_BUF___S                            2

#define UMAC_TQM_R1_CACHE_BUF_DATA                (0x00A3E044)
#define   UMAC_TQM_R1_CACHE_BUF_DATA___RWC          QCSR_REG_RO    
#define   UMAC_TQM_R1_CACHE_BUF_DATA___POR       0x00000000
#define   UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___POR 0x00000000
#define   UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___M  0xFFFFFFFF
#define   UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___S                0
#define   UMAC_TQM_R1_CACHE_BUF_DATA___M         0xFFFFFFFF   
#define   UMAC_TQM_R1_CACHE_BUF_DATA___S                       0

#define UMAC_TQM_R1_MISC_DEBUG_CTRL               (0x00A3E048)
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL___POR      0x00000000
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___POR 0x0
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___POR 0x0
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___M 0x00000002
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___S               1
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___M 0x00000001
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___S               0
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL___M        0x00000003   
#define   UMAC_TQM_R1_MISC_DEBUG_CTRL___S                      0

#define UMAC_TQM_R1_LOG                           (0x00A3E04C)
#define   UMAC_TQM_R1_LOG___RWC                     QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG___POR                  0x0FFFFFFF
#define   UMAC_TQM_R1_LOG__CURR_CMD_IDX___POR    0xF
#define   UMAC_TQM_R1_LOG__CURR_CMD_NUM___POR    0xFFFFFF
#define   UMAC_TQM_R1_LOG__CURR_CMD_IDX___M      0x0F000000
#define   UMAC_TQM_R1_LOG__CURR_CMD_IDX___S                   24
#define   UMAC_TQM_R1_LOG__CURR_CMD_NUM___M      0x00FFFFFF
#define   UMAC_TQM_R1_LOG__CURR_CMD_NUM___S                    0
#define   UMAC_TQM_R1_LOG___M                    0x0FFFFFFF   
#define   UMAC_TQM_R1_LOG___S                                  0

#define UMAC_TQM_R1_BANK_SM_STATES_IX0            (0x00A3E050)
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0___POR   0x00000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___M 0x1E000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___S              25
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___M 0x01E00000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___S              21
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___M 0x00180000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___S              19
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___M 0x00078000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___S              15
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___M 0x00007C00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___S              10
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___M 0x000003E0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___S               5
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___M 0x0000001F
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___S               0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0___M     0x1FFFFFFF   
#define   UMAC_TQM_R1_BANK_SM_STATES_IX0___S                   0

#define UMAC_TQM_R1_BANK_SM_STATES_IX1            (0x00A3E054)
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1___POR   0x00000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___M 0xC0000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___S              30
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___M 0x30000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___S              28
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___M 0x0F800000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___S              23
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___M 0x007C0000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___S              18
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___M 0x0003F000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___S              12
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___M 0x00000E00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___S               9
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___M 0x000001F0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___S               4
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___M 0x0000000F
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___S               0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1___M     0xFFFFFFFF   
#define   UMAC_TQM_R1_BANK_SM_STATES_IX1___S                   0

#define UMAC_TQM_R1_BANK_SM_STATES_IX2            (0x00A3E058)
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2___POR   0x00000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___POR 0x00000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___M 0x80000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___S              31
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___M 0x70000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___S              28
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___M 0x0F000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___S              24
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___M 0x00F00000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___S              20
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___M 0x000C0000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___S              18
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___M 0x0003FFFF
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___S               0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2___M     0xFFFFFFFF   
#define   UMAC_TQM_R1_BANK_SM_STATES_IX2___S                   0

#define UMAC_TQM_R1_BANK_SM_STATES_IX3            (0x00A3E05C)
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3___POR   0x00000000
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___POR 0x00
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___POR 0x0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___M 0x00000F80
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___S               7
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___M 0x00000060
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___S               5
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___M 0x0000001C
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___S               2
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___M 0x00000003
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___S               0
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3___M     0x00000FFF   
#define   UMAC_TQM_R1_BANK_SM_STATES_IX3___S                   0

#define UMAC_TQM_R1_CCMN_IDLE                     (0x00A3E060)
#define   UMAC_TQM_R1_CCMN_IDLE___RWC               QCSR_REG_RO    
#define   UMAC_TQM_R1_CCMN_IDLE___POR            0x00000000
#define   UMAC_TQM_R1_CCMN_IDLE__SOURCES___POR   0x00000000
#define   UMAC_TQM_R1_CCMN_IDLE__SOURCES___M     0xFFFFFFFF
#define   UMAC_TQM_R1_CCMN_IDLE__SOURCES___S                   0
#define   UMAC_TQM_R1_CCMN_IDLE___M              0xFFFFFFFF   
#define   UMAC_TQM_R1_CCMN_IDLE___S                            0

#define UMAC_TQM_R1_CURRENT_COMMAND               (0x00A3E064)
#define   UMAC_TQM_R1_CURRENT_COMMAND___RWC         QCSR_REG_RO    
#define   UMAC_TQM_R1_CURRENT_COMMAND___POR      0x00000000
#define   UMAC_TQM_R1_CURRENT_COMMAND__POINTER___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___POR 0x0
#define   UMAC_TQM_R1_CURRENT_COMMAND__POINTER___M 0xF0000000
#define   UMAC_TQM_R1_CURRENT_COMMAND__POINTER___S              28
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___M 0x0F000000
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___S              24
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___M 0x00F00000
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___S              20
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___M 0x000F0000
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___S              16
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___M 0x0000F000
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___S              12
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___M 0x00000F00
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___S               8
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___M 0x000000F0
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___S               4
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___M 0x0000000F
#define   UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___S               0
#define   UMAC_TQM_R1_CURRENT_COMMAND___M        0xFFFFFFFF   
#define   UMAC_TQM_R1_CURRENT_COMMAND___S                      0

#define UMAC_TQM_R1_LOG_ADD_MSDU                  (0x00A3E068)
#define   UMAC_TQM_R1_LOG_ADD_MSDU___RWC            QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_ADD_MSDU___POR         0x00FFFFFF
#define   UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___POR 0xFFFFFF
#define   UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___M 0x00FFFFFF
#define   UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___S               0
#define   UMAC_TQM_R1_LOG_ADD_MSDU___M           0x00FFFFFF   
#define   UMAC_TQM_R1_LOG_ADD_MSDU___S                         0

#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0             (0x00A3E06C)
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0___POR    0x00000000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___M 0x3FF00000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___S              20
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___M 0x000FFC00
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___S              10
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___M 0x000003FF
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___S               0
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0___M      0x3FFFFFFF   
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX0___S                    0

#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1             (0x00A3E070)
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1___POR    0x00000000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___M 0x3FF00000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___S              20
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___M 0x000FFC00
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___S              10
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___M 0x000003FF
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___S               0
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1___M      0x3FFFFFFF   
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX1___S                    0

#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2             (0x00A3E074)
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2___POR    0x00000000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___POR 0x0
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___M 0x00700000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___S              20
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___M 0x000FFC00
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___S              10
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___M 0x000003FF
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___S               0
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2___M      0x007FFFFF   
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX2___S                    0

#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3             (0x00A3E078)
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3___RWC       QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3___POR    0x00000000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___POR 0x000000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___POR 0x000
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___M 0xFFFFFC00
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___S              10
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___M 0x000003FF
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___S               0
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3___M      0xFFFFFFFF   
#define   UMAC_TQM_R1_LOG_TIMESTAMP_IX3___S                    0

#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0           (0x00A3E07C)
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0___POR  0x00000000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___POR 0x0000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___POR 0x0000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___M 0xFFFF0000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___S              16
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___M 0x0000FFFF
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___S               0
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0___M    0xFFFFFFFF   
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX0___S                  0

#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1           (0x00A3E080)
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1___RWC     QCSR_REG_RO    
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1___POR  0x00000000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___POR 0x0000
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___M 0x0000FFFF
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___S               0
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1___M    0x0000FFFF   
#define   UMAC_TQM_R1_WATCHDOG_STATUS_IX1___S                  0

#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH            (0x00A3E084)
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___POR   0x00000000
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___POR 0x00000000
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___M 0xFFFFFFFF
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___S               0
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___M     0xFFFFFFFF   
#define   UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___S                   0

#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH            (0x00A3E088)
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___RWC      QCSR_REG_RO    
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___POR   0x00000000
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___POR 0x00000000
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___M 0xFFFFFFFF
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___S               0
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___M     0xFFFFFFFF   
#define   UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___S                   0

#define UMAC_TQM_R2_TCL2TQM_RING_HP               (0x00A3F000)
#define   UMAC_TQM_R2_TCL2TQM_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R2_TCL2TQM_RING_HP___POR      0x00000000
#define   UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_TCL2TQM_RING_HP___M        0x0000FFFF   
#define   UMAC_TQM_R2_TCL2TQM_RING_HP___S                      0

#define UMAC_TQM_R2_TCL2TQM_RING_TP               (0x00A3F004)
#define   UMAC_TQM_R2_TCL2TQM_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R2_TCL2TQM_RING_TP___POR      0x00000000
#define   UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_TCL2TQM_RING_TP___M        0x0000FFFF   
#define   UMAC_TQM_R2_TCL2TQM_RING_TP___S                      0

#define UMAC_TQM_R2_SW2TQM_RING_HP                (0x00A3F008)
#define   UMAC_TQM_R2_SW2TQM_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_SW2TQM_RING_HP___POR       0x00000000
#define   UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_SW2TQM_RING_HP___M         0x0000FFFF   
#define   UMAC_TQM_R2_SW2TQM_RING_HP___S                       0

#define UMAC_TQM_R2_SW2TQM_RING_TP                (0x00A3F00C)
#define   UMAC_TQM_R2_SW2TQM_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_SW2TQM_RING_TP___POR       0x00000000
#define   UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_SW2TQM_RING_TP___M         0x0000FFFF   
#define   UMAC_TQM_R2_SW2TQM_RING_TP___S                       0

#define UMAC_TQM_R2_FW2TQM_RING_HP                (0x00A3F010)
#define   UMAC_TQM_R2_FW2TQM_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_FW2TQM_RING_HP___POR       0x00000000
#define   UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_FW2TQM_RING_HP___M         0x0000FFFF   
#define   UMAC_TQM_R2_FW2TQM_RING_HP___S                       0

#define UMAC_TQM_R2_FW2TQM_RING_TP                (0x00A3F014)
#define   UMAC_TQM_R2_FW2TQM_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_FW2TQM_RING_TP___POR       0x00000000
#define   UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_FW2TQM_RING_TP___M         0x0000FFFF   
#define   UMAC_TQM_R2_FW2TQM_RING_TP___S                       0

#define UMAC_TQM_R2_SW_CMD_RING_HP                (0x00A3F018)
#define   UMAC_TQM_R2_SW_CMD_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_SW_CMD_RING_HP___POR       0x00000000
#define   UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_SW_CMD_RING_HP___M         0x0000FFFF   
#define   UMAC_TQM_R2_SW_CMD_RING_HP___S                       0

#define UMAC_TQM_R2_SW_CMD_RING_TP                (0x00A3F01C)
#define   UMAC_TQM_R2_SW_CMD_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_TQM_R2_SW_CMD_RING_TP___POR       0x00000000
#define   UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_SW_CMD_RING_TP___M         0x0000FFFF   
#define   UMAC_TQM_R2_SW_CMD_RING_TP___S                       0

#define UMAC_TQM_R2_SW_CMD1_RING_HP               (0x00A3F020)
#define   UMAC_TQM_R2_SW_CMD1_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R2_SW_CMD1_RING_HP___POR      0x00000000
#define   UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_SW_CMD1_RING_HP___M        0x0000FFFF   
#define   UMAC_TQM_R2_SW_CMD1_RING_HP___S                      0

#define UMAC_TQM_R2_SW_CMD1_RING_TP               (0x00A3F024)
#define   UMAC_TQM_R2_SW_CMD1_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TQM_R2_SW_CMD1_RING_TP___POR      0x00000000
#define   UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_SW_CMD1_RING_TP___M        0x0000FFFF   
#define   UMAC_TQM_R2_SW_CMD1_RING_TP___S                      0

#define UMAC_TQM_R2_SCH2TQM0_RING_HP              (0x00A3F028)
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP___POR     0x00000000
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP___M       0x0000FFFF   
#define   UMAC_TQM_R2_SCH2TQM0_RING_HP___S                     0

#define UMAC_TQM_R2_SCH2TQM0_RING_TP              (0x00A3F02C)
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP___RWC        QCSR_REG_RW    
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP___POR     0x00000000
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP___M       0x0000FFFF   
#define   UMAC_TQM_R2_SCH2TQM0_RING_TP___S                     0

#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP          (0x00A3F040)
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___POR 0x00000000
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___M   0x0000FFFF   
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___S                 0

#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP          (0x00A3F044)
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___RWC    QCSR_REG_RW    
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___POR 0x00000000
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___M   0x0000FFFF   
#define   UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___S                 0

#define UMAC_TQM_R2_TQM_RELEASE_RING_HP           (0x00A3F048)
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP___POR  0x00000000
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP___M    0x0000FFFF   
#define   UMAC_TQM_R2_TQM_RELEASE_RING_HP___S                  0

#define UMAC_TQM_R2_TQM_RELEASE_RING_TP           (0x00A3F04C)
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP___POR  0x00000000
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP___M    0x0000FFFF   
#define   UMAC_TQM_R2_TQM_RELEASE_RING_TP___S                  0

#define UMAC_TQM_R2_TQM_STATUS_RING_HP            (0x00A3F050)
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP___RWC      QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP___POR   0x00000000
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP___M     0x0000FFFF   
#define   UMAC_TQM_R2_TQM_STATUS_RING_HP___S                   0

#define UMAC_TQM_R2_TQM_STATUS_RING_TP            (0x00A3F054)
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP___RWC      QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP___POR   0x00000000
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP___M     0x0000FFFF   
#define   UMAC_TQM_R2_TQM_STATUS_RING_TP___S                   0

#define UMAC_TQM_R2_TQM_STATUS1_RING_HP           (0x00A3F058)
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP___POR  0x00000000
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___S               0
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP___M    0x0000FFFF   
#define   UMAC_TQM_R2_TQM_STATUS1_RING_HP___S                  0

#define UMAC_TQM_R2_TQM_STATUS1_RING_TP           (0x00A3F05C)
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP___POR  0x00000000
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___S               0
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP___M    0x0000FFFF   
#define   UMAC_TQM_R2_TQM_STATUS1_RING_TP___S                  0

#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN            (0x00A40000)
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___RWC      QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___POR   0x002FFFE2
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___M 0x00200000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___S              21
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___M 0x00080000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___S              19
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___M 0x00040000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___S              18
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___M 0x00020000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___S              17
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___M 0x00010000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___S              16
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___M 0x00008000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___S              15
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___M 0x00004000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___S              14
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___M 0x00002000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___S              13
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___M 0x00001000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___S              12
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___M 0x00000800
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___S              11
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___M 0x00000400
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___S              10
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___M 0x00000200
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___S               9
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___M 0x00000100
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___S               8
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___M 0x00000080
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___S               7
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___M 0x00000040
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___S               6
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___M 0x00000020
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___S               5
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___M 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___S               1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___M     0x002FFFE2   
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___S                   1

#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE  (0x00A40004)
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___POR 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___POR 0x1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___M 0x00200000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___S              21
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___M 0x00080000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___S              19
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___M 0x00040000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___S              18
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___M 0x00020000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___S              17
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___M 0x00010000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___S              16
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___M 0x00008000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___S              15
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___M 0x00004000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___S              14
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___M 0x00002000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___S              13
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___M 0x00001000
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___S              12
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___M 0x00000800
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___S              11
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___M 0x00000400
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___S              10
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___M 0x00000100
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___S               8
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___M 0x00000080
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___S               7
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___M 0x00000040
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___S               6
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___M 0x00000020
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___S               5
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___M 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___S               1
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___M 0x002FFDE2   
#define   UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___S               1

#define UMAC_UMCMN_R0_UMRCM_SOFTRESET             (0x00A40008)
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET___RWC       QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET___POR    0x00000000
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___M 0x00000400
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___S              10
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___M 0x00000100
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___S               8
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___M 0x00000080
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___S               7
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___M 0x00000040
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___S               6
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___M 0x00000020
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___S               5
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___M 0x00000010
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___S               4
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___M  0x00000008
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___S                3
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___M 0x00000004
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___S               2
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___M 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___S               1
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___M 0x00000001
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___S               0
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET___M      0x000005FF   
#define   UMAC_UMCMN_R0_UMRCM_SOFTRESET___S                    0

#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET           (0x00A4000C)
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET___RWC     QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET___POR  0x00000000
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___M 0x00000020
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___S               5
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___M 0x00000010
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___S               4
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___M 0x00000008
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___S               3
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___M 0x00000004
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___S               2
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___M 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___S               1
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___M 0x00000001
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___S               0
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET___M    0x0000003F   
#define   UMAC_UMCMN_R0_UMRCM_CONFIGRESET___S                  0

#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE       (0x00A40010)
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___POR 0x00000000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___POR 0x0
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___M 0x00400000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___S              22
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___M 0x00080000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___S              19
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___M 0x00040000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___S              18
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___M 0x00020000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___S              17
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___M 0x00010000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___S              16
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___M 0x00008000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___S              15
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___M 0x00004000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___S              14
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___M 0x00002000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___S              13
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___M 0x00001000
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___S              12
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___M 0x00000800
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___S              11
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___M 0x00000400
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___S              10
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___M 0x00000100
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___S               8
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___M 0x00000080
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___S               7
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___M 0x00000040
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___S               6
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___M 0x00000020
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___S               5
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___M 0x00000002
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___S               1
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___M 0x004FFDE2   
#define   UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___S               1

#define UMAC_UMCMN_R0_UMAC_RTL_VERSION            (0x00A40014)
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION___RWC      QCSR_REG_RO    
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION___POR   0x00000000
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___POR 0x00000000
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___M 0xFFFFFFFF
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___S               0
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION___M     0xFFFFFFFF   
#define   UMAC_UMCMN_R0_UMAC_RTL_VERSION___S                   0

#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET        (0x00A40018)
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___RWC  QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___POR 0x00000000
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___POR 0x0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___POR 0x0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___POR 0x0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___POR 0x0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___POR 0x0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___M 0x00000010
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___S               4
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___M 0x00000008
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___S               3
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___M 0x00000004
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___S               2
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___M 0x00000002
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___S               1
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___M 0x00000001
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___S               0
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___M 0x0000001F   
#define   UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___S               0

#define UMAC_UMCMN_R0_CLK_GATE_DISABLE            (0x00A4001C)
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE___RWC      QCSR_REG_RW    
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE___POR   0x00000000
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___POR 0x0000000
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___POR 0x0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___M 0x40000000
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___S              30
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFF0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___S               4
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000008
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___S               3
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___M 0x00000004
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___S               2
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___M 0x00000002
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___S               1
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___M 0x00000001
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___S               0
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE___M     0xFFFFFFFF   
#define   UMAC_UMCMN_R0_CLK_GATE_DISABLE___S                   0

#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE          (0x00A40020)
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___RWC    QCSR_REG_RW    
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___POR 0x00000001
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___POR 0x1
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___M 0x0000000F
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___S               0
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___M   0x0000000F   
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___S                 0

#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN       (0x00A40024)
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___POR 0x00000001
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___POR 0x1
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___M 0x00000001
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___S               0
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___M 0x00000001   
#define   UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___S               0

#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0             (0x00A40028)
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___RWC       QCSR_REG_RW    
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___POR    0x00000000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___POR 0x000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___POR 0x0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___M 0x0FFF0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___S              16
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___M 0x0000FFFF
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___S               0
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___M      0x0FFFFFFF   
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___S                    0

#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1             (0x00A4002C)
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___RWC       QCSR_REG_RW    
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___POR    0x00000000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___POR 0x000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___POR 0x0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___M 0x0FFF0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___S              16
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___M 0x0000FFFF
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___S               0
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___M      0x0FFFFFFF   
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___S                    0

#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2             (0x00A40030)
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___RWC       QCSR_REG_RW    
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___POR    0x00000000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___POR 0x000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___POR 0x0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___M 0x0FFF0000
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___S              16
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___M 0x0000FFFF
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___S               0
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___M      0x0FFFFFFF   
#define   UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___S                    0

#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL       (0x00A40034)
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___POR 0x00000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___POR 0x0
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___M 0x20000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___S              29
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___M 0x10000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___S              28
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___M 0x08000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___S              27
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___M 0x04000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___S              26
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___M 0x02000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___S              25
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___M 0x01000000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___S              24
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___M 0x00800000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___S              23
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___M 0x00400000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___S              22
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___M 0x00200000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___S              21
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___M 0x00100000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___S              20
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___M 0x00080000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___S              19
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___M 0x00040000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___S              18
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___M 0x00020000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___S              17
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___M 0x00010000
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___S              16
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___M 0x3FFF0000   
#define   UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___S              16

#define UMAC_UMCMN_R0_ISR_P                       (0x00A40038)
#define   UMAC_UMCMN_R0_ISR_P___RWC                 QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_P___POR              0x00000000
#define   UMAC_UMCMN_R0_ISR_P__GXI___POR         0x0
#define   UMAC_UMCMN_R0_ISR_P__TQM2___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__TQM1___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__TQM0___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__TCL1___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__TCL0___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__REO4___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__REO3___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__REO2___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__REO1___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__REO0___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__WBM2___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__WBM1___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__WBM0___POR        0x0
#define   UMAC_UMCMN_R0_ISR_P__MEM___POR         0x0
#define   UMAC_UMCMN_R0_ISR_P__CXC___POR         0x0
#define   UMAC_UMCMN_R0_ISR_P__APB___POR         0x0
#define   UMAC_UMCMN_R0_ISR_P__GXI___M           0x00010000
#define   UMAC_UMCMN_R0_ISR_P__GXI___S                        16
#define   UMAC_UMCMN_R0_ISR_P__TQM2___M          0x00008000
#define   UMAC_UMCMN_R0_ISR_P__TQM2___S                       15
#define   UMAC_UMCMN_R0_ISR_P__TQM1___M          0x00004000
#define   UMAC_UMCMN_R0_ISR_P__TQM1___S                       14
#define   UMAC_UMCMN_R0_ISR_P__TQM0___M          0x00002000
#define   UMAC_UMCMN_R0_ISR_P__TQM0___S                       13
#define   UMAC_UMCMN_R0_ISR_P__TCL1___M          0x00001000
#define   UMAC_UMCMN_R0_ISR_P__TCL1___S                       12
#define   UMAC_UMCMN_R0_ISR_P__TCL0___M          0x00000800
#define   UMAC_UMCMN_R0_ISR_P__TCL0___S                       11
#define   UMAC_UMCMN_R0_ISR_P__REO4___M          0x00000400
#define   UMAC_UMCMN_R0_ISR_P__REO4___S                       10
#define   UMAC_UMCMN_R0_ISR_P__REO3___M          0x00000200
#define   UMAC_UMCMN_R0_ISR_P__REO3___S                        9
#define   UMAC_UMCMN_R0_ISR_P__REO2___M          0x00000100
#define   UMAC_UMCMN_R0_ISR_P__REO2___S                        8
#define   UMAC_UMCMN_R0_ISR_P__REO1___M          0x00000080
#define   UMAC_UMCMN_R0_ISR_P__REO1___S                        7
#define   UMAC_UMCMN_R0_ISR_P__REO0___M          0x00000040
#define   UMAC_UMCMN_R0_ISR_P__REO0___S                        6
#define   UMAC_UMCMN_R0_ISR_P__WBM2___M          0x00000020
#define   UMAC_UMCMN_R0_ISR_P__WBM2___S                        5
#define   UMAC_UMCMN_R0_ISR_P__WBM1___M          0x00000010
#define   UMAC_UMCMN_R0_ISR_P__WBM1___S                        4
#define   UMAC_UMCMN_R0_ISR_P__WBM0___M          0x00000008
#define   UMAC_UMCMN_R0_ISR_P__WBM0___S                        3
#define   UMAC_UMCMN_R0_ISR_P__MEM___M           0x00000004
#define   UMAC_UMCMN_R0_ISR_P__MEM___S                         2
#define   UMAC_UMCMN_R0_ISR_P__CXC___M           0x00000002
#define   UMAC_UMCMN_R0_ISR_P__CXC___S                         1
#define   UMAC_UMCMN_R0_ISR_P__APB___M           0x00000001
#define   UMAC_UMCMN_R0_ISR_P__APB___S                         0
#define   UMAC_UMCMN_R0_ISR_P___M                0x0001FFFF   
#define   UMAC_UMCMN_R0_ISR_P___S                              0

#define UMAC_UMCMN_R0_ISR_S0                      (0x00A4003C)
#define   UMAC_UMCMN_R0_ISR_S0___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S0___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___M 0x00800000
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___S              23
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___M 0x00400000
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___S              22
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000
#define   UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___S              21
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___M 0x00100000
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___S              20
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___M 0x00080000
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___S              19
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___S              18
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___S              17
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___S              16
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___S              15
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___S              14
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___S              13
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___S              12
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___S              11
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___S              10
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___S               9
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___S               8
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___S               7
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___S               6
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___S               5
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___S               4
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___S               3
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___S               2
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___S               1
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___S               0
#define   UMAC_UMCMN_R0_ISR_S0___M               0x00FFFFFF   
#define   UMAC_UMCMN_R0_ISR_S0___S                             0

#define UMAC_UMCMN_R0_ISR_S1                      (0x00A40040)
#define   UMAC_UMCMN_R0_ISR_S1___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S1___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S1__CE_WDG___POR     0x0
#define   UMAC_UMCMN_R0_ISR_S1__CE_ERR___POR     0x0
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___POR  0x0
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S1__MCIM___POR       0x0
#define   UMAC_UMCMN_R0_ISR_S1__SMH___POR        0x0
#define   UMAC_UMCMN_R0_ISR_S1__PMH___POR        0x0
#define   UMAC_UMCMN_R0_ISR_S1__LMH___POR        0x0
#define   UMAC_UMCMN_R0_ISR_S1__BMH___POR        0x0
#define   UMAC_UMCMN_R0_ISR_S1__CE_WDG___M       0x00020000
#define   UMAC_UMCMN_R0_ISR_S1__CE_WDG___S                    17
#define   UMAC_UMCMN_R0_ISR_S1__CE_ERR___M       0x00010000
#define   UMAC_UMCMN_R0_ISR_S1__CE_ERR___S                    16
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___M    0x00000040
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___S                  6
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___M  0x00000020
#define   UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___S                5
#define   UMAC_UMCMN_R0_ISR_S1__MCIM___M         0x00000010
#define   UMAC_UMCMN_R0_ISR_S1__MCIM___S                       4
#define   UMAC_UMCMN_R0_ISR_S1__SMH___M          0x00000008
#define   UMAC_UMCMN_R0_ISR_S1__SMH___S                        3
#define   UMAC_UMCMN_R0_ISR_S1__PMH___M          0x00000004
#define   UMAC_UMCMN_R0_ISR_S1__PMH___S                        2
#define   UMAC_UMCMN_R0_ISR_S1__LMH___M          0x00000002
#define   UMAC_UMCMN_R0_ISR_S1__LMH___S                        1
#define   UMAC_UMCMN_R0_ISR_S1__BMH___M          0x00000001
#define   UMAC_UMCMN_R0_ISR_S1__BMH___S                        0
#define   UMAC_UMCMN_R0_ISR_S1___M               0x0003007F   
#define   UMAC_UMCMN_R0_ISR_S1___S                             0

#define UMAC_UMCMN_R0_ISR_S2                      (0x00A40044)
#define   UMAC_UMCMN_R0_ISR_S2___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S2___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___S               1
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___S               0
#define   UMAC_UMCMN_R0_ISR_S2___M               0x0000000F   
#define   UMAC_UMCMN_R0_ISR_S2___S                             0

#define UMAC_UMCMN_R0_ISR_S3                      (0x00A40048)
#define   UMAC_UMCMN_R0_ISR_S3___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S3___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___POR 0x00
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___M 0xFF000000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___S              24
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___M 0x00380000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___S              19
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___S              18
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___S              17
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___S              15
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___S              13
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___S              12
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___S              11
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___S              10
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___S               9
#define   UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___S               8
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___S               7
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___S               6
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___S               5
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___S               4
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___S               3
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___S               2
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___S               1
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___S               0
#define   UMAC_UMCMN_R0_ISR_S3___M               0xFF3FFFFF   
#define   UMAC_UMCMN_R0_ISR_S3___S                             0

#define UMAC_UMCMN_R0_ISR_S4                      (0x00A4004C)
#define   UMAC_UMCMN_R0_ISR_S4___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S4___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___M 0x10000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___S              28
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___M 0x08000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___S              27
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___M 0x04000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___S              26
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___M 0x02000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___S              25
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___M 0x01000000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___S              24
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___M 0x00800000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___S              23
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___M 0x00400000
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___S              22
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___S              21
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___S              20
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___S              19
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___S              18
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___S              17
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___S              12
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S4___M               0x1FFFFFFF   
#define   UMAC_UMCMN_R0_ISR_S4___S                             0

#define UMAC_UMCMN_R0_ISR_S5                      (0x00A40050)
#define   UMAC_UMCMN_R0_ISR_S5___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S5___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___M 0x10000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___S              28
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___M 0x08000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___S              27
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___M 0x04000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___S              26
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___M 0x02000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___S              25
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___M 0x01000000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___S              24
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___M 0x00800000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___S              23
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___M 0x00400000
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___S              22
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___S              21
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___S              20
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___S              19
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___S              18
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___S              17
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S5___M               0x1FFFFFFF   
#define   UMAC_UMCMN_R0_ISR_S5___S                             0

#define UMAC_UMCMN_R0_ISR_S6                      (0x00A40054)
#define   UMAC_UMCMN_R0_ISR_S6___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S6___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___S              15
#define   UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___S              14
#define   UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___S              13
#define   UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___S              12
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___S              11
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___S              10
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___S               9
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___S               8
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___S               7
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___S               6
#define   UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___S               5
#define   UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___S               4
#define   UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___S               3
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___S               2
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___S               1
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___S               0
#define   UMAC_UMCMN_R0_ISR_S6___M               0x0000FFFF   
#define   UMAC_UMCMN_R0_ISR_S6___S                             0

#define UMAC_UMCMN_R0_ISR_S7                      (0x00A40058)
#define   UMAC_UMCMN_R0_ISR_S7___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S7___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___POR 0x0000
#define   UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___M 0xFFFF0000
#define   UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___S              16
#define   UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___M 0x0000000F
#define   UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___S               0
#define   UMAC_UMCMN_R0_ISR_S7___M               0xFFFF000F   
#define   UMAC_UMCMN_R0_ISR_S7___S                             0

#define UMAC_UMCMN_R0_ISR_S8                      (0x00A4005C)
#define   UMAC_UMCMN_R0_ISR_S8___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S8___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___POR 0x000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___M 0xFFF00000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___S              20
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___M 0x00080000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___S              19
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___S              18
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___S              17
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___S              16
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___S              15
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___S              14
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___S              13
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___S              12
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___S              10
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___S               9
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___S               8
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___S               7
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___S               6
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___S               5
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___S               4
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___S               3
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___S               2
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___S               1
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___S               0
#define   UMAC_UMCMN_R0_ISR_S8___M               0xFFFFFFFF   
#define   UMAC_UMCMN_R0_ISR_S8___S                             0

#define UMAC_UMCMN_R0_ISR_S9                      (0x00A40060)
#define   UMAC_UMCMN_R0_ISR_S9___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S9___POR             0x00000000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___POR 0x000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___M 0x00FF8000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___S              14
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___S              13
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___S              12
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___S              11
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___S              10
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___S               9
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___S               8
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___S               7
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___S               6
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___S               5
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___S               4
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___S               3
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___S               2
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___S               1
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___S               0
#define   UMAC_UMCMN_R0_ISR_S9___M               0x00FFFFFF   
#define   UMAC_UMCMN_R0_ISR_S9___S                             0

#define UMAC_UMCMN_R0_ISR_S10                     (0x00A40064)
#define   UMAC_UMCMN_R0_ISR_S10___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S10___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___M 0x0000C000
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___S              14
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S10___M              0x0000FFFF   
#define   UMAC_UMCMN_R0_ISR_S10___S                            0

#define UMAC_UMCMN_R0_ISR_S11                     (0x00A40068)
#define   UMAC_UMCMN_R0_ISR_S11___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S11___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___S              17
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S11___M              0x0003FFFF   
#define   UMAC_UMCMN_R0_ISR_S11___S                            0

#define UMAC_UMCMN_R0_ISR_S12                     (0x00A4006C)
#define   UMAC_UMCMN_R0_ISR_S12___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S12___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___S              13
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___S              12
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___S              11
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___S              10
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___S               6
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S12___M              0x00003FFF   
#define   UMAC_UMCMN_R0_ISR_S12___S                            0

#define UMAC_UMCMN_R0_ISR_S13                     (0x00A40070)
#define   UMAC_UMCMN_R0_ISR_S13___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S13___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___S              21
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___S              20
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___S              19
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___S              18
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___S              17
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___S              12
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___S               8
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___S               4
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S13___M              0x003FFFFF   
#define   UMAC_UMCMN_R0_ISR_S13___S                            0

#define UMAC_UMCMN_R0_ISR_S14                     (0x00A40074)
#define   UMAC_UMCMN_R0_ISR_S14___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S14___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___POR 0x000
#define   UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___POR 0x00
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___M 0x0FFF0000
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___S              16
#define   UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___S              11
#define   UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___M 0x000000FF
#define   UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___S               0
#define   UMAC_UMCMN_R0_ISR_S14___M              0x0FFF0CFF   
#define   UMAC_UMCMN_R0_ISR_S14___S                            0

#define UMAC_UMCMN_R0_ISR_S15                     (0x00A40078)
#define   UMAC_UMCMN_R0_ISR_S15___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S15___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___M 0x00010000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___S              16
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___S              15
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___S              14
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___S              13
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___S              12
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___S              11
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___S              10
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___S               9
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___S               8
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___S               7
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___S               6
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___S               5
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___S               4
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___S               3
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___S               0
#define   UMAC_UMCMN_R0_ISR_S15___M              0x0001FFFF   
#define   UMAC_UMCMN_R0_ISR_S15___S                            0

#define UMAC_UMCMN_R0_ISR_S16                     (0x00A4007C)
#define   UMAC_UMCMN_R0_ISR_S16___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_ISR_S16___POR            0x00000000
#define   UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___POR 0x0000
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___M 0xFFFF0000
#define   UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___S              16
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___S              15
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___S              14
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___S              13
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___M 0x00001000
#define   UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___S              12
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___S              11
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___S              10
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___S               9
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___M 0x00000100
#define   UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___S               8
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___S               7
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___S               6
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___S               5
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___M 0x00000010
#define   UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___S               4
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___S               3
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___S               2
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___S               1
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___M 0x00000001
#define   UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___S               0
#define   UMAC_UMCMN_R0_ISR_S16___M              0xFFFFFFFF   
#define   UMAC_UMCMN_R0_ISR_S16___S                            0

#define UMAC_UMCMN_R0_IMR_P                       (0x00A40080)
#define   UMAC_UMCMN_R0_IMR_P___RWC                 QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_P___POR              0x00000000
#define   UMAC_UMCMN_R0_IMR_P__GXI___POR         0x0
#define   UMAC_UMCMN_R0_IMR_P__TQM2___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__TQM1___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__TQM0___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__TCL1___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__TCL0___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__REO4___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__REO3___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__REO2___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__REO1___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__REO0___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__WBM2___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__WBM1___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__WBM0___POR        0x0
#define   UMAC_UMCMN_R0_IMR_P__MEM___POR         0x0
#define   UMAC_UMCMN_R0_IMR_P__CXC___POR         0x0
#define   UMAC_UMCMN_R0_IMR_P__APB___POR         0x0
#define   UMAC_UMCMN_R0_IMR_P__GXI___M           0x00010000
#define   UMAC_UMCMN_R0_IMR_P__GXI___S                        16
#define   UMAC_UMCMN_R0_IMR_P__TQM2___M          0x00008000
#define   UMAC_UMCMN_R0_IMR_P__TQM2___S                       15
#define   UMAC_UMCMN_R0_IMR_P__TQM1___M          0x00004000
#define   UMAC_UMCMN_R0_IMR_P__TQM1___S                       14
#define   UMAC_UMCMN_R0_IMR_P__TQM0___M          0x00002000
#define   UMAC_UMCMN_R0_IMR_P__TQM0___S                       13
#define   UMAC_UMCMN_R0_IMR_P__TCL1___M          0x00001000
#define   UMAC_UMCMN_R0_IMR_P__TCL1___S                       12
#define   UMAC_UMCMN_R0_IMR_P__TCL0___M          0x00000800
#define   UMAC_UMCMN_R0_IMR_P__TCL0___S                       11
#define   UMAC_UMCMN_R0_IMR_P__REO4___M          0x00000400
#define   UMAC_UMCMN_R0_IMR_P__REO4___S                       10
#define   UMAC_UMCMN_R0_IMR_P__REO3___M          0x00000200
#define   UMAC_UMCMN_R0_IMR_P__REO3___S                        9
#define   UMAC_UMCMN_R0_IMR_P__REO2___M          0x00000100
#define   UMAC_UMCMN_R0_IMR_P__REO2___S                        8
#define   UMAC_UMCMN_R0_IMR_P__REO1___M          0x00000080
#define   UMAC_UMCMN_R0_IMR_P__REO1___S                        7
#define   UMAC_UMCMN_R0_IMR_P__REO0___M          0x00000040
#define   UMAC_UMCMN_R0_IMR_P__REO0___S                        6
#define   UMAC_UMCMN_R0_IMR_P__WBM2___M          0x00000020
#define   UMAC_UMCMN_R0_IMR_P__WBM2___S                        5
#define   UMAC_UMCMN_R0_IMR_P__WBM1___M          0x00000010
#define   UMAC_UMCMN_R0_IMR_P__WBM1___S                        4
#define   UMAC_UMCMN_R0_IMR_P__WBM0___M          0x00000008
#define   UMAC_UMCMN_R0_IMR_P__WBM0___S                        3
#define   UMAC_UMCMN_R0_IMR_P__MEM___M           0x00000004
#define   UMAC_UMCMN_R0_IMR_P__MEM___S                         2
#define   UMAC_UMCMN_R0_IMR_P__CXC___M           0x00000002
#define   UMAC_UMCMN_R0_IMR_P__CXC___S                         1
#define   UMAC_UMCMN_R0_IMR_P__APB___M           0x00000001
#define   UMAC_UMCMN_R0_IMR_P__APB___S                         0
#define   UMAC_UMCMN_R0_IMR_P___M                0x0001FFFF   
#define   UMAC_UMCMN_R0_IMR_P___S                              0

#define UMAC_UMCMN_R0_IMR_S0                      (0x00A40084)
#define   UMAC_UMCMN_R0_IMR_S0___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S0___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___M 0x00800000
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___S              23
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___M 0x00400000
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___S              22
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000
#define   UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___S              21
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___M 0x00100000
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___S              20
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___M 0x00080000
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___S              19
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___S              18
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___S              17
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___S              16
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___S              15
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___S              14
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___S              13
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___S              12
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___S              11
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___S              10
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___S               9
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___S               8
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___S               7
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___S               6
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___S               5
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___S               4
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___S               3
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___S               2
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___S               1
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___S               0
#define   UMAC_UMCMN_R0_IMR_S0___M               0x00FFFFFF   
#define   UMAC_UMCMN_R0_IMR_S0___S                             0

#define UMAC_UMCMN_R0_IMR_S1                      (0x00A40088)
#define   UMAC_UMCMN_R0_IMR_S1___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S1___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S1__CE_WDG___POR     0x0
#define   UMAC_UMCMN_R0_IMR_S1__CE_ERR___POR     0x0
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___POR  0x0
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S1__MCIM___POR       0x0
#define   UMAC_UMCMN_R0_IMR_S1__SMH___POR        0x0
#define   UMAC_UMCMN_R0_IMR_S1__PMH___POR        0x0
#define   UMAC_UMCMN_R0_IMR_S1__LMH___POR        0x0
#define   UMAC_UMCMN_R0_IMR_S1__BMH___POR        0x0
#define   UMAC_UMCMN_R0_IMR_S1__CE_WDG___M       0x00020000
#define   UMAC_UMCMN_R0_IMR_S1__CE_WDG___S                    17
#define   UMAC_UMCMN_R0_IMR_S1__CE_ERR___M       0x00010000
#define   UMAC_UMCMN_R0_IMR_S1__CE_ERR___S                    16
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___M    0x00000040
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___S                  6
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___M  0x00000020
#define   UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___S                5
#define   UMAC_UMCMN_R0_IMR_S1__MCIM___M         0x00000010
#define   UMAC_UMCMN_R0_IMR_S1__MCIM___S                       4
#define   UMAC_UMCMN_R0_IMR_S1__SMH___M          0x00000008
#define   UMAC_UMCMN_R0_IMR_S1__SMH___S                        3
#define   UMAC_UMCMN_R0_IMR_S1__PMH___M          0x00000004
#define   UMAC_UMCMN_R0_IMR_S1__PMH___S                        2
#define   UMAC_UMCMN_R0_IMR_S1__LMH___M          0x00000002
#define   UMAC_UMCMN_R0_IMR_S1__LMH___S                        1
#define   UMAC_UMCMN_R0_IMR_S1__BMH___M          0x00000001
#define   UMAC_UMCMN_R0_IMR_S1__BMH___S                        0
#define   UMAC_UMCMN_R0_IMR_S1___M               0x0003007F   
#define   UMAC_UMCMN_R0_IMR_S1___S                             0

#define UMAC_UMCMN_R0_IMR_S2                      (0x00A4008C)
#define   UMAC_UMCMN_R0_IMR_S2___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S2___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___S               1
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___S               0
#define   UMAC_UMCMN_R0_IMR_S2___M               0x0000000F   
#define   UMAC_UMCMN_R0_IMR_S2___S                             0

#define UMAC_UMCMN_R0_IMR_S3                      (0x00A40090)
#define   UMAC_UMCMN_R0_IMR_S3___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S3___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___POR 0x00
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___M 0xFF000000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___S              24
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___M 0x00380000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___S              19
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___S              18
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___S              17
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___S              15
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___S              13
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___S              12
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___S              11
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___S              10
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___S               9
#define   UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___S               8
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___S               7
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___S               6
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___S               5
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___S               4
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___S               3
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___S               2
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___S               1
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___S               0
#define   UMAC_UMCMN_R0_IMR_S3___M               0xFF3FFFFF   
#define   UMAC_UMCMN_R0_IMR_S3___S                             0

#define UMAC_UMCMN_R0_IMR_S4                      (0x00A40094)
#define   UMAC_UMCMN_R0_IMR_S4___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S4___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___M 0x10000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___S              28
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___M 0x08000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___S              27
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___M 0x04000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___S              26
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___M 0x02000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___S              25
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___M 0x01000000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___S              24
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___M 0x00800000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___S              23
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___M 0x00400000
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___S              22
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___S              21
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___S              20
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___S              19
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___S              18
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___S              17
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___S              12
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S4___M               0x1FFFFFFF   
#define   UMAC_UMCMN_R0_IMR_S4___S                             0

#define UMAC_UMCMN_R0_IMR_S5                      (0x00A40098)
#define   UMAC_UMCMN_R0_IMR_S5___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S5___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___M 0x10000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___S              28
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___M 0x08000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___S              27
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___M 0x04000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___S              26
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___M 0x02000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___S              25
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___M 0x01000000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___S              24
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___M 0x00800000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___S              23
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___M 0x00400000
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___S              22
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___S              21
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___S              20
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___S              19
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___S              18
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___S              17
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S5___M               0x1FFFFFFF   
#define   UMAC_UMCMN_R0_IMR_S5___S                             0

#define UMAC_UMCMN_R0_IMR_S6                      (0x00A4009C)
#define   UMAC_UMCMN_R0_IMR_S6___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S6___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___S              15
#define   UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___S              14
#define   UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___S              13
#define   UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___S              12
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___S              11
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___S              10
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___S               9
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___S               8
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___S               7
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___S               6
#define   UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___S               5
#define   UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___S               4
#define   UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___S               3
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___S               2
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___S               1
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___S               0
#define   UMAC_UMCMN_R0_IMR_S6___M               0x0000FFFF   
#define   UMAC_UMCMN_R0_IMR_S6___S                             0

#define UMAC_UMCMN_R0_IMR_S7                      (0x00A400A0)
#define   UMAC_UMCMN_R0_IMR_S7___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S7___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___POR 0x0000
#define   UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___M 0xFFFF0000
#define   UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___S              16
#define   UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___M 0x0000000F
#define   UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___S               0
#define   UMAC_UMCMN_R0_IMR_S7___M               0xFFFF000F   
#define   UMAC_UMCMN_R0_IMR_S7___S                             0

#define UMAC_UMCMN_R0_IMR_S8                      (0x00A400A4)
#define   UMAC_UMCMN_R0_IMR_S8___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S8___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___POR 0x000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___M 0xFFF00000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___S              20
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___M 0x00080000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___S              19
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___S              18
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___S              17
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___S              16
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___S              15
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___S              14
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___S              13
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___S              12
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___S              10
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___S               9
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___S               8
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___S               7
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___S               6
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___S               5
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___S               4
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___S               3
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___S               2
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___S               1
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___S               0
#define   UMAC_UMCMN_R0_IMR_S8___M               0xFFFFFFFF   
#define   UMAC_UMCMN_R0_IMR_S8___S                             0

#define UMAC_UMCMN_R0_IMR_S9                      (0x00A400A8)
#define   UMAC_UMCMN_R0_IMR_S9___RWC                QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S9___POR             0x00000000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___POR 0x000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___M 0x00FF8000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___S              14
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___S              13
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___S              12
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___S              11
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___S              10
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___S               9
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___S               8
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___S               7
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___S               6
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___S               5
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___S               4
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___S               3
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___S               2
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___S               1
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___S               0
#define   UMAC_UMCMN_R0_IMR_S9___M               0x00FFFFFF   
#define   UMAC_UMCMN_R0_IMR_S9___S                             0

#define UMAC_UMCMN_R0_IMR_S10                     (0x00A400AC)
#define   UMAC_UMCMN_R0_IMR_S10___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S10___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___M 0x0000C000
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___S              14
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S10___M              0x0000FFFF   
#define   UMAC_UMCMN_R0_IMR_S10___S                            0

#define UMAC_UMCMN_R0_IMR_S11                     (0x00A400B0)
#define   UMAC_UMCMN_R0_IMR_S11___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S11___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___S              17
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___S              12
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S11___M              0x0003FFFF   
#define   UMAC_UMCMN_R0_IMR_S11___S                            0

#define UMAC_UMCMN_R0_IMR_S12                     (0x00A400B4)
#define   UMAC_UMCMN_R0_IMR_S12___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S12___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___S              13
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___S              12
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___S              11
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___S              10
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___S               6
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S12___M              0x00003FFF   
#define   UMAC_UMCMN_R0_IMR_S12___S                            0

#define UMAC_UMCMN_R0_IMR_S13                     (0x00A400B8)
#define   UMAC_UMCMN_R0_IMR_S13___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S13___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___M 0x00200000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___S              21
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___M 0x00100000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___S              20
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___M 0x00080000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___S              19
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___M 0x00040000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___S              18
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___M 0x00020000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___S              17
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___S              12
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___S               8
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___S               4
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S13___M              0x003FFFFF   
#define   UMAC_UMCMN_R0_IMR_S13___S                            0

#define UMAC_UMCMN_R0_IMR_S14                     (0x00A400BC)
#define   UMAC_UMCMN_R0_IMR_S14___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S14___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___POR 0x000
#define   UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___POR 0x00
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___M 0x0FFF0000
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___S              16
#define   UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___S              11
#define   UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___M 0x000000FF
#define   UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___S               0
#define   UMAC_UMCMN_R0_IMR_S14___M              0x0FFF0CFF   
#define   UMAC_UMCMN_R0_IMR_S14___S                            0

#define UMAC_UMCMN_R0_IMR_S15                     (0x00A400C0)
#define   UMAC_UMCMN_R0_IMR_S15___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S15___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___M 0x00010000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___S              16
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___S              15
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___S              14
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___S              13
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___S              12
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___S              11
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___S              10
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___S               9
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___S               8
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___S               7
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___S               6
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___S               5
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___S               4
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___S               3
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___S               0
#define   UMAC_UMCMN_R0_IMR_S15___M              0x0001FFFF   
#define   UMAC_UMCMN_R0_IMR_S15___S                            0

#define UMAC_UMCMN_R0_IMR_S16                     (0x00A400C4)
#define   UMAC_UMCMN_R0_IMR_S16___RWC               QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IMR_S16___POR            0x00000000
#define   UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___POR 0x0000
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___POR 0x0
#define   UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___M 0xFFFF0000
#define   UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___S              16
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___S              15
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___S              14
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___S              13
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___M 0x00001000
#define   UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___S              12
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___S              11
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___S              10
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___M 0x00000200
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___S               9
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___M 0x00000100
#define   UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___S               8
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___M 0x00000080
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___S               7
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___M 0x00000040
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___S               6
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___M 0x00000020
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___S               5
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___M 0x00000010
#define   UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___S               4
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___M 0x00000008
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___S               3
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___M 0x00000004
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___S               2
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___M 0x00000002
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___S               1
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___M 0x00000001
#define   UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___S               0
#define   UMAC_UMCMN_R0_IMR_S16___M              0xFFFFFFFF   
#define   UMAC_UMCMN_R0_IMR_S16___S                            0

#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN              (0x00A400C8)
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN___RWC        QCSR_REG_RW    
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN___POR     0x00000000
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___POR 0x0
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___M  0x00000001
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___S                0
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN___M       0x00000001   
#define   UMAC_UMCMN_R0_WOCLR_ISR_P_EN___S                     0

#define UMAC_UMCMN_R0_UMAC_REVISION               (0x00A400CC)
#define   UMAC_UMCMN_R0_UMAC_REVISION___RWC         QCSR_REG_RO    
#define   UMAC_UMCMN_R0_UMAC_REVISION___POR      0x10080000
#define   UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___POR 0x1
#define   UMAC_UMCMN_R0_UMAC_REVISION__MINOR___POR 0x008
#define   UMAC_UMCMN_R0_UMAC_REVISION__STEP___POR 0x0000
#define   UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___M 0xF0000000
#define   UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___S              28
#define   UMAC_UMCMN_R0_UMAC_REVISION__MINOR___M 0x0FFF0000
#define   UMAC_UMCMN_R0_UMAC_REVISION__MINOR___S              16
#define   UMAC_UMCMN_R0_UMAC_REVISION__STEP___M  0x0000FFFF
#define   UMAC_UMCMN_R0_UMAC_REVISION__STEP___S                0
#define   UMAC_UMCMN_R0_UMAC_REVISION___M        0xFFFFFFFF   
#define   UMAC_UMCMN_R0_UMAC_REVISION___S                      0

#define UMAC_UMCMN_R0_IDLE_CTRL0                  (0x00A400D0)
#define   UMAC_UMCMN_R0_IDLE_CTRL0___RWC            QCSR_REG_RW    
#define   UMAC_UMCMN_R0_IDLE_CTRL0___POR         0x000007DE
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___POR 0x01F
#define   UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___POR 0x0F
#define   UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___POR 0x0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___M 0x00200000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___S              21
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___M 0x00100000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___S              20
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___M 0x00080000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___S              19
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___M 0x00040000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___S              18
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___M 0x00020000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___S              17
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___M 0x00010000
#define   UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___S              16
#define   UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___M 0x0000FFC0
#define   UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___S               6
#define   UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___M 0x0000003E
#define   UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___S               1
#define   UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___M 0x00000001
#define   UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___S               0
#define   UMAC_UMCMN_R0_IDLE_CTRL0___M           0x003FFFFF   
#define   UMAC_UMCMN_R0_IDLE_CTRL0___S                         0

#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR        (0x00A400D4)
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___RWC  QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___POR 0x00000000
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___M 0x00001000
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___S              12
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___M 0x00000800
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___S              11
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___M 0x00000400
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___S              10
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___M 0x00000200
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___S               9
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___M 0x00000100
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___S               8
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___M 0x00000080
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___S               7
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___M 0x00000040
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___S               6
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___M 0x00000020
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___S               5
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___M 0x00000010
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___S               4
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___M 0x00000008
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___S               3
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___M 0x00000004
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___S               2
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___M 0x00000002
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___S               1
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___M 0x00000001
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___S               0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___M 0x00001FFF   
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___S               0

#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL       (0x00A400D8)
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___POR 0x00000001
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___POR 0x0000
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___POR 0x1
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___M 0x0003FFFC
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___S               2
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___M 0x00000002
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___S               1
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___M 0x00000001
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___S               0
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___M 0x0003FFFF   
#define   UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___S               0

#define UMAC_UMCMN_R0_IDLE_SIGNAL                 (0x00A400DC)
#define   UMAC_UMCMN_R0_IDLE_SIGNAL___RWC           QCSR_REG_RO    
#define   UMAC_UMCMN_R0_IDLE_SIGNAL___POR        0x0000007D
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__REO___POR   0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___POR   0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___POR   0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___POR   0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___POR   0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CE___POR    0x1
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__REO___M     0x00000040
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__REO___S                   6
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___M     0x00000020
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___S                   5
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___M     0x00000010
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___S                   4
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___M     0x00000008
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___S                   3
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___M     0x00000004
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___S                   2
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CE___M      0x00000001
#define   UMAC_UMCMN_R0_IDLE_SIGNAL__CE___S                    0
#define   UMAC_UMCMN_R0_IDLE_SIGNAL___M          0x0000007D   
#define   UMAC_UMCMN_R0_IDLE_SIGNAL___S                        0

#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS       (0x00A400E0)
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___RWC QCSR_REG_RO    
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___POR 0x00000000
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___POR 0x0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___POR 0x0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___POR 0x0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___POR 0x0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___POR 0x0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___M 0x00000010
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___S               4
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___M 0x00000008
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___S               3
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___M 0x00000004
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___S               2
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___M 0x00000002
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___S               1
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___M 0x00000001
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___S               0
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___M 0x0000001F   
#define   UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___S               0

#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR (0x00A400E4)
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___RWC QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___POR 0x00000000
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___M 0x00000800
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___S              11
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___M 0x00000400
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___S              10
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___M 0x00000200
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___S               9
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___M 0x00000100
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___S               8
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___M 0x00000080
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___S               7
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___M 0x00000040
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___S               6
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___M 0x00000020
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___S               5
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___M 0x00000010
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___S               4
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___M 0x00000008
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___S               3
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___M 0x00000004
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___S               2
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___M 0x00000002
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___S               1
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___M 0x00000001
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___S               0
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___M 0x00000FFF   
#define   UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___S               0

#define UMAC_UMCMN_R0_S_PARE_0                    (0x00A400E8)
#define   UMAC_UMCMN_R0_S_PARE_0___RWC              QCSR_REG_RW    
#define   UMAC_UMCMN_R0_S_PARE_0___POR           0x00000000
#define   UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___POR 0x00000000
#define   UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___M 0xFFFFFFFF
#define   UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___S               0
#define   UMAC_UMCMN_R0_S_PARE_0___M             0xFFFFFFFF   
#define   UMAC_UMCMN_R0_S_PARE_0___S                           0

#define UMAC_UMCMN_R0_S_PARE_1                    (0x00A400EC)
#define   UMAC_UMCMN_R0_S_PARE_1___RWC              QCSR_REG_RW    
#define   UMAC_UMCMN_R0_S_PARE_1___POR           0x00000000
#define   UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___POR 0x00000000
#define   UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___M 0xFFFFFFFF
#define   UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___S               0
#define   UMAC_UMCMN_R0_S_PARE_1___M             0xFFFFFFFF   
#define   UMAC_UMCMN_R0_S_PARE_1___S                           0

#define UMAC_UMCMN_R0_S_PARE_2                    (0x00A400F0)
#define   UMAC_UMCMN_R0_S_PARE_2___RWC              QCSR_REG_RW    
#define   UMAC_UMCMN_R0_S_PARE_2___POR           0x00000000
#define   UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___POR 0x00000000
#define   UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___M 0xFFFFFFFF
#define   UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___S               0
#define   UMAC_UMCMN_R0_S_PARE_2___M             0xFFFFFFFF   
#define   UMAC_UMCMN_R0_S_PARE_2___S                           0

#define UMAC_UMCMN_R0_S_PARE_3                    (0x00A400F4)
#define   UMAC_UMCMN_R0_S_PARE_3___RWC              QCSR_REG_RW    
#define   UMAC_UMCMN_R0_S_PARE_3___POR           0x00000000
#define   UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___POR 0x00000000
#define   UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___M 0xFFFFFFFF
#define   UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___S               0
#define   UMAC_UMCMN_R0_S_PARE_3___M             0xFFFFFFFF   
#define   UMAC_UMCMN_R0_S_PARE_3___S                           0

#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH            (0x00A400F8)
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___RWC      QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___POR   0x00000008
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___POR 0x0008
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___M 0x0000FFFF
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___S               0
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___M     0x0000FFFF   
#define   UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___S                   0

#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH        (0x00A400FC)
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___RWC  QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___POR 0x0000000A
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___POR 0x000A
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___M 0x0000FFFF
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___S               0
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___M 0x0000FFFF   
#define   UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___S               0

#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL         (0x00A40100)
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___RWC   QCSR_REG_RW    
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___POR 0x00000000
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___POR 0x0
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___M 0x0000000C
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___S               2
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___M 0x00000003
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___S               0
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___M  0x0000000F   
#define   UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___S                0

#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR        (0x00A41000)
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___RWC  QCSR_REG_RO    
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___POR 0x000
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___M 0x00000FFF
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___S               0
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___M 0x00000FFF   
#define   UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___S               0

#define UMAC_UMCMN_R1_UMAC_IDLE                   (0x00A41004)
#define   UMAC_UMCMN_R1_UMAC_IDLE___RWC             QCSR_REG_RO    
#define   UMAC_UMCMN_R1_UMAC_IDLE___POR          0x00000001
#define   UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___POR 0x0
#define   UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___POR 0x0001
#define   UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___M 0x00010000
#define   UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___S              16
#define   UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___M 0x0000FFFF
#define   UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___S               0
#define   UMAC_UMCMN_R1_UMAC_IDLE___M            0x0001FFFF   
#define   UMAC_UMCMN_R1_UMAC_IDLE___S                          0

#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS   (0x00A41008)
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___RWC QCSR_REG_RO    
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___POR 0x00000000
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___POR 0x000000
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___M 0x00FFFFFF
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___S               0
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___M 0x00FFFFFF   
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___S               0

#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR           (0x00A4100C)
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___RWC     QCSR_REG_RW    
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___POR  0x00000000
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___POR 0x00
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___POR 0x00
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___M 0x00000FC0
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___S               6
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___M 0x0000003F
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___S               0
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___M    0x00000FFF   
#define   UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___S                  0

#define UMAC_TCL_R0_SW2TCL1_RING_CTRL             (0x00A44000)
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL___POR    0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___S               6
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___S               5
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL___M      0x0003FFE0   
#define   UMAC_TCL_R0_SW2TCL1_RING_CTRL___S                    5

#define UMAC_TCL_R0_SW2TCL2_RING_CTRL             (0x00A44004)
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL___POR    0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___S               6
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___S               5
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL___M      0x0003FFE0   
#define   UMAC_TCL_R0_SW2TCL2_RING_CTRL___S                    5

#define UMAC_TCL_R0_SW2TCL3_RING_CTRL             (0x00A44008)
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL___POR    0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___S               6
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___S               5
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL___M      0x0003FFE0   
#define   UMAC_TCL_R0_SW2TCL3_RING_CTRL___S                    5

#define UMAC_TCL_R0_FW2TCL1_RING_CTRL             (0x00A4400C)
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL___POR    0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___S               6
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___M 0x00000020
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___S               5
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL___M      0x0003FFE0   
#define   UMAC_TCL_R0_FW2TCL1_RING_CTRL___S                    5

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL       (0x00A44010)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___S               6
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___S               5
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___M 0x0003FFE0   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___S               5

#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG        (0x00A44014)
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___POR 0x0019C000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___POR 0x1
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___POR 0x1
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___POR 0x7
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___POR 0x0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___M 0x00100000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___S              20
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___M 0x00080000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___S              19
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___M 0x00040000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___S              18
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___M 0x00020000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___S              17
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___M 0x0001C000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___S              14
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___M 0x00002000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___S              13
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___M 0x00001000
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___S              12
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___M 0x00000800
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___S              11
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___M 0x00000400
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___S              10
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___M 0x00000200
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___S               9
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___M 0x00000100
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___S               8
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___M 0x00000080
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___S               7
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___M 0x00000040
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___S               6
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___M 0x00000020
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___S               5
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___M 0x00000010
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___S               4
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___M 0x00000008
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___S               3
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___M 0x00000004
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___S               2
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___M 0x00000002
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___S               1
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___M 0x00000001
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___S               0
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___M 0x001FFFFF   
#define   UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_CTRL             (0x00A44018)
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL___POR    0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___M 0x0000C000
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___S              14
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___M 0x00002000
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___S              13
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___M 0x00001000
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___S              12
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL___M      0x0000FFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_CTRL___S                    0

#define UMAC_TCL_R0_TCL2FW_RING_CTRL              (0x00A4401C)
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL___POR     0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL___M       0x00000FFF   
#define   UMAC_TCL_R0_TCL2FW_RING_CTRL___S                     0

#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL         (0x00A44020)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___M  0x00000FFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___S                0

#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL         (0x00A44024)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___POR 0x000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___M  0x00000FFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___S                0

#define UMAC_TCL_R0_GEN_CTRL                      (0x00A44028)
#define   UMAC_TCL_R0_GEN_CTRL___RWC                QCSR_REG_RW    
#define   UMAC_TCL_R0_GEN_CTRL___POR             0x00000000
#define   UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___POR 0x0000
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___POR 0x0
#define   UMAC_TCL_R0_GEN_CTRL__FSE_EN___POR     0x0
#define   UMAC_TCL_R0_GEN_CTRL__CCE_EN___POR     0x0
#define   UMAC_TCL_R0_GEN_CTRL__TO_FW___POR      0x0
#define   UMAC_TCL_R0_GEN_CTRL__EN_11AH___POR    0x0
#define   UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___M 0xFFFF0000
#define   UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___S              16
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___M 0x00008000
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___S              15
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___M 0x00004000
#define   UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___S              14
#define   UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___M 0x00002000
#define   UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___S              13
#define   UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___M 0x00001000
#define   UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___S              12
#define   UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___M 0x00000100
#define   UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___S               8
#define   UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___M 0x00000080
#define   UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___S               7
#define   UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___M 0x00000040
#define   UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___S               6
#define   UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___M 0x00000020
#define   UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___S               5
#define   UMAC_TCL_R0_GEN_CTRL__FSE_EN___M       0x00000010
#define   UMAC_TCL_R0_GEN_CTRL__FSE_EN___S                     4
#define   UMAC_TCL_R0_GEN_CTRL__CCE_EN___M       0x00000008
#define   UMAC_TCL_R0_GEN_CTRL__CCE_EN___S                     3
#define   UMAC_TCL_R0_GEN_CTRL__TO_FW___M        0x00000002
#define   UMAC_TCL_R0_GEN_CTRL__TO_FW___S                      1
#define   UMAC_TCL_R0_GEN_CTRL__EN_11AH___M      0x00000001
#define   UMAC_TCL_R0_GEN_CTRL__EN_11AH___S                    0
#define   UMAC_TCL_R0_GEN_CTRL___M               0xFFFFF1FB   
#define   UMAC_TCL_R0_GEN_CTRL___S                             0

#define UMAC_TCL_R0_DSCP_TID_MAP_n(n)    (0x00A4402C+0x4*(n))
#define   UMAC_TCL_R0_DSCP_TID_MAP_n_nMIN 0    
#define   UMAC_TCL_R0_DSCP_TID_MAP_n_nMAX 287  
#define   UMAC_TCL_R0_DSCP_TID_MAP_n_ELEM 288  
#define   UMAC_TCL_R0_DSCP_TID_MAP_n___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_n___POR       0x00000000
#define   UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___POR  0x00000000
#define   UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___S                  0
#define   UMAC_TCL_R0_DSCP_TID_MAP_n___M         0xFFFFFFFF   
#define   UMAC_TCL_R0_DSCP_TID_MAP_n___S                       0
#define UMAC_TCL_R0_DSCP_TID_MAP_0                (0x00A4402C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_0___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_0__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_0__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_1                (0x00A44030)
#define   UMAC_TCL_R0_DSCP_TID_MAP_1___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_1__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_1__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_2                (0x00A44034)
#define   UMAC_TCL_R0_DSCP_TID_MAP_2___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_2__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_2__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_3                (0x00A44038)
#define   UMAC_TCL_R0_DSCP_TID_MAP_3___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_3__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_3__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_4                (0x00A4403C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_4___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_4__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_4__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_5                (0x00A44040)
#define   UMAC_TCL_R0_DSCP_TID_MAP_5___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_5__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_5__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_6                (0x00A44044)
#define   UMAC_TCL_R0_DSCP_TID_MAP_6___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_6__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_6__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_7                (0x00A44048)
#define   UMAC_TCL_R0_DSCP_TID_MAP_7___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_7__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_7__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_8                (0x00A4404C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_8___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_8__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_8__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_9                (0x00A44050)
#define   UMAC_TCL_R0_DSCP_TID_MAP_9___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_9__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_9__VAL___S                  0
#define UMAC_TCL_R0_DSCP_TID_MAP_10               (0x00A44054)
#define   UMAC_TCL_R0_DSCP_TID_MAP_10___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_10__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_10__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_11               (0x00A44058)
#define   UMAC_TCL_R0_DSCP_TID_MAP_11___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_11__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_11__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_12               (0x00A4405C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_12___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_12__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_12__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_13               (0x00A44060)
#define   UMAC_TCL_R0_DSCP_TID_MAP_13___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_13__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_13__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_14               (0x00A44064)
#define   UMAC_TCL_R0_DSCP_TID_MAP_14___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_14__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_14__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_15               (0x00A44068)
#define   UMAC_TCL_R0_DSCP_TID_MAP_15___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_15__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_15__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_16               (0x00A4406C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_16___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_16__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_16__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_17               (0x00A44070)
#define   UMAC_TCL_R0_DSCP_TID_MAP_17___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_17__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_17__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_18               (0x00A44074)
#define   UMAC_TCL_R0_DSCP_TID_MAP_18___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_18__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_18__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_19               (0x00A44078)
#define   UMAC_TCL_R0_DSCP_TID_MAP_19___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_19__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_19__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_20               (0x00A4407C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_20___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_20__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_20__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_21               (0x00A44080)
#define   UMAC_TCL_R0_DSCP_TID_MAP_21___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_21__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_21__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_22               (0x00A44084)
#define   UMAC_TCL_R0_DSCP_TID_MAP_22___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_22__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_22__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_23               (0x00A44088)
#define   UMAC_TCL_R0_DSCP_TID_MAP_23___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_23__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_23__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_24               (0x00A4408C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_24___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_24__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_24__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_25               (0x00A44090)
#define   UMAC_TCL_R0_DSCP_TID_MAP_25___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_25__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_25__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_26               (0x00A44094)
#define   UMAC_TCL_R0_DSCP_TID_MAP_26___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_26__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_26__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_27               (0x00A44098)
#define   UMAC_TCL_R0_DSCP_TID_MAP_27___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_27__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_27__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_28               (0x00A4409C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_28___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_28__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_28__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_29               (0x00A440A0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_29___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_29__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_29__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_30               (0x00A440A4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_30___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_30__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_30__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_31               (0x00A440A8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_31___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_31__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_31__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_32               (0x00A440AC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_32___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_32__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_32__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_33               (0x00A440B0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_33___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_33__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_33__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_34               (0x00A440B4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_34___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_34__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_34__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_35               (0x00A440B8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_35___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_35__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_35__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_36               (0x00A440BC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_36___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_36__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_36__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_37               (0x00A440C0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_37___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_37__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_37__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_38               (0x00A440C4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_38___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_38__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_38__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_39               (0x00A440C8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_39___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_39__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_39__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_40               (0x00A440CC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_40___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_40__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_40__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_41               (0x00A440D0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_41___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_41__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_41__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_42               (0x00A440D4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_42___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_42__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_42__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_43               (0x00A440D8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_43___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_43__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_43__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_44               (0x00A440DC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_44___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_44__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_44__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_45               (0x00A440E0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_45___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_45__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_45__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_46               (0x00A440E4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_46___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_46__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_46__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_47               (0x00A440E8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_47___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_47__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_47__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_48               (0x00A440EC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_48___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_48__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_48__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_49               (0x00A440F0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_49___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_49__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_49__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_50               (0x00A440F4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_50___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_50__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_50__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_51               (0x00A440F8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_51___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_51__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_51__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_52               (0x00A440FC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_52___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_52__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_52__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_53               (0x00A44100)
#define   UMAC_TCL_R0_DSCP_TID_MAP_53___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_53__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_53__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_54               (0x00A44104)
#define   UMAC_TCL_R0_DSCP_TID_MAP_54___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_54__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_54__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_55               (0x00A44108)
#define   UMAC_TCL_R0_DSCP_TID_MAP_55___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_55__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_55__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_56               (0x00A4410C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_56___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_56__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_56__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_57               (0x00A44110)
#define   UMAC_TCL_R0_DSCP_TID_MAP_57___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_57__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_57__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_58               (0x00A44114)
#define   UMAC_TCL_R0_DSCP_TID_MAP_58___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_58__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_58__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_59               (0x00A44118)
#define   UMAC_TCL_R0_DSCP_TID_MAP_59___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_59__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_59__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_60               (0x00A4411C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_60___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_60__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_60__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_61               (0x00A44120)
#define   UMAC_TCL_R0_DSCP_TID_MAP_61___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_61__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_61__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_62               (0x00A44124)
#define   UMAC_TCL_R0_DSCP_TID_MAP_62___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_62__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_62__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_63               (0x00A44128)
#define   UMAC_TCL_R0_DSCP_TID_MAP_63___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_63__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_63__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_64               (0x00A4412C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_64___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_64__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_64__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_65               (0x00A44130)
#define   UMAC_TCL_R0_DSCP_TID_MAP_65___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_65__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_65__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_66               (0x00A44134)
#define   UMAC_TCL_R0_DSCP_TID_MAP_66___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_66__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_66__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_67               (0x00A44138)
#define   UMAC_TCL_R0_DSCP_TID_MAP_67___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_67__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_67__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_68               (0x00A4413C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_68___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_68__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_68__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_69               (0x00A44140)
#define   UMAC_TCL_R0_DSCP_TID_MAP_69___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_69__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_69__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_70               (0x00A44144)
#define   UMAC_TCL_R0_DSCP_TID_MAP_70___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_70__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_70__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_71               (0x00A44148)
#define   UMAC_TCL_R0_DSCP_TID_MAP_71___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_71__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_71__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_72               (0x00A4414C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_72___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_72__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_72__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_73               (0x00A44150)
#define   UMAC_TCL_R0_DSCP_TID_MAP_73___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_73__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_73__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_74               (0x00A44154)
#define   UMAC_TCL_R0_DSCP_TID_MAP_74___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_74__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_74__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_75               (0x00A44158)
#define   UMAC_TCL_R0_DSCP_TID_MAP_75___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_75__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_75__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_76               (0x00A4415C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_76___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_76__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_76__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_77               (0x00A44160)
#define   UMAC_TCL_R0_DSCP_TID_MAP_77___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_77__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_77__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_78               (0x00A44164)
#define   UMAC_TCL_R0_DSCP_TID_MAP_78___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_78__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_78__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_79               (0x00A44168)
#define   UMAC_TCL_R0_DSCP_TID_MAP_79___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_79__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_79__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_80               (0x00A4416C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_80___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_80__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_80__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_81               (0x00A44170)
#define   UMAC_TCL_R0_DSCP_TID_MAP_81___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_81__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_81__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_82               (0x00A44174)
#define   UMAC_TCL_R0_DSCP_TID_MAP_82___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_82__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_82__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_83               (0x00A44178)
#define   UMAC_TCL_R0_DSCP_TID_MAP_83___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_83__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_83__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_84               (0x00A4417C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_84___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_84__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_84__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_85               (0x00A44180)
#define   UMAC_TCL_R0_DSCP_TID_MAP_85___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_85__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_85__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_86               (0x00A44184)
#define   UMAC_TCL_R0_DSCP_TID_MAP_86___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_86__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_86__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_87               (0x00A44188)
#define   UMAC_TCL_R0_DSCP_TID_MAP_87___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_87__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_87__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_88               (0x00A4418C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_88___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_88__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_88__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_89               (0x00A44190)
#define   UMAC_TCL_R0_DSCP_TID_MAP_89___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_89__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_89__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_90               (0x00A44194)
#define   UMAC_TCL_R0_DSCP_TID_MAP_90___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_90__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_90__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_91               (0x00A44198)
#define   UMAC_TCL_R0_DSCP_TID_MAP_91___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_91__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_91__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_92               (0x00A4419C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_92___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_92__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_92__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_93               (0x00A441A0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_93___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_93__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_93__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_94               (0x00A441A4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_94___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_94__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_94__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_95               (0x00A441A8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_95___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_95__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_95__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_96               (0x00A441AC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_96___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_96__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_96__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_97               (0x00A441B0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_97___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_97__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_97__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_98               (0x00A441B4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_98___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_98__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_98__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_99               (0x00A441B8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_99___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_99__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_99__VAL___S                 0
#define UMAC_TCL_R0_DSCP_TID_MAP_100              (0x00A441BC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_100___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_100__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_100__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_101              (0x00A441C0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_101___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_101__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_101__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_102              (0x00A441C4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_102___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_102__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_102__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_103              (0x00A441C8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_103___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_103__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_103__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_104              (0x00A441CC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_104___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_104__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_104__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_105              (0x00A441D0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_105___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_105__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_105__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_106              (0x00A441D4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_106___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_106__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_106__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_107              (0x00A441D8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_107___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_107__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_107__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_108              (0x00A441DC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_108___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_108__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_108__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_109              (0x00A441E0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_109___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_109__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_109__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_110              (0x00A441E4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_110___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_110__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_110__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_111              (0x00A441E8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_111___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_111__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_111__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_112              (0x00A441EC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_112___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_112__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_112__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_113              (0x00A441F0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_113___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_113__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_113__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_114              (0x00A441F4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_114___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_114__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_114__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_115              (0x00A441F8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_115___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_115__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_115__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_116              (0x00A441FC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_116___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_116__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_116__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_117              (0x00A44200)
#define   UMAC_TCL_R0_DSCP_TID_MAP_117___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_117__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_117__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_118              (0x00A44204)
#define   UMAC_TCL_R0_DSCP_TID_MAP_118___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_118__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_118__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_119              (0x00A44208)
#define   UMAC_TCL_R0_DSCP_TID_MAP_119___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_119__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_119__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_120              (0x00A4420C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_120___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_120__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_120__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_121              (0x00A44210)
#define   UMAC_TCL_R0_DSCP_TID_MAP_121___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_121__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_121__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_122              (0x00A44214)
#define   UMAC_TCL_R0_DSCP_TID_MAP_122___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_122__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_122__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_123              (0x00A44218)
#define   UMAC_TCL_R0_DSCP_TID_MAP_123___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_123__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_123__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_124              (0x00A4421C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_124___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_124__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_124__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_125              (0x00A44220)
#define   UMAC_TCL_R0_DSCP_TID_MAP_125___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_125__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_125__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_126              (0x00A44224)
#define   UMAC_TCL_R0_DSCP_TID_MAP_126___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_126__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_126__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_127              (0x00A44228)
#define   UMAC_TCL_R0_DSCP_TID_MAP_127___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_127__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_127__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_128              (0x00A4422C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_128___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_128__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_128__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_129              (0x00A44230)
#define   UMAC_TCL_R0_DSCP_TID_MAP_129___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_129__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_129__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_130              (0x00A44234)
#define   UMAC_TCL_R0_DSCP_TID_MAP_130___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_130__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_130__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_131              (0x00A44238)
#define   UMAC_TCL_R0_DSCP_TID_MAP_131___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_131__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_131__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_132              (0x00A4423C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_132___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_132__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_132__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_133              (0x00A44240)
#define   UMAC_TCL_R0_DSCP_TID_MAP_133___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_133__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_133__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_134              (0x00A44244)
#define   UMAC_TCL_R0_DSCP_TID_MAP_134___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_134__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_134__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_135              (0x00A44248)
#define   UMAC_TCL_R0_DSCP_TID_MAP_135___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_135__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_135__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_136              (0x00A4424C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_136___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_136__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_136__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_137              (0x00A44250)
#define   UMAC_TCL_R0_DSCP_TID_MAP_137___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_137__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_137__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_138              (0x00A44254)
#define   UMAC_TCL_R0_DSCP_TID_MAP_138___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_138__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_138__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_139              (0x00A44258)
#define   UMAC_TCL_R0_DSCP_TID_MAP_139___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_139__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_139__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_140              (0x00A4425C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_140___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_140__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_140__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_141              (0x00A44260)
#define   UMAC_TCL_R0_DSCP_TID_MAP_141___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_141__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_141__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_142              (0x00A44264)
#define   UMAC_TCL_R0_DSCP_TID_MAP_142___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_142__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_142__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_143              (0x00A44268)
#define   UMAC_TCL_R0_DSCP_TID_MAP_143___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_143__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_143__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_144              (0x00A4426C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_144___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_144__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_144__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_145              (0x00A44270)
#define   UMAC_TCL_R0_DSCP_TID_MAP_145___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_145__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_145__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_146              (0x00A44274)
#define   UMAC_TCL_R0_DSCP_TID_MAP_146___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_146__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_146__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_147              (0x00A44278)
#define   UMAC_TCL_R0_DSCP_TID_MAP_147___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_147__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_147__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_148              (0x00A4427C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_148___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_148__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_148__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_149              (0x00A44280)
#define   UMAC_TCL_R0_DSCP_TID_MAP_149___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_149__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_149__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_150              (0x00A44284)
#define   UMAC_TCL_R0_DSCP_TID_MAP_150___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_150__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_150__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_151              (0x00A44288)
#define   UMAC_TCL_R0_DSCP_TID_MAP_151___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_151__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_151__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_152              (0x00A4428C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_152___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_152__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_152__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_153              (0x00A44290)
#define   UMAC_TCL_R0_DSCP_TID_MAP_153___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_153__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_153__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_154              (0x00A44294)
#define   UMAC_TCL_R0_DSCP_TID_MAP_154___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_154__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_154__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_155              (0x00A44298)
#define   UMAC_TCL_R0_DSCP_TID_MAP_155___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_155__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_155__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_156              (0x00A4429C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_156___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_156__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_156__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_157              (0x00A442A0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_157___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_157__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_157__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_158              (0x00A442A4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_158___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_158__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_158__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_159              (0x00A442A8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_159___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_159__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_159__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_160              (0x00A442AC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_160___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_160__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_160__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_161              (0x00A442B0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_161___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_161__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_161__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_162              (0x00A442B4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_162___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_162__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_162__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_163              (0x00A442B8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_163___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_163__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_163__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_164              (0x00A442BC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_164___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_164__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_164__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_165              (0x00A442C0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_165___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_165__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_165__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_166              (0x00A442C4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_166___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_166__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_166__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_167              (0x00A442C8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_167___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_167__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_167__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_168              (0x00A442CC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_168___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_168__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_168__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_169              (0x00A442D0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_169___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_169__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_169__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_170              (0x00A442D4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_170___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_170__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_170__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_171              (0x00A442D8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_171___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_171__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_171__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_172              (0x00A442DC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_172___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_172__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_172__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_173              (0x00A442E0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_173___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_173__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_173__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_174              (0x00A442E4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_174___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_174__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_174__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_175              (0x00A442E8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_175___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_175__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_175__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_176              (0x00A442EC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_176___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_176__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_176__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_177              (0x00A442F0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_177___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_177__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_177__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_178              (0x00A442F4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_178___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_178__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_178__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_179              (0x00A442F8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_179___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_179__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_179__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_180              (0x00A442FC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_180___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_180__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_180__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_181              (0x00A44300)
#define   UMAC_TCL_R0_DSCP_TID_MAP_181___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_181__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_181__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_182              (0x00A44304)
#define   UMAC_TCL_R0_DSCP_TID_MAP_182___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_182__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_182__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_183              (0x00A44308)
#define   UMAC_TCL_R0_DSCP_TID_MAP_183___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_183__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_183__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_184              (0x00A4430C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_184___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_184__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_184__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_185              (0x00A44310)
#define   UMAC_TCL_R0_DSCP_TID_MAP_185___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_185__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_185__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_186              (0x00A44314)
#define   UMAC_TCL_R0_DSCP_TID_MAP_186___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_186__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_186__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_187              (0x00A44318)
#define   UMAC_TCL_R0_DSCP_TID_MAP_187___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_187__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_187__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_188              (0x00A4431C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_188___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_188__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_188__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_189              (0x00A44320)
#define   UMAC_TCL_R0_DSCP_TID_MAP_189___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_189__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_189__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_190              (0x00A44324)
#define   UMAC_TCL_R0_DSCP_TID_MAP_190___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_190__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_190__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_191              (0x00A44328)
#define   UMAC_TCL_R0_DSCP_TID_MAP_191___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_191__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_191__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_192              (0x00A4432C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_192___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_192__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_192__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_193              (0x00A44330)
#define   UMAC_TCL_R0_DSCP_TID_MAP_193___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_193__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_193__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_194              (0x00A44334)
#define   UMAC_TCL_R0_DSCP_TID_MAP_194___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_194__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_194__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_195              (0x00A44338)
#define   UMAC_TCL_R0_DSCP_TID_MAP_195___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_195__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_195__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_196              (0x00A4433C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_196___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_196__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_196__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_197              (0x00A44340)
#define   UMAC_TCL_R0_DSCP_TID_MAP_197___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_197__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_197__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_198              (0x00A44344)
#define   UMAC_TCL_R0_DSCP_TID_MAP_198___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_198__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_198__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_199              (0x00A44348)
#define   UMAC_TCL_R0_DSCP_TID_MAP_199___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_199__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_199__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_200              (0x00A4434C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_200___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_200__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_200__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_201              (0x00A44350)
#define   UMAC_TCL_R0_DSCP_TID_MAP_201___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_201__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_201__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_202              (0x00A44354)
#define   UMAC_TCL_R0_DSCP_TID_MAP_202___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_202__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_202__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_203              (0x00A44358)
#define   UMAC_TCL_R0_DSCP_TID_MAP_203___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_203__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_203__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_204              (0x00A4435C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_204___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_204__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_204__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_205              (0x00A44360)
#define   UMAC_TCL_R0_DSCP_TID_MAP_205___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_205__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_205__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_206              (0x00A44364)
#define   UMAC_TCL_R0_DSCP_TID_MAP_206___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_206__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_206__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_207              (0x00A44368)
#define   UMAC_TCL_R0_DSCP_TID_MAP_207___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_207__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_207__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_208              (0x00A4436C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_208___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_208__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_208__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_209              (0x00A44370)
#define   UMAC_TCL_R0_DSCP_TID_MAP_209___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_209__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_209__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_210              (0x00A44374)
#define   UMAC_TCL_R0_DSCP_TID_MAP_210___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_210__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_210__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_211              (0x00A44378)
#define   UMAC_TCL_R0_DSCP_TID_MAP_211___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_211__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_211__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_212              (0x00A4437C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_212___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_212__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_212__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_213              (0x00A44380)
#define   UMAC_TCL_R0_DSCP_TID_MAP_213___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_213__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_213__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_214              (0x00A44384)
#define   UMAC_TCL_R0_DSCP_TID_MAP_214___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_214__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_214__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_215              (0x00A44388)
#define   UMAC_TCL_R0_DSCP_TID_MAP_215___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_215__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_215__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_216              (0x00A4438C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_216___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_216__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_216__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_217              (0x00A44390)
#define   UMAC_TCL_R0_DSCP_TID_MAP_217___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_217__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_217__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_218              (0x00A44394)
#define   UMAC_TCL_R0_DSCP_TID_MAP_218___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_218__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_218__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_219              (0x00A44398)
#define   UMAC_TCL_R0_DSCP_TID_MAP_219___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_219__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_219__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_220              (0x00A4439C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_220___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_220__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_220__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_221              (0x00A443A0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_221___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_221__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_221__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_222              (0x00A443A4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_222___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_222__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_222__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_223              (0x00A443A8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_223___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_223__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_223__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_224              (0x00A443AC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_224___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_224__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_224__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_225              (0x00A443B0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_225___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_225__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_225__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_226              (0x00A443B4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_226___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_226__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_226__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_227              (0x00A443B8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_227___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_227__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_227__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_228              (0x00A443BC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_228___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_228__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_228__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_229              (0x00A443C0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_229___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_229__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_229__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_230              (0x00A443C4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_230___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_230__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_230__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_231              (0x00A443C8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_231___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_231__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_231__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_232              (0x00A443CC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_232___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_232__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_232__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_233              (0x00A443D0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_233___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_233__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_233__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_234              (0x00A443D4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_234___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_234__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_234__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_235              (0x00A443D8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_235___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_235__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_235__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_236              (0x00A443DC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_236___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_236__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_236__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_237              (0x00A443E0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_237___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_237__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_237__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_238              (0x00A443E4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_238___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_238__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_238__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_239              (0x00A443E8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_239___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_239__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_239__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_240              (0x00A443EC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_240___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_240__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_240__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_241              (0x00A443F0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_241___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_241__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_241__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_242              (0x00A443F4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_242___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_242__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_242__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_243              (0x00A443F8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_243___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_243__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_243__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_244              (0x00A443FC)
#define   UMAC_TCL_R0_DSCP_TID_MAP_244___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_244__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_244__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_245              (0x00A44400)
#define   UMAC_TCL_R0_DSCP_TID_MAP_245___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_245__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_245__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_246              (0x00A44404)
#define   UMAC_TCL_R0_DSCP_TID_MAP_246___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_246__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_246__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_247              (0x00A44408)
#define   UMAC_TCL_R0_DSCP_TID_MAP_247___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_247__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_247__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_248              (0x00A4440C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_248___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_248__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_248__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_249              (0x00A44410)
#define   UMAC_TCL_R0_DSCP_TID_MAP_249___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_249__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_249__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_250              (0x00A44414)
#define   UMAC_TCL_R0_DSCP_TID_MAP_250___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_250__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_250__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_251              (0x00A44418)
#define   UMAC_TCL_R0_DSCP_TID_MAP_251___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_251__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_251__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_252              (0x00A4441C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_252___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_252__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_252__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_253              (0x00A44420)
#define   UMAC_TCL_R0_DSCP_TID_MAP_253___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_253__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_253__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_254              (0x00A44424)
#define   UMAC_TCL_R0_DSCP_TID_MAP_254___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_254__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_254__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_255              (0x00A44428)
#define   UMAC_TCL_R0_DSCP_TID_MAP_255___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_255__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_255__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_256              (0x00A4442C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_256___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_256__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_256__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_257              (0x00A44430)
#define   UMAC_TCL_R0_DSCP_TID_MAP_257___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_257__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_257__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_258              (0x00A44434)
#define   UMAC_TCL_R0_DSCP_TID_MAP_258___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_258__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_258__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_259              (0x00A44438)
#define   UMAC_TCL_R0_DSCP_TID_MAP_259___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_259__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_259__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_260              (0x00A4443C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_260___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_260__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_260__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_261              (0x00A44440)
#define   UMAC_TCL_R0_DSCP_TID_MAP_261___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_261__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_261__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_262              (0x00A44444)
#define   UMAC_TCL_R0_DSCP_TID_MAP_262___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_262__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_262__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_263              (0x00A44448)
#define   UMAC_TCL_R0_DSCP_TID_MAP_263___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_263__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_263__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_264              (0x00A4444C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_264___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_264__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_264__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_265              (0x00A44450)
#define   UMAC_TCL_R0_DSCP_TID_MAP_265___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_265__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_265__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_266              (0x00A44454)
#define   UMAC_TCL_R0_DSCP_TID_MAP_266___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_266__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_266__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_267              (0x00A44458)
#define   UMAC_TCL_R0_DSCP_TID_MAP_267___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_267__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_267__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_268              (0x00A4445C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_268___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_268__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_268__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_269              (0x00A44460)
#define   UMAC_TCL_R0_DSCP_TID_MAP_269___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_269__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_269__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_270              (0x00A44464)
#define   UMAC_TCL_R0_DSCP_TID_MAP_270___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_270__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_270__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_271              (0x00A44468)
#define   UMAC_TCL_R0_DSCP_TID_MAP_271___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_271__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_271__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_272              (0x00A4446C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_272___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_272__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_272__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_273              (0x00A44470)
#define   UMAC_TCL_R0_DSCP_TID_MAP_273___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_273__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_273__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_274              (0x00A44474)
#define   UMAC_TCL_R0_DSCP_TID_MAP_274___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_274__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_274__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_275              (0x00A44478)
#define   UMAC_TCL_R0_DSCP_TID_MAP_275___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_275__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_275__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_276              (0x00A4447C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_276___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_276__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_276__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_277              (0x00A44480)
#define   UMAC_TCL_R0_DSCP_TID_MAP_277___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_277__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_277__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_278              (0x00A44484)
#define   UMAC_TCL_R0_DSCP_TID_MAP_278___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_278__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_278__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_279              (0x00A44488)
#define   UMAC_TCL_R0_DSCP_TID_MAP_279___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_279__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_279__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_280              (0x00A4448C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_280___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_280__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_280__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_281              (0x00A44490)
#define   UMAC_TCL_R0_DSCP_TID_MAP_281___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_281__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_281__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_282              (0x00A44494)
#define   UMAC_TCL_R0_DSCP_TID_MAP_282___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_282__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_282__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_283              (0x00A44498)
#define   UMAC_TCL_R0_DSCP_TID_MAP_283___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_283__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_283__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_284              (0x00A4449C)
#define   UMAC_TCL_R0_DSCP_TID_MAP_284___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_284__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_284__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_285              (0x00A444A0)
#define   UMAC_TCL_R0_DSCP_TID_MAP_285___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_285__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_285__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_286              (0x00A444A4)
#define   UMAC_TCL_R0_DSCP_TID_MAP_286___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_286__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_286__VAL___S                0
#define UMAC_TCL_R0_DSCP_TID_MAP_287              (0x00A444A8)
#define   UMAC_TCL_R0_DSCP_TID_MAP_287___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_DSCP_TID_MAP_287__VAL___M  0xFFFFFFFF
#define   UMAC_TCL_R0_DSCP_TID_MAP_287__VAL___S                0

#define UMAC_TCL_R0_PCP_TID_MAP                   (0x00A444AC)
#define   UMAC_TCL_R0_PCP_TID_MAP___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_PCP_TID_MAP___POR          0x00000000
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_7___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_6___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_5___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_4___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_3___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_2___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_1___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_0___POR   0x0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_7___M     0x00E00000
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_7___S                  21
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_6___M     0x001C0000
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_6___S                  18
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_5___M     0x00038000
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_5___S                  15
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_4___M     0x00007000
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_4___S                  12
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_3___M     0x00000E00
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_3___S                   9
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_2___M     0x000001C0
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_2___S                   6
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_1___M     0x00000038
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_1___S                   3
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_0___M     0x00000007
#define   UMAC_TCL_R0_PCP_TID_MAP__PCP_0___S                   0
#define   UMAC_TCL_R0_PCP_TID_MAP___M            0x00FFFFFF   
#define   UMAC_TCL_R0_PCP_TID_MAP___S                          0

#define UMAC_TCL_R0_ASE_HASH_KEY_31_0             (0x00A444B0)
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0___POR    0x00000000
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___POR 0x00000000
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___S               0
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0___M      0xFFFFFFFF   
#define   UMAC_TCL_R0_ASE_HASH_KEY_31_0___S                    0

#define UMAC_TCL_R0_ASE_HASH_KEY_63_32            (0x00A444B4)
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32___RWC      QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32___POR   0x00000000
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___POR 0x00000000
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___S               0
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32___M     0xFFFFFFFF   
#define   UMAC_TCL_R0_ASE_HASH_KEY_63_32___S                   0

#define UMAC_TCL_R0_ASE_HASH_KEY_64               (0x00A444B8)
#define   UMAC_TCL_R0_ASE_HASH_KEY_64___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_HASH_KEY_64___POR      0x00000000
#define   UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___POR 0x0
#define   UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___M   0x00000001
#define   UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___S                 0
#define   UMAC_TCL_R0_ASE_HASH_KEY_64___M        0x00000001   
#define   UMAC_TCL_R0_ASE_HASH_KEY_64___S                      0

#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE           (0x00A444BC)
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___POR  0x00840014
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___POR 0x1
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___POR 0x2
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___POR 0x0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___POR 0x1
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___POR 0x1
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___M 0x00800000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___S              23
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___M 0x00700000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___S              20
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___M 0x000E0000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___S              17
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___M 0x0001C000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___S              14
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___M 0x00002000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___S              13
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___M 0x00001000
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___S              12
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___M 0x00000800
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___S              11
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___M 0x00000400
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___S              10
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___M 0x000001C0
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___S               6
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___M 0x00000030
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___S               4
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___M 0x0000000C
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___S               2
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___M    0x00FFFDFC   
#define   UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___S                  2

#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW        (0x00A444C0)
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___POR 0x00000000
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___POR 0x00000000
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___S               0
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___S               0

#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH       (0x00A444C4)
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___POR 0x00000000
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___POR 0x00
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___M 0x000000FF
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___S               0
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___M 0x000000FF   
#define   UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___S               0

#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW        (0x00A444C8)
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___POR 0x00000000
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___POR 0x00000000
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___S               0
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___S               0

#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH       (0x00A444CC)
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___POR 0x00000000
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___POR 0x00
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___M 0x000000FF
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___S               0
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___M 0x000000FF   
#define   UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___S               0

#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA        (0x00A444D0)
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA___POR 0x00000000
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___POR 0x0000
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___POR 0x0000
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___M 0xFFFF0000
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___S              16
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___M 0x0000FFFF
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___S               0
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_CONFIG_SEARCH_METADATA___S               0

#define UMAC_TCL_R0_TID_MAP_PRTY                  (0x00A444D4)
#define   UMAC_TCL_R0_TID_MAP_PRTY___RWC            QCSR_REG_RW    
#define   UMAC_TCL_R0_TID_MAP_PRTY___POR         0x00000000
#define   UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___POR 0x0
#define   UMAC_TCL_R0_TID_MAP_PRTY__VAL___POR    0x0
#define   UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___M  0x000000E0
#define   UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___S                5
#define   UMAC_TCL_R0_TID_MAP_PRTY__VAL___M      0x0000000F
#define   UMAC_TCL_R0_TID_MAP_PRTY__VAL___S                    0
#define   UMAC_TCL_R0_TID_MAP_PRTY___M           0x000000EF   
#define   UMAC_TCL_R0_TID_MAP_PRTY___S                         0

#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR          (0x00A444D8)
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR___RWC    QCSR_REG_RO    
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___POR 0x00000000
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___S               0
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR___M   0xFFFFFFFF   
#define   UMAC_TCL_R0_INVALID_APB_ACC_ADDR___S                 0

#define UMAC_TCL_R0_WATCHDOG                      (0x00A444DC)
#define   UMAC_TCL_R0_WATCHDOG___RWC                QCSR_REG_RW    
#define   UMAC_TCL_R0_WATCHDOG___POR             0x0000FFFF
#define   UMAC_TCL_R0_WATCHDOG__STATUS___POR     0x0000
#define   UMAC_TCL_R0_WATCHDOG__LIMIT___POR      0xFFFF
#define   UMAC_TCL_R0_WATCHDOG__STATUS___M       0xFFFF0000
#define   UMAC_TCL_R0_WATCHDOG__STATUS___S                    16
#define   UMAC_TCL_R0_WATCHDOG__LIMIT___M        0x0000FFFF
#define   UMAC_TCL_R0_WATCHDOG__LIMIT___S                      0
#define   UMAC_TCL_R0_WATCHDOG___M               0xFFFFFFFF   
#define   UMAC_TCL_R0_WATCHDOG___S                             0

#define UMAC_TCL_R0_LCE_RULE_n(n)        (0x00A444E0+0x4*(n))
#define   UMAC_TCL_R0_LCE_RULE_n_nMIN 0    
#define   UMAC_TCL_R0_LCE_RULE_n_nMAX 25   
#define   UMAC_TCL_R0_LCE_RULE_n_ELEM 26   
#define   UMAC_TCL_R0_LCE_RULE_n___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_n___POR           0x00000000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___POR 0x0
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___POR 0x0000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___S                0
#define   UMAC_TCL_R0_LCE_RULE_n___M             0x007FFFFF   
#define   UMAC_TCL_R0_LCE_RULE_n___S                           0
#define UMAC_TCL_R0_LCE_RULE_0                    (0x00A444E0)
#define   UMAC_TCL_R0_LCE_RULE_0___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_0__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_0__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_0__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_1                    (0x00A444E4)
#define   UMAC_TCL_R0_LCE_RULE_1___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_1__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_1__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_1__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_2                    (0x00A444E8)
#define   UMAC_TCL_R0_LCE_RULE_2___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_2__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_2__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_2__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_3                    (0x00A444EC)
#define   UMAC_TCL_R0_LCE_RULE_3___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_3__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_3__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_3__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_4                    (0x00A444F0)
#define   UMAC_TCL_R0_LCE_RULE_4___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_4__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_4__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_4__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_5                    (0x00A444F4)
#define   UMAC_TCL_R0_LCE_RULE_5___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_5__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_5__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_5__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_6                    (0x00A444F8)
#define   UMAC_TCL_R0_LCE_RULE_6___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_6__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_6__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_6__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_7                    (0x00A444FC)
#define   UMAC_TCL_R0_LCE_RULE_7___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_7__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_7__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_7__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_8                    (0x00A44500)
#define   UMAC_TCL_R0_LCE_RULE_8___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_8__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_8__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_8__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_9                    (0x00A44504)
#define   UMAC_TCL_R0_LCE_RULE_9___RWC              QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_9__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_9__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_VAL___M  0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_9__MATCH_VAL___S                0
#define UMAC_TCL_R0_LCE_RULE_10                   (0x00A44508)
#define   UMAC_TCL_R0_LCE_RULE_10___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_10__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_10__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_10__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_11                   (0x00A4450C)
#define   UMAC_TCL_R0_LCE_RULE_11___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_11__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_11__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_11__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_12                   (0x00A44510)
#define   UMAC_TCL_R0_LCE_RULE_12___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_12__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_12__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_12__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_13                   (0x00A44514)
#define   UMAC_TCL_R0_LCE_RULE_13___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_13__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_13__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_13__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_14                   (0x00A44518)
#define   UMAC_TCL_R0_LCE_RULE_14___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_14__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_14__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_14__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_15                   (0x00A4451C)
#define   UMAC_TCL_R0_LCE_RULE_15___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_15__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_15__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_15__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_16                   (0x00A44520)
#define   UMAC_TCL_R0_LCE_RULE_16___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_16__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_16__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_16__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_17                   (0x00A44524)
#define   UMAC_TCL_R0_LCE_RULE_17___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_17__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_17__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_17__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_18                   (0x00A44528)
#define   UMAC_TCL_R0_LCE_RULE_18___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_18__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_18__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_18__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_19                   (0x00A4452C)
#define   UMAC_TCL_R0_LCE_RULE_19___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_19__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_19__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_19__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_20                   (0x00A44530)
#define   UMAC_TCL_R0_LCE_RULE_20___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_20__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_20__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_20__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_21                   (0x00A44534)
#define   UMAC_TCL_R0_LCE_RULE_21___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_21__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_21__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_21__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_22                   (0x00A44538)
#define   UMAC_TCL_R0_LCE_RULE_22___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_22__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_22__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_22__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_23                   (0x00A4453C)
#define   UMAC_TCL_R0_LCE_RULE_23___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_23__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_23__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_23__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_24                   (0x00A44540)
#define   UMAC_TCL_R0_LCE_RULE_24___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_24__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_24__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_24__MATCH_VAL___S               0
#define UMAC_TCL_R0_LCE_RULE_25                   (0x00A44544)
#define   UMAC_TCL_R0_LCE_RULE_25___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_IP_PROT___M 0x00400000
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_IP_PROT___S              22
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_ADDR_BIT_0___M 0x00200000
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_ADDR_BIT_0___S              21
#define   UMAC_TCL_R0_LCE_RULE_25__TCP_OR_UDP___M 0x00180000
#define   UMAC_TCL_R0_LCE_RULE_25__TCP_OR_UDP___S              19
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_PORT___M 0x00040000
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_PORT___S              18
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_SRC_PORT___M 0x00020000
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_SRC_PORT___S              17
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_L3_TYPE___M 0x00010000
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_L3_TYPE___S              16
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_LCE_RULE_25__MATCH_VAL___S               0

#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n(n) (0x00A44548+0x4*(n))
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_nMIN 0    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_nMAX 25   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ELEM 26   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___POR 0x00000000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___POR 0x00000000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___S               0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0  (0x00A44548)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1  (0x00A4454C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2  (0x00A44550)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3  (0x00A44554)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4  (0x00A44558)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5  (0x00A4455C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6  (0x00A44560)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7  (0x00A44564)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8  (0x00A44568)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9  (0x00A4456C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10 (0x00A44570)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11 (0x00A44574)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12 (0x00A44578)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13 (0x00A4457C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14 (0x00A44580)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15 (0x00A44584)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16 (0x00A44588)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17 (0x00A4458C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18 (0x00A44590)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19 (0x00A44594)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20 (0x00A44598)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21 (0x00A4459C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22 (0x00A445A0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23 (0x00A445A4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24 (0x00A445A8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25 (0x00A445AC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25__VAL___S               0

#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n(n) (0x00A445B0+0x4*(n))
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_nMIN 0    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_nMAX 25   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ELEM 26   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___POR 0x00000000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___POR 0x00
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___S               0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___M 0x000000FF   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0  (0x00A445B0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1  (0x00A445B4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2  (0x00A445B8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3  (0x00A445BC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4  (0x00A445C0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5  (0x00A445C4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6  (0x00A445C8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7  (0x00A445CC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8  (0x00A445D0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9  (0x00A445D4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10 (0x00A445D8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11 (0x00A445DC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12 (0x00A445E0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13 (0x00A445E4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14 (0x00A445E8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15 (0x00A445EC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16 (0x00A445F0)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17 (0x00A445F4)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18 (0x00A445F8)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19 (0x00A445FC)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20 (0x00A44600)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21 (0x00A44604)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22 (0x00A44608)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23 (0x00A4460C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24 (0x00A44610)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24__VAL___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25 (0x00A44614)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25__VAL___M 0x000000FF
#define   UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25__VAL___S               0

#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n(n) (0x00A44618+0x4*(n))
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_nMIN 0    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_nMAX 25   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ELEM 26   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___POR 0x00000000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___POR 0x0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___POR 0x0000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___POR 0x0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___POR 0x0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___POR 0x0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___POR 0x0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___S               0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___M 0x003FFFFF   
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0       (0x00A44618)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1       (0x00A4461C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2       (0x00A44620)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3       (0x00A44624)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4       (0x00A44628)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5       (0x00A4462C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6       (0x00A44630)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7       (0x00A44634)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8       (0x00A44638)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9       (0x00A4463C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10      (0x00A44640)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11      (0x00A44644)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12      (0x00A44648)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13      (0x00A4464C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14      (0x00A44650)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15      (0x00A44654)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16      (0x00A44658)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17      (0x00A4465C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18      (0x00A44660)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19      (0x00A44664)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20      (0x00A44668)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21      (0x00A4466C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22      (0x00A44670)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23      (0x00A44674)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24      (0x00A44678)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_HANDLER___S               0
#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25      (0x00A4467C)
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__RULE_HIT___M 0x00200000
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__RULE_HIT___S              21
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__METADATA___M 0x001FFFE0
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__METADATA___S               5
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__MSDU_DROP___M 0x00000010
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__MSDU_DROP___S               4
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TO_TQM_IF_M0_FW___M 0x00000008
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TO_TQM_IF_M0_FW___S               3
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_LOOP_HANDLER___M 0x00000004
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_LOOP_HANDLER___S               2
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_HANDLER___M 0x00000003
#define   UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_HANDLER___S               0

#define UMAC_TCL_R0_CLKGATE_DISABLE               (0x00A44680)
#define   UMAC_TCL_R0_CLKGATE_DISABLE___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_CLKGATE_DISABLE___POR      0x00000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__FSE___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__ASE___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GXI___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___POR 0x0
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___M 0x20000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___S              29
#define   UMAC_TCL_R0_CLKGATE_DISABLE__FSE___M   0x10000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__FSE___S                28
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___M 0x08000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___S              27
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___M 0x04000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___S              26
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___M 0x02000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___S              25
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___M 0x01000000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___S              24
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___M 0x00800000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___S              23
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___M 0x00400000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___S              22
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___M 0x00200000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___S              21
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___M 0x00100000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___S              20
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___M 0x00080000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___S              19
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___M 0x00040000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___S              18
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___M 0x00020000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___S              17
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___M 0x00010000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___S              16
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___M 0x00008000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___S              15
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___M 0x00004000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___S              14
#define   UMAC_TCL_R0_CLKGATE_DISABLE__ASE___M   0x00002000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__ASE___S                13
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GXI___M   0x00001000
#define   UMAC_TCL_R0_CLKGATE_DISABLE__GXI___S                12
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___M 0x00000800
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___S              11
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___M 0x00000400
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___S              10
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___M 0x00000200
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___S               9
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___M 0x00000100
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___S               8
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___M 0x00000080
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___S               7
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___M 0x00000040
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___S               6
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___M 0x00000020
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___S               5
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___M 0x00000010
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___S               4
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___M 0x00000008
#define   UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___S               3
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___M 0x00000004
#define   UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___S               2
#define   UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___M 0x00000002
#define   UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___S               1
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___M 0x00000001
#define   UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___S               0
#define   UMAC_TCL_R0_CLKGATE_DISABLE___M        0xFFFFFFFF   
#define   UMAC_TCL_R0_CLKGATE_DISABLE___S                      0

#define UMAC_TCL_R0_CREDIT_COUNT                  (0x00A44684)
#define   UMAC_TCL_R0_CREDIT_COUNT___RWC            QCSR_REG_RW    
#define   UMAC_TCL_R0_CREDIT_COUNT___POR         0x00000000
#define   UMAC_TCL_R0_CREDIT_COUNT__ENABLE___POR 0x0
#define   UMAC_TCL_R0_CREDIT_COUNT__VAL___POR    0x0000
#define   UMAC_TCL_R0_CREDIT_COUNT__ENABLE___M   0x00010000
#define   UMAC_TCL_R0_CREDIT_COUNT__ENABLE___S                16
#define   UMAC_TCL_R0_CREDIT_COUNT__VAL___M      0x0000FFFF
#define   UMAC_TCL_R0_CREDIT_COUNT__VAL___S                    0
#define   UMAC_TCL_R0_CREDIT_COUNT___M           0x0001FFFF   
#define   UMAC_TCL_R0_CREDIT_COUNT___S                         0

#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT          (0x00A44688)
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT___RWC    QCSR_REG_RO    
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT___POR 0x00000000
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___POR 0x0000
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___M 0x0000FFFF
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___S               0
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT___M   0x0000FFFF   
#define   UMAC_TCL_R0_CURRENT_CREDIT_COUNT___S                 0

#define UMAC_TCL_R0_S_PARE_REGISTER               (0x00A4468C)
#define   UMAC_TCL_R0_S_PARE_REGISTER___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_S_PARE_REGISTER___POR      0x00000000
#define   UMAC_TCL_R0_S_PARE_REGISTER__VAL___POR 0x00000000
#define   UMAC_TCL_R0_S_PARE_REGISTER__VAL___M   0xFFFFFFFF
#define   UMAC_TCL_R0_S_PARE_REGISTER__VAL___S                 0
#define   UMAC_TCL_R0_S_PARE_REGISTER___M        0xFFFFFFFF   
#define   UMAC_TCL_R0_S_PARE_REGISTER___S                      0

#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB         (0x00A44690)
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___S                0

#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB         (0x00A44694)
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___S                0

#define UMAC_TCL_R0_SW2TCL1_RING_ID               (0x00A44698)
#define   UMAC_TCL_R0_SW2TCL1_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_ID___POR      0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_ID___M        0x000000FF   
#define   UMAC_TCL_R0_SW2TCL1_RING_ID___S                      0

#define UMAC_TCL_R0_SW2TCL1_RING_STATUS           (0x00A4469C)
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_STATUS___S                  0

#define UMAC_TCL_R0_SW2TCL1_RING_MISC             (0x00A446A0)
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC___POR    0x00000080
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC___M      0x003FFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_MISC___S                    0

#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB      (0x00A446AC)
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB      (0x00A446B0)
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A446C0)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A446C4)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS (0x00A446C8)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A446CC)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A446D0)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A446D4)
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              20
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB    (0x00A446D8)
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB    (0x00A446DC)
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA        (0x00A446E0)
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET  (0x00A446E4)
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB         (0x00A446E8)
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___S                0

#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB         (0x00A446EC)
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___S                0

#define UMAC_TCL_R0_SW2TCL2_RING_ID               (0x00A446F0)
#define   UMAC_TCL_R0_SW2TCL2_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_ID___POR      0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_ID___M        0x000000FF   
#define   UMAC_TCL_R0_SW2TCL2_RING_ID___S                      0

#define UMAC_TCL_R0_SW2TCL2_RING_STATUS           (0x00A446F4)
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_STATUS___S                  0

#define UMAC_TCL_R0_SW2TCL2_RING_MISC             (0x00A446F8)
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC___POR    0x00000080
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC___M      0x003FFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_MISC___S                    0

#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB      (0x00A44704)
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB      (0x00A44708)
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 (0x00A44718)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 (0x00A4471C)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS (0x00A44720)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER (0x00A44724)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER (0x00A44728)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS (0x00A4472C)
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              20
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB    (0x00A44730)
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB    (0x00A44734)
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA        (0x00A44738)
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET  (0x00A4473C)
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB         (0x00A44740)
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___S                0

#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB         (0x00A44744)
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___M  0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___S                0

#define UMAC_TCL_R0_SW2TCL3_RING_ID               (0x00A44748)
#define   UMAC_TCL_R0_SW2TCL3_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_ID___POR      0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_ID___M        0x000000FF   
#define   UMAC_TCL_R0_SW2TCL3_RING_ID___S                      0

#define UMAC_TCL_R0_SW2TCL3_RING_STATUS           (0x00A4474C)
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_STATUS___S                  0

#define UMAC_TCL_R0_SW2TCL3_RING_MISC             (0x00A44750)
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC___POR    0x00000080
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC___M      0x003FFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_MISC___S                    0

#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB      (0x00A4475C)
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB      (0x00A44760)
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 (0x00A44770)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 (0x00A44774)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS (0x00A44778)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER (0x00A4477C)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER (0x00A44780)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS (0x00A44784)
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              20
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB    (0x00A44788)
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB    (0x00A4478C)
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA        (0x00A44790)
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET  (0x00A44794)
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB   (0x00A44798)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB   (0x00A4479C)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___M 0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID         (0x00A447A0)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___M  0x000000FF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___S                0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS     (0x00A447A4)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC       (0x00A447A8)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___POR 0x00000080
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___M 0x003FFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB (0x00A447B4)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB (0x00A447B8)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 (0x00A447C8)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 (0x00A447CC)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS (0x00A447D0)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER (0x00A447D4)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER (0x00A447D8)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS (0x00A447DC)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              20
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB (0x00A447E0)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB (0x00A447E4)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA  (0x00A447E8)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET (0x00A447EC)
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB         (0x00A447F0)
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___S                0

#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB         (0x00A447F4)
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___S                0

#define UMAC_TCL_R0_FW2TCL1_RING_ID               (0x00A447F8)
#define   UMAC_TCL_R0_FW2TCL1_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_ID___POR      0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_ID___M        0x000000FF   
#define   UMAC_TCL_R0_FW2TCL1_RING_ID___S                      0

#define UMAC_TCL_R0_FW2TCL1_RING_STATUS           (0x00A447FC)
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_STATUS___S                  0

#define UMAC_TCL_R0_FW2TCL1_RING_MISC             (0x00A44800)
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC___POR    0x00000080
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC___M      0x003FFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_MISC___S                    0

#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB      (0x00A4480C)
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB      (0x00A44810)
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A44820)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A44824)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS (0x00A44828)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A4482C)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A44830)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A44834)
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB    (0x00A44838)
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB    (0x00A4483C)
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA        (0x00A44840)
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET  (0x00A44844)
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB         (0x00A44848)
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___S                0

#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB         (0x00A4484C)
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___M  0x00FFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___S                0

#define UMAC_TCL_R0_TCL2TQM_RING_ID               (0x00A44850)
#define   UMAC_TCL_R0_TCL2TQM_RING_ID___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_ID___POR      0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___S               8
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_ID___M        0x0000FFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_ID___S                      0

#define UMAC_TCL_R0_TCL2TQM_RING_STATUS           (0x00A44854)
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_STATUS___S                  0

#define UMAC_TCL_R0_TCL2TQM_RING_MISC             (0x00A44858)
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC___POR    0x00000080
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC___M      0x03FFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_MISC___S                    0

#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB      (0x00A4485C)
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB      (0x00A44860)
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP (0x00A4486C)
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS (0x00A44870)
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER (0x00A44874)
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB    (0x00A44890)
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB    (0x00A44894)
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA        (0x00A44898)
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET  (0x00A4489C)
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB     (0x00A448A0)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB     (0x00A448A4)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_ID           (0x00A448A8)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID___POR  0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___S               8
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID___M    0x0000FFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_ID___S                  0

#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS       (0x00A448AC)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC         (0x00A448B0)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC___POR 0x00000080
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC___M  0x03FFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MISC___S                0

#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB  (0x00A448B4)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB  (0x00A448B8)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP (0x00A448C4)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS (0x00A448C8)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A448CC)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB (0x00A448E8)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB (0x00A448EC)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA    (0x00A448F0)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET (0x00A448F4)
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB     (0x00A448F8)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB     (0x00A448FC)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___M 0x00FFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_ID           (0x00A44900)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID___POR  0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___S               8
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID___M    0x0000FFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_ID___S                  0

#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS       (0x00A44904)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC         (0x00A44908)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC___POR 0x00000080
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC___M  0x03FFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MISC___S                0

#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB  (0x00A4490C)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB  (0x00A44910)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP (0x00A4491C)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS (0x00A44920)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER (0x00A44924)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB (0x00A44940)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB (0x00A44944)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA    (0x00A44948)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___S               0

#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET (0x00A4494C)
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB          (0x00A44950)
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___RWC    QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___M   0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___S                 0

#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB          (0x00A44954)
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___RWC    QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___S               8
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___M   0x00FFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___S                 0

#define UMAC_TCL_R0_TCL2FW_RING_ID                (0x00A44958)
#define   UMAC_TCL_R0_TCL2FW_RING_ID___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_ID___POR       0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___M 0x0000FF00
#define   UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___S               8
#define   UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_ID___M         0x0000FFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_ID___S                       0

#define UMAC_TCL_R0_TCL2FW_RING_STATUS            (0x00A4495C)
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS___RWC      QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS___POR   0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS___M     0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_STATUS___S                   0

#define UMAC_TCL_R0_TCL2FW_RING_MISC              (0x00A44960)
#define   UMAC_TCL_R0_TCL2FW_RING_MISC___RWC        QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_MISC___POR     0x00000080
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___M 0x03C00000
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___S              22
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___S              14
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___S              12
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___S               8
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___S               7
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___S               6
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___S               3
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___M 0x00000004
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___S               2
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___S               1
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_MISC___M       0x03FFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_MISC___S                     0

#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB       (0x00A44964)
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___S               0

#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB       (0x00A44968)
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___M 0x000000FF   
#define   UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___S               0

#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP (0x00A44974)
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___S               0

#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS (0x00A44978)
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___S               0

#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER (0x00A4497C)
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___S               0

#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB     (0x00A44998)
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___S               0

#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB     (0x00A4499C)
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___S               0

#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA         (0x00A449A0)
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___S                0

#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET   (0x00A449A4)
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___S               0

#define UMAC_TCL_R0_GXI_TESTBUS_LOWER             (0x00A449A8)
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER___RWC       QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER___POR    0x00000000
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___S               0
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER___M      0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_TESTBUS_LOWER___S                    0

#define UMAC_TCL_R0_GXI_TESTBUS_UPPER             (0x00A449AC)
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER___RWC       QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER___POR    0x00000000
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___S               0
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER___M      0x000000FF   
#define   UMAC_TCL_R0_GXI_TESTBUS_UPPER___S                    0

#define UMAC_TCL_R0_GXI_SM_STATES_IX_0            (0x00A449B0)
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0___RWC      QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0___POR   0x00000211
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S               9
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S               4
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S               0
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0___M     0x00000FFF   
#define   UMAC_TCL_R0_GXI_SM_STATES_IX_0___S                   0

#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK         (0x00A449B4)
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___M  0x00000001   
#define   UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___S                0

#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE        (0x00A449B8)
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S              11
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S              10
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S               9
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S               8
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S               7
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S               6
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S               5
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S               4
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S               3
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S               2
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S               1
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___S               0
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF   
#define   UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___S               0

#define UMAC_TCL_R0_GXI_GXI_ERR_INTS              (0x00A449BC)
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS___RWC        QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS___POR     0x00000000
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S              24
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S              16
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S               8
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S               0
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS___M       0x01010101   
#define   UMAC_TCL_R0_GXI_GXI_ERR_INTS___S                     0

#define UMAC_TCL_R0_GXI_GXI_ERR_STATS             (0x00A449C0)
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS___RWC       QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS___POR    0x00000000
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S              16
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S               8
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S               0
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS___M      0x003F3F3F   
#define   UMAC_TCL_R0_GXI_GXI_ERR_STATS___S                    0

#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL       (0x00A449C4)
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S              24
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S               8
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S               0
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F   
#define   UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___S               0

#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL       (0x00A449C8)
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S              24
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S              16
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S               8
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S               0
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F   
#define   UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___S               0

#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL          (0x00A449CC)
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S              27
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S              26
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S              25
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S              24
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S              23
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S              20
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S              17
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S               9
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S               1
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S               0
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___M   0x0FFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___S                 0

#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL          (0x00A449D0)
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___RWC    QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S              16
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S               0
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___M   0xFFFF0001   
#define   UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___S                 0

#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS           (0x00A449D4)
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___POR  0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S               0
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___M    0x0000FFFF   
#define   UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___S                  0

#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS         (0x00A449D8)
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___RWC   QCSR_REG_RO    
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S              16
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S               0
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___S                0

#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL       (0x00A449DC)
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___S               0

#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL       (0x00A449E0)
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF   
#define   UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___S               0

#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A449E4)
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A449E8)
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A449EC)
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S               0

#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A449F0)
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S               0

#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL    (0x00A449F4)
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S              15
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S               8
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S               7
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S               0
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F   
#define   UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___S               0

#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW         (0x00A449F8)
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___POR 0x00000000
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___S               0
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___M  0xFFFFFFFF   
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___S                0

#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH        (0x00A449FC)
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___RWC  QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___POR 0x00000000
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___POR 0x00
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___S               0
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___M 0x000000FF   
#define   UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___S               0

#define UMAC_TCL_R0_ASE_GST_SIZE                  (0x00A44A00)
#define   UMAC_TCL_R0_ASE_GST_SIZE___RWC            QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_GST_SIZE___POR         0x00000000
#define   UMAC_TCL_R0_ASE_GST_SIZE__VAL___POR    0x00000
#define   UMAC_TCL_R0_ASE_GST_SIZE__VAL___M      0x000FFFFF
#define   UMAC_TCL_R0_ASE_GST_SIZE__VAL___S                    0
#define   UMAC_TCL_R0_ASE_GST_SIZE___M           0x000FFFFF   
#define   UMAC_TCL_R0_ASE_GST_SIZE___S                         0

#define UMAC_TCL_R0_ASE_SEARCH_CTRL               (0x00A44A04)
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL___POR      0x00003806
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___POR 0x06
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___S              16
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S              13
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S              12
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S              11
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S              10
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___S               9
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___S               8
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___S               0
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL___M        0xFFFF3FFF   
#define   UMAC_TCL_R0_ASE_SEARCH_CTRL___S                      0

#define UMAC_TCL_R0_ASE_WATCHDOG                  (0x00A44A08)
#define   UMAC_TCL_R0_ASE_WATCHDOG___RWC            QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_WATCHDOG___POR         0x0000FFFF
#define   UMAC_TCL_R0_ASE_WATCHDOG__STATUS___POR 0x0000
#define   UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___POR  0xFFFF
#define   UMAC_TCL_R0_ASE_WATCHDOG__STATUS___M   0xFFFF0000
#define   UMAC_TCL_R0_ASE_WATCHDOG__STATUS___S                16
#define   UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___M    0x0000FFFF
#define   UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___S                  0
#define   UMAC_TCL_R0_ASE_WATCHDOG___M           0xFFFFFFFF   
#define   UMAC_TCL_R0_ASE_WATCHDOG___S                         0

#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE           (0x00A44A0C)
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE___POR  0x00000000
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___POR 0x0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___S               9
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___S               8
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___M 0x00000080
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___S               7
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S               6
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___S               5
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___S               4
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___S               3
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___S               2
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___S               1
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___S               0
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE___M    0xFFFFFFFF   
#define   UMAC_TCL_R0_ASE_CLKGATE_DISABLE___S                  0

#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING        (0x00A44A10)
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___RWC  QCSR_REG_RO    
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___POR 0x00000000
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___POR 0x0
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___M 0x00000001
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___S               0
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___M 0x00000001   
#define   UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___S               0

#define UMAC_TCL_R1_CACHE_FLUSH                   (0x00A45000)
#define   UMAC_TCL_R1_CACHE_FLUSH___RWC             QCSR_REG_RW    
#define   UMAC_TCL_R1_CACHE_FLUSH___POR          0x00000000
#define   UMAC_TCL_R1_CACHE_FLUSH__STATUS___POR  0x0
#define   UMAC_TCL_R1_CACHE_FLUSH__ENABLE___POR  0x0
#define   UMAC_TCL_R1_CACHE_FLUSH__STATUS___M    0x00000002
#define   UMAC_TCL_R1_CACHE_FLUSH__STATUS___S                  1
#define   UMAC_TCL_R1_CACHE_FLUSH__ENABLE___M    0x00000001
#define   UMAC_TCL_R1_CACHE_FLUSH__ENABLE___S                  0
#define   UMAC_TCL_R1_CACHE_FLUSH___M            0x00000003   
#define   UMAC_TCL_R1_CACHE_FLUSH___S                          0

#define UMAC_TCL_R1_SM_STATES_IX_0                (0x00A45004)
#define   UMAC_TCL_R1_SM_STATES_IX_0___RWC          QCSR_REG_RO    
#define   UMAC_TCL_R1_SM_STATES_IX_0___POR       0x00000000
#define   UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___M 0x07000000
#define   UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___S              24
#define   UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___M 0x00E00000
#define   UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___S              21
#define   UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___M 0x001C0000
#define   UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___S              18
#define   UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___M 0x00038000
#define   UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___S              15
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___M 0x00007000
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___S              12
#define   UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___M 0x00000E00
#define   UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___S               9
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___M 0x000001C0
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___S               6
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___M 0x00000038
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___S               3
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___M 0x00000007
#define   UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___S               0
#define   UMAC_TCL_R1_SM_STATES_IX_0___M         0x07FFFFFF   
#define   UMAC_TCL_R1_SM_STATES_IX_0___S                       0

#define UMAC_TCL_R1_SM_STATES_IX_1                (0x00A45008)
#define   UMAC_TCL_R1_SM_STATES_IX_1___RWC          QCSR_REG_RO    
#define   UMAC_TCL_R1_SM_STATES_IX_1___POR       0x00000000
#define   UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___POR 0x0
#define   UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___M 0x00038000
#define   UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___S              15
#define   UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___M 0x00007000
#define   UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___S              12
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___M 0x00000E00
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___S               9
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___M 0x000001C0
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___S               6
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___M 0x00000038
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___S               3
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___M 0x00000007
#define   UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___S               0
#define   UMAC_TCL_R1_SM_STATES_IX_1___M         0x0003FFFF   
#define   UMAC_TCL_R1_SM_STATES_IX_1___S                       0

#define UMAC_TCL_R1_TESTBUS_CTRL_0                (0x00A4500C)
#define   UMAC_TCL_R1_TESTBUS_CTRL_0___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_TESTBUS_CTRL_0___POR       0x00000000
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___POR 0x00
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___POR 0x00
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___POR 0x0
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___POR 0x0
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___POR 0x00
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___POR 0x00
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x20000000
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S              29
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___M 0x1F800000
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___S              23
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___M 0x007C0000
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___S              18
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___M 0x0003C000
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___S              14
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___M 0x00003C00
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___S              10
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___M 0x000003E0
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___S               5
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___M 0x0000001F
#define   UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___S               0
#define   UMAC_TCL_R1_TESTBUS_CTRL_0___M         0x3FFFFFFF   
#define   UMAC_TCL_R1_TESTBUS_CTRL_0___S                       0

#define UMAC_TCL_R1_TESTBUS_LOW                   (0x00A45010)
#define   UMAC_TCL_R1_TESTBUS_LOW___RWC             QCSR_REG_RO    
#define   UMAC_TCL_R1_TESTBUS_LOW___POR          0x00000000
#define   UMAC_TCL_R1_TESTBUS_LOW__VAL___POR     0x00000000
#define   UMAC_TCL_R1_TESTBUS_LOW__VAL___M       0xFFFFFFFF
#define   UMAC_TCL_R1_TESTBUS_LOW__VAL___S                     0
#define   UMAC_TCL_R1_TESTBUS_LOW___M            0xFFFFFFFF   
#define   UMAC_TCL_R1_TESTBUS_LOW___S                          0

#define UMAC_TCL_R1_TESTBUS_HIGH                  (0x00A45014)
#define   UMAC_TCL_R1_TESTBUS_HIGH___RWC            QCSR_REG_RO    
#define   UMAC_TCL_R1_TESTBUS_HIGH___POR         0x00000000
#define   UMAC_TCL_R1_TESTBUS_HIGH__VAL___POR    0x00
#define   UMAC_TCL_R1_TESTBUS_HIGH__VAL___M      0x000000FF
#define   UMAC_TCL_R1_TESTBUS_HIGH__VAL___S                    0
#define   UMAC_TCL_R1_TESTBUS_HIGH___M           0x000000FF   
#define   UMAC_TCL_R1_TESTBUS_HIGH___S                         0

#define UMAC_TCL_R1_EVENTMASK_IX_0                (0x00A45018)
#define   UMAC_TCL_R1_EVENTMASK_IX_0___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_EVENTMASK_IX_0___POR       0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_0__VAL___POR  0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_0__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_0__VAL___S                  0
#define   UMAC_TCL_R1_EVENTMASK_IX_0___M         0xFFFFFFFF   
#define   UMAC_TCL_R1_EVENTMASK_IX_0___S                       0

#define UMAC_TCL_R1_EVENTMASK_IX_1                (0x00A4501C)
#define   UMAC_TCL_R1_EVENTMASK_IX_1___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_EVENTMASK_IX_1___POR       0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_1__VAL___POR  0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_1__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_1__VAL___S                  0
#define   UMAC_TCL_R1_EVENTMASK_IX_1___M         0xFFFFFFFF   
#define   UMAC_TCL_R1_EVENTMASK_IX_1___S                       0

#define UMAC_TCL_R1_EVENTMASK_IX_2                (0x00A45020)
#define   UMAC_TCL_R1_EVENTMASK_IX_2___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_EVENTMASK_IX_2___POR       0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_2__VAL___POR  0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_2__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_2__VAL___S                  0
#define   UMAC_TCL_R1_EVENTMASK_IX_2___M         0xFFFFFFFF   
#define   UMAC_TCL_R1_EVENTMASK_IX_2___S                       0

#define UMAC_TCL_R1_EVENTMASK_IX_3                (0x00A45024)
#define   UMAC_TCL_R1_EVENTMASK_IX_3___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_EVENTMASK_IX_3___POR       0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_3__VAL___POR  0x0000FFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_3__VAL___M    0xFFFFFFFF
#define   UMAC_TCL_R1_EVENTMASK_IX_3__VAL___S                  0
#define   UMAC_TCL_R1_EVENTMASK_IX_3___M         0xFFFFFFFF   
#define   UMAC_TCL_R1_EVENTMASK_IX_3___S                       0

#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL     (0x00A45028)
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define UMAC_TCL_R1_SPARE_REGISTER                (0x00A4502C)
#define   UMAC_TCL_R1_SPARE_REGISTER___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R1_SPARE_REGISTER___POR       0x00000000
#define   UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___POR 0x00000000
#define   UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___M 0xFFFFFFFF
#define   UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___S               0
#define   UMAC_TCL_R1_SPARE_REGISTER___M         0xFFFFFFFF   
#define   UMAC_TCL_R1_SPARE_REGISTER___S                       0

#define UMAC_TCL_R1_END_OF_TEST_CHECK             (0x00A45030)
#define   UMAC_TCL_R1_END_OF_TEST_CHECK___RWC       QCSR_REG_RW    
#define   UMAC_TCL_R1_END_OF_TEST_CHECK___POR    0x00000000
#define   UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TCL_R1_END_OF_TEST_CHECK___M      0x00000001   
#define   UMAC_TCL_R1_END_OF_TEST_CHECK___S                    0

#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK         (0x00A45034)
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___POR 0x00000000
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___M  0x00000001   
#define   UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___S                0

#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS      (0x00A45038)
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW    
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___S               0
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___M 0x00000001   
#define   UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___S               0

#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A4503C)
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S               0
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF   
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___S               0

#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A45040)
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S               0
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF   
#define   UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___S               0

#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A45044)
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S              10
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S               0
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF   
#define   UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___S               0

#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A45048)
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S              10
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S               5
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S               0
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF   
#define   UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___S               0

#define UMAC_TCL_R1_ASE_SM_STATES                 (0x00A4504C)
#define   UMAC_TCL_R1_ASE_SM_STATES___RWC           QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_SM_STATES___POR        0x00000000
#define   UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___POR 0x0
#define   UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___M 0x00300000
#define   UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___S              20
#define   UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000
#define   UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___S              18
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___M 0x00030000
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___S              16
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___S              14
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___M 0x00003800
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___S              11
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___M 0x00000700
#define   UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___S               8
#define   UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___M 0x0000000F
#define   UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___S               0
#define   UMAC_TCL_R1_ASE_SM_STATES___M          0x003FFF0F   
#define   UMAC_TCL_R1_ASE_SM_STATES___S                        0

#define UMAC_TCL_R1_ASE_CACHE_DEBUG               (0x00A45050)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG___POR      0x00000000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___POR 0x000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___M 0x000003FF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___S               0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG___M        0x000003FF   
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG___S                      0

#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS   (0x00A45054)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S               3
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S               2
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S               1
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___S               0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF   
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___S               0

#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A45058+0x4*(n))
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMIN 0    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMAX 31   
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ELEM 32   
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___POR 0x00000000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___S               0
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF   
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0       (0x00A45058)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1       (0x00A4505C)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2       (0x00A45060)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3       (0x00A45064)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4       (0x00A45068)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5       (0x00A4506C)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6       (0x00A45070)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7       (0x00A45074)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8       (0x00A45078)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9       (0x00A4507C)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10      (0x00A45080)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11      (0x00A45084)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12      (0x00A45088)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13      (0x00A4508C)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14      (0x00A45090)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15      (0x00A45094)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16      (0x00A45098)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17      (0x00A4509C)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18      (0x00A450A0)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19      (0x00A450A4)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20      (0x00A450A8)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21      (0x00A450AC)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22      (0x00A450B0)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23      (0x00A450B4)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24      (0x00A450B8)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25      (0x00A450BC)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26      (0x00A450C0)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27      (0x00A450C4)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28      (0x00A450C8)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29      (0x00A450CC)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30      (0x00A450D0)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___S               0
#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31      (0x00A450D4)
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO    
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF
#define   UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___S               0

#define UMAC_TCL_R2_SW2TCL1_RING_HP               (0x00A46000)
#define   UMAC_TCL_R2_SW2TCL1_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL1_RING_HP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL1_RING_HP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL1_RING_HP___S                      0

#define UMAC_TCL_R2_SW2TCL1_RING_TP               (0x00A46004)
#define   UMAC_TCL_R2_SW2TCL1_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL1_RING_TP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL1_RING_TP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL1_RING_TP___S                      0

#define UMAC_TCL_R2_SW2TCL2_RING_HP               (0x00A46008)
#define   UMAC_TCL_R2_SW2TCL2_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL2_RING_HP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL2_RING_HP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL2_RING_HP___S                      0

#define UMAC_TCL_R2_SW2TCL2_RING_TP               (0x00A4600C)
#define   UMAC_TCL_R2_SW2TCL2_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL2_RING_TP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL2_RING_TP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL2_RING_TP___S                      0

#define UMAC_TCL_R2_SW2TCL3_RING_HP               (0x00A46010)
#define   UMAC_TCL_R2_SW2TCL3_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL3_RING_HP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL3_RING_HP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL3_RING_HP___S                      0

#define UMAC_TCL_R2_SW2TCL3_RING_TP               (0x00A46014)
#define   UMAC_TCL_R2_SW2TCL3_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL3_RING_TP___POR      0x00000000
#define   UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL3_RING_TP___M        0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL3_RING_TP___S                      0

#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP         (0x00A46018)
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___POR 0x00000000
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___M  0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___S                0

#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP         (0x00A4601C)
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___RWC   QCSR_REG_RW    
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___POR 0x00000000
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___POR 0x00000
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___M 0x000FFFFF
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___M  0x000FFFFF   
#define   UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___S                0

#define UMAC_TCL_R2_FW2TCL1_RING_HP               (0x00A46020)
#define   UMAC_TCL_R2_FW2TCL1_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_FW2TCL1_RING_HP___POR      0x00000000
#define   UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_FW2TCL1_RING_HP___M        0x0000FFFF   
#define   UMAC_TCL_R2_FW2TCL1_RING_HP___S                      0

#define UMAC_TCL_R2_FW2TCL1_RING_TP               (0x00A46024)
#define   UMAC_TCL_R2_FW2TCL1_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_FW2TCL1_RING_TP___POR      0x00000000
#define   UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_FW2TCL1_RING_TP___M        0x0000FFFF   
#define   UMAC_TCL_R2_FW2TCL1_RING_TP___S                      0

#define UMAC_TCL_R2_TCL2TQM_RING_HP               (0x00A46028)
#define   UMAC_TCL_R2_TCL2TQM_RING_HP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL2TQM_RING_HP___POR      0x00000000
#define   UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_TCL2TQM_RING_HP___M        0x0000FFFF   
#define   UMAC_TCL_R2_TCL2TQM_RING_HP___S                      0

#define UMAC_TCL_R2_TCL2TQM_RING_TP               (0x00A4602C)
#define   UMAC_TCL_R2_TCL2TQM_RING_TP___RWC         QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL2TQM_RING_TP___POR      0x00000000
#define   UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_TCL2TQM_RING_TP___M        0x0000FFFF   
#define   UMAC_TCL_R2_TCL2TQM_RING_TP___S                      0

#define UMAC_TCL_R2_TCL_STATUS1_RING_HP           (0x00A46030)
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP___POR  0x00000000
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP___M    0x0000FFFF   
#define   UMAC_TCL_R2_TCL_STATUS1_RING_HP___S                  0

#define UMAC_TCL_R2_TCL_STATUS1_RING_TP           (0x00A46034)
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP___POR  0x00000000
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP___M    0x0000FFFF   
#define   UMAC_TCL_R2_TCL_STATUS1_RING_TP___S                  0

#define UMAC_TCL_R2_TCL_STATUS2_RING_HP           (0x00A46038)
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP___POR  0x00000000
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP___M    0x0000FFFF   
#define   UMAC_TCL_R2_TCL_STATUS2_RING_HP___S                  0

#define UMAC_TCL_R2_TCL_STATUS2_RING_TP           (0x00A4603C)
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP___RWC     QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP___POR  0x00000000
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP___M    0x0000FFFF   
#define   UMAC_TCL_R2_TCL_STATUS2_RING_TP___S                  0

#define UMAC_TCL_R2_TCL2FW_RING_HP                (0x00A46040)
#define   UMAC_TCL_R2_TCL2FW_RING_HP___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL2FW_RING_HP___POR       0x00000000
#define   UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___S               0
#define   UMAC_TCL_R2_TCL2FW_RING_HP___M         0x0000FFFF   
#define   UMAC_TCL_R2_TCL2FW_RING_HP___S                       0

#define UMAC_TCL_R2_TCL2FW_RING_TP                (0x00A46044)
#define   UMAC_TCL_R2_TCL2FW_RING_TP___RWC          QCSR_REG_RW    
#define   UMAC_TCL_R2_TCL2FW_RING_TP___POR       0x00000000
#define   UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___POR 0x0000
#define   UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___S               0
#define   UMAC_TCL_R2_TCL2FW_RING_TP___M         0x0000FFFF   
#define   UMAC_TCL_R2_TCL2FW_RING_TP___S                       0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0             (0x00A47000)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___POR    0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1             (0x00A47004)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___POR    0x0000002B
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2             (0x00A47008)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___POR    0x0000003C
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3             (0x00A4700C)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___POR    0x00000033
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4             (0x00A47010)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___POR    0x00000887
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5             (0x00A47014)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___RWC       QCSR_REG_RO    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___POR    0x0000082C
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6             (0x00A47018)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___RWC       QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___POR    0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7             (0x00A4701C)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___RWC       QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___POR    0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8             (0x00A47020)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___RWC       QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___POR    0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9             (0x00A47024)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___RWC       QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___POR    0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___M      0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___S                    0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10            (0x00A47028)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___S                   0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11            (0x00A4702C)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___S                   0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12            (0x00A47030)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___S                   0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13            (0x00A47034)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___S                   0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14            (0x00A47038)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___S                   0

#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15            (0x00A4703C)
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___POR   0x00000000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S               8
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S               0
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___M     0x000FFFFF   
#define   UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___S                   0

#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN            (0x00A47040)
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___RWC      QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___POR   0x00000000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S               4
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S               0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___M     0x000000FF   
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___S                   0

#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0  (0x00A47044)
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S              24
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S              16
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S               8
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S               0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF   
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S               0

#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1  (0x00A47048)
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S              24
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S              16
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S               8
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S               0
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF   
#define   UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S               0

#define UMAC_CP_R0_IPV6_CONFIG                    (0x00A4704C)
#define   UMAC_CP_R0_IPV6_CONFIG___RWC              QCSR_REG_RW    
#define   UMAC_CP_R0_IPV6_CONFIG___POR           0x00000080
#define   UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0
#define   UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0
#define   UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0
#define   UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0
#define   UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80
#define   UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800
#define   UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S              11
#define   UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400
#define   UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S              10
#define   UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200
#define   UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S               9
#define   UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100
#define   UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S               8
#define   UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF
#define   UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S               0
#define   UMAC_CP_R0_IPV6_CONFIG___M             0x00000FFF   
#define   UMAC_CP_R0_IPV6_CONFIG___S                           0

#define UMAC_CP_R0_COMMIT_TLV_CONFIG              (0x00A47050)
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG___RWC        QCSR_REG_RO    
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG___POR     0x00010040
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___POR 0x100
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___POR 0x40
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___M 0x0001FF00
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___S               8
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___M 0x000000FF
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___S               0
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG___M       0x0001FFFF   
#define   UMAC_CP_R0_COMMIT_TLV_CONFIG___S                     0

#define UMAC_CP_R0_CLKGATE_DISABLE                (0x00A47054)
#define   UMAC_CP_R0_CLKGATE_DISABLE___RWC          QCSR_REG_RW    
#define   UMAC_CP_R0_CLKGATE_DISABLE___POR       0x00000000
#define   UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000
#define   UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__ETH___POR  0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__APB___POR  0x0
#define   UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00
#define   UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S               8
#define   UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080
#define   UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___S               7
#define   UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___M  0x00000040
#define   UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___S                6
#define   UMAC_CP_R0_CLKGATE_DISABLE__ETH___M    0x00000020
#define   UMAC_CP_R0_CLKGATE_DISABLE__ETH___S                  5
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S               4
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008
#define   UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S               3
#define   UMAC_CP_R0_CLKGATE_DISABLE__WIFI___M   0x00000004
#define   UMAC_CP_R0_CLKGATE_DISABLE__WIFI___S                 2
#define   UMAC_CP_R0_CLKGATE_DISABLE__CORE___M   0x00000002
#define   UMAC_CP_R0_CLKGATE_DISABLE__CORE___S                 1
#define   UMAC_CP_R0_CLKGATE_DISABLE__APB___M    0x00000001
#define   UMAC_CP_R0_CLKGATE_DISABLE__APB___S                  0
#define   UMAC_CP_R0_CLKGATE_DISABLE___M         0xFFFFFFFF   
#define   UMAC_CP_R0_CLKGATE_DISABLE___S                       0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0         (0x00A47058)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1         (0x00A4705C)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2         (0x00A47060)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3         (0x00A47064)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0         (0x00A47068)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1         (0x00A4706C)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2         (0x00A47070)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3         (0x00A47074)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4         (0x00A47078)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5         (0x00A4707C)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6         (0x00A47080)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7         (0x00A47084)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8         (0x00A47088)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9         (0x00A4708C)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___M 0xFFFFFFFF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___M  0xFFFFFFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___S                0

#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6         (0x00A47090)
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___RWC   QCSR_REG_RW    
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___POR 0x00000000
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___POR 0x00
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___POR 0x00
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___M 0x0000FF00
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___S               8
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___M 0x000000FF
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___S               0
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___M  0x0000FFFF   
#define   UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___S                0

#define UMAC_CP_R0_MISC_CONFIG                    (0x00A47094)
#define   UMAC_CP_R0_MISC_CONFIG___RWC              QCSR_REG_RW    
#define   UMAC_CP_R0_MISC_CONFIG___POR           0x0001E110
#define   UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0
#define   UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C
#define   UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0
#define   UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0
#define   UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1
#define   UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___POR 0x0
#define   UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0
#define   UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10
#define   UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000
#define   UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S              27
#define   UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800
#define   UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S              11
#define   UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400
#define   UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___S              10
#define   UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200
#define   UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___S               9
#define   UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100
#define   UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S               8
#define   UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___M 0x000000C0
#define   UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___S               6
#define   UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020
#define   UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S               5
#define   UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F
#define   UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S               0
#define   UMAC_CP_R0_MISC_CONFIG___M             0x0FFFFFFF   
#define   UMAC_CP_R0_MISC_CONFIG___S                           0

#define UMAC_CP_R0_WATCHDOG_TIMER                 (0x00A47098)
#define   UMAC_CP_R0_WATCHDOG_TIMER___RWC           QCSR_REG_RW    
#define   UMAC_CP_R0_WATCHDOG_TIMER___POR        0x00000000
#define   UMAC_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000
#define   UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0
#define   UMAC_CP_R0_WATCHDOG_TIMER__VALUE___M   0xFFFFFFFE
#define   UMAC_CP_R0_WATCHDOG_TIMER__VALUE___S                 1
#define   UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___M  0x00000001
#define   UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___S                0
#define   UMAC_CP_R0_WATCHDOG_TIMER___M          0xFFFFFFFF   
#define   UMAC_CP_R0_WATCHDOG_TIMER___S                        0

#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL      (0x00A48000)
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define UMAC_CP_R1_SM_STATES                      (0x00A48004)
#define   UMAC_CP_R1_SM_STATES___RWC                QCSR_REG_RO    
#define   UMAC_CP_R1_SM_STATES___POR             0x00000000
#define   UMAC_CP_R1_SM_STATES__MISC___POR       0x000000
#define   UMAC_CP_R1_SM_STATES__STATE_INFO___POR 0x00
#define   UMAC_CP_R1_SM_STATES__STATE_MAIN___POR 0x00
#define   UMAC_CP_R1_SM_STATES__MISC___M         0xFFFFFC00
#define   UMAC_CP_R1_SM_STATES__MISC___S                      10
#define   UMAC_CP_R1_SM_STATES__STATE_INFO___M   0x000003E0
#define   UMAC_CP_R1_SM_STATES__STATE_INFO___S                 5
#define   UMAC_CP_R1_SM_STATES__STATE_MAIN___M   0x0000001F
#define   UMAC_CP_R1_SM_STATES__STATE_MAIN___S                 0
#define   UMAC_CP_R1_SM_STATES___M               0xFFFFFFFF   
#define   UMAC_CP_R1_SM_STATES___S                             0

#define UMAC_CP_R1_END_OF_TEST_CHECK              (0x00A48008)
#define   UMAC_CP_R1_END_OF_TEST_CHECK___RWC        QCSR_REG_RW    
#define   UMAC_CP_R1_END_OF_TEST_CHECK___POR     0x00000000
#define   UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   UMAC_CP_R1_END_OF_TEST_CHECK___M       0x00000001   
#define   UMAC_CP_R1_END_OF_TEST_CHECK___S                     0


#define WMAC0                       (0x00A80000)

#define WMAC0_PDG_R0_CONFIG                       (0x00A80000)
#define   WMAC0_PDG_R0_CONFIG___RWC                 QCSR_REG_RW    
#define   WMAC0_PDG_R0_CONFIG___POR              0x00000010
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___POR 0x0
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___POR 0x00
#define   WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___POR 0x10
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___M 0x00002000
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___S              13
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___M 0x00001F00
#define   WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___S               8
#define   WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___M  0x000000FF
#define   WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___S                0
#define   WMAC0_PDG_R0_CONFIG___M                0x00003FFF   
#define   WMAC0_PDG_R0_CONFIG___S                              0

#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE           (0x00A80004)
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE___RWC     QCSR_REG_RW    
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE___POR  0x00000000
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___POR 0x0
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___POR 0x0
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___POR 0x0
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___POR 0x00
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___M 0x00000200
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___S               9
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___M 0x00000100
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___S               8
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___M 0x00000080
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___S               7
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___M 0x0000007F
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___S               0
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE___M    0x000003FF   
#define   WMAC0_PDG_R0_SCRAMBLING_OVERIDE___S                  0

#define WMAC0_PDG_R0_CLKGATE_DISABLE              (0x00A80008)
#define   WMAC0_PDG_R0_CLKGATE_DISABLE___RWC        QCSR_REG_RW    
#define   WMAC0_PDG_R0_CLKGATE_DISABLE___POR     0x80000000
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x1
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___POR 0x0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___M 0x00000080
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___S               7
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___M 0x00000040
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___S               6
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___M 0x00000020
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___S               5
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___M 0x00000010
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___S               4
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___M 0x00000008
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___S               3
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___M 0x00000004
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___S               2
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___M 0x00000002
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___S               1
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___M 0x00000001
#define   WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___S               0
#define   WMAC0_PDG_R0_CLKGATE_DISABLE___M       0xC00000FF   
#define   WMAC0_PDG_R0_CLKGATE_DISABLE___S                     0

#define WMAC0_PDG_R0_SLOT_TIME                    (0x00A8000C)
#define   WMAC0_PDG_R0_SLOT_TIME___RWC              QCSR_REG_RW    
#define   WMAC0_PDG_R0_SLOT_TIME___POR           0x00000009
#define   WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___POR 0x0009
#define   WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___M 0x0000FFFF
#define   WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___S               0
#define   WMAC0_PDG_R0_SLOT_TIME___M             0x0000FFFF   
#define   WMAC0_PDG_R0_SLOT_TIME___S                           0

#define WMAC0_PDG_R0_FEATURE_ENABLE               (0x00A80010)
#define   WMAC0_PDG_R0_FEATURE_ENABLE___RWC         QCSR_REG_RW    
#define   WMAC0_PDG_R0_FEATURE_ENABLE___POR      0x00396300
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ECO___POR 0x000E
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ECO___M   0xFFFC0000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ECO___S                18
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___M 0x00020000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___S              17
#define   WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___M 0x00010000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___S              16
#define   WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___M 0x00008000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___S              15
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___M 0x00004000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___S              14
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___M 0x00002000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___S              13
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___M 0x00001000
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___S              12
#define   WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___M 0x00000800
#define   WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___S              11
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___M 0x00000400
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___S              10
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___M 0x00000200
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___S               9
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___M 0x00000100
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___S               8
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___M 0x00000080
#define   WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___S               7
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___M 0x00000040
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___S               6
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___M 0x00000020
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___S               5
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___M 0x00000010
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___S               4
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___M 0x00000008
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___S               3
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___M 0x00000004
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___S               2
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___M 0x00000002
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___S               1
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___M 0x00000001
#define   WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___S               0
#define   WMAC0_PDG_R0_FEATURE_ENABLE___M        0xFFFFFFFF   
#define   WMAC0_PDG_R0_FEATURE_ENABLE___S                      0

#define WMAC0_PDG_R0_FEATURE_ENABLE_II            (0x00A80014)
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II___POR   0x00005973
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___POR 0x0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___POR 0x1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___M 0x00004000
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___S              14
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___M 0x00002000
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___S              13
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___M 0x00001000
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___S              12
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___M 0x00000800
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___S              11
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___M 0x00000400
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___S              10
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___M 0x00000200
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___S               9
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___M 0x00000100
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___S               8
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___M 0x00000080
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___S               7
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___M 0x00000040
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___S               6
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___M 0x00000020
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___S               5
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___M 0x00000010
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___S               4
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___M 0x00000008
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___S               3
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___M 0x00000004
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___S               2
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___M 0x00000002
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___S               1
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___M 0x00000001
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___S               0
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II___M     0x00007FFF   
#define   WMAC0_PDG_R0_FEATURE_ENABLE_II___S                   0

#define WMAC0_PDG_R0_SPARE_REG                    (0x00A80018)
#define   WMAC0_PDG_R0_SPARE_REG___RWC              QCSR_REG_RW    
#define   WMAC0_PDG_R0_SPARE_REG___POR           0x00000000
#define   WMAC0_PDG_R0_SPARE_REG__ECO___POR      0x0000
#define   WMAC0_PDG_R0_SPARE_REG__ECO___M        0x0000FFFF
#define   WMAC0_PDG_R0_SPARE_REG__ECO___S                      0
#define   WMAC0_PDG_R0_SPARE_REG___M             0x0000FFFF   
#define   WMAC0_PDG_R0_SPARE_REG___S                           0

#define WMAC0_PDG_R0_MASK_TIMER                   (0x00A8001C)
#define   WMAC0_PDG_R0_MASK_TIMER___RWC             QCSR_REG_RW    
#define   WMAC0_PDG_R0_MASK_TIMER___POR          0x00000001
#define   WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___POR 0x01
#define   WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___M 0x000000FF
#define   WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___S               0
#define   WMAC0_PDG_R0_MASK_TIMER___M            0x000000FF   
#define   WMAC0_PDG_R0_MASK_TIMER___S                          0

#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT            (0x00A80020)
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___POR   0x000048C0
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___POR 0x48C0
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___M     0x0000FFFF   
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___S                   0

#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT       (0x00A80024)
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___POR 0x00000C1C
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___POR 0x0C1C
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___S               0

#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT     (0x00A80028)
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___POR 0x0000156C
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___POR 0x156C
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___S               0

#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT          (0x00A8002C)
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___POR 0x0000156C
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___POR 0x156C
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___M   0x0000FFFF   
#define   WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___S                 0

#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT (0x00A80030)
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___POR 0x0000156C
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___POR 0x156C
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___S               0

#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT (0x00A80034)
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___POR 0x0000156C
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___POR 0x156C
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___S               0
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___S               0

#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY        (0x00A80038)
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___POR 0x00000000
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___POR 0x0000
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___M 0x0000FFFF
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___S               0
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___M 0x0000FFFF   
#define   WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___S               0

#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY   (0x00A8003C)
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___POR 0x00000000
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___POR 0x0000
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___S               0
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___S               0

#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY (0x00A80040)
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___POR 0x00000000
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___POR 0x0000
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___S               0
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___S               0

#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY (0x00A80044)
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___POR 0x00000000
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___POR 0x0000
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___S               0
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___S               0

#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY (0x00A80048)
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___POR 0x00000000
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___POR 0x0000
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___S               0
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___S               0

#define WMAC0_PDG_R0_PROTECTION_SIFS              (0x00A8004C)
#define   WMAC0_PDG_R0_PROTECTION_SIFS___RWC        QCSR_REG_RW    
#define   WMAC0_PDG_R0_PROTECTION_SIFS___POR     0x00000000
#define   WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___POR 0x00
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___POR 0x00
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___POR 0x00
#define   WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___M 0x00FF0000
#define   WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___S              16
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___M 0x0000FF00
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___S               8
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___M 0x000000FF
#define   WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___S               0
#define   WMAC0_PDG_R0_PROTECTION_SIFS___M       0x00FFFFFF   
#define   WMAC0_PDG_R0_PROTECTION_SIFS___S                     0

#define WMAC0_PDG_R0_CAL_CTRL                     (0x00A80050)
#define   WMAC0_PDG_R0_CAL_CTRL___RWC               QCSR_REG_RW    
#define   WMAC0_PDG_R0_CAL_CTRL___POR            0x013F010A
#define   WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___POR 0x0
#define   WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___POR 0x13F
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___POR 0x01
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___POR 0x0A
#define   WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___M 0x02000000
#define   WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___S              25
#define   WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___M 0x01FF0000
#define   WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___S              16
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___M 0x0000FF00
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___S               8
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___M 0x0000003F
#define   WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___S               0
#define   WMAC0_PDG_R0_CAL_CTRL___M              0x03FFFF3F   
#define   WMAC0_PDG_R0_CAL_CTRL___S                            0

#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE          (0x00A80054)
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___POR 0x00000000
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___POR 0x0
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___M 0x00000001
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___S               0
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___M   0x00000001   
#define   WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___S                 0

#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON        (0x00A80058)
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___POR 0x2B1B1212
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___POR 0x2B
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___POR 0x1B
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___POR 0x12
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___POR 0x12
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___M 0x3F000000
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___S              24
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___M 0x003F0000
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___S              16
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___M 0x00003F00
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___S               8
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___M 0x0000003F
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___S               0
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___M 0x3F3F3F3F   
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___S               0

#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER          (0x00A8005C)
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___POR 0x00001F34
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___POR 0x1F
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___POR 0x34
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___M 0x00003F00
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___S               8
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___M 0x0000003F
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___S               0
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___M   0x00003F3F   
#define   WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___S                 0

#define WMAC0_PDG_R0_RESP_MODE_CONFIG             (0x00A80060)
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG___POR    0x00000000
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___M 0x00000002
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___S               1
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___M 0x00000001
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___S               0
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG___M      0x00000003   
#define   WMAC0_PDG_R0_RESP_MODE_CONFIG___S                    0

#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG         (0x00A80064)
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___POR 0x02100000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___POR 0x1
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___POR 0x1
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___M 0x08000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___S              27
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___M 0x04000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___S              26
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___M 0x02000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___S              25
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___M 0x00400000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___S              22
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___M 0x00200000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___S              21
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___M 0x00100000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___S              20
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___M 0x00080000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___S              19
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___M 0x00040000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___S              18
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___M 0x00020000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___S              17
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___M 0x00010000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___S              16
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___M 0x0000FF00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___S               8
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___M 0x000000FF
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___M  0x0E7FFFFF   
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___S                0

#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1        (0x00A80068)
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___POR 0x00000001
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___POR 0x00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___POR 0x01
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___M 0x0000FF00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___S               8
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___M 0x000000FF
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___S               0

#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1    (0x00A8006C)
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___POR 0x00000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___POR 0x00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___POR 0x000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___M 0x40000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___S              30
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___M 0x3F000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___S              24
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___M 0x7FFFFFFF   
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___S               0

#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2    (0x00A80070)
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___POR 0x00000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___POR 0x00
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___POR 0x000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___M 0x40000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___S              30
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___M 0x3F000000
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___S              24
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___M 0x7FFFFFFF   
#define   WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___S               0

#define WMAC0_PDG_R0_HE_CONFIG                    (0x00A80074)
#define   WMAC0_PDG_R0_HE_CONFIG___RWC              QCSR_REG_RW    
#define   WMAC0_PDG_R0_HE_CONFIG___POR           0x000C01FF
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___POR 0x1
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___POR 0x1
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___POR 0x0
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___POR 0x1
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___POR 0x1
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___POR 0x7F
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___M 0x00080000
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___S              19
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___M 0x00040000
#define   WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___S              18
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___M 0x00020000
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___S              17
#define   WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___M 0x0001E000
#define   WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___S              13
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___M 0x00001000
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___S              12
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___M 0x00000800
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___S              11
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___M 0x00000400
#define   WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___S              10
#define   WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___M 0x00000200
#define   WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___S               9
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___M 0x00000100
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___S               8
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___M   0x00000080
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___S                 7
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___M 0x0000007F
#define   WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___S               0
#define   WMAC0_PDG_R0_HE_CONFIG___M             0x000FFFFF   
#define   WMAC0_PDG_R0_HE_CONFIG___S                           0

#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG          (0x00A80078)
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___POR 0x00000000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___POR 0x000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___POR 0x0
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___POR 0x0
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___POR 0x0000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___M 0x1FF00000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___S              20
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___M 0x00080000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___S              19
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___M 0x00070000
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___S              16
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___M 0x0000FFFF
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___S               0
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___M   0x1FFFFFFF   
#define   WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___S                 0

#define WMAC0_PDG_R0_UPC_CONFIG                   (0x00A8007C)
#define   WMAC0_PDG_R0_UPC_CONFIG___RWC             QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_CONFIG___POR          0x00003F36
#define   WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___POR 0x00
#define   WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___POR 0x0
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___POR 0x00
#define   WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___POR 0x0
#define   WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___POR 0x0
#define   WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___POR 0x1F
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___POR 0x136
#define   WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___S              24
#define   WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___M 0x00800000
#define   WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___S              23
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___M 0x007F0000
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___S              16
#define   WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___M 0x00008000
#define   WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___S              15
#define   WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___M 0x00004000
#define   WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___S              14
#define   WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___M 0x00003E00
#define   WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___S               9
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___M 0x000001FF
#define   WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___S               0
#define   WMAC0_PDG_R0_UPC_CONFIG___M            0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_CONFIG___S                          0

#define WMAC0_PDG_R0_UPC_CONFIG2                  (0x00A80080)
#define   WMAC0_PDG_R0_UPC_CONFIG2___RWC            QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_CONFIG2___POR         0x00000000
#define   WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___POR 0x00
#define   WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___S               8
#define   WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___S               0
#define   WMAC0_PDG_R0_UPC_CONFIG2___M           0x0000FFFF   
#define   WMAC0_PDG_R0_UPC_CONFIG2___S                         0

#define WMAC0_PDG_R0_UPC_OVERRIDE                 (0x00A80084)
#define   WMAC0_PDG_R0_UPC_OVERRIDE___RWC           QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_OVERRIDE___POR        0x00000000
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___POR 0x00
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___POR 0x00
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___M 0x00008000
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___S              15
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___M 0x00007E00
#define   WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___S               9
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___M 0x00000100
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___S               8
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___S               0
#define   WMAC0_PDG_R0_UPC_OVERRIDE___M          0x0000FFFF   
#define   WMAC0_PDG_R0_UPC_OVERRIDE___S                        0

#define WMAC0_PDG_R0_UPC_STATUS                   (0x00A80088)
#define   WMAC0_PDG_R0_UPC_STATUS___RWC             QCSR_REG_RO    
#define   WMAC0_PDG_R0_UPC_STATUS___POR          0x00000000
#define   WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___POR 0x00
#define   WMAC0_PDG_R0_UPC_STATUS__NRX___POR     0x0
#define   WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___POR 0x00
#define   WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___POR 0x00
#define   WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___POR 0x0
#define   WMAC0_PDG_R0_UPC_STATUS__HEADROOM___POR 0x00
#define   WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___S              24
#define   WMAC0_PDG_R0_UPC_STATUS__NRX___M       0x00F00000
#define   WMAC0_PDG_R0_UPC_STATUS__NRX___S                    20
#define   WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___M 0x000FF000
#define   WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___S              12
#define   WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___M  0x00000FC0
#define   WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___S                6
#define   WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___M 0x00000020
#define   WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___S               5
#define   WMAC0_PDG_R0_UPC_STATUS__HEADROOM___M  0x0000001F
#define   WMAC0_PDG_R0_UPC_STATUS__HEADROOM___S                0
#define   WMAC0_PDG_R0_UPC_STATUS___M            0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_STATUS___S                          0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0             (0x00A8008C)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1             (0x00A80090)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2             (0x00A80094)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3             (0x00A80098)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4             (0x00A8009C)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5             (0x00A800A0)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6             (0x00A800A4)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7             (0x00A800A8)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8             (0x00A800AC)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9             (0x00A800B0)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___RWC       QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___POR    0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___M      0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___S                    0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10            (0x00A800B4)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___POR   0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___M     0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___S                   0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11            (0x00A800B8)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___POR   0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___M     0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___S                   0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12            (0x00A800BC)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___POR   0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___M     0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___S                   0

#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13            (0x00A800C0)
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___POR   0x00000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___POR 0x00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___S              24
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___S              16
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___S               8
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___S               0
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___M     0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___S                   0

#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3           (0x00A800C4)
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___RWC     QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___POR  0x00000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___S              24
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___S              16
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___S               8
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___S               0
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___M    0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___S                  0

#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7           (0x00A800C8)
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___RWC     QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___POR  0x00000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___S              24
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___S              16
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___S               8
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___S               0
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___M    0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___S                  0

#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11          (0x00A800CC)
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___POR 0x00000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___M 0xFF000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___S              24
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___S              16
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___S               8
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___S               0
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___M   0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___S                 0

#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13         (0x00A800D0)
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___POR 0x00000000
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___POR 0x00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___M 0x0000FF00
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___S               8
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___S               0
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___M  0x0000FFFF   
#define   WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___S                0

#define WMAC0_PDG_R0_REGULATORY_PMAX              (0x00A800D4)
#define   WMAC0_PDG_R0_REGULATORY_PMAX___RWC        QCSR_REG_RW    
#define   WMAC0_PDG_R0_REGULATORY_PMAX___POR     0x00000000
#define   WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___POR 0x00
#define   WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___POR 0x00
#define   WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___M 0x0000FF00
#define   WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___S               8
#define   WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___M 0x000000FF
#define   WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___S               0
#define   WMAC0_PDG_R0_REGULATORY_PMAX___M       0x0000FFFF   
#define   WMAC0_PDG_R0_REGULATORY_PMAX___S                     0

#define WMAC0_PDG_R0_SPATIAL_REUSE                (0x00A800D8)
#define   WMAC0_PDG_R0_SPATIAL_REUSE___RWC          QCSR_REG_RW    
#define   WMAC0_PDG_R0_SPATIAL_REUSE___POR       0x02220000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___POR 0x0
#define   WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___POR 0x0
#define   WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___POR 0x4
#define   WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___POR 0x4
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___POR 0x0
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___POR 0x1
#define   WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___POR 0x0
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___POR 0x00
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___POR 0x00
#define   WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___M 0x10000000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___S              28
#define   WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___M 0x08000000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___S              27
#define   WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___M 0x07800000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___S              23
#define   WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___M 0x00780000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___S              19
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___M 0x00040000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___S              18
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___M 0x00020000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___S              17
#define   WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___M 0x00010000
#define   WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___S              16
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___M 0x0000FF00
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___S               8
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___M 0x000000FF
#define   WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___S               0
#define   WMAC0_PDG_R0_SPATIAL_REUSE___M         0x1FFFFFFF   
#define   WMAC0_PDG_R0_SPATIAL_REUSE___S                       0

#define WMAC0_PDG_R0_UPC_SR                       (0x00A800DC)
#define   WMAC0_PDG_R0_UPC_SR___RWC                 QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_SR___POR              0x0000007F
#define   WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___M 0x000000FF
#define   WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___S               0
#define   WMAC0_PDG_R0_UPC_SR___M                0x000000FF   
#define   WMAC0_PDG_R0_UPC_SR___S                              0

#define WMAC0_PDG_R0_UPC_SR_PBASE0                (0x00A800E0)
#define   WMAC0_PDG_R0_UPC_SR_PBASE0___RWC          QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_SR_PBASE0___POR       0x7F7F7F7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___M  0xFF000000
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___S               24
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___M  0x00FF0000
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___S               16
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___M   0x0000FF00
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___S                 8
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___M   0x000000FF
#define   WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___S                 0
#define   WMAC0_PDG_R0_UPC_SR_PBASE0___M         0xFFFFFFFF   
#define   WMAC0_PDG_R0_UPC_SR_PBASE0___S                       0

#define WMAC0_PDG_R0_UPC_SR_PBASE1                (0x00A800E4)
#define   WMAC0_PDG_R0_UPC_SR_PBASE1___RWC          QCSR_REG_RW    
#define   WMAC0_PDG_R0_UPC_SR_PBASE1___POR       0x007F7F7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___POR 0x7F
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___M 0x00FF0000
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___S              16
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___M  0x0000FF00
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___S                8
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___M  0x000000FF
#define   WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___S                0
#define   WMAC0_PDG_R0_UPC_SR_PBASE1___M         0x00FFFFFF   
#define   WMAC0_PDG_R0_UPC_SR_PBASE1___S                       0

#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU          (0x00A800E8)
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___POR 0x25120904
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___POR 0x25
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___POR 0x12
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___POR 0x09
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___POR 0x4
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___M 0x7F000000
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___S              24
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___M 0x003F0000
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___S              16
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___M 0x00001F00
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___S               8
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___M 0x0000000F
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___S               0
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___M   0x7F3F1F0F   
#define   WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___S                 0

#define WMAC0_PDG_R0_BLOCK_TRIG_RESP              (0x00A800EC)
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP___RWC        QCSR_REG_RW    
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP___POR     0x00000000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___POR 0x0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___M 0x00800000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___S              23
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___M 0x00400000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___S              22
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___M 0x00200000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___S              21
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___M 0x00100000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___S              20
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___M 0x00080000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___S              19
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___M 0x00040000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___S              18
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___M 0x00020000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___S              17
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___M 0x00010000
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___S              16
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___M 0x00000800
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___S              11
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___M 0x00000400
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___S              10
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___M 0x00000200
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___S               9
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___M 0x00000100
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___S               8
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___M 0x00000008
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___S               3
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___M 0x00000004
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___S               2
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___M 0x00000002
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___S               1
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___M 0x00000001
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___S               0
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP___M       0x00FF0F0F   
#define   WMAC0_PDG_R0_BLOCK_TRIG_RESP___S                     0

#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE        (0x00A800F0)
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___POR 0x00000000
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___POR 0x0000
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___M 0x0000FFFF
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___M 0x0000FFFF   
#define   WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___S               0

#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION       (0x00A800F4)
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___POR 0x00000000
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___M 0x00000001
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___M 0x00000001   
#define   WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___S               0

#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH (0x00A800F8)
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___POR 0x00FAC688
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___POR 0x7
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___POR 0x6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___POR 0x5
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___POR 0x4
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___POR 0x3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___POR 0x2
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___POR 0x1
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___POR 0x0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___M 0x00E00000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___S              21
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___M 0x001C0000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___S              18
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___M 0x00038000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___S              15
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___M 0x00007000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___S              12
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___M 0x00000E00
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___S               9
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___M 0x000001C0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___S               6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___M 0x00000038
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___S               3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___M 0x00000007
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___S               0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___M 0x00FFFFFF   
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___S               0

#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH (0x00A800FC)
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___POR 0x00FAC688
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___POR 0x7
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___POR 0x6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___POR 0x5
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___POR 0x4
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___POR 0x3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___POR 0x2
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___POR 0x1
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___POR 0x0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___M 0x00E00000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___S              21
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___M 0x001C0000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___S              18
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___M 0x00038000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___S              15
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___M 0x00007000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___S              12
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___M 0x00000E00
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___S               9
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___M 0x000001C0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___S               6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___M 0x00000038
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___S               3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___M 0x00000007
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___S               0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___M 0x00FFFFFF   
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___S               0

#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS       (0x00A80100)
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___POR 0x00000003
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___POR 0x3
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___M 0x00000007
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___S               0
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___M 0x00000007   
#define   WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___S               0

#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0 (0x00A80104)
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___POR 0x01041041
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___POR 0x01041041
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___M 0x3FFFFFFF
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___S               0
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___M 0x3FFFFFFF   
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___S               0

#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30 (0x00A80108)
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___POR 0x00001041
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___POR 0x01041
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___M 0x0003FFFF
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___S               0
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___M 0x0003FFFF   
#define   WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___S               0

#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS (0x00A8010C)
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___POR 0x01FAC688
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___POR 0x1
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___POR 0x7
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___POR 0x6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___POR 0x5
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___POR 0x4
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___POR 0x3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___POR 0x2
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___POR 0x1
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___POR 0x0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___M 0x01000000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___S              24
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___M 0x00E00000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___S              21
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___M 0x001C0000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___S              18
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___M 0x00038000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___S              15
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___M 0x00007000
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___S              12
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___M 0x00000E00
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___S               9
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___M 0x000001C0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___S               6
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___M 0x00000038
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___S               3
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___M 0x00000007
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___S               0
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___M 0x01FFFFFF   
#define   WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___S               0

#define WMAC0_PDG_R0_CENTER_RU_CTRL               (0x00A80110)
#define   WMAC0_PDG_R0_CENTER_RU_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_PDG_R0_CENTER_RU_CTRL___POR      0x00000000
#define   WMAC0_PDG_R0_CENTER_RU_CTRL__EN___POR  0x0
#define   WMAC0_PDG_R0_CENTER_RU_CTRL__EN___M    0x00000001
#define   WMAC0_PDG_R0_CENTER_RU_CTRL__EN___S                  0
#define   WMAC0_PDG_R0_CENTER_RU_CTRL___M        0x00000001   
#define   WMAC0_PDG_R0_CENTER_RU_CTRL___S                      0

#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST (0x00A80114)
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___POR 0x00000000
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___POR 0x0
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___M 0x00000001
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___S               0
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___M 0x00000001   
#define   WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___S               0

#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW      (0x00A80118)
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___POR 0x00000003
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___POR 0x0
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___POR 0x0
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___POR 0x3
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___M 0x00000010
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___S               4
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___M 0x00000008
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___S               3
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___M 0x00000007
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___S               0
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___M 0x0000001F   
#define   WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n(n) (0x00A8011C+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___POR 0x000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___M  0xFFFFFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___S                0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0         (0x00A8011C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_GAIN_SETTING___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_GAIN_SETTING___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_ANTENNA_SECTOR_CTRL___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1         (0x00A80120)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_GAIN_SETTING___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_GAIN_SETTING___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_ANTENNA_SECTOR_CTRL___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n(n) (0x00A8013C+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___M 0x00300000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___M 0x000C0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___S              18
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___M 0x00030000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___M 0x0000C000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___M 0x00001000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___S              12
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___M 0x00000800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___M 0x00000400
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___M 0x003FFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0        (0x00A8013C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE_RESP___M 0x00300000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE_RESP___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE___M 0x000C0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE___S              18
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI_RESP___M 0x00030000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI_RESP___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI___M 0x0000C000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DPD_ENABLE___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DPD_ENABLE___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED_RESP___M 0x00001000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED_RESP___S              12
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED___M 0x00000800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC_RESP___M 0x00000400
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC_RESP___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SMOOTHING___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SMOOTHING___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1        (0x00A80140)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE_RESP___M 0x00300000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE_RESP___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE___M 0x000C0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE___S              18
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI_RESP___M 0x00030000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI_RESP___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI___M 0x0000C000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DPD_ENABLE___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DPD_ENABLE___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED_RESP___M 0x00001000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED_RESP___S              12
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED___M 0x00000800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC_RESP___M 0x00000400
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC_RESP___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SMOOTHING___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SMOOTHING___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n(n) (0x00A8015C+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___M 0xFFFFFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0       (0x00A8015C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1       (0x00A80160)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n(n) (0x00A8017C+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___M 0x00020000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___S              17
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___M 0x00010000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___M 0x0000E000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___M 0x00001C00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___M 0x0003FFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0        (0x00A8017C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM_RESP___M 0x00020000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM_RESP___S              17
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM___M 0x00010000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS_RESP___M 0x0000E000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS_RESP___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS___M 0x00001C00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC_RESP___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC_RESP___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1        (0x00A80180)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM_RESP___M 0x00020000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM_RESP___S              17
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM___M 0x00010000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS_RESP___M 0x0000E000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS_RESP___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS___M 0x00001C00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS___S              10
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC_RESP___M 0x00000200
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC_RESP___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n(n) (0x00A8019C+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___M 0x00100000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___S              19
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___M 0x00078000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___M 0x00001E00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___M 0x000000C0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___S               6
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___M 0x00000038
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___S               3
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___S               2
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___M 0x00000002
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___S               1
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___M 0x00000001
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___M  0x001FFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___S                0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0         (0x00A8019C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BW_20_OVERRIDE_ENABLE___M 0x00100000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BW_20_OVERRIDE_ENABLE___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BACK_TO_BACK_TRANSMISSION_EXPECTED___S              19
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__COEX_TX_PRIORITY___M 0x00078000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__COEX_TX_PRIORITY___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__MEASURE_POWER___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__MEASURE_POWER___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_DL_UL_FLAG___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_DL_UL_FLAG___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_SPATIAL_REUSE___M 0x00001E00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_SPATIAL_REUSE___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CONTENT___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CONTENT___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_LTF_SIZE___M 0x000000C0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_LTF_SIZE___S               6
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_NSS___M 0x00000038
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_NSS___S               3
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CHAIN_CSD_EN___S               2
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_CHAIN_CSD_EN___M 0x00000002
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_CHAIN_CSD_EN___S               1
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__STF_LTF_3DB_BOOST___M 0x00000001
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__STF_LTF_3DB_BOOST___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1         (0x00A801A0)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BW_20_OVERRIDE_ENABLE___M 0x00100000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BW_20_OVERRIDE_ENABLE___S              20
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BACK_TO_BACK_TRANSMISSION_EXPECTED___S              19
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__COEX_TX_PRIORITY___M 0x00078000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__COEX_TX_PRIORITY___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__MEASURE_POWER___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__MEASURE_POWER___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_DL_UL_FLAG___M 0x00002000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_DL_UL_FLAG___S              13
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_SPATIAL_REUSE___M 0x00001E00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_SPATIAL_REUSE___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CONTENT___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CONTENT___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_LTF_SIZE___M 0x000000C0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_LTF_SIZE___S               6
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_NSS___M 0x00000038
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_NSS___S               3
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CHAIN_CSD_EN___S               2
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_CHAIN_CSD_EN___M 0x00000002
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_CHAIN_CSD_EN___S               1
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__STF_LTF_3DB_BOOST___M 0x00000001
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__STF_LTF_3DB_BOOST___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n(n) (0x00A801BC+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___M 0x80000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___S              31
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___M 0x40000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___S              30
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___M 0x20000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___S              29
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___M 0x10000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___S              28
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___M 0x0FE00000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___S              21
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___M 0x001FC000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___M 0x00003F80
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___S               7
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___M 0x0000007F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___M 0xFFFFFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0        (0x00A801BC)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__TPC_GLUT_SELF_CAL___M 0x80000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__TPC_GLUT_SELF_CAL___S              31
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE_RESP___M 0x40000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE_RESP___S              30
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE___M 0x20000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE___S              29
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BF_ENABLED___M 0x10000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BF_ENABLED___S              28
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END_RESP___M 0x0FE00000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END_RESP___S              21
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END___M 0x001FC000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START_RESP___M 0x00003F80
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START_RESP___S               7
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START___M 0x0000007F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1        (0x00A801C0)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1___RWC  QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__TPC_GLUT_SELF_CAL___M 0x80000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__TPC_GLUT_SELF_CAL___S              31
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE_RESP___M 0x40000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE_RESP___S              30
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE___M 0x20000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE___S              29
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BF_ENABLED___M 0x10000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BF_ENABLED___S              28
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END_RESP___M 0x0FE00000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END_RESP___S              21
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END___M 0x001FC000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START_RESP___M 0x00003F80
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START_RESP___S               7
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START___M 0x0000007F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n(n) (0x00A801DC+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___M 0xFFFFFFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0       (0x00A801DC)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1       (0x00A801E0)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_CHAIN_MASK___M 0xFF000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_CHAIN_MASK___S              24
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR_1___M 0x00FF0000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR_1___S              16
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_MIN_TX_PWR___M 0x0000FF00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_MIN_TX_PWR___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n(n) (0x00A801FC+0x4*(n))
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_nMIN 0    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_nMAX 1    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_ELEM 2    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___POR 0x00000000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___M 0x00018000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___M 0x00003800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___M 0x00000700
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___M 0x0001FFFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0      (0x00A801FC)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__USER_BF_TYPE___M 0x00018000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__USER_BF_TYPE___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__VHT_HE_SIG_TXBF___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__VHT_HE_SIG_TXBF___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS_RESP___M 0x00003800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS_RESP___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS___M 0x00000700
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS___S               0
#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1      (0x00A80200)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__USER_BF_TYPE___M 0x00018000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__USER_BF_TYPE___S              15
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__VHT_HE_SIG_TXBF___M 0x00004000
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__VHT_HE_SIG_TXBF___S              14
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS_RESP___M 0x00003800
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS_RESP___S              11
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS___M 0x00000700
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS_RESP___M 0x000000F0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS_RESP___S               4
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS___M 0x0000000F
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS___S               0

#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX          (0x00A8021C)
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___RWC    QCSR_REG_RW    
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___POR 0x00000E00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___POR 0x7
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___POR 0x0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___POR 0x00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___M 0x00000E00
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___S               9
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___M 0x00000100
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___S               8
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___M 0x000000FF
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___S               0
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___M   0x00000FFF   
#define   WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___S                 0

#define WMAC0_PDG_R0_ILP_REGS                     (0x00A80220)
#define   WMAC0_PDG_R0_ILP_REGS___RWC               QCSR_REG_RW    
#define   WMAC0_PDG_R0_ILP_REGS___POR            0x000044A3
#define   WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___POR 0x22
#define   WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___POR 0x51
#define   WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___POR 0x1
#define   WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___M 0x00007E00
#define   WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___S               9
#define   WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___M 0x000001FE
#define   WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___S               1
#define   WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___M 0x00000001
#define   WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___S               0
#define   WMAC0_PDG_R0_ILP_REGS___M              0x00007FFF   
#define   WMAC0_PDG_R0_ILP_REGS___S                            0

#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE         (0x00A80224)
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___POR 0x00000000
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S               6
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S               5
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S               4
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S               3
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S               2
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S               1
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S               0
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___M  0x0000007F   
#define   WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___S                0

#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE       (0x00A80228)
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___POR 0x00000000
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S               6
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S               5
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S               4
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S               3
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S               2
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S               1
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S               0
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___M 0x0000007F   
#define   WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___S               0

#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE         (0x00A8022C)
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___POR 0x00000000
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S               6
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S               5
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S               4
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S               3
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S               2
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S               1
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S               0
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___M  0x0000007F   
#define   WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___S                0

#define WMAC0_PDG_R0_COEX_CTS_OFFSET              (0x00A80230)
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET___RWC        QCSR_REG_RW    
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET___POR     0x00000000
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___POR 0x0000
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___M 0x0000FFFF
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___S               0
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET___M       0x0000FFFF   
#define   WMAC0_PDG_R0_COEX_CTS_OFFSET___S                     0

#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION    (0x00A80234)
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___POR 0x00000000
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___POR 0x0000
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___M 0x0000FFFF
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___S               0
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___M 0x0000FFFF   
#define   WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___S               0

#define WMAC0_PDG_R0_COEX_CTS_MODE                (0x00A80238)
#define   WMAC0_PDG_R0_COEX_CTS_MODE___RWC          QCSR_REG_RW    
#define   WMAC0_PDG_R0_COEX_CTS_MODE___POR       0x00000000
#define   WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___POR 0x0
#define   WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___M 0x00000003
#define   WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___S               0
#define   WMAC0_PDG_R0_COEX_CTS_MODE___M         0x00000003   
#define   WMAC0_PDG_R0_COEX_CTS_MODE___S                       0

#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY  (0x00A8023C)
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___POR 0x00000000
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___POR 0x0
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___M 0x0000000F
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___S               0
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___M 0x0000000F   
#define   WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___S               0

#define WMAC0_PDG_R1_EVENTMASK_IX_0               (0x00A81000)
#define   WMAC0_PDG_R1_EVENTMASK_IX_0___RWC         QCSR_REG_RW    
#define   WMAC0_PDG_R1_EVENTMASK_IX_0___POR      0x00000000
#define   WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___POR 0x00000000
#define   WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___M 0xFFFFFFFF
#define   WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___S               0
#define   WMAC0_PDG_R1_EVENTMASK_IX_0___M        0xFFFFFFFF   
#define   WMAC0_PDG_R1_EVENTMASK_IX_0___S                      0

#define WMAC0_PDG_R1_EVENTMASK_IX_1               (0x00A81004)
#define   WMAC0_PDG_R1_EVENTMASK_IX_1___RWC         QCSR_REG_RW    
#define   WMAC0_PDG_R1_EVENTMASK_IX_1___POR      0x00000000
#define   WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___POR 0x00000000
#define   WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___M 0xFFFFFFFF
#define   WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___S               0
#define   WMAC0_PDG_R1_EVENTMASK_IX_1___M        0xFFFFFFFF   
#define   WMAC0_PDG_R1_EVENTMASK_IX_1___S                      0

#define WMAC0_PDG_R1_TESTBUS_CTRL                 (0x00A81008)
#define   WMAC0_PDG_R1_TESTBUS_CTRL___RWC           QCSR_REG_RW    
#define   WMAC0_PDG_R1_TESTBUS_CTRL___POR        0x00000000
#define   WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___POR 0x000
#define   WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___M 0x000001FF
#define   WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___S               0
#define   WMAC0_PDG_R1_TESTBUS_CTRL___M          0x000001FF   
#define   WMAC0_PDG_R1_TESTBUS_CTRL___S                        0

#define WMAC0_PDG_R1_TESTBUS_LOWER                (0x00A8100C)
#define   WMAC0_PDG_R1_TESTBUS_LOWER___RWC          QCSR_REG_RO    
#define   WMAC0_PDG_R1_TESTBUS_LOWER___POR       0x00000000
#define   WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___M  0xFFFFFFFF
#define   WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___S                0
#define   WMAC0_PDG_R1_TESTBUS_LOWER___M         0xFFFFFFFF   
#define   WMAC0_PDG_R1_TESTBUS_LOWER___S                       0

#define WMAC0_PDG_R1_TESTBUS_UPPER                (0x00A81010)
#define   WMAC0_PDG_R1_TESTBUS_UPPER___RWC          QCSR_REG_RO    
#define   WMAC0_PDG_R1_TESTBUS_UPPER___POR       0x00000000
#define   WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___M  0x000000FF
#define   WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___S                0
#define   WMAC0_PDG_R1_TESTBUS_UPPER___M         0x000000FF   
#define   WMAC0_PDG_R1_TESTBUS_UPPER___S                       0

#define WMAC0_PDG_R1_SM_STATES_IX_0               (0x00A81014)
#define   WMAC0_PDG_R1_SM_STATES_IX_0___RWC         QCSR_REG_RO    
#define   WMAC0_PDG_R1_SM_STATES_IX_0___POR      0x00220841
#define   WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___POR 0x01
#define   WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___POR 0x1
#define   WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___POR 0x01
#define   WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___POR 0x01
#define   WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___POR 0x01
#define   WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___M 0x03E00000
#define   WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___S              21
#define   WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___M 0x001E0000
#define   WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___S              17
#define   WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___M 0x0001F800
#define   WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___S              11
#define   WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___M 0x000007C0
#define   WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___S               6
#define   WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___M 0x0000003F
#define   WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___S               0
#define   WMAC0_PDG_R1_SM_STATES_IX_0___M        0x03FFFFFF   
#define   WMAC0_PDG_R1_SM_STATES_IX_0___S                      0

#define WMAC0_PDG_R1_IDLE_STATUS                  (0x00A81018)
#define   WMAC0_PDG_R1_IDLE_STATUS___RWC            QCSR_REG_RO    
#define   WMAC0_PDG_R1_IDLE_STATUS___POR         0x000001FF
#define   WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___POR 0x1
#define   WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___M 0x00000100
#define   WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___S               8
#define   WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___M 0x00000080
#define   WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___S               7
#define   WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___M 0x00000040
#define   WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___S               6
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___M 0x00000020
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___S               5
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___M 0x00000010
#define   WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___S               4
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___M 0x00000008
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___S               3
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___M 0x00000004
#define   WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___S               2
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___M 0x00000002
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___S               1
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___M 0x00000001
#define   WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___S               0
#define   WMAC0_PDG_R1_IDLE_STATUS___M           0x000001FF   
#define   WMAC0_PDG_R1_IDLE_STATUS___S                         0

#define WMAC0_PDG_R1_WATCHDOG                     (0x00A8101C)
#define   WMAC0_PDG_R1_WATCHDOG___RWC               QCSR_REG_RW    
#define   WMAC0_PDG_R1_WATCHDOG___POR            0x0000FFFF
#define   WMAC0_PDG_R1_WATCHDOG__STATUS___POR    0x0000
#define   WMAC0_PDG_R1_WATCHDOG__LIMIT___POR     0xFFFF
#define   WMAC0_PDG_R1_WATCHDOG__STATUS___M      0xFFFF0000
#define   WMAC0_PDG_R1_WATCHDOG__STATUS___S                   16
#define   WMAC0_PDG_R1_WATCHDOG__LIMIT___M       0x0000FFFF
#define   WMAC0_PDG_R1_WATCHDOG__LIMIT___S                     0
#define   WMAC0_PDG_R1_WATCHDOG___M              0xFFFFFFFF   
#define   WMAC0_PDG_R1_WATCHDOG___S                            0

#define WMAC0_PDG_R1_TRUNCATE_DEBUG               (0x00A81020)
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG___RWC         QCSR_REG_RO    
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG___POR      0x00000000
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___POR 0x0000
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___POR 0x000
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___M 0x01FFF000
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___S              12
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___M 0x00000FFF
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___S               0
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG___M        0x01FFFFFF   
#define   WMAC0_PDG_R1_TRUNCATE_DEBUG___S                      0

#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR          (0x00A81024)
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR___RWC    QCSR_REG_RO    
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR___M   0x0001FFFF   
#define   WMAC0_PDG_R1_INVALID_APB_ACC_ADR___S                 0

#define WMAC0_PDG_R1_AMPDU_RESULTS_USER           (0x00A81028)
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER___RWC     QCSR_REG_RW    
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER___POR  0x00000000
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___POR 0x00
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___M 0x0000003F
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___S               0
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER___M    0x0000003F   
#define   WMAC0_PDG_R1_AMPDU_RESULTS_USER___S                  0

#define WMAC0_PDG_R1_AMPDU_RESULTS                (0x00A8102C)
#define   WMAC0_PDG_R1_AMPDU_RESULTS___RWC          QCSR_REG_RO    
#define   WMAC0_PDG_R1_AMPDU_RESULTS___POR       0x00000000
#define   WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___POR 0x000000
#define   WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___POR 0x000
#define   WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___M 0xFFFFFE00
#define   WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___S               9
#define   WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___M 0x000001FF
#define   WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___S               0
#define   WMAC0_PDG_R1_AMPDU_RESULTS___M         0xFFFFFFFF   
#define   WMAC0_PDG_R1_AMPDU_RESULTS___S                       0

#define WMAC0_PDG_R1_SETUP_ERROR_STATUS           (0x00A81030)
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS___RWC     QCSR_REG_RO    
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS___POR  0x00000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___POR 0x0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___M 0x10000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___S              28
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___M 0x08000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___S              27
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___M 0x04000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___S              26
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___M 0x02000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___S              25
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___M 0x01000000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___S              24
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___M 0x00800000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___S              23
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___M 0x00400000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___S              22
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___M 0x00200000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___S              21
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___M 0x00100000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___S              20
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___M 0x00080000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___S              19
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___M 0x00040000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___S              18
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___M 0x00020000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___S              17
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___M 0x00010000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___S              16
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___M 0x00008000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___S              15
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___M 0x00004000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___S              14
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___M 0x00002000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___S              13
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___M 0x00001000
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___S              12
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___M 0x00000800
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___S              11
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___M 0x00000400
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___S              10
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___M 0x00000200
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___S               9
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___M 0x00000100
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___S               8
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___M 0x00000080
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___S               7
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___M 0x00000040
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___S               6
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___M 0x00000020
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___S               5
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___M 0x00000010
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___S               4
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___M 0x00000008
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___S               3
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___M 0x00000004
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___S               2
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___M 0x00000002
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___S               1
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___M 0x00000001
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___S               0
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS___M    0x1FFFFFFF   
#define   WMAC0_PDG_R1_SETUP_ERROR_STATUS___S                  0

#define WMAC0_PDG_R1_CLEAR_R1                     (0x00A81034)
#define   WMAC0_PDG_R1_CLEAR_R1___RWC               QCSR_REG_WO    
#define   WMAC0_PDG_R1_CLEAR_R1___POR            0x00000000
#define   WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___POR 0x0
#define   WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___M 0x00000001
#define   WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___S               0
#define   WMAC0_PDG_R1_CLEAR_R1___M              0x00000001   
#define   WMAC0_PDG_R1_CLEAR_R1___S                            0

#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS       (0x00A81038)
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___POR 0x00000000
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___POR 0x00
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___M 0x0000003F
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___S               0
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___M 0x0000003F   
#define   WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___S               0

#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER            (0x00A8103C)
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER___POR   0x00000000
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___M 0x0000FF00
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___S               8
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___M 0x000000FF
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___S               0
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER___M     0x0000FFFF   
#define   WMAC0_PDG_R1_DEBUG_H2D_COUNTER___S                   0

#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER            (0x00A81040)
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER___RWC      QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER___POR   0x00000000
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___POR 0x00
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___M 0xFF000000
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___S              24
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___M 0x00FF0000
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___S              16
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___M 0x0000FF00
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___S               8
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___M 0x000000FF
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___S               0
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER___M     0xFFFFFFFF   
#define   WMAC0_PDG_R1_DEBUG_D2H_COUNTER___S                   0

#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER    (0x00A81044)
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___POR 0x0000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___M 0x0000FFFF
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___M 0x0000FFFF   
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER (0x00A81048)
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___POR 0x0000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___M 0x0000FFFF
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___M 0x0000FFFF   
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER    (0x00A8104C)
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___POR 0x0000
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___M 0x0000FFFF
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___M 0x0000FFFF   
#define   WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER    (0x00A81050)
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER (0x00A81054)
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER    (0x00A81058)
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER    (0x00A8105C)
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER (0x00A81060)
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___S               0

#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER    (0x00A81064)
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___POR 0x00000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___POR 0x000000
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___M 0x00FFFFFF
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___S               0
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___M 0x00FFFFFF   
#define   WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___S               0

#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS         (0x00A81068)
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___RWC   QCSR_REG_RW    
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___POR 0x00000000
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___POR 0x0
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___M 0x00000001
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___S               0
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___M  0x00000001   
#define   WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___S                0

#define WMAC0_PDG_R1_COEX_DEBUG                   (0x00A8106C)
#define   WMAC0_PDG_R1_COEX_DEBUG___RWC             QCSR_REG_RO    
#define   WMAC0_PDG_R1_COEX_DEBUG___POR          0x00000000
#define   WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___M 0xFF000000
#define   WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___S              24
#define   WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___M 0x00FF0000
#define   WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___S              16
#define   WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___M 0x0000FF00
#define   WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___S               8
#define   WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___M 0x000000FF
#define   WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___S               0
#define   WMAC0_PDG_R1_COEX_DEBUG___M            0xFFFFFFFF   
#define   WMAC0_PDG_R1_COEX_DEBUG___S                          0

#define WMAC0_PDG_R1_COEX_DEBUG2                  (0x00A81070)
#define   WMAC0_PDG_R1_COEX_DEBUG2___RWC            QCSR_REG_RO    
#define   WMAC0_PDG_R1_COEX_DEBUG2___POR         0x00000000
#define   WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___POR 0x00
#define   WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___M 0x0000FF00
#define   WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___S               8
#define   WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___M 0x000000FF
#define   WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___S               0
#define   WMAC0_PDG_R1_COEX_DEBUG2___M           0x0000FFFF   
#define   WMAC0_PDG_R1_COEX_DEBUG2___S                         0

#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG  (0x00A83000)
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___POR 0x00000005
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___POR 0x5
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___M 0x00000007
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___S               0
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___M 0x00000007   
#define   WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG     (0x00A83004)
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___POR 0x00000314
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___POR 0x03
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___POR 0x14
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___M 0x00004000
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___S              14
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___M 0x00003F00
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___S               8
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___M 0x00007FFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG  (0x00A83008)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___POR 0x0000007F
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___POR 0x7F
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___M 0x000000FF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___S               0

#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG             (0x00A8300C)
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG___RWC       QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG___POR    0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___S              16
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG___M      0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_WATCHDOG___S                    0

#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS        (0x00A83010)
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___RWC  QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___S               0
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___M 0x00000001   
#define   WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP             (0x00A83020)
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___RWC       QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___POR    0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___M 0x00800000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___S              23
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___M 0x00400000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___S              22
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___M 0x00200000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___S              21
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___M 0x00100000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___S              20
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___M 0x00080000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___S              19
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___M 0x00040000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___S              18
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___M 0x00020000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___S              17
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___M 0x00010000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___S              16
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___M 0x00008000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___S              15
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___M 0x00004000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___S              14
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___M 0x00002000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___S              13
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___M 0x00001000
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___S              12
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___M 0x00000800
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___S              11
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___M 0x00000400
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___S              10
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___M 0x00000200
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___S               9
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___M 0x00000100
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___S               8
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___M 0x00000080
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___S               7
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___S               6
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___M 0x00000020
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___S               5
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___M 0x00000010
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___S               4
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___M 0x00000008
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___S               3
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___M 0x00000004
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___S               2
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___M 0x00000002
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___S               1
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___S               0
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___M      0x00FFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___S                    0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG  (0x00A83050)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___POR 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___POR 0x00FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE (0x00A83054)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___S               6
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___M 0x00000020
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___S               5
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___M 0x0000001F
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___M 0x0000007F   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU (0x00A83058)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___POR 0x00000010
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___POR 0x0010
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE (0x00A8305C)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___POR 0x00000FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___POR 0x00000FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR (0x00A8306C)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND (0x00A83084)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___M 0x00000001   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1 (0x00A83088)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___POR 0x10285003
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___POR 0x50
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___POR 0x50
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___POR 0x03
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___M 0x10000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___S              28
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___M 0x08000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___S              27
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___M 0x06000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___S              25
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___M 0x01800000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___S              23
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___M 0x00400000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___S              22
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___M 0x003F8000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___S              15
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___M 0x00007F00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___S               8
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___M 0x1FFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2 (0x00A8308C)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___M 0x0FFFC000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___S              14
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___M 0x00003FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___M 0x0FFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3 (0x00A83090)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___M 0x7FFF8000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___S              15
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___M 0x00004000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___S              14
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___M 0x00003FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___M 0x7FFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4 (0x00A83094)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5 (0x00A83098)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6 (0x00A8309C)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___POR 0x000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___POR 0x000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___M 0x00040000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___S              18
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___M 0x0003FE00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___S               9
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___M 0x000001FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___M 0x0007FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7 (0x00A830A0)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR  (0x00A830A4)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___M 0x00000001   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG         (0x00A830A8)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___RWC   QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___POR 0x00008000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___M 0x00080000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___S              19
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___M 0x00040000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___S              18
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___M 0x00020000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___S              17
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___M 0x00010000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___M 0x00008000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___S              15
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___M 0x00007FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___M  0x000FFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___S                0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG      (0x00A830AC)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___M 0x7FFF0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___M 0x00007F00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___S               8
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___M 0x000000FE
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___S               1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___M 0x7FFF7FFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1    (0x00A830B0)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___POR 0x00200000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___POR 0x010
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___POR 0x000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___M 0x1FFE0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___S              17
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___M 0x0001FC00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___S              10
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___M 0x000003FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___M 0x1FFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1 (0x00A830B4)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___POR 0x000003FE
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___POR 0x1FF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___M 0x0000FC00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___S              10
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___M 0x000003FE
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___S               1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2 (0x00A830B8)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS (0x00A830C8)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___POR 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___POR 0xFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS (0x00A830CC)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___POR 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___POR 0xFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT (0x00A830D0)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___POR 0x00000FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___POR 0xFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___M 0x00000FFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___M 0x00000FFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS   (0x00A830D4)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___M 0x00002000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___S              13
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___M 0x00001F00
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___S               8
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___M 0x000000F0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___S               4
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___M 0x0000000F
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___M 0x00003FFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS (0x00A830D8)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___POR 0x00000700
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___M 0x00020000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___S              17
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___M 0x00010000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___S              16
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___M 0x00000400
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___S              10
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___M 0x00000200
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___S               9
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___M 0x00000100
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___S               8
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___M 0x00000004
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___S               2
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___M 0x00000002
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___S               1
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___M 0x00030707   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL     (0x00A830DC)
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___S               0
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB (0x00A830E0)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB (0x00A830E4)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID (0x00A830E8)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___S               8
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS (0x00A830EC)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC (0x00A830F0)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___POR 0x00000080
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB (0x00A830F4)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB (0x00A830F8)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP (0x00A83104)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS (0x00A83108)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER (0x00A8310C)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB (0x00A83128)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB (0x00A8312C)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA (0x00A83130)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___S               0

#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET (0x00A83134)
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS       (0x00A84010)
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___S               0

#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL      (0x00A84014)
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___M 0x00000180
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___S               7
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___S               6
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___M 0x0000003F
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___S               0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___M 0x000001FF   
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE (0x00A84024)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___M 0x00000100
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___S               8
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___M 0x00000080
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___S               7
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___S               6
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___M 0x00000020
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___S               5
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___M 0x00000010
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___S               4
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___M 0x00000008
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___S               3
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___M 0x00000004
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___S               2
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___M 0x00000002
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___S               1
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___M 0x000001FF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP      (0x00A84028)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH          (0x00A8402C)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___RWC    QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___M   0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___S                 0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS     (0x00A84030)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ      (0x00A84034)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU           (0x00A84038)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___RWC     QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___POR  0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___M    0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___S                  0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS (0x00A8403C)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0       (0x00A84040)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___POR 0x00000008
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___POR 0x1
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___M 0x07000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___S              24
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___M 0x00C00000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___S              22
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___M 0x00300000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___S              20
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___M 0x000F0000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___S              16
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___M 0x0000F000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___S              12
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___M 0x00000800
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___S              11
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___M 0x00000600
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___S               9
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___M 0x00000180
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___S               7
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___M 0x00000060
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___S               5
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___M 0x00000018
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___S               3
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___M 0x00000007
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___M 0x07FFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___S               0

#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0 (0x00A84048)
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___POR 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___S               0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___S               0

#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1 (0x00A8404C)
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___POR 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___S               0
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK (0x00A84060)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT (0x00A84064)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA (0x00A84068)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB    (0x00A84070)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB    (0x00A84074)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___M 0x000000FF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ (0x00A84078)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___POR 0x000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___POR 0x00
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___M 0xFFFFFF00
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___S               8
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___M 0x000000FF
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___M 0xFFFFFFFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___S               0

#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE     (0x00A84080)
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___RWC QCSR_REG_RO    
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___POR 0x0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___M 0x00004000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___S              14
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___M 0x00002000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___S              13
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___M 0x00001000
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___S              12
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___M 0x00000800
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___S              11
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___M 0x00000400
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___S              10
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___M 0x00000200
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___S               9
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___M 0x00000100
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___S               8
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___M 0x00000080
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___S               7
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___M 0x00000040
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___S               6
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___M 0x00000020
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___S               5
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___M 0x00000010
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___S               4
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___M 0x00000008
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___S               3
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___M 0x00000004
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___S               2
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___M 0x00000002
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___S               1
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___M 0x00000001
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___S               0
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___M 0x00007FFF   
#define   WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___S               0

#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP (0x00A85000)
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___S               0
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___S               0

#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP (0x00A85004)
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___POR 0x00000000
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___S               0
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___M 0x0000FFFF   
#define   WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB (0x00A86000)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB (0x00A86004)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID (0x00A86008)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS (0x00A8600C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC (0x00A86010)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A8601C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86020)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86030)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86034)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A86038)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8603C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86040)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86044)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A86048)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A8604C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA (0x00A86050)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A86054)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT (0x00A86058)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0 (0x00A8605C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S               1
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1 (0x00A86060)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___S               2

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2 (0x00A86064)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___S               2

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3 (0x00A86068)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___S               2

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4 (0x00A8606C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___M 0x00000FFC   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___S               2

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB (0x00A86070)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB (0x00A86074)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID (0x00A86078)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS (0x00A8607C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC (0x00A86080)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A8608C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86090)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A860A0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A860A4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A860A8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A860AC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A860B0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A860B4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A860B8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A860BC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA (0x00A860C0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A860C4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT (0x00A860C8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0 (0x00A860CC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1 (0x00A860D0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___S               2

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2 (0x00A860D4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___S               2

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3 (0x00A860D8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___S               2

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4 (0x00A860DC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___M 0x00000FFC   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___S               2

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB (0x00A860E0)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB (0x00A860E4)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID (0x00A860E8)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS (0x00A860EC)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC (0x00A860F0)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A860FC)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86100)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86110)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86114)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A86118)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8611C)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86120)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86124)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A86128)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A8612C)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA (0x00A86130)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A86134)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT (0x00A86138)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0 (0x00A8613C)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S               1
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1 (0x00A86140)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___S               2

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2 (0x00A86144)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___S               2

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3 (0x00A86148)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S              18
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___S               2

#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4 (0x00A8614C)
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___M 0x00000FFC   
#define   WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___S               2

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB (0x00A86150)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB (0x00A86154)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID (0x00A86158)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS (0x00A8615C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC (0x00A86160)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB (0x00A8616C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB (0x00A86170)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86180)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86184)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS (0x00A86188)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8618C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86190)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86194)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB (0x00A86198)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB (0x00A8619C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA (0x00A861A0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET (0x00A861A4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT (0x00A861A8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___M 0x00010000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___M 0x0001FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB (0x00A861AC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB (0x00A861B0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID (0x00A861B4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS (0x00A861B8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC (0x00A861BC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB (0x00A861C8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB (0x00A861CC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A861DC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A861E0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS (0x00A861E4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER (0x00A861E8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER (0x00A861EC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS (0x00A861F0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB (0x00A861F4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB (0x00A861F8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA (0x00A861FC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET (0x00A86200)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT (0x00A86204)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___M 0x00010000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___M 0x0001FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB (0x00A86208)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB (0x00A8620C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID (0x00A86210)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS (0x00A86214)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC (0x00A86218)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB (0x00A86224)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB (0x00A86228)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A86238)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A8623C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS (0x00A86240)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A86244)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A86248)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A8624C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB (0x00A86250)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB (0x00A86254)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA (0x00A86258)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET (0x00A8625C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT (0x00A86260)
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___M 0x00000001   
#define   WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB (0x00A86264)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB (0x00A86268)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID (0x00A8626C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS (0x00A86270)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC (0x00A86274)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB (0x00A86280)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB (0x00A86284)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A86294)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A86298)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS (0x00A8629C)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A862A0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A862A4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A862A8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB (0x00A862AC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB (0x00A862B0)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA (0x00A862B4)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET (0x00A862B8)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT (0x00A862BC)
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___M 0x00000001   
#define   WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB (0x00A862C0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB (0x00A862C4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID    (0x00A862C8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS (0x00A862CC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC  (0x00A862D0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB (0x00A862D4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB (0x00A862D8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP (0x00A862E4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS (0x00A862E8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER (0x00A862EC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB (0x00A86308)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB (0x00A8630C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA (0x00A86310)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET (0x00A86314)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB (0x00A86318)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB (0x00A8631C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID     (0x00A86320)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS (0x00A86324)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC   (0x00A86328)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB (0x00A8632C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB (0x00A86330)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP (0x00A8633C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS (0x00A86340)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER (0x00A86344)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB (0x00A86360)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB (0x00A86364)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA (0x00A86368)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET (0x00A8636C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB (0x00A86370)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB (0x00A86374)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID     (0x00A86378)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS (0x00A8637C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC   (0x00A86380)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB (0x00A86384)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB (0x00A86388)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP (0x00A86394)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS (0x00A86398)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER (0x00A8639C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB (0x00A863B8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB (0x00A863BC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA (0x00A863C0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET (0x00A863C4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB (0x00A863C8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB (0x00A863CC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID (0x00A863D0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS (0x00A863D4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC (0x00A863D8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___POR 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB (0x00A863DC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB (0x00A863E0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP (0x00A863EC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS (0x00A863F0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A863F4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB (0x00A86410)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB (0x00A86414)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA (0x00A86418)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET (0x00A8641C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT (0x00A86420)
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___POR 0x00000006
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___S               2
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___S               1
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER (0x00A86424)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE (0x00A86428)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___POR 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___POR 0x2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___M 0x00000018
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___M 0x0000001F   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A8642C)
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S              27
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S              24
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S              21
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S              18
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S              15
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S               9
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S               6
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S               3
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86430)
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S               9
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S               6
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF   
#define   WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A86434)
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S              27
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S              24
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S              21
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S              18
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S              15
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S               9
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S               6
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S               3
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86438)
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S               9
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S               6
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF   
#define   WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A8643C)
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S              27
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S              24
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S              21
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S              18
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S              15
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S               9
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___S               0

#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86440)
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S              12
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S               9
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S               6
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S               3
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF   
#define   WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___S               0

#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2           (0x00A86444)
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___RWC     QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___POR  0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___M 0x00000180
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___S               7
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___S               6
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___S               5
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___S               4
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___S               3
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___S               2
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___S               1
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___S               0
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___M    0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___S                  0

#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER           (0x00A86448)
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___RWC     QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___POR  0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___M 0x00000100
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___S               8
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___M 0x00000080
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___S               7
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___S               6
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___S               5
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___S               4
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___S               3
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___S               2
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___S               1
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___M    0x000001FF   
#define   WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___S                  0

#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0   (0x00A8644C)
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___POR 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___S               0
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___S               0

#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1   (0x00A86450)
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___POR 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___S               0
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE    (0x00A86454)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___POR 0x00000800
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___POR 0x200
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___M 0x00000FFC
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___M 0x00000FFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___S               0

#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG    (0x00A86458)
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___POR 0x00000007
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___POR 0x3
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___M 0x00000006
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___S               1
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___S               0
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___M 0x00000007   
#define   WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___S               0

#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0 (0x00A8645C)
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___M 0x3FF00000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___S              20
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___M 0x000FFC00
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___S              10
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___M 0x3FFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___S               0

#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1 (0x00A86460)
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___M 0x000FFC00
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___S              10
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___M 0x000FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___S               0

#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD (0x00A86464)
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___M 0x000FFC00
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___S              10
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___M 0x000003FF
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___M 0x000FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG     (0x00A86468)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR (0x00A8646C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___POR 0x00010000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___POR 0x020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___M 0x003FF800
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___S              11
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___M 0x000007FF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___M 0x003FFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG (0x00A86470)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___POR 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST    (0x00A86474)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE (0x00A86478)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___M 0x00000040
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___S               6
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___S               5
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___S               4
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___S               3
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___S               2
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___S               1
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___M 0x0000007F   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT    (0x00A8647C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___M 0x0000003F
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___M 0x0000003F   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB (0x00A86480)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB (0x00A86484)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB (0x00A86488)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB (0x00A8648C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB (0x00A86490)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB (0x00A86494)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS     (0x00A86498)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___M 0x07C00000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___S              22
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___M 0x003E0000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___S              17
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___M 0x0001F000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___S              12
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___M 0x00000F80
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___S               7
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___M 0x00000078
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___M 0x07FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH (0x00A8649C)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___M 0x00000020
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___S               5
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___M 0x00000010
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___S               4
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___M 0x00000008
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___S               3
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___M 0x00000004
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___S               2
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___S               1
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___M 0x0000003F   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB (0x00A864A0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB (0x00A864A4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB (0x00A864A8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB (0x00A864AC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB (0x00A864B0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB (0x00A864B4)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB (0x00A864B8)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB (0x00A864BC)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___S               0

#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT (0x00A864C0)
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___M 0x0000003F
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___S               0
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___M 0x0000003F   
#define   WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___S               0

#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR   (0x00A864C4)
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___M 0x000007FF
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___M 0x000007FF   
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___S               0

#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA   (0x00A864C8)
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD      (0x00A864CC)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD      (0x00A864D0)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1 (0x00A864D4)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2 (0x00A864D8)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___S              16
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___S               0

#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP (0x00A864DC)
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___S               0

#define WMAC0_RXDMA_RXDMA_R0_WDOG                 (0x00A864E0)
#define   WMAC0_RXDMA_RXDMA_R0_WDOG___RWC           QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_WDOG___POR        0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___POR 0xFFFF
#define   WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___M   0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___S                 0
#define   WMAC0_RXDMA_RXDMA_R0_WDOG___M          0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_WDOG___S                        0

#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL         (0x00A864E4)
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___M 0x0000003F
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___S               0
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___M  0x0000003F   
#define   WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___S                0

#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE           (0x00A864E8)
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___RWC     QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___POR  0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___M    0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___S                  0

#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR  (0x00A864EC)
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___S               0

#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A87000)
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER        (0x00A87004)
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___RWC  QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___S               0
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___S               0

#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER        (0x00A87008)
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___RWC  QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___M 0x000000FF
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___S               0
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___M 0x000000FF   
#define   WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___S               0

#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS            (0x00A8700C)
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS___RWC      QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS___POR   0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___POR 0x000
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___M 0x7F800000
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___S              23
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___M 0x007C0000
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___S              18
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___M 0x0003E000
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___S              13
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___M 0x00001E00
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___S               9
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___M 0x000001FF
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___S               0
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS___M     0x7FFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_SM_STATUS___S                   0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG        (0x00A87010)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___RWC  QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___M 0x00800000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___S              23
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___M 0x007F8000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___S              15
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___M 0x00007E00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___S               9
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___M 0x000001F0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___S               4
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___M 0x0000000F
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___M 0x00FFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS   (0x00A87014)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___M 0x00000780
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___S               7
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___M 0x0000007F
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___M 0x000007FF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1  (0x00A87018)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___M 0x80000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___S              31
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___M 0x7E000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___S              25
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___M 0x01F00000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___S              20
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___M 0x000F8000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___S              15
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___M 0x00007800
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___S              11
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___M 0x00000780
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___S               7
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___M 0x0000007F
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2  (0x00A8701C)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___RWC QCSR_REG_RO    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___POR 0x00
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___M 0x80000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___S              31
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___M 0x7E000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___S              25
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___M 0x01F00000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___S              20
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___M 0x000F8000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___S              15
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___M 0x00007800
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___S              11
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___M 0x00000780
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___S               7
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___M 0x0000007F
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___S               0

#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE (0x00A87020)
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___POR 0x00000
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___M 0x000FFFFF
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___S               0
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___M 0x000FFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___S               0

#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE (0x00A87024)
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___POR 0x00000
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___M 0x000FFFFF
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___S               0
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___M 0x000FFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG (0x00A87028)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG (0x00A8702C)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___M 0xFFFF0000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___S              16
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___M 0xFFFFFFFF   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___S               0

#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS (0x00A87030)
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___POR 0x0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___M 0x00000002
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___S               1
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___M 0x00000001
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___S               0
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___M 0x00000003   
#define   WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___S               0

#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP (0x00A88000)
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP (0x00A88004)
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP (0x00A88008)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP (0x00A8800C)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP (0x00A88010)
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP (0x00A88014)
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP (0x00A88018)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP (0x00A8801C)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP (0x00A88020)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP (0x00A88024)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP (0x00A88028)
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP (0x00A8802C)
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP (0x00A88030)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP (0x00A88034)
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP    (0x00A88038)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP    (0x00A8803C)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP     (0x00A88040)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP     (0x00A88044)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP     (0x00A88048)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP     (0x00A8804C)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP (0x00A88050)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___S               0

#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP (0x00A88054)
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___RWC QCSR_REG_RW    
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___POR 0x00000000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___S               0
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___M 0x0000FFFF   
#define   WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___S               0

#define WMAC0_MCMN_R0_MCMN_ISR_S0                 (0x00A89000)
#define   WMAC0_MCMN_R0_MCMN_ISR_S0___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S0___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S0___M          0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S0___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S1                 (0x00A89004)
#define   WMAC0_MCMN_R0_MCMN_ISR_S1___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S1___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___S              22
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___S              19
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___M 0x0003C000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S1___M          0x007FFFEF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S1___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S2                 (0x00A89008)
#define   WMAC0_MCMN_R0_MCMN_ISR_S2___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S2___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___M 0x04000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___S              26
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___S              25
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___M 0x01800000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___S              23
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___S              22
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___S              19
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S2___M          0x07FFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S2___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S3                 (0x00A8900C)
#define   WMAC0_MCMN_R0_MCMN_ISR_S3___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S3___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___POR 0x00000
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___S              28
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___M 0x0FFFFF00
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S3___M          0x1FFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S3___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S4                 (0x00A89010)
#define   WMAC0_MCMN_R0_MCMN_ISR_S4___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S4___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S4___M          0x000000FF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S4___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S5                 (0x00A89014)
#define   WMAC0_MCMN_R0_MCMN_ISR_S5___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S5___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___M 0x80000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___S              31
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___M 0x40000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___S              30
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___M 0x20000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___S              29
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___S              28
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___M 0x0C000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___S              26
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___M 0x03000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___S              24
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___S              23
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___M 0x00600000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___S              19
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___M 0x00000C00
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___M  0x00000300
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___S                8
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___M 0x000000C0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___M 0x00000030
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___M 0x0000000C
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___M 0x00000003
#define   WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S5___M          0xFFFFEFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S5___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S6                 (0x00A89018)
#define   WMAC0_MCMN_R0_MCMN_ISR_S6___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S6___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___M 0x0000C000
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___M 0x00001800
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S6___M          0x0000FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S6___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S7                 (0x00A8901C)
#define   WMAC0_MCMN_R0_MCMN_ISR_S7___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S7___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S7___M          0x00003FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S7___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S8                 (0x00A89020)
#define   WMAC0_MCMN_R0_MCMN_ISR_S8___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S8___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___M 0xFFFF0000
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___M 0x0000FFFF
#define   WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S8___M          0xFFFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S8___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S9                 (0x00A89024)
#define   WMAC0_MCMN_R0_MCMN_ISR_S9___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S9___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___M 0xFF000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___S              24
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___M 0x00FF0000
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___M 0x0000FFFF
#define   WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S9___M          0xFFFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S9___S                        0

#define WMAC0_MCMN_R0_MCMN_ISR_S10                (0x00A89028)
#define   WMAC0_MCMN_R0_MCMN_ISR_S10___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S10___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___S              25
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___M 0x01000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___S              24
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___S              23
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___S              22
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___S              19
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___M 0x000001E0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S10___M         0x03FFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S10___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S11                (0x00A8902C)
#define   WMAC0_MCMN_R0_MCMN_ISR_S11___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S11___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S11___M         0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_ISR_S11___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S12                (0x00A89030)
#define   WMAC0_MCMN_R0_MCMN_ISR_S12___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S12___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S12___M         0x00000007   
#define   WMAC0_MCMN_R0_MCMN_ISR_S12___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S13                (0x00A89034)
#define   WMAC0_MCMN_R0_MCMN_ISR_S13___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S13___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S13___M         0x00000001   
#define   WMAC0_MCMN_R0_MCMN_ISR_S13___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S14                (0x00A89038)
#define   WMAC0_MCMN_R0_MCMN_ISR_S14___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S14___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___M 0x20000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___S              29
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___S              28
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___M 0x08000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___S              27
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___M 0x04000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___S              26
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___S              25
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___M 0x01000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___S              24
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___S              23
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___S              22
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___S              19
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S14___M         0x3FFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S14___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S15                (0x00A8903C)
#define   WMAC0_MCMN_R0_MCMN_ISR_S15___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S15___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S15___M         0x00007FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S15___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S16                (0x00A89040)
#define   WMAC0_MCMN_R0_MCMN_ISR_S16___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S16___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___S              18
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___S              17
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___S              16
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___S              15
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___S              14
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___S              13
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S16___M         0x0007FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S16___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S17                (0x00A89044)
#define   WMAC0_MCMN_R0_MCMN_ISR_S17___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S17___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___S              11
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___S              10
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___S               9
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___S               7
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S17___M         0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S17___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S18                (0x00A89048)
#define   WMAC0_MCMN_R0_MCMN_ISR_S18___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S18___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S18___M         0x0000003F   
#define   WMAC0_MCMN_R0_MCMN_ISR_S18___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S20                (0x00A89050)
#define   WMAC0_MCMN_R0_MCMN_ISR_S20___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S20___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___M 0x0003F000
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___M 0x00000FC0
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___M 0x0000003F
#define   WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S20___M         0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S20___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S21                (0x00A89054)
#define   WMAC0_MCMN_R0_MCMN_ISR_S21___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S21___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___M 0x00000F00
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___M 0x000000F0
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S21___M         0x00000FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S21___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S22                (0x00A89058)
#define   WMAC0_MCMN_R0_MCMN_ISR_S22___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S22___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___M 0x0003F000
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___M 0x00000FC0
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___M 0x0000003F
#define   WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S22___M         0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S22___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S26                (0x00A89068)
#define   WMAC0_MCMN_R0_MCMN_ISR_S26___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S26___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S26___M         0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_ISR_S26___S                       0

#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT             (0x00A8906C)
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___M 0x000000F0
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___M      0x000000FF   
#define   WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___S                    0

#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT             (0x00A89070)
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___M      0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___S                    0

#define WMAC0_MCMN_R0_MCMN_IMR_S0                 (0x00A89100)
#define   WMAC0_MCMN_R0_MCMN_IMR_S0___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S0___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S0___M          0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S0___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S1                 (0x00A89104)
#define   WMAC0_MCMN_R0_MCMN_IMR_S1___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S1___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___S              22
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___S              19
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___M 0x0003C000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S1___M          0x007FFFEF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S1___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S2                 (0x00A89108)
#define   WMAC0_MCMN_R0_MCMN_IMR_S2___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S2___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___M 0x04000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___S              26
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___S              25
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___M 0x01800000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___S              23
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___S              22
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___S              19
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S2___M          0x07FFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S2___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S3                 (0x00A8910C)
#define   WMAC0_MCMN_R0_MCMN_IMR_S3___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S3___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___POR 0x00000
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___S              28
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___M 0x0FFFFF00
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S3___M          0x1FFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S3___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S4                 (0x00A89110)
#define   WMAC0_MCMN_R0_MCMN_IMR_S4___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S4___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S4___M          0x000000FF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S4___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S5                 (0x00A89114)
#define   WMAC0_MCMN_R0_MCMN_IMR_S5___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S5___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___M 0x80000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___S              31
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___M 0x40000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___S              30
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___M 0x20000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___S              29
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___S              28
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___M 0x0C000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___S              26
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___M 0x03000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___S              24
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___S              23
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___M 0x00600000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___S              19
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___M 0x00000C00
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___M  0x00000300
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___S                8
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___M 0x000000C0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___M 0x00000030
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___M 0x0000000C
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___M 0x00000003
#define   WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S5___M          0xFFFFEFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S5___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S6                 (0x00A89118)
#define   WMAC0_MCMN_R0_MCMN_IMR_S6___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S6___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___M 0x0000C000
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___M 0x00001800
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S6___M          0x0000FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S6___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S7                 (0x00A8911C)
#define   WMAC0_MCMN_R0_MCMN_IMR_S7___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S7___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S7___M          0x00003FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S7___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S8                 (0x00A89120)
#define   WMAC0_MCMN_R0_MCMN_IMR_S8___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S8___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___M 0xFFFF0000
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___M 0x0000FFFF
#define   WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S8___M          0xFFFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S8___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S9                 (0x00A89124)
#define   WMAC0_MCMN_R0_MCMN_IMR_S9___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S9___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___POR 0x0000
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___M 0xFF000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___S              24
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___M 0x00FF0000
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___M 0x0000FFFF
#define   WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S9___M          0xFFFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S9___S                        0

#define WMAC0_MCMN_R0_MCMN_IMR_S10                (0x00A89128)
#define   WMAC0_MCMN_R0_MCMN_IMR_S10___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S10___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___S              25
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___M 0x01000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___S              24
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___S              23
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___S              22
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___S              19
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___M 0x000001E0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S10___M         0x03FFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S10___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S11                (0x00A8912C)
#define   WMAC0_MCMN_R0_MCMN_IMR_S11___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S11___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S11___M         0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_IMR_S11___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S12                (0x00A89130)
#define   WMAC0_MCMN_R0_MCMN_IMR_S12___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S12___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S12___M         0x00000007   
#define   WMAC0_MCMN_R0_MCMN_IMR_S12___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S13                (0x00A89134)
#define   WMAC0_MCMN_R0_MCMN_IMR_S13___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S13___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S13___M         0x00000001   
#define   WMAC0_MCMN_R0_MCMN_IMR_S13___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S14                (0x00A89138)
#define   WMAC0_MCMN_R0_MCMN_IMR_S14___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S14___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___M 0x20000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___S              29
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___M 0x10000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___S              28
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___M 0x08000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___S              27
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___M 0x04000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___S              26
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___S              25
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___M 0x01000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___S              24
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___S              23
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___S              22
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___S              19
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S14___M         0x3FFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S14___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S15                (0x00A8913C)
#define   WMAC0_MCMN_R0_MCMN_IMR_S15___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S15___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S15___M         0x00007FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S15___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S16                (0x00A89140)
#define   WMAC0_MCMN_R0_MCMN_IMR_S16___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S16___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___S              18
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___S              17
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___S              16
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___S              15
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___S              14
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___S              13
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S16___M         0x0007FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S16___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S17                (0x00A89144)
#define   WMAC0_MCMN_R0_MCMN_IMR_S17___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S17___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___S              11
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___S              10
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___S               9
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___S               7
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S17___M         0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S17___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S18                (0x00A89148)
#define   WMAC0_MCMN_R0_MCMN_IMR_S18___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S18___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___S               5
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S18___M         0x0000003F   
#define   WMAC0_MCMN_R0_MCMN_IMR_S18___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S20                (0x00A89150)
#define   WMAC0_MCMN_R0_MCMN_IMR_S20___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S20___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___M 0x0003F000
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___M 0x00000FC0
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___M 0x0000003F
#define   WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S20___M         0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S20___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S21                (0x00A89154)
#define   WMAC0_MCMN_R0_MCMN_IMR_S21___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S21___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___M 0x00000F00
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___S               8
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___M 0x000000F0
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S21___M         0x00000FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S21___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S22                (0x00A89158)
#define   WMAC0_MCMN_R0_MCMN_IMR_S22___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S22___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___POR 0x00
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___M 0x0003F000
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___S              12
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___M 0x00000FC0
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___S               6
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___M 0x0000003F
#define   WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S22___M         0x0003FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S22___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S26                (0x00A89168)
#define   WMAC0_MCMN_R0_MCMN_IMR_S26___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S26___POR       0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S26___M         0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_IMR_S26___S                       0

#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT             (0x00A8916C)
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___M 0x000000F0
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___M      0x000000FF   
#define   WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___S                    0

#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT             (0x00A89170)
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___M 0x0000000F
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___M      0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___S                    0

#define WMAC0_MCMN_R0_MCMN_ISR_P                  (0x00A89200)
#define   WMAC0_MCMN_R0_MCMN_ISR_P___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_P___POR         0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__SFM___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB1___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB0___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RRI___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MXI___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__PDG___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___M     0x04000000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___S                  26
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___M    0x02000000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___S                 25
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___M    0x01000000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___S                 24
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___S              22
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___S              21
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___S              20
#define   WMAC0_MCMN_R0_MCMN_ISR_P__SFM___M      0x00040000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__SFM___S                   18
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___M    0x00020000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___S                 17
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___M    0x00010000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___S                 16
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB1___M     0x00008000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB1___S                  15
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB0___M     0x00004000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__APB0___S                  14
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RRI___M      0x00002000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RRI___S                   13
#define   WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___M     0x00001000
#define   WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___S                  12
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MXI___M      0x00000800
#define   WMAC0_MCMN_R0_MCMN_ISR_P__MXI___S                   11
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___M   0x00000400
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___S                10
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___M   0x00000200
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___S                 9
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___M   0x00000100
#define   WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___S                 8
#define   WMAC0_MCMN_R0_MCMN_ISR_P__PDG___M      0x00000080
#define   WMAC0_MCMN_R0_MCMN_ISR_P__PDG___S                    7
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___M   0x00000040
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___S                 6
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___M   0x00000020
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___S                 5
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___M   0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___S                 4
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___M   0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___S                 3
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___M    0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___S                  2
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___M    0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___S                  1
#define   WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___M   0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___S                 0
#define   WMAC0_MCMN_R0_MCMN_ISR_P___M           0x0777FFFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_P___S                         0

#define WMAC0_MCMN_R0_MCMN_IMR_P                  (0x00A89204)
#define   WMAC0_MCMN_R0_MCMN_IMR_P___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_P___POR         0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__SFM___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB1___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB0___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RRI___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___POR   0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MXI___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__PDG___POR    0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___M     0x04000000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___S                  26
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___M    0x02000000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___S                 25
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___M    0x01000000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___S                 24
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___S              22
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___S              21
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___S              20
#define   WMAC0_MCMN_R0_MCMN_IMR_P__SFM___M      0x00040000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__SFM___S                   18
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___M    0x00020000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___S                 17
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___M    0x00010000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___S                 16
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB1___M     0x00008000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB1___S                  15
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB0___M     0x00004000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__APB0___S                  14
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RRI___M      0x00002000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RRI___S                   13
#define   WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___M     0x00001000
#define   WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___S                  12
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MXI___M      0x00000800
#define   WMAC0_MCMN_R0_MCMN_IMR_P__MXI___S                   11
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___M   0x00000400
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___S                10
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___M   0x00000200
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___S                 9
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___M   0x00000100
#define   WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___S                 8
#define   WMAC0_MCMN_R0_MCMN_IMR_P__PDG___M      0x00000080
#define   WMAC0_MCMN_R0_MCMN_IMR_P__PDG___S                    7
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___M   0x00000040
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___S                 6
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___M   0x00000020
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___S                 5
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___M   0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___S                 4
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___M   0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___S                 3
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___M    0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___S                  2
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___M    0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___S                  1
#define   WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___M   0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___S                 0
#define   WMAC0_MCMN_R0_MCMN_IMR_P___M           0x0777FFFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_P___S                         0

#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR          (0x00A89208)
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___RWC    QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___POR 0x00000000
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___POR 0x00
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___M 0x000000FF
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___S               0
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___M   0x000000FF   
#define   WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___S                 0

#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32 (0x00A8920C)
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___M 0xFFFFFFFF
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___S               0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___S               0

#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16 (0x00A89210)
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___POR 0x0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___POR 0x0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___POR 0x0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___POR 0x0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___POR 0x0000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___M 0x00080000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___S              19
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___M 0x00040000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___S              18
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___M 0x00020000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___S              17
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___M 0x00010000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___S              16
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___M 0x0000FFFF
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___S               0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___M 0x000FFFFF   
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___S               0

#define WMAC0_MCMN_R0_WMAC_RTL_VERSION            (0x00A89214)
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION___RWC      QCSR_REG_RO    
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION___POR   0x00000000
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___POR 0x00000000
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___M 0xFFFFFFFF
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___S               0
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION___M     0xFFFFFFFF   
#define   WMAC0_MCMN_R0_WMAC_RTL_VERSION___S                   0

#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32 (0x00A89218)
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___M 0xFFFFFFFF
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___S               0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___S               0

#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16 (0x00A8921C)
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___POR 0x00000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___POR 0x0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___POR 0x0000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___POR 0x0000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___M 0x40000000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___S              30
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___M 0x1FFF0000
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___S              16
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___M 0x0000FFFF
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___S               0
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___M 0x5FFFFFFF   
#define   WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___S               0

#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE        (0x00A89224)
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___POR 0x00000002
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___POR 0x1
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___M 0x00000002
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___S               1
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___M 0x00000001
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___S               0
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___M 0x00000003   
#define   WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___S               0

#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL     (0x00A89230)
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___POR 0x00000280
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___POR 0x0280
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___M 0x80000000
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___S              31
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___M 0x40000000
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___S              30
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___M 0x0000FFFF
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___S               0
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___M 0xC000FFFF   
#define   WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___S               0

#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE             (0x00A89234)
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___S               6
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___S               5
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___S               4
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___S               3
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___S               2
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___S               0
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___M      0x0000007F   
#define   WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___S                    0

#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH            (0x00A89238)
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___RWC      QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___POR   0x0000000A
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___POR 0x0A
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___M 0x0000003F
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___S               0
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___M     0x0000003F   
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___S                   0

#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK              (0x00A89240)
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK___POR     0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___POR 0x000
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___M 0x00001FF8
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK___M       0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK___S                     0

#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1             (0x00A89244)
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___POR 0x000
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___M 0x00001FF8
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___M      0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___S                    0

#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK              (0x00A89248)
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK___POR     0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___POR 0x000
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___M 0x00001FF8
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK___M       0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK___S                     0

#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1             (0x00A8924C)
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___POR    0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___POR 0x000
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___M 0x00001FF8
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___M      0x00001FFF   
#define   WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___S                    0

#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP          (0x00A89250)
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___RWC    QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___S               4
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___S               3
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___S               2
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___M   0x0000001F   
#define   WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___S                 0

#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP          (0x00A89254)
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___RWC    QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___S               4
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___S               3
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___S               2
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___M   0x0000001F   
#define   WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___S                 0

#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK              (0x00A89258)
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK___POR     0x00000000
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___S               1
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___S               0
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK___M       0x00000003   
#define   WMAC0_MCMN_R0_MCMN_ISR_TX_OK___S                     0

#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK              (0x00A8925C)
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK___POR     0x00000000
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___S               1
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___S               0
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK___M       0x00000003   
#define   WMAC0_MCMN_R0_MCMN_IMR_TX_OK___S                     0

#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN         (0x00A89260)
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___RWC   QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___S               0
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___M  0x00000001   
#define   WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___S                0

#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL        (0x00A89264)
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___POR 0x00000000
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___POR 0x0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___M 0x00000010
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___S               4
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___M 0x00000008
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___S               3
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___M 0x00000004
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___S               2
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___M 0x00000002
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___S               1
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___M 0x00000001
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___S               0
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___M 0x0000001F   
#define   WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___S               0

#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN        (0x00A89268)
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___POR 0x0002FFFF
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___S              17
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___S              15
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___S              14
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___S              13
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___S              12
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___S              11
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___S              10
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___S               9
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___S               8
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___S               7
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___S               6
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___S               5
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___S               3
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___S               2
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___S               0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___M 0x0002FFFF   
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___S               0

#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS  (0x00A8926C)
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___POR 0x000088C8
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___POR 0x1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___S              17
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___S              15
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___S              14
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___S              13
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___S              12
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___S              11
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___S              10
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___S               9
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___S               8
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___S               7
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___S               6
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___S               5
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___S               3
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___S               2
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___S               0
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___M 0x0002FFFF   
#define   WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___S               0

#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET         (0x00A89270)
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___RWC   QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___S              18
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___S              16
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___S              15
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___S              14
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___S              13
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___S              12
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___S              11
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___S              10
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___S               9
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___S               8
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___S               7
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___S               6
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___S               5
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___S               3
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___S               2
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___S               0
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___M  0x0005FFFF   
#define   WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___S                0

#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET       (0x00A89274)
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___S              17
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___S              15
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___S              14
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___S              13
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___S              12
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___S              11
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___S              10
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___S               9
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___S               8
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___S               7
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___S               6
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___S               5
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___S               3
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___S               2
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___S               0
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___M 0x0002FFFF   
#define   WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___S               0

#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE    (0x00A89278)
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___S              14
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___S              12
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___S              11
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___S              10
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___S               9
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___S               8
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___S               7
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___S               6
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___S               5
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___S               3
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___S               2
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___S               1
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___S               0
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___M 0x00005FFF   
#define   WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___S               0

#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE       (0x00A8927C)
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___POR 0x00000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___M 0x40000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___S              30
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___M 0x30000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___S              28
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___M 0x08000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___S              27
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___M 0x04000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___S              26
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___M 0x02000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___S              25
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___M 0x01000000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___S              24
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___M 0x00800000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___S              23
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___S              22
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___S              21
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___M 0x00100000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___S              20
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___S              19
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___S              18
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___M 0x00020000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___S              17
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___M 0x00010000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___S              16
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___M 0x00008000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___S              15
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___M 0x00004000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___S              14
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___S              13
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___S              12
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___S              11
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___S              10
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___S               9
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___S               8
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___S               7
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___S               6
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___S               5
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___S               4
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___S               3
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___S               2
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___M 0x00000002
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___S               1
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___M 0x00000001
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___S               0
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___S               0

#define WMAC0_MCMN_R0_WMAC_REVISION               (0x00A89280)
#define   WMAC0_MCMN_R0_WMAC_REVISION___RWC         QCSR_REG_RO    
#define   WMAC0_MCMN_R0_WMAC_REVISION___POR      0x10080000
#define   WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___POR 0x1
#define   WMAC0_MCMN_R0_WMAC_REVISION__MINOR___POR 0x008
#define   WMAC0_MCMN_R0_WMAC_REVISION__STEP___POR 0x0000
#define   WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___M 0xF0000000
#define   WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___S              28
#define   WMAC0_MCMN_R0_WMAC_REVISION__MINOR___M 0x0FFF0000
#define   WMAC0_MCMN_R0_WMAC_REVISION__MINOR___S              16
#define   WMAC0_MCMN_R0_WMAC_REVISION__STEP___M  0x0000FFFF
#define   WMAC0_MCMN_R0_WMAC_REVISION__STEP___S                0
#define   WMAC0_MCMN_R0_WMAC_REVISION___M        0xFFFFFFFF   
#define   WMAC0_MCMN_R0_WMAC_REVISION___S                      0

#define WMAC0_MCMN_R0_MCMN_INVALID_APB            (0x00A89284)
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB___RWC      QCSR_REG_RO    
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB___POR   0x00000000
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___POR 0x00000
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___M 0x0001FFFF
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___S               0
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB___M     0x0001FFFF   
#define   WMAC0_MCMN_R0_MCMN_INVALID_APB___S                   0

#define WMAC0_MCMN_R0_MCMN_MAC_IDLE               (0x00A89288)
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE___RWC         QCSR_REG_RO    
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE___POR      0x00000000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___POR  0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___M    0x01000000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___S                 24
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___M    0x00800000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___S                 23
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___M 0x00400000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___S              22
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___M 0x00200000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___S              21
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___M  0x00100000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___S               20
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___M 0x00080000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___S              19
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___M 0x00040000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___S              18
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___M   0x00010000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___S                16
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___M   0x00008000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___S                15
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___M   0x00004000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___S                14
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___M 0x00002000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___S              13
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___M 0x00001000
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___S              12
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___M 0x00000800
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___S              11
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___M 0x00000400
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___S              10
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___M 0x00000200
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___S               9
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___M 0x00000100
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___S               8
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___M 0x00000080
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___S               7
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___M 0x00000040
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___S               6
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___M 0x00000020
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___S               5
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___M 0x00000010
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___S               4
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___M   0x00000008
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___S                 3
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___S               2
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___M   0x00000001
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___S                 0
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE___M        0x01FDFFFD   
#define   WMAC0_MCMN_R0_MCMN_MAC_IDLE___S                      0

#define WMAC0_MCMN_R0_MCMN_CONFIG                 (0x00A8928C)
#define   WMAC0_MCMN_R0_MCMN_CONFIG___RWC           QCSR_REG_RW    
#define   WMAC0_MCMN_R0_MCMN_CONFIG___POR        0x00000000
#define   WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___POR 0x0
#define   WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___M 0x00000008
#define   WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___S               3
#define   WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___M 0x00000004
#define   WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___S               2
#define   WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___M 0x00000003
#define   WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___S               0
#define   WMAC0_MCMN_R0_MCMN_CONFIG___M          0x0000000F   
#define   WMAC0_MCMN_R0_MCMN_CONFIG___S                        0

#define WMAC0_MCMN_R0_IDLE_CTRL0                  (0x00A89290)
#define   WMAC0_MCMN_R0_IDLE_CTRL0___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL0___POR         0x00007810
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___POR 0x00F
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___POR 0x008
#define   WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___M 0x001FF800
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___S              11
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___M 0x000007FE
#define   WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___S               1
#define   WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___M 0x00000001
#define   WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL0___M           0x001FFFFF   
#define   WMAC0_MCMN_R0_IDLE_CTRL0___S                         0

#define WMAC0_MCMN_R0_IDLE_CTRL1                  (0x00A89294)
#define   WMAC0_MCMN_R0_IDLE_CTRL1___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL1___POR         0x7FFFFBFF
#define   WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___POR 0x3FF
#define   WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___POR 0x3FF
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___POR 0x3FF
#define   WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___M 0x7FE00000
#define   WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___S              21
#define   WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___M 0x001FF800
#define   WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___S              11
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___M 0x00000400
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___S              10
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___M 0x000003FF
#define   WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL1___M           0x7FFFFFFF   
#define   WMAC0_MCMN_R0_IDLE_CTRL1___S                         0

#define WMAC0_MCMN_R0_IDLE_CTRL2                  (0x00A89298)
#define   WMAC0_MCMN_R0_IDLE_CTRL2___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL2___POR         0x00000000
#define   WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___M 0x00000200
#define   WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___S               9
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___M 0x00000100
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___S               8
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___M 0x00000080
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___S               7
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___M 0x00000040
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___S               6
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___M 0x00000020
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___S               5
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___M 0x00000010
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___S               4
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___M 0x00000008
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___S               3
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___M 0x00000004
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___S               2
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___M 0x00000002
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___S               1
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___M 0x00000001
#define   WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL2___M           0x000003FF   
#define   WMAC0_MCMN_R0_IDLE_CTRL2___S                         0

#define WMAC0_MCMN_R0_IDLE_CTRL3                  (0x00A8929C)
#define   WMAC0_MCMN_R0_IDLE_CTRL3___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL3___POR         0x0003FCFF
#define   WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___POR 0x0FF
#define   WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___POR 0x0FF
#define   WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___M 0x000FFC00
#define   WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___S              10
#define   WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___M 0x000003FF
#define   WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL3___M           0x000FFFFF   
#define   WMAC0_MCMN_R0_IDLE_CTRL3___S                         0

#define WMAC0_MCMN_R0_IDLE_CTRL4                  (0x00A892A0)
#define   WMAC0_MCMN_R0_IDLE_CTRL4___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL4___POR         0x0003FCFF
#define   WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___POR 0x0FF
#define   WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___POR 0x0FF
#define   WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___M 0x000FFC00
#define   WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___S              10
#define   WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___M 0x000003FF
#define   WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL4___M           0x000FFFFF   
#define   WMAC0_MCMN_R0_IDLE_CTRL4___S                         0

#define WMAC0_MCMN_R0_IDLE_CTRL5                  (0x00A892A4)
#define   WMAC0_MCMN_R0_IDLE_CTRL5___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R0_IDLE_CTRL5___POR         0x00000000
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___POR 0x0
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___M 0x00000004
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___S               2
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___M 0x00000002
#define   WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___S               1
#define   WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___M 0x00000001
#define   WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___S               0
#define   WMAC0_MCMN_R0_IDLE_CTRL5___M           0x00000007   
#define   WMAC0_MCMN_R0_IDLE_CTRL5___S                         0

#define WMAC0_MCMN_R0_S_PARE0                     (0x00A892A8)
#define   WMAC0_MCMN_R0_S_PARE0___RWC               QCSR_REG_RW    
#define   WMAC0_MCMN_R0_S_PARE0___POR            0x00000000
#define   WMAC0_MCMN_R0_S_PARE0__VAL___POR       0x00000000
#define   WMAC0_MCMN_R0_S_PARE0__VAL___M         0xFFFFFFFF
#define   WMAC0_MCMN_R0_S_PARE0__VAL___S                       0
#define   WMAC0_MCMN_R0_S_PARE0___M              0xFFFFFFFF   
#define   WMAC0_MCMN_R0_S_PARE0___S                            0

#define WMAC0_MCMN_R0_S_PARE1                     (0x00A892AC)
#define   WMAC0_MCMN_R0_S_PARE1___RWC               QCSR_REG_RW    
#define   WMAC0_MCMN_R0_S_PARE1___POR            0x00000000
#define   WMAC0_MCMN_R0_S_PARE1__VAL___POR       0x00000000
#define   WMAC0_MCMN_R0_S_PARE1__VAL___M         0xFFFFFFFF
#define   WMAC0_MCMN_R0_S_PARE1__VAL___S                       0
#define   WMAC0_MCMN_R0_S_PARE1___M              0xFFFFFFFF   
#define   WMAC0_MCMN_R0_S_PARE1___S                            0

#define WMAC0_MCMN_R0_S_PARE2                     (0x00A892B0)
#define   WMAC0_MCMN_R0_S_PARE2___RWC               QCSR_REG_RW    
#define   WMAC0_MCMN_R0_S_PARE2___POR            0x00000000
#define   WMAC0_MCMN_R0_S_PARE2__VAL___POR       0x00000000
#define   WMAC0_MCMN_R0_S_PARE2__VAL___M         0xFFFFFFFF
#define   WMAC0_MCMN_R0_S_PARE2__VAL___S                       0
#define   WMAC0_MCMN_R0_S_PARE2___M              0xFFFFFFFF   
#define   WMAC0_MCMN_R0_S_PARE2___S                            0

#define WMAC0_MCMN_R0_S_PARE3                     (0x00A892B4)
#define   WMAC0_MCMN_R0_S_PARE3___RWC               QCSR_REG_RW    
#define   WMAC0_MCMN_R0_S_PARE3___POR            0x00000000
#define   WMAC0_MCMN_R0_S_PARE3__VAL___POR       0x00000000
#define   WMAC0_MCMN_R0_S_PARE3__VAL___M         0xFFFFFFFF
#define   WMAC0_MCMN_R0_S_PARE3__VAL___S                       0
#define   WMAC0_MCMN_R0_S_PARE3___M              0xFFFFFFFF   
#define   WMAC0_MCMN_R0_S_PARE3___S                            0

#define WMAC0_MCMN_R0_L0_REQ_OVERIDE              (0x00A892BC)
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE___POR     0x00000000
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___POR 0x0
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___POR 0x0
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___M 0x00000002
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___S               1
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___M 0x00000001
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___S               0
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE___M       0x00000003   
#define   WMAC0_MCMN_R0_L0_REQ_OVERIDE___S                     0

#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB        (0x00A892C0)
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___POR 0x0000000A
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___POR 0x0A
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___M 0x0000003F
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___S               0
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___M 0x0000003F   
#define   WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___S               0

#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT        (0x00A8A000)
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___S               0

#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT        (0x00A8A004)
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___S               0

#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT        (0x00A8A008)
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___RWC  QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___S               0

#define WMAC0_MCMN_R1_TRC_VID0                    (0x00A8A00C)
#define   WMAC0_MCMN_R1_TRC_VID0___RWC              QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_VID0___POR           0x0C520C41
#define   WMAC0_MCMN_R1_TRC_VID0__RXOLE___POR    0x06
#define   WMAC0_MCMN_R1_TRC_VID0__TXOLE___POR    0x05
#define   WMAC0_MCMN_R1_TRC_VID0__RXDMA___POR    0x04
#define   WMAC0_MCMN_R1_TRC_VID0__TXDMA___POR    0x03
#define   WMAC0_MCMN_R1_TRC_VID0__PDG___POR      0x02
#define   WMAC0_MCMN_R1_TRC_VID0__HWSCH___POR    0x01
#define   WMAC0_MCMN_R1_TRC_VID0__RXOLE___M      0x3E000000
#define   WMAC0_MCMN_R1_TRC_VID0__RXOLE___S                   25
#define   WMAC0_MCMN_R1_TRC_VID0__TXOLE___M      0x01F00000
#define   WMAC0_MCMN_R1_TRC_VID0__TXOLE___S                   20
#define   WMAC0_MCMN_R1_TRC_VID0__RXDMA___M      0x000F8000
#define   WMAC0_MCMN_R1_TRC_VID0__RXDMA___S                   15
#define   WMAC0_MCMN_R1_TRC_VID0__TXDMA___M      0x00007C00
#define   WMAC0_MCMN_R1_TRC_VID0__TXDMA___S                   10
#define   WMAC0_MCMN_R1_TRC_VID0__PDG___M        0x000003E0
#define   WMAC0_MCMN_R1_TRC_VID0__PDG___S                      5
#define   WMAC0_MCMN_R1_TRC_VID0__HWSCH___M      0x0000001F
#define   WMAC0_MCMN_R1_TRC_VID0__HWSCH___S                    0
#define   WMAC0_MCMN_R1_TRC_VID0___M             0x3FFFFFFF   
#define   WMAC0_MCMN_R1_TRC_VID0___S                           0

#define WMAC0_MCMN_R1_TRC_VID1                    (0x00A8A010)
#define   WMAC0_MCMN_R1_TRC_VID1___RWC              QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_VID1___POR           0x18B52507
#define   WMAC0_MCMN_R1_TRC_VID1__C___POR        0x0C
#define   WMAC0_MCMN_R1_TRC_VID1__AMPI___POR     0x0B
#define   WMAC0_MCMN_R1_TRC_VID1__RRI___POR      0x0A
#define   WMAC0_MCMN_R1_TRC_VID1__RXPCU___POR    0x09
#define   WMAC0_MCMN_R1_TRC_VID1__TXPCU___POR    0x08
#define   WMAC0_MCMN_R1_TRC_VID1__CRYPTO___POR   0x07
#define   WMAC0_MCMN_R1_TRC_VID1__C___M          0x3E000000
#define   WMAC0_MCMN_R1_TRC_VID1__C___S                       25
#define   WMAC0_MCMN_R1_TRC_VID1__AMPI___M       0x01F00000
#define   WMAC0_MCMN_R1_TRC_VID1__AMPI___S                    20
#define   WMAC0_MCMN_R1_TRC_VID1__RRI___M        0x000F8000
#define   WMAC0_MCMN_R1_TRC_VID1__RRI___S                     15
#define   WMAC0_MCMN_R1_TRC_VID1__RXPCU___M      0x00007C00
#define   WMAC0_MCMN_R1_TRC_VID1__RXPCU___S                   10
#define   WMAC0_MCMN_R1_TRC_VID1__TXPCU___M      0x000003E0
#define   WMAC0_MCMN_R1_TRC_VID1__TXPCU___S                    5
#define   WMAC0_MCMN_R1_TRC_VID1__CRYPTO___M     0x0000001F
#define   WMAC0_MCMN_R1_TRC_VID1__CRYPTO___S                   0
#define   WMAC0_MCMN_R1_TRC_VID1___M             0x3FFFFFFF   
#define   WMAC0_MCMN_R1_TRC_VID1___S                           0

#define WMAC0_MCMN_R1_TRC_VID2                    (0x00A8A014)
#define   WMAC0_MCMN_R1_TRC_VID2___RWC              QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_VID2___POR           0x251801CD
#define   WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___POR 0x0
#define   WMAC0_MCMN_R1_TRC_VID2__SFM___POR      0x12
#define   WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___POR  0x11
#define   WMAC0_MCMN_R1_TRC_VID2__LPEC___POR     0x10
#define   WMAC0_MCMN_R1_TRC_VID2__MCMN___POR     0x0E
#define   WMAC0_MCMN_R1_TRC_VID2__MXI___POR      0x0D
#define   WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___M 0x80000000
#define   WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___S              31
#define   WMAC0_MCMN_R1_TRC_VID2__SFM___M        0x3E000000
#define   WMAC0_MCMN_R1_TRC_VID2__SFM___S                     25
#define   WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___M    0x01F00000
#define   WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___S                 20
#define   WMAC0_MCMN_R1_TRC_VID2__LPEC___M       0x000F8000
#define   WMAC0_MCMN_R1_TRC_VID2__LPEC___S                    15
#define   WMAC0_MCMN_R1_TRC_VID2__MCMN___M       0x000003E0
#define   WMAC0_MCMN_R1_TRC_VID2__MCMN___S                     5
#define   WMAC0_MCMN_R1_TRC_VID2__MXI___M        0x0000001F
#define   WMAC0_MCMN_R1_TRC_VID2__MXI___S                      0
#define   WMAC0_MCMN_R1_TRC_VID2___M             0xBFFF83FF   
#define   WMAC0_MCMN_R1_TRC_VID2___S                           0

#define WMAC0_MCMN_R1_TRC_VID3                    (0x00A8A018)
#define   WMAC0_MCMN_R1_TRC_VID3___RWC              QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_VID3___POR           0x00000013
#define   WMAC0_MCMN_R1_TRC_VID3__LPECEB1___POR  0x13
#define   WMAC0_MCMN_R1_TRC_VID3__LPECEB1___M    0x0000001F
#define   WMAC0_MCMN_R1_TRC_VID3__LPECEB1___S                  0
#define   WMAC0_MCMN_R1_TRC_VID3___M             0x0000001F   
#define   WMAC0_MCMN_R1_TRC_VID3___S                           0

#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT           (0x00A8A01C)
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___RWC     QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___POR  0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___M    0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___S                  0

#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT         (0x00A8A020)
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___RWC   QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___POR 0x00000000
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___POR 0x0
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___M 0x00000001
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___S               0
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___M  0x00000001   
#define   WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___S                0

#define WMAC0_MCMN_R1_DEBUG_LMAC                  (0x00A8A024)
#define   WMAC0_MCMN_R1_DEBUG_LMAC___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R1_DEBUG_LMAC___POR         0x00000000
#define   WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___POR 0x0
#define   WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___M  0x0000000F
#define   WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___S                0
#define   WMAC0_MCMN_R1_DEBUG_LMAC___M           0x0000000F   
#define   WMAC0_MCMN_R1_DEBUG_LMAC___S                         0

#define WMAC0_MCMN_R1_LMAC_IDLE                   (0x00A8A028)
#define   WMAC0_MCMN_R1_LMAC_IDLE___RWC             QCSR_REG_RO    
#define   WMAC0_MCMN_R1_LMAC_IDLE___POR          0x00000000
#define   WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___POR 0x0
#define   WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___POR 0x000
#define   WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___POR 0x00
#define   WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___POR 0x000
#define   WMAC0_MCMN_R1_LMAC_IDLE__VALUE___POR   0x0
#define   WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___M 0x10000000
#define   WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___S              28
#define   WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___M 0x0FF80000
#define   WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___S              19
#define   WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___M  0x0007F800
#define   WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___S               11
#define   WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___M  0x000007FE
#define   WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___S                1
#define   WMAC0_MCMN_R1_LMAC_IDLE__VALUE___M     0x00000001
#define   WMAC0_MCMN_R1_LMAC_IDLE__VALUE___S                   0
#define   WMAC0_MCMN_R1_LMAC_IDLE___M            0x1FFFFFFF   
#define   WMAC0_MCMN_R1_LMAC_IDLE___S                          0

#define WMAC0_MCMN_R1_MCMN_STM_SELECT1            (0x00A8A02C)
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1___RWC      QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1___POR   0x00000000
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___POR 0x0
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___M 0x0000000F
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___S               0
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1___M     0x0000000F   
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT1___S                   0

#define WMAC0_MCMN_R1_TESTBUS_SELECT              (0x00A8A030)
#define   WMAC0_MCMN_R1_TESTBUS_SELECT___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TESTBUS_SELECT___POR     0x00000000
#define   WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___POR 0x00
#define   WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___M 0x0000001F
#define   WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___S               0
#define   WMAC0_MCMN_R1_TESTBUS_SELECT___M       0x0000001F   
#define   WMAC0_MCMN_R1_TESTBUS_SELECT___S                     0

#define WMAC0_MCMN_R1_TLV_READY                   (0x00A8A034)
#define   WMAC0_MCMN_R1_TLV_READY___RWC             QCSR_REG_RO    
#define   WMAC0_MCMN_R1_TLV_READY___POR          0x00000000
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___M 0x00080000
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___S              19
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___M 0x00040000
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___S              18
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___M 0x00020000
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___S              17
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___M 0x00010000
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___S              16
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___M 0x00008000
#define   WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___S              15
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___M 0x00004000
#define   WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___S              14
#define   WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___M 0x00002000
#define   WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___S              13
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___M 0x00001000
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___S              12
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___M 0x00000800
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___S              11
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___M 0x00000400
#define   WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___S              10
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___M 0x00000200
#define   WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___S               9
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___M 0x00000100
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___S               8
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___M 0x00000080
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___S               7
#define   WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___M 0x00000040
#define   WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___S               6
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___M 0x00000020
#define   WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___S               5
#define   WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___M 0x00000010
#define   WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___S               4
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___M 0x00000008
#define   WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___S               3
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___M 0x00000004
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___S               2
#define   WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___M 0x00000002
#define   WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___S               1
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___M 0x00000001
#define   WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___S               0
#define   WMAC0_MCMN_R1_TLV_READY___M            0x000FFFFF   
#define   WMAC0_MCMN_R1_TLV_READY___S                          0

#define WMAC0_MCMN_R1_TRC_SELECT                  (0x00A8A038)
#define   WMAC0_MCMN_R1_TRC_SELECT___RWC            QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_SELECT___POR         0x00000001
#define   WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___POR 0x0
#define   WMAC0_MCMN_R1_TRC_SELECT__VAL___POR    0x1
#define   WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___M 0x00000002
#define   WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___S               1
#define   WMAC0_MCMN_R1_TRC_SELECT__VAL___M      0x00000001
#define   WMAC0_MCMN_R1_TRC_SELECT__VAL___S                    0
#define   WMAC0_MCMN_R1_TRC_SELECT___M           0x00000003   
#define   WMAC0_MCMN_R1_TRC_SELECT___S                         0

#define WMAC0_MCMN_R1_TRC_BLOCK_MASK              (0x00A8A03C)
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK___RWC        QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK___POR     0x00000000
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___POR 0x00000
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___M  0x000FFFFF
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___S                0
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK___M       0x000FFFFF   
#define   WMAC0_MCMN_R1_TRC_BLOCK_MASK___S                     0

#define WMAC0_MCMN_R1_TRC_SW_EVENT                (0x00A8A040)
#define   WMAC0_MCMN_R1_TRC_SW_EVENT___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TRC_SW_EVENT___POR       0x00000000
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___POR 0x0
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__IN___POR   0x00000000
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___M  0x40000000
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___S               30
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__IN___M     0x3FFFFFFF
#define   WMAC0_MCMN_R1_TRC_SW_EVENT__IN___S                   0
#define   WMAC0_MCMN_R1_TRC_SW_EVENT___M         0x7FFFFFFF   
#define   WMAC0_MCMN_R1_TRC_SW_EVENT___S                       0

#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT (0x00A8A044)
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___S               0

#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT (0x00A8A048)
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___S               0

#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT (0x00A8A04C)
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___S               0

#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT (0x00A8A050)
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___POR 0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___S               0

#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT          (0x00A8A054)
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___RWC    QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___POR 0x00000000
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___POR 0x00
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___POR 0x0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___POR 0x0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___POR 0x0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___POR 0x00
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___M 0x003FC000
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___S              14
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___M 0x00003000
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___S              12
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___M 0x00000C00
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___S              10
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___M 0x00000300
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___S               8
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___M 0x000000C0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___S               6
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___M 0x00000020
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___S               5
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___M 0x0000001F
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___S               0
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___M   0x003FFFFF   
#define   WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___S                 0

#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL       (0x00A8A058)
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___POR 0x00000000
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___POR 0x0
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___M 0x00000003
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___S               0
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___M 0x00000003   
#define   WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___S               0

#define WMAC0_MCMN_R1_SUBSYSTEM_ID                (0x00A8A05C)
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID___POR       0x00000001
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___POR  0x1
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___M    0x00000003
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___S                  0
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID___M         0x00000003   
#define   WMAC0_MCMN_R1_SUBSYSTEM_ID___S                       0

#define WMAC0_MCMN_R1_DEBUG_ENABLE                (0x00A8A060)
#define   WMAC0_MCMN_R1_DEBUG_ENABLE___RWC          QCSR_REG_RW    
#define   WMAC0_MCMN_R1_DEBUG_ENABLE___POR       0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___POR 0x000
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___POR 0x0
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___POR  0x0
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___M 0x0FFF0000
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___S              16
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___M 0x00000002
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___S               1
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___M    0x00000001
#define   WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___S                  0
#define   WMAC0_MCMN_R1_DEBUG_ENABLE___M         0x0FFF0003   
#define   WMAC0_MCMN_R1_DEBUG_ENABLE___S                       0

#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ      (0x00A8A064)
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME (0x00A8A068)
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ      (0x00A8A06C)
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME (0x00A8A070)
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ (0x00A8A074)
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME (0x00A8A078)
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ   (0x00A8A07C)
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___S               0

#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME (0x00A8A080)
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___RWC QCSR_REG_RO    
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___POR 0x00000000
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___S               0
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___S               0

#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW             (0x00A8A220)
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___RWC       QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___POR    0x00000000
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___POR 0x0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___POR 0x0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___POR 0x0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___POR 0x0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___POR 0x0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___M 0x00000010
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___S               4
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___M 0x00000008
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___S               3
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___M 0x00000004
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___S               2
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___M 0x00000002
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___S               1
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___M 0x00000001
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___S               0
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___M      0x0000001F   
#define   WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___S                    0

#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0     (0x00A8A228)
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___POR 0x00000000
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___POR 0x00000000
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___S               0
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___S               0

#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1     (0x00A8A22C)
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___POR 0x00000000
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___POR 0x000
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___M 0x00000FFF
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___S               0
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___M 0x00000FFF   
#define   WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___S               0

#define WMAC0_MCMN_R1_MCMN_STM_SELECT0            (0x00A8A23C)
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0___RWC      QCSR_REG_RW    
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0___POR   0x00000000
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___POR 0x00000000
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___M 0xFFFFFFFF
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___S               0
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0___M     0xFFFFFFFF   
#define   WMAC0_MCMN_R1_MCMN_STM_SELECT0___S                   0

#define WMAC0_RXPCU_R0_BSSID2_L32                 (0x00A8C000)
#define   WMAC0_RXPCU_R0_BSSID2_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID2_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID2_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID2_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID2_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID2_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID2_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID2_U16                 (0x00A8C004)
#define   WMAC0_RXPCU_R0_BSSID2_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID2_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___POR 0x0
#define   WMAC0_RXPCU_R0_BSSID2_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID2_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___M 0x40000000
#define   WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___S              30
#define   WMAC0_RXPCU_R0_BSSID2_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID2_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID2_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID2_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID2_U16___M          0x7FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID2_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID3_L32                 (0x00A8C008)
#define   WMAC0_RXPCU_R0_BSSID3_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID3_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID3_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID3_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID3_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID3_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID3_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID3_U16                 (0x00A8C00C)
#define   WMAC0_RXPCU_R0_BSSID3_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID3_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID3_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID3_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID3_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID3_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID3_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID3_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID3_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID3_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID4_L32                 (0x00A8C010)
#define   WMAC0_RXPCU_R0_BSSID4_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID4_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID4_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID4_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID4_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID4_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID4_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID4_U16                 (0x00A8C014)
#define   WMAC0_RXPCU_R0_BSSID4_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID4_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID4_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID4_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID4_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID4_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID4_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID4_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID4_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID4_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID5_L32                 (0x00A8C018)
#define   WMAC0_RXPCU_R0_BSSID5_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID5_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID5_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID5_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID5_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID5_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID5_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID5_U16                 (0x00A8C01C)
#define   WMAC0_RXPCU_R0_BSSID5_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID5_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID5_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID5_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID5_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID5_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID5_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID5_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID5_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID5_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID6_L32                 (0x00A8C020)
#define   WMAC0_RXPCU_R0_BSSID6_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID6_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID6_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID6_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID6_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID6_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID6_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID6_U16                 (0x00A8C024)
#define   WMAC0_RXPCU_R0_BSSID6_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID6_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID6_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID6_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID6_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID6_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID6_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID6_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID6_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID6_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID7_L32                 (0x00A8C028)
#define   WMAC0_RXPCU_R0_BSSID7_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID7_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID7_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID7_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID7_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID7_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID7_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID7_U16                 (0x00A8C02C)
#define   WMAC0_RXPCU_R0_BSSID7_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID7_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID7_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID7_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID7_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID7_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID7_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID7_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID7_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID7_U16___S                        0

#define WMAC0_RXPCU_R0_BSSID8_L32                 (0x00A8C030)
#define   WMAC0_RXPCU_R0_BSSID8_L32___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID8_L32___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID8_L32__ADDR___POR  0x00000000
#define   WMAC0_RXPCU_R0_BSSID8_L32__ADDR___M    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSSID8_L32__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID8_L32___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSSID8_L32___S                        0

#define WMAC0_RXPCU_R0_BSSID8_U16                 (0x00A8C034)
#define   WMAC0_RXPCU_R0_BSSID8_U16___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSSID8_U16___POR        0x00000000
#define   WMAC0_RXPCU_R0_BSSID8_U16__AID___POR   0x0000
#define   WMAC0_RXPCU_R0_BSSID8_U16__ADDR___POR  0x0000
#define   WMAC0_RXPCU_R0_BSSID8_U16__AID___M     0x3FFE0000
#define   WMAC0_RXPCU_R0_BSSID8_U16__AID___S                  17
#define   WMAC0_RXPCU_R0_BSSID8_U16__ADDR___M    0x0000FFFF
#define   WMAC0_RXPCU_R0_BSSID8_U16__ADDR___S                  0
#define   WMAC0_RXPCU_R0_BSSID8_U16___M          0x3FFEFFFF   
#define   WMAC0_RXPCU_R0_BSSID8_U16___S                        0

#define WMAC0_RXPCU_R0_STA_ADDR2_L32              (0x00A8C038)
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR2_L32___S                     0

#define WMAC0_RXPCU_R0_STA_ADDR2_U16              (0x00A8C03C)
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___POR 0x0
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___POR 0x0000
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___M 0x80000000
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___S              31
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16___M       0x8000FFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR2_U16___S                     0

#define WMAC0_RXPCU_R0_STA_ADDR3_L32              (0x00A8C040)
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR3_L32___S                     0

#define WMAC0_RXPCU_R0_STA_ADDR3_U16              (0x00A8C044)
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___POR 0x0
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___POR 0x0000
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___M 0x80000000
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___S              31
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16___M       0x8000FFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR3_U16___S                     0

#define WMAC0_RXPCU_R0_STA_ADDR4_L32              (0x00A8C048)
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR4_L32___S                     0

#define WMAC0_RXPCU_R0_STA_ADDR4_U16              (0x00A8C04C)
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16___POR     0x00000000
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___POR 0x0
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___POR 0x0000
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___M 0x80000000
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___S              31
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___S               0
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16___M       0x8000FFFF   
#define   WMAC0_RXPCU_R0_STA_ADDR4_U16___S                     0

#define WMAC0_RXPCU_R0_ADDR4_MASK_L32             (0x00A8C050)
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32___POR    0xFFFFFFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_ADDR4_MASK_L32___S                    0

#define WMAC0_RXPCU_R0_ADDR4_MASK_U16             (0x00A8C054)
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16___POR    0x0000FFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___POR 0xFFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16___M      0x0000FFFF   
#define   WMAC0_RXPCU_R0_ADDR4_MASK_U16___S                    0

#define WMAC0_RXPCU_R0_HE_BSS1                    (0x00A8C058)
#define   WMAC0_RXPCU_R0_HE_BSS1___RWC              QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HE_BSS1___POR           0x00000000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___S              30
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___M 0x3F000000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___S              24
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___M 0x00400000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___S              22
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___M 0x003F0000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___S              16
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___M 0x00004000
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___S              14
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___M 0x00003F00
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___S               8
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___S               6
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___M 0x0000003F
#define   WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___S               0
#define   WMAC0_RXPCU_R0_HE_BSS1___M             0x7F7F7F7F   
#define   WMAC0_RXPCU_R0_HE_BSS1___S                           0

#define WMAC0_RXPCU_R0_HE_BSS2                    (0x00A8C05C)
#define   WMAC0_RXPCU_R0_HE_BSS2___RWC              QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HE_BSS2___POR           0x00000000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___S              30
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___M 0x3F000000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___S              24
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___M 0x00400000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___S              22
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___M 0x003F0000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___S              16
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___M 0x00004000
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___S              14
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___M 0x00003F00
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___S               8
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___S               6
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___M 0x0000003F
#define   WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___S               0
#define   WMAC0_RXPCU_R0_HE_BSS2___M             0x7F7F7F7F   
#define   WMAC0_RXPCU_R0_HE_BSS2___S                           0

#define WMAC0_RXPCU_R0_HE_BSS3                    (0x00A8C060)
#define   WMAC0_RXPCU_R0_HE_BSS3___RWC              QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HE_BSS3___POR           0x00000040
#define   WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___POR 0x0
#define   WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___POR 0x1
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___M 0x00020000
#define   WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___S              17
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___M 0x00010000
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___S              16
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___M 0x00008000
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___S              15
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___M 0x00004000
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___S              14
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___M 0x00002000
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___S              13
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___M 0x00001000
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___S              12
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___M 0x00000800
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___S              11
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___M 0x00000400
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___S              10
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___M 0x00000200
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___S               9
#define   WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___M 0x00000180
#define   WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___S               7
#define   WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___M 0x00000040
#define   WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___S               6
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___M 0x0000003F
#define   WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___S               0
#define   WMAC0_RXPCU_R0_HE_BSS3___M             0x0003FFFF   
#define   WMAC0_RXPCU_R0_HE_BSS3___S                           0

#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32       (0x00A8C064)
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___S               0

#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32       (0x00A8C068)
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___S               0

#define WMAC0_RXPCU_R0_RFF_RX_FILTER              (0x00A8C06C)
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER___POR     0x00000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___M 0x80000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___S              31
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___M 0x40000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___S              30
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___M 0x20000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___S              29
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___M 0x18000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___S              27
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___M 0x07E00000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___S              21
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___M 0x00100000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___S              20
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___M 0x00080000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___S              19
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___M 0x00040000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___S              18
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___M 0x00020000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___S              17
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___S              16
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___M 0x00008000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___S              15
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___M 0x00004000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___S              14
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___M 0x00002000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___S              13
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___M 0x00001000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___S              12
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___M 0x00000800
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___S              11
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___M 0x00000400
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___S              10
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___M 0x00000200
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___S               9
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___M 0x00000100
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___S               8
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___M 0x00000080
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___S               7
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___M 0x00000040
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___S               6
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___M 0x00000020
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___S               5
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___M 0x00000010
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___S               4
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___M 0x00000008
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___S               3
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___S               2
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___M 0x00000002
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___S               1
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___S               0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER___S                     0

#define WMAC0_RXPCU_R0_RFF_RX_FILTER2             (0x00A8C070)
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2___POR    0x00000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___M 0xFC000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___S              26
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___M 0x03F00000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___S              20
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___M 0x00080000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___S              19
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___M 0x00040000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___S              18
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___M 0x00030000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___S              16
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___M 0x0000C000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___S              14
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___M 0x00002000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___S              13
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___M 0x00001000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___S              12
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___M 0x00000800
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___S              11
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___M 0x00000400
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___S              10
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___M 0x00000200
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___S               9
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___M 0x00000100
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___S               8
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___S               0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER2___S                    0

#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH     (0x00A8C074)
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___POR 0x00000064
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___POR 0x0064
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___M 0x00010000
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___S              16
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___M 0x00013FFF   
#define   WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___S               0

#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL           (0x00A8C078)
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___M 0x20000000
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___S              29
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___M 0x1F000000
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___S              24
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___S              16
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___S               8
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___M    0x3FFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___S                  0

#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2              (0x00A8C07C)
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2___POR     0x00000000
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___POR 0x0
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___M 0x20000000
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___S              29
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___M 0x00FF0000
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___S              16
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___M 0x000000FF
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___S               0
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2___M       0x20FF00FF   
#define   WMAC0_RXPCU_R0_BCN_RSSI_CTL2___S                     0

#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE           (0x00A8C080)
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___POR  0x08000800
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___POR 0x800
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___POR 0x800
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___M 0x0FFF0000
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___S              16
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___M 0x00000FFF
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___M    0x0FFF0FFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___S                  0

#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE            (0x00A8C084)
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE___POR   0x00000580
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___POR 0x5
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___POR 0x80
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___M 0x00001000
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___S              12
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___M 0x00000800
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___S              11
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___M 0x00000700
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___S               8
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___S               0
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE___M     0x00001FFF   
#define   WMAC0_RXPCU_R0_FILTER_RSSI_AVE___S                   0

#define WMAC0_RXPCU_R0_BA_BAR_CONTROL             (0x00A8C088)
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL___POR    0x00000000
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___POR 0x0
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___M 0x00000400
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___S              10
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL___M      0x00000400   
#define   WMAC0_RXPCU_R0_BA_BAR_CONTROL___S                   10

#define WMAC0_RXPCU_R0_RTT_CTRL_IX0               (0x00A8C08C)
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0___POR      0x04002100
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___POR 0x04
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___POR 0x0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___POR 0x21
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___POR 0x0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___POR 0x0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___M 0xFF000000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___S              24
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___M 0x00010000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___S              16
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___S               8
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___M 0x00000002
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___S               1
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___M 0x00000001
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___S               0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0___M        0xFF01FF03   
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX0___S                      0

#define WMAC0_RXPCU_R0_RTT_CTRL_IX1               (0x00A8C090)
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1___POR      0x0B000100
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___POR 0x0B
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___POR 0x0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___POR 0x01
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___M 0xFF000000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___S              24
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___M 0x00010000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___S              16
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___S               8
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1___M        0xFF01FF00   
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX1___S                      8

#define WMAC0_RXPCU_R0_RTT_CTRL_IX2               (0x00A8C094)
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2___POR      0x00000000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___POR 0x0000
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___S               0
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2___M        0x0000FFFF   
#define   WMAC0_RXPCU_R0_RTT_CTRL_IX2___S                      0

#define WMAC0_RXPCU_R0_TXBF_CNTL                  (0x00A8C098)
#define   WMAC0_RXPCU_R0_TXBF_CNTL___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TXBF_CNTL___POR         0x00190002
#define   WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___POR 0x19
#define   WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___POR 0x1
#define   WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___M 0x00FF0000
#define   WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___S              16
#define   WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___M 0x0000FF00
#define   WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___S               8
#define   WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___M 0x0000000E
#define   WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___S               1
#define   WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___S               0
#define   WMAC0_RXPCU_R0_TXBF_CNTL___M           0x00FFFF0F   
#define   WMAC0_RXPCU_R0_TXBF_CNTL___S                         0

#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT    (0x00A8C09C)
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___POR 0x1F400FA0
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___POR 0x1F40
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___POR 0x0FA0
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___S              16
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___S               0

#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20     (0x00A8C0A0)
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___POR 0x00000077
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___POR 0x77
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___S              10
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___S               9
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___S               8
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___S               0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___M 0x000007FF   
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___S               0

#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40     (0x00A8C0A4)
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___POR 0x00000077
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___POR 0x77
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___S              10
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___S               9
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___S               8
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___S               0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___M 0x000007FF   
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___S               0

#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80     (0x00A8C0A8)
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___POR 0x00000077
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___POR 0x77
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___S              10
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___S               9
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___S               8
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___S               0
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___M 0x000007FF   
#define   WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___S               0

#define WMAC0_RXPCU_R0_PROXY_STA                  (0x00A8C0AC)
#define   WMAC0_RXPCU_R0_PROXY_STA___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PROXY_STA___POR         0x00000000
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___POR 0x0
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___M 0x00008000
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___S              15
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___M 0x00004000
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___S              14
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___M 0x00002000
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___S              13
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___M 0x00001000
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___S              12
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___M 0x00000800
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___S              11
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___M 0x00000400
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___S              10
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___M 0x00000200
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___S               9
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___M 0x00000100
#define   WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___S               8
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___M 0x00000080
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___S               7
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___M 0x00000040
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___S               6
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___M 0x00000020
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___S               5
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___M 0x00000010
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___S               4
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___M 0x00000008
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___S               3
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___M 0x00000004
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___S               2
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___M 0x00000002
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___S               1
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___M 0x00000001
#define   WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___S               0
#define   WMAC0_RXPCU_R0_PROXY_STA___M           0x0000FFFF   
#define   WMAC0_RXPCU_R0_PROXY_STA___S                         0

#define WMAC0_RXPCU_R0_RX_ANTENNA                 (0x00A8C0B0)
#define   WMAC0_RXPCU_R0_RX_ANTENNA___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ANTENNA___POR        0x00000000
#define   WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___M   0x00FFFFFF
#define   WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___S                 0
#define   WMAC0_RXPCU_R0_RX_ANTENNA___M          0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RX_ANTENNA___S                        0

#define WMAC0_RXPCU_R0_NAV_CFG                    (0x00A8C0B4)
#define   WMAC0_RXPCU_R0_NAV_CFG___RWC              QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NAV_CFG___POR           0x2803C13A
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___POR 0x0
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___POR 0x1
#define   WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___POR 0x0
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___POR 0x1
#define   WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___POR 0x0
#define   WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___POR 0x0
#define   WMAC0_RXPCU_R0_NAV_CFG__OFDM___POR     0x03C
#define   WMAC0_RXPCU_R0_NAV_CFG__CCK___POR      0x13A
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___M 0x40000000
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___S              30
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___M 0x20000000
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___S              29
#define   WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___M 0x10000000
#define   WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___S              28
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___M 0x08000000
#define   WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___S              27
#define   WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___M 0x04000000
#define   WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___S              26
#define   WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___M 0x02000000
#define   WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___S              25
#define   WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___S              24
#define   WMAC0_RXPCU_R0_NAV_CFG__OFDM___M       0x00FFF000
#define   WMAC0_RXPCU_R0_NAV_CFG__OFDM___S                    12
#define   WMAC0_RXPCU_R0_NAV_CFG__CCK___M        0x00000FFF
#define   WMAC0_RXPCU_R0_NAV_CFG__CCK___S                      0
#define   WMAC0_RXPCU_R0_NAV_CFG___M             0x7FFFFFFF   
#define   WMAC0_RXPCU_R0_NAV_CFG___S                           0

#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1         (0x00A8C0B8)
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___POR 0x0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___POR 0x0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___S              16
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___S               0
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___S                0

#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2         (0x00A8C0BC)
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___POR 0x00000000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___POR 0x0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___POR 0x0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___S              16
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___S               0
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___S                0

#define WMAC0_RXPCU_R0_SPATIAL_REUSE              (0x00A8C0C0)
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE___POR     0x42801380
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___POR 0x1
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___POR 0x1
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___POR 0x80
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___POR 0x1
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___POR 0x3
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___POR 0x80
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___M 0x80000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___S              31
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___S              30
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___M 0x20000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___S              29
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___M 0x10000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___S              28
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___M 0x08000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___S              27
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___M 0x04000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___S              26
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___M 0x02000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___S              25
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___M 0x01000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___S              24
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___M 0x00FF0000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___S              16
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___M 0x00008000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___S              15
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___M 0x00001000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___S              12
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___M 0x00000F00
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___S               8
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___M 0x000000FF
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE___M       0xFFFF9FFF   
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE___S                     0

#define WMAC0_RXPCU_R0_SPATIAL_REUSE2             (0x00A8C0C4)
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2___POR    0x004A8000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___POR 0x4A
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___POR 0x80
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___POR 0x00
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___M 0x80000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___S              31
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___S              30
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___M 0x20000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___S              29
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___M 0x03000000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___S              24
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___M 0x00FF0000
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___S              16
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___M 0x0000FF00
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___S               8
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___M 0x000000FF
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___S               0
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2___M      0xE3FFFFFF   
#define   WMAC0_RXPCU_R0_SPATIAL_REUSE2___S                    0

#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n(n) (0x00A8C0C8+0x4*(n))
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_nMAX 1    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_ELEM 2    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___S               0
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___S                0
#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0         (0x00A8C0C8)
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0__VALUE___S               0
#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1         (0x00A8C0CC)
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1__VALUE___S               0

#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n(n) (0x00A8C0D0+0x4*(n))
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_nMAX 1    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_ELEM 2    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___S               0
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___S               0
#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0     (0x00A8C0D0)
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0__VALUE___S               0
#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1     (0x00A8C0D4)
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1__VALUE___S               0

#define WMAC0_RXPCU_R0_SRP_LUT_0                  (0x00A8C0D8)
#define   WMAC0_RXPCU_R0_SRP_LUT_0___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_LUT_0___POR         0x00000000
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___M     0xFF000000
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___S                  24
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___M     0x00FF0000
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___S                  16
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___M     0x0000FF00
#define   WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___S                   8
#define   WMAC0_RXPCU_R0_SRP_LUT_0___M           0xFFFFFF00   
#define   WMAC0_RXPCU_R0_SRP_LUT_0___S                         8

#define WMAC0_RXPCU_R0_SRP_LUT_1                  (0x00A8C0DC)
#define   WMAC0_RXPCU_R0_SRP_LUT_1___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_LUT_1___POR         0x00000000
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___M     0xFF000000
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___S                  24
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___M     0x00FF0000
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___S                  16
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___M     0x0000FF00
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___S                   8
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___M     0x000000FF
#define   WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___S                   0
#define   WMAC0_RXPCU_R0_SRP_LUT_1___M           0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_LUT_1___S                         0

#define WMAC0_RXPCU_R0_SRP_LUT_2                  (0x00A8C0E0)
#define   WMAC0_RXPCU_R0_SRP_LUT_2___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_LUT_2___POR         0x00000000
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___POR  0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___POR  0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___POR   0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___M    0xFF000000
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___S                 24
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___M    0x00FF0000
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___S                 16
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___M     0x0000FF00
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___S                   8
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___M     0x000000FF
#define   WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___S                   0
#define   WMAC0_RXPCU_R0_SRP_LUT_2___M           0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_LUT_2___S                         0

#define WMAC0_RXPCU_R0_SRP_LUT_3                  (0x00A8C0E4)
#define   WMAC0_RXPCU_R0_SRP_LUT_3___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_LUT_3___POR         0x00000000
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___POR  0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___POR  0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___POR  0x00
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___M    0x00FF0000
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___S                 16
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___M    0x0000FF00
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___S                  8
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___M    0x000000FF
#define   WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___S                  0
#define   WMAC0_RXPCU_R0_SRP_LUT_3___M           0x00FFFFFF   
#define   WMAC0_RXPCU_R0_SRP_LUT_3___S                         0

#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT         (0x00A8C0E8)
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___POR 0x27D09010
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___POR 0x09F
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___M 0xFFC00000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___S              22
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___M 0x00100000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___S              20
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___M 0x00080000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___S              19
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___M 0x00040000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___S              18
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___M 0x00020000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___S              17
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___S              16
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___M 0x00008000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___S              15
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___M 0x00003F00
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___S               8
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___M 0x00000020
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___S               5
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___M 0x00000010
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___S               4
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___M 0x00000008
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___S               3
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___M  0xFFDFBF38   
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___S                3

#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2        (0x00A8C0EC)
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___POR 0x10101010
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___M 0x3F000000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___S              24
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___M 0x003F0000
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___S              16
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___M 0x00003F00
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___S               8
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___M 0x0000003F
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___S               0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___M 0x3F3F3F3F   
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___S               0

#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3        (0x00A8C0F0)
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___POR 0x00000010
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___POR 0x10
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___M 0x0000003F
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___S               0
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___M 0x0000003F   
#define   WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___S               0

#define WMAC0_RXPCU_R0_LAST_BEACON_TSF            (0x00A8C0F4)
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF___POR   0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___S               0
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF___S                   0

#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH       (0x00A8C0F8)
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___S               0
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___S               0

#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF           (0x00A8C0FC)
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF___POR  0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___S               0
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF___S                  0

#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH      (0x00A8C100)
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___S               0
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___S               0

#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1           (0x00A8C104)
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___M 0xFF000000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___S              24
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___S              16
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___S               8
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___M 0x00000080
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___S               7
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___M 0x00000040
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___S               6
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___M 0x00000020
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___S               5
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___M 0x00000008
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___S               3
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___S               2
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___M 0x00000002
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___S               1
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___S               0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___M    0xFFFFFFEF   
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___S                  0

#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2           (0x00A8C108)
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___M 0x00020000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___S              17
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___S              16
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___S               8
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___S               2
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___M    0x0003FF04   
#define   WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___S                  2

#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT           (0x00A8C10C)
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___POR  0x0FFC0000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___POR 0x3FF
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___M 0x70000000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___S              28
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___M 0x0FFC0000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___S              18
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___M 0x0003FC00
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___S              10
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___M 0x000003FF
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___M    0x7FFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___S                  0

#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1           (0x00A8C110)
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___M 0x03FF0000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___S              16
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___M 0x00000FFF
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___M    0x03FF0FFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___S                  0

#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2           (0x00A8C114)
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___M 0x000FFF00
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___S               8
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___M    0x000FFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___S                  0

#define WMAC0_RXPCU_R0_RFF_BCN_MISS               (0x00A8C118)
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___M  0x80000000
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___S               31
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___M 0x00003FFF
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS___M        0x80003FFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_MISS___S                      0

#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX           (0x00A8C11C)
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___M 0x03FF0000
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___S              16
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___M 0x00003FFF
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___M    0x03FF3FFF   
#define   WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___S                  0

#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM     (0x00A8C120)
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___M 0x00003FFF   
#define   WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___S               0

#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM         (0x00A8C124)
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___POR 0x00000000
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___S               0
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___M  0x00003FFF   
#define   WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___S                0

#define WMAC0_RXPCU_R0_RFF_BCN1_CRC               (0x00A8C128)
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN1_CRC___S                      0

#define WMAC0_RXPCU_R0_BCN2_CRC                   (0x00A8C12C)
#define   WMAC0_RXPCU_R0_BCN2_CRC___RWC             QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BCN2_CRC___POR          0x00000000
#define   WMAC0_RXPCU_R0_BCN2_CRC__VALUE___POR   0x00000000
#define   WMAC0_RXPCU_R0_BCN2_CRC__VALUE___M     0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BCN2_CRC__VALUE___S                   0
#define   WMAC0_RXPCU_R0_BCN2_CRC___M            0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BCN2_CRC___S                          0

#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0   (0x00A8C130)
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___S               0

#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32  (0x00A8C134)
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___S               0

#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0       (0x00A8C138)
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___S               0
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___S               0

#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32      (0x00A8C13C)
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___S               0

#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS            (0x00A8C140)
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___POR   0x00200008
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___POR 0x1
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___POR 0x1
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___M 0x00200000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___S              21
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___M 0x00100000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___S              20
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___M 0x00080000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___S              19
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___M 0x00040000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___S              18
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___M 0x00020000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___S              17
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___M 0x00010000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___S              16
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___M 0x00004000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___S              14
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___M 0x00002000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___S              13
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___M 0x00001000
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___S              12
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___M 0x00000F00
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___S               8
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___M 0x000000F0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___S               4
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___M 0x00000008
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___S               3
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___S               2
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___S               1
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___S               0
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___M     0x003F7FFF   
#define   WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___S                   0

#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0           (0x00A8C144)
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___POR  0x0C800000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___POR 0x0C8
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___M 0xFFF00000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___S              20
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___M 0x00080000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___S              19
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___M 0x00040000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___S              18
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___M 0x00020000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___S              17
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___S              16
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___M 0x00008000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___S              15
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___M 0x00004000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___S              14
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___M 0x00002000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___S              13
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___M 0x00001000
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___S              12
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___M 0x00000800
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___S              11
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___M 0x00000400
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___S              10
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___M 0x00000100
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___S               8
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___M 0x00000080
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___S               7
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___M 0x00000010
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___S               4
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___M 0x00000008
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___S               3
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___S               2
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___M 0x00000002
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___S               1
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___S               0
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___M    0xFFFFFD9F   
#define   WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___S                  0

#define WMAC0_RXPCU_R0_POWER_SAVE_1               (0x00A8C148)
#define   WMAC0_RXPCU_R0_POWER_SAVE_1___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_1___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___M 0x20000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___S              29
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___M 0x1FF00000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___S              20
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___M 0x00080000
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___S              19
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___M 0x0007FC00
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___S              10
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___S               9
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___M 0x000001FF
#define   WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_1___M        0x3FFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_1___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_2               (0x00A8C14C)
#define   WMAC0_RXPCU_R0_POWER_SAVE_2___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_2___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___POR 0x000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___M 0x20000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___S              29
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___M 0x1FF00000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___S              20
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___M 0x00080000
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___S              19
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___M 0x0007FC00
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___S              10
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___S               9
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___M 0x000001FF
#define   WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_2___M        0x3FFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_2___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_3               (0x00A8C150)
#define   WMAC0_RXPCU_R0_POWER_SAVE_3___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_3___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_3___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_3___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_4               (0x00A8C154)
#define   WMAC0_RXPCU_R0_POWER_SAVE_4___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_4___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_4___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_4___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_5               (0x00A8C158)
#define   WMAC0_RXPCU_R0_POWER_SAVE_5___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_5___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_5___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_5___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_6               (0x00A8C15C)
#define   WMAC0_RXPCU_R0_POWER_SAVE_6___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_6___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_6___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_6___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_7               (0x00A8C160)
#define   WMAC0_RXPCU_R0_POWER_SAVE_7___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_7___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_7___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_7___S                      0

#define WMAC0_RXPCU_R0_POWER_SAVE_8               (0x00A8C164)
#define   WMAC0_RXPCU_R0_POWER_SAVE_8___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_POWER_SAVE_8___POR      0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___POR 0x00000000
#define   WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___S               0
#define   WMAC0_RXPCU_R0_POWER_SAVE_8___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_POWER_SAVE_8___S                      0

#define WMAC0_RXPCU_R0_RFF_NAP_CTRL               (0x00A8C168)
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___M 0xFF000000
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___S              24
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___S              16
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___S               8
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___S               0
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL___M        0xFF01FFFF   
#define   WMAC0_RXPCU_R0_RFF_NAP_CTRL___S                      0

#define WMAC0_RXPCU_R0_RFF_EBT_CFG0               (0x00A8C16C)
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___M 0xC0000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___S              30
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___M 0x30000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___S              28
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___M 0x0C000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___S              26
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___M 0x03000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___S              24
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___M 0x00C00000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___S              22
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___M 0x003FF800
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___S              11
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___M 0x000007FF
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___S               0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG0___S                      0

#define WMAC0_RXPCU_R0_RFF_EBT_CFG1               (0x00A8C170)
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___M 0xFF000000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___S              24
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___S              16
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___S               8
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___M 0x00000010
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___S               4
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___S               2
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___S               0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1___M        0xFFFFFF15   
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG1___S                      0

#define WMAC0_RXPCU_R0_RFF_EBT_CFG2               (0x00A8C174)
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2___POR      0x00000080
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___POR 0x80
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___S               8
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___S               0
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2___M        0x0000FFFF   
#define   WMAC0_RXPCU_R0_RFF_EBT_CFG2___S                      0

#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG             (0x00A8C178)
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___POR    0x00000000
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___M 0x000FF000
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___S              12
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___M 0x00000F00
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___S               8
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___M 0x000000F0
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___S               4
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___M 0x0000000F
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___S               0
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___M      0x000FFFFF   
#define   WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___S                    0

#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT        (0x00A8C17C)
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___S               0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0           (0x00A8C180)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___M 0xC0000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___S              30
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0___M    0xC0FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST0___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1           (0x00A8C184)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST1___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2           (0x00A8C188)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST2___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3           (0x00A8C18C)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST3___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4           (0x00A8C190)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST4___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5           (0x00A8C194)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST5___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6           (0x00A8C198)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST6___S                  0

#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7           (0x00A8C19C)
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___S              16
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7___M    0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_CONGEST_EST7___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT                   (0x00A8C1A0)
#define   WMAC0_RXPCU_R0_RFF_TBTT___RWC             QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT___POR          0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___POR 0x00
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___M 0xFF000000
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___S              24
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___S              16
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___S               8
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___M 0x000000FF
#define   WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT___M            0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT___S                          0

#define WMAC0_RXPCU_R0_RFF_TBTT_CFG               (0x00A8C1A4)
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG___POR      0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___M 0x00000008
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___S               3
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___M 0x00000004
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___S               2
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___M 0x00000003
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG___M        0x0000000F   
#define   WMAC0_RXPCU_R0_RFF_TBTT_CFG___S                      0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0           (0x00A8C1A8)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1           (0x00A8C1AC)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2           (0x00A8C1B0)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3           (0x00A8C1B4)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4           (0x00A8C1B8)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5           (0x00A8C1BC)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6           (0x00A8C1C0)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___S                  0

#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7           (0x00A8C1C4)
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___S                  0

#define WMAC0_RXPCU_R0_EBT_DEBUG                  (0x00A8C1C8)
#define   WMAC0_RXPCU_R0_EBT_DEBUG___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_EBT_DEBUG___POR         0x00000000
#define   WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___POR 0x0
#define   WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___POR 0x0
#define   WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___POR 0x0
#define   WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___M 0x00000020
#define   WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___S               5
#define   WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___M 0x00000010
#define   WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___S               4
#define   WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___M 0x00000002
#define   WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___S               1
#define   WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___M 0x00000001
#define   WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___S               0
#define   WMAC0_RXPCU_R0_EBT_DEBUG___M           0x00000033   
#define   WMAC0_RXPCU_R0_EBT_DEBUG___S                         0

#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW      (0x00A8C1CC)
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___POR 0x00000000
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___S               0
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___S               0

#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH     (0x00A8C1D0)
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___POR 0x00000000
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___POR 0x00
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___S               0
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___M 0x000000FF   
#define   WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___S               0

#define WMAC0_RXPCU_R0_GSE_GST_SIZE               (0x00A8C1D4)
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE___POR      0x00000000
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___POR 0x00000
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___M   0x000FFFFF
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___S                 0
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE___M        0x000FFFFF   
#define   WMAC0_RXPCU_R0_GSE_GST_SIZE___S                      0

#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL            (0x00A8C1D8)
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___POR   0x00003806
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___POR 0x06
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___S              16
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S              13
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S              12
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S              11
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S              10
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___S               9
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___S               8
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___S               0
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___M     0xFFFF3FFF   
#define   WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___S                   0

#define WMAC0_RXPCU_R0_GSE_WATCHDOG               (0x00A8C1DC)
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG___POR      0x0000FFFF
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___S              16
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___S               0
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GSE_WATCHDOG___S                      0

#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE        (0x00A8C1E0)
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___S               9
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___S               8
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___M 0x00000080
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___S               7
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S               6
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___S               5
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___S               4
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___S               3
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___S               2
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___S               1
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___S               0
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___S               0

#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING     (0x00A8C1E4)
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___POR 0x00000000
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___POR 0x0
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___M 0x00000001
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___S               0
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___M 0x00000001   
#define   WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___S               0

#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL            (0x00A8C1E8)
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___POR   0x00000000
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___POR 0x0
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___M 0x00000003
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___S               0
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___M     0x00000003   
#define   WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___S                   0

#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1             (0x00A8C1EC)
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1___POR    0x00000000
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___S               0
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_1___S                    0

#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2             (0x00A8C1F0)
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2___POR    0x00000000
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___S               0
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_2___S                    0

#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3             (0x00A8C1F4)
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3___POR    0x00000000
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___M 0x0000001F
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___S               0
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3___M      0x0000001F   
#define   WMAC0_RXPCU_R0_ASE_HASH_KEY_3___S                    0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG           (0x00A8C1F8)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___POR  0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___S              16
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___M 0x00001000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___S              12
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___M 0x00000800
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___S              11
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___M 0x00000400
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___S              10
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___M 0x00000200
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___S               9
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___M 0x00000100
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___S               8
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___M 0x00000080
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___S               7
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___M 0x00000040
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___S               6
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___M 0x00000030
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___S               4
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___M 0x0000000F
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___M    0xFFFF1FFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___S                  0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2         (0x00A8C1FC)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___S                0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3         (0x00A8C200)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___S                0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00       (0x00A8C204)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32       (0x00A8C208)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64       (0x00A8C20C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96      (0x00A8C210)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128     (0x00A8C214)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160     (0x00A8C218)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192     (0x00A8C21C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224     (0x00A8C220)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00       (0x00A8C224)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32       (0x00A8C228)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64       (0x00A8C22C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96      (0x00A8C230)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128     (0x00A8C234)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160     (0x00A8C238)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192     (0x00A8C23C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224     (0x00A8C240)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00       (0x00A8C244)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32       (0x00A8C248)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64       (0x00A8C24C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96      (0x00A8C250)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128     (0x00A8C254)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160     (0x00A8C258)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192     (0x00A8C25C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224     (0x00A8C260)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00       (0x00A8C264)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32       (0x00A8C268)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64       (0x00A8C26C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96      (0x00A8C270)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128     (0x00A8C274)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160     (0x00A8C278)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192     (0x00A8C27C)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___S               0

#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224     (0x00A8C280)
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___S               0

#define WMAC0_RXPCU_R0_MISC_MODE                  (0x00A8C284)
#define   WMAC0_RXPCU_R0_MISC_MODE___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MISC_MODE___POR         0x00070000
#define   WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___POR 0x00
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___M 0x80000000
#define   WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___S              31
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___M 0x40000000
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___S              30
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___M 0x20000000
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___S              29
#define   WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___M 0x10000000
#define   WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___S              28
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___M 0x08000000
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___S              27
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___M 0x00100000
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___S              20
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___M 0x00080000
#define   WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___S              19
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___M 0x00040000
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___S              18
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___M 0x00020000
#define   WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___S              17
#define   WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___M 0x00010000
#define   WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___S              16
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___M 0x0000FF00
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___S               8
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___M 0x00000020
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___S               5
#define   WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___M 0x00000010
#define   WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___S               4
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___M 0x00000008
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___S               3
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___M 0x00000004
#define   WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___S               2
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___M 0x00000002
#define   WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___S               1
#define   WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___M 0x00000001
#define   WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___S               0
#define   WMAC0_RXPCU_R0_MISC_MODE___M           0xF81FFF3F   
#define   WMAC0_RXPCU_R0_MISC_MODE___S                         0

#define WMAC0_RXPCU_R0_MISC_MODE2                 (0x00A8C288)
#define   WMAC0_RXPCU_R0_MISC_MODE2___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MISC_MODE2___POR        0x00100000
#define   WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___POR 0x000
#define   WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___M 0x00800000
#define   WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___S              23
#define   WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___M 0x00400000
#define   WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___S              22
#define   WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___M 0x00100000
#define   WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___S              20
#define   WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___M 0x00002000
#define   WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___S              13
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___M 0x00001000
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___S              12
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___M 0x00000800
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___S              11
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___M 0x000007FF
#define   WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_MISC_MODE2___M          0x00D03FFF   
#define   WMAC0_RXPCU_R0_MISC_MODE2___S                        0

#define WMAC0_RXPCU_R0_MISC_MODE3                 (0x00A8C28C)
#define   WMAC0_RXPCU_R0_MISC_MODE3___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MISC_MODE3___POR        0x00901900
#define   WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___POR 0x1
#define   WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___POR 0x19
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___M 0x20000000
#define   WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___S              29
#define   WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___M 0x00800000
#define   WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___S              23
#define   WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___M 0x00200000
#define   WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___S              21
#define   WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___M 0x00100000
#define   WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___S              20
#define   WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___M 0x00007F00
#define   WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___S               8
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___M 0x00000080
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___S               7
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___M 0x00000040
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___S               6
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___M 0x00000020
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___S               5
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___M 0x00000010
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___S               4
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___M 0x00000008
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___S               3
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___M 0x00000004
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___S               2
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___M 0x00000002
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___S               1
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___M 0x00000001
#define   WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___S               0
#define   WMAC0_RXPCU_R0_MISC_MODE3___M          0x20B07FFF   
#define   WMAC0_RXPCU_R0_MISC_MODE3___S                        0

#define WMAC0_RXPCU_R0_RFF_MISC_MODE4             (0x00A8C290)
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4___POR    0x01001080
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___M 0xF0000000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___S              28
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___M 0x08000000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___S              27
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___M 0x04000000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___S              26
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___M 0x02000000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___S              25
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___M 0x01000000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___S              24
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___M 0x00400000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___S              22
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___M 0x00200000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___S              21
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___M 0x00100000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___S              20
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___M 0x00080000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___S              19
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___M 0x00040000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___S              18
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___M 0x00020000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___S              17
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___S              16
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___M 0x00008000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___S              15
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___M 0x00004000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___S              14
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___M 0x00002000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___S              13
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___M 0x00001000
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___S              12
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___M 0x00000800
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___S              11
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___M 0x00000400
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___S              10
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___M 0x00000200
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___S               9
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___M 0x00000100
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___S               8
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___M 0x00000080
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___S               7
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___M 0x00000040
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___S               6
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4___M      0xFF7FFFC0   
#define   WMAC0_RXPCU_R0_RFF_MISC_MODE4___S                    6

#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE            (0x00A8C294)
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___POR   0x00000000
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___POR 0x0
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___S               1
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___M     0x00000002   
#define   WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___S                   1

#define WMAC0_RXPCU_R0_WATCHDOG                   (0x00A8C298)
#define   WMAC0_RXPCU_R0_WATCHDOG___RWC             QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_WATCHDOG___POR          0x0000FFFF
#define   WMAC0_RXPCU_R0_WATCHDOG__STATUS___POR  0x0000
#define   WMAC0_RXPCU_R0_WATCHDOG__LIMIT___POR   0xFFFF
#define   WMAC0_RXPCU_R0_WATCHDOG__STATUS___M    0xFFFF0000
#define   WMAC0_RXPCU_R0_WATCHDOG__STATUS___S                 16
#define   WMAC0_RXPCU_R0_WATCHDOG__LIMIT___M     0x0000FFFF
#define   WMAC0_RXPCU_R0_WATCHDOG__LIMIT___S                   0
#define   WMAC0_RXPCU_R0_WATCHDOG___M            0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_WATCHDOG___S                          0

#define WMAC0_RXPCU_R0_FCS_FAIL_CNT               (0x00A8C29C)
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT___RWC         QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT___POR      0x00000000
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT___M        0x0000FFFF   
#define   WMAC0_RXPCU_R0_FCS_FAIL_CNT___S                      0

#define WMAC0_RXPCU_R0_RFF_BEACON_CNT             (0x00A8C2A0)
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT___POR    0x00000000
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT___M      0x0000FFFF   
#define   WMAC0_RXPCU_R0_RFF_BEACON_CNT___S                    0

#define WMAC0_RXPCU_R0_BEACON2_CNT                (0x00A8C2A4)
#define   WMAC0_RXPCU_R0_BEACON2_CNT___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_BEACON2_CNT___POR       0x00000000
#define   WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___M  0x0000FFFF
#define   WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___S                0
#define   WMAC0_RXPCU_R0_BEACON2_CNT___M         0x0000FFFF   
#define   WMAC0_RXPCU_R0_BEACON2_CNT___S                       0

#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT            (0x00A8C2A8)
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT___POR   0x00000000
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT___M     0x00FFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_OFDM_CNT___S                   0

#define WMAC0_RXPCU_R0_FILTER_CCK_CNT             (0x00A8C2AC)
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT___POR    0x00000000
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT___M      0x00FFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_CCK_CNT___S                    0

#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL             (0x00A8C2B0)
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL___POR    0x00005500
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___POR 0x1
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___POR 0x1
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___POR 0x1
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___POR 0x1
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___M 0x00010000
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___S              16
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___M 0x0000C000
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___S              14
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___M 0x00003000
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___S              12
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___M 0x00000C00
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___S              10
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___M 0x00000300
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___S               8
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___S               3
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___S               2
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___S               1
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___S               0
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL___M      0x0001FF0F   
#define   WMAC0_RXPCU_R0_SIFS_RESP_CTRL___S                    0

#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS           (0x00A8C2B4)
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS___RWC     QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS___POR  0x00000000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___POR 0x0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___POR 0x0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___S              16
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___S               0
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS___S                  0

#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2          (0x00A8C2B8)
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___RWC    QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___POR 0x00000000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___POR 0x0
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___POR 0x0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___M 0x00070000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___S              16
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___S               0
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___M   0x0007FFFF   
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___S                 0

#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3          (0x00A8C2BC)
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___RWC    QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___POR 0x00000000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___POR 0x0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___POR 0x0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___S              16
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___S               0
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___S                 0

#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n(n) (0x00A8C2C0+0x4*(n))
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_nMIN 0    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_nMAX 1    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_ELEM 2    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___POR 0x00000000
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___S               0
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___S               0
#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0        (0x00A8C2C0)
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0__TIMESTAMP___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0__TIMESTAMP___S               0
#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1        (0x00A8C2C4)
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1__TIMESTAMP___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1__TIMESTAMP___S               0

#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT  (0x00A8C2C8)
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___S               0

#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT         (0x00A8C2CC)
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___M  0x000000FF   
#define   WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___S                0

#define WMAC0_RXPCU_R0_PHY_ERROR_MASK             (0x00A8C2D0)
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK___POR    0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK___S                    0

#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT        (0x00A8C2D4)
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK        (0x00A8C2D8)
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___S               0

#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT   (0x00A8C2DC)
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS             (0x00A8C2E0)
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS___POR    0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___M 0x00000001
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS___M      0x00000001   
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS___S                    0

#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK        (0x00A8C2E4)
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___S               0

#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT   (0x00A8C2E8)
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1              (0x00A8C2EC)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1___POR     0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1___M       0x00FFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1___S                     0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK         (0x00A8C2F0)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___S                0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT    (0x00A8C2F4)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2              (0x00A8C2F8)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2___POR     0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2___M       0x00FFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2___S                     0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK         (0x00A8C2FC)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___S                0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT    (0x00A8C300)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3              (0x00A8C304)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3___POR     0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___POR 0x000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3___M       0x00FFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3___S                     0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK         (0x00A8C308)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___S                0

#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT    (0x00A8C30C)
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_SPARE_REG1                 (0x00A8C310)
#define   WMAC0_RXPCU_R0_SPARE_REG1___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SPARE_REG1___POR        0x00000000
#define   WMAC0_RXPCU_R0_SPARE_REG1__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_SPARE_REG1__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SPARE_REG1__VALUE___S                 0
#define   WMAC0_RXPCU_R0_SPARE_REG1___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SPARE_REG1___S                        0

#define WMAC0_RXPCU_R0_SPARE_REG2                 (0x00A8C314)
#define   WMAC0_RXPCU_R0_SPARE_REG2___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SPARE_REG2___POR        0x00000000
#define   WMAC0_RXPCU_R0_SPARE_REG2__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_SPARE_REG2__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SPARE_REG2__VALUE___S                 0
#define   WMAC0_RXPCU_R0_SPARE_REG2___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SPARE_REG2___S                        0

#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR        (0x00A8C318)
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___S               0

#define WMAC0_RXPCU_R0_PREFETCH_STATUS            (0x00A8C31C)
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS___POR   0x00000000
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___POR 0x0
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___POR 0x0000000
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___POR 0x00
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___M 0x80000000
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___S              31
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___M 0x7FFFFFC0
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___S               6
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___M 0x0000003F
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___S               0
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PREFETCH_STATUS___S                   0

#define WMAC0_RXPCU_R0_FCS_DEBUG                  (0x00A8C320)
#define   WMAC0_RXPCU_R0_FCS_DEBUG___RWC            QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_FCS_DEBUG___POR         0x00000000
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___M 0xFF000000
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___S              24
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___M 0x00FF0000
#define   WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___S              16
#define   WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___M  0x0000FFFF
#define   WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___S                0
#define   WMAC0_RXPCU_R0_FCS_DEBUG___M           0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_FCS_DEBUG___S                         0

#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG            (0x00A8C324)
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___RWC      QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___POR   0x00000000
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___POR 0x00
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___M 0xFF000000
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___S              24
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___M 0x00FF0000
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___S              16
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___S               8
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___S               0
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___S                   0

#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG             (0x00A8C328)
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___RWC       QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___POR    0x00000000
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___S              16
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___S               0
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___S                    0

#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG              (0x00A8C32C)
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG___RWC        QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG___POR     0x00000000
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___S              16
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___S               0
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_DUR_DEBUG___S                     0

#define WMAC0_RXPCU_R0_SR_DUR_DEBUG               (0x00A8C330)
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG___RWC         QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG___POR      0x00000000
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___S              16
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___S               0
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SR_DUR_DEBUG___S                      0

#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG              (0x00A8C334)
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG___RWC        QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG___POR     0x00000000
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___M 0xFF000000
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___S              24
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___M 0x00FF0000
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___S              16
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___S               8
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___S               0
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG___M       0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NAV_UPD_DEBUG___S                     0

#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG             (0x00A8C338)
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG___RWC       QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG___POR    0x00000000
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___M 0xFF000000
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___S              24
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___M 0x00FF0000
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___S              16
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___S               8
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___M 0x000000FF
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___S               0
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SR_ABORT_DEBUG___S                    0

#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG           (0x00A8C33C)
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___RWC     QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___POR  0x00000000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___M 0x80000000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___S              31
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___M 0x7FFF0000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___S              16
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___M 0x00008000
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___S              15
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___M 0x00007FFF
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___S               0
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___S                  0

#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG            (0x00A8C340)
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG___RWC      QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG___POR   0x00000000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___M 0x80000000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___S              31
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___M 0x7FFF0000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___S              16
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___M 0x00008000
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___S              15
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___M 0x00007FFF
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___S               0
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_LATEST_SR_DEBUG___S                   0

#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG           (0x00A8C344)
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___RWC     QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___POR  0x00000000
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___POR 0x0
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___POR 0x0000
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___M 0x00020000
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___S              17
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___M 0x00010000
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___S              16
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___S               0
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___M    0x0003FFFF   
#define   WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___S                  0

#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG             (0x00A8C348)
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___RWC       QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___POR    0x00000000
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___S              16
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___S               0
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___S                    0

#define WMAC0_RXPCU_R0_NAP_DEBUG                  (0x00A8C34C)
#define   WMAC0_RXPCU_R0_NAP_DEBUG___RWC            QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_NAP_DEBUG___POR         0x00000000
#define   WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___POR 0x0000
#define   WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___S              16
#define   WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___M  0x0000FFFF
#define   WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___S                0
#define   WMAC0_RXPCU_R0_NAP_DEBUG___M           0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NAP_DEBUG___S                         0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA         (0x00A8C350)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___M  0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___S                0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC   (0x00A8C354)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___M 0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL    (0x00A8C358)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___M 0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL         (0x00A8C35C)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___M  0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___S                0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT         (0x00A8C360)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___M  0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___S                0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN         (0x00A8C364)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___M 0x00003FFF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___M  0x00003FFF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___S                0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT (0x00A8C368)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT (0x00A8C36C)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT (0x00A8C370)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___M 0x0000FF00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___S               8
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___M 0x0000FF00   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___S               8

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT (0x00A8C374)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT (0x00A8C378)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___S               0

#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT (0x00A8C37C)
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___S               0

#define WMAC0_RXPCU_R0_CLKGATE_CTRL               (0x00A8C380)
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL___POR      0x00000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___M 0x80000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___S              31
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___S              30
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___M 0x20000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___S              29
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___M 0x10000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___S              28
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___M 0x08000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___S              27
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___M 0x04000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___S              26
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___M 0x02000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___S              25
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___M 0x01000000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___S              24
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___M 0x00800000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___S              23
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___M 0x00400000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___S              22
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___M 0x00200000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___S              21
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___M 0x00100000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___S              20
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___M 0x00080000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___S              19
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___M 0x00040000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___S              18
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___M 0x00020000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___S              17
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___M 0x00010000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___S              16
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___M 0x00008000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___S              15
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___M 0x00004000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___S              14
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___M 0x00002000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___S              13
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___M 0x00001000
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___S              12
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___M 0x00000800
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___S              11
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___M 0x00000400
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___S              10
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___M 0x00000200
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___S               9
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___M 0x00000100
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___S               8
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___M 0x00000080
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___S               7
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___M 0x00000040
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___S               6
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___M 0x00000020
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___S               5
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___M 0x00000010
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___S               4
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___M 0x00000008
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___S               3
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___M 0x00000004
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___S               2
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___M 0x00000002
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___S               1
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___M 0x00000001
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___S               0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL___S                      0

#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK (0x00A8C384)
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___S               0

#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT (0x00A8C388)
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___S               0
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___S               0

#define WMAC0_RXPCU_R0_COEX_CTRL                  (0x00A8C38C)
#define   WMAC0_RXPCU_R0_COEX_CTRL___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_COEX_CTRL___POR         0x00000001
#define   WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___POR 0x0
#define   WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___POR 0x0
#define   WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___POR 0x1
#define   WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___M 0x00000004
#define   WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___S               2
#define   WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___M 0x00000002
#define   WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___S               1
#define   WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___M  0x00000001
#define   WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___S                0
#define   WMAC0_RXPCU_R0_COEX_CTRL___M           0x00000007   
#define   WMAC0_RXPCU_R0_COEX_CTRL___S                         0

#define WMAC0_RXPCU_R0_EIFS_CTRL                  (0x00A8C390)
#define   WMAC0_RXPCU_R0_EIFS_CTRL___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_EIFS_CTRL___POR         0x00000000
#define   WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___POR 0x0
#define   WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___M 0x000000F0
#define   WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___S               4
#define   WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___M 0x0000000F
#define   WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___S               0
#define   WMAC0_RXPCU_R0_EIFS_CTRL___M           0x000000FF   
#define   WMAC0_RXPCU_R0_EIFS_CTRL___S                         0

#define WMAC0_RXPCU_R0_CBF_CTRL                   (0x00A8C394)
#define   WMAC0_RXPCU_R0_CBF_CTRL___RWC             QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_CBF_CTRL___POR          0x00000000
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___POR 0x0
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___M  0x00000400
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___S               10
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___M 0x00000380
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___S               7
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___M 0x00000040
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___S               6
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___M  0x00000020
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___S                5
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___M 0x0000001C
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___S               2
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___M 0x00000002
#define   WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___S               1
#define   WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___M 0x00000001
#define   WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___S               0
#define   WMAC0_RXPCU_R0_CBF_CTRL___M            0x000007FF   
#define   WMAC0_RXPCU_R0_CBF_CTRL___S                          0

#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL           (0x00A8C398)
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___POR  0x00000000
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___POR 0x0
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___M 0x00000001
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___S               0
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___M    0x00000001   
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___S                  0

#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32      (0x00A8C39C)
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___S               0

#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16      (0x00A8C3A0)
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___S               0

#define WMAC0_RXPCU_R0_GP_CTRL                    (0x00A8C3A4)
#define   WMAC0_RXPCU_R0_GP_CTRL___RWC              QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_CTRL___POR           0x00000000
#define   WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___M 0x00FFFF00
#define   WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___S               8
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___M  0x00000040
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___S                6
#define   WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___M 0x00000020
#define   WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___S               5
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___M 0x00000010
#define   WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___S               4
#define   WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___M 0x00000008
#define   WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___S               3
#define   WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___M 0x00000004
#define   WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___S               2
#define   WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___M 0x00000002
#define   WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___S               1
#define   WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___M 0x00000001
#define   WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___S               0
#define   WMAC0_RXPCU_R0_GP_CTRL___M             0x00FFFF7F   
#define   WMAC0_RXPCU_R0_GP_CTRL___S                           0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32        (0x00A8C3A8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16        (0x00A8C3AC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32        (0x00A8C3B0)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16        (0x00A8C3B4)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32        (0x00A8C3B8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16        (0x00A8C3BC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32        (0x00A8C3C0)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16        (0x00A8C3C4)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32        (0x00A8C3C8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16        (0x00A8C3CC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32        (0x00A8C3D0)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16        (0x00A8C3D4)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32        (0x00A8C3D8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16        (0x00A8C3DC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32        (0x00A8C3E0)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16        (0x00A8C3E4)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32        (0x00A8C3E8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16        (0x00A8C3EC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32        (0x00A8C3F0)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16        (0x00A8C3F4)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32       (0x00A8C3F8)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16       (0x00A8C3FC)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32       (0x00A8C400)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16       (0x00A8C404)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32       (0x00A8C408)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16       (0x00A8C40C)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32       (0x00A8C410)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16       (0x00A8C414)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32       (0x00A8C418)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16       (0x00A8C41C)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32       (0x00A8C420)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___S               0

#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16       (0x00A8C424)
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___S               0
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___S               0

#define WMAC0_RXPCU_R0_PFU_CTRL                   (0x00A8C428)
#define   WMAC0_RXPCU_R0_PFU_CTRL___RWC             QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PFU_CTRL___POR          0x01000210
#define   WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___POR 0x0100
#define   WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___POR 0x0
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___POR 0x0
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___POR 0x0
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___POR 0x0
#define   WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___POR  0x1
#define   WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___POR 0x0
#define   WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___POR 0x10
#define   WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___S              16
#define   WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___M 0x00008000
#define   WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___S              15
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___M 0x00006000
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___S              13
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___M 0x00001000
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___S              12
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___M 0x00000800
#define   WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___S              11
#define   WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___M    0x00000600
#define   WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___S                  9
#define   WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___M 0x00000100
#define   WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___S               8
#define   WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___M 0x000000FF
#define   WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___S               0
#define   WMAC0_RXPCU_R0_PFU_CTRL___M            0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PFU_CTRL___S                          0

#define WMAC0_RXPCU_R0_RX_THRESHOLD               (0x00A8C42C)
#define   WMAC0_RXPCU_R0_RX_THRESHOLD___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_THRESHOLD___POR      0x00000000
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___POR 0x00
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___POR 0x00
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___S              24
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___S              16
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___S               8
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___M 0x000000FF
#define   WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_RX_THRESHOLD___M        0x01FF01FF   
#define   WMAC0_RXPCU_R0_RX_THRESHOLD___S                      0

#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL             (0x00A8C430)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___POR    0x00000000
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___POR 0x000
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___M 0x0000FFF0
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___S               4
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___M 0x0000000E
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___S               1
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___S               0
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___M      0x0000FFFF   
#define   WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___S                    0

#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n(n) (0x00A8C434+0x4*(n))
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_nMIN 0    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_nMAX 31   
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_ELEM 32   
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___POR 0x00000000
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___S               0
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0        (0x00A8C434)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1        (0x00A8C438)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2        (0x00A8C43C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3        (0x00A8C440)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4        (0x00A8C444)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5        (0x00A8C448)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6        (0x00A8C44C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7        (0x00A8C450)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8        (0x00A8C454)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9        (0x00A8C458)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9___RWC  QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10       (0x00A8C45C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11       (0x00A8C460)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12       (0x00A8C464)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13       (0x00A8C468)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14       (0x00A8C46C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15       (0x00A8C470)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16       (0x00A8C474)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17       (0x00A8C478)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18       (0x00A8C47C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19       (0x00A8C480)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20       (0x00A8C484)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21       (0x00A8C488)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22       (0x00A8C48C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23       (0x00A8C490)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24       (0x00A8C494)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25       (0x00A8C498)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26       (0x00A8C49C)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27       (0x00A8C4A0)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28       (0x00A8C4A4)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29       (0x00A8C4A8)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30       (0x00A8C4AC)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30__MEM_RDDATA___S               0
#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31       (0x00A8C4B0)
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31__MEM_RDDATA___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31__MEM_RDDATA___S               0

#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL              (0x00A8C4B4)
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL___POR     0x00000000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___M 0x0F000000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___S              24
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___M 0x00400000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___S              22
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___M 0x00200000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___S              21
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___M 0x00100000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___S              20
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___M 0x00080000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___S              19
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___M 0x00040000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___S              18
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___M 0x00020000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___S              17
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___M 0x00010000
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___S              16
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___S               0
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL___M       0x0F7FFFFF   
#define   WMAC0_RXPCU_R0_RX_FLUSH_CTRL___S                     0

#define WMAC0_RXPCU_R0_RX_INT_CTRL                (0x00A8C4B8)
#define   WMAC0_RXPCU_R0_RX_INT_CTRL___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_INT_CTRL___POR       0x00000000
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___POR 0x00
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___M 0x00000080
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___S               7
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___S               6
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___M 0x0000003F
#define   WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___S               0
#define   WMAC0_RXPCU_R0_RX_INT_CTRL___M         0x000000FF   
#define   WMAC0_RXPCU_R0_RX_INT_CTRL___S                       0

#define WMAC0_RXPCU_R0_PPDU_ID                    (0x00A8C4BC)
#define   WMAC0_RXPCU_R0_PPDU_ID___RWC              QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_PPDU_ID___POR           0x00000000
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___POR  0x0
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___POR  0x0
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___M    0x00000200
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___S                  9
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___M    0x00000100
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___S                  8
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___M 0x000000F0
#define   WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___S               4
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___M 0x0000000F
#define   WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___S               0
#define   WMAC0_RXPCU_R0_PPDU_ID___M             0x000003FF   
#define   WMAC0_RXPCU_R0_PPDU_ID___S                           0

#define WMAC0_RXPCU_R0_LSIG_DELAY                 (0x00A8C4C0)
#define   WMAC0_RXPCU_R0_LSIG_DELAY___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_LSIG_DELAY___POR        0x00000000
#define   WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___M   0x0000FFFF
#define   WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___S                 0
#define   WMAC0_RXPCU_R0_LSIG_DELAY___M          0x0000FFFF   
#define   WMAC0_RXPCU_R0_LSIG_DELAY___S                        0

#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE      (0x00A8C4C4)
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___POR 0x0
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___POR 0x0
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___POR 0x0
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___M 0x000001E0
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___S               5
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___M 0x0000001C
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___S               2
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___M 0x00000003
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___S               0
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___M 0x000001FF   
#define   WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___S               0

#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B          (0x00A8C4C8)
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___RWC    QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___S               0
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___S                 0

#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n(n) (0x00A8C4CC+0x4*(n))
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_nMIN 0    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_nMAX 3    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_ELEM 4    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___S               0
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0  (0x00A8C4CC)
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1  (0x00A8C4D0)
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2  (0x00A8C4D4)
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3  (0x00A8C4D8)
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3__VALUE___S               0

#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n(n) (0x00A8C4DC+0x4*(n))
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_nMIN 0    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_nMAX 7    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_ELEM 8    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___S               0
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0     (0x00A8C4DC)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1     (0x00A8C4E0)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2     (0x00A8C4E4)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3     (0x00A8C4E8)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4     (0x00A8C4EC)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5     (0x00A8C4F0)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6     (0x00A8C4F4)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6__VALUE___S               0
#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7     (0x00A8C4F8)
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7__VALUE___S               0

#define WMAC0_RXPCU_R0_MPDU_HDR_n(n)     (0x00A8C4FC+0x4*(n))
#define   WMAC0_RXPCU_R0_MPDU_HDR_n_nMIN 0    
#define   WMAC0_RXPCU_R0_MPDU_HDR_n_nMAX 15   
#define   WMAC0_RXPCU_R0_MPDU_HDR_n_ELEM 16   
#define   WMAC0_RXPCU_R0_MPDU_HDR_n___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_n___POR        0x00000000
#define   WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___S                 0
#define   WMAC0_RXPCU_R0_MPDU_HDR_n___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_MPDU_HDR_n___S                        0
#define WMAC0_RXPCU_R0_MPDU_HDR_0                 (0x00A8C4FC)
#define   WMAC0_RXPCU_R0_MPDU_HDR_0___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_0__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_0__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_1                 (0x00A8C500)
#define   WMAC0_RXPCU_R0_MPDU_HDR_1___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_1__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_1__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_2                 (0x00A8C504)
#define   WMAC0_RXPCU_R0_MPDU_HDR_2___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_2__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_2__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_3                 (0x00A8C508)
#define   WMAC0_RXPCU_R0_MPDU_HDR_3___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_3__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_3__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_4                 (0x00A8C50C)
#define   WMAC0_RXPCU_R0_MPDU_HDR_4___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_4__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_4__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_5                 (0x00A8C510)
#define   WMAC0_RXPCU_R0_MPDU_HDR_5___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_5__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_5__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_6                 (0x00A8C514)
#define   WMAC0_RXPCU_R0_MPDU_HDR_6___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_6__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_6__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_7                 (0x00A8C518)
#define   WMAC0_RXPCU_R0_MPDU_HDR_7___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_7__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_7__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_8                 (0x00A8C51C)
#define   WMAC0_RXPCU_R0_MPDU_HDR_8___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_8__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_8__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_9                 (0x00A8C520)
#define   WMAC0_RXPCU_R0_MPDU_HDR_9___RWC           QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_9__VALUE___M   0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_9__VALUE___S                 0
#define WMAC0_RXPCU_R0_MPDU_HDR_10                (0x00A8C524)
#define   WMAC0_RXPCU_R0_MPDU_HDR_10___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_10__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_10__VALUE___S                0
#define WMAC0_RXPCU_R0_MPDU_HDR_11                (0x00A8C528)
#define   WMAC0_RXPCU_R0_MPDU_HDR_11___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_11__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_11__VALUE___S                0
#define WMAC0_RXPCU_R0_MPDU_HDR_12                (0x00A8C52C)
#define   WMAC0_RXPCU_R0_MPDU_HDR_12___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_12__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_12__VALUE___S                0
#define WMAC0_RXPCU_R0_MPDU_HDR_13                (0x00A8C530)
#define   WMAC0_RXPCU_R0_MPDU_HDR_13___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_13__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_13__VALUE___S                0
#define WMAC0_RXPCU_R0_MPDU_HDR_14                (0x00A8C534)
#define   WMAC0_RXPCU_R0_MPDU_HDR_14___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_14__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_14__VALUE___S                0
#define WMAC0_RXPCU_R0_MPDU_HDR_15                (0x00A8C538)
#define   WMAC0_RXPCU_R0_MPDU_HDR_15___RWC          QCSR_REG_RO    
#define   WMAC0_RXPCU_R0_MPDU_HDR_15__VALUE___M  0xFFFFFFFF
#define   WMAC0_RXPCU_R0_MPDU_HDR_15__VALUE___S                0

#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL         (0x00A8C53C)
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___POR 0x00000000
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___M 0x00010000
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___S              16
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___S               9
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___M 0x00000100
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___S               8
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___M 0x00000080
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___S               7
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___S               6
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___M 0x00000020
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___S               5
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___M 0x00000010
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___S               4
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___S               3
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___S               2
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___S               1
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___S               0
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___M  0x000103FF   
#define   WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___S                0

#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS      (0x00A8C540)
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___POR 0x0000
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___S              16
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___M 0x0000F000
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___S              12
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___M 0x00000080
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___S               7
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___M 0x00000040
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___S               6
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___M 0x00000020
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___S               5
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___M 0x00000010
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___S               4
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___M 0x00000008
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___S               3
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___M 0x00000004
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___S               2
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___M 0x00000002
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___S               1
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___M 0x00000001
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___S               0
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___M 0xFFFFF0FF   
#define   WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___S               0

#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS      (0x00A8C544)
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___POR 0x0
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___POR 0x0
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___M 0x0000F000
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___S              12
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___M 0x00000002
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___S               1
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___M 0x00000001
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___S               0
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___M 0x0000F003   
#define   WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___S               0

#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG       (0x00A8C548)
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___POR 0x002041CC
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___POR 0x08
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___POR 0x04
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___POR 0x07
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___POR 0x0C
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___M 0x00FC0000
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___S              18
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___M 0x0003F000
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___S              12
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___M 0x00000FC0
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___S               6
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___M 0x0000003F
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___S               0
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___S               0

#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0 (0x00A8C54C)
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___POR 0x00000000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___S              16
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___S               0
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___S               0

#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1 (0x00A8C550)
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___S              16
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___S               0
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___S               0

#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0 (0x00A8C554)
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___POR 0x00000000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___S              16
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___S               0
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___S               0

#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1 (0x00A8C558)
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___S              16
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___S               0
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___S               0

#define WMAC0_RXPCU_R0_BRU_CTRL                   (0x00A8C55C)
#define   WMAC0_RXPCU_R0_BRU_CTRL___RWC             QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BRU_CTRL___POR          0x00000000
#define   WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___POR 0x0
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___POR 0x0
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___POR 0x0
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___POR 0x0
#define   WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___M 0x00000010
#define   WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___S               4
#define   WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___M 0x00000008
#define   WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___S               3
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___M 0x00000004
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___S               2
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___M 0x00000002
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___S               1
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___M 0x00000001
#define   WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___S               0
#define   WMAC0_RXPCU_R0_BRU_CTRL___M            0x0000001F   
#define   WMAC0_RXPCU_R0_BRU_CTRL___S                          0

#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL          (0x00A8C560)
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___POR 0x0003FFFF
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___POR 0x1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___M 0x00020000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___S              17
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___M 0x00010000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___S              16
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___M 0x00008000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___S              15
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___M 0x00004000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___S              14
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___M 0x00002000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___S              13
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___M 0x00001000
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___S              12
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___M 0x00000800
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___S              11
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___M 0x00000400
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___S              10
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___M 0x00000200
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___S               9
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___M 0x00000100
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___S               8
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___M 0x00000080
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___S               7
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___M 0x00000040
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___S               6
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___M 0x00000020
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___S               5
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___M 0x00000010
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___S               4
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___M 0x00000008
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___S               3
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___M 0x00000004
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___S               2
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___M 0x00000002
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___S               1
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___M 0x00000001
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___S               0
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___M   0x0003FFFF   
#define   WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___S                 0

#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL            (0x00A8C564)
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL___POR   0x003FC07F
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___POR 0x0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___M 0x00200000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___S              21
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___M 0x00100000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___S              20
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___M 0x00080000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___S              19
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___M 0x00040000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___S              18
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___M 0x00020000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___S              17
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___M 0x00010000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___S              16
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___M 0x00008000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___S              15
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___M 0x00004000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___S              14
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___M 0x00002000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___S              13
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___M 0x00001000
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___S              12
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___M 0x00000800
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___S              11
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___M 0x00000400
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___S              10
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___M 0x00000200
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___S               9
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___M 0x00000100
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___S               8
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___M 0x00000080
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___S               7
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___M 0x00000040
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___S               6
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___M 0x00000020
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___S               5
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___M 0x00000010
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___S               4
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___M 0x00000008
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___S               3
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___M 0x00000004
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___S               2
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___M 0x00000002
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___S               1
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___M 0x00000001
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___S               0
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL___M     0x003FFFFF   
#define   WMAC0_RXPCU_R0_ACK_REPORT_CTRL___S                   0

#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0  (0x00A8C568)
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___POR 0x00000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___M 0x80000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___S              31
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___M 0x40000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___S              30
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___M 0x20000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___S              29
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___M 0x10000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___S              28
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___M 0x08000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___S              27
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___M 0x04000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___S              26
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___M 0x02000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___S              25
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___M 0x01000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___S              24
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___M 0x00800000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___S              23
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___M 0x00400000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___S              22
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___M 0x00200000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___S              21
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___M 0x00100000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___S              20
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___M 0x00080000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___S              19
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___M 0x00040000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___S              18
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___M 0x00020000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___S              17
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___M 0x00010000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___S              16
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___M 0x00008000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___S              15
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___M 0x00004000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___S              14
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___M 0x00002000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___S              13
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___M 0x00001000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___S              12
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___M 0x00000800
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___S              11
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___M 0x00000400
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___S              10
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___M 0x00000200
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___S               9
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___M 0x00000100
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___S               8
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___M 0x00000080
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___S               7
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___M 0x00000040
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___S               6
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___M 0x00000020
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___S               5
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___M 0x00000010
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___S               4
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___M 0x00000008
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___S               3
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___M 0x00000004
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___S               2
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___M 0x00000002
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___S               1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___M 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___S               0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___S               0

#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1  (0x00A8C56C)
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___POR 0x0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___M 0x80000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___S              31
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___M 0x40000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___S              30
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___M 0x20000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___S              29
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___M 0x10000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___S              28
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___M 0x08000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___S              27
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___M 0x04000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___S              26
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___M 0x02000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___S              25
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___M 0x01000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___S              24
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___M 0x00800000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___S              23
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___M 0x00400000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___S              22
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___M 0x00200000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___S              21
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___M 0x00100000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___S              20
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___M 0x00080000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___S              19
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___M 0x00040000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___S              18
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___M 0x00020000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___S              17
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___M 0x00010000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___S              16
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___M 0x00008000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___S              15
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___M 0x00004000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___S              14
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___M 0x00002000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___S              13
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___M 0x00001000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___S              12
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___M 0x00000800
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___S              11
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___M 0x00000400
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___S              10
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___M 0x00000200
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___S               9
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___M 0x00000100
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___S               8
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___M 0x00000080
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___S               7
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___M 0x00000040
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___S               6
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___M 0x00000020
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___S               5
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___M 0x00000010
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___S               4
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___M 0x00000008
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___S               3
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___M 0x00000004
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___S               2
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___M 0x00000002
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___S               1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___M 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___S               0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___S               0

#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0   (0x00A8C570)
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___M 0x80000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___S              31
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___M 0x40000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___S              30
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___M 0x20000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___S              29
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___M 0x10000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___S              28
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___M 0x08000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___S              27
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___M 0x04000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___S              26
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___M 0x02000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___S              25
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___M 0x01000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___S              24
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___M 0x00800000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___S              23
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___M 0x00400000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___S              22
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___M 0x00200000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___S              21
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___M 0x00100000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___S              20
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___M 0x00080000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___S              19
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___M 0x00040000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___S              18
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___M 0x00020000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___S              17
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___M 0x00010000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___S              16
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___M 0x00008000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___S              15
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___M 0x00004000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___S              14
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___M 0x00002000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___S              13
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___M 0x00001000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___S              12
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___M 0x00000800
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___S              11
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___M 0x00000400
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___S              10
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___M 0x00000200
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___S               9
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___M 0x00000100
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___S               8
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___M 0x00000080
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___S               7
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___M 0x00000040
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___S               6
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___M 0x00000020
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___S               5
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___M 0x00000010
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___S               4
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___M 0x00000008
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___S               3
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___M 0x00000004
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___S               2
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___M 0x00000002
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___S               1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___M 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___S               0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___S               0

#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1   (0x00A8C574)
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___M 0x80000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___S              31
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___M 0x40000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___S              30
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___M 0x20000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___S              29
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___M 0x10000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___S              28
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___M 0x08000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___S              27
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___M 0x04000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___S              26
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___M 0x02000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___S              25
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___M 0x01000000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___S              24
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___M 0x00800000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___S              23
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___M 0x00400000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___S              22
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___M 0x00200000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___S              21
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___M 0x00100000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___S              20
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___M 0x00080000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___S              19
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___M 0x00040000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___S              18
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___M 0x00020000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___S              17
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___M 0x00010000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___S              16
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___M 0x00008000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___S              15
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___M 0x00004000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___S              14
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___M 0x00002000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___S              13
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___M 0x00001000
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___S              12
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___M 0x00000800
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___S              11
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___M 0x00000400
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___S              10
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___M 0x00000200
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___S               9
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___M 0x00000100
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___S               8
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___M 0x00000080
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___S               7
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___M 0x00000040
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___S               6
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___M 0x00000020
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___S               5
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___M 0x00000010
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___S               4
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___M 0x00000008
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___S               3
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___M 0x00000004
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___S               2
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___M 0x00000002
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___S               1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___M 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___S               0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___S               0

#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2   (0x00A8C578)
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___POR 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___POR 0x1
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___M 0x00000001
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___S               0
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___M 0x00000001   
#define   WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0       (0x00A8C57C)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___POR 0x00000001
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___POR 0x01
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___M 0xFF000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___S              24
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___M 0x00FF0000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___S              16
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1       (0x00A8C580)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0     (0x00A8C584)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___POR 0x00000003
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___POR 0x03
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___M 0xFF000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___S              24
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___M 0x00FF0000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___S              16
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1     (0x00A8C588)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0     (0x00A8C58C)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___POR 0x0000000F
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___POR 0x0F
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___M 0xFF000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___S              24
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___M 0x00FF0000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___S              16
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1     (0x00A8C590)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0     (0x00A8C594)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___POR 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___POR 0xFF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___M 0xFF000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___S              24
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___M 0x00FF0000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___S              16
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1     (0x00A8C598)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___S               0

#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0    (0x00A8C59C)
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___POR 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___POR 0x00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___POR 0xFF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___M 0x00FF0000
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___S              16
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___S               8
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___M 0x000000FF
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___S               0
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___S               0

#define WMAC0_RXPCU_R0_HE_MISC_CFG                (0x00A8C5A0)
#define   WMAC0_RXPCU_R0_HE_MISC_CFG___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HE_MISC_CFG___POR       0x00000100
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___POR 0x1
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___POR 0x0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___M 0x00000100
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___S               8
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___M 0x00000040
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___S               6
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___M 0x00000020
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___S               5
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___M 0x00000010
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___S               4
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___M 0x00000008
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___S               3
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___M 0x00000004
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___S               2
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___M 0x00000002
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___S               1
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___M 0x00000001
#define   WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___S               0
#define   WMAC0_RXPCU_R0_HE_MISC_CFG___M         0x0000017F   
#define   WMAC0_RXPCU_R0_HE_MISC_CFG___S                       0

#define WMAC0_RXPCU_R0_TFD_OBO_CFG1               (0x00A8C5A4)
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1___POR      0xAC5A0010
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___POR 0x5
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___POR 0x3
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___POR 0x5A
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___POR 0x1
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___M 0xE0000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___S              29
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___M 0x1C000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___S              26
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___M  0x03800000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___S               23
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___M 0x007F0000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___M 0x00007F00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___S               8
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___M 0x00000070
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___S               4
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___M 0x00000008
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___S               3
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___M 0x00000004
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___S               2
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___S               1
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1___M        0xFFFF7F7F   
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG1___S                      0

#define WMAC0_RXPCU_R0_TFD_OBO_CNT1               (0x00A8C5A8)
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1___POR      0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___M 0x80000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___S              31
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___M 0x00010000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___S               8
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1___M        0x8001FFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT1___S                      0

#define WMAC0_RXPCU_R0_TFD_OBO_CFG2               (0x00A8C5AC)
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2___POR      0xAC5A0010
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___POR 0x5
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___POR 0x3
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___POR 0x5A
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___POR 0x1
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___M 0xE0000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___S              29
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___M 0x1C000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___S              26
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___M  0x03800000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___S               23
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___M 0x007F0000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___M 0x00007F00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___S               8
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___M 0x00000070
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___S               4
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___M 0x00000008
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___S               3
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___M 0x00000004
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___S               2
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___S               1
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2___M        0xFFFF7F7F   
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG2___S                      0

#define WMAC0_RXPCU_R0_TFD_OBO_CFG3               (0x00A8C5B0)
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3___POR      0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___M 0x00008000
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___S              15
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___M 0x00007F00
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___S               8
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___M 0x000000FE
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___S               1
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3___M        0x0000FFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO_CFG3___S                      0

#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1         (0x00A8C5B4)
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___POR 0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___M 0x1FC00000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___S              22
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___M 0x003F0000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___M 0x0000F800
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___S              11
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___M 0x00000780
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___S               7
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___M 0x00000070
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___S               4
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___M 0x0000000C
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___S               2
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___M 0x00000002
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___S               1
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___M 0x00000001
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___M  0x1FFFFFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___S                0

#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2         (0x00A8C5B8)
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___POR 0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___M 0x0FE00000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___S              21
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___M 0x001FC000
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___S              14
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___M 0x00003F80
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___S               7
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___M 0x0000007F
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___M  0x0FFFFFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___S                0

#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1         (0x00A8C5BC)
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___POR 0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___M 0x1FC00000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___S              22
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___M 0x003F0000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___M 0x0000F800
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___S              11
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___M 0x00000780
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___S               7
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___M 0x00000070
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___S               4
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___M 0x0000000C
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___S               2
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___M 0x00000002
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___S               1
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___M 0x00000001
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___M  0x1FFFFFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___S                0

#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2         (0x00A8C5C0)
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___POR 0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___M 0x0FE00000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___S              21
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___M 0x001FC000
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___S              14
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___M 0x00003F80
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___S               7
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___M 0x0000007F
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___M  0x0FFFFFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___S                0

#define WMAC0_RXPCU_R0_TFD_OBO_CNT2               (0x00A8C5C4)
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2___POR      0x00000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___POR 0x0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___M 0x80000000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___S              31
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___M 0x00010000
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___S              16
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___S               8
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___S               0
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2___M        0x8001FFFF   
#define   WMAC0_RXPCU_R0_TFD_OBO_CNT2___S                      0

#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32          (0x00A8C5C8)
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___POR 0x00000000
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___S               0
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___S                 0

#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16          (0x00A8C5CC)
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___POR 0x00000000
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___POR 0x0000
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___S               0
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___M   0x0000FFFF   
#define   WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___S                 0

#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1         (0x00A8C5D0)
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___S               0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___S                0

#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2         (0x00A8C5D4)
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___POR 0xFFFFFFF8
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___POR 0x1F
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___POR 0xFFFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___POR 0xFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___POR 0x0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___POR 0x0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___POR 0x0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___M 0xF8000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___S              27
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___M 0x07FFF800
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___S              11
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___M 0x000007F8
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___S               3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___M 0x00000004
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___S               2
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___M 0x00000002
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___S               1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___M 0x00000001
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___S               0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___S                0

#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3         (0x00A8C5D8)
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___POR 0xFF3FFFFF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___POR 0x0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___POR 0x0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___POR 0xF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___POR 0x7
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___POR 0xF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___POR 0x7F
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___M 0xC0000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___S              30
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___M 0x30000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___S              28
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___M 0x0C000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___S              26
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___M 0x03000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___S              24
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___M 0x00800000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___S              23
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___M 0x00400000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___S              22
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___M 0x00200000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___S              21
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___M 0x001E0000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___S              17
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___M 0x00010000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___S              16
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___M 0x00008000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___S              15
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___M 0x00007000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___S              12
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___M 0x00000800
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___S              11
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___M 0x00000780
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___S               7
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___M 0x0000007F
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___S               0
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___S                0

#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4         (0x00A8C5DC)
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___POR 0xFFF00000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___POR 0xF
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___POR 0x3
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___POR 0x1
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___M 0x80000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___S              31
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___M 0x60000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___S              29
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___M 0x1E000000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___S              25
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___M 0x01800000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___S              23
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___M 0x00400000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___S              22
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___M 0x00200000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___S              21
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___M 0x00100000
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___S              20
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___M  0xFFF00000   
#define   WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___S               20

#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL        (0x00A8C5E0)
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___POR 0x0008C410
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___POR 0x4
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___POR 0x1
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___POR 0x11
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___POR 0x00
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___POR 0x10
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___M 0x001E0000
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___S              17
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___M 0x00018000
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___S              15
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___M 0x00007C00
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___S              10
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___M 0x000003E0
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___S               5
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___M 0x0000001F
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___S               0
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___M 0x001FFFFF   
#define   WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___S               0

#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0          (0x00A8C5E4)
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___POR 0x025203A0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___POR 0x1
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___POR 0x05
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___POR 0x2
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___POR 0x1
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___POR 0x1A
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___S              25
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___M 0x01F00000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___S              20
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___M 0x000F0000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___S              16
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___S               9
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___M 0x000001F0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___S               4
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___M 0x0000000F
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___S               0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___M   0x03FF03FF   
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___S                 0

#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1          (0x00A8C5E8)
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___POR 0x025203A0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___POR 0x1
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___POR 0x05
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___POR 0x2
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___POR 0x1
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___POR 0x1A
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___S              25
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___M 0x01F00000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___S              20
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___M 0x000F0000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___S              16
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___S               9
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___M 0x000001F0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___S               4
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___M 0x0000000F
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___S               0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___M   0x03FF03FF   
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___S                 0

#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2          (0x00A8C5EC)
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___POR 0x00050004
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___POR 0x00
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___POR 0x5
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___POR 0x00
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___POR 0x4
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___S              25
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___M 0x01F00000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___S              20
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___M 0x000F0000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___S              16
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___S               9
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___M 0x000001F0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___S               4
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___M 0x0000000F
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___S               0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___M   0x03FF03FF   
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___S                 0

#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3          (0x00A8C5F0)
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___POR 0x00070006
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___POR 0x00
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___POR 0x7
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___POR 0x0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___POR 0x00
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___POR 0x6
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___S              25
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___M 0x01F00000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___S              20
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___M 0x000F0000
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___S              16
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___S               9
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___M 0x000001F0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___S               4
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___M 0x0000000F
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___S               0
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___M   0x03FF03FF   
#define   WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___S                 0

#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL   (0x00A8C5F4)
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___POR 0x00000000
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___POR 0x0
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___POR 0x00
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___M 0x00000100
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___S               8
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___M 0x000000FF
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___S               0
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___M 0x000001FF   
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___S               0

#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS (0x00A8C5F8)
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___POR 0x0
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___POR 0x0
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___M 0x00000002
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___S               1
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___M 0x00000001
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___S               0
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___M 0x00000003   
#define   WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___S               0

#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS (0x00A8C5FC)
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___POR 0x0
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___POR 0x0
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___M 0x00000002
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___S               1
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___M 0x00000001
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___S               0
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___M 0x00000003   
#define   WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___S               0

#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM             (0x00A8C600)
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM___POR    0x10000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___POR 0x1
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___POR 0x000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___M 0x80000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___S              31
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___M 0x40000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___S              30
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___M 0x20000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___S              29
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___M 0x10000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___S              28
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___M 0x08000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___S              27
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___M 0x07000000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___S              24
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___M 0x007FF000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___S              12
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___M 0x00000FFE
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___S               1
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___S               0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM___M      0xFF7FFFFF   
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM___S                    0

#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2            (0x00A8C604)
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___POR   0x00000001
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___POR 0x001
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___M 0x00010000
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___S              16
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___M 0x000001FF
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___S               0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___M     0x000101FF   
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___S                   0

#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3            (0x00A8C608)
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___POR   0x00000001
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___POR 0x001
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___M 0x000001FF
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___S               0
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___M     0x000001FF   
#define   WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___S                   0

#define WMAC0_RXPCU_R0_MBSSID_MASK                (0x00A8C60C)
#define   WMAC0_RXPCU_R0_MBSSID_MASK___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MBSSID_MASK___POR       0x000003FF
#define   WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___POR 0x3FF
#define   WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___M  0x000003FF
#define   WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___S                0
#define   WMAC0_RXPCU_R0_MBSSID_MASK___M         0x000003FF   
#define   WMAC0_RXPCU_R0_MBSSID_MASK___S                       0

#define WMAC0_RXPCU_R0_RFF_RX_FILTER3             (0x00A8C610)
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3___POR    0x00000000
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___POR 0x0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___S               1
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___M 0x00000001
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___S               0
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3___M      0x00000003   
#define   WMAC0_RXPCU_R0_RFF_RX_FILTER3___S                    0

#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL     (0x00A8C614)
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___POR 0x0717EE6A
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___M 0x80000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___S              31
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___S              30
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___M 0x20000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___S              29
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___M 0x10000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___S              28
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___S              27
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___S              26
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___S              25
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___S              24
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___M 0x00800000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___S              23
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___M 0x00200000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___S              21
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___M 0x00100000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___S              20
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___M 0x00080000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___S              19
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___M 0x00040000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___S              18
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___M 0x00020000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___S              17
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___M 0x00010000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___S              16
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___M 0x00008000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___S              15
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___M 0x00004000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___S              14
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___M 0x00002000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___S              13
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___M 0x00001000
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___S              12
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___M 0x00000800
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___S              11
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___S              10
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___S               9
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___S               8
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___M 0x00000080
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___S               7
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___S               6
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___M 0x00000020
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___S               5
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___M 0x00000010
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___S               4
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___M 0x00000008
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___S               3
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___M 0x00000004
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___S               2
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___S               1
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___M 0x00000001
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___S               0
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___M 0xFFBFFFFF   
#define   WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___S               0

#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO     (0x00A8C618)
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___POR 0x00000000
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___M 0xFF000000
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___S              24
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___M 0x00FF0000
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___S              16
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___M 0x0000FF00
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___S               8
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___M 0x000000FF
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___S               0
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___S               0

#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO         (0x00A8C61C)
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___POR 0x00000000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___POR 0x0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___POR 0x0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___POR 0x0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___POR 0x0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___POR 0x0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___POR 0x00
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___M 0xFF000000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___S              24
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___M 0x00008000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___S              15
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___M 0x00004000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___S              14
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___M 0x00002000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___S              13
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___M 0x00001000
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___S              12
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___M 0x00000F00
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___S               8
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___M 0x000000FF
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___S               0
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___M  0xFF00FFFF   
#define   WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___S                0

#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO (0x00A8C620)
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___POR 0x00000000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___POR 0x00
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___POR 0x0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___POR 0x00
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___M 0xFF000000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___S              24
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___M 0x00020000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___S              17
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___M 0x00010000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___S              16
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___M 0x00008000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___S              15
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___M 0x00004000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___S              14
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___M 0x00002000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___S              13
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___M 0x00001000
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___S              12
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___M 0x00000F00
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___S               8
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___M 0x000000FF
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___S               0
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___M 0xFF03FFFF   
#define   WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___S               0

#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0 (0x00A8C624)
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___POR 0x0000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___POR 0x00
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___S              16
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___M 0x0000F000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___S              12
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___M 0x00000F00
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___S               8
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___M 0x000000FF
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___S               0
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___S               0

#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1 (0x00A8C628)
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___S               0
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___S               0

#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0 (0x00A8C62C)
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___POR 0x0000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___POR 0x0
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___POR 0x00
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___S              16
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___M 0x0000F000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___S              12
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___M 0x00000F00
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___S               8
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___M 0x000000FF
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___S               0
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___S               0

#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1 (0x00A8C630)
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___S               0
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG       (0x00A8C634)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___POR 0x00100000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___M 0x40000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___S              30
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___M 0x20000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___S              29
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___M 0x10000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___S              28
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___S              27
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___S              26
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___S              25
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___S              24
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___M 0x00400000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___S              22
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___M 0x00200000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___S              21
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___M 0x00100000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___S              20
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___M 0x00080000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___S              19
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___M 0x00040000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___S              18
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___M 0x00020000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___S              17
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___M 0x00010000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___M 0x00006000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___S              13
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___M 0x00001000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___S              12
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___M 0x00000800
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___S              11
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___S              10
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___S               9
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___S               8
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___M 0x00000080
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___S               7
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___M 0x00000040
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___S               6
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___M 0x00000020
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___S               5
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___M 0x00000010
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___S               4
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___S               3
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___S               2
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___S               1
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___M 0x00000001
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___M 0x7F7F7FFF   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1      (0x00A8C638)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___M 0x00000F00
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___S               8
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___M 0x00000030
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___S               4
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___M 0x0000000C
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___S               2
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___M 0x00000003
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___M 0xFFFF0F3F   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___S               0

#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ          (0x00A8C63C)
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___POR 0x5A5A5A5A
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___POR 0x5A5A5A5A
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___S               0
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___S                 0

#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE            (0x00A8C640)
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE___POR   0xC3C3C3C3
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___POR 0xC3C3C3C3
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___S               0
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PPDU_DATA_VALUE___S                   0

#define WMAC0_RXPCU_R0_PPDU_DATA_BASE             (0x00A8C644)
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE___POR    0xA5A5A5A5
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___POR 0xA5A5A5A5
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___S               0
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PPDU_DATA_BASE___S                    0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE     (0x00A8C648)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___POR 0x00400102
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___POR 0x40
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___POR 0x1
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___POR 0x2
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___S              27
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___S              26
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___S              25
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___S              24
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___M 0x007F0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___M 0x00000F00
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___S               8
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___M 0x000000F0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___S               4
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___M 0x0000000F
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___M 0x0F7F0FFF   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK  (0x00A8C64C)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___POR 0x00
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___M 0x00000800
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___S              11
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___S              10
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___S               9
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___S               8
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___M 0x000000FF
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___M 0x00000FFF   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT (0x00A8C650)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___POR 0x002F0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___POR 0x002F
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG (0x00A8C654)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___POR 0x00
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___M 0x0F000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___S              24
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___M 0x00FF0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___M 0x00000300
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___S               8
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___M 0x0FFF0301   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___S               0

#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO (0x00A8C658)
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___S              16
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___S               0
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___S               0

#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0     (0x00A8C65C)
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___POR 0x000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___M 0x20000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___S              29
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___M 0x10000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___S              28
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___M 0x08000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___S              27
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___M 0x04000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___S              26
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___S              25
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___S              24
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___S               0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___M 0x3FFFFFFF   
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___S               0

#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1     (0x00A8C660)
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___POR 0x000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___S               0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___S               0

#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0    (0x00A8C664)
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___POR 0x000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___S               0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___S               0

#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1    (0x00A8C668)
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___POR 0x0000
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___S               0
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___S               0

#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION      (0x00A8C66C)
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___POR 0x0
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___POR 0x0
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___M 0x00000004
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___S               2
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___M 0x00000002
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___S               1
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___M 0x00000001
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___S               0
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___M 0x00000007   
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___S               0

#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL (0x00A8C670)
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___POR 0x00000000
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___S               0
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___S               0

#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0     (0x00A8C674)
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___POR 0x000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___S              27
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___S              26
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___S              25
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___S              24
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___S               0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___M 0x0FFFFFFF   
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___S               0

#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1     (0x00A8C678)
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___POR 0x000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___S               0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___S               0

#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0    (0x00A8C67C)
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___POR 0x000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___S               0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___S               0

#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1    (0x00A8C680)
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___POR 0x00000000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___POR 0x0000
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___S               0
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___S               0

#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT     (0x00A8C684)
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___POR 0x0
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___M 0x0000FF00
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___S               8
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___M 0x00000001
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___S               0
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___M 0x0000FF01   
#define   WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0     (0x00A8C688)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___POR 0x000000C1
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___POR 0x1
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___POR 0x1
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___POR 0x1
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___M 0x00001000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___S              12
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___M 0x00000800
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___S              11
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___M 0x00000400
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___S              10
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___M 0x00000200
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___S               9
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___M 0x00000100
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___S               8
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___M 0x00000080
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___S               7
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___M 0x00000040
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___S               6
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___M 0x00000020
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___S               5
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___M 0x00000010
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___S               3
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___S               2
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___S               1
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___M 0xFFFF1FFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1     (0x00A8C68C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___POR 0x000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2     (0x00A8C690)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3     (0x00A8C694)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___POR 0x00
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___M 0x00000100
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___S               8
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___M 0x0000001F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___M 0x0000011F   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4     (0x00A8C698)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___POR 0x000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___M 0x00FFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5     (0x00A8C69C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___POR 0x00
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___M 0x0000FF00
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___S               8
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___M 0x0000FF01   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6     (0x00A8C6A0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___M 0x00010000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___M 0x0001FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n(n) (0x00A8C6A4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0 (0x00A8C6A4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0__EXPECT_TA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0__EXPECT_TA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1 (0x00A8C6A8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1__EXPECT_TA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1__EXPECT_TA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2 (0x00A8C6AC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2__EXPECT_TA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2__EXPECT_TA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3 (0x00A8C6B0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3__EXPECT_TA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3__EXPECT_TA_L_32___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n(n) (0x00A8C6E4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0 (0x00A8C6E4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0__EXPECT_TA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0__EXPECT_TA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1 (0x00A8C6E8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1__EXPECT_TA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1__EXPECT_TA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2 (0x00A8C6EC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2__EXPECT_TA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2__EXPECT_TA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3 (0x00A8C6F0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3__EXPECT_TA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3__EXPECT_TA_U_16___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n(n) (0x00A8C724+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0 (0x00A8C724)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0__EXPECT_TA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1 (0x00A8C728)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1__EXPECT_TA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2 (0x00A8C72C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2__EXPECT_TA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3 (0x00A8C730)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3__EXPECT_TA_MASK_L_32___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n(n) (0x00A8C764+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___POR 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___POR 0xFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0 (0x00A8C764)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0__EXPECT_TA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0__EXPECT_TA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1 (0x00A8C768)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1__EXPECT_TA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1__EXPECT_TA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2 (0x00A8C76C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2__EXPECT_TA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2__EXPECT_TA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3 (0x00A8C770)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3__EXPECT_TA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3__EXPECT_TA_MASK_U_16___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n(n) (0x00A8C7A4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0 (0x00A8C7A4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0__EXPECT_RA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0__EXPECT_RA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1 (0x00A8C7A8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1__EXPECT_RA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1__EXPECT_RA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2 (0x00A8C7AC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2__EXPECT_RA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2__EXPECT_RA_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3 (0x00A8C7B0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3__EXPECT_RA_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3__EXPECT_RA_L_32___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n(n) (0x00A8C7E4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0 (0x00A8C7E4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0__EXPECT_RA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0__EXPECT_RA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1 (0x00A8C7E8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1__EXPECT_RA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1__EXPECT_RA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2 (0x00A8C7EC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2__EXPECT_RA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2__EXPECT_RA_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3 (0x00A8C7F0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3__EXPECT_RA_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3__EXPECT_RA_U_16___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n(n) (0x00A8C824+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0 (0x00A8C824)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0__EXPECT_RA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1 (0x00A8C828)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1__EXPECT_RA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2 (0x00A8C82C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2__EXPECT_RA_MASK_L_32___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3 (0x00A8C830)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3__EXPECT_RA_MASK_L_32___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n(n) (0x00A8C864+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___POR 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___POR 0xFFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0 (0x00A8C864)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0__EXPECT_RA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0__EXPECT_RA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1 (0x00A8C868)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1__EXPECT_RA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1__EXPECT_RA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2 (0x00A8C86C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2__EXPECT_RA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2__EXPECT_RA_MASK_U_16___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3 (0x00A8C870)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3__EXPECT_RA_MASK_U_16___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3__EXPECT_RA_MASK_U_16___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n(n) (0x00A8C8A4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___POR 0x00
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___POR 0x0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___M 0x00000FF0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___M 0x0000000F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___M 0x00000FFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0 (0x00A8C8A4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_NSS___M 0x00000FF0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_NSS___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_BW___M 0x0000000F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_BW___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1 (0x00A8C8A8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_NSS___M 0x00000FF0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_NSS___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_BW___M 0x0000000F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_BW___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2 (0x00A8C8AC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_NSS___M 0x00000FF0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_NSS___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_BW___M 0x0000000F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_BW___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3 (0x00A8C8B0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_NSS___M 0x00000FF0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_NSS___S               4
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_BW___M 0x0000000F
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_BW___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n(n) (0x00A8C8E4+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0 (0x00A8C8E4)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_CTRL_SUB_TYPE___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_MGMT_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1 (0x00A8C8E8)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_CTRL_SUB_TYPE___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_MGMT_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2 (0x00A8C8EC)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_CTRL_SUB_TYPE___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_MGMT_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3 (0x00A8C8F0)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_CTRL_SUB_TYPE___S              16
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_MGMT_SUB_TYPE___S               0

#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n(n) (0x00A8C924+0x4*(n))
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_nMIN 0    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_nMAX 3    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_ELEM 4    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___POR 0x00000000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___POR 0x0000
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___S               0
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___M 0x0000FFFF   
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0 (0x00A8C924)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0__EXPECT_DATA_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1 (0x00A8C928)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1__EXPECT_DATA_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2 (0x00A8C92C)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2__EXPECT_DATA_SUB_TYPE___S               0
#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3 (0x00A8C930)
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF
#define   WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3__EXPECT_DATA_SUB_TYPE___S               0

#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL           (0x00A8C964)
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___POR  0x78FC0C3C
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___M 0x80000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___S              31
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___M 0x40000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___S              30
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___M 0x20000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___S              29
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___M 0x10000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___S              28
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___S              27
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___S              26
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___S              25
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___S              24
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___M 0x00800000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___S              23
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___M 0x00400000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___S              22
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___M 0x00200000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___S              21
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___M 0x00100000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___S              20
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___M 0x00080000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___S              19
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___M 0x00040000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___S              18
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___M 0x00020000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___S              17
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___M 0x00010000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___S              16
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___M 0x00008000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___S              15
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___M 0x00004000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___S              14
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___M 0x00002000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___S              13
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___M 0x00001000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___S              12
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___M 0x00000800
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___S              11
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___S              10
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___S               9
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___S               8
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___M 0x00000080
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___S               7
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___M 0x00000040
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___S               6
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___M 0x00000020
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___S               5
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___M 0x00000010
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___S               4
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___M 0x00000008
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___S               3
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___M 0x00000004
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___S               2
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___S               1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___S               0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___S                  0

#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2          (0x00A8C968)
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___POR 0x4E95D21F
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___POR 0x1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___M 0x80000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___S              31
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___M 0x40000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___S              30
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___M 0x20000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___S              29
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___M 0x10000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___S              28
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___M 0x08000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___S              27
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___M 0x04000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___S              26
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___M 0x02000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___S              25
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___M 0x01000000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___S              24
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___M 0x00800000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___S              23
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___M 0x00400000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___S              22
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___M 0x00200000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___S              21
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___M 0x00100000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___S              20
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___M 0x00080000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___S              19
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___M 0x00040000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___S              18
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___M 0x00020000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___S              17
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___M 0x00010000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___S              16
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___M 0x00008000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___S              15
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___M 0x00004000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___S              14
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___M 0x00002000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___S              13
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___M 0x00001000
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___S              12
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___M 0x00000800
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___S              11
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___M 0x00000400
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___S              10
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___M 0x00000200
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___S               9
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___M 0x00000100
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___S               8
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___M 0x000000F0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___S               4
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___S               3
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___M 0x00000004
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___S               2
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___S               1
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___M 0x00000001
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___S               0
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___S                 0

#define WMAC0_RXPCU_R0_CLKGATE_CTRL2              (0x00A8C96C)
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2___POR     0x00000004
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___POR 0x1
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___POR 0x0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___M 0x00000008
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___S               3
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___M 0x00000004
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___S               2
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___M 0x00000002
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___S               1
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___M 0x00000001
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___S               0
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2___M       0x0000000F   
#define   WMAC0_RXPCU_R0_CLKGATE_CTRL2___S                     0

#define WMAC0_RXPCU_R0_MISC_MODE5                 (0x00A8C970)
#define   WMAC0_RXPCU_R0_MISC_MODE5___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_MISC_MODE5___POR        0x00002008
#define   WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___POR 0x0
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___POR 0x010
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___POR 0x008
#define   WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___M 0x00040000
#define   WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___S              18
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___M 0x0003FE00
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___S               9
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___M 0x000001FF
#define   WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___S               0
#define   WMAC0_RXPCU_R0_MISC_MODE5___M          0x0007FFFF   
#define   WMAC0_RXPCU_R0_MISC_MODE5___S                        0

#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY      (0x00A8C974)
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___M 0xFF000000
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___S              24
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___M 0x00FF0000
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___S              16
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___M 0x0000FF00
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___S               8
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___M 0x000000FF
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___S               0
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___S               0

#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY        (0x00A8C978)
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___POR 0x00000000
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___POR 0x00
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___M 0xFF000000
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___S              24
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___M 0x00FF0000
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___S              16
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___M 0x0000FF00
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___S               8
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___M 0x000000FF
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___S               0
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___S               0

#define WMAC0_RXPCU_R0_AXI_TIMEOUT                (0x00A8C97C)
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT___POR       0x00000000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___POR 0x0
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___POR 0x0
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___POR 0x0000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___POR 0x0000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___M 0x40000000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___S              30
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___M 0x20000000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___S              29
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___M 0x1FFF0000
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___S              16
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___M 0x00001FFF
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___S               0
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT___M         0x7FFF1FFF   
#define   WMAC0_RXPCU_R0_AXI_TIMEOUT___S                       0

#define WMAC0_RXPCU_R0_GSE_AXI_DELAY              (0x00A8C980)
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY___RWC        QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY___POR     0x00000000
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___POR 0x0000
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___POR 0x0000
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___M 0x1FFF0000
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___S              16
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___M 0x00001FFF
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___S               0
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY___M       0x1FFF1FFF   
#define   WMAC0_RXPCU_R0_GSE_AXI_DELAY___S                     0

#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY       (0x00A8C984)
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___POR 0x00000000
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___POR 0x0000
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___POR 0x0000
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___M 0x1FFF0000
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___S              16
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___M 0x00001FFF
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___S               0
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___M 0x1FFF1FFF   
#define   WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___S               0

#define WMAC0_RXPCU_R0_TRI_TLV_INFO               (0x00A8C988)
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO___POR      0x00000001
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___POR 0x000
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___POR 0x000
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___POR 0x000
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___POR 0x0
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___POR 0x1
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___M 0xFFF00000
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___S              20
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___M 0x000FF800
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___S              11
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___M 0x000007FC
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___S               2
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___M 0x00000002
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___S               1
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___S               0
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_TRI_TLV_INFO___S                      0

#define WMAC0_RXPCU_R0_TWT_SP_CFG                 (0x00A8C98C)
#define   WMAC0_RXPCU_R0_TWT_SP_CFG___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_TWT_SP_CFG___POR        0x60000B16
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___POR 0x60
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___POR 0x00
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___POR 0x0B
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___POR 0x16
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___M 0xFF000000
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___S              24
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___M 0x00FF0000
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___S              16
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___M 0x0000FF00
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___S               8
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___M 0x000000FF
#define   WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___S               0
#define   WMAC0_RXPCU_R0_TWT_SP_CFG___M          0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_TWT_SP_CFG___S                        0

#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n(n) (0x00A8C990+0x4*(n))
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_nMIN 0    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_nMAX 1    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_ELEM 2    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___S               0
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___S               0
#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0    (0x00A8C990)
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0__BITMAP_EN___S               0
#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1    (0x00A8C994)
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1__BITMAP_EN___S               0

#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n(n) (0x00A8C998+0x4*(n))
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_nMIN 0    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_nMAX 1    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_ELEM 2    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___S               0
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___S               0
#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0        (0x00A8C998)
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0__BITMAP_EN___S               0
#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1        (0x00A8C99C)
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1__BITMAP_EN___S               0

#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n(n) (0x00A8C9A0+0x4*(n))
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_nMIN 0    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_nMAX 1    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_ELEM 2    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___S               0
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___S               0
#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0    (0x00A8C9A0)
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0__BITMAP_EN___S               0
#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1    (0x00A8C9A4)
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1__BITMAP_EN___S               0

#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n(n) (0x00A8C9A8+0x4*(n))
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_nMIN 0    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_nMAX 1    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_ELEM 2    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___POR 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___S               0
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___S               0
#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0        (0x00A8C9A8)
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0__BITMAP_EN___S               0
#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1        (0x00A8C9AC)
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1__BITMAP_EN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1__BITMAP_EN___S               0

#define WMAC0_RXPCU_R0_SR_CFG_MISC                (0x00A8C9B0)
#define   WMAC0_RXPCU_R0_SR_CFG_MISC___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SR_CFG_MISC___POR       0x00000001
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___POR 0x000
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___POR 0x000
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___POR 0x0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___POR 0x0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___POR 0x1
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___M 0x1FFE0000
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___S              17
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___M 0x0001FFE0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___S               5
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___M 0x00000010
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___S               4
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___M 0x00000008
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___S               3
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___M 0x00000004
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___S               2
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___M 0x00000002
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___S               1
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___M 0x00000001
#define   WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___S               0
#define   WMAC0_RXPCU_R0_SR_CFG_MISC___M         0x1FFFFFFF   
#define   WMAC0_RXPCU_R0_SR_CFG_MISC___S                       0

#define WMAC0_RXPCU_R0_SRP_RESP_CFG               (0x00A8C9B4)
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG___POR      0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___POR 0x0
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___POR 0x00
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___M 0x00000040
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___S               6
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___M 0x0000003F
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG___M        0x0000007F   
#define   WMAC0_RXPCU_R0_SRP_RESP_CFG___S                      0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0            (0x00A8C9B8)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0___POR   0x01180007
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___POR 0x01180007
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE0___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1            (0x00A8C9BC)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1___POR   0x00118013
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___POR 0x00118013
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE1___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2            (0x00A8C9C0)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2___POR   0x00460017
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___POR 0x00460017
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE2___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3            (0x00A8C9C4)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3___POR   0x0000011B
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___POR 0x0000011B
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE3___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4            (0x00A8C9C8)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4___POR   0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___POR 0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE4___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5            (0x00A8C9CC)
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5___POR   0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___POR 0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5___M     0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_VALUE5___S                   0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK0             (0x00A8C9D0)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0___POR    0x013C003F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___POR 0x013C003F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK0___S                    0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK1             (0x00A8C9D4)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1___POR    0x0013C03F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___POR 0x0013C03F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK1___S                    0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK2             (0x00A8C9D8)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2___POR    0x004F003F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___POR 0x004F003F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK2___S                    0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK3             (0x00A8C9DC)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3___POR    0x0000013F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___POR 0x0000013F
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK3___S                    0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK4             (0x00A8C9E0)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4___POR    0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___POR 0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK4___S                    0

#define WMAC0_RXPCU_R0_SRP_RESP_MASK5             (0x00A8C9E4)
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5___POR    0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___POR 0x00000000
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___S               0
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R0_SRP_RESP_MASK5___S                    0

#define WMAC0_RXPCU_R0_ILP_CFG_1                  (0x00A8C9E8)
#define   WMAC0_RXPCU_R0_ILP_CFG_1___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_1___POR         0x1D000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___POR 0x1
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___POR 0x1
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___POR 0x1
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___POR 0x0
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___POR 0x1
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___POR 0x00
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___POR 0x00
#define   WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___POR 0x00
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___M 0x10000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___S              28
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___M 0x08000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___S              27
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___M 0x04000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___S              26
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___M 0x02000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___S              25
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___M 0x01000000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___S              24
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___M 0x00FF0000
#define   WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___S              16
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___M 0x0000FF00
#define   WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___S               8
#define   WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___M 0x000000FF
#define   WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_1___M           0x1FFFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_1___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_2                  (0x00A8C9EC)
#define   WMAC0_RXPCU_R0_ILP_CFG_2___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_2___POR         0x00000000
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___M 0x07FC0000
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___S              18
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___M 0x0003FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_2___M           0x07FFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_2___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_3                  (0x00A8C9F0)
#define   WMAC0_RXPCU_R0_ILP_CFG_3___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_3___POR         0x00000000
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___M 0x07FC0000
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___S              18
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___M 0x0003FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_3___M           0x07FFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_3___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_4                  (0x00A8C9F4)
#define   WMAC0_RXPCU_R0_ILP_CFG_4___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_4___POR         0x00000000
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___M 0x07FC0000
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___S              18
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___M 0x0003FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_4___M           0x07FFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_4___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_5                  (0x00A8C9F8)
#define   WMAC0_RXPCU_R0_ILP_CFG_5___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_5___POR         0x00000000
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___M 0x07FC0000
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___S              18
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___M 0x0003FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_5___M           0x07FFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_5___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_6                  (0x00A8C9FC)
#define   WMAC0_RXPCU_R0_ILP_CFG_6___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_6___POR         0x00000000
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___M 0x07FC0000
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___S              18
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___M 0x0003FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_6___M           0x07FFFFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_6___S                         0

#define WMAC0_RXPCU_R0_ILP_CFG_7                  (0x00A8CA00)
#define   WMAC0_RXPCU_R0_ILP_CFG_7___RWC            QCSR_REG_RW    
#define   WMAC0_RXPCU_R0_ILP_CFG_7___POR         0x00008000
#define   WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___POR 0x40
#define   WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___POR 0x000
#define   WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___M 0x0000FE00
#define   WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___S               9
#define   WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___M 0x000001FF
#define   WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___S               0
#define   WMAC0_RXPCU_R0_ILP_CFG_7___M           0x0000FFFF   
#define   WMAC0_RXPCU_R0_ILP_CFG_7___S                         0

#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK      (0x00A8D000)
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___S               0

#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS   (0x00A8D004)
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___S               0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___M 0x00000001   
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___S               0

#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A8D008)
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S               0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___S               0

#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER (0x00A8D00C)
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S               0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___S               0

#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A8D010)
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S              10
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S               0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF   
#define   WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___S               0

#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER (0x00A8D014)
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S              10
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S               5
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S               0
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF   
#define   WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___S               0

#define WMAC0_RXPCU_R1_GSE_SM_STATES              (0x00A8D018)
#define   WMAC0_RXPCU_R1_GSE_SM_STATES___RWC        QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_SM_STATES___POR     0x00000000
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___M 0x00300000
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___S              20
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___S              18
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___M 0x00030000
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___S              16
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___S              14
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___M 0x00003800
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___S              11
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___M 0x00000700
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___S               8
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___M 0x0000000F
#define   WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___S               0
#define   WMAC0_RXPCU_R1_GSE_SM_STATES___M       0x003FFF0F   
#define   WMAC0_RXPCU_R1_GSE_SM_STATES___S                     0

#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG            (0x00A8D01C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___RWC      QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___POR   0x00000000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___POR 0x000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___M 0x000003FF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___S               0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___M     0x000003FF   
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___S                   0

#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS (0x00A8D020)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S               3
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S               2
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S               1
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___S               0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF   
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___S               0

#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n(n) (0x00A8D024+0x4*(n))
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_nMIN 0    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_nMAX 31   
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_ELEM 32   
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___S               0
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0    (0x00A8D024)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1    (0x00A8D028)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2    (0x00A8D02C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3    (0x00A8D030)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4    (0x00A8D034)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5    (0x00A8D038)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6    (0x00A8D03C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7    (0x00A8D040)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8    (0x00A8D044)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9    (0x00A8D048)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10   (0x00A8D04C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11   (0x00A8D050)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12   (0x00A8D054)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13   (0x00A8D058)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14   (0x00A8D05C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15   (0x00A8D060)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16   (0x00A8D064)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17   (0x00A8D068)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18   (0x00A8D06C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19   (0x00A8D070)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20   (0x00A8D074)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21   (0x00A8D078)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22   (0x00A8D07C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23   (0x00A8D080)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24   (0x00A8D084)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25   (0x00A8D088)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26   (0x00A8D08C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27   (0x00A8D090)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28   (0x00A8D094)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29   (0x00A8D098)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30   (0x00A8D09C)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30__VAL___S               0
#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31   (0x00A8D0A0)
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31__VAL___S               0

#define WMAC0_RXPCU_R1_PHY_ERR_CODE               (0x00A8D0A4)
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE___POR      0x00000000
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___POR 0x00
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___M 0x000000FF
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___S               0
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE___M        0x000000FF   
#define   WMAC0_RXPCU_R1_PHY_ERR_CODE___S                      0

#define WMAC0_RXPCU_R1_TESTBUS_CTRL               (0x00A8D0A8)
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL___POR      0x00000000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___POR 0x00
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___POR 0x0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___POR 0x00
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___M 0xF0000000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___S              28
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___M 0x00800000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___S              23
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___M 0x00400000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___S              22
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___M 0x003C0000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___S              18
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___M 0x00038000
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___S              15
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___M  0x00007E00
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___S                9
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___M 0x000001C0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___S               6
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___M   0x0000003F
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___S                 0
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL___M        0xF0FFFFFF   
#define   WMAC0_RXPCU_R1_TESTBUS_CTRL___S                      0

#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS       (0x00A8D0AC)
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___S               0
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___S               0

#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS       (0x00A8D0B0)
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___POR 0x00000000
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___S               0
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___S               0

#define WMAC0_RXPCU_R1_FSM_STATUS_0               (0x00A8D0B4)
#define   WMAC0_RXPCU_R1_FSM_STATUS_0___RWC         QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_FSM_STATUS_0___POR      0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___S               0
#define   WMAC0_RXPCU_R1_FSM_STATUS_0___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_FSM_STATUS_0___S                      0

#define WMAC0_RXPCU_R1_FSM_STATUS_1               (0x00A8D0B8)
#define   WMAC0_RXPCU_R1_FSM_STATUS_1___RWC         QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_FSM_STATUS_1___POR      0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___S               0
#define   WMAC0_RXPCU_R1_FSM_STATUS_1___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_FSM_STATUS_1___S                      0

#define WMAC0_RXPCU_R1_FSM_STATUS_2               (0x00A8D0BC)
#define   WMAC0_RXPCU_R1_FSM_STATUS_2___RWC         QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_FSM_STATUS_2___POR      0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___S               0
#define   WMAC0_RXPCU_R1_FSM_STATUS_2___M        0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_FSM_STATUS_2___S                      0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT (0x00A8D0C0)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT (0x00A8D0C4)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT (0x00A8D0C8)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT (0x00A8D0CC)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT (0x00A8D0D0)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT (0x00A8D0D4)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT (0x00A8D0D8)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT   (0x00A8D0DC)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT   (0x00A8D0E0)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT   (0x00A8D0E4)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT (0x00A8D0E8)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT (0x00A8D0EC)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT (0x00A8D0F0)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT (0x00A8D0F4)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT (0x00A8D0F8)
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD          (0x00A8D0FC)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___RWC    QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___M 0xFFFF0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___S              16
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___S                 0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT (0x00A8D100)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT (0x00A8D104)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT (0x00A8D108)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT (0x00A8D10C)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT (0x00A8D110)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT (0x00A8D114)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT (0x00A8D118)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT (0x00A8D11C)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___S               0

#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT (0x00A8D120)
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___POR 0x00
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___POR 0x00
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___POR 0x00
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___M 0x00FF0000
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___S              16
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___M 0x0000FF00
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___S               8
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___M 0x000000FF
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___S               0
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___M 0x00FFFFFF   
#define   WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT (0x00A8D124)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT (0x00A8D128)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT  (0x00A8D12C)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT (0x00A8D130)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT (0x00A8D134)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___S               0

#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP      (0x00A8D138)
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___RWC QCSR_REG_RO    
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___POR 0x00000000
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___S               0
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___M 0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___S               0

#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT (0x00A8D13C)
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___S               0

#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT (0x00A8D140)
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___S               0

#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT (0x00A8D144)
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___S               0

#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT (0x00A8D148)
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT    (0x00A8D14C)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT (0x00A8D150)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT         (0x00A8D154)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___M  0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___S                0

#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT        (0x00A8D158)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___RWC  QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT    (0x00A8D15C)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT   (0x00A8D160)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___M 0x0000FFFF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___M 0x0000FFFF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___S               0

#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT     (0x00A8D164)
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___RWC QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___POR 0x00000000
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___M 0x000000FF
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___S               0
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___M 0x000000FF   
#define   WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___S               0

#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0         (0x00A8D168)
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___POR 0x00000000
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___S               0
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___S                0

#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1         (0x00A8D16C)
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___POR 0x00000000
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___S               0
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___S                0

#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1             (0x00A8D170)
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1___POR    0x00000032
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___POR 0x32
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___M 0x000000FF
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___S               0
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1___M      0x000000FF   
#define   WMAC0_RXPCU_R1_EVENT_BUS_CFG1___S                    0

#define WMAC0_RXPCU_R1_CMNTRIG_CFG                (0x00A8D174)
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG___RWC          QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG___POR       0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___POR 0x0
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___POR  0x00
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___M 0x00000700
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___S               8
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___M    0x000000FF
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___S                  0
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG___M         0x000007FF   
#define   WMAC0_RXPCU_R1_CMNTRIG_CFG___S                       0

#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32           (0x00A8D178)
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___POR  0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___S               0
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___M    0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___S                  0

#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07           (0x00A8D17C)
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___POR  0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___M 0x0000007F
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___S               0
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___M    0x0000007F   
#define   WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___S                  0

#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32          (0x00A8D180)
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___POR 0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___S               0
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___M   0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___S                 0

#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07          (0x00A8D184)
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___RWC    QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___POR 0x00000000
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___POR 0x00
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___M 0x0000007F
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___S               0
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___M   0x0000007F   
#define   WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___S                 0

#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU             (0x00A8D188)
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU___RWC       QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU___POR    0x00000000
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___S               0
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU___M      0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_FCS_PASS_AMPDU___S                    0

#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU         (0x00A8D18C)
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___RWC   QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___POR 0x00000000
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___POR 0x00000000
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___S               0
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___M  0xFFFFFFFF   
#define   WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___S                0

#define WMAC0_RXPCU_R1_GP_ACK_CNT                 (0x00A8D190)
#define   WMAC0_RXPCU_R1_GP_ACK_CNT___RWC           QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_GP_ACK_CNT___POR        0x00000000
#define   WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___POR 0x0000
#define   WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___M   0x0000FFFF
#define   WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___S                 0
#define   WMAC0_RXPCU_R1_GP_ACK_CNT___M          0x0000FFFF   
#define   WMAC0_RXPCU_R1_GP_ACK_CNT___S                        0

#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS           (0x00A8D194)
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS___RWC     QCSR_REG_RW    
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS___POR  0x00000000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___POR 0x0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___POR 0x0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___POR 0x0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___POR 0x00
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___POR 0x000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___POR 0x0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___POR 0x000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___POR 0x0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___M 0x40000000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___S              30
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___M 0x20000000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___S              29
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___M 0x10000000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___S              28
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___M 0x0FF00000
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___S              20
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___M 0x000FF800
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___S              11
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___M 0x00000400
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___S              10
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___M 0x000003FE
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___S               1
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___M 0x00000001
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___S               0
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS___M    0x7FFFFFFF   
#define   WMAC0_RXPCU_R1_PMI_ERROR_STATUS___S                  0

#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS            (0x00A8F000)
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___RWC      QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___POR   0x30301919
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___POR 0x30
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___POR 0x30
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___POR 0x19
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___POR 0x19
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___M 0xFF000000
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___S              24
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___M 0x00FF0000
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___S              16
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___M 0x0000FF00
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___S               8
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___M 0x000000FF
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___S               0
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___M     0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___S                   0

#define WMAC0_TXPCU_R0_TIMEOUT_CBF                (0x00A8F004)
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF___RWC          QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF___POR       0x00004019
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___POR 0x40
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___POR 0x19
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___M 0x0000FF00
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___S               8
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___M 0x000000FF
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___S               0
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF___M         0x0000FFFF   
#define   WMAC0_TXPCU_R0_TIMEOUT_CBF___S                       0

#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT           (0x00A8F008)
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___RWC     QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___POR  0x0014000E
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___POR 0x1400
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___POR 0x0E
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___M 0x00FFFF00
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___S               8
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___M 0x000000FF
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___S               0
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___M    0x00FFFFFF   
#define   WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___S                  0

#define WMAC0_TXPCU_R0_WUR_CONTROL                (0x00A8F00C)
#define   WMAC0_TXPCU_R0_WUR_CONTROL___RWC          QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_WUR_CONTROL___POR       0x00050000
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___POR 0x05
#define   WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___POR 0x0
#define   WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___POR 0x0
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___POR 0x00
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___M 0x003F0000
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___S              16
#define   WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___M 0x00001000
#define   WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___S              12
#define   WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___M 0x00000100
#define   WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___S               8
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___M 0x000000FF
#define   WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___S               0
#define   WMAC0_TXPCU_R0_WUR_CONTROL___M         0x003F11FF   
#define   WMAC0_TXPCU_R0_WUR_CONTROL___S                       0

#define WMAC0_TXPCU_R0_WATCHDOG                   (0x00A8F010)
#define   WMAC0_TXPCU_R0_WATCHDOG___RWC             QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_WATCHDOG___POR          0x00002710
#define   WMAC0_TXPCU_R0_WATCHDOG__STATUS___POR  0x0000
#define   WMAC0_TXPCU_R0_WATCHDOG__LIMIT___POR   0x2710
#define   WMAC0_TXPCU_R0_WATCHDOG__STATUS___M    0xFFFF0000
#define   WMAC0_TXPCU_R0_WATCHDOG__STATUS___S                 16
#define   WMAC0_TXPCU_R0_WATCHDOG__LIMIT___M     0x0000FFFF
#define   WMAC0_TXPCU_R0_WATCHDOG__LIMIT___S                   0
#define   WMAC0_TXPCU_R0_WATCHDOG___M            0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_WATCHDOG___S                          0

#define WMAC0_TXPCU_R0_SIFS_TIMEOUT               (0x00A8F014)
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT___RWC         QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT___POR      0x000000FF
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___POR 0x0
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___POR 0xFF
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___M 0x00000100
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___S               8
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___S               0
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT___M        0x000001FF   
#define   WMAC0_TXPCU_R0_SIFS_TIMEOUT___S                      0

#define WMAC0_TXPCU_R0_PHY_TX_LATENCY             (0x00A8F018)
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY___POR    0x00000000
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___POR 0x00
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___POR 0x00
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___M 0x00003F00
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___S               8
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___S               0
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY___M      0x00003FFF   
#define   WMAC0_TXPCU_R0_PHY_TX_LATENCY___S                    0

#define WMAC0_TXPCU_R0_TX_ANT_CTL                 (0x00A8F01C)
#define   WMAC0_TXPCU_R0_TX_ANT_CTL___RWC           QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TX_ANT_CTL___POR        0x80000000
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___POR 0x1
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___POR 0x0
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___POR 0x000000
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___M 0x80000000
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___S              31
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___M 0x03000000
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___S              24
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___M 0x00FFFFFF
#define   WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___S               0
#define   WMAC0_TXPCU_R0_TX_ANT_CTL___M          0x83FFFFFF   
#define   WMAC0_TXPCU_R0_TX_ANT_CTL___S                        0

#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM               (0x00A8F020)
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM___RWC         QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM___POR      0x02FF0000
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___POR 0x2FF
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___POR 0x000
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___M   0x0FFF0000
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___S                16
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___M   0x00000FFF
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___S                 0
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM___M        0x0FFF0FFF   
#define   WMAC0_TXPCU_R0_MGMT_SEQ_NUM___S                      0

#define WMAC0_TXPCU_R0_MISC_MODE                  (0x00A8F024)
#define   WMAC0_TXPCU_R0_MISC_MODE___RWC            QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MISC_MODE___POR         0xB01FF20C
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___M 0x80000000
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___S              31
#define   WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___M 0x40000000
#define   WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___S              30
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___M 0x20000000
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___S              29
#define   WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___M 0x10000000
#define   WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___S              28
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___M 0x08000000
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___S              27
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___M 0x04000000
#define   WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___S              26
#define   WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___M 0x02000000
#define   WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___S              25
#define   WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___M 0x01000000
#define   WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___S              24
#define   WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___M 0x00800000
#define   WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___S              23
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___M 0x00400000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___S              22
#define   WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___M 0x00200000
#define   WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___S              21
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___M 0x00100000
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___S              20
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___M 0x00080000
#define   WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___S              19
#define   WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___M 0x00040000
#define   WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___S              18
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___M 0x00020000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___S              17
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___M 0x00010000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___S              16
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___M 0x00008000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___S              15
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___M 0x00004000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___S              14
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___M 0x00002000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___S              13
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___M 0x00001000
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___S              12
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___M 0x00000800
#define   WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___S              11
#define   WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___M 0x00000400
#define   WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___S              10
#define   WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___M 0x00000200
#define   WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___S               9
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___M 0x00000100
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___S               8
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___M 0x00000080
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___S               7
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___M 0x00000040
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___S               6
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___M 0x00000020
#define   WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___S               5
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___M 0x00000010
#define   WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___S               4
#define   WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___M 0x00000008
#define   WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___S               3
#define   WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___M 0x00000004
#define   WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___S               2
#define   WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___M 0x00000002
#define   WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___S               1
#define   WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___M 0x00000001
#define   WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___S               0
#define   WMAC0_TXPCU_R0_MISC_MODE___M           0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_MISC_MODE___S                         0

#define WMAC0_TXPCU_R0_RTT_CTRL                   (0x00A8F028)
#define   WMAC0_TXPCU_R0_RTT_CTRL___RWC             QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RTT_CTRL___POR          0x00000000
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___POR 0x0
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___POR 0x0
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___M 0x00000002
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___S               1
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___M 0x00000001
#define   WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___S               0
#define   WMAC0_TXPCU_R0_RTT_CTRL___M            0x00000003   
#define   WMAC0_TXPCU_R0_RTT_CTRL___S                          0

#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD         (0x00A8F02C)
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___POR 0x00200020
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___POR 0x0020
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___POR 0x0020
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___S              16
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___S               0
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___M  0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___S                0

#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD  (0x00A8F030)
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___POR 0x00000002
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___POR 0x0000
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___POR 0x0002
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___S              16
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___S               0
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___S               0

#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL             (0x00A8F034)
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___POR    0x00006490
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___POR 0x3
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___POR 0x1
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___POR 0x1
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___POR 0x1
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___POR 0x0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___M 0x00006000
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___S              13
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___M 0x00001000
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___S              12
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___M 0x00000C00
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___S              10
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___M 0x00000200
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___S               9
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___M 0x00000180
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___S               7
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___M 0x00000040
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___S               6
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___M 0x00000020
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___S               5
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___M 0x00000010
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___S               4
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___M 0x0000000C
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___S               2
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___M 0x00000002
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___S               1
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___M 0x00000001
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___S               0
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___M      0x00007FFF   
#define   WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___S                    0

#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME        (0x00A8F038)
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___RWC  QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___POR 0x00000007
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___POR 0x0007
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___S               0
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___M 0x0000FFFF   
#define   WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___S               0

#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY    (0x00A8F03C)
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___POR 0x00000001
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___POR 0x01
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___S               0
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___M 0x000000FF   
#define   WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___S               0

#define WMAC0_TXPCU_R0_CBF_DETAILS                (0x00A8F040)
#define   WMAC0_TXPCU_R0_CBF_DETAILS___RWC          QCSR_REG_RO    
#define   WMAC0_TXPCU_R0_CBF_DETAILS___POR       0x00000000
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___POR 0x0
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___POR 0x0
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___M 0x00000002
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___S               1
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___M 0x00000001
#define   WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___S               0
#define   WMAC0_TXPCU_R0_CBF_DETAILS___M         0x00000003   
#define   WMAC0_TXPCU_R0_CBF_DETAILS___S                       0

#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY (0x00A8F044)
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___POR 0x00000005
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___POR 0x0005
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___S               0
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___M 0x0000FFFF   
#define   WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___S               0

#define WMAC0_TXPCU_R0_MISC_MODE_EXT              (0x00A8F048)
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT___RWC        QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT___POR     0x0A000840
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___POR 0x280
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___POR 0x1
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___POR 0x0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___M 0x0FFC0000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___S              18
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___M 0x00020000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___S              17
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___M 0x00010000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___S              16
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___M 0x00008000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___S              15
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___M 0x00004000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___S              14
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___M 0x00002000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___S              13
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___M 0x00001000
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___S              12
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___M 0x00000800
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___S              11
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___M 0x00000400
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___S              10
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___M 0x00000200
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___S               9
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___M 0x00000100
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___S               8
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___M 0x00000080
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___S               7
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___M 0x00000040
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___S               6
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___M 0x00000020
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___S               5
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___M 0x00000010
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___S               4
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___M 0x00000008
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___S               3
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___M 0x00000004
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___S               2
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___M 0x00000002
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___S               1
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___M 0x00000001
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___S               0
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT___M       0x0FFFFFFF   
#define   WMAC0_TXPCU_R0_MISC_MODE_EXT___S                     0

#define WMAC0_TXPCU_R0_TQM_UPDATE                 (0x00A8F04C)
#define   WMAC0_TXPCU_R0_TQM_UPDATE___RWC           QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TQM_UPDATE___POR        0x00000000
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___POR 0x0
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___POR 0x0
#define   WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___POR 0x000000
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___M 0x02000000
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___S              25
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___M 0x01000000
#define   WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___S              24
#define   WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___M 0x00FFFFFF
#define   WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___S               0
#define   WMAC0_TXPCU_R0_TQM_UPDATE___M          0x03FFFFFF   
#define   WMAC0_TXPCU_R0_TQM_UPDATE___S                        0

#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY           (0x00A8F050)
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___RWC     QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___POR  0x01400001
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___POR 0x0140
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___POR 0x01
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___S              16
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___S               0
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___M    0xFFFF00FF   
#define   WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___S                  0

#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE  (0x00A8F054)
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___POR 0x00000C00
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___POR 0x0C00
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___S               0
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___M 0x0000FFFF   
#define   WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___S               0

#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE      (0x00A8F058)
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___POR 0x00000080
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___POR 0x0080
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___S               0
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___M 0x0000FFFF   
#define   WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___S               0

#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME  (0x00A8F05C)
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___POR 0x00000009
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___POR 0x09
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___S               0
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___M 0x000000FF   
#define   WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___S               0

#define WMAC0_TXPCU_R0_CBF_PADDING                (0x00A8F060)
#define   WMAC0_TXPCU_R0_CBF_PADDING___RWC          QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_PADDING___POR       0x00040001
#define   WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___POR 0x04
#define   WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___POR 0x0001
#define   WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___M 0x001F0000
#define   WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___S              16
#define   WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___S               0
#define   WMAC0_TXPCU_R0_CBF_PADDING___M         0x001FFFFF   
#define   WMAC0_TXPCU_R0_CBF_PADDING___S                       0

#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC      (0x00A8F064)
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___POR 0x00A00780
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___POR 0x00A0
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___POR 0x0780
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___S              16
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___S               0
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___S               0

#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER            (0x00A8F068)
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER___RWC      QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER___POR   0x0E600D20
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___POR 0x0E60
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___POR 0x0D20
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___S              16
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___S               0
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER___M     0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_PIFS_TIMER___S                   0

#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL             (0x00A8F06C)
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL___POR    0x001F0780
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___POR 0x001F
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___POR 0x0780
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___S              16
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___S               0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_TRIG_RESP_CTRL___S                    0

#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR        (0x00A8F074)
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___RWC  QCSR_REG_RO    
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___S               0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0     (0x00A8F078)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___M 0xFF000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___S              24
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___M 0x00FF0000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___S              16
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___M 0x0000FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___S               0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1     (0x00A8F07C)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___M 0xFF000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___S              24
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___M 0x00FF0000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___S              16
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___M 0x0000FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___S               0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0         (0x00A8F080)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___POR 0x000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___M 0x0001FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___M  0x0001FFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___S                0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0     (0x00A8F084)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___M 0xFF000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___S              24
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___M 0x00FF0000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___S              16
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___M 0x0000FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___S               0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1     (0x00A8F088)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___M 0xFF000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___S              24
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___M 0x00FF0000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___S              16
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___M 0x0000FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___S               0

#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1         (0x00A8F08C)
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___POR 0x00000000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___POR 0x000
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___POR 0x00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___M 0x0001FF00
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___S               8
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___M 0x000000FF
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___S               0
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___M  0x0001FFFF   
#define   WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___S                0

#define WMAC0_TXPCU_R0_SELF_GEN_ERROR             (0x00A8F0E0)
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR___RWC       QCSR_REG_RO    
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR___POR    0x00000000
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___POR 0x00
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___M 0x000000FF
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___S               0
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR___M      0x000000FF   
#define   WMAC0_TXPCU_R0_SELF_GEN_ERROR___S                    0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n(n) (0x00A8F104+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMAX 6    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_ELEM 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0 (0x00A8F104)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1 (0x00A8F108)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2 (0x00A8F10C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3 (0x00A8F110)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4 (0x00A8F114)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5 (0x00A8F118)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6 (0x00A8F11C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n(n) (0x00A8F120+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0 (0x00A8F120)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1 (0x00A8F124)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2 (0x00A8F128)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3 (0x00A8F12C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4 (0x00A8F130)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5 (0x00A8F134)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6 (0x00A8F138)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7 (0x00A8F13C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n(n) (0x00A8F140+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0  (0x00A8F140)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1  (0x00A8F144)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2  (0x00A8F148)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3  (0x00A8F14C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4  (0x00A8F150)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5  (0x00A8F154)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6  (0x00A8F158)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7  (0x00A8F15C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n(n) (0x00A8F160+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMAX 11   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_ELEM 12   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0 (0x00A8F160)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1 (0x00A8F164)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2 (0x00A8F168)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3 (0x00A8F16C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4 (0x00A8F170)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5 (0x00A8F174)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6 (0x00A8F178)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7 (0x00A8F17C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8 (0x00A8F180)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9 (0x00A8F184)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10 (0x00A8F188)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11 (0x00A8F18C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n(n) (0x00A8F190+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0  (0x00A8F190)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1  (0x00A8F194)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2  (0x00A8F198)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3  (0x00A8F19C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4  (0x00A8F1A0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5  (0x00A8F1A4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6  (0x00A8F1A8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7  (0x00A8F1AC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8  (0x00A8F1B0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9  (0x00A8F1B4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10 (0x00A8F1B8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11 (0x00A8F1BC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12 (0x00A8F1C0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13 (0x00A8F1C4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n(n) (0x00A8F1C8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0 (0x00A8F1C8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1 (0x00A8F1CC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2 (0x00A8F1D0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3 (0x00A8F1D4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4 (0x00A8F1D8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5 (0x00A8F1DC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6 (0x00A8F1E0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7 (0x00A8F1E4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n(n) (0x00A8F1E8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0 (0x00A8F1E8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1 (0x00A8F1EC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2 (0x00A8F1F0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3 (0x00A8F1F4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4 (0x00A8F1F8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5 (0x00A8F1FC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6 (0x00A8F200)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7 (0x00A8F204)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n(n) (0x00A8F208+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0 (0x00A8F208)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1 (0x00A8F20C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2 (0x00A8F210)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3 (0x00A8F214)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4 (0x00A8F218)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5 (0x00A8F21C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6 (0x00A8F220)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7 (0x00A8F224)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n(n) (0x00A8F228+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMAX 11   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_ELEM 12   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0 (0x00A8F228)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1 (0x00A8F22C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2 (0x00A8F230)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3 (0x00A8F234)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4 (0x00A8F238)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5 (0x00A8F23C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6 (0x00A8F240)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7 (0x00A8F244)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8 (0x00A8F248)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9 (0x00A8F24C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10 (0x00A8F250)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11 (0x00A8F254)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n(n) (0x00A8F258+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0 (0x00A8F258)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1 (0x00A8F25C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2 (0x00A8F260)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3 (0x00A8F264)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4 (0x00A8F268)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5 (0x00A8F26C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6 (0x00A8F270)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7 (0x00A8F274)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8 (0x00A8F278)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9 (0x00A8F27C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10 (0x00A8F280)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11 (0x00A8F284)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12 (0x00A8F288)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13 (0x00A8F28C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n(n) (0x00A8F290+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0 (0x00A8F290)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1 (0x00A8F294)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2 (0x00A8F298)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3 (0x00A8F29C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4 (0x00A8F2A0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5 (0x00A8F2A4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6 (0x00A8F2A8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7 (0x00A8F2AC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8 (0x00A8F2B0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9 (0x00A8F2B4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10 (0x00A8F2B8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11 (0x00A8F2BC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12 (0x00A8F2C0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13 (0x00A8F2C4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n(n) (0x00A8F2C8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0 (0x00A8F2C8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1 (0x00A8F2CC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2 (0x00A8F2D0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3 (0x00A8F2D4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4 (0x00A8F2D8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5 (0x00A8F2DC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6 (0x00A8F2E0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7 (0x00A8F2E4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n(n) (0x00A8F2E8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMAX 11   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_ELEM 12   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0 (0x00A8F2E8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1 (0x00A8F2EC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2 (0x00A8F2F0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3 (0x00A8F2F4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4 (0x00A8F2F8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5 (0x00A8F2FC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6 (0x00A8F300)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7 (0x00A8F304)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8 (0x00A8F308)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9 (0x00A8F30C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10 (0x00A8F310)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11 (0x00A8F314)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n(n) (0x00A8F318+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0 (0x00A8F318)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1 (0x00A8F31C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2 (0x00A8F320)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3 (0x00A8F324)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4 (0x00A8F328)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5 (0x00A8F32C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6 (0x00A8F330)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7 (0x00A8F334)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8 (0x00A8F338)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9 (0x00A8F33C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10 (0x00A8F340)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11 (0x00A8F344)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12 (0x00A8F348)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13 (0x00A8F34C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n(n) (0x00A8F350+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0 (0x00A8F350)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1 (0x00A8F354)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2 (0x00A8F358)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3 (0x00A8F35C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4 (0x00A8F360)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5 (0x00A8F364)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6 (0x00A8F368)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7 (0x00A8F36C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8 (0x00A8F370)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9 (0x00A8F374)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10 (0x00A8F378)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11 (0x00A8F37C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12 (0x00A8F380)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13 (0x00A8F384)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n(n) (0x00A8F388+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0 (0x00A8F388)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1 (0x00A8F38C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2 (0x00A8F390)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3 (0x00A8F394)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4 (0x00A8F398)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5 (0x00A8F39C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6 (0x00A8F3A0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7 (0x00A8F3A4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n(n) (0x00A8F3A8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0 (0x00A8F3A8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1 (0x00A8F3AC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2 (0x00A8F3B0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3 (0x00A8F3B4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4 (0x00A8F3B8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5 (0x00A8F3BC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6 (0x00A8F3C0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7 (0x00A8F3C4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n(n) (0x00A8F3C8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0 (0x00A8F3C8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1 (0x00A8F3CC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2 (0x00A8F3D0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3 (0x00A8F3D4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4 (0x00A8F3D8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5 (0x00A8F3DC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6 (0x00A8F3E0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7 (0x00A8F3E4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n(n) (0x00A8F3E8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0 (0x00A8F3E8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1 (0x00A8F3EC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2 (0x00A8F3F0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3 (0x00A8F3F4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4 (0x00A8F3F8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5 (0x00A8F3FC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6 (0x00A8F400)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7 (0x00A8F404)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n(n) (0x00A8F408+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0 (0x00A8F408)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1 (0x00A8F40C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2 (0x00A8F410)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3 (0x00A8F414)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4 (0x00A8F418)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5 (0x00A8F41C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6 (0x00A8F420)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7 (0x00A8F424)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n(n) (0x00A8F428+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0 (0x00A8F428)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1 (0x00A8F42C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2 (0x00A8F430)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3 (0x00A8F434)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4 (0x00A8F438)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5 (0x00A8F43C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6 (0x00A8F440)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7 (0x00A8F444)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n(n) (0x00A8F448+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0 (0x00A8F448)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1 (0x00A8F44C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2 (0x00A8F450)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3 (0x00A8F454)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4 (0x00A8F458)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5 (0x00A8F45C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6 (0x00A8F460)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7 (0x00A8F464)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n(n) (0x00A8F468+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMAX 7    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_ELEM 8    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0 (0x00A8F468)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1 (0x00A8F46C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2 (0x00A8F470)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3 (0x00A8F474)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4 (0x00A8F478)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5 (0x00A8F47C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6 (0x00A8F480)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7 (0x00A8F484)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n(n) (0x00A8F488+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0 (0x00A8F488)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1 (0x00A8F48C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2 (0x00A8F490)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3 (0x00A8F494)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n(n) (0x00A8F498+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0 (0x00A8F498)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1 (0x00A8F49C)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2 (0x00A8F4A0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3 (0x00A8F4A4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n(n) (0x00A8F4A8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0 (0x00A8F4A8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1 (0x00A8F4AC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2 (0x00A8F4B0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3 (0x00A8F4B4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n(n) (0x00A8F4B8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0 (0x00A8F4B8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1 (0x00A8F4BC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2 (0x00A8F4C0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3 (0x00A8F4C4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n(n) (0x00A8F4C8+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0 (0x00A8F4C8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1 (0x00A8F4CC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2 (0x00A8F4D0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3 (0x00A8F4D4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4 (0x00A8F4D8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5 (0x00A8F4DC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6 (0x00A8F4E0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7 (0x00A8F4E4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8 (0x00A8F4E8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9 (0x00A8F4EC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10 (0x00A8F4F0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11 (0x00A8F4F4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12 (0x00A8F4F8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13 (0x00A8F4FC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___S               0

#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n(n) (0x00A8F500+0x4*(n))
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMIN 0    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMAX 1023 
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_ELEM 1024 
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___POR 0x00000000
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___S               0
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0 (0x00A8F500)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1 (0x00A8F504)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2 (0x00A8F508)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3 (0x00A8F50C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4 (0x00A8F510)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5 (0x00A8F514)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6 (0x00A8F518)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7 (0x00A8F51C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8 (0x00A8F520)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9 (0x00A8F524)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10 (0x00A8F528)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11 (0x00A8F52C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12 (0x00A8F530)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13 (0x00A8F534)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14 (0x00A8F538)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15 (0x00A8F53C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16 (0x00A8F540)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17 (0x00A8F544)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18 (0x00A8F548)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19 (0x00A8F54C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20 (0x00A8F550)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21 (0x00A8F554)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22 (0x00A8F558)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23 (0x00A8F55C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24 (0x00A8F560)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25 (0x00A8F564)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26 (0x00A8F568)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27 (0x00A8F56C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28 (0x00A8F570)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29 (0x00A8F574)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30 (0x00A8F578)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31 (0x00A8F57C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32 (0x00A8F580)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33 (0x00A8F584)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34 (0x00A8F588)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35 (0x00A8F58C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36 (0x00A8F590)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37 (0x00A8F594)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38 (0x00A8F598)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39 (0x00A8F59C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40 (0x00A8F5A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41 (0x00A8F5A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42 (0x00A8F5A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43 (0x00A8F5AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44 (0x00A8F5B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45 (0x00A8F5B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46 (0x00A8F5B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47 (0x00A8F5BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48 (0x00A8F5C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49 (0x00A8F5C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50 (0x00A8F5C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51 (0x00A8F5CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52 (0x00A8F5D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53 (0x00A8F5D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54 (0x00A8F5D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55 (0x00A8F5DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56 (0x00A8F5E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57 (0x00A8F5E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58 (0x00A8F5E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59 (0x00A8F5EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60 (0x00A8F5F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61 (0x00A8F5F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62 (0x00A8F5F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63 (0x00A8F5FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64 (0x00A8F600)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65 (0x00A8F604)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66 (0x00A8F608)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67 (0x00A8F60C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68 (0x00A8F610)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69 (0x00A8F614)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70 (0x00A8F618)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71 (0x00A8F61C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72 (0x00A8F620)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73 (0x00A8F624)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74 (0x00A8F628)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75 (0x00A8F62C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76 (0x00A8F630)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77 (0x00A8F634)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78 (0x00A8F638)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79 (0x00A8F63C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80 (0x00A8F640)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81 (0x00A8F644)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82 (0x00A8F648)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83 (0x00A8F64C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84 (0x00A8F650)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85 (0x00A8F654)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86 (0x00A8F658)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87 (0x00A8F65C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88 (0x00A8F660)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89 (0x00A8F664)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90 (0x00A8F668)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91 (0x00A8F66C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92 (0x00A8F670)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93 (0x00A8F674)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94 (0x00A8F678)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95 (0x00A8F67C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96 (0x00A8F680)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97 (0x00A8F684)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98 (0x00A8F688)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99 (0x00A8F68C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100 (0x00A8F690)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101 (0x00A8F694)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102 (0x00A8F698)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103 (0x00A8F69C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104 (0x00A8F6A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105 (0x00A8F6A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106 (0x00A8F6A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107 (0x00A8F6AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108 (0x00A8F6B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109 (0x00A8F6B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110 (0x00A8F6B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111 (0x00A8F6BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112 (0x00A8F6C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113 (0x00A8F6C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114 (0x00A8F6C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115 (0x00A8F6CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116 (0x00A8F6D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117 (0x00A8F6D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118 (0x00A8F6D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119 (0x00A8F6DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120 (0x00A8F6E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121 (0x00A8F6E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122 (0x00A8F6E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123 (0x00A8F6EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124 (0x00A8F6F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125 (0x00A8F6F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126 (0x00A8F6F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127 (0x00A8F6FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128 (0x00A8F700)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129 (0x00A8F704)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130 (0x00A8F708)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131 (0x00A8F70C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132 (0x00A8F710)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133 (0x00A8F714)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134 (0x00A8F718)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135 (0x00A8F71C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136 (0x00A8F720)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137 (0x00A8F724)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138 (0x00A8F728)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139 (0x00A8F72C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140 (0x00A8F730)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141 (0x00A8F734)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142 (0x00A8F738)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143 (0x00A8F73C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144 (0x00A8F740)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145 (0x00A8F744)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146 (0x00A8F748)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147 (0x00A8F74C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148 (0x00A8F750)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149 (0x00A8F754)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150 (0x00A8F758)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151 (0x00A8F75C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152 (0x00A8F760)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153 (0x00A8F764)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154 (0x00A8F768)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155 (0x00A8F76C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156 (0x00A8F770)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157 (0x00A8F774)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158 (0x00A8F778)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159 (0x00A8F77C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160 (0x00A8F780)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161 (0x00A8F784)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162 (0x00A8F788)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163 (0x00A8F78C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164 (0x00A8F790)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165 (0x00A8F794)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166 (0x00A8F798)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167 (0x00A8F79C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168 (0x00A8F7A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169 (0x00A8F7A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170 (0x00A8F7A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171 (0x00A8F7AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172 (0x00A8F7B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173 (0x00A8F7B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174 (0x00A8F7B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175 (0x00A8F7BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176 (0x00A8F7C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177 (0x00A8F7C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178 (0x00A8F7C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179 (0x00A8F7CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180 (0x00A8F7D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181 (0x00A8F7D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182 (0x00A8F7D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183 (0x00A8F7DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184 (0x00A8F7E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185 (0x00A8F7E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186 (0x00A8F7E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187 (0x00A8F7EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188 (0x00A8F7F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189 (0x00A8F7F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190 (0x00A8F7F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191 (0x00A8F7FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192 (0x00A8F800)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193 (0x00A8F804)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194 (0x00A8F808)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195 (0x00A8F80C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196 (0x00A8F810)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197 (0x00A8F814)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198 (0x00A8F818)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199 (0x00A8F81C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200 (0x00A8F820)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201 (0x00A8F824)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202 (0x00A8F828)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203 (0x00A8F82C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204 (0x00A8F830)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205 (0x00A8F834)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206 (0x00A8F838)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207 (0x00A8F83C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208 (0x00A8F840)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209 (0x00A8F844)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210 (0x00A8F848)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211 (0x00A8F84C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212 (0x00A8F850)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213 (0x00A8F854)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214 (0x00A8F858)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215 (0x00A8F85C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216 (0x00A8F860)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217 (0x00A8F864)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218 (0x00A8F868)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219 (0x00A8F86C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220 (0x00A8F870)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221 (0x00A8F874)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222 (0x00A8F878)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223 (0x00A8F87C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224 (0x00A8F880)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225 (0x00A8F884)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226 (0x00A8F888)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227 (0x00A8F88C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228 (0x00A8F890)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229 (0x00A8F894)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230 (0x00A8F898)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231 (0x00A8F89C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232 (0x00A8F8A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233 (0x00A8F8A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234 (0x00A8F8A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235 (0x00A8F8AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236 (0x00A8F8B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237 (0x00A8F8B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238 (0x00A8F8B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239 (0x00A8F8BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240 (0x00A8F8C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241 (0x00A8F8C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242 (0x00A8F8C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243 (0x00A8F8CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244 (0x00A8F8D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245 (0x00A8F8D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246 (0x00A8F8D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247 (0x00A8F8DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248 (0x00A8F8E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249 (0x00A8F8E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250 (0x00A8F8E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251 (0x00A8F8EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252 (0x00A8F8F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253 (0x00A8F8F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254 (0x00A8F8F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255 (0x00A8F8FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256 (0x00A8F900)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257 (0x00A8F904)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258 (0x00A8F908)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259 (0x00A8F90C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260 (0x00A8F910)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261 (0x00A8F914)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262 (0x00A8F918)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263 (0x00A8F91C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264 (0x00A8F920)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265 (0x00A8F924)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266 (0x00A8F928)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267 (0x00A8F92C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268 (0x00A8F930)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269 (0x00A8F934)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270 (0x00A8F938)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271 (0x00A8F93C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272 (0x00A8F940)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273 (0x00A8F944)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274 (0x00A8F948)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275 (0x00A8F94C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276 (0x00A8F950)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277 (0x00A8F954)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278 (0x00A8F958)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279 (0x00A8F95C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280 (0x00A8F960)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281 (0x00A8F964)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282 (0x00A8F968)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283 (0x00A8F96C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284 (0x00A8F970)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285 (0x00A8F974)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286 (0x00A8F978)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287 (0x00A8F97C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288 (0x00A8F980)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289 (0x00A8F984)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290 (0x00A8F988)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291 (0x00A8F98C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292 (0x00A8F990)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293 (0x00A8F994)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294 (0x00A8F998)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295 (0x00A8F99C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296 (0x00A8F9A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297 (0x00A8F9A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298 (0x00A8F9A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299 (0x00A8F9AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300 (0x00A8F9B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301 (0x00A8F9B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302 (0x00A8F9B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303 (0x00A8F9BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304 (0x00A8F9C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305 (0x00A8F9C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306 (0x00A8F9C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307 (0x00A8F9CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308 (0x00A8F9D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309 (0x00A8F9D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310 (0x00A8F9D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311 (0x00A8F9DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312 (0x00A8F9E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313 (0x00A8F9E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314 (0x00A8F9E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315 (0x00A8F9EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316 (0x00A8F9F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317 (0x00A8F9F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318 (0x00A8F9F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319 (0x00A8F9FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320 (0x00A8FA00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321 (0x00A8FA04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322 (0x00A8FA08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323 (0x00A8FA0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324 (0x00A8FA10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325 (0x00A8FA14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326 (0x00A8FA18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327 (0x00A8FA1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328 (0x00A8FA20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329 (0x00A8FA24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330 (0x00A8FA28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331 (0x00A8FA2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332 (0x00A8FA30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333 (0x00A8FA34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334 (0x00A8FA38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335 (0x00A8FA3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336 (0x00A8FA40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337 (0x00A8FA44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338 (0x00A8FA48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339 (0x00A8FA4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340 (0x00A8FA50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341 (0x00A8FA54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342 (0x00A8FA58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343 (0x00A8FA5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344 (0x00A8FA60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345 (0x00A8FA64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346 (0x00A8FA68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347 (0x00A8FA6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348 (0x00A8FA70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349 (0x00A8FA74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350 (0x00A8FA78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351 (0x00A8FA7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352 (0x00A8FA80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353 (0x00A8FA84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354 (0x00A8FA88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355 (0x00A8FA8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356 (0x00A8FA90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357 (0x00A8FA94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358 (0x00A8FA98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359 (0x00A8FA9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360 (0x00A8FAA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361 (0x00A8FAA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362 (0x00A8FAA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363 (0x00A8FAAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364 (0x00A8FAB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365 (0x00A8FAB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366 (0x00A8FAB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367 (0x00A8FABC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368 (0x00A8FAC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369 (0x00A8FAC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370 (0x00A8FAC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371 (0x00A8FACC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372 (0x00A8FAD0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373 (0x00A8FAD4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374 (0x00A8FAD8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375 (0x00A8FADC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376 (0x00A8FAE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377 (0x00A8FAE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378 (0x00A8FAE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379 (0x00A8FAEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380 (0x00A8FAF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381 (0x00A8FAF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382 (0x00A8FAF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383 (0x00A8FAFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384 (0x00A8FB00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385 (0x00A8FB04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386 (0x00A8FB08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387 (0x00A8FB0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388 (0x00A8FB10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389 (0x00A8FB14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390 (0x00A8FB18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391 (0x00A8FB1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392 (0x00A8FB20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393 (0x00A8FB24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394 (0x00A8FB28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395 (0x00A8FB2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396 (0x00A8FB30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397 (0x00A8FB34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398 (0x00A8FB38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399 (0x00A8FB3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400 (0x00A8FB40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401 (0x00A8FB44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402 (0x00A8FB48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403 (0x00A8FB4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404 (0x00A8FB50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405 (0x00A8FB54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406 (0x00A8FB58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407 (0x00A8FB5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408 (0x00A8FB60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409 (0x00A8FB64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410 (0x00A8FB68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411 (0x00A8FB6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412 (0x00A8FB70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413 (0x00A8FB74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414 (0x00A8FB78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415 (0x00A8FB7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416 (0x00A8FB80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417 (0x00A8FB84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418 (0x00A8FB88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419 (0x00A8FB8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420 (0x00A8FB90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421 (0x00A8FB94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422 (0x00A8FB98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423 (0x00A8FB9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424 (0x00A8FBA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425 (0x00A8FBA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426 (0x00A8FBA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427 (0x00A8FBAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428 (0x00A8FBB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429 (0x00A8FBB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430 (0x00A8FBB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431 (0x00A8FBBC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432 (0x00A8FBC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433 (0x00A8FBC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434 (0x00A8FBC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435 (0x00A8FBCC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436 (0x00A8FBD0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437 (0x00A8FBD4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438 (0x00A8FBD8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439 (0x00A8FBDC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440 (0x00A8FBE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441 (0x00A8FBE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442 (0x00A8FBE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443 (0x00A8FBEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444 (0x00A8FBF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445 (0x00A8FBF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446 (0x00A8FBF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447 (0x00A8FBFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448 (0x00A8FC00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449 (0x00A8FC04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450 (0x00A8FC08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451 (0x00A8FC0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452 (0x00A8FC10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453 (0x00A8FC14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454 (0x00A8FC18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455 (0x00A8FC1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456 (0x00A8FC20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457 (0x00A8FC24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458 (0x00A8FC28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459 (0x00A8FC2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460 (0x00A8FC30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461 (0x00A8FC34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462 (0x00A8FC38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463 (0x00A8FC3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464 (0x00A8FC40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465 (0x00A8FC44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466 (0x00A8FC48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467 (0x00A8FC4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468 (0x00A8FC50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469 (0x00A8FC54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470 (0x00A8FC58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471 (0x00A8FC5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472 (0x00A8FC60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473 (0x00A8FC64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474 (0x00A8FC68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475 (0x00A8FC6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476 (0x00A8FC70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477 (0x00A8FC74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478 (0x00A8FC78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479 (0x00A8FC7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480 (0x00A8FC80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481 (0x00A8FC84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482 (0x00A8FC88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483 (0x00A8FC8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484 (0x00A8FC90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485 (0x00A8FC94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486 (0x00A8FC98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487 (0x00A8FC9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488 (0x00A8FCA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489 (0x00A8FCA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490 (0x00A8FCA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491 (0x00A8FCAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492 (0x00A8FCB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493 (0x00A8FCB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494 (0x00A8FCB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495 (0x00A8FCBC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496 (0x00A8FCC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497 (0x00A8FCC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498 (0x00A8FCC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499 (0x00A8FCCC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500 (0x00A8FCD0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501 (0x00A8FCD4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502 (0x00A8FCD8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503 (0x00A8FCDC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504 (0x00A8FCE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505 (0x00A8FCE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506 (0x00A8FCE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507 (0x00A8FCEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508 (0x00A8FCF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509 (0x00A8FCF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510 (0x00A8FCF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511 (0x00A8FCFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512 (0x00A8FD00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513 (0x00A8FD04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514 (0x00A8FD08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515 (0x00A8FD0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516 (0x00A8FD10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517 (0x00A8FD14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518 (0x00A8FD18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519 (0x00A8FD1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520 (0x00A8FD20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521 (0x00A8FD24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522 (0x00A8FD28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523 (0x00A8FD2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524 (0x00A8FD30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525 (0x00A8FD34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526 (0x00A8FD38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527 (0x00A8FD3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528 (0x00A8FD40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529 (0x00A8FD44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530 (0x00A8FD48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531 (0x00A8FD4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532 (0x00A8FD50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533 (0x00A8FD54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534 (0x00A8FD58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535 (0x00A8FD5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536 (0x00A8FD60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537 (0x00A8FD64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538 (0x00A8FD68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539 (0x00A8FD6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540 (0x00A8FD70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541 (0x00A8FD74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542 (0x00A8FD78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543 (0x00A8FD7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544 (0x00A8FD80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545 (0x00A8FD84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546 (0x00A8FD88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547 (0x00A8FD8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548 (0x00A8FD90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549 (0x00A8FD94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550 (0x00A8FD98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551 (0x00A8FD9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552 (0x00A8FDA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553 (0x00A8FDA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554 (0x00A8FDA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555 (0x00A8FDAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556 (0x00A8FDB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557 (0x00A8FDB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558 (0x00A8FDB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559 (0x00A8FDBC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560 (0x00A8FDC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561 (0x00A8FDC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562 (0x00A8FDC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563 (0x00A8FDCC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564 (0x00A8FDD0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565 (0x00A8FDD4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566 (0x00A8FDD8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567 (0x00A8FDDC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568 (0x00A8FDE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569 (0x00A8FDE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570 (0x00A8FDE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571 (0x00A8FDEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572 (0x00A8FDF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573 (0x00A8FDF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574 (0x00A8FDF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575 (0x00A8FDFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576 (0x00A8FE00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577 (0x00A8FE04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578 (0x00A8FE08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579 (0x00A8FE0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580 (0x00A8FE10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581 (0x00A8FE14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582 (0x00A8FE18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583 (0x00A8FE1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584 (0x00A8FE20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585 (0x00A8FE24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586 (0x00A8FE28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587 (0x00A8FE2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588 (0x00A8FE30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589 (0x00A8FE34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590 (0x00A8FE38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591 (0x00A8FE3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592 (0x00A8FE40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593 (0x00A8FE44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594 (0x00A8FE48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595 (0x00A8FE4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596 (0x00A8FE50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597 (0x00A8FE54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598 (0x00A8FE58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599 (0x00A8FE5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600 (0x00A8FE60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601 (0x00A8FE64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602 (0x00A8FE68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603 (0x00A8FE6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604 (0x00A8FE70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605 (0x00A8FE74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606 (0x00A8FE78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607 (0x00A8FE7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608 (0x00A8FE80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609 (0x00A8FE84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610 (0x00A8FE88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611 (0x00A8FE8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612 (0x00A8FE90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613 (0x00A8FE94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614 (0x00A8FE98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615 (0x00A8FE9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616 (0x00A8FEA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617 (0x00A8FEA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618 (0x00A8FEA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619 (0x00A8FEAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620 (0x00A8FEB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621 (0x00A8FEB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622 (0x00A8FEB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623 (0x00A8FEBC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624 (0x00A8FEC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625 (0x00A8FEC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626 (0x00A8FEC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627 (0x00A8FECC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628 (0x00A8FED0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629 (0x00A8FED4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630 (0x00A8FED8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631 (0x00A8FEDC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632 (0x00A8FEE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633 (0x00A8FEE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634 (0x00A8FEE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635 (0x00A8FEEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636 (0x00A8FEF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637 (0x00A8FEF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638 (0x00A8FEF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639 (0x00A8FEFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640 (0x00A8FF00)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641 (0x00A8FF04)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642 (0x00A8FF08)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643 (0x00A8FF0C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644 (0x00A8FF10)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645 (0x00A8FF14)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646 (0x00A8FF18)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647 (0x00A8FF1C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648 (0x00A8FF20)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649 (0x00A8FF24)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650 (0x00A8FF28)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651 (0x00A8FF2C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652 (0x00A8FF30)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653 (0x00A8FF34)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654 (0x00A8FF38)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655 (0x00A8FF3C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656 (0x00A8FF40)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657 (0x00A8FF44)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658 (0x00A8FF48)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659 (0x00A8FF4C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660 (0x00A8FF50)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661 (0x00A8FF54)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662 (0x00A8FF58)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663 (0x00A8FF5C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664 (0x00A8FF60)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665 (0x00A8FF64)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666 (0x00A8FF68)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667 (0x00A8FF6C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668 (0x00A8FF70)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669 (0x00A8FF74)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670 (0x00A8FF78)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671 (0x00A8FF7C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672 (0x00A8FF80)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673 (0x00A8FF84)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674 (0x00A8FF88)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675 (0x00A8FF8C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676 (0x00A8FF90)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677 (0x00A8FF94)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678 (0x00A8FF98)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679 (0x00A8FF9C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680 (0x00A8FFA0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681 (0x00A8FFA4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682 (0x00A8FFA8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683 (0x00A8FFAC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684 (0x00A8FFB0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685 (0x00A8FFB4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686 (0x00A8FFB8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687 (0x00A8FFBC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688 (0x00A8FFC0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689 (0x00A8FFC4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690 (0x00A8FFC8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691 (0x00A8FFCC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692 (0x00A8FFD0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693 (0x00A8FFD4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694 (0x00A8FFD8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695 (0x00A8FFDC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696 (0x00A8FFE0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697 (0x00A8FFE4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698 (0x00A8FFE8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699 (0x00A8FFEC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700 (0x00A8FFF0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701 (0x00A8FFF4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702 (0x00A8FFF8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703 (0x00A8FFFC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704 (0x00A90000)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705 (0x00A90004)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706 (0x00A90008)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707 (0x00A9000C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708 (0x00A90010)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709 (0x00A90014)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710 (0x00A90018)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711 (0x00A9001C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712 (0x00A90020)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713 (0x00A90024)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714 (0x00A90028)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715 (0x00A9002C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716 (0x00A90030)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717 (0x00A90034)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718 (0x00A90038)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719 (0x00A9003C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720 (0x00A90040)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721 (0x00A90044)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722 (0x00A90048)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723 (0x00A9004C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724 (0x00A90050)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725 (0x00A90054)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726 (0x00A90058)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727 (0x00A9005C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728 (0x00A90060)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729 (0x00A90064)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730 (0x00A90068)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731 (0x00A9006C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732 (0x00A90070)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733 (0x00A90074)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734 (0x00A90078)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735 (0x00A9007C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736 (0x00A90080)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737 (0x00A90084)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738 (0x00A90088)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739 (0x00A9008C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740 (0x00A90090)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741 (0x00A90094)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742 (0x00A90098)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743 (0x00A9009C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744 (0x00A900A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745 (0x00A900A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746 (0x00A900A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747 (0x00A900AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748 (0x00A900B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749 (0x00A900B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750 (0x00A900B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751 (0x00A900BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752 (0x00A900C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753 (0x00A900C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754 (0x00A900C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755 (0x00A900CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756 (0x00A900D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757 (0x00A900D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758 (0x00A900D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759 (0x00A900DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760 (0x00A900E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761 (0x00A900E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762 (0x00A900E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763 (0x00A900EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764 (0x00A900F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765 (0x00A900F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766 (0x00A900F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767 (0x00A900FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768 (0x00A90100)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769 (0x00A90104)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770 (0x00A90108)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771 (0x00A9010C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772 (0x00A90110)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773 (0x00A90114)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774 (0x00A90118)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775 (0x00A9011C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776 (0x00A90120)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777 (0x00A90124)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778 (0x00A90128)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779 (0x00A9012C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780 (0x00A90130)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781 (0x00A90134)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782 (0x00A90138)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783 (0x00A9013C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784 (0x00A90140)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785 (0x00A90144)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786 (0x00A90148)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787 (0x00A9014C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788 (0x00A90150)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789 (0x00A90154)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790 (0x00A90158)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791 (0x00A9015C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792 (0x00A90160)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793 (0x00A90164)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794 (0x00A90168)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795 (0x00A9016C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796 (0x00A90170)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797 (0x00A90174)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798 (0x00A90178)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799 (0x00A9017C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800 (0x00A90180)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801 (0x00A90184)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802 (0x00A90188)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803 (0x00A9018C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804 (0x00A90190)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805 (0x00A90194)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806 (0x00A90198)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807 (0x00A9019C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808 (0x00A901A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809 (0x00A901A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810 (0x00A901A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811 (0x00A901AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812 (0x00A901B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813 (0x00A901B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814 (0x00A901B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815 (0x00A901BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816 (0x00A901C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817 (0x00A901C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818 (0x00A901C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819 (0x00A901CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820 (0x00A901D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821 (0x00A901D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822 (0x00A901D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823 (0x00A901DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824 (0x00A901E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825 (0x00A901E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826 (0x00A901E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827 (0x00A901EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828 (0x00A901F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829 (0x00A901F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830 (0x00A901F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831 (0x00A901FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832 (0x00A90200)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833 (0x00A90204)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834 (0x00A90208)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835 (0x00A9020C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836 (0x00A90210)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837 (0x00A90214)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838 (0x00A90218)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839 (0x00A9021C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840 (0x00A90220)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841 (0x00A90224)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842 (0x00A90228)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843 (0x00A9022C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844 (0x00A90230)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845 (0x00A90234)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846 (0x00A90238)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847 (0x00A9023C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848 (0x00A90240)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849 (0x00A90244)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850 (0x00A90248)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851 (0x00A9024C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852 (0x00A90250)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853 (0x00A90254)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854 (0x00A90258)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855 (0x00A9025C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856 (0x00A90260)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857 (0x00A90264)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858 (0x00A90268)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859 (0x00A9026C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860 (0x00A90270)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861 (0x00A90274)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862 (0x00A90278)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863 (0x00A9027C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864 (0x00A90280)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865 (0x00A90284)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866 (0x00A90288)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867 (0x00A9028C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868 (0x00A90290)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869 (0x00A90294)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870 (0x00A90298)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871 (0x00A9029C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872 (0x00A902A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873 (0x00A902A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874 (0x00A902A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875 (0x00A902AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876 (0x00A902B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877 (0x00A902B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878 (0x00A902B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879 (0x00A902BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880 (0x00A902C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881 (0x00A902C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882 (0x00A902C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883 (0x00A902CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884 (0x00A902D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885 (0x00A902D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886 (0x00A902D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887 (0x00A902DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888 (0x00A902E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889 (0x00A902E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890 (0x00A902E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891 (0x00A902EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892 (0x00A902F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893 (0x00A902F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894 (0x00A902F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895 (0x00A902FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896 (0x00A90300)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897 (0x00A90304)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898 (0x00A90308)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899 (0x00A9030C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900 (0x00A90310)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901 (0x00A90314)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902 (0x00A90318)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903 (0x00A9031C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904 (0x00A90320)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905 (0x00A90324)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906 (0x00A90328)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907 (0x00A9032C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908 (0x00A90330)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909 (0x00A90334)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910 (0x00A90338)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911 (0x00A9033C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912 (0x00A90340)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913 (0x00A90344)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914 (0x00A90348)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915 (0x00A9034C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916 (0x00A90350)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917 (0x00A90354)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918 (0x00A90358)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919 (0x00A9035C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920 (0x00A90360)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921 (0x00A90364)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922 (0x00A90368)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923 (0x00A9036C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924 (0x00A90370)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925 (0x00A90374)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926 (0x00A90378)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927 (0x00A9037C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928 (0x00A90380)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929 (0x00A90384)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930 (0x00A90388)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931 (0x00A9038C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932 (0x00A90390)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933 (0x00A90394)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934 (0x00A90398)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935 (0x00A9039C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936 (0x00A903A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937 (0x00A903A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938 (0x00A903A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939 (0x00A903AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940 (0x00A903B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941 (0x00A903B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942 (0x00A903B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943 (0x00A903BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944 (0x00A903C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945 (0x00A903C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946 (0x00A903C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947 (0x00A903CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948 (0x00A903D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949 (0x00A903D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950 (0x00A903D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951 (0x00A903DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952 (0x00A903E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953 (0x00A903E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954 (0x00A903E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955 (0x00A903EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956 (0x00A903F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957 (0x00A903F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958 (0x00A903F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959 (0x00A903FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960 (0x00A90400)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961 (0x00A90404)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962 (0x00A90408)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963 (0x00A9040C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964 (0x00A90410)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965 (0x00A90414)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966 (0x00A90418)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967 (0x00A9041C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968 (0x00A90420)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969 (0x00A90424)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970 (0x00A90428)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971 (0x00A9042C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972 (0x00A90430)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973 (0x00A90434)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974 (0x00A90438)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975 (0x00A9043C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976 (0x00A90440)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977 (0x00A90444)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978 (0x00A90448)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979 (0x00A9044C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980 (0x00A90450)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981 (0x00A90454)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982 (0x00A90458)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983 (0x00A9045C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984 (0x00A90460)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985 (0x00A90464)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986 (0x00A90468)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987 (0x00A9046C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988 (0x00A90470)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989 (0x00A90474)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990 (0x00A90478)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991 (0x00A9047C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992 (0x00A90480)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993 (0x00A90484)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994 (0x00A90488)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995 (0x00A9048C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996 (0x00A90490)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997 (0x00A90494)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998 (0x00A90498)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999 (0x00A9049C)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000 (0x00A904A0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001 (0x00A904A4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002 (0x00A904A8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003 (0x00A904AC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004 (0x00A904B0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005 (0x00A904B4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006 (0x00A904B8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007 (0x00A904BC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008 (0x00A904C0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009 (0x00A904C4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010 (0x00A904C8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011 (0x00A904CC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012 (0x00A904D0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013 (0x00A904D4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014 (0x00A904D8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015 (0x00A904DC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016 (0x00A904E0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017 (0x00A904E4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018 (0x00A904E8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019 (0x00A904EC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020 (0x00A904F0)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021 (0x00A904F4)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022 (0x00A904F8)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___S               0
#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023 (0x00A904FC)
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___S               0

#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE         (0x00A90500)
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___POR 0x00000000
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___POR 0x0000
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___S               0
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___M  0x0000FFFF   
#define   WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___S                0

#define WMAC0_TXPCU_R0_PHY_ACK_STATUS             (0x00A90504)
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS___POR    0x00000000
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___POR 0x0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___M 0x00004000
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___S              14
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___M 0x00002000
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___S              13
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___M 0x00001000
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___S              12
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___M 0x00000800
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___S              11
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___M 0x00000400
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___S              10
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___M 0x00000200
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___S               9
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___M 0x00000100
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___S               8
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___M 0x00000080
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___S               7
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___M 0x00000040
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___S               6
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___M 0x00000020
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___S               5
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___M 0x00000010
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___S               4
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___M 0x00000008
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___S               3
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___M 0x00000004
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___S               2
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___M 0x00000002
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___S               1
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___M 0x00000001
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___S               0
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS___M      0x00007FFF   
#define   WMAC0_TXPCU_R0_PHY_ACK_STATUS___S                    0

#define WMAC0_TXPCU_R0_ABORT_REQ_ACK              (0x00A90508)
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK___RWC        QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK___POR     0x00000030
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___POR 0x0030
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___S               0
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK___M       0x0000FFFF   
#define   WMAC0_TXPCU_R0_ABORT_REQ_ACK___S                     0

#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE        (0x00A9050C)
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___RWC  QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___POR 0x01000100
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___POR 0x0100
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___POR 0x0100
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___S              16
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___S               0
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___S               0

#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE      (0x00A90510)
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___POR 0x01000100
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___POR 0x0100
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___POR 0x0100
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___S              16
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___S               0
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___S               0

#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE           (0x00A90514)
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___RWC     QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___POR  0x00000100
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___POR 0x0100
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___S               0
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___M    0x0000FFFF   
#define   WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___S                  0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0  (0x00A90518)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1  (0x00A9051C)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2  (0x00A90520)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3  (0x00A90524)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4  (0x00A90528)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5  (0x00A9052C)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6  (0x00A90530)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7  (0x00A90534)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8  (0x00A90538)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9  (0x00A9053C)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10 (0x00A90540)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11 (0x00A90544)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12 (0x00A90548)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13 (0x00A9054C)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14 (0x00A90550)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___S               0

#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15 (0x00A90554)
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___S               0
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___S               0

#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK         (0x00A90558)
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___POR 0x00000000
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___POR 0x0
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___POR 0x0
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___POR 0x0
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___M 0x00000004
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___S               2
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___M 0x00000002
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___S               1
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___M 0x00000001
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___S               0
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___M  0x00000007   
#define   WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___S                0

#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP   (0x00A9055C)
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___POR 0x00000000
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___POR 0x000000
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___M 0x00FFFFFF
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___S               0
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___M 0x00FFFFFF   
#define   WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___S               0

#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP (0x00A90560)
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___POR 0x00000000
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___POR 0x0
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___POR 0x00000
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___M 0x00020000
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___S              17
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___M 0x0001FFFF
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___S               0
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___M 0x0003FFFF   
#define   WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___S               0

#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0 (0x00A90564)
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___S               0
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___S               0

#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32 (0x00A90568)
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___S               0
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___S               0

#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9056C)
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___S               0
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___S               0

#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90570)
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___S               0
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___S               0

#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0 (0x00A90574)
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___S               0
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___S               0

#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32 (0x00A90578)
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___S               0
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___S               0

#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9057C)
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___S               0
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___S               0

#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90580)
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___S               0
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___S               0

#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0 (0x00A90588)
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___POR 0x000000FF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___POR 0x0000
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___POR 0x00FF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___M 0xFFFF0000
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___S              16
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___S               0
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___S               0

#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1 (0x00A9058C)
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___POR 0x000000FF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___POR 0x0
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___POR 0x00FF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___M 0x00010000
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___S              16
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___S               0
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___M 0x0001FFFF   
#define   WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___S               0

#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1         (0x00A90590)
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___POR 0x00249249
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___M 0x00FC0000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___S              18
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___M 0x0003F000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___S              12
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___M 0x00000FC0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___S               6
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___M 0x0000003F
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___S               0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___M  0x00FFFFFF   
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___S                0

#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2         (0x00A90594)
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___POR 0x00249249
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___POR 0x09
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___M 0x00FC0000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___S              18
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___M 0x0003F000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___S              12
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___M 0x00000FC0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___S               6
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___M 0x0000003F
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___S               0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___M  0x00FFFFFF   
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___S                0

#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3         (0x00A90598)
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___POR 0x01800000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___POR 0x3
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___POR 0x000000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___M 0x01800000
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___S              23
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___M 0x007FFFFF
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___S               0
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___M  0x01FFFFFF   
#define   WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___S                0

#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT             (0x00A9059C)
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___POR    0x00003019
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___POR 0x30
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___POR 0x19
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___M 0x0000FF00
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___S               8
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___M 0x000000FF
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___S               0
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___M      0x0000FFFF   
#define   WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___S                    0

#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY        (0x00A905A0)
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___RWC  QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___POR 0x15001E00
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___POR 0x15
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___POR 0x00
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___POR 0x1E
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___POR 0x00
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___M 0xFF000000
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___S              24
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___M 0x00FF0000
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___S              16
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___M 0x0000FF00
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___S               8
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___M 0x000000FF
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___S               0
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n(n) (0x00A905A4+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0 (0x00A905A4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1 (0x00A905A8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2 (0x00A905AC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3 (0x00A905B0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n(n) (0x00A905B4+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMAX 3    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_ELEM 4    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0 (0x00A905B4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1 (0x00A905B8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2 (0x00A905BC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3 (0x00A905C0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___S               0

#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n(n) (0x00A905C4+0x4*(n))
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMIN 0    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMAX 13   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_ELEM 14   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___S               0
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0 (0x00A905C4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1 (0x00A905C8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2 (0x00A905CC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3 (0x00A905D0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4 (0x00A905D4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5 (0x00A905D8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6 (0x00A905DC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7 (0x00A905E0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8 (0x00A905E4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9 (0x00A905E8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10 (0x00A905EC)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11 (0x00A905F0)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12 (0x00A905F4)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___S               0
#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13 (0x00A905F8)
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___S               0

#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL       (0x00A905FC)
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___POR 0x00000000
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___POR 0x0
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___M 0x00000001
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___S               0
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___M 0x00000001   
#define   WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___S               0

#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL (0x00A90600)
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___POR 0x00000000
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___POR 0x0
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___M 0x00000001
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___S               0
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___M 0x00000001   
#define   WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___S               0

#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL      (0x00A90604)
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___POR 0x00000002
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___POR 0x0
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___POR 0x02
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___M 0x00000060
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___S               5
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___M 0x0000001F
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___S               0
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___M 0x0000007F   
#define   WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___S               0

#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL         (0x00A90608)
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___RWC   QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___POR 0x00000003
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___POR 0x00000003
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___S               0
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___M  0xFFFFFFFF   
#define   WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___S                0

#define WMAC0_TXPCU_R0_SPR_FLOPS                  (0x00A906CC)
#define   WMAC0_TXPCU_R0_SPR_FLOPS___RWC            QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_SPR_FLOPS___POR         0x00000000
#define   WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___POR 0x0000
#define   WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___M 0x0000FFFF
#define   WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___S               0
#define   WMAC0_TXPCU_R0_SPR_FLOPS___M           0x0000FFFF   
#define   WMAC0_TXPCU_R0_SPR_FLOPS___S                         0

#define WMAC0_TXPCU_R0_FLUSH_HANDLER              (0x00A906D0)
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER___RWC        QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER___POR     0x000001F0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___POR 0x1
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___POR 0xF
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___POR 0x0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___POR 0x0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___POR 0x0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___POR 0x0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___M 0x00000100
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___S               8
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___M 0x000000F0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___S               4
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___M 0x00000008
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___S               3
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___M 0x00000004
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___S               2
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___M 0x00000002
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___S               1
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___M 0x00000001
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___S               0
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER___M       0x000001FF   
#define   WMAC0_TXPCU_R0_FLUSH_HANDLER___S                     0

#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP            (0x00A906D4)
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___RWC      QCSR_REG_RW    
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___POR   0x00FAC688
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___POR 0x7
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___POR 0x6
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___POR 0x5
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___POR 0x4
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___POR 0x3
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___POR 0x2
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___POR 0x1
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___POR 0x0
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___M 0x00E00000
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___S              21
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___M 0x001C0000
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___S              18
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___M 0x00038000
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___S              15
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___M 0x00007000
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___S              12
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___M 0x00000E00
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___S               9
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___M 0x000001C0
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___S               6
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___M 0x00000038
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___S               3
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___M 0x00000007
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___S               0
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___M     0x00FFFFFF   
#define   WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___S                   0

#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL       (0x00A91584)
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___POR 0x00000000
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___POR 0x0
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___POR 0x0000
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___M 0x00010000
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___S              16
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___M 0x0000FFFF
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___S               0
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___M 0x0001FFFF   
#define   WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___S               0

#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT (0x00A9160C)
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___S              16
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___S               8
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___S               0
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___M 0x00FFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT (0x00A91610)
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___S               8
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___S               0
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___M 0x0000FFFF   
#define   WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT  (0x00A91614)
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___S               8
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___S               0
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___M 0x0000FFFF   
#define   WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT    (0x00A91618)
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_STATE                (0x00A9161C)
#define   WMAC0_TXPCU_R1_DEBUG_STATE___RWC          QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_STATE___POR       0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___M 0x3C000000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___S              26
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___M 0x03C00000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___S              22
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___M 0x00380000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___S              19
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___M 0x00070000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___S              16
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___M 0x0000E000
#define   WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___S              13
#define   WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___M 0x00001C00
#define   WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___S              10
#define   WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___M 0x000003C0
#define   WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___S               6
#define   WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___M 0x0000003F
#define   WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___S               0
#define   WMAC0_TXPCU_R1_DEBUG_STATE___M         0x3FFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_STATE___S                       0

#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0             (0x00A91620)
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0___RWC       QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0___POR    0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_0___S                    0

#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1             (0x00A91624)
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1___RWC       QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1___POR    0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_1___S                    0

#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2             (0x00A91628)
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2___RWC       QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2___POR    0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_2___S                    0

#define WMAC0_TXPCU_R1_TRACEBUS_CTRL              (0x00A9162C)
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL___RWC        QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL___POR     0x00000000
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___POR 0x00000000
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___S               0
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL___M       0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_TRACEBUS_CTRL___S                     0

#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER      (0x00A91630)
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___POR 0x08000000
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___POR 0x08000000
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___S               0

#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER      (0x00A91634)
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___S               0

#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT         (0x00A91638)
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___RWC   QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___M  0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___S                0

#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT         (0x00A9163C)
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___RWC   QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___M  0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___S                0

#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT      (0x00A91640)
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT         (0x00A91644)
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___RWC   QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___M  0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___S                0

#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT      (0x00A91648)
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT         (0x00A9164C)
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___RWC   QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___M  0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___S                0

#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT         (0x00A91650)
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___RWC   QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___M  0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___S                0

#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT     (0x00A91654)
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT (0x00A91658)
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT  (0x00A9165C)
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT (0x00A91660)
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___M 0x000000FF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___S               0

#define WMAC0_TXPCU_R1_EVENTMASK_IX_0             (0x00A91664)
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0___POR    0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___POR 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___S               0
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_0___S                    0

#define WMAC0_TXPCU_R1_EVENTMASK_IX_1             (0x00A91668)
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1___RWC       QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1___POR    0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___POR 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___S               0
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1___M      0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_EVENTMASK_IX_1___S                    0

#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV       (0x00A9166C)
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___POR 0x0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___POR 0x0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___M 0xFFFF0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___M 0x0000FFFF
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___S               0

#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0    (0x00A91670)
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___M 0xFF000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___S               8
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___S               0

#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1    (0x00A91674)
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___M 0xFF000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___S               8
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___S               0

#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2    (0x00A91678)
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___M 0xFF000000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___S               8
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___S               0

#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0    (0x00A9167C)
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___M 0xFF000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___S               8
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___S               0

#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1    (0x00A91680)
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___M 0xFF000000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___M 0x00FF0000
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___M 0x0000FF00
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___S               8
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___M 0x000000FF
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___S               0

#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR            (0x00A91684)
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___RWC      QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___POR   0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___POR 0x0000
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___M 0x0000FFFF
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___M     0x0000FFFF   
#define   WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___S                   0

#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS        (0x00A91688)
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___RWC  QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___M 0x00000100
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___S               8
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___M 0x00000080
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___S               7
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___M 0x00000040
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___S               6
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___M 0x00000020
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___S               5
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___M 0x00000010
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___S               4
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___M 0x00000008
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___S               3
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___M 0x00000004
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___S               2
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___M 0x00000002
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___S               1
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___S               0
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___M 0x000001FF   
#define   WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE   (0x00A9168C)
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___M 0x0000003F
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___M 0x0000003F   
#define   WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___S               0

#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT    (0x00A91690)
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___POR 0x0000
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___POR 0x0000
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___M 0xFFFF0000
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___S              16
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___M 0x0000FFFF
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT    (0x00A91694)
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT   (0x00A91698)
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT (0x00A9169C)
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___S               0

#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL (0x00A916A0)
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___M 0x20000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___S              29
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___M 0x10000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___S              28
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___M 0x08000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___S              27
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___M 0x04000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___S              26
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___M 0x02000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___S              25
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___M 0x01000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___S              24
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___M 0x00800000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___S              23
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___M 0x00400000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___S              22
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___M 0x00200000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___S              21
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___M 0x00100000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___S              20
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___M 0x00080000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___S              19
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___M 0x00040000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___S              18
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___M 0x00020000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___S              17
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___M 0x00010000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___S              16
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___M 0x00008000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___S              15
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___M 0x00004000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___S              14
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___M 0x00002000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___S              13
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___M 0x00001000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___S              12
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___M 0x00000800
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___S              11
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___M 0x00000400
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___S              10
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___M 0x00000200
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___S               9
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___M 0x00000100
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___S               8
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___M 0x00000080
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___S               7
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___M 0x00000040
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___S               6
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___M 0x00000020
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___S               5
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___M 0x00000010
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___S               4
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___M 0x00000008
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___S               3
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___M 0x00000004
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___S               2
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___M 0x00000002
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___S               1
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___M 0x3FFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___S               0

#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS    (0x00A916A4)
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___POR 0x007C0000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___POR 0x1F
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___M 0x007C0000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___S              18
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___M 0x00020000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___S              17
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___M 0x00010000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___S              16
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00008000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___S              15
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00004000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___S              14
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00002000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S              13
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00001000
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S              12
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000800
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S              11
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000400
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___S              10
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000200
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___S               9
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___M 0x00000100
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___S               8
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___M 0x00000080
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___S               7
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___M 0x00000040
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___S               6
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___M 0x00000020
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___S               5
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___M 0x00000010
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___S               4
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___M 0x00000008
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___S               3
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___M 0x00000004
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___S               2
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___M 0x00000002
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___S               1
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___S               0
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___M 0x007FFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK (0x00A916A8)
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___M 0x00004000
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___S              14
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___M 0x00002000
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___S              13
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___M 0x00001000
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___S              12
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___M 0x00000800
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___S              11
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___M 0x00000400
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___S              10
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___M 0x00000200
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___S               9
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___M 0x00000100
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___S               8
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___M 0x00000080
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___S               7
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___M 0x00000040
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___S               6
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000020
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___S               5
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000010
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___S               4
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000008
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___S               3
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___M 0x00000004
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___S               2
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___M 0x00000002
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___S               1
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___S               0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___M 0x00007FFF   
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___S               0

#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS (0x00A916AC)
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___POR 0x0000001F
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___POR 0x1F
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___M 0xFFFFF800
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___S              11
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___M 0x000007E0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___S               5
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___M 0x0000001F
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL (0x00A916B0)
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___POR 0x00100040
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___POR 0x01
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___POR 0x01
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___M 0x03F00000
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___S              20
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___M 0x000FC000
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___S              14
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___M 0x00002000
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___S              13
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___M 0x00001000
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___S              12
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___M 0x00000FC0
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___S               6
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___M 0x0000003F
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___S               0
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___M 0x03FFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___S               0

#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS (0x00A916B4)
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___M 0xF8000000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___S              27
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___M 0x07E00000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___S              21
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___M 0x001FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS (0x00A916B8)
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___M 0xF8000000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___S              27
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___M 0x07E00000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___S              21
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___M 0x001FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS (0x00A916BC)
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___POR 0x00200000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___POR 0x01
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___M 0xF8000000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___S              27
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___M 0x07E00000
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___S              21
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___M 0x001FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS (0x00A916C0)
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___POR 0x00200000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___POR 0x01
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___M 0xF8000000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___S              27
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___M 0x07E00000
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___S              21
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___M 0x001FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___S               0
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS (0x00A916C4)
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x00
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___M 0x1F800000
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___S              23
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___M 0x007FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___S               0
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS (0x00A916C8)
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___POR 0x00800000
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x01
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___POR 0x000000
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___M 0x1F800000
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___S              23
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___M 0x007FFFFF
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___S               0
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___S               0

#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0 (0x00A916D8)
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___S               0

#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1 (0x00A916DC)
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___S               0

#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL     (0x00A916E0)
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___POR 0x0000000
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___M 0xFFFFFFF0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___S               4
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___M 0x0000000E
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___S               1
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___S               0
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___M 0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___S               0

#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER          (0x00A916E4)
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___RWC    QCSR_REG_RO    
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___POR 0x00000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___POR 0x0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___M 0x80000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___S              31
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___M 0x40000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___S              30
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___M 0x20000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___S              29
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___M 0x10000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___S              28
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___M 0x08000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___S              27
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___M 0x04000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___S              26
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___M 0x02000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___S              25
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___M 0x01000000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___S              24
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___M 0x00800000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___S              23
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___M 0x00400000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___S              22
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___M 0x00200000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___S              21
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___M 0x00100000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___S              20
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___M 0x00080000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___S              19
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___M 0x00040000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___S              18
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___M 0x00020000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___S              17
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___M 0x00010000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___S              16
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___M 0x00008000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___S              15
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___M 0x00004000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___S              14
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___M 0x00002000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___S              13
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___M 0x00001000
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___S              12
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___M 0x00000800
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___S              11
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___M 0x00000400
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___S              10
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___M 0x00000200
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___S               9
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___M 0x00000100
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___S               8
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___M 0x00000080
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___S               7
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___M 0x00000040
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___S               6
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___M 0x00000020
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___S               5
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___M 0x00000010
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___S               4
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___M 0x00000008
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___S               3
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___M 0x00000004
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___S               2
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___M 0x00000002
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___S               1
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___M 0x00000001
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___S               0
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___M   0xFFFFFFFF   
#define   WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___S                 0

#define WMAC0_AMPI_R0_TX_SIFS                     (0x00A92000)
#define   WMAC0_AMPI_R0_TX_SIFS___RWC               QCSR_REG_RW    
#define   WMAC0_AMPI_R0_TX_SIFS___POR            0x000004F4
#define   WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___POR 0x04F4
#define   WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___M 0x0000FFFF
#define   WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___S               0
#define   WMAC0_AMPI_R0_TX_SIFS___M              0x0000FFFF   
#define   WMAC0_AMPI_R0_TX_SIFS___S                            0

#define WMAC0_AMPI_R0_CLKGATE_DISABLE             (0x00A92004)
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE___RWC       QCSR_REG_RW    
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE___POR    0x00000000
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___POR 0x0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___M 0x00000100
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___S               8
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___M 0x00000080
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___S               7
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___M 0x00000040
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___S               6
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x00000020
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S               5
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___M 0x00000010
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___S               4
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___M 0x00000008
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___S               3
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___M 0x00000004
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___S               2
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___M 0x00000002
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___S               1
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___M 0x00000001
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___S               0
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE___M      0x000001FF   
#define   WMAC0_AMPI_R0_CLKGATE_DISABLE___S                    0

#define WMAC0_AMPI_R0_FEATURE_DISABLE             (0x00A92008)
#define   WMAC0_AMPI_R0_FEATURE_DISABLE___RWC       QCSR_REG_RW    
#define   WMAC0_AMPI_R0_FEATURE_DISABLE___POR    0x00000060
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___POR 0x00
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___POR 0x1
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___POR 0x1
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___POR 0x0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___M 0x0003F000
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___S              12
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___M 0x00000800
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___S              11
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___M 0x00000400
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___S              10
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___M 0x00000200
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___S               9
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___M 0x00000100
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___S               8
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___M 0x00000080
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___S               7
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___M 0x00000040
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___S               6
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___M 0x00000020
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___S               5
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___M 0x00000008
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___S               3
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___M 0x00000004
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___S               2
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___M 0x00000002
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___S               1
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___M 0x00000001
#define   WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___S               0
#define   WMAC0_AMPI_R0_FEATURE_DISABLE___M      0x0003FFEF   
#define   WMAC0_AMPI_R0_FEATURE_DISABLE___S                    0

#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE       (0x00A9200C)
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___POR 0x00000000
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___POR 0x000000
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___M 0x00FFFFFF
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___S               0
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___M 0x00FFFFFF   
#define   WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___S               0

#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE       (0x00A92010)
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___POR 0x00000000
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___POR 0x000000
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___M 0x00FFFFFF
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___S               0
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___M 0x00FFFFFF   
#define   WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___S               0

#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE (0x00A92014)
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___POR 0x00000000
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___POR 0x0
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___POR 0x0
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___POR 0x0
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___M 0x00000004
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___S               2
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___M 0x00000002
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___S               1
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___M 0x00000001
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___S               0
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___M 0x00000007   
#define   WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___S               0

#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL           (0x00A92018)
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___POR  0x00000000
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___POR 0x0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___POR 0x0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___POR 0x0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___POR 0x0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___POR 0x0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___M 0x00000010
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___S               4
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___M 0x00000008
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___S               3
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___M 0x00000004
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___S               2
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___M 0x00000002
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___S               1
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___M 0x00000001
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___S               0
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___M    0x0000001F   
#define   WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___S                  0

#define WMAC0_AMPI_R0_LOOPBACK_CTRL               (0x00A9201C)
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL___POR      0x00020040
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___POR 0x0
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___POR 0x000
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___POR 0x040
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___POR 0x020
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___POR 0x0
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___M 0x80000000
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___S              31
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___M 0x7FE00000
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___S              21
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___M 0x001FF800
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___S              11
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___M 0x000007FE
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___S               1
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___M 0x00000001
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___S               0
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL___M        0xFFFFFFFF   
#define   WMAC0_AMPI_R0_LOOPBACK_CTRL___S                      0

#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG      (0x00A92020)
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___POR 0x00000000
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___POR 0x0
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___POR 0x0
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___M 0x00000002
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___S               1
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___M 0x00000001
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___S               0
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___M 0x00000003   
#define   WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___S               0

#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n(n) (0x00A93000+0x4*(n))
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_nMIN 0    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_nMAX 1    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_ELEM 2    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___POR 0x00000000
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___POR 0x00000000
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___S               0
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___M 0xFFFFFFFF   
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___S               0
#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0      (0x00A93000)
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0__VAL___S               0
#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1      (0x00A93004)
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1__VAL___S               0

#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n(n) (0x00A93008+0x4*(n))
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_nMIN 0    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_nMAX 1    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_ELEM 2    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___POR 0x00000000
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___POR 0x00000000
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___S               0
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___M  0xFFFFFFFF   
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___S                0
#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0         (0x00A93008)
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0__VAL___S               0
#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1         (0x00A9300C)
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1__VAL___S               0

#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n(n) (0x00A93010+0x4*(n))
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_nMIN 0    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_nMAX 1    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_ELEM 2    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___POR 0x00000000
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___POR 0x00000000
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___S               0
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___M  0xFFFFFFFF   
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___S                0
#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0         (0x00A93010)
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0__VAL___S               0
#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1         (0x00A93014)
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1__VAL___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1__VAL___S               0

#define WMAC0_AMPI_R1_TESTBUS_CTRL                (0x00A93018)
#define   WMAC0_AMPI_R1_TESTBUS_CTRL___RWC          QCSR_REG_RW    
#define   WMAC0_AMPI_R1_TESTBUS_CTRL___POR       0x00000000
#define   WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00000000
#define   WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   WMAC0_AMPI_R1_TESTBUS_CTRL___M         0xFFFFFFFF   
#define   WMAC0_AMPI_R1_TESTBUS_CTRL___S                       0

#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT        (0x00A9301C)
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___RWC  QCSR_REG_RO    
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___POR 0x0000
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___M 0x0000FFFF
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___S               0
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___M 0x0000FFFF   
#define   WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___S               0

#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT        (0x00A93020)
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___RWC  QCSR_REG_RO    
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___POR 0x0000
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___M 0x0000FFFF
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___S               0
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___M 0x0000FFFF   
#define   WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___S               0

#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT       (0x00A93024)
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___RWC QCSR_REG_RO    
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___POR 0x0000
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___M 0x0000FFFF
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___S               0
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___M 0x0000FFFF   
#define   WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___S               0

#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT         (0x00A93028)
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___RWC   QCSR_REG_RO    
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___POR 0x0000
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___M 0x0000FFFF
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___S               0
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___M  0x0000FFFF   
#define   WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___S                0

#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT      (0x00A9302C)
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___RWC QCSR_REG_RO    
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___POR 0x0000
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___M 0x0000FFFF
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___S               0
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___M 0x0000FFFF   
#define   WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___S               0

#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT   (0x00A93030)
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___RWC QCSR_REG_RO    
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___POR 0x00000000
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___POR 0x0000
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___M 0x0000FFFF
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___S               0
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___M 0x0000FFFF   
#define   WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___S               0

#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR (0x00A93034)
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___S               0

#define WMAC0_AMPI_R1_SM_STATES_IX_0              (0x00A93038)
#define   WMAC0_AMPI_R1_SM_STATES_IX_0___RWC        QCSR_REG_RO    
#define   WMAC0_AMPI_R1_SM_STATES_IX_0___POR     0x00000000
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___POR 0x00
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___M 0x80000000
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___S              31
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___M 0x0000003F
#define   WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___S               0
#define   WMAC0_AMPI_R1_SM_STATES_IX_0___M       0x8000003F   
#define   WMAC0_AMPI_R1_SM_STATES_IX_0___S                     0

#define WMAC0_AMPI_R1_SM_STATES_IX_1              (0x00A9303C)
#define   WMAC0_AMPI_R1_SM_STATES_IX_1___RWC        QCSR_REG_RO    
#define   WMAC0_AMPI_R1_SM_STATES_IX_1___POR     0x00000000
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___POR 0x000
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___M 0x80000000
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___S              31
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___M 0x000001FF
#define   WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___S               0
#define   WMAC0_AMPI_R1_SM_STATES_IX_1___M       0x800001FF   
#define   WMAC0_AMPI_R1_SM_STATES_IX_1___S                     0

#define WMAC0_AMPI_R1_EVENTMASK_IX_0              (0x00A93040)
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0___RWC        QCSR_REG_RW    
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0___POR     0x00000000
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___POR 0x00000000
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___S               0
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0___M       0xFFFFFFFF   
#define   WMAC0_AMPI_R1_EVENTMASK_IX_0___S                     0

#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT          (0x00A93044)
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___POR 0x00000000
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___POR 0x0
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___POR 0x0
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___POR 0x0
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___M 0x00000078
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___S               3
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___M 0x00000004
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___S               2
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___M 0x00000003
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___S               0
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___M   0x0000007F   
#define   WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___S                 0

#define WMAC0_AMPI_R1_TESTBUS_LOWER               (0x00A93048)
#define   WMAC0_AMPI_R1_TESTBUS_LOWER___RWC         QCSR_REG_RO    
#define   WMAC0_AMPI_R1_TESTBUS_LOWER___POR      0x00000000
#define   WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___S               0
#define   WMAC0_AMPI_R1_TESTBUS_LOWER___M        0xFFFFFFFF   
#define   WMAC0_AMPI_R1_TESTBUS_LOWER___S                      0

#define WMAC0_AMPI_R1_TESTBUS_UPPER               (0x00A9304C)
#define   WMAC0_AMPI_R1_TESTBUS_UPPER___RWC         QCSR_REG_RO    
#define   WMAC0_AMPI_R1_TESTBUS_UPPER___POR      0x00000000
#define   WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___S               0
#define   WMAC0_AMPI_R1_TESTBUS_UPPER___M        0x000000FF   
#define   WMAC0_AMPI_R1_TESTBUS_UPPER___S                      0

#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL   (0x00A93050)
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER         (0x00A93054)
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___POR 0x00000000
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___POR 0x0000
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___M 0x0000FFFF
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___S               0
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___M  0x0000FFFF   
#define   WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___S                0

#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1           (0x00A9305C)
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1___POR  0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___POR 0x0000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___M 0x00080000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___S              19
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___M 0x00040000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___S              18
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___M 0x00020000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___S              17
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___M 0x00010000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___S              16
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___M 0x00008000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___S              15
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___M 0x00007FFF
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1___M    0x000FFFFF   
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_1___S                  0

#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2           (0x00A93060)
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2___POR  0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___POR 0x0000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___M 0x00008000
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___S              15
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___M 0x00007FFF
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2___M    0x0000FFFF   
#define   WMAC0_AMPI_R1_LOOPBACK_STATUS_2___S                  0

#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1           (0x00A93064)
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___POR  0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___POR 0x00
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___POR 0x0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___M 0x00004000
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___S              14
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___M 0x00002000
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___S              13
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___M 0x00001FE0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___S               5
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___M 0x00000010
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___S               4
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___M 0x00000008
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___S               3
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___M 0x00000007
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___M    0x00007FFF   
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___S                  0

#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2           (0x00A93068)
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___POR  0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___POR 0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___M    0xFFFFFFFF   
#define   WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___S                  0

#define WMAC0_AMPI_R1_CCA_CTRL                    (0x00A9306C)
#define   WMAC0_AMPI_R1_CCA_CTRL___RWC              QCSR_REG_RW    
#define   WMAC0_AMPI_R1_CCA_CTRL___POR           0x00000000
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___POR 0x0000
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___POR 0x0000
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___M 0xFFFF0000
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___S              16
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___M 0x0000FFFF
#define   WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___S               0
#define   WMAC0_AMPI_R1_CCA_CTRL___M             0xFFFFFFFF   
#define   WMAC0_AMPI_R1_CCA_CTRL___S                           0

#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG            (0x00A93070)
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___RWC      QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___POR   0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___POR 0x00
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___POR 0x00
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___M 0x00003FC0
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___S               6
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___M 0x0000003F
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___M     0x00003FFF   
#define   WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___S                   0

#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n(n) (0x00A93074+0x4*(n))
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_nMIN 0    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_nMAX 511  
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_ELEM 512  
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___POR  0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___POR 0x00000000
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___S               0
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___M    0xFFFFFFFF   
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___S                  0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_0           (0x00A93074)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_0___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_0__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_0__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_1           (0x00A93078)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_1___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_1__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_1__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_2           (0x00A9307C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_2___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_2__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_2__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_3           (0x00A93080)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_3___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_3__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_3__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_4           (0x00A93084)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_4___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_4__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_4__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_5           (0x00A93088)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_5___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_5__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_5__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_6           (0x00A9308C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_6___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_6__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_6__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_7           (0x00A93090)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_7___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_7__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_7__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_8           (0x00A93094)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_8___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_8__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_8__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_9           (0x00A93098)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_9___RWC     QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_9__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_9__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_10          (0x00A9309C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_10___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_10__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_10__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_11          (0x00A930A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_11___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_11__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_11__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_12          (0x00A930A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_12___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_12__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_12__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_13          (0x00A930A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_13___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_13__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_13__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_14          (0x00A930AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_14___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_14__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_14__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_15          (0x00A930B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_15___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_15__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_15__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_16          (0x00A930B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_16___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_16__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_16__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_17          (0x00A930B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_17___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_17__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_17__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_18          (0x00A930BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_18___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_18__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_18__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_19          (0x00A930C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_19___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_19__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_19__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_20          (0x00A930C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_20___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_20__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_20__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_21          (0x00A930C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_21___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_21__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_21__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_22          (0x00A930CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_22___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_22__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_22__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_23          (0x00A930D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_23___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_23__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_23__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_24          (0x00A930D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_24___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_24__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_24__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_25          (0x00A930D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_25___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_25__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_25__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_26          (0x00A930DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_26___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_26__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_26__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_27          (0x00A930E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_27___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_27__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_27__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_28          (0x00A930E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_28___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_28__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_28__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_29          (0x00A930E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_29___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_29__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_29__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_30          (0x00A930EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_30___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_30__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_30__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_31          (0x00A930F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_31___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_31__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_31__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_32          (0x00A930F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_32___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_32__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_32__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_33          (0x00A930F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_33___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_33__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_33__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_34          (0x00A930FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_34___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_34__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_34__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_35          (0x00A93100)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_35___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_35__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_35__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_36          (0x00A93104)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_36___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_36__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_36__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_37          (0x00A93108)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_37___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_37__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_37__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_38          (0x00A9310C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_38___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_38__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_38__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_39          (0x00A93110)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_39___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_39__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_39__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_40          (0x00A93114)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_40___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_40__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_40__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_41          (0x00A93118)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_41___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_41__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_41__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_42          (0x00A9311C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_42___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_42__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_42__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_43          (0x00A93120)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_43___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_43__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_43__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_44          (0x00A93124)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_44___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_44__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_44__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_45          (0x00A93128)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_45___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_45__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_45__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_46          (0x00A9312C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_46___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_46__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_46__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_47          (0x00A93130)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_47___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_47__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_47__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_48          (0x00A93134)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_48___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_48__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_48__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_49          (0x00A93138)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_49___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_49__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_49__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_50          (0x00A9313C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_50___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_50__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_50__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_51          (0x00A93140)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_51___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_51__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_51__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_52          (0x00A93144)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_52___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_52__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_52__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_53          (0x00A93148)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_53___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_53__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_53__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_54          (0x00A9314C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_54___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_54__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_54__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_55          (0x00A93150)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_55___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_55__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_55__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_56          (0x00A93154)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_56___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_56__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_56__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_57          (0x00A93158)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_57___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_57__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_57__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_58          (0x00A9315C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_58___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_58__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_58__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_59          (0x00A93160)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_59___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_59__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_59__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_60          (0x00A93164)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_60___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_60__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_60__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_61          (0x00A93168)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_61___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_61__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_61__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_62          (0x00A9316C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_62___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_62__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_62__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_63          (0x00A93170)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_63___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_63__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_63__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_64          (0x00A93174)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_64___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_64__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_64__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_65          (0x00A93178)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_65___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_65__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_65__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_66          (0x00A9317C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_66___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_66__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_66__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_67          (0x00A93180)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_67___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_67__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_67__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_68          (0x00A93184)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_68___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_68__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_68__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_69          (0x00A93188)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_69___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_69__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_69__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_70          (0x00A9318C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_70___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_70__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_70__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_71          (0x00A93190)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_71___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_71__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_71__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_72          (0x00A93194)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_72___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_72__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_72__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_73          (0x00A93198)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_73___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_73__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_73__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_74          (0x00A9319C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_74___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_74__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_74__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_75          (0x00A931A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_75___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_75__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_75__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_76          (0x00A931A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_76___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_76__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_76__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_77          (0x00A931A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_77___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_77__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_77__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_78          (0x00A931AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_78___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_78__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_78__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_79          (0x00A931B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_79___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_79__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_79__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_80          (0x00A931B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_80___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_80__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_80__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_81          (0x00A931B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_81___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_81__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_81__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_82          (0x00A931BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_82___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_82__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_82__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_83          (0x00A931C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_83___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_83__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_83__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_84          (0x00A931C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_84___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_84__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_84__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_85          (0x00A931C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_85___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_85__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_85__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_86          (0x00A931CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_86___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_86__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_86__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_87          (0x00A931D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_87___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_87__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_87__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_88          (0x00A931D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_88___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_88__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_88__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_89          (0x00A931D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_89___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_89__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_89__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_90          (0x00A931DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_90___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_90__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_90__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_91          (0x00A931E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_91___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_91__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_91__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_92          (0x00A931E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_92___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_92__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_92__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_93          (0x00A931E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_93___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_93__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_93__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_94          (0x00A931EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_94___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_94__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_94__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_95          (0x00A931F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_95___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_95__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_95__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_96          (0x00A931F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_96___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_96__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_96__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_97          (0x00A931F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_97___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_97__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_97__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_98          (0x00A931FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_98___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_98__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_98__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_99          (0x00A93200)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_99___RWC    QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_99__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_99__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_100         (0x00A93204)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_100___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_100__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_100__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_101         (0x00A93208)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_101___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_101__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_101__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_102         (0x00A9320C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_102___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_102__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_102__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_103         (0x00A93210)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_103___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_103__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_103__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_104         (0x00A93214)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_104___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_104__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_104__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_105         (0x00A93218)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_105___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_105__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_105__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_106         (0x00A9321C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_106___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_106__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_106__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_107         (0x00A93220)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_107___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_107__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_107__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_108         (0x00A93224)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_108___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_108__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_108__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_109         (0x00A93228)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_109___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_109__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_109__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_110         (0x00A9322C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_110___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_110__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_110__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_111         (0x00A93230)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_111___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_111__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_111__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_112         (0x00A93234)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_112___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_112__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_112__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_113         (0x00A93238)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_113___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_113__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_113__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_114         (0x00A9323C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_114___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_114__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_114__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_115         (0x00A93240)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_115___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_115__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_115__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_116         (0x00A93244)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_116___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_116__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_116__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_117         (0x00A93248)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_117___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_117__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_117__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_118         (0x00A9324C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_118___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_118__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_118__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_119         (0x00A93250)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_119___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_119__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_119__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_120         (0x00A93254)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_120___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_120__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_120__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_121         (0x00A93258)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_121___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_121__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_121__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_122         (0x00A9325C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_122___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_122__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_122__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_123         (0x00A93260)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_123___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_123__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_123__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_124         (0x00A93264)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_124___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_124__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_124__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_125         (0x00A93268)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_125___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_125__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_125__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_126         (0x00A9326C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_126___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_126__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_126__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_127         (0x00A93270)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_127___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_127__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_127__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_128         (0x00A93274)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_128___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_128__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_128__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_129         (0x00A93278)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_129___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_129__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_129__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_130         (0x00A9327C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_130___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_130__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_130__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_131         (0x00A93280)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_131___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_131__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_131__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_132         (0x00A93284)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_132___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_132__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_132__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_133         (0x00A93288)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_133___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_133__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_133__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_134         (0x00A9328C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_134___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_134__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_134__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_135         (0x00A93290)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_135___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_135__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_135__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_136         (0x00A93294)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_136___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_136__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_136__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_137         (0x00A93298)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_137___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_137__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_137__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_138         (0x00A9329C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_138___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_138__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_138__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_139         (0x00A932A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_139___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_139__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_139__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_140         (0x00A932A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_140___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_140__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_140__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_141         (0x00A932A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_141___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_141__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_141__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_142         (0x00A932AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_142___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_142__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_142__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_143         (0x00A932B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_143___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_143__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_143__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_144         (0x00A932B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_144___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_144__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_144__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_145         (0x00A932B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_145___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_145__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_145__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_146         (0x00A932BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_146___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_146__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_146__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_147         (0x00A932C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_147___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_147__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_147__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_148         (0x00A932C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_148___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_148__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_148__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_149         (0x00A932C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_149___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_149__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_149__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_150         (0x00A932CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_150___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_150__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_150__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_151         (0x00A932D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_151___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_151__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_151__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_152         (0x00A932D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_152___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_152__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_152__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_153         (0x00A932D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_153___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_153__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_153__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_154         (0x00A932DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_154___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_154__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_154__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_155         (0x00A932E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_155___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_155__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_155__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_156         (0x00A932E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_156___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_156__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_156__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_157         (0x00A932E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_157___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_157__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_157__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_158         (0x00A932EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_158___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_158__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_158__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_159         (0x00A932F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_159___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_159__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_159__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_160         (0x00A932F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_160___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_160__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_160__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_161         (0x00A932F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_161___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_161__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_161__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_162         (0x00A932FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_162___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_162__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_162__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_163         (0x00A93300)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_163___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_163__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_163__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_164         (0x00A93304)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_164___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_164__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_164__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_165         (0x00A93308)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_165___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_165__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_165__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_166         (0x00A9330C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_166___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_166__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_166__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_167         (0x00A93310)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_167___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_167__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_167__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_168         (0x00A93314)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_168___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_168__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_168__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_169         (0x00A93318)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_169___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_169__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_169__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_170         (0x00A9331C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_170___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_170__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_170__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_171         (0x00A93320)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_171___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_171__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_171__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_172         (0x00A93324)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_172___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_172__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_172__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_173         (0x00A93328)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_173___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_173__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_173__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_174         (0x00A9332C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_174___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_174__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_174__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_175         (0x00A93330)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_175___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_175__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_175__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_176         (0x00A93334)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_176___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_176__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_176__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_177         (0x00A93338)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_177___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_177__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_177__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_178         (0x00A9333C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_178___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_178__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_178__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_179         (0x00A93340)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_179___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_179__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_179__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_180         (0x00A93344)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_180___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_180__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_180__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_181         (0x00A93348)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_181___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_181__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_181__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_182         (0x00A9334C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_182___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_182__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_182__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_183         (0x00A93350)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_183___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_183__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_183__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_184         (0x00A93354)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_184___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_184__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_184__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_185         (0x00A93358)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_185___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_185__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_185__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_186         (0x00A9335C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_186___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_186__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_186__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_187         (0x00A93360)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_187___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_187__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_187__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_188         (0x00A93364)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_188___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_188__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_188__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_189         (0x00A93368)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_189___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_189__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_189__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_190         (0x00A9336C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_190___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_190__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_190__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_191         (0x00A93370)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_191___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_191__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_191__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_192         (0x00A93374)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_192___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_192__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_192__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_193         (0x00A93378)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_193___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_193__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_193__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_194         (0x00A9337C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_194___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_194__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_194__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_195         (0x00A93380)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_195___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_195__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_195__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_196         (0x00A93384)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_196___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_196__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_196__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_197         (0x00A93388)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_197___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_197__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_197__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_198         (0x00A9338C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_198___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_198__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_198__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_199         (0x00A93390)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_199___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_199__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_199__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_200         (0x00A93394)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_200___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_200__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_200__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_201         (0x00A93398)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_201___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_201__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_201__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_202         (0x00A9339C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_202___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_202__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_202__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_203         (0x00A933A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_203___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_203__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_203__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_204         (0x00A933A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_204___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_204__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_204__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_205         (0x00A933A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_205___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_205__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_205__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_206         (0x00A933AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_206___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_206__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_206__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_207         (0x00A933B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_207___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_207__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_207__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_208         (0x00A933B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_208___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_208__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_208__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_209         (0x00A933B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_209___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_209__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_209__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_210         (0x00A933BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_210___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_210__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_210__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_211         (0x00A933C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_211___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_211__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_211__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_212         (0x00A933C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_212___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_212__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_212__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_213         (0x00A933C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_213___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_213__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_213__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_214         (0x00A933CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_214___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_214__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_214__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_215         (0x00A933D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_215___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_215__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_215__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_216         (0x00A933D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_216___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_216__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_216__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_217         (0x00A933D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_217___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_217__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_217__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_218         (0x00A933DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_218___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_218__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_218__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_219         (0x00A933E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_219___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_219__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_219__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_220         (0x00A933E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_220___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_220__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_220__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_221         (0x00A933E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_221___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_221__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_221__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_222         (0x00A933EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_222___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_222__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_222__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_223         (0x00A933F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_223___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_223__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_223__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_224         (0x00A933F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_224___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_224__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_224__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_225         (0x00A933F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_225___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_225__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_225__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_226         (0x00A933FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_226___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_226__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_226__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_227         (0x00A93400)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_227___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_227__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_227__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_228         (0x00A93404)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_228___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_228__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_228__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_229         (0x00A93408)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_229___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_229__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_229__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_230         (0x00A9340C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_230___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_230__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_230__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_231         (0x00A93410)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_231___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_231__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_231__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_232         (0x00A93414)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_232___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_232__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_232__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_233         (0x00A93418)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_233___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_233__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_233__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_234         (0x00A9341C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_234___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_234__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_234__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_235         (0x00A93420)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_235___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_235__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_235__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_236         (0x00A93424)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_236___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_236__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_236__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_237         (0x00A93428)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_237___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_237__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_237__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_238         (0x00A9342C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_238___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_238__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_238__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_239         (0x00A93430)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_239___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_239__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_239__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_240         (0x00A93434)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_240___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_240__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_240__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_241         (0x00A93438)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_241___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_241__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_241__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_242         (0x00A9343C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_242___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_242__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_242__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_243         (0x00A93440)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_243___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_243__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_243__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_244         (0x00A93444)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_244___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_244__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_244__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_245         (0x00A93448)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_245___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_245__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_245__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_246         (0x00A9344C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_246___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_246__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_246__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_247         (0x00A93450)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_247___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_247__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_247__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_248         (0x00A93454)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_248___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_248__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_248__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_249         (0x00A93458)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_249___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_249__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_249__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_250         (0x00A9345C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_250___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_250__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_250__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_251         (0x00A93460)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_251___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_251__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_251__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_252         (0x00A93464)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_252___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_252__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_252__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_253         (0x00A93468)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_253___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_253__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_253__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_254         (0x00A9346C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_254___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_254__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_254__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_255         (0x00A93470)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_255___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_255__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_255__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_256         (0x00A93474)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_256___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_256__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_256__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_257         (0x00A93478)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_257___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_257__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_257__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_258         (0x00A9347C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_258___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_258__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_258__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_259         (0x00A93480)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_259___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_259__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_259__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_260         (0x00A93484)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_260___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_260__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_260__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_261         (0x00A93488)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_261___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_261__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_261__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_262         (0x00A9348C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_262___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_262__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_262__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_263         (0x00A93490)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_263___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_263__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_263__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_264         (0x00A93494)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_264___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_264__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_264__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_265         (0x00A93498)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_265___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_265__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_265__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_266         (0x00A9349C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_266___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_266__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_266__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_267         (0x00A934A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_267___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_267__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_267__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_268         (0x00A934A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_268___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_268__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_268__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_269         (0x00A934A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_269___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_269__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_269__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_270         (0x00A934AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_270___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_270__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_270__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_271         (0x00A934B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_271___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_271__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_271__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_272         (0x00A934B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_272___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_272__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_272__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_273         (0x00A934B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_273___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_273__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_273__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_274         (0x00A934BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_274___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_274__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_274__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_275         (0x00A934C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_275___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_275__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_275__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_276         (0x00A934C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_276___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_276__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_276__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_277         (0x00A934C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_277___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_277__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_277__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_278         (0x00A934CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_278___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_278__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_278__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_279         (0x00A934D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_279___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_279__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_279__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_280         (0x00A934D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_280___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_280__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_280__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_281         (0x00A934D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_281___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_281__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_281__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_282         (0x00A934DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_282___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_282__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_282__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_283         (0x00A934E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_283___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_283__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_283__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_284         (0x00A934E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_284___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_284__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_284__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_285         (0x00A934E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_285___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_285__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_285__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_286         (0x00A934EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_286___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_286__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_286__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_287         (0x00A934F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_287___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_287__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_287__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_288         (0x00A934F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_288___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_288__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_288__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_289         (0x00A934F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_289___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_289__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_289__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_290         (0x00A934FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_290___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_290__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_290__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_291         (0x00A93500)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_291___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_291__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_291__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_292         (0x00A93504)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_292___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_292__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_292__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_293         (0x00A93508)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_293___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_293__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_293__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_294         (0x00A9350C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_294___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_294__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_294__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_295         (0x00A93510)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_295___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_295__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_295__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_296         (0x00A93514)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_296___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_296__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_296__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_297         (0x00A93518)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_297___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_297__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_297__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_298         (0x00A9351C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_298___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_298__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_298__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_299         (0x00A93520)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_299___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_299__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_299__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_300         (0x00A93524)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_300___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_300__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_300__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_301         (0x00A93528)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_301___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_301__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_301__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_302         (0x00A9352C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_302___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_302__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_302__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_303         (0x00A93530)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_303___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_303__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_303__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_304         (0x00A93534)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_304___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_304__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_304__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_305         (0x00A93538)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_305___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_305__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_305__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_306         (0x00A9353C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_306___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_306__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_306__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_307         (0x00A93540)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_307___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_307__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_307__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_308         (0x00A93544)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_308___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_308__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_308__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_309         (0x00A93548)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_309___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_309__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_309__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_310         (0x00A9354C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_310___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_310__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_310__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_311         (0x00A93550)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_311___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_311__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_311__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_312         (0x00A93554)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_312___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_312__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_312__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_313         (0x00A93558)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_313___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_313__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_313__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_314         (0x00A9355C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_314___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_314__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_314__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_315         (0x00A93560)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_315___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_315__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_315__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_316         (0x00A93564)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_316___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_316__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_316__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_317         (0x00A93568)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_317___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_317__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_317__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_318         (0x00A9356C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_318___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_318__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_318__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_319         (0x00A93570)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_319___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_319__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_319__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_320         (0x00A93574)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_320___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_320__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_320__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_321         (0x00A93578)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_321___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_321__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_321__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_322         (0x00A9357C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_322___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_322__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_322__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_323         (0x00A93580)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_323___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_323__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_323__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_324         (0x00A93584)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_324___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_324__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_324__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_325         (0x00A93588)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_325___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_325__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_325__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_326         (0x00A9358C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_326___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_326__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_326__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_327         (0x00A93590)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_327___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_327__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_327__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_328         (0x00A93594)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_328___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_328__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_328__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_329         (0x00A93598)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_329___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_329__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_329__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_330         (0x00A9359C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_330___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_330__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_330__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_331         (0x00A935A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_331___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_331__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_331__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_332         (0x00A935A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_332___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_332__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_332__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_333         (0x00A935A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_333___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_333__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_333__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_334         (0x00A935AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_334___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_334__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_334__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_335         (0x00A935B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_335___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_335__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_335__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_336         (0x00A935B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_336___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_336__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_336__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_337         (0x00A935B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_337___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_337__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_337__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_338         (0x00A935BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_338___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_338__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_338__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_339         (0x00A935C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_339___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_339__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_339__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_340         (0x00A935C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_340___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_340__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_340__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_341         (0x00A935C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_341___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_341__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_341__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_342         (0x00A935CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_342___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_342__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_342__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_343         (0x00A935D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_343___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_343__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_343__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_344         (0x00A935D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_344___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_344__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_344__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_345         (0x00A935D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_345___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_345__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_345__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_346         (0x00A935DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_346___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_346__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_346__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_347         (0x00A935E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_347___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_347__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_347__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_348         (0x00A935E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_348___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_348__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_348__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_349         (0x00A935E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_349___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_349__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_349__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_350         (0x00A935EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_350___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_350__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_350__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_351         (0x00A935F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_351___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_351__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_351__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_352         (0x00A935F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_352___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_352__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_352__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_353         (0x00A935F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_353___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_353__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_353__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_354         (0x00A935FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_354___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_354__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_354__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_355         (0x00A93600)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_355___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_355__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_355__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_356         (0x00A93604)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_356___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_356__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_356__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_357         (0x00A93608)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_357___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_357__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_357__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_358         (0x00A9360C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_358___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_358__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_358__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_359         (0x00A93610)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_359___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_359__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_359__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_360         (0x00A93614)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_360___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_360__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_360__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_361         (0x00A93618)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_361___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_361__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_361__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_362         (0x00A9361C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_362___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_362__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_362__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_363         (0x00A93620)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_363___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_363__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_363__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_364         (0x00A93624)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_364___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_364__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_364__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_365         (0x00A93628)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_365___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_365__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_365__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_366         (0x00A9362C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_366___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_366__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_366__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_367         (0x00A93630)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_367___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_367__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_367__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_368         (0x00A93634)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_368___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_368__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_368__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_369         (0x00A93638)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_369___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_369__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_369__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_370         (0x00A9363C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_370___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_370__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_370__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_371         (0x00A93640)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_371___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_371__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_371__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_372         (0x00A93644)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_372___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_372__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_372__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_373         (0x00A93648)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_373___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_373__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_373__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_374         (0x00A9364C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_374___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_374__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_374__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_375         (0x00A93650)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_375___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_375__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_375__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_376         (0x00A93654)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_376___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_376__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_376__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_377         (0x00A93658)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_377___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_377__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_377__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_378         (0x00A9365C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_378___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_378__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_378__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_379         (0x00A93660)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_379___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_379__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_379__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_380         (0x00A93664)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_380___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_380__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_380__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_381         (0x00A93668)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_381___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_381__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_381__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_382         (0x00A9366C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_382___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_382__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_382__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_383         (0x00A93670)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_383___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_383__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_383__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_384         (0x00A93674)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_384___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_384__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_384__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_385         (0x00A93678)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_385___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_385__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_385__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_386         (0x00A9367C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_386___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_386__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_386__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_387         (0x00A93680)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_387___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_387__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_387__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_388         (0x00A93684)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_388___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_388__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_388__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_389         (0x00A93688)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_389___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_389__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_389__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_390         (0x00A9368C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_390___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_390__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_390__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_391         (0x00A93690)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_391___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_391__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_391__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_392         (0x00A93694)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_392___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_392__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_392__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_393         (0x00A93698)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_393___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_393__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_393__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_394         (0x00A9369C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_394___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_394__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_394__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_395         (0x00A936A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_395___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_395__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_395__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_396         (0x00A936A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_396___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_396__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_396__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_397         (0x00A936A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_397___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_397__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_397__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_398         (0x00A936AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_398___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_398__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_398__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_399         (0x00A936B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_399___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_399__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_399__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_400         (0x00A936B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_400___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_400__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_400__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_401         (0x00A936B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_401___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_401__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_401__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_402         (0x00A936BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_402___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_402__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_402__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_403         (0x00A936C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_403___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_403__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_403__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_404         (0x00A936C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_404___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_404__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_404__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_405         (0x00A936C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_405___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_405__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_405__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_406         (0x00A936CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_406___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_406__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_406__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_407         (0x00A936D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_407___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_407__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_407__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_408         (0x00A936D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_408___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_408__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_408__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_409         (0x00A936D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_409___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_409__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_409__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_410         (0x00A936DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_410___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_410__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_410__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_411         (0x00A936E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_411___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_411__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_411__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_412         (0x00A936E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_412___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_412__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_412__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_413         (0x00A936E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_413___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_413__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_413__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_414         (0x00A936EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_414___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_414__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_414__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_415         (0x00A936F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_415___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_415__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_415__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_416         (0x00A936F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_416___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_416__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_416__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_417         (0x00A936F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_417___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_417__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_417__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_418         (0x00A936FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_418___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_418__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_418__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_419         (0x00A93700)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_419___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_419__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_419__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_420         (0x00A93704)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_420___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_420__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_420__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_421         (0x00A93708)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_421___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_421__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_421__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_422         (0x00A9370C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_422___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_422__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_422__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_423         (0x00A93710)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_423___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_423__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_423__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_424         (0x00A93714)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_424___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_424__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_424__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_425         (0x00A93718)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_425___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_425__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_425__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_426         (0x00A9371C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_426___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_426__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_426__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_427         (0x00A93720)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_427___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_427__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_427__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_428         (0x00A93724)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_428___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_428__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_428__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_429         (0x00A93728)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_429___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_429__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_429__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_430         (0x00A9372C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_430___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_430__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_430__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_431         (0x00A93730)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_431___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_431__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_431__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_432         (0x00A93734)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_432___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_432__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_432__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_433         (0x00A93738)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_433___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_433__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_433__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_434         (0x00A9373C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_434___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_434__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_434__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_435         (0x00A93740)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_435___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_435__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_435__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_436         (0x00A93744)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_436___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_436__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_436__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_437         (0x00A93748)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_437___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_437__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_437__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_438         (0x00A9374C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_438___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_438__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_438__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_439         (0x00A93750)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_439___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_439__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_439__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_440         (0x00A93754)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_440___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_440__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_440__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_441         (0x00A93758)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_441___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_441__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_441__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_442         (0x00A9375C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_442___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_442__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_442__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_443         (0x00A93760)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_443___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_443__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_443__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_444         (0x00A93764)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_444___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_444__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_444__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_445         (0x00A93768)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_445___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_445__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_445__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_446         (0x00A9376C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_446___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_446__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_446__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_447         (0x00A93770)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_447___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_447__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_447__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_448         (0x00A93774)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_448___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_448__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_448__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_449         (0x00A93778)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_449___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_449__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_449__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_450         (0x00A9377C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_450___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_450__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_450__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_451         (0x00A93780)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_451___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_451__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_451__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_452         (0x00A93784)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_452___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_452__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_452__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_453         (0x00A93788)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_453___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_453__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_453__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_454         (0x00A9378C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_454___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_454__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_454__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_455         (0x00A93790)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_455___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_455__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_455__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_456         (0x00A93794)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_456___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_456__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_456__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_457         (0x00A93798)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_457___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_457__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_457__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_458         (0x00A9379C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_458___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_458__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_458__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_459         (0x00A937A0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_459___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_459__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_459__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_460         (0x00A937A4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_460___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_460__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_460__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_461         (0x00A937A8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_461___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_461__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_461__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_462         (0x00A937AC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_462___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_462__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_462__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_463         (0x00A937B0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_463___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_463__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_463__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_464         (0x00A937B4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_464___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_464__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_464__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_465         (0x00A937B8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_465___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_465__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_465__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_466         (0x00A937BC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_466___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_466__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_466__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_467         (0x00A937C0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_467___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_467__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_467__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_468         (0x00A937C4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_468___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_468__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_468__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_469         (0x00A937C8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_469___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_469__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_469__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_470         (0x00A937CC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_470___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_470__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_470__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_471         (0x00A937D0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_471___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_471__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_471__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_472         (0x00A937D4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_472___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_472__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_472__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_473         (0x00A937D8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_473___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_473__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_473__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_474         (0x00A937DC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_474___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_474__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_474__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_475         (0x00A937E0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_475___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_475__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_475__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_476         (0x00A937E4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_476___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_476__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_476__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_477         (0x00A937E8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_477___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_477__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_477__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_478         (0x00A937EC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_478___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_478__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_478__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_479         (0x00A937F0)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_479___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_479__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_479__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_480         (0x00A937F4)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_480___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_480__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_480__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_481         (0x00A937F8)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_481___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_481__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_481__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_482         (0x00A937FC)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_482___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_482__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_482__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_483         (0x00A93800)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_483___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_483__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_483__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_484         (0x00A93804)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_484___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_484__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_484__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_485         (0x00A93808)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_485___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_485__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_485__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_486         (0x00A9380C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_486___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_486__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_486__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_487         (0x00A93810)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_487___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_487__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_487__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_488         (0x00A93814)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_488___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_488__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_488__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_489         (0x00A93818)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_489___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_489__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_489__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_490         (0x00A9381C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_490___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_490__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_490__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_491         (0x00A93820)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_491___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_491__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_491__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_492         (0x00A93824)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_492___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_492__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_492__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_493         (0x00A93828)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_493___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_493__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_493__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_494         (0x00A9382C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_494___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_494__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_494__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_495         (0x00A93830)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_495___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_495__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_495__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_496         (0x00A93834)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_496___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_496__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_496__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_497         (0x00A93838)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_497___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_497__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_497__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_498         (0x00A9383C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_498___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_498__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_498__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_499         (0x00A93840)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_499___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_499__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_499__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_500         (0x00A93844)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_500___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_500__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_500__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_501         (0x00A93848)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_501___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_501__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_501__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_502         (0x00A9384C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_502___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_502__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_502__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_503         (0x00A93850)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_503___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_503__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_503__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_504         (0x00A93854)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_504___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_504__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_504__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_505         (0x00A93858)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_505___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_505__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_505__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_506         (0x00A9385C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_506___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_506__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_506__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_507         (0x00A93860)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_507___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_507__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_507__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_508         (0x00A93864)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_508___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_508__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_508__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_509         (0x00A93868)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_509___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_509__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_509__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_510         (0x00A9386C)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_510___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_510__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_510__DATA___S               0
#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_511         (0x00A93870)
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_511___RWC   QCSR_REG_RW    
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_511__DATA___M 0xFFFFFFFF
#define   WMAC0_AMPI_R1_LOOPBACK_BUFFER_511__DATA___S               0

#define WMAC0_RXOLE_RXOLE_R0_CONFIG               (0x00A95000)
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG___RWC         QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG___POR      0xDECF8300
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___POR 0x100
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___S              31
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___S              30
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___S              29
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___S              27
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___S              25
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___S              24
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___S              23
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___S              22
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___S              21
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___S              20
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___S              18
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___S              17
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___S              16
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___S              15
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___S              13
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___S              11
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___S              10
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___S               9
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___M 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___S               0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG___M        0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG___S                      0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET (0x00A95004)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___M 0x00FC0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___M 0x0003F000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___M 0x00000FC0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___M 0x0000003F
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___M 0x00FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET (0x00A95008)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___M 0x00FC0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___M 0x0003F000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___M 0x00000FC0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___M 0x0000003F
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___M 0x00FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT (0x00A9500C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0 (0x00A95010)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1 (0x00A95014)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2 (0x00A95018)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3 (0x00A9501C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0 (0x00A95020)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1 (0x00A95024)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2 (0x00A95028)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3 (0x00A9502C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT (0x00A95030)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___POR 0x00000FF1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___M 0x00000FFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT (0x00A95034)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0 (0x00A95038)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1 (0x00A9503C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2 (0x00A95040)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3 (0x00A95044)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0 (0x00A95048)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1 (0x00A9504C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2 (0x00A95050)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3 (0x00A95054)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT (0x00A95058)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___POR 0x00000FF1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___POR 0x3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___M 0x00000FFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A9505C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95060)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95064)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95068)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A9506C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95070)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL (0x00A95074)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0 (0x00A95078)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1 (0x00A9507C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0 (0x00A95080)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1 (0x00A95084)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL (0x00A95088)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___POR 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL (0x00A9508C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___POR 0x7ECFD9FB
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___S              30
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___M 0x7FCFF9FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL (0x00A95090)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___POR 0x00AAAAAB
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___M 0x03FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL (0x00A95094)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___M 0x000001FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0 (0x00A95098)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1 (0x00A9509C)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0 (0x00A950A0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1 (0x00A950A4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL (0x00A950A8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___POR 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL (0x00A950AC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___POR 0x7ECFD9FB
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___S              30
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___S              29
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___S              27
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___M 0x7FCFF9FF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL (0x00A950B0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___POR 0x00AAAAAB
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___S              25
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00800000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              23
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              21
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S              19
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              17
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00008000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              15
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00004000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S              13
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S              11
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S               9
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S               7
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___S               5
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___S               3
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___S               1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___M 0x03FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT (0x00A950B4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0 (0x00A950B8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1 (0x00A950BC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2 (0x00A950C0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3 (0x00A950C4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0 (0x00A950C8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1 (0x00A950CC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2 (0x00A950D0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3 (0x00A950D4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT (0x00A950D8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___POR 0x00000005
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___M 0x00000FFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT (0x00A950DC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0 (0x00A950E0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1 (0x00A950E4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2 (0x00A950E8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3 (0x00A950EC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0 (0x00A950F0)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1 (0x00A950F4)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2 (0x00A950F8)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___M 0x30000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___S              28
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___M 0x0C000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___S              26
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___M 0x03000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___M 0x00C00000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___S              22
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___S              20
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___S              18
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___S              16
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___S              14
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___M 0x00003000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___S              12
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___M 0x3FFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3 (0x00A950FC)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___M 0x0000003F   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___S               0

#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT (0x00A95100)
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___POR 0x00000005
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___M 0x00000C00
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___S              10
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___S               8
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___M 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___S               6
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___S               4
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___S               2
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___S               0
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___M 0x00000FFF   
#define   WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___S               0

#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION (0x00A95104)
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___POR 0x81000024
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___POR 0x2
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___S              31
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___S              30
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___M 0x20000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___S              29
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___M 0x10000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___S              28
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___M 0x08000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___S              27
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___M 0x04000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___S              26
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___M 0x02000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___S              25
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___M 0x01000000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___S              24
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___M 0x00F00000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___S              20
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___M 0x000F0000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___S              16
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___M 0x0000F000
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___S              12
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___S              11
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___S              10
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___S               9
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___S               8
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___S               7
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___S               6
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___M 0x00000030
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___S               4
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___M 0x0000000C
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___M 0x00000003
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___S               0
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___S               0

#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG         (0x00A95108)
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___POR 0x00410072
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___M 0x00400000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___S              22
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___M 0x00200000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___S              21
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___M 0x00100000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___S              20
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___M 0x00080000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___S              19
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___M 0x00040000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___S              18
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___M 0x00020000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___S              17
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___M 0x00010000
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___S              16
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___S               6
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___S               5
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___S               4
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___S               2
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___S               1
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___M  0x007F0077   
#define   WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___S                0

#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING       (0x00A9510C)
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___S               2
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___M 0x00000004   
#define   WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___S               2

#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT          (0x00A95110)
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___RWC    QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___POR 0x03010300
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___POR 0x030
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___POR 0x030
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___M 0xFFF00000
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___S              20
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___M 0x000F0000
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___S              16
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___M 0x0000FFF0
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___S               4
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___S               1
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___M   0xFFFFFFF7   
#define   WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___S                 0

#define WMAC0_RXOLE_RXOLE_R0_LRO                  (0x00A95114)
#define   WMAC0_RXOLE_RXOLE_R0_LRO___RWC            QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_LRO___POR         0x00000006
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___M 0x003FE000
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___S              13
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___M 0x00001FF0
#define   WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___S               4
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___S               2
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___S               1
#define   WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___M   0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___S                 0
#define   WMAC0_RXOLE_RXOLE_R0_LRO___M           0x003FFFF7   
#define   WMAC0_RXOLE_RXOLE_R0_LRO___S                         0

#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL            (0x00A95118)
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___POR   0x0003E068
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___POR 0xF
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___M 0x0003C000
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___S              14
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___S              13
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___S              12
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___S              11
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___S              10
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___S               9
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___S               8
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___S               7
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___S               6
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___S               5
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___S               4
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___S               3
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___S               2
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___S               1
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___M     0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___S                   0

#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH  (0x00A9511C)
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___S               0

#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG             (0x00A95120)
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG___RWC       QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG___POR    0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___S              16
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___S               0
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG___M      0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_WATCHDOG___S                    0

#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE      (0x00A95124)
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___M 0x3FFFF800
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___S              11
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___S               9
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___S               8
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___S               7
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___S               6
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___S               5
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___S               4
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___S               3
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___S               2
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___S               1
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___S               0

#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG          (0x00A95128)
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___RWC    QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___POR 0x000000C0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___POR 0x0C
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___M 0x000001F0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___S               2
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___S               1
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___S               0
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___M   0x000001F7   
#define   WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___S                 0

#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG         (0x00A9512C)
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___POR 0x00000606
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___S              10
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___S               9
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___S               8
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___S               7
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___S               6
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___S               5
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___S               3
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___S               2
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___S               1
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___M  0x000007FF   
#define   WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___S                0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0 (0x00A95130)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32 (0x00A95134)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64  (0x00A95138)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0 (0x00A9513C)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32 (0x00A95140)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64 (0x00A95144)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96 (0x00A95148)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128 (0x00A9514C)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160 (0x00A95150)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192 (0x00A95154)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224 (0x00A95158)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256 (0x00A9515C)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___S               0

#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288 (0x00A95160)
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___POR 0x0000000
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___M 0x07FFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___M 0x07FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0 (0x00A95164)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32 (0x00A95168)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64 (0x00A9516C)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96 (0x00A95170)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0 (0x00A95174)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32 (0x00A95178)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64 (0x00A9517C)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96 (0x00A95180)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT  (0x00A95184)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___S              16
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___M 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO (0x00A95188)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___M 0x000000FF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND (0x00A9518C)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___S               3
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___S               2
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___S               1
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___M 0x0000001F   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0 (0x00A95190)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___POR 0x000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___M 0x0FFFFFF0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___S               4
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___S               1
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___M 0x0FFFFFF3   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1 (0x00A95194)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___S               0

#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2 (0x00A95198)
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0 (0x00A9519C)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID (0x00A951A0)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___S              16
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___M 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___M 0x0003FFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND (0x00A951A4)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___S               4
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___S               3
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___S               2
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___S               1
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___M 0x0000001F   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0 (0x00A951A8)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___POR 0x000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___M 0x0FFFFFF0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___S               4
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___S               1
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___M 0x0FFFFFF3   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1 (0x00A951AC)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___S               0

#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2 (0x00A951B0)
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___S               0

#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW (0x00A951B4)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___S               0

#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH (0x00A951B8)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___M 0x000000FF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___S               0

#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE         (0x00A951BC)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___M 0x000FFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___M  0x000FFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___S                0

#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL      (0x00A951C0)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___POR 0x00003806
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___POR 0x06
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___S              16
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S              13
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S              12
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S              11
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___S               9
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___S               8
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___M 0xFFFF3FFF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___S               0

#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG         (0x00A951C4)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___POR 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___S              16
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___M  0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___S                0

#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE  (0x00A951C8)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___S               9
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___S               8
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___S               7
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S               6
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___S               5
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___S               4
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___S               3
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___S               2
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___S               1
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___S               0

#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING (0x00A951CC)
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___S               0
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___S               0

#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW (0x00A951D0)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___S               0

#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH (0x00A951D4)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___M 0x000000FF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___S               0

#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE         (0x00A951D8)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___M 0x000FFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___M  0x000FFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___S                0

#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL      (0x00A951DC)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___POR 0x00003806
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___POR 0x06
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___S              16
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S              13
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S              12
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S              11
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S              10
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___S               9
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___S               8
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___M 0xFFFF3FFF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___S               0

#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG         (0x00A951E0)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___POR 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___S              16
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___M  0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___S                0

#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE  (0x00A951E4)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___S               9
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___S               8
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___M 0x00000080
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___S               7
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S               6
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___S               5
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___S               4
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___S               3
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___S               2
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___S               1
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___S               0

#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING (0x00A951E8)
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___S               0
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___S               0

#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A96000)
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL         (0x00A96004)
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x80000000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S              31
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___M 0x003C0000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___S              18
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___M 0x0003C000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___S              14
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___M 0x00003E00
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___S               9
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___M 0x000001F0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___S               4
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___M 0x0000000F
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___M  0x803FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___S                0

#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER        (0x00A96008)
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___RWC  QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___S               0

#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER        (0x00A9600C)
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___RWC  QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___M 0x000000FF   
#define   WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___S               0

#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK    (0x00A96010)
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___S               0
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___S               0

#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR  (0x00A96014)
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___S               0

#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0       (0x00A96018)
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___S               0

#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1       (0x00A9601C)
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___S               0

#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2       (0x00A96020)
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___S               0

#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3       (0x00A96024)
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___S               0

#define WMAC0_RXOLE_RXOLE_R1_SM_STATES            (0x00A96028)
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES___RWC      QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES___POR   0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___M 0x00001800
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___S              11
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___M 0x00000400
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___S              10
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___M 0x00000300
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___S               8
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___M 0x000000E0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___S               5
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___M 0x0000001F
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES___M     0x00001FFF   
#define   WMAC0_RXOLE_RXOLE_R1_SM_STATES___S                   0

#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0    (0x00A9602C)
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___M 0x0001FFFE
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___S               1
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___M 0x0001FFFF   
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___S               0

#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1    (0x00A96030)
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___M 0x007E0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___S              17
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___M 0x0001FFFE
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___S               1
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___S               0

#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2    (0x00A96034)
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___M 0x007E0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___S              17
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___M 0x0001FFFE
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___S               1
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___S               0

#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3    (0x00A96038)
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___M 0x007E0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___S              17
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___M 0x0001FFFE
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___S               1
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___S               0

#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4    (0x00A9603C)
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___M 0x007E0000
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___S              17
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___M 0x0001FFFE
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___S               1
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK (0x00A96040)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS (0x00A96044)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A96048)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A9604C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A96050)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S              10
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A96054)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S              10
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S               5
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES        (0x00A96058)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___RWC  QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___S              20
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___S              18
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___S              16
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___S              14
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___M 0x00003800
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___S              11
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___M 0x00000700
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___S               8
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___M 0x0000000F
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___M 0x003FFF0F   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG      (0x00A9605C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___M 0x000003FF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___M 0x000003FF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS (0x00A96060)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S               3
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S               2
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S               1
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___S               0

#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A96064+0x4*(n))
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_nMIN 0    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_nMAX 31   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_ELEM 32   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0 (0x00A96064)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1 (0x00A96068)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2 (0x00A9606C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3 (0x00A96070)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4 (0x00A96074)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5 (0x00A96078)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6 (0x00A9607C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7 (0x00A96080)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8 (0x00A96084)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9 (0x00A96088)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10 (0x00A9608C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11 (0x00A96090)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12 (0x00A96094)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13 (0x00A96098)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14 (0x00A9609C)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15 (0x00A960A0)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16 (0x00A960A4)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17 (0x00A960A8)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18 (0x00A960AC)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19 (0x00A960B0)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20 (0x00A960B4)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21 (0x00A960B8)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22 (0x00A960BC)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23 (0x00A960C0)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24 (0x00A960C4)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25 (0x00A960C8)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26 (0x00A960CC)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27 (0x00A960D0)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28 (0x00A960D4)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29 (0x00A960D8)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30 (0x00A960DC)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31 (0x00A960E0)
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK (0x00A960E4)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS (0x00A960E8)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___M 0x00000001   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A960EC)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER (0x00A960F0)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A960F4)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S              10
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER (0x00A960F8)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S              10
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S               5
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES        (0x00A960FC)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___RWC  QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___M 0x00300000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___S              20
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___S              18
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___M 0x00030000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___S              16
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___S              14
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___M 0x00003800
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___S              11
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___M 0x00000700
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___S               8
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___M 0x0000000F
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___M 0x003FFF0F   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG      (0x00A96100)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___RWC QCSR_REG_RW    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___POR 0x000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___M 0x000003FF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___M 0x000003FF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS (0x00A96104)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S               3
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S               2
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S               1
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___S               0

#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n(n) (0x00A96108+0x4*(n))
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_nMIN 0    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_nMAX 31   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_ELEM 32   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___S               0
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF   
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0 (0x00A96108)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1 (0x00A9610C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2 (0x00A96110)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3 (0x00A96114)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4 (0x00A96118)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5 (0x00A9611C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6 (0x00A96120)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7 (0x00A96124)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8 (0x00A96128)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9 (0x00A9612C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10 (0x00A96130)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11 (0x00A96134)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12 (0x00A96138)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13 (0x00A9613C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14 (0x00A96140)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15 (0x00A96144)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16 (0x00A96148)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17 (0x00A9614C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18 (0x00A96150)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19 (0x00A96154)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20 (0x00A96158)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21 (0x00A9615C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22 (0x00A96160)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23 (0x00A96164)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24 (0x00A96168)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25 (0x00A9616C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26 (0x00A96170)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27 (0x00A96174)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28 (0x00A96178)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29 (0x00A9617C)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30 (0x00A96180)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30__VAL___S               0
#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31 (0x00A96184)
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO    
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF
#define   WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31__VAL___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0 (0x00A98000)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1 (0x00A98004)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___POR 0x0000002B
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2 (0x00A98008)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___POR 0x0000003C
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3 (0x00A9800C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___POR 0x00000033
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4 (0x00A98010)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___POR 0x00000887
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5 (0x00A98014)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___POR 0x0000082C
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6 (0x00A98018)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7 (0x00A9801C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8 (0x00A98020)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9 (0x00A98024)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10 (0x00A98028)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11 (0x00A9802C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12 (0x00A98030)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13 (0x00A98034)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14 (0x00A98038)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15 (0x00A9803C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___M 0x000FFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN (0x00A98040)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S               4
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___M 0x000000FF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0 (0x00A98044)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S              24
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S              16
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1 (0x00A98048)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S              24
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S              16
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG    (0x00A9804C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___POR 0x00000080
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S              11
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S              10
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S               9
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___M 0x00000FFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG (0x00A98050)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___POR 0x00010040
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___POR 0x100
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___POR 0x40
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___M 0x0001FF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___M 0x0001FFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE (0x00A98054)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___S               7
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___M 0x00000040
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___S               6
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___M 0x00000020
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___S               5
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S               4
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S               3
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___M 0x00000004
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___S               2
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___M 0x00000002
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___S               1
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___M 0x00000001
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0 (0x00A98058)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1 (0x00A9805C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2 (0x00A98060)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3 (0x00A98064)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0 (0x00A98068)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1 (0x00A9806C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2 (0x00A98070)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3 (0x00A98074)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4 (0x00A98078)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5 (0x00A9807C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6 (0x00A98080)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7 (0x00A98084)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8 (0x00A98088)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9 (0x00A9808C)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6 (0x00A98090)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___M 0x0000FF00
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___M 0x000000FF
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___M 0x0000FFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG    (0x00A98094)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___POR 0x0001E110
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S              27
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S              11
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___S              10
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___S               9
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S               8
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___M 0x000000C0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___S               6
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S               5
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___M 0x0FFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER (0x00A98098)
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___M 0xFFFFFFFE
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___S               1
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___M 0x00000001
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A99000)
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES      (0x00A99004)
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___RWC QCSR_REG_RO    
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___POR 0x000000
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___POR 0x00
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___M 0xFFFFFC00
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___S              10
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___M 0x000003E0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___S               5
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___M 0x0000001F
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___M 0xFFFFFFFF   
#define   WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___S               0

#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK (0x00A99008)
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___S               0

#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING (0x00A9B000)
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___POR 0x0
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___POR 0x0
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___M 0x00000002
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___S               1
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___M 0x00000001
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___S               0
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___M 0x00000003   
#define   WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___S               0

#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE     (0x00A9B004)
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___M 0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___S               0

#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID          (0x00A9B008)
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___POR 0x00
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___M 0x0000003F
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID___M   0x0000003F   
#define   WMAC0_CCE_CCE_R0_LAST_RULE_VALID___S                 0

#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID    (0x00A9B00C)
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___POR 0x00
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___M 0x0000001F
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___M 0x0000001F   
#define   WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___S               0

#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0         (0x00A9B010)
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___M  0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___S                0

#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1         (0x00A9B014)
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___M  0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___S                0

#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS        (0x00A9B018)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___M 0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___S               0

#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE          (0x00A9B01C)
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___POR 0x0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___M 0x00000080
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___S               7
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___M 0x00000040
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___S               6
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___M 0x00000020
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___S               5
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___M 0x00000010
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___S               4
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___M 0x00000008
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___S               3
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___M 0x00000004
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___S               2
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___M 0x00000002
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___S               1
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___M 0x00000001
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___S               0
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___M   0xC00000FF   
#define   WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___S                 0

#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE (0x00A9B020)
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___POR 0x00
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___M 0x0000001F
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___M 0x0000001F   
#define   WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___S               0

#define WMAC0_CCE_CCE_R0_WATCHDOG                 (0x00A9B024)
#define   WMAC0_CCE_CCE_R0_WATCHDOG___RWC           QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_WATCHDOG___POR        0x0000FFFF
#define   WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___M  0xFFFF0000
#define   WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___S               16
#define   WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___M   0x0000FFFF
#define   WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___S                 0
#define   WMAC0_CCE_CCE_R0_WATCHDOG___M          0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_WATCHDOG___S                        0

#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n(n) (0x00A9B100+0x4*(n))
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_nMIN 0    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_nMAX 127  
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_ELEM 128  
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___M   0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___S                 0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0          (0x00A9B100)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1          (0x00A9B104)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2          (0x00A9B108)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3          (0x00A9B10C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4          (0x00A9B110)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5          (0x00A9B114)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6          (0x00A9B118)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7          (0x00A9B11C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8          (0x00A9B120)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9          (0x00A9B124)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9___RWC    QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10         (0x00A9B128)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11         (0x00A9B12C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12         (0x00A9B130)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13         (0x00A9B134)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14         (0x00A9B138)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15         (0x00A9B13C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16         (0x00A9B140)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17         (0x00A9B144)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18         (0x00A9B148)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19         (0x00A9B14C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20         (0x00A9B150)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21         (0x00A9B154)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22         (0x00A9B158)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23         (0x00A9B15C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24         (0x00A9B160)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25         (0x00A9B164)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26         (0x00A9B168)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27         (0x00A9B16C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28         (0x00A9B170)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29         (0x00A9B174)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30         (0x00A9B178)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31         (0x00A9B17C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32         (0x00A9B180)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33         (0x00A9B184)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34         (0x00A9B188)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35         (0x00A9B18C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36         (0x00A9B190)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37         (0x00A9B194)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38         (0x00A9B198)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39         (0x00A9B19C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40         (0x00A9B1A0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41         (0x00A9B1A4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42         (0x00A9B1A8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43         (0x00A9B1AC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44         (0x00A9B1B0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45         (0x00A9B1B4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46         (0x00A9B1B8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47         (0x00A9B1BC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48         (0x00A9B1C0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49         (0x00A9B1C4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50         (0x00A9B1C8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51         (0x00A9B1CC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52         (0x00A9B1D0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53         (0x00A9B1D4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54         (0x00A9B1D8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55         (0x00A9B1DC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56         (0x00A9B1E0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57         (0x00A9B1E4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58         (0x00A9B1E8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59         (0x00A9B1EC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60         (0x00A9B1F0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61         (0x00A9B1F4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62         (0x00A9B1F8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63         (0x00A9B1FC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64         (0x00A9B200)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65         (0x00A9B204)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66         (0x00A9B208)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67         (0x00A9B20C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68         (0x00A9B210)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69         (0x00A9B214)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70         (0x00A9B218)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71         (0x00A9B21C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72         (0x00A9B220)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73         (0x00A9B224)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74         (0x00A9B228)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75         (0x00A9B22C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76         (0x00A9B230)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77         (0x00A9B234)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78         (0x00A9B238)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79         (0x00A9B23C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80         (0x00A9B240)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81         (0x00A9B244)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82         (0x00A9B248)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83         (0x00A9B24C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84         (0x00A9B250)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85         (0x00A9B254)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86         (0x00A9B258)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87         (0x00A9B25C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88         (0x00A9B260)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89         (0x00A9B264)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90         (0x00A9B268)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91         (0x00A9B26C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92         (0x00A9B270)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93         (0x00A9B274)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94         (0x00A9B278)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95         (0x00A9B27C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96         (0x00A9B280)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97         (0x00A9B284)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98         (0x00A9B288)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99         (0x00A9B28C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99___RWC   QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100        (0x00A9B290)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101        (0x00A9B294)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102        (0x00A9B298)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103        (0x00A9B29C)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104        (0x00A9B2A0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105        (0x00A9B2A4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106        (0x00A9B2A8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107        (0x00A9B2AC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108        (0x00A9B2B0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109        (0x00A9B2B4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110        (0x00A9B2B8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111        (0x00A9B2BC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112        (0x00A9B2C0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113        (0x00A9B2C4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114        (0x00A9B2C8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115        (0x00A9B2CC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116        (0x00A9B2D0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117        (0x00A9B2D4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118        (0x00A9B2D8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119        (0x00A9B2DC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120        (0x00A9B2E0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121        (0x00A9B2E4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122        (0x00A9B2E8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123        (0x00A9B2EC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124        (0x00A9B2F0)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125        (0x00A9B2F4)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126        (0x00A9B2F8)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126__VALUE___S               0
#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127        (0x00A9B2FC)
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127__VALUE___S               0

#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n(n) (0x00A9B300+0x4*(n))
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_nMIN 0    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_nMAX 255  
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_ELEM 256  
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___POR 0x00000000
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___S               0
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___M 0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0    (0x00A9B300)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1    (0x00A9B304)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2    (0x00A9B308)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3    (0x00A9B30C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4    (0x00A9B310)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5    (0x00A9B314)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6    (0x00A9B318)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7    (0x00A9B31C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8    (0x00A9B320)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9    (0x00A9B324)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10   (0x00A9B328)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11   (0x00A9B32C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12   (0x00A9B330)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13   (0x00A9B334)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14   (0x00A9B338)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15   (0x00A9B33C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16   (0x00A9B340)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17   (0x00A9B344)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18   (0x00A9B348)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19   (0x00A9B34C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20   (0x00A9B350)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21   (0x00A9B354)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22   (0x00A9B358)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23   (0x00A9B35C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24   (0x00A9B360)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25   (0x00A9B364)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26   (0x00A9B368)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27   (0x00A9B36C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28   (0x00A9B370)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29   (0x00A9B374)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30   (0x00A9B378)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31   (0x00A9B37C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32   (0x00A9B380)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33   (0x00A9B384)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34   (0x00A9B388)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35   (0x00A9B38C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36   (0x00A9B390)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37   (0x00A9B394)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38   (0x00A9B398)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39   (0x00A9B39C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40   (0x00A9B3A0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41   (0x00A9B3A4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42   (0x00A9B3A8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43   (0x00A9B3AC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44   (0x00A9B3B0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45   (0x00A9B3B4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46   (0x00A9B3B8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47   (0x00A9B3BC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48   (0x00A9B3C0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49   (0x00A9B3C4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50   (0x00A9B3C8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51   (0x00A9B3CC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52   (0x00A9B3D0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53   (0x00A9B3D4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54   (0x00A9B3D8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55   (0x00A9B3DC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56   (0x00A9B3E0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57   (0x00A9B3E4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58   (0x00A9B3E8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59   (0x00A9B3EC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60   (0x00A9B3F0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61   (0x00A9B3F4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62   (0x00A9B3F8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63   (0x00A9B3FC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64   (0x00A9B400)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65   (0x00A9B404)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66   (0x00A9B408)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67   (0x00A9B40C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68   (0x00A9B410)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69   (0x00A9B414)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70   (0x00A9B418)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71   (0x00A9B41C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72   (0x00A9B420)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73   (0x00A9B424)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74   (0x00A9B428)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75   (0x00A9B42C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76   (0x00A9B430)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77   (0x00A9B434)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78   (0x00A9B438)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79   (0x00A9B43C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80   (0x00A9B440)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81   (0x00A9B444)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82   (0x00A9B448)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83   (0x00A9B44C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84   (0x00A9B450)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85   (0x00A9B454)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86   (0x00A9B458)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87   (0x00A9B45C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88   (0x00A9B460)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89   (0x00A9B464)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90   (0x00A9B468)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91   (0x00A9B46C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92   (0x00A9B470)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93   (0x00A9B474)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94   (0x00A9B478)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95   (0x00A9B47C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96   (0x00A9B480)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97   (0x00A9B484)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98   (0x00A9B488)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99   (0x00A9B48C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100  (0x00A9B490)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101  (0x00A9B494)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102  (0x00A9B498)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103  (0x00A9B49C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104  (0x00A9B4A0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105  (0x00A9B4A4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106  (0x00A9B4A8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107  (0x00A9B4AC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108  (0x00A9B4B0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109  (0x00A9B4B4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110  (0x00A9B4B8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111  (0x00A9B4BC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112  (0x00A9B4C0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113  (0x00A9B4C4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114  (0x00A9B4C8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115  (0x00A9B4CC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116  (0x00A9B4D0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117  (0x00A9B4D4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118  (0x00A9B4D8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119  (0x00A9B4DC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120  (0x00A9B4E0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121  (0x00A9B4E4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122  (0x00A9B4E8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123  (0x00A9B4EC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124  (0x00A9B4F0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125  (0x00A9B4F4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126  (0x00A9B4F8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127  (0x00A9B4FC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128  (0x00A9B500)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129  (0x00A9B504)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130  (0x00A9B508)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131  (0x00A9B50C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132  (0x00A9B510)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133  (0x00A9B514)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134  (0x00A9B518)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135  (0x00A9B51C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136  (0x00A9B520)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137  (0x00A9B524)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138  (0x00A9B528)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139  (0x00A9B52C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140  (0x00A9B530)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141  (0x00A9B534)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142  (0x00A9B538)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143  (0x00A9B53C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144  (0x00A9B540)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145  (0x00A9B544)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146  (0x00A9B548)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147  (0x00A9B54C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148  (0x00A9B550)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149  (0x00A9B554)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150  (0x00A9B558)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151  (0x00A9B55C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152  (0x00A9B560)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153  (0x00A9B564)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154  (0x00A9B568)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155  (0x00A9B56C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156  (0x00A9B570)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157  (0x00A9B574)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158  (0x00A9B578)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159  (0x00A9B57C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160  (0x00A9B580)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161  (0x00A9B584)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162  (0x00A9B588)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163  (0x00A9B58C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164  (0x00A9B590)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165  (0x00A9B594)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166  (0x00A9B598)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167  (0x00A9B59C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168  (0x00A9B5A0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169  (0x00A9B5A4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170  (0x00A9B5A8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171  (0x00A9B5AC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172  (0x00A9B5B0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173  (0x00A9B5B4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174  (0x00A9B5B8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175  (0x00A9B5BC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176  (0x00A9B5C0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177  (0x00A9B5C4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178  (0x00A9B5C8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179  (0x00A9B5CC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180  (0x00A9B5D0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181  (0x00A9B5D4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182  (0x00A9B5D8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183  (0x00A9B5DC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184  (0x00A9B5E0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185  (0x00A9B5E4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186  (0x00A9B5E8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187  (0x00A9B5EC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188  (0x00A9B5F0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189  (0x00A9B5F4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190  (0x00A9B5F8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191  (0x00A9B5FC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192  (0x00A9B600)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193  (0x00A9B604)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194  (0x00A9B608)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195  (0x00A9B60C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196  (0x00A9B610)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197  (0x00A9B614)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198  (0x00A9B618)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199  (0x00A9B61C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200  (0x00A9B620)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201  (0x00A9B624)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202  (0x00A9B628)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203  (0x00A9B62C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204  (0x00A9B630)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205  (0x00A9B634)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206  (0x00A9B638)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207  (0x00A9B63C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208  (0x00A9B640)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209  (0x00A9B644)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210  (0x00A9B648)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211  (0x00A9B64C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212  (0x00A9B650)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213  (0x00A9B654)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214  (0x00A9B658)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215  (0x00A9B65C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216  (0x00A9B660)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217  (0x00A9B664)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218  (0x00A9B668)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219  (0x00A9B66C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220  (0x00A9B670)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221  (0x00A9B674)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222  (0x00A9B678)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223  (0x00A9B67C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224  (0x00A9B680)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225  (0x00A9B684)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226  (0x00A9B688)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227  (0x00A9B68C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228  (0x00A9B690)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229  (0x00A9B694)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230  (0x00A9B698)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231  (0x00A9B69C)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232  (0x00A9B6A0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233  (0x00A9B6A4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234  (0x00A9B6A8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235  (0x00A9B6AC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236  (0x00A9B6B0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237  (0x00A9B6B4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238  (0x00A9B6B8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239  (0x00A9B6BC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240  (0x00A9B6C0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241  (0x00A9B6C4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242  (0x00A9B6C8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243  (0x00A9B6CC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244  (0x00A9B6D0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245  (0x00A9B6D4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246  (0x00A9B6D8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247  (0x00A9B6DC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248  (0x00A9B6E0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249  (0x00A9B6E4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250  (0x00A9B6E8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251  (0x00A9B6EC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252  (0x00A9B6F0)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253  (0x00A9B6F4)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254  (0x00A9B6F8)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254__VALUE___S               0
#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255  (0x00A9B6FC)
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255__VALUE___M 0xFFFFFFFF
#define   WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255__VALUE___S               0

#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A9C000)
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK        (0x00A9C004)
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___RWC  QCSR_REG_RW    
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___POR 0x0
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___M 0x00000001
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___S               0
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___S               0

#define WMAC0_CCE_CCE_R1_SM_STATES                (0x00A9C008)
#define   WMAC0_CCE_CCE_R1_SM_STATES___RWC          QCSR_REG_RO    
#define   WMAC0_CCE_CCE_R1_SM_STATES___POR       0x00000000
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___POR 0x0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___M 0x00003000
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___S              12
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___M 0x00000C00
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___S              10
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___M 0x00000300
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___S               8
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___M 0x000000C0
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___S               6
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___M 0x00000030
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___S               4
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___M 0x0000000E
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___S               1
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___M 0x00000001
#define   WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___S               0
#define   WMAC0_CCE_CCE_R1_SM_STATES___M         0x00003FFF   
#define   WMAC0_CCE_CCE_R1_SM_STATES___S                       0

#define WMAC0_TXOLE_TXOLE_R0_CONFIG               (0x00A9E000)
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG___RWC         QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG___POR      0x00000000
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___M 0x00000008
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___S               3
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___M 0x00000004
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___S               2
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___M 0x00000002
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___S               1
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___S               0
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG___M        0x0000000F   
#define   WMAC0_TXOLE_TXOLE_R0_CONFIG___S                      0

#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE      (0x00A9E004)
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___POR 0x0000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___M 0x3FFFC000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___S              14
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___M 0x00002000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___S              13
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___M 0x00001000
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___S              12
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___M 0x00000800
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___S              11
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___M 0x00000400
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___S              10
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___M 0x00000200
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___S               9
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___M 0x00000100
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___S               8
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___M 0x00000080
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___S               7
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___M 0x00000040
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___S               6
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___M 0x00000020
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___S               5
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___M 0x00000010
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___S               4
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___M 0x00000008
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___S               3
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___M 0x00000004
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___S               2
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___M 0x00000002
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___S               1
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___S               0
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___S               0

#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN             (0x00A9E008)
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___RWC       QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___POR    0x00000000
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___M 0x00002000
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___S              13
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___M 0x00001000
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___S              12
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___M 0x00000800
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___S              11
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___M 0x00000400
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___S              10
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___M 0x00000200
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___S               9
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___M 0x00000100
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___S               8
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___M 0x00000080
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___S               7
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___M 0x00000040
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___S               6
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___M 0x00000020
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___S               5
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___M 0x00000010
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___S               4
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___M 0x00000008
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___S               3
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___M 0x00000004
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___S               2
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___M 0x00000002
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___S               1
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___S               0
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___M      0x00003FFF   
#define   WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___S                    0

#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS           (0x00A9E00C)
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___RWC     QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___POR  0x00001020
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___POR 0x08
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___POR 0x020
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___M 0x00003E00
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___S               9
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___M 0x000001FF
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___S               0
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___M    0x00003FFF   
#define   WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___S                  0

#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF     (0x00A9E010)
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___S               0

#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG             (0x00A9E014)
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG___RWC       QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG___POR    0x0000FFFF
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___POR 0x0000
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___POR 0xFFFF
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___M 0xFFFF0000
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___S              16
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___M 0x0000FFFF
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___S               0
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG___M      0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R0_WATCHDOG___S                    0

#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL         (0x00A9F000)
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___POR 0x00
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___POR 0x00
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x00000400
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S              10
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___M 0x000003E0
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___S               5
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___M 0x0000001F
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___S               0
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___M  0x000007FF   
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___S                0

#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK    (0x00A9F004)
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___S               0

#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0       (0x00A9F008)
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___S               0

#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1       (0x00A9F00C)
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___S               0

#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A9F010)
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER        (0x00A9F014)
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___RWC  QCSR_REG_RO    
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___S               0

#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER        (0x00A9F018)
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___RWC  QCSR_REG_RO    
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___M 0x000000FF   
#define   WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___S               0

#define WMAC0_TXOLE_TXOLE_R1_SM_STATES            (0x00A9F01C)
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES___RWC      QCSR_REG_RO    
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES___POR   0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___POR 0x00
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___M 0x18000000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___S              27
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___M 0x06000000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___S              25
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___M 0x01E00000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___S              21
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___M 0x00180000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___S              19
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___M 0x00070000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___S              16
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___M 0x0000E000
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___S              13
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___M 0x00001C00
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___S              10
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___M 0x000003C0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___S               6
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___M 0x0000003F
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES___M     0x1FFFFFFF   
#define   WMAC0_TXOLE_TXOLE_R1_SM_STATES___S                   0

#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS (0x00A9F020)
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___POR 0x0
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___M 0x00000001
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___S               0
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___M 0x00000001   
#define   WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___S               0

#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR  (0x00A9F024)
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___S               0
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0 (0x00AA1000)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1 (0x00AA1004)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___POR 0x0000002B
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2 (0x00AA1008)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___POR 0x0000003C
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3 (0x00AA100C)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___POR 0x00000033
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4 (0x00AA1010)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___POR 0x00000887
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5 (0x00AA1014)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___POR 0x0000082C
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6 (0x00AA1018)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7 (0x00AA101C)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8 (0x00AA1020)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9 (0x00AA1024)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10 (0x00AA1028)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11 (0x00AA102C)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12 (0x00AA1030)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13 (0x00AA1034)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14 (0x00AA1038)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15 (0x00AA103C)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___M 0x000FFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN (0x00AA1040)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S               4
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___M 0x000000FF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0 (0x00AA1044)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S              24
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S              16
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1 (0x00AA1048)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S              24
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S              16
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG    (0x00AA104C)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___POR 0x00000080
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S              11
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S              10
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S               9
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___M 0x00000FFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE (0x00AA1054)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S              31
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S              30
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___S               7
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___M 0x00000040
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___S               6
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___M 0x00000020
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___S               5
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S               4
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S               3
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___M 0x00000004
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___S               2
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___M 0x00000002
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___S               1
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___M 0x00000001
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG    (0x00AA1094)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___POR 0x0001E110
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S              27
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S              11
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___S              10
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___S               9
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S               8
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S               5
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___M 0x0FFFFF3F   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER (0x00AA1098)
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___M 0xFFFFFFFE
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___S               1
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___M 0x00000001
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AA2000)
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES      (0x00AA2004)
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___RWC QCSR_REG_RO    
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___POR 0x000000
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___POR 0x00
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___M 0xFFFFFC00
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___S              10
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___M 0x000003E0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___S               5
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___M 0x0000001F
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___M 0xFFFFFFFF   
#define   WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___S               0

#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK (0x00AA2008)
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___S               0

#define WMAC0_RRI_R0_SW_REG_REINIT_P              (0x00AA4000)
#define   WMAC0_RRI_R0_SW_REG_REINIT_P___RWC        QCSR_REG_RW    
#define   WMAC0_RRI_R0_SW_REG_REINIT_P___POR     0x00000000
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___POR 0x00000000
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___POR 0x0
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___M 0xFFFFFFFE
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___S               1
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___M  0x00000001
#define   WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___S                0
#define   WMAC0_RRI_R0_SW_REG_REINIT_P___M       0xFFFFFFFF   
#define   WMAC0_RRI_R0_SW_REG_REINIT_P___S                     0

#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR           (0x00AA4004)
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR___RWC     QCSR_REG_RW    
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR___POR  0x00000000
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___POR 0x00000000
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___M 0xFFFFFFFC
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___S               2
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR___M    0xFFFFFFFC   
#define   WMAC0_RRI_R0_SW_REG_REINIT_ADDR___S                  2

#define WMAC0_RRI_R0_MISC_CFG                     (0x00AA4008)
#define   WMAC0_RRI_R0_MISC_CFG___RWC               QCSR_REG_RW    
#define   WMAC0_RRI_R0_MISC_CFG___POR            0x00000000
#define   WMAC0_RRI_R0_MISC_CFG__SPARE___POR     0x0
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___POR 0x0
#define   WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___POR 0x0
#define   WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___POR 0x00
#define   WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___POR 0x00
#define   WMAC0_RRI_R0_MISC_CFG__SPARE2___POR    0x0
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___POR 0x0
#define   WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___POR 0x0
#define   WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___POR  0x0
#define   WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___POR 0x00
#define   WMAC0_RRI_R0_MISC_CFG__SPARE___M       0xC0000000
#define   WMAC0_RRI_R0_MISC_CFG__SPARE___S                    30
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___M 0x20000000
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___S              29
#define   WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___M 0x10000000
#define   WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___S              28
#define   WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___M 0x0FF00000
#define   WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___S              20
#define   WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___M 0x000F8000
#define   WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___S              15
#define   WMAC0_RRI_R0_MISC_CFG__SPARE2___M      0x00007800
#define   WMAC0_RRI_R0_MISC_CFG__SPARE2___S                   11
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___M   0x00000400
#define   WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___S                10
#define   WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___M 0x00000200
#define   WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___S               9
#define   WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___M    0x00000100
#define   WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___S                  8
#define   WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___M 0x000000FF
#define   WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___S               0
#define   WMAC0_RRI_R0_MISC_CFG___M              0xFFFFFFFF   
#define   WMAC0_RRI_R0_MISC_CFG___S                            0

#define WMAC0_RRI_R0_MEM_RANGE_START              (0x00AA400C)
#define   WMAC0_RRI_R0_MEM_RANGE_START___RWC        QCSR_REG_RW    
#define   WMAC0_RRI_R0_MEM_RANGE_START___POR     0x00000000
#define   WMAC0_RRI_R0_MEM_RANGE_START__ADDR___POR 0x00000000
#define   WMAC0_RRI_R0_MEM_RANGE_START__ADDR___M 0xFFFFFFFF
#define   WMAC0_RRI_R0_MEM_RANGE_START__ADDR___S               0
#define   WMAC0_RRI_R0_MEM_RANGE_START___M       0xFFFFFFFF   
#define   WMAC0_RRI_R0_MEM_RANGE_START___S                     0

#define WMAC0_RRI_R0_MEM_RANGE_END                (0x00AA4010)
#define   WMAC0_RRI_R0_MEM_RANGE_END___RWC          QCSR_REG_RW    
#define   WMAC0_RRI_R0_MEM_RANGE_END___POR       0x0000407F
#define   WMAC0_RRI_R0_MEM_RANGE_END__ADDR___POR 0x0000407F
#define   WMAC0_RRI_R0_MEM_RANGE_END__ADDR___M   0xFFFFFFFF
#define   WMAC0_RRI_R0_MEM_RANGE_END__ADDR___S                 0
#define   WMAC0_RRI_R0_MEM_RANGE_END___M         0xFFFFFFFF   
#define   WMAC0_RRI_R0_MEM_RANGE_END___S                       0

#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE        (0x00AA4014)
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___RWC  QCSR_REG_RW    
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___POR 0x00000000
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___POR 0x00
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___M 0x0000003F
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___S               0
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___M 0x0000003F   
#define   WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___S               0

#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR          (0x00AA4018)
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___RWC    QCSR_REG_RW    
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___POR 0x00000000
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___POR 0x00000000
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___M 0xFFFFFFFC
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___S               2
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___M   0xFFFFFFFC   
#define   WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___S                 2

#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR            (0x00AA5000)
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___RWC      QCSR_REG_RO    
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___POR   0x00000000
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___POR 0x00000000
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___M 0xFFFFFFFC
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___S               2
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___M     0xFFFFFFFC   
#define   WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___S                   2

#define WMAC0_RRI_R1_ERR_INT_P                    (0x00AA5004)
#define   WMAC0_RRI_R1_ERR_INT_P___RWC              QCSR_REG_RO    
#define   WMAC0_RRI_R1_ERR_INT_P___POR           0x00000000
#define   WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_P__APB_ERR___POR  0x0
#define   WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___M 0x00000004
#define   WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___S               2
#define   WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___M 0x00000002
#define   WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___S               1
#define   WMAC0_RRI_R1_ERR_INT_P__APB_ERR___M    0x00000001
#define   WMAC0_RRI_R1_ERR_INT_P__APB_ERR___S                  0
#define   WMAC0_RRI_R1_ERR_INT_P___M             0x00000007   
#define   WMAC0_RRI_R1_ERR_INT_P___S                           0

#define WMAC0_RRI_R1_ERR_INT_BITMASK              (0x00AA5008)
#define   WMAC0_RRI_R1_ERR_INT_BITMASK___RWC        QCSR_REG_RW    
#define   WMAC0_RRI_R1_ERR_INT_BITMASK___POR     0x00000080
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___POR 0x1
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___M 0x00000100
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___S               8
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___M 0x00000080
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___S               7
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___M 0x00000040
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___S               6
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___M 0x00000020
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___S               5
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___M 0x00000010
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___S               4
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___M 0x00000008
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___S               3
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___M 0x00000004
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___S               2
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___M 0x00000002
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___S               1
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___M 0x00000001
#define   WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___S               0
#define   WMAC0_RRI_R1_ERR_INT_BITMASK___M       0x000001FF   
#define   WMAC0_RRI_R1_ERR_INT_BITMASK___S                     0

#define WMAC0_RRI_R1_ERR_INT_STATUS               (0x00AA500C)
#define   WMAC0_RRI_R1_ERR_INT_STATUS___RWC         QCSR_REG_RW    
#define   WMAC0_RRI_R1_ERR_INT_STATUS___POR      0x00000000
#define   WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___M 0x00000100
#define   WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___S               8
#define   WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___M 0x00000080
#define   WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___S               7
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___M 0x00000040
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___S               6
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___M 0x00000020
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___S               5
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___M 0x00000010
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___S               4
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___M 0x00000008
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___S               3
#define   WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___M 0x00000004
#define   WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___S               2
#define   WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___M 0x00000002
#define   WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___S               1
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___M 0x00000001
#define   WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___S               0
#define   WMAC0_RRI_R1_ERR_INT_STATUS___M        0x000001FF   
#define   WMAC0_RRI_R1_ERR_INT_STATUS___S                      0

#define WMAC0_RRI_R1_CURRENT_ADDR                 (0x00AA5010)
#define   WMAC0_RRI_R1_CURRENT_ADDR___RWC           QCSR_REG_RO    
#define   WMAC0_RRI_R1_CURRENT_ADDR___POR        0x00000000
#define   WMAC0_RRI_R1_CURRENT_ADDR__VAL___POR   0x00000000
#define   WMAC0_RRI_R1_CURRENT_ADDR__VAL___M     0xFFFFFFFF
#define   WMAC0_RRI_R1_CURRENT_ADDR__VAL___S                   0
#define   WMAC0_RRI_R1_CURRENT_ADDR___M          0xFFFFFFFF   
#define   WMAC0_RRI_R1_CURRENT_ADDR___S                        0

#define WMAC0_RRI_R1_EVENTMASK_IX_0               (0x00AA5014)
#define   WMAC0_RRI_R1_EVENTMASK_IX_0___RWC         QCSR_REG_RW    
#define   WMAC0_RRI_R1_EVENTMASK_IX_0___POR      0x00000000
#define   WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___POR 0x0000000
#define   WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___M  0x03FFFFFF
#define   WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___S                0
#define   WMAC0_RRI_R1_EVENTMASK_IX_0___M        0x03FFFFFF   
#define   WMAC0_RRI_R1_EVENTMASK_IX_0___S                      0

#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR          (0x00AA5018)
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR___RWC    QCSR_REG_RO    
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___POR 0x00000
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___M 0x0001FFFF
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___S               0
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR___M   0x0001FFFF   
#define   WMAC0_RRI_R1_INVALID_APB_ACC_ADR___S                 0

#define WMAC0_RRI_R1_SM_STATES_IX_0               (0x00AA501C)
#define   WMAC0_RRI_R1_SM_STATES_IX_0___RWC         QCSR_REG_RO    
#define   WMAC0_RRI_R1_SM_STATES_IX_0___POR      0x00000000
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___POR 0x0
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___POR 0x00
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___POR 0x00
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___M 0x0000E000
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___S              13
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___M 0x00001FE0
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___S               5
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___M 0x0000001F
#define   WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___S               0
#define   WMAC0_RRI_R1_SM_STATES_IX_0___M        0x0000FFFF   
#define   WMAC0_RRI_R1_SM_STATES_IX_0___S                      0

#define WMAC0_RRI_R1_ACTIVE                       (0x00AA5020)
#define   WMAC0_RRI_R1_ACTIVE___RWC                 QCSR_REG_RO    
#define   WMAC0_RRI_R1_ACTIVE___POR              0x00000000
#define   WMAC0_RRI_R1_ACTIVE__VAL___POR         0x0
#define   WMAC0_RRI_R1_ACTIVE__VAL___M           0x00000001
#define   WMAC0_RRI_R1_ACTIVE__VAL___S                         0
#define   WMAC0_RRI_R1_ACTIVE___M                0x00000001   
#define   WMAC0_RRI_R1_ACTIVE___S                              0

#define WMAC0_RRI_R1_APB_TIMEOUT                  (0x00AA5024)
#define   WMAC0_RRI_R1_APB_TIMEOUT___RWC            QCSR_REG_RW    
#define   WMAC0_RRI_R1_APB_TIMEOUT___POR         0x000000FF
#define   WMAC0_RRI_R1_APB_TIMEOUT__VAL___POR    0x000000FF
#define   WMAC0_RRI_R1_APB_TIMEOUT__VAL___M      0xFFFFFFFF
#define   WMAC0_RRI_R1_APB_TIMEOUT__VAL___S                    0
#define   WMAC0_RRI_R1_APB_TIMEOUT___M           0xFFFFFFFF   
#define   WMAC0_RRI_R1_APB_TIMEOUT___S                         0

#define WMAC0_RRI_R1_INVALID_CMD_WORD             (0x00AA5028)
#define   WMAC0_RRI_R1_INVALID_CMD_WORD___RWC       QCSR_REG_RO    
#define   WMAC0_RRI_R1_INVALID_CMD_WORD___POR    0x00000000
#define   WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___POR 0x00000000
#define   WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___M 0xFFFFFFFF
#define   WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___S               0
#define   WMAC0_RRI_R1_INVALID_CMD_WORD___M      0xFFFFFFFF   
#define   WMAC0_RRI_R1_INVALID_CMD_WORD___S                    0

#define WMAC0_RRI_R1_TESTBUS_LOWER                (0x00AA502C)
#define   WMAC0_RRI_R1_TESTBUS_LOWER___RWC          QCSR_REG_RO    
#define   WMAC0_RRI_R1_TESTBUS_LOWER___POR       0x00000000
#define   WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___M  0xFFFFFFFF
#define   WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___S                0
#define   WMAC0_RRI_R1_TESTBUS_LOWER___M         0xFFFFFFFF   
#define   WMAC0_RRI_R1_TESTBUS_LOWER___S                       0

#define WMAC0_RRI_R1_TESTBUS_UPPER                (0x00AA5030)
#define   WMAC0_RRI_R1_TESTBUS_UPPER___RWC          QCSR_REG_RO    
#define   WMAC0_RRI_R1_TESTBUS_UPPER___POR       0x00000000
#define   WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___M  0x000000FF
#define   WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___S                0
#define   WMAC0_RRI_R1_TESTBUS_UPPER___M         0x000000FF   
#define   WMAC0_RRI_R1_TESTBUS_UPPER___S                       0

#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED        (0x00AA5034)
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___RWC  QCSR_REG_RO    
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___POR 0x00000000
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___POR 0x0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___M 0x00000100
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___S               8
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___M 0x00000080
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___S               7
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___M 0x00000040
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___S               6
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___M 0x00000020
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___S               5
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___M 0x00000010
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___S               4
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___M 0x00000008
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___S               3
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___M 0x00000004
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___S               2
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___M 0x00000002
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___S               1
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___M 0x00000001
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___S               0
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___M 0x000001FF   
#define   WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___S               0

#define WMAC0_RRI_R1_TESTBUS_CTRL                 (0x00AA5038)
#define   WMAC0_RRI_R1_TESTBUS_CTRL___RWC           QCSR_REG_RW    
#define   WMAC0_RRI_R1_TESTBUS_CTRL___POR        0x00000000
#define   WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0
#define   WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F
#define   WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   WMAC0_RRI_R1_TESTBUS_CTRL___M          0x0000000F   
#define   WMAC0_RRI_R1_TESTBUS_CTRL___S                        0

#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL    (0x00AA503C)
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_RRI_R1_RRI_SPARE_REGISTER           (0x00AA5040)
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER___RWC     QCSR_REG_RW    
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER___POR  0x00000000
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___POR 0x0000
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___M 0x0000FFFF
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___S               0
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER___M    0x0000FFFF   
#define   WMAC0_RRI_R1_RRI_SPARE_REGISTER___S                  0

#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0           (0x00AA7000)
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___POR  0x000F478F
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___POR 0x000F
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___POR 0x478F
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___M 0xFFFF0000
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___S              16
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___S               0
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___S                  0

#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1           (0x00AA7004)
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___POR  0xC7FF000F
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___POR 0xC7FF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___POR 0x000F
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___M 0xFFFF0000
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___S              16
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___S               0
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___S                  0

#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL           (0x00AA7008)
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___POR  0x000000AA
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___POR 0x00AA
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___S               0
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___M    0x0000FFFF   
#define   WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___S                  0

#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT            (0x00AA700C)
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT___POR   0x00003210
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___POR 0x00003210
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___S               0
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT___M     0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_MIC_QOS_SELECT___S                   0

#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK         (0x00AA7010)
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___RWC   QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___POR 0x0000008F
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___POR 0x008F
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___S               0
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___M  0x0000FFFF   
#define   WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___S                0

#define WMAC0_CRYPTO_R0_MISC_CONTROL              (0x00AA7014)
#define   WMAC0_CRYPTO_R0_MISC_CONTROL___RWC        QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_MISC_CONTROL___POR     0x1E100009
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___POR 0x10
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___POR 0x0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___M 0x10000000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___S              28
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___M 0x08000000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___S              27
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___M 0x04000000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___S              26
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___M 0x02000000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___S              25
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___M 0x01000000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___S              24
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___M 0x00FF0000
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___S              16
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___M 0x00000080
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___S               7
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___M 0x00000040
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___S               6
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___M 0x00000020
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___S               5
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___M 0x00000010
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___S               4
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___M 0x00000008
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___S               3
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___M 0x00000004
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___S               2
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___M 0x00000002
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___S               1
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___M 0x00000001
#define   WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___S               0
#define   WMAC0_CRYPTO_R0_MISC_CONTROL___M       0x1FFF00FF   
#define   WMAC0_CRYPTO_R0_MISC_CONTROL___S                     0

#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE        (0x00AA7018)
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___POR 0x00000080
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___POR 0x1
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___M 0x00000200
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___S               9
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___M 0x00000100
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___S               8
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___M 0x00000080
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___S               7
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___M 0x00000040
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___S               6
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___M 0x00000020
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___S               5
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___M 0x00000010
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___S               4
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___M 0x00000008
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___S               3
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___M 0x00000004
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___S               2
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___M 0x00000002
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___S               1
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___M 0x00000001
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___S               0
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___M 0x000003FF   
#define   WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___S               0

#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG      (0x00AA701C)
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___POR 0x00000000
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___POR 0x0
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___POR 0x0
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___POR 0x0
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___POR 0x0
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___M 0x00000008
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___S               3
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___M 0x00000004
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___S               2
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___M 0x00000002
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___S               1
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___M 0x00000001
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___S               0
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___M 0x0000000F   
#define   WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___S               0

#define WMAC0_CRYPTO_R0_FIPS_CONTROL              (0x00AA7020)
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL___RWC        QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL___POR     0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___POR 0x0
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___POR 0x0
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___M 0x00000004
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___S               2
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___M 0x00000002
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___S               1
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___M 0x00000001
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___S               0
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL___M       0x00000007   
#define   WMAC0_CRYPTO_R0_FIPS_CONTROL___S                     0

#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n(n) (0x00AA7024+0x4*(n))
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_nMIN 0    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_nMAX 7    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_ELEM 8    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___POR   0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___POR 0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___S               0
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___M     0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___S                   0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_0            (0x00AA7024)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_0___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_0__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_0__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_1            (0x00AA7028)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_1___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_1__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_1__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_2            (0x00AA702C)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_2___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_2__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_2__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_3            (0x00AA7030)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_3___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_3__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_3__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_4            (0x00AA7034)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_4___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_4__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_4__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_5            (0x00AA7038)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_5___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_5__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_5__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_6            (0x00AA703C)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_6___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_6__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_6__AES_KEY___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_7            (0x00AA7040)
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_7___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_7__AES_KEY___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_KEY_7__AES_KEY___S               0

#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n(n) (0x00AA7044+0x4*(n))
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_nMIN 0    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_nMAX 3    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_ELEM 4    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___POR 0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___POR 0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___S               0
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0        (0x00AA7044)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0__AES_DATA_IN___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0__AES_DATA_IN___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1        (0x00AA7048)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1__AES_DATA_IN___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1__AES_DATA_IN___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2        (0x00AA704C)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2__AES_DATA_IN___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2__AES_DATA_IN___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3        (0x00AA7050)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3__AES_DATA_IN___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3__AES_DATA_IN___S               0

#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n(n) (0x00AA7054+0x4*(n))
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_nMIN 0    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_nMAX 3    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_ELEM 4    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___POR 0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___POR 0x00000000
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___S               0
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0       (0x00AA7054)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0__AES_DATA_OUT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0__AES_DATA_OUT___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1       (0x00AA7058)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1__AES_DATA_OUT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1__AES_DATA_OUT___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2       (0x00AA705C)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2__AES_DATA_OUT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2__AES_DATA_OUT___S               0
#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3       (0x00AA7060)
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3__AES_DATA_OUT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3__AES_DATA_OUT___S               0

#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH        (0x00AA7064)
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___POR 0x000013E3
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___POR 0x13E3
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___S               0
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___M 0x0000FFFF   
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___S               0

#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV           (0x00AA7068)
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___POR  0x00000000
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___POR 0x00000000
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___S               0
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___S                  0

#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK   (0x00AA706C)
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___POR 0x000FC78F
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___POR 0x000F
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___POR 0xC78F
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___M 0xFFFF0000
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___S              16
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___S               0
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___S               0

#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK    (0x00AA7070)
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___POR 0x000FC78F
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___POR 0x000F
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___POR 0xC78F
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___M 0xFFFF0000
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___S              16
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___S               0
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___S               0

#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL            (0x00AA7074)
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___POR   0x00010E0E
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___POR 0x1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___POR 0x0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___M 0x00010000
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___S              16
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___M 0x00008000
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___S              15
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___M 0x00004000
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___S              14
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___M 0x00002000
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___S              13
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___M 0x00001000
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___S              12
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___M 0x00000800
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___S              11
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___M 0x00000400
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___S              10
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___M 0x00000200
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___S               9
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___M 0x00000100
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___S               8
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___M 0x00000008
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___S               3
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___M 0x00000004
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___S               2
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___M 0x00000002
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___S               1
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___M 0x00000001
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___S               0
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___M     0x0001FF0F   
#define   WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___S                   0

#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH        (0x00AA7078)
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___RWC  QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___POR 0x1FFF1FFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___POR 0x1FFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___POR 0x1FFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___M 0xFFFF0000
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___S              16
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___M 0x0000FFFF
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___S               0
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___S               0

#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT           (0x00AA707C)
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT___POR  0x00000101
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___POR 0x01
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___POR 0x01
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___M 0x0000FF00
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___S               8
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___M 0x000000FF
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___S               0
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT___M    0x0000FFFF   
#define   WMAC0_CRYPTO_R0_USER_SWITCH_CNT___S                  0

#define WMAC0_CRYPTO_R0_ARBITER_CTRL              (0x00AA7080)
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL___RWC        QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL___POR     0x00010000
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___POR 0x00
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___POR 0x00
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___M 0x00010000
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___S              16
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___M 0x0000FF00
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___S               8
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___M 0x000000FF
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___S               0
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL___M       0x0001FFFF   
#define   WMAC0_CRYPTO_R0_ARBITER_CTRL___S                     0

#define WMAC0_CRYPTO_R0_SPARE_CTRL                (0x00AA7084)
#define   WMAC0_CRYPTO_R0_SPARE_CTRL___RWC          QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_SPARE_CTRL___POR       0x0000FF01
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___POR 0x7F80
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___POR 0x1
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___M 0x0000FFFE
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___S               1
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___M 0x00000001
#define   WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___S               0
#define   WMAC0_CRYPTO_R0_SPARE_CTRL___M         0x0000FFFF   
#define   WMAC0_CRYPTO_R0_SPARE_CTRL___S                       0

#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL          (0x00AA7088)
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___RWC    QCSR_REG_RW    
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___POR 0x00000007
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___POR 0x0000
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___POR 0x7
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___M 0x0000FFF8
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___S               3
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___M 0x00000007
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___S               0
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___M   0x0000FFFF   
#define   WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___S                 0

#define WMAC0_CRYPTO_R1_SM_STATES_IX_0            (0x00AA8000)
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0___RWC      QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0___POR   0x00000000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___POR 0x00
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___POR 0x00
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___M 0x01000000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___S              24
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___M 0x00800000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___S              23
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___M 0x00600000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___S              21
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___M 0x000F8000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___S              15
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___M 0x00001F00
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___S               8
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___M 0x000000F0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___S               4
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___M 0x0000000F
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___S               0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0___M     0x01EF9FFF   
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_0___S                   0

#define WMAC0_CRYPTO_R1_TESTBUS_CTRL              (0x00AA8004)
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL___RWC        QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL___POR     0x00000000
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x000000FF
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL___M       0x000000FF   
#define   WMAC0_CRYPTO_R1_TESTBUS_CTRL___S                     0

#define WMAC0_CRYPTO_R1_TESTBUS_LOWER             (0x00AA8008)
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER___RWC       QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER___POR    0x00000000
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___S               0
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER___M      0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_TESTBUS_LOWER___S                    0

#define WMAC0_CRYPTO_R1_TESTBUS_UPPER             (0x00AA800C)
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER___RWC       QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER___POR    0x00000000
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___S               0
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER___M      0x000000FF   
#define   WMAC0_CRYPTO_R1_TESTBUS_UPPER___S                    0

#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS    (0x00AA8010)
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___POR 0x0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___M 0x00010000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___S              16
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___M 0x00008000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___S              15
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___M 0x00004000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___S              14
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___M 0x00002000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___S              13
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___M 0x00001000
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___S              12
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___M 0x00000800
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___S              11
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___M 0x00000400
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___S              10
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___M 0x00000200
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___S               9
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___M 0x00000100
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___S               8
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___M 0x00000080
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___S               7
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___M 0x00000040
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___S               6
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___M 0x00000020
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___S               5
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___M 0x00000010
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___S               4
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___M 0x00000008
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___S               3
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___M 0x00000004
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___S               2
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___M 0x00000002
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___S               1
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___M 0x00000001
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___S               0
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___M 0x0001FFFF   
#define   WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___S               0

#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE   (0x00AA8014)
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___S               0
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___S               0

#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD (0x00AA8018)
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___S               0
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___S               0

#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL      (0x00AA801C)
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___POR 0x00000021
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___M 0x00004000
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___S              14
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___M 0x00002000
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___S              13
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___M 0x00001000
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___S              12
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___M 0x00000800
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___S              11
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___M 0x00000400
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___S              10
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___M 0x00000200
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___S               9
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___M 0x00000100
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___S               8
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___M 0x00000080
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___S               7
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___M 0x00000040
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___S               6
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___M 0x00000020
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___S               5
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___M 0x00000010
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___S               4
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___M 0x00000008
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___S               3
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___M 0x00000004
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___S               2
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___M 0x00000002
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___S               1
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___M 0x00000001
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___S               0
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___M 0x00007FFF   
#define   WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___S               0

#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT           (0x00AA8020)
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___RWC     QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___POR  0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___S                  0

#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT     (0x00AA8024)
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT      (0x00AA8028)
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___POR 0x0000
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___M 0x0000FFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___M 0x0000FFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT      (0x00AA802C)
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___POR 0x0000
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___M 0x0000FFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___M 0x0000FFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT          (0x00AA8030)
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___RWC    QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___POR 0x0000
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___M 0x0000FFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___M   0x0000FFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___S                 0

#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT           (0x00AA8034)
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___RWC     QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___POR  0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___S                  0

#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT     (0x00AA8038)
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT          (0x00AA803C)
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___RWC    QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___POR 0x0000
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___M 0x0000FFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___M   0x0000FFFF   
#define   WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___S                 0

#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0            (0x00AA8040)
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0___POR   0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___POR 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___S               0
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0___M     0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_0___S                   0

#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1            (0x00AA8044)
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1___RWC      QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1___POR   0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___POR 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___S               0
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1___M     0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_EVENTMASK_IX_1___S                   0

#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT    (0x00AA8048)
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT    (0x00AA804C)
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___S               0

#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT           (0x00AA8050)
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___RWC     QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___POR  0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___S                  0

#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT            (0x00AA8054)
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___RWC      QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___POR   0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___POR 0x00000000
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___M     0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___S                   0

#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT           (0x00AA8058)
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___RWC     QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___POR  0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___POR 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___S               0
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___M    0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___S                  0

#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE (0x00AA805C)
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___S               0
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___S               0

#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD (0x00AA8060)
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___S               0
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___S               0

#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR       (0x00AA8064)
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___POR 0x00000000
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___POR 0x00000000
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___S               0
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___S               0

#define WMAC0_CRYPTO_R1_SM_STATES_IX_1            (0x00AA8068)
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1___RWC      QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1___POR   0x00000000
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___POR 0x0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___POR 0x00
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___M 0x00000E00
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___S               9
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___M 0x00000100
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___S               8
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___M 0x00000080
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___S               7
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___M 0x0000007F
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___S               0
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1___M     0x00000FFF   
#define   WMAC0_CRYPTO_R1_SM_STATES_IX_1___S                   0

#define WMAC0_CRYPTO_R1_BUSY_STATUS               (0x00AA806C)
#define   WMAC0_CRYPTO_R1_BUSY_STATUS___RWC         QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_BUSY_STATUS___POR      0x00000000
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___POR 0x00
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___POR 0x0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___M 0x00020000
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___S              17
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___M 0x00010000
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___S              16
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___M 0x00008000
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___S              15
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___M 0x00004000
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___S              14
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___M 0x00003FC0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___S               6
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___M 0x00000020
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___S               5
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___M 0x00000010
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___S               4
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___M 0x00000008
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___S               3
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___M 0x00000004
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___S               2
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___M 0x00000002
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___S               1
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___M 0x00000001
#define   WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___S               0
#define   WMAC0_CRYPTO_R1_BUSY_STATUS___M        0x0003FFFF   
#define   WMAC0_CRYPTO_R1_BUSY_STATUS___S                      0

#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG           (0x00AA8070)
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG___RWC     QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG___POR  0x00000000
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___POR 0x00
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___POR 0x00
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___M 0x0000FF00
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___S               8
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___M 0x000000FF
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___S               0
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG___M    0x0000FFFF   
#define   WMAC0_CRYPTO_R1_CSB_READ_CONFIG___S                  0

#define WMAC0_CRYPTO_R1_CSB_USER_COUNT            (0x00AA8074)
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT___RWC      QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT___POR   0x00000000
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___POR 0x00
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___POR 0x00
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___M 0x0000FF00
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___S               8
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___M 0x000000FF
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___S               0
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT___M     0x0000FFFF   
#define   WMAC0_CRYPTO_R1_CSB_USER_COUNT___S                   0

#define WMAC0_CRYPTO_R1_TX_WEP_LEN                (0x00AA8078)
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN___RWC          QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN___POR       0x00000000
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___POR 0x0000
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___POR 0x0000
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___M 0xFFFF0000
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___S              16
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___M 0x0000FFFF
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___S               0
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN___M         0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_TX_WEP_LEN___S                       0

#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE   (0x00AA807C)
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___RWC QCSR_REG_RO    
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___S               0
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___S               0

#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD (0x00AA8080)
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___POR 0x00000000
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___M 0xFFFFFFFF
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___S               0
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___S               0

#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AA8084)
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK         (0x00AA8088)
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___RWC   QCSR_REG_RW    
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___M  0x00000001   
#define   WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___S                0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0             (0x00AAA000)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___POR    0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___M      0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___S                    0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2             (0x00AAA004)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___POR    0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___M      0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___S                    0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4             (0x00AAA008)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___POR    0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___M      0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___S                    0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6             (0x00AAA00C)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___POR    0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___M      0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___S                    0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8             (0x00AAA010)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___POR    0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___M      0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___S                    0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10           (0x00AAA014)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___POR  0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___M    0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___S                  0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12           (0x00AAA018)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___POR  0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___M    0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___S                  0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14           (0x00AAA01C)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___POR  0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___M    0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___S                  0

#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16           (0x00AAA020)
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___POR  0x001C0025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___POR 0x01C
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___POR 0x025
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___M 0x03FF0000
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___S              16
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___M 0x000003FF
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___S               0
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___M    0x03FF03FF   
#define   WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___S                  0

#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT   (0x00AAA028)
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___POR 0x00001909
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___POR 0x019
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___POR 0x09
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___M 0x00020000
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___S              17
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___M 0x0001FF00
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___S               8
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___M 0x000000FF
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___S               0
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___S               0

#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1 (0x00AAA02C)
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___POR 0x0000005A
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___POR 0x005A
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___S               0
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___S               0

#define WMAC0_HWSCH_R0_COEX_CTRL                  (0x00AAA030)
#define   WMAC0_HWSCH_R0_COEX_CTRL___RWC            QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_COEX_CTRL___POR         0x00000F18
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___POR 0x0
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___POR 0x0
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___POR 0x0
#define   WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___POR 0x0
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___POR 0x0
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___POR 0x1
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___M 0x00002000
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___S              13
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___M 0x00001000
#define   WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___S              12
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___M 0x00000800
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___S              11
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___M 0x00000400
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___S              10
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___M 0x00000200
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___S               9
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___M 0x00000100
#define   WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___S               8
#define   WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___M 0x00000080
#define   WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___S               7
#define   WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___M 0x00000040
#define   WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___S               6
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___M 0x00000020
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___S               5
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___M 0x00000010
#define   WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___S               4
#define   WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___M 0x00000008
#define   WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___S               3
#define   WMAC0_HWSCH_R0_COEX_CTRL___M           0x00003FF8   
#define   WMAC0_HWSCH_R0_COEX_CTRL___S                         3

#define WMAC0_HWSCH_R0_RID_CNT                    (0x00AAA034)
#define   WMAC0_HWSCH_R0_RID_CNT___RWC              QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_RID_CNT___POR           0x000000FF
#define   WMAC0_HWSCH_R0_RID_CNT__RID_CNT___POR  0x000000FF
#define   WMAC0_HWSCH_R0_RID_CNT__RID_CNT___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RID_CNT__RID_CNT___S                  0
#define   WMAC0_HWSCH_R0_RID_CNT___M             0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_RID_CNT___S                           0

#define WMAC0_HWSCH_R0_NAV_CNT                    (0x00AAA038)
#define   WMAC0_HWSCH_R0_NAV_CNT___RWC              QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_NAV_CNT___POR           0x000000FF
#define   WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___POR  0x000000FF
#define   WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___S                  0
#define   WMAC0_HWSCH_R0_NAV_CNT___M             0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_NAV_CNT___S                           0

#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT      (0x00AAA03C)
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___POR 0x000000FF
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___POR 0x000000FF
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___S               0
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___S               0

#define WMAC0_HWSCH_R0_BKOF_CNT_0                 (0x00AAA040)
#define   WMAC0_HWSCH_R0_BKOF_CNT_0___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_0___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_0___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_0___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_1                 (0x00AAA044)
#define   WMAC0_HWSCH_R0_BKOF_CNT_1___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_1___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_1___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_1___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_2                 (0x00AAA048)
#define   WMAC0_HWSCH_R0_BKOF_CNT_2___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_2___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_2___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_2___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_3                 (0x00AAA04C)
#define   WMAC0_HWSCH_R0_BKOF_CNT_3___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_3___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_3___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_3___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_4                 (0x00AAA050)
#define   WMAC0_HWSCH_R0_BKOF_CNT_4___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_4___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_4___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_4___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_5                 (0x00AAA054)
#define   WMAC0_HWSCH_R0_BKOF_CNT_5___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_5___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_5___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_5___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_6                 (0x00AAA058)
#define   WMAC0_HWSCH_R0_BKOF_CNT_6___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_6___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_6___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_6___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_7                 (0x00AAA05C)
#define   WMAC0_HWSCH_R0_BKOF_CNT_7___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_7___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_7___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_7___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_8                 (0x00AAA060)
#define   WMAC0_HWSCH_R0_BKOF_CNT_8___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_8___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_8___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_8___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_9                 (0x00AAA064)
#define   WMAC0_HWSCH_R0_BKOF_CNT_9___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_9___POR        0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_9___M          0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_9___S                        0

#define WMAC0_HWSCH_R0_BKOF_CNT_10                (0x00AAA068)
#define   WMAC0_HWSCH_R0_BKOF_CNT_10___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_10___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_10___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_10___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_11                (0x00AAA06C)
#define   WMAC0_HWSCH_R0_BKOF_CNT_11___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_11___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_11___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_11___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_12                (0x00AAA070)
#define   WMAC0_HWSCH_R0_BKOF_CNT_12___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_12___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_12___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_12___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_13                (0x00AAA074)
#define   WMAC0_HWSCH_R0_BKOF_CNT_13___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_13___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_13___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_13___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_14                (0x00AAA078)
#define   WMAC0_HWSCH_R0_BKOF_CNT_14___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_14___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_14___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_14___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_15                (0x00AAA07C)
#define   WMAC0_HWSCH_R0_BKOF_CNT_15___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_15___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_15___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_15___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_16                (0x00AAA080)
#define   WMAC0_HWSCH_R0_BKOF_CNT_16___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_16___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_16___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_16___S                       0

#define WMAC0_HWSCH_R0_BKOF_CNT_17                (0x00AAA084)
#define   WMAC0_HWSCH_R0_BKOF_CNT_17___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BKOF_CNT_17___POR       0x00040003
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___POR 0x04
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___POR 0x0003
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___M 0x00FF0000
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___S              16
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___S               0
#define   WMAC0_HWSCH_R0_BKOF_CNT_17___M         0x00FFFFFF   
#define   WMAC0_HWSCH_R0_BKOF_CNT_17___S                       0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0 (0x00AAA090)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1 (0x00AAA094)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2 (0x00AAA098)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3 (0x00AAA09C)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4 (0x00AAA0A0)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5 (0x00AAA0A4)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6 (0x00AAA0A8)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7 (0x00AAA0AC)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8 (0x00AAA0B0)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9 (0x00AAA0B4)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10 (0x00AAA0B8)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11 (0x00AAA0BC)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12 (0x00AAA0C0)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13 (0x00AAA0C4)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14 (0x00AAA0C8)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15 (0x00AAA0CC)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16 (0x00AAA0D0)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___S               0

#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17 (0x00AAA0D4)
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___POR 0x00000007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___POR 0x0007
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___S               0
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0         (0x00AAA0E0)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1         (0x00AAA0E4)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2         (0x00AAA0E8)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___POR 0x00070003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___POR 0x0007
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___POR 0x0003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3         (0x00AAA0EC)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___POR 0x00070003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___POR 0x0007
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___POR 0x0003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4         (0x00AAA0F0)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___POR 0x00070003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___POR 0x0007
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___POR 0x0003
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5         (0x00AAA0F4)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___POR 0x000F0007
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___POR 0x0007
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6         (0x00AAA0F8)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7         (0x00AAA0FC)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8         (0x00AAA100)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9         (0x00AAA104)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___S                0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10        (0x00AAA108)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11        (0x00AAA10C)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12        (0x00AAA110)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13        (0x00AAA114)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14        (0x00AAA118)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15        (0x00AAA11C)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16        (0x00AAA120)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___S               0

#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17        (0x00AAA124)
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___POR 0x03FF000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___POR 0x03FF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___POR 0x000F
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___S              16
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___S               0
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___S               0

#define WMAC0_HWSCH_R0_CW_ACTION_CTRL             (0x00AAA130)
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL___POR    0x00010082
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___POR 0x0010082
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___M 0x0FFFFFFF
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___S               0
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL___M      0x0FFFFFFF   
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL___S                    0

#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0             (0x00AAA134)
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0___POR    0x0000000F
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___POR 0xF
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___M 0x0000000F
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___S               0
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0___M      0x0000000F   
#define   WMAC0_HWSCH_R0_MTU_11AH_CTRL0___S                    0

#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS         (0x00AAA138)
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___POR 0x00000000
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___M 0x00000010
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___S               4
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___M 0x00000008
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___S               3
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___M 0x00000004
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___S               2
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___M 0x00000002
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___S               1
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___M 0x00000001
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___S               0
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___M  0x0000001F   
#define   WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___S                0

#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS        (0x00AAA13C)
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___POR 0x0002BA04
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___POR 0x02BA
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___POR 0x04
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___M 0x007FFF00
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___S               8
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___M 0x000000FF
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___S               0
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___M 0x007FFFFF   
#define   WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___S               0

#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL       (0x00AAA140)
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___POR 0x000105BB
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___POR 0x1
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___POR 0x02DD
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___M 0x00010000
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___S              16
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___M 0x0000FFFE
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___S               1
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___M 0x00000001
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___S               0
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___M 0x0001FFFF   
#define   WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___S               0

#define WMAC0_HWSCH_R0_CCA_COUNTER0               (0x00AAA144)
#define   WMAC0_HWSCH_R0_CCA_COUNTER0___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_COUNTER0___POR      0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___S               0
#define   WMAC0_HWSCH_R0_CCA_COUNTER0___M        0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_COUNTER0___S                      0

#define WMAC0_HWSCH_R0_CCA_COUNTER1               (0x00AAA148)
#define   WMAC0_HWSCH_R0_CCA_COUNTER1___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_COUNTER1___POR      0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___S               0
#define   WMAC0_HWSCH_R0_CCA_COUNTER1___M        0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_COUNTER1___S                      0

#define WMAC0_HWSCH_R0_CCA_COUNTER2               (0x00AAA14C)
#define   WMAC0_HWSCH_R0_CCA_COUNTER2___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_COUNTER2___POR      0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___S               0
#define   WMAC0_HWSCH_R0_CCA_COUNTER2___M        0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_COUNTER2___S                      0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1          (0x00AAA150)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___POR 0x00700000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___POR 0x3
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___POR 0x1
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___POR 0x00000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___M 0x08000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___S              27
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___M 0x04000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___S              26
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___M 0x02000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___S              25
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___M 0x01000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___M 0x00800000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___S              23
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___M 0x00600000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___S              21
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___M 0x00100000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___S              20
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___M   0x0FF3FFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2          (0x00AAA154)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___POR 0x00000219
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___POR 0x000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___POR 0x1
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___POR 0x019
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___M 0x40000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___S              30
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___M 0x20000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___S              29
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___M 0x0F000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___M 0x00800000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___S              23
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___M 0x00400000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___S              22
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___M 0x003FFC00
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___S              10
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___M 0x00000200
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___S               9
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___M 0x000001FF
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___M   0x6FFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3          (0x00AAA158)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___POR 0xBBBBBBBB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___M 0xF0000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___S              28
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___M 0x0F000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___M 0x00F00000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___S              20
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___M 0x000F0000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___S              16
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___M 0x0000F000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___S              12
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___M 0x00000F00
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___S               8
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4          (0x00AAA15C)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___POR 0xBBBBBBBB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___M 0xF0000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___S              28
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___M 0x0F000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___M 0x00F00000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___S              20
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___M 0x000F0000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___S              16
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___M 0x0000F000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___S              12
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___M 0x00000F00
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___S               8
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5          (0x00AAA160)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___M 0xF0000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___S              28
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___M 0x0F000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___M 0x00F00000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___S              20
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___M 0x000F0000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___S              16
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___M 0x0000F000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___S              12
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___M 0x00000F00
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___S               8
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6          (0x00AAA164)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___M 0xF0000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___S              28
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___M 0x0F000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___S              24
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___M 0x00F00000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___S              20
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___M 0x000F0000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___S              16
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___M 0x0000F000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___S              12
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___M 0x00000F00
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___S               8
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7          (0x00AAA168)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___POR 0x000000BB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___POR 0xB
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___M   0x000000FF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8          (0x00AAA16C)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___M 0x000000F0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___S               4
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___M 0x0000000F
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___M   0x000000FF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___S                 0

#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9          (0x00AAA170)
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___POR 0x000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___POR 0x0000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___M 0x7FF80000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___S              19
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___M 0x00040000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___S              18
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___M 0x00020000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___S              17
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___M 0x00010000
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___S              16
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___S               0
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___M   0x7FFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___S                 0

#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL         (0x00AAA174)
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___POR 0x0877500F
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___POR 0x0EE
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___POR 0x00F
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___M 0x30000000
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___S              28
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___M 0x08000000
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___S              27
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___M 0x07FF8000
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___S              15
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___M 0x00004000
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___S              14
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___M 0x00001000
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___S              12
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___M 0x00000FFF
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___S               0
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___M  0x3FFFDFFF   
#define   WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___S                0

#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS            (0x00AAA178)
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS___POR   0x01440111
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___POR 0x0
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___POR 0x05
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___POR 0x04
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___POR 0x01
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___POR 0x11
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___M 0x10000000
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___S              28
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___M 0x0FC00000
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___S              22
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___M 0x003F0000
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___S              16
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___M 0x0000FF00
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___S               8
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___M 0x000000FF
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___S               0
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS___M     0x1FFFFFFF   
#define   WMAC0_HWSCH_R0_PREBKOFF_LIMITS___S                   0

#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS      (0x00AAA17C)
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___POR 0xEC000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___POR 0x4
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___POR 0x00000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___M 0x80000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___S              31
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___M 0x40000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___S              30
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___M 0x20000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___S              29
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___M 0x10000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___S              28
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___M 0x08000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___S              27
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___M 0x07000000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___S              24
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___M 0x00F00000
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___S              20
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___S               0
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___M 0xFFF3FFFF   
#define   WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___S               0

#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0    (0x00AAA180)
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___S               0
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___S               0

#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1    (0x00AAA184)
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___S               0
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___S               0

#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2    (0x00AAA188)
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___S               0
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___S               0

#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3    (0x00AAA18C)
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___S               0
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___S               0

#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4    (0x00AAA190)
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___POR 0x00000000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___POR 0x0000
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___S               0
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___S               0

#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV (0x00AAA194)
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___POR 0x00000A16
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___POR 0x0A16
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___M 0x00007FFF
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___S               0
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___M 0x00007FFF   
#define   WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___S               0

#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW  (0x00AAA198)
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___POR 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___POR 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___S               0
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___S               0

#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH (0x00AAA19C)
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___POR 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___POR 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___S               0
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___S               0

#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0      (0x00AAA1A0)
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___POR 0x0000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___POR 0x0000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___S              16
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___S               0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___S               0

#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1      (0x00AAA1A4)
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___S               0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0 (0x00AAA1A8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1 (0x00AAA1AC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2 (0x00AAA1B0)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3 (0x00AAA1B4)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4 (0x00AAA1B8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5 (0x00AAA1BC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6 (0x00AAA1C0)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7 (0x00AAA1C4)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8 (0x00AAA1C8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9 (0x00AAA1CC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10 (0x00AAA1D0)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11 (0x00AAA1D4)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12 (0x00AAA1D8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13 (0x00AAA1DC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14 (0x00AAA1E0)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15 (0x00AAA1E4)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16 (0x00AAA1E8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17 (0x00AAA1EC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0 (0x00AAA1F8)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1 (0x00AAA1FC)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2 (0x00AAA200)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3 (0x00AAA204)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4 (0x00AAA208)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5 (0x00AAA20C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6 (0x00AAA210)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7 (0x00AAA214)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8 (0x00AAA218)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9 (0x00AAA21C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10 (0x00AAA220)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11 (0x00AAA224)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12 (0x00AAA228)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13 (0x00AAA22C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14 (0x00AAA230)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15 (0x00AAA234)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16 (0x00AAA238)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17 (0x00AAA23C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___POR 0x00000100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___POR 0x0100
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0 (0x00AAA248)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1 (0x00AAA24C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2 (0x00AAA250)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3 (0x00AAA254)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4 (0x00AAA258)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5 (0x00AAA25C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6 (0x00AAA260)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7 (0x00AAA264)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8 (0x00AAA268)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9 (0x00AAA26C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10 (0x00AAA270)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11 (0x00AAA274)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12 (0x00AAA278)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13 (0x00AAA27C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14 (0x00AAA280)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15 (0x00AAA284)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16 (0x00AAA288)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17 (0x00AAA28C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___POR 0x000000F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___POR 0x00F0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB   (0x00AAA298)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY  (0x00AAA29C)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___POR 0x00000800
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___POR 0x0800
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS (0x00AAA2A0)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___POR 0x00010200
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___POR 0x0001
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___POR 0x0200
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___S              16
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___S               0

#define WMAC0_HWSCH_R0_WATCHDOG_TIMER             (0x00AAA2A4)
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER___POR    0x00010000
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___POR 0x010000
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___M 0x003FFFFF
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___S               0
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER___M      0x003FFFFF   
#define   WMAC0_HWSCH_R0_WATCHDOG_TIMER___S                    0

#define WMAC0_HWSCH_R0_AXI_TIMEOUT                (0x00AAA2A8)
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT___POR       0x000001F4
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___POR 0x01F4
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___S               0
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT___M         0x0000FFFF   
#define   WMAC0_HWSCH_R0_AXI_TIMEOUT___S                       0

#define WMAC0_HWSCH_R0_CMD_RING_PAUSE             (0x00AAA2AC)
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE___POR    0x00000000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___M 0x00020000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___S              17
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___M 0x00010000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___S              16
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___M 0x00008000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___S              15
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___M 0x00004000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___S              14
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___M 0x00002000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___S              13
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___M 0x00001000
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___S              12
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___M 0x00000800
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___S              11
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___M 0x00000400
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___S              10
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___M 0x00000200
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___S               9
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___M 0x00000100
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___S               8
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___M 0x00000080
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___S               7
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___M 0x00000040
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___S               6
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___M 0x00000020
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___S               5
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___M 0x00000010
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___S               4
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___M 0x00000008
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___S               3
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___M 0x00000004
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___S               2
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___M 0x00000002
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___S               1
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___M 0x00000001
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___S               0
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE___M      0x0003FFFF   
#define   WMAC0_HWSCH_R0_CMD_RING_PAUSE___S                    0

#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL      (0x00AAA2B0)
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___POR 0x00000003
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___POR 0x1
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___M 0x00000002
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___S               1
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___M 0x00000001
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___S               0
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___M 0x00000003   
#define   WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___S               0

#define WMAC0_HWSCH_R0_SEND_FLUSH                 (0x00AAA2B4)
#define   WMAC0_HWSCH_R0_SEND_FLUSH___RWC           QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SEND_FLUSH___POR        0x00000000
#define   WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___POR 0x0
#define   WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___POR 0x00000
#define   WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___M 0x80000000
#define   WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___S              31
#define   WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___S               0
#define   WMAC0_HWSCH_R0_SEND_FLUSH___M          0x8003FFFF   
#define   WMAC0_HWSCH_R0_SEND_FLUSH___S                        0

#define WMAC0_HWSCH_R0_FLUSH_STATUS               (0x00AAA2B8)
#define   WMAC0_HWSCH_R0_FLUSH_STATUS___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_STATUS___POR      0x00000000
#define   WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___POR 0x0
#define   WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___M 0x00000001
#define   WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___S               0
#define   WMAC0_HWSCH_R0_FLUSH_STATUS___M        0x00000001   
#define   WMAC0_HWSCH_R0_FLUSH_STATUS___S                      0

#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0            (0x00AAA2BC)
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0___POR   0x00000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___M 0x80000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___S              31
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___M 0x00007FFF
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___S               0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0___M     0x80007FFF   
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER0___S                   0

#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1            (0x00AAA2C0)
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1___POR   0x00000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___M 0x80000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___S              31
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___M 0x00007FFF
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___S               0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1___M     0x80007FFF   
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER1___S                   0

#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2            (0x00AAA2C4)
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2___POR   0x00000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___M 0x80000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___S              31
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___M 0x00007FFF
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___S               0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2___M     0x80007FFF   
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER2___S                   0

#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3            (0x00AAA2C8)
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3___POR   0x00000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___M 0x80000000
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___S              31
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___M 0x00007FFF
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___S               0
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3___M     0x80007FFF   
#define   WMAC0_HWSCH_R0_BOUNDARY_TIMER3___S                   0

#define WMAC0_HWSCH_R0_TXOP_CONTROL0              (0x00AAA2CC)
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0___POR     0x03030303
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___M 0xFF000000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___S              24
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___M 0x00FF0000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___S              16
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___M 0x0000FF00
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___S               8
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___M 0x000000FF
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___S               0
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TXOP_CONTROL0___S                     0

#define WMAC0_HWSCH_R0_TXOP_CONTROL1              (0x00AAA2D0)
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1___POR     0x03030303
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___M 0xFF000000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___S              24
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___M 0x00FF0000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___S              16
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___M 0x0000FF00
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___S               8
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___M 0x000000FF
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___S               0
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TXOP_CONTROL1___S                     0

#define WMAC0_HWSCH_R0_TXOP_CONTROL2              (0x00AAA2D4)
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2___POR     0x03030303
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___M 0xFF000000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___S              24
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___M 0x00FF0000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___S              16
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___M 0x0000FF00
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___S               8
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___M 0x000000FF
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___S               0
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TXOP_CONTROL2___S                     0

#define WMAC0_HWSCH_R0_TXOP_CONTROL3              (0x00AAA2D8)
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3___POR     0x03030303
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___M 0xFF000000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___S              24
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___M 0x00FF0000
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___S              16
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___M 0x0000FF00
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___S               8
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___M 0x000000FF
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___S               0
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TXOP_CONTROL3___S                     0

#define WMAC0_HWSCH_R0_TXOP_CONTROL4              (0x00AAA2DC)
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4___POR     0x00000303
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___POR 0x03
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___M 0x0000FF00
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___S               8
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___M 0x000000FF
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___S               0
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4___M       0x0000FFFF   
#define   WMAC0_HWSCH_R0_TXOP_CONTROL4___S                     0

#define WMAC0_HWSCH_R0_TESTBUS_CTRL               (0x00AAA2E0)
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL___POR      0x00000000
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___POR 0x00
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___POR 0x0
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___M 0x000003F0
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___S               4
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___M 0x0000000F
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___S               0
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL___M        0x000003FF   
#define   WMAC0_HWSCH_R0_TESTBUS_CTRL___S                      0

#define WMAC0_HWSCH_R0_TESTBUS_n(n)      (0x00AAA2E4+0x4*(n))
#define   WMAC0_HWSCH_R0_TESTBUS_n_nMIN 0    
#define   WMAC0_HWSCH_R0_TESTBUS_n_nMAX 2047 
#define   WMAC0_HWSCH_R0_TESTBUS_n_ELEM 2048 
#define   WMAC0_HWSCH_R0_TESTBUS_n___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_n___POR         0x00000000
#define   WMAC0_HWSCH_R0_TESTBUS_n__DATA___POR   0x00000000
#define   WMAC0_HWSCH_R0_TESTBUS_n__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_n__DATA___S                   0
#define   WMAC0_HWSCH_R0_TESTBUS_n___M           0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TESTBUS_n___S                         0
#define WMAC0_HWSCH_R0_TESTBUS_0                  (0x00AAA2E4)
#define   WMAC0_HWSCH_R0_TESTBUS_0___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_0__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_0__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_1                  (0x00AAA2E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_2                  (0x00AAA2EC)
#define   WMAC0_HWSCH_R0_TESTBUS_2___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_3                  (0x00AAA2F0)
#define   WMAC0_HWSCH_R0_TESTBUS_3___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_3__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_3__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_4                  (0x00AAA2F4)
#define   WMAC0_HWSCH_R0_TESTBUS_4___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_4__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_4__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_5                  (0x00AAA2F8)
#define   WMAC0_HWSCH_R0_TESTBUS_5___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_5__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_5__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_6                  (0x00AAA2FC)
#define   WMAC0_HWSCH_R0_TESTBUS_6___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_6__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_6__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_7                  (0x00AAA300)
#define   WMAC0_HWSCH_R0_TESTBUS_7___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_7__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_7__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_8                  (0x00AAA304)
#define   WMAC0_HWSCH_R0_TESTBUS_8___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_8__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_8__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_9                  (0x00AAA308)
#define   WMAC0_HWSCH_R0_TESTBUS_9___RWC            QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_9__DATA___M     0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_9__DATA___S                   0
#define WMAC0_HWSCH_R0_TESTBUS_10                 (0x00AAA30C)
#define   WMAC0_HWSCH_R0_TESTBUS_10___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_10__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_10__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_11                 (0x00AAA310)
#define   WMAC0_HWSCH_R0_TESTBUS_11___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_11__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_11__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_12                 (0x00AAA314)
#define   WMAC0_HWSCH_R0_TESTBUS_12___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_12__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_12__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_13                 (0x00AAA318)
#define   WMAC0_HWSCH_R0_TESTBUS_13___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_13__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_13__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_14                 (0x00AAA31C)
#define   WMAC0_HWSCH_R0_TESTBUS_14___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_14__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_14__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_15                 (0x00AAA320)
#define   WMAC0_HWSCH_R0_TESTBUS_15___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_15__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_15__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_16                 (0x00AAA324)
#define   WMAC0_HWSCH_R0_TESTBUS_16___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_16__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_16__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_17                 (0x00AAA328)
#define   WMAC0_HWSCH_R0_TESTBUS_17___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_17__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_17__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_18                 (0x00AAA32C)
#define   WMAC0_HWSCH_R0_TESTBUS_18___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_18__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_18__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_19                 (0x00AAA330)
#define   WMAC0_HWSCH_R0_TESTBUS_19___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_19__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_19__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_20                 (0x00AAA334)
#define   WMAC0_HWSCH_R0_TESTBUS_20___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_20__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_20__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_21                 (0x00AAA338)
#define   WMAC0_HWSCH_R0_TESTBUS_21___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_21__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_21__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_22                 (0x00AAA33C)
#define   WMAC0_HWSCH_R0_TESTBUS_22___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_22__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_22__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_23                 (0x00AAA340)
#define   WMAC0_HWSCH_R0_TESTBUS_23___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_23__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_23__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_24                 (0x00AAA344)
#define   WMAC0_HWSCH_R0_TESTBUS_24___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_24__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_24__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_25                 (0x00AAA348)
#define   WMAC0_HWSCH_R0_TESTBUS_25___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_25__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_25__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_26                 (0x00AAA34C)
#define   WMAC0_HWSCH_R0_TESTBUS_26___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_26__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_26__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_27                 (0x00AAA350)
#define   WMAC0_HWSCH_R0_TESTBUS_27___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_27__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_27__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_28                 (0x00AAA354)
#define   WMAC0_HWSCH_R0_TESTBUS_28___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_28__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_28__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_29                 (0x00AAA358)
#define   WMAC0_HWSCH_R0_TESTBUS_29___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_29__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_29__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_30                 (0x00AAA35C)
#define   WMAC0_HWSCH_R0_TESTBUS_30___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_30__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_30__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_31                 (0x00AAA360)
#define   WMAC0_HWSCH_R0_TESTBUS_31___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_31__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_31__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_32                 (0x00AAA364)
#define   WMAC0_HWSCH_R0_TESTBUS_32___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_32__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_32__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_33                 (0x00AAA368)
#define   WMAC0_HWSCH_R0_TESTBUS_33___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_33__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_33__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_34                 (0x00AAA36C)
#define   WMAC0_HWSCH_R0_TESTBUS_34___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_34__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_34__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_35                 (0x00AAA370)
#define   WMAC0_HWSCH_R0_TESTBUS_35___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_35__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_35__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_36                 (0x00AAA374)
#define   WMAC0_HWSCH_R0_TESTBUS_36___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_36__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_36__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_37                 (0x00AAA378)
#define   WMAC0_HWSCH_R0_TESTBUS_37___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_37__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_37__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_38                 (0x00AAA37C)
#define   WMAC0_HWSCH_R0_TESTBUS_38___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_38__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_38__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_39                 (0x00AAA380)
#define   WMAC0_HWSCH_R0_TESTBUS_39___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_39__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_39__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_40                 (0x00AAA384)
#define   WMAC0_HWSCH_R0_TESTBUS_40___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_40__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_40__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_41                 (0x00AAA388)
#define   WMAC0_HWSCH_R0_TESTBUS_41___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_41__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_41__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_42                 (0x00AAA38C)
#define   WMAC0_HWSCH_R0_TESTBUS_42___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_42__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_42__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_43                 (0x00AAA390)
#define   WMAC0_HWSCH_R0_TESTBUS_43___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_43__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_43__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_44                 (0x00AAA394)
#define   WMAC0_HWSCH_R0_TESTBUS_44___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_44__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_44__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_45                 (0x00AAA398)
#define   WMAC0_HWSCH_R0_TESTBUS_45___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_45__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_45__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_46                 (0x00AAA39C)
#define   WMAC0_HWSCH_R0_TESTBUS_46___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_46__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_46__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_47                 (0x00AAA3A0)
#define   WMAC0_HWSCH_R0_TESTBUS_47___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_47__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_47__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_48                 (0x00AAA3A4)
#define   WMAC0_HWSCH_R0_TESTBUS_48___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_48__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_48__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_49                 (0x00AAA3A8)
#define   WMAC0_HWSCH_R0_TESTBUS_49___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_49__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_49__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_50                 (0x00AAA3AC)
#define   WMAC0_HWSCH_R0_TESTBUS_50___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_50__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_50__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_51                 (0x00AAA3B0)
#define   WMAC0_HWSCH_R0_TESTBUS_51___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_51__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_51__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_52                 (0x00AAA3B4)
#define   WMAC0_HWSCH_R0_TESTBUS_52___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_52__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_52__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_53                 (0x00AAA3B8)
#define   WMAC0_HWSCH_R0_TESTBUS_53___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_53__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_53__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_54                 (0x00AAA3BC)
#define   WMAC0_HWSCH_R0_TESTBUS_54___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_54__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_54__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_55                 (0x00AAA3C0)
#define   WMAC0_HWSCH_R0_TESTBUS_55___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_55__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_55__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_56                 (0x00AAA3C4)
#define   WMAC0_HWSCH_R0_TESTBUS_56___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_56__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_56__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_57                 (0x00AAA3C8)
#define   WMAC0_HWSCH_R0_TESTBUS_57___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_57__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_57__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_58                 (0x00AAA3CC)
#define   WMAC0_HWSCH_R0_TESTBUS_58___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_58__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_58__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_59                 (0x00AAA3D0)
#define   WMAC0_HWSCH_R0_TESTBUS_59___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_59__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_59__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_60                 (0x00AAA3D4)
#define   WMAC0_HWSCH_R0_TESTBUS_60___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_60__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_60__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_61                 (0x00AAA3D8)
#define   WMAC0_HWSCH_R0_TESTBUS_61___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_61__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_61__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_62                 (0x00AAA3DC)
#define   WMAC0_HWSCH_R0_TESTBUS_62___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_62__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_62__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_63                 (0x00AAA3E0)
#define   WMAC0_HWSCH_R0_TESTBUS_63___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_63__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_63__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_64                 (0x00AAA3E4)
#define   WMAC0_HWSCH_R0_TESTBUS_64___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_64__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_64__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_65                 (0x00AAA3E8)
#define   WMAC0_HWSCH_R0_TESTBUS_65___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_65__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_65__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_66                 (0x00AAA3EC)
#define   WMAC0_HWSCH_R0_TESTBUS_66___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_66__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_66__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_67                 (0x00AAA3F0)
#define   WMAC0_HWSCH_R0_TESTBUS_67___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_67__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_67__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_68                 (0x00AAA3F4)
#define   WMAC0_HWSCH_R0_TESTBUS_68___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_68__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_68__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_69                 (0x00AAA3F8)
#define   WMAC0_HWSCH_R0_TESTBUS_69___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_69__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_69__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_70                 (0x00AAA3FC)
#define   WMAC0_HWSCH_R0_TESTBUS_70___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_70__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_70__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_71                 (0x00AAA400)
#define   WMAC0_HWSCH_R0_TESTBUS_71___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_71__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_71__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_72                 (0x00AAA404)
#define   WMAC0_HWSCH_R0_TESTBUS_72___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_72__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_72__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_73                 (0x00AAA408)
#define   WMAC0_HWSCH_R0_TESTBUS_73___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_73__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_73__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_74                 (0x00AAA40C)
#define   WMAC0_HWSCH_R0_TESTBUS_74___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_74__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_74__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_75                 (0x00AAA410)
#define   WMAC0_HWSCH_R0_TESTBUS_75___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_75__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_75__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_76                 (0x00AAA414)
#define   WMAC0_HWSCH_R0_TESTBUS_76___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_76__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_76__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_77                 (0x00AAA418)
#define   WMAC0_HWSCH_R0_TESTBUS_77___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_77__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_77__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_78                 (0x00AAA41C)
#define   WMAC0_HWSCH_R0_TESTBUS_78___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_78__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_78__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_79                 (0x00AAA420)
#define   WMAC0_HWSCH_R0_TESTBUS_79___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_79__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_79__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_80                 (0x00AAA424)
#define   WMAC0_HWSCH_R0_TESTBUS_80___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_80__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_80__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_81                 (0x00AAA428)
#define   WMAC0_HWSCH_R0_TESTBUS_81___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_81__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_81__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_82                 (0x00AAA42C)
#define   WMAC0_HWSCH_R0_TESTBUS_82___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_82__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_82__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_83                 (0x00AAA430)
#define   WMAC0_HWSCH_R0_TESTBUS_83___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_83__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_83__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_84                 (0x00AAA434)
#define   WMAC0_HWSCH_R0_TESTBUS_84___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_84__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_84__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_85                 (0x00AAA438)
#define   WMAC0_HWSCH_R0_TESTBUS_85___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_85__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_85__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_86                 (0x00AAA43C)
#define   WMAC0_HWSCH_R0_TESTBUS_86___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_86__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_86__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_87                 (0x00AAA440)
#define   WMAC0_HWSCH_R0_TESTBUS_87___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_87__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_87__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_88                 (0x00AAA444)
#define   WMAC0_HWSCH_R0_TESTBUS_88___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_88__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_88__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_89                 (0x00AAA448)
#define   WMAC0_HWSCH_R0_TESTBUS_89___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_89__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_89__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_90                 (0x00AAA44C)
#define   WMAC0_HWSCH_R0_TESTBUS_90___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_90__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_90__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_91                 (0x00AAA450)
#define   WMAC0_HWSCH_R0_TESTBUS_91___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_91__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_91__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_92                 (0x00AAA454)
#define   WMAC0_HWSCH_R0_TESTBUS_92___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_92__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_92__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_93                 (0x00AAA458)
#define   WMAC0_HWSCH_R0_TESTBUS_93___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_93__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_93__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_94                 (0x00AAA45C)
#define   WMAC0_HWSCH_R0_TESTBUS_94___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_94__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_94__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_95                 (0x00AAA460)
#define   WMAC0_HWSCH_R0_TESTBUS_95___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_95__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_95__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_96                 (0x00AAA464)
#define   WMAC0_HWSCH_R0_TESTBUS_96___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_96__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_96__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_97                 (0x00AAA468)
#define   WMAC0_HWSCH_R0_TESTBUS_97___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_97__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_97__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_98                 (0x00AAA46C)
#define   WMAC0_HWSCH_R0_TESTBUS_98___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_98__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_98__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_99                 (0x00AAA470)
#define   WMAC0_HWSCH_R0_TESTBUS_99___RWC           QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_99__DATA___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_99__DATA___S                  0
#define WMAC0_HWSCH_R0_TESTBUS_100                (0x00AAA474)
#define   WMAC0_HWSCH_R0_TESTBUS_100___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_100__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_100__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_101                (0x00AAA478)
#define   WMAC0_HWSCH_R0_TESTBUS_101___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_101__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_101__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_102                (0x00AAA47C)
#define   WMAC0_HWSCH_R0_TESTBUS_102___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_102__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_102__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_103                (0x00AAA480)
#define   WMAC0_HWSCH_R0_TESTBUS_103___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_103__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_103__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_104                (0x00AAA484)
#define   WMAC0_HWSCH_R0_TESTBUS_104___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_104__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_104__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_105                (0x00AAA488)
#define   WMAC0_HWSCH_R0_TESTBUS_105___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_105__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_105__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_106                (0x00AAA48C)
#define   WMAC0_HWSCH_R0_TESTBUS_106___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_106__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_106__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_107                (0x00AAA490)
#define   WMAC0_HWSCH_R0_TESTBUS_107___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_107__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_107__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_108                (0x00AAA494)
#define   WMAC0_HWSCH_R0_TESTBUS_108___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_108__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_108__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_109                (0x00AAA498)
#define   WMAC0_HWSCH_R0_TESTBUS_109___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_109__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_109__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_110                (0x00AAA49C)
#define   WMAC0_HWSCH_R0_TESTBUS_110___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_110__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_110__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_111                (0x00AAA4A0)
#define   WMAC0_HWSCH_R0_TESTBUS_111___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_111__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_111__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_112                (0x00AAA4A4)
#define   WMAC0_HWSCH_R0_TESTBUS_112___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_112__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_112__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_113                (0x00AAA4A8)
#define   WMAC0_HWSCH_R0_TESTBUS_113___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_113__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_113__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_114                (0x00AAA4AC)
#define   WMAC0_HWSCH_R0_TESTBUS_114___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_114__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_114__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_115                (0x00AAA4B0)
#define   WMAC0_HWSCH_R0_TESTBUS_115___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_115__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_115__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_116                (0x00AAA4B4)
#define   WMAC0_HWSCH_R0_TESTBUS_116___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_116__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_116__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_117                (0x00AAA4B8)
#define   WMAC0_HWSCH_R0_TESTBUS_117___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_117__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_117__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_118                (0x00AAA4BC)
#define   WMAC0_HWSCH_R0_TESTBUS_118___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_118__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_118__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_119                (0x00AAA4C0)
#define   WMAC0_HWSCH_R0_TESTBUS_119___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_119__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_119__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_120                (0x00AAA4C4)
#define   WMAC0_HWSCH_R0_TESTBUS_120___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_120__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_120__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_121                (0x00AAA4C8)
#define   WMAC0_HWSCH_R0_TESTBUS_121___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_121__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_121__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_122                (0x00AAA4CC)
#define   WMAC0_HWSCH_R0_TESTBUS_122___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_122__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_122__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_123                (0x00AAA4D0)
#define   WMAC0_HWSCH_R0_TESTBUS_123___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_123__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_123__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_124                (0x00AAA4D4)
#define   WMAC0_HWSCH_R0_TESTBUS_124___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_124__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_124__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_125                (0x00AAA4D8)
#define   WMAC0_HWSCH_R0_TESTBUS_125___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_125__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_125__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_126                (0x00AAA4DC)
#define   WMAC0_HWSCH_R0_TESTBUS_126___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_126__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_126__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_127                (0x00AAA4E0)
#define   WMAC0_HWSCH_R0_TESTBUS_127___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_127__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_127__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_128                (0x00AAA4E4)
#define   WMAC0_HWSCH_R0_TESTBUS_128___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_128__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_128__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_129                (0x00AAA4E8)
#define   WMAC0_HWSCH_R0_TESTBUS_129___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_129__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_129__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_130                (0x00AAA4EC)
#define   WMAC0_HWSCH_R0_TESTBUS_130___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_130__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_130__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_131                (0x00AAA4F0)
#define   WMAC0_HWSCH_R0_TESTBUS_131___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_131__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_131__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_132                (0x00AAA4F4)
#define   WMAC0_HWSCH_R0_TESTBUS_132___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_132__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_132__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_133                (0x00AAA4F8)
#define   WMAC0_HWSCH_R0_TESTBUS_133___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_133__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_133__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_134                (0x00AAA4FC)
#define   WMAC0_HWSCH_R0_TESTBUS_134___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_134__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_134__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_135                (0x00AAA500)
#define   WMAC0_HWSCH_R0_TESTBUS_135___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_135__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_135__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_136                (0x00AAA504)
#define   WMAC0_HWSCH_R0_TESTBUS_136___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_136__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_136__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_137                (0x00AAA508)
#define   WMAC0_HWSCH_R0_TESTBUS_137___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_137__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_137__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_138                (0x00AAA50C)
#define   WMAC0_HWSCH_R0_TESTBUS_138___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_138__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_138__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_139                (0x00AAA510)
#define   WMAC0_HWSCH_R0_TESTBUS_139___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_139__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_139__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_140                (0x00AAA514)
#define   WMAC0_HWSCH_R0_TESTBUS_140___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_140__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_140__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_141                (0x00AAA518)
#define   WMAC0_HWSCH_R0_TESTBUS_141___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_141__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_141__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_142                (0x00AAA51C)
#define   WMAC0_HWSCH_R0_TESTBUS_142___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_142__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_142__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_143                (0x00AAA520)
#define   WMAC0_HWSCH_R0_TESTBUS_143___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_143__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_143__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_144                (0x00AAA524)
#define   WMAC0_HWSCH_R0_TESTBUS_144___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_144__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_144__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_145                (0x00AAA528)
#define   WMAC0_HWSCH_R0_TESTBUS_145___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_145__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_145__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_146                (0x00AAA52C)
#define   WMAC0_HWSCH_R0_TESTBUS_146___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_146__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_146__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_147                (0x00AAA530)
#define   WMAC0_HWSCH_R0_TESTBUS_147___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_147__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_147__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_148                (0x00AAA534)
#define   WMAC0_HWSCH_R0_TESTBUS_148___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_148__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_148__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_149                (0x00AAA538)
#define   WMAC0_HWSCH_R0_TESTBUS_149___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_149__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_149__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_150                (0x00AAA53C)
#define   WMAC0_HWSCH_R0_TESTBUS_150___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_150__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_150__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_151                (0x00AAA540)
#define   WMAC0_HWSCH_R0_TESTBUS_151___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_151__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_151__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_152                (0x00AAA544)
#define   WMAC0_HWSCH_R0_TESTBUS_152___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_152__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_152__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_153                (0x00AAA548)
#define   WMAC0_HWSCH_R0_TESTBUS_153___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_153__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_153__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_154                (0x00AAA54C)
#define   WMAC0_HWSCH_R0_TESTBUS_154___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_154__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_154__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_155                (0x00AAA550)
#define   WMAC0_HWSCH_R0_TESTBUS_155___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_155__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_155__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_156                (0x00AAA554)
#define   WMAC0_HWSCH_R0_TESTBUS_156___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_156__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_156__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_157                (0x00AAA558)
#define   WMAC0_HWSCH_R0_TESTBUS_157___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_157__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_157__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_158                (0x00AAA55C)
#define   WMAC0_HWSCH_R0_TESTBUS_158___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_158__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_158__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_159                (0x00AAA560)
#define   WMAC0_HWSCH_R0_TESTBUS_159___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_159__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_159__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_160                (0x00AAA564)
#define   WMAC0_HWSCH_R0_TESTBUS_160___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_160__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_160__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_161                (0x00AAA568)
#define   WMAC0_HWSCH_R0_TESTBUS_161___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_161__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_161__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_162                (0x00AAA56C)
#define   WMAC0_HWSCH_R0_TESTBUS_162___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_162__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_162__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_163                (0x00AAA570)
#define   WMAC0_HWSCH_R0_TESTBUS_163___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_163__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_163__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_164                (0x00AAA574)
#define   WMAC0_HWSCH_R0_TESTBUS_164___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_164__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_164__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_165                (0x00AAA578)
#define   WMAC0_HWSCH_R0_TESTBUS_165___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_165__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_165__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_166                (0x00AAA57C)
#define   WMAC0_HWSCH_R0_TESTBUS_166___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_166__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_166__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_167                (0x00AAA580)
#define   WMAC0_HWSCH_R0_TESTBUS_167___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_167__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_167__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_168                (0x00AAA584)
#define   WMAC0_HWSCH_R0_TESTBUS_168___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_168__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_168__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_169                (0x00AAA588)
#define   WMAC0_HWSCH_R0_TESTBUS_169___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_169__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_169__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_170                (0x00AAA58C)
#define   WMAC0_HWSCH_R0_TESTBUS_170___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_170__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_170__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_171                (0x00AAA590)
#define   WMAC0_HWSCH_R0_TESTBUS_171___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_171__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_171__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_172                (0x00AAA594)
#define   WMAC0_HWSCH_R0_TESTBUS_172___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_172__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_172__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_173                (0x00AAA598)
#define   WMAC0_HWSCH_R0_TESTBUS_173___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_173__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_173__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_174                (0x00AAA59C)
#define   WMAC0_HWSCH_R0_TESTBUS_174___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_174__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_174__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_175                (0x00AAA5A0)
#define   WMAC0_HWSCH_R0_TESTBUS_175___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_175__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_175__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_176                (0x00AAA5A4)
#define   WMAC0_HWSCH_R0_TESTBUS_176___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_176__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_176__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_177                (0x00AAA5A8)
#define   WMAC0_HWSCH_R0_TESTBUS_177___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_177__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_177__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_178                (0x00AAA5AC)
#define   WMAC0_HWSCH_R0_TESTBUS_178___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_178__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_178__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_179                (0x00AAA5B0)
#define   WMAC0_HWSCH_R0_TESTBUS_179___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_179__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_179__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_180                (0x00AAA5B4)
#define   WMAC0_HWSCH_R0_TESTBUS_180___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_180__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_180__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_181                (0x00AAA5B8)
#define   WMAC0_HWSCH_R0_TESTBUS_181___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_181__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_181__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_182                (0x00AAA5BC)
#define   WMAC0_HWSCH_R0_TESTBUS_182___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_182__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_182__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_183                (0x00AAA5C0)
#define   WMAC0_HWSCH_R0_TESTBUS_183___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_183__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_183__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_184                (0x00AAA5C4)
#define   WMAC0_HWSCH_R0_TESTBUS_184___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_184__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_184__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_185                (0x00AAA5C8)
#define   WMAC0_HWSCH_R0_TESTBUS_185___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_185__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_185__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_186                (0x00AAA5CC)
#define   WMAC0_HWSCH_R0_TESTBUS_186___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_186__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_186__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_187                (0x00AAA5D0)
#define   WMAC0_HWSCH_R0_TESTBUS_187___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_187__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_187__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_188                (0x00AAA5D4)
#define   WMAC0_HWSCH_R0_TESTBUS_188___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_188__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_188__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_189                (0x00AAA5D8)
#define   WMAC0_HWSCH_R0_TESTBUS_189___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_189__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_189__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_190                (0x00AAA5DC)
#define   WMAC0_HWSCH_R0_TESTBUS_190___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_190__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_190__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_191                (0x00AAA5E0)
#define   WMAC0_HWSCH_R0_TESTBUS_191___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_191__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_191__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_192                (0x00AAA5E4)
#define   WMAC0_HWSCH_R0_TESTBUS_192___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_192__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_192__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_193                (0x00AAA5E8)
#define   WMAC0_HWSCH_R0_TESTBUS_193___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_193__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_193__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_194                (0x00AAA5EC)
#define   WMAC0_HWSCH_R0_TESTBUS_194___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_194__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_194__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_195                (0x00AAA5F0)
#define   WMAC0_HWSCH_R0_TESTBUS_195___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_195__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_195__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_196                (0x00AAA5F4)
#define   WMAC0_HWSCH_R0_TESTBUS_196___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_196__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_196__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_197                (0x00AAA5F8)
#define   WMAC0_HWSCH_R0_TESTBUS_197___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_197__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_197__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_198                (0x00AAA5FC)
#define   WMAC0_HWSCH_R0_TESTBUS_198___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_198__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_198__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_199                (0x00AAA600)
#define   WMAC0_HWSCH_R0_TESTBUS_199___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_199__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_199__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_200                (0x00AAA604)
#define   WMAC0_HWSCH_R0_TESTBUS_200___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_200__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_200__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_201                (0x00AAA608)
#define   WMAC0_HWSCH_R0_TESTBUS_201___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_201__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_201__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_202                (0x00AAA60C)
#define   WMAC0_HWSCH_R0_TESTBUS_202___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_202__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_202__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_203                (0x00AAA610)
#define   WMAC0_HWSCH_R0_TESTBUS_203___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_203__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_203__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_204                (0x00AAA614)
#define   WMAC0_HWSCH_R0_TESTBUS_204___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_204__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_204__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_205                (0x00AAA618)
#define   WMAC0_HWSCH_R0_TESTBUS_205___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_205__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_205__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_206                (0x00AAA61C)
#define   WMAC0_HWSCH_R0_TESTBUS_206___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_206__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_206__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_207                (0x00AAA620)
#define   WMAC0_HWSCH_R0_TESTBUS_207___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_207__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_207__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_208                (0x00AAA624)
#define   WMAC0_HWSCH_R0_TESTBUS_208___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_208__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_208__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_209                (0x00AAA628)
#define   WMAC0_HWSCH_R0_TESTBUS_209___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_209__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_209__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_210                (0x00AAA62C)
#define   WMAC0_HWSCH_R0_TESTBUS_210___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_210__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_210__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_211                (0x00AAA630)
#define   WMAC0_HWSCH_R0_TESTBUS_211___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_211__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_211__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_212                (0x00AAA634)
#define   WMAC0_HWSCH_R0_TESTBUS_212___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_212__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_212__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_213                (0x00AAA638)
#define   WMAC0_HWSCH_R0_TESTBUS_213___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_213__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_213__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_214                (0x00AAA63C)
#define   WMAC0_HWSCH_R0_TESTBUS_214___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_214__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_214__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_215                (0x00AAA640)
#define   WMAC0_HWSCH_R0_TESTBUS_215___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_215__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_215__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_216                (0x00AAA644)
#define   WMAC0_HWSCH_R0_TESTBUS_216___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_216__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_216__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_217                (0x00AAA648)
#define   WMAC0_HWSCH_R0_TESTBUS_217___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_217__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_217__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_218                (0x00AAA64C)
#define   WMAC0_HWSCH_R0_TESTBUS_218___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_218__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_218__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_219                (0x00AAA650)
#define   WMAC0_HWSCH_R0_TESTBUS_219___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_219__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_219__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_220                (0x00AAA654)
#define   WMAC0_HWSCH_R0_TESTBUS_220___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_220__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_220__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_221                (0x00AAA658)
#define   WMAC0_HWSCH_R0_TESTBUS_221___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_221__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_221__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_222                (0x00AAA65C)
#define   WMAC0_HWSCH_R0_TESTBUS_222___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_222__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_222__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_223                (0x00AAA660)
#define   WMAC0_HWSCH_R0_TESTBUS_223___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_223__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_223__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_224                (0x00AAA664)
#define   WMAC0_HWSCH_R0_TESTBUS_224___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_224__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_224__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_225                (0x00AAA668)
#define   WMAC0_HWSCH_R0_TESTBUS_225___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_225__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_225__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_226                (0x00AAA66C)
#define   WMAC0_HWSCH_R0_TESTBUS_226___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_226__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_226__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_227                (0x00AAA670)
#define   WMAC0_HWSCH_R0_TESTBUS_227___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_227__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_227__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_228                (0x00AAA674)
#define   WMAC0_HWSCH_R0_TESTBUS_228___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_228__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_228__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_229                (0x00AAA678)
#define   WMAC0_HWSCH_R0_TESTBUS_229___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_229__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_229__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_230                (0x00AAA67C)
#define   WMAC0_HWSCH_R0_TESTBUS_230___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_230__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_230__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_231                (0x00AAA680)
#define   WMAC0_HWSCH_R0_TESTBUS_231___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_231__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_231__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_232                (0x00AAA684)
#define   WMAC0_HWSCH_R0_TESTBUS_232___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_232__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_232__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_233                (0x00AAA688)
#define   WMAC0_HWSCH_R0_TESTBUS_233___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_233__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_233__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_234                (0x00AAA68C)
#define   WMAC0_HWSCH_R0_TESTBUS_234___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_234__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_234__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_235                (0x00AAA690)
#define   WMAC0_HWSCH_R0_TESTBUS_235___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_235__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_235__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_236                (0x00AAA694)
#define   WMAC0_HWSCH_R0_TESTBUS_236___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_236__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_236__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_237                (0x00AAA698)
#define   WMAC0_HWSCH_R0_TESTBUS_237___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_237__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_237__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_238                (0x00AAA69C)
#define   WMAC0_HWSCH_R0_TESTBUS_238___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_238__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_238__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_239                (0x00AAA6A0)
#define   WMAC0_HWSCH_R0_TESTBUS_239___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_239__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_239__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_240                (0x00AAA6A4)
#define   WMAC0_HWSCH_R0_TESTBUS_240___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_240__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_240__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_241                (0x00AAA6A8)
#define   WMAC0_HWSCH_R0_TESTBUS_241___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_241__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_241__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_242                (0x00AAA6AC)
#define   WMAC0_HWSCH_R0_TESTBUS_242___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_242__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_242__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_243                (0x00AAA6B0)
#define   WMAC0_HWSCH_R0_TESTBUS_243___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_243__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_243__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_244                (0x00AAA6B4)
#define   WMAC0_HWSCH_R0_TESTBUS_244___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_244__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_244__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_245                (0x00AAA6B8)
#define   WMAC0_HWSCH_R0_TESTBUS_245___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_245__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_245__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_246                (0x00AAA6BC)
#define   WMAC0_HWSCH_R0_TESTBUS_246___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_246__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_246__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_247                (0x00AAA6C0)
#define   WMAC0_HWSCH_R0_TESTBUS_247___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_247__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_247__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_248                (0x00AAA6C4)
#define   WMAC0_HWSCH_R0_TESTBUS_248___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_248__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_248__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_249                (0x00AAA6C8)
#define   WMAC0_HWSCH_R0_TESTBUS_249___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_249__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_249__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_250                (0x00AAA6CC)
#define   WMAC0_HWSCH_R0_TESTBUS_250___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_250__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_250__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_251                (0x00AAA6D0)
#define   WMAC0_HWSCH_R0_TESTBUS_251___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_251__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_251__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_252                (0x00AAA6D4)
#define   WMAC0_HWSCH_R0_TESTBUS_252___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_252__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_252__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_253                (0x00AAA6D8)
#define   WMAC0_HWSCH_R0_TESTBUS_253___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_253__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_253__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_254                (0x00AAA6DC)
#define   WMAC0_HWSCH_R0_TESTBUS_254___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_254__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_254__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_255                (0x00AAA6E0)
#define   WMAC0_HWSCH_R0_TESTBUS_255___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_255__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_255__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_256                (0x00AAA6E4)
#define   WMAC0_HWSCH_R0_TESTBUS_256___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_256__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_256__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_257                (0x00AAA6E8)
#define   WMAC0_HWSCH_R0_TESTBUS_257___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_257__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_257__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_258                (0x00AAA6EC)
#define   WMAC0_HWSCH_R0_TESTBUS_258___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_258__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_258__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_259                (0x00AAA6F0)
#define   WMAC0_HWSCH_R0_TESTBUS_259___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_259__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_259__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_260                (0x00AAA6F4)
#define   WMAC0_HWSCH_R0_TESTBUS_260___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_260__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_260__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_261                (0x00AAA6F8)
#define   WMAC0_HWSCH_R0_TESTBUS_261___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_261__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_261__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_262                (0x00AAA6FC)
#define   WMAC0_HWSCH_R0_TESTBUS_262___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_262__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_262__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_263                (0x00AAA700)
#define   WMAC0_HWSCH_R0_TESTBUS_263___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_263__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_263__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_264                (0x00AAA704)
#define   WMAC0_HWSCH_R0_TESTBUS_264___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_264__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_264__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_265                (0x00AAA708)
#define   WMAC0_HWSCH_R0_TESTBUS_265___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_265__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_265__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_266                (0x00AAA70C)
#define   WMAC0_HWSCH_R0_TESTBUS_266___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_266__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_266__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_267                (0x00AAA710)
#define   WMAC0_HWSCH_R0_TESTBUS_267___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_267__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_267__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_268                (0x00AAA714)
#define   WMAC0_HWSCH_R0_TESTBUS_268___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_268__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_268__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_269                (0x00AAA718)
#define   WMAC0_HWSCH_R0_TESTBUS_269___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_269__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_269__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_270                (0x00AAA71C)
#define   WMAC0_HWSCH_R0_TESTBUS_270___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_270__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_270__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_271                (0x00AAA720)
#define   WMAC0_HWSCH_R0_TESTBUS_271___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_271__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_271__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_272                (0x00AAA724)
#define   WMAC0_HWSCH_R0_TESTBUS_272___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_272__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_272__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_273                (0x00AAA728)
#define   WMAC0_HWSCH_R0_TESTBUS_273___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_273__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_273__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_274                (0x00AAA72C)
#define   WMAC0_HWSCH_R0_TESTBUS_274___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_274__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_274__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_275                (0x00AAA730)
#define   WMAC0_HWSCH_R0_TESTBUS_275___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_275__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_275__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_276                (0x00AAA734)
#define   WMAC0_HWSCH_R0_TESTBUS_276___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_276__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_276__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_277                (0x00AAA738)
#define   WMAC0_HWSCH_R0_TESTBUS_277___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_277__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_277__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_278                (0x00AAA73C)
#define   WMAC0_HWSCH_R0_TESTBUS_278___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_278__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_278__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_279                (0x00AAA740)
#define   WMAC0_HWSCH_R0_TESTBUS_279___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_279__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_279__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_280                (0x00AAA744)
#define   WMAC0_HWSCH_R0_TESTBUS_280___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_280__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_280__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_281                (0x00AAA748)
#define   WMAC0_HWSCH_R0_TESTBUS_281___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_281__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_281__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_282                (0x00AAA74C)
#define   WMAC0_HWSCH_R0_TESTBUS_282___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_282__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_282__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_283                (0x00AAA750)
#define   WMAC0_HWSCH_R0_TESTBUS_283___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_283__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_283__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_284                (0x00AAA754)
#define   WMAC0_HWSCH_R0_TESTBUS_284___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_284__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_284__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_285                (0x00AAA758)
#define   WMAC0_HWSCH_R0_TESTBUS_285___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_285__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_285__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_286                (0x00AAA75C)
#define   WMAC0_HWSCH_R0_TESTBUS_286___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_286__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_286__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_287                (0x00AAA760)
#define   WMAC0_HWSCH_R0_TESTBUS_287___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_287__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_287__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_288                (0x00AAA764)
#define   WMAC0_HWSCH_R0_TESTBUS_288___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_288__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_288__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_289                (0x00AAA768)
#define   WMAC0_HWSCH_R0_TESTBUS_289___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_289__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_289__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_290                (0x00AAA76C)
#define   WMAC0_HWSCH_R0_TESTBUS_290___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_290__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_290__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_291                (0x00AAA770)
#define   WMAC0_HWSCH_R0_TESTBUS_291___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_291__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_291__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_292                (0x00AAA774)
#define   WMAC0_HWSCH_R0_TESTBUS_292___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_292__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_292__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_293                (0x00AAA778)
#define   WMAC0_HWSCH_R0_TESTBUS_293___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_293__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_293__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_294                (0x00AAA77C)
#define   WMAC0_HWSCH_R0_TESTBUS_294___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_294__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_294__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_295                (0x00AAA780)
#define   WMAC0_HWSCH_R0_TESTBUS_295___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_295__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_295__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_296                (0x00AAA784)
#define   WMAC0_HWSCH_R0_TESTBUS_296___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_296__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_296__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_297                (0x00AAA788)
#define   WMAC0_HWSCH_R0_TESTBUS_297___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_297__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_297__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_298                (0x00AAA78C)
#define   WMAC0_HWSCH_R0_TESTBUS_298___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_298__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_298__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_299                (0x00AAA790)
#define   WMAC0_HWSCH_R0_TESTBUS_299___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_299__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_299__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_300                (0x00AAA794)
#define   WMAC0_HWSCH_R0_TESTBUS_300___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_300__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_300__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_301                (0x00AAA798)
#define   WMAC0_HWSCH_R0_TESTBUS_301___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_301__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_301__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_302                (0x00AAA79C)
#define   WMAC0_HWSCH_R0_TESTBUS_302___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_302__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_302__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_303                (0x00AAA7A0)
#define   WMAC0_HWSCH_R0_TESTBUS_303___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_303__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_303__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_304                (0x00AAA7A4)
#define   WMAC0_HWSCH_R0_TESTBUS_304___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_304__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_304__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_305                (0x00AAA7A8)
#define   WMAC0_HWSCH_R0_TESTBUS_305___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_305__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_305__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_306                (0x00AAA7AC)
#define   WMAC0_HWSCH_R0_TESTBUS_306___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_306__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_306__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_307                (0x00AAA7B0)
#define   WMAC0_HWSCH_R0_TESTBUS_307___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_307__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_307__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_308                (0x00AAA7B4)
#define   WMAC0_HWSCH_R0_TESTBUS_308___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_308__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_308__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_309                (0x00AAA7B8)
#define   WMAC0_HWSCH_R0_TESTBUS_309___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_309__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_309__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_310                (0x00AAA7BC)
#define   WMAC0_HWSCH_R0_TESTBUS_310___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_310__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_310__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_311                (0x00AAA7C0)
#define   WMAC0_HWSCH_R0_TESTBUS_311___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_311__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_311__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_312                (0x00AAA7C4)
#define   WMAC0_HWSCH_R0_TESTBUS_312___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_312__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_312__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_313                (0x00AAA7C8)
#define   WMAC0_HWSCH_R0_TESTBUS_313___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_313__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_313__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_314                (0x00AAA7CC)
#define   WMAC0_HWSCH_R0_TESTBUS_314___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_314__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_314__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_315                (0x00AAA7D0)
#define   WMAC0_HWSCH_R0_TESTBUS_315___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_315__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_315__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_316                (0x00AAA7D4)
#define   WMAC0_HWSCH_R0_TESTBUS_316___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_316__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_316__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_317                (0x00AAA7D8)
#define   WMAC0_HWSCH_R0_TESTBUS_317___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_317__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_317__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_318                (0x00AAA7DC)
#define   WMAC0_HWSCH_R0_TESTBUS_318___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_318__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_318__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_319                (0x00AAA7E0)
#define   WMAC0_HWSCH_R0_TESTBUS_319___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_319__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_319__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_320                (0x00AAA7E4)
#define   WMAC0_HWSCH_R0_TESTBUS_320___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_320__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_320__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_321                (0x00AAA7E8)
#define   WMAC0_HWSCH_R0_TESTBUS_321___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_321__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_321__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_322                (0x00AAA7EC)
#define   WMAC0_HWSCH_R0_TESTBUS_322___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_322__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_322__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_323                (0x00AAA7F0)
#define   WMAC0_HWSCH_R0_TESTBUS_323___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_323__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_323__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_324                (0x00AAA7F4)
#define   WMAC0_HWSCH_R0_TESTBUS_324___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_324__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_324__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_325                (0x00AAA7F8)
#define   WMAC0_HWSCH_R0_TESTBUS_325___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_325__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_325__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_326                (0x00AAA7FC)
#define   WMAC0_HWSCH_R0_TESTBUS_326___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_326__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_326__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_327                (0x00AAA800)
#define   WMAC0_HWSCH_R0_TESTBUS_327___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_327__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_327__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_328                (0x00AAA804)
#define   WMAC0_HWSCH_R0_TESTBUS_328___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_328__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_328__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_329                (0x00AAA808)
#define   WMAC0_HWSCH_R0_TESTBUS_329___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_329__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_329__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_330                (0x00AAA80C)
#define   WMAC0_HWSCH_R0_TESTBUS_330___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_330__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_330__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_331                (0x00AAA810)
#define   WMAC0_HWSCH_R0_TESTBUS_331___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_331__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_331__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_332                (0x00AAA814)
#define   WMAC0_HWSCH_R0_TESTBUS_332___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_332__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_332__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_333                (0x00AAA818)
#define   WMAC0_HWSCH_R0_TESTBUS_333___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_333__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_333__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_334                (0x00AAA81C)
#define   WMAC0_HWSCH_R0_TESTBUS_334___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_334__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_334__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_335                (0x00AAA820)
#define   WMAC0_HWSCH_R0_TESTBUS_335___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_335__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_335__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_336                (0x00AAA824)
#define   WMAC0_HWSCH_R0_TESTBUS_336___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_336__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_336__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_337                (0x00AAA828)
#define   WMAC0_HWSCH_R0_TESTBUS_337___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_337__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_337__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_338                (0x00AAA82C)
#define   WMAC0_HWSCH_R0_TESTBUS_338___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_338__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_338__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_339                (0x00AAA830)
#define   WMAC0_HWSCH_R0_TESTBUS_339___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_339__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_339__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_340                (0x00AAA834)
#define   WMAC0_HWSCH_R0_TESTBUS_340___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_340__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_340__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_341                (0x00AAA838)
#define   WMAC0_HWSCH_R0_TESTBUS_341___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_341__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_341__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_342                (0x00AAA83C)
#define   WMAC0_HWSCH_R0_TESTBUS_342___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_342__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_342__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_343                (0x00AAA840)
#define   WMAC0_HWSCH_R0_TESTBUS_343___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_343__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_343__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_344                (0x00AAA844)
#define   WMAC0_HWSCH_R0_TESTBUS_344___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_344__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_344__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_345                (0x00AAA848)
#define   WMAC0_HWSCH_R0_TESTBUS_345___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_345__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_345__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_346                (0x00AAA84C)
#define   WMAC0_HWSCH_R0_TESTBUS_346___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_346__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_346__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_347                (0x00AAA850)
#define   WMAC0_HWSCH_R0_TESTBUS_347___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_347__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_347__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_348                (0x00AAA854)
#define   WMAC0_HWSCH_R0_TESTBUS_348___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_348__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_348__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_349                (0x00AAA858)
#define   WMAC0_HWSCH_R0_TESTBUS_349___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_349__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_349__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_350                (0x00AAA85C)
#define   WMAC0_HWSCH_R0_TESTBUS_350___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_350__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_350__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_351                (0x00AAA860)
#define   WMAC0_HWSCH_R0_TESTBUS_351___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_351__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_351__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_352                (0x00AAA864)
#define   WMAC0_HWSCH_R0_TESTBUS_352___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_352__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_352__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_353                (0x00AAA868)
#define   WMAC0_HWSCH_R0_TESTBUS_353___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_353__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_353__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_354                (0x00AAA86C)
#define   WMAC0_HWSCH_R0_TESTBUS_354___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_354__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_354__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_355                (0x00AAA870)
#define   WMAC0_HWSCH_R0_TESTBUS_355___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_355__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_355__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_356                (0x00AAA874)
#define   WMAC0_HWSCH_R0_TESTBUS_356___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_356__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_356__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_357                (0x00AAA878)
#define   WMAC0_HWSCH_R0_TESTBUS_357___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_357__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_357__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_358                (0x00AAA87C)
#define   WMAC0_HWSCH_R0_TESTBUS_358___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_358__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_358__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_359                (0x00AAA880)
#define   WMAC0_HWSCH_R0_TESTBUS_359___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_359__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_359__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_360                (0x00AAA884)
#define   WMAC0_HWSCH_R0_TESTBUS_360___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_360__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_360__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_361                (0x00AAA888)
#define   WMAC0_HWSCH_R0_TESTBUS_361___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_361__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_361__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_362                (0x00AAA88C)
#define   WMAC0_HWSCH_R0_TESTBUS_362___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_362__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_362__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_363                (0x00AAA890)
#define   WMAC0_HWSCH_R0_TESTBUS_363___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_363__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_363__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_364                (0x00AAA894)
#define   WMAC0_HWSCH_R0_TESTBUS_364___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_364__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_364__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_365                (0x00AAA898)
#define   WMAC0_HWSCH_R0_TESTBUS_365___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_365__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_365__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_366                (0x00AAA89C)
#define   WMAC0_HWSCH_R0_TESTBUS_366___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_366__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_366__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_367                (0x00AAA8A0)
#define   WMAC0_HWSCH_R0_TESTBUS_367___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_367__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_367__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_368                (0x00AAA8A4)
#define   WMAC0_HWSCH_R0_TESTBUS_368___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_368__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_368__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_369                (0x00AAA8A8)
#define   WMAC0_HWSCH_R0_TESTBUS_369___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_369__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_369__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_370                (0x00AAA8AC)
#define   WMAC0_HWSCH_R0_TESTBUS_370___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_370__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_370__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_371                (0x00AAA8B0)
#define   WMAC0_HWSCH_R0_TESTBUS_371___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_371__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_371__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_372                (0x00AAA8B4)
#define   WMAC0_HWSCH_R0_TESTBUS_372___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_372__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_372__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_373                (0x00AAA8B8)
#define   WMAC0_HWSCH_R0_TESTBUS_373___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_373__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_373__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_374                (0x00AAA8BC)
#define   WMAC0_HWSCH_R0_TESTBUS_374___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_374__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_374__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_375                (0x00AAA8C0)
#define   WMAC0_HWSCH_R0_TESTBUS_375___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_375__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_375__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_376                (0x00AAA8C4)
#define   WMAC0_HWSCH_R0_TESTBUS_376___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_376__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_376__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_377                (0x00AAA8C8)
#define   WMAC0_HWSCH_R0_TESTBUS_377___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_377__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_377__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_378                (0x00AAA8CC)
#define   WMAC0_HWSCH_R0_TESTBUS_378___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_378__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_378__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_379                (0x00AAA8D0)
#define   WMAC0_HWSCH_R0_TESTBUS_379___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_379__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_379__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_380                (0x00AAA8D4)
#define   WMAC0_HWSCH_R0_TESTBUS_380___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_380__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_380__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_381                (0x00AAA8D8)
#define   WMAC0_HWSCH_R0_TESTBUS_381___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_381__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_381__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_382                (0x00AAA8DC)
#define   WMAC0_HWSCH_R0_TESTBUS_382___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_382__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_382__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_383                (0x00AAA8E0)
#define   WMAC0_HWSCH_R0_TESTBUS_383___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_383__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_383__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_384                (0x00AAA8E4)
#define   WMAC0_HWSCH_R0_TESTBUS_384___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_384__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_384__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_385                (0x00AAA8E8)
#define   WMAC0_HWSCH_R0_TESTBUS_385___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_385__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_385__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_386                (0x00AAA8EC)
#define   WMAC0_HWSCH_R0_TESTBUS_386___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_386__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_386__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_387                (0x00AAA8F0)
#define   WMAC0_HWSCH_R0_TESTBUS_387___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_387__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_387__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_388                (0x00AAA8F4)
#define   WMAC0_HWSCH_R0_TESTBUS_388___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_388__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_388__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_389                (0x00AAA8F8)
#define   WMAC0_HWSCH_R0_TESTBUS_389___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_389__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_389__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_390                (0x00AAA8FC)
#define   WMAC0_HWSCH_R0_TESTBUS_390___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_390__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_390__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_391                (0x00AAA900)
#define   WMAC0_HWSCH_R0_TESTBUS_391___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_391__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_391__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_392                (0x00AAA904)
#define   WMAC0_HWSCH_R0_TESTBUS_392___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_392__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_392__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_393                (0x00AAA908)
#define   WMAC0_HWSCH_R0_TESTBUS_393___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_393__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_393__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_394                (0x00AAA90C)
#define   WMAC0_HWSCH_R0_TESTBUS_394___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_394__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_394__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_395                (0x00AAA910)
#define   WMAC0_HWSCH_R0_TESTBUS_395___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_395__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_395__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_396                (0x00AAA914)
#define   WMAC0_HWSCH_R0_TESTBUS_396___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_396__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_396__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_397                (0x00AAA918)
#define   WMAC0_HWSCH_R0_TESTBUS_397___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_397__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_397__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_398                (0x00AAA91C)
#define   WMAC0_HWSCH_R0_TESTBUS_398___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_398__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_398__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_399                (0x00AAA920)
#define   WMAC0_HWSCH_R0_TESTBUS_399___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_399__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_399__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_400                (0x00AAA924)
#define   WMAC0_HWSCH_R0_TESTBUS_400___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_400__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_400__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_401                (0x00AAA928)
#define   WMAC0_HWSCH_R0_TESTBUS_401___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_401__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_401__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_402                (0x00AAA92C)
#define   WMAC0_HWSCH_R0_TESTBUS_402___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_402__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_402__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_403                (0x00AAA930)
#define   WMAC0_HWSCH_R0_TESTBUS_403___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_403__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_403__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_404                (0x00AAA934)
#define   WMAC0_HWSCH_R0_TESTBUS_404___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_404__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_404__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_405                (0x00AAA938)
#define   WMAC0_HWSCH_R0_TESTBUS_405___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_405__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_405__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_406                (0x00AAA93C)
#define   WMAC0_HWSCH_R0_TESTBUS_406___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_406__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_406__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_407                (0x00AAA940)
#define   WMAC0_HWSCH_R0_TESTBUS_407___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_407__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_407__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_408                (0x00AAA944)
#define   WMAC0_HWSCH_R0_TESTBUS_408___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_408__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_408__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_409                (0x00AAA948)
#define   WMAC0_HWSCH_R0_TESTBUS_409___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_409__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_409__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_410                (0x00AAA94C)
#define   WMAC0_HWSCH_R0_TESTBUS_410___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_410__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_410__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_411                (0x00AAA950)
#define   WMAC0_HWSCH_R0_TESTBUS_411___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_411__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_411__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_412                (0x00AAA954)
#define   WMAC0_HWSCH_R0_TESTBUS_412___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_412__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_412__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_413                (0x00AAA958)
#define   WMAC0_HWSCH_R0_TESTBUS_413___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_413__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_413__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_414                (0x00AAA95C)
#define   WMAC0_HWSCH_R0_TESTBUS_414___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_414__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_414__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_415                (0x00AAA960)
#define   WMAC0_HWSCH_R0_TESTBUS_415___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_415__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_415__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_416                (0x00AAA964)
#define   WMAC0_HWSCH_R0_TESTBUS_416___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_416__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_416__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_417                (0x00AAA968)
#define   WMAC0_HWSCH_R0_TESTBUS_417___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_417__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_417__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_418                (0x00AAA96C)
#define   WMAC0_HWSCH_R0_TESTBUS_418___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_418__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_418__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_419                (0x00AAA970)
#define   WMAC0_HWSCH_R0_TESTBUS_419___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_419__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_419__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_420                (0x00AAA974)
#define   WMAC0_HWSCH_R0_TESTBUS_420___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_420__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_420__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_421                (0x00AAA978)
#define   WMAC0_HWSCH_R0_TESTBUS_421___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_421__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_421__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_422                (0x00AAA97C)
#define   WMAC0_HWSCH_R0_TESTBUS_422___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_422__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_422__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_423                (0x00AAA980)
#define   WMAC0_HWSCH_R0_TESTBUS_423___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_423__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_423__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_424                (0x00AAA984)
#define   WMAC0_HWSCH_R0_TESTBUS_424___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_424__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_424__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_425                (0x00AAA988)
#define   WMAC0_HWSCH_R0_TESTBUS_425___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_425__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_425__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_426                (0x00AAA98C)
#define   WMAC0_HWSCH_R0_TESTBUS_426___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_426__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_426__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_427                (0x00AAA990)
#define   WMAC0_HWSCH_R0_TESTBUS_427___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_427__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_427__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_428                (0x00AAA994)
#define   WMAC0_HWSCH_R0_TESTBUS_428___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_428__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_428__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_429                (0x00AAA998)
#define   WMAC0_HWSCH_R0_TESTBUS_429___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_429__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_429__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_430                (0x00AAA99C)
#define   WMAC0_HWSCH_R0_TESTBUS_430___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_430__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_430__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_431                (0x00AAA9A0)
#define   WMAC0_HWSCH_R0_TESTBUS_431___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_431__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_431__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_432                (0x00AAA9A4)
#define   WMAC0_HWSCH_R0_TESTBUS_432___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_432__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_432__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_433                (0x00AAA9A8)
#define   WMAC0_HWSCH_R0_TESTBUS_433___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_433__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_433__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_434                (0x00AAA9AC)
#define   WMAC0_HWSCH_R0_TESTBUS_434___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_434__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_434__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_435                (0x00AAA9B0)
#define   WMAC0_HWSCH_R0_TESTBUS_435___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_435__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_435__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_436                (0x00AAA9B4)
#define   WMAC0_HWSCH_R0_TESTBUS_436___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_436__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_436__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_437                (0x00AAA9B8)
#define   WMAC0_HWSCH_R0_TESTBUS_437___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_437__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_437__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_438                (0x00AAA9BC)
#define   WMAC0_HWSCH_R0_TESTBUS_438___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_438__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_438__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_439                (0x00AAA9C0)
#define   WMAC0_HWSCH_R0_TESTBUS_439___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_439__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_439__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_440                (0x00AAA9C4)
#define   WMAC0_HWSCH_R0_TESTBUS_440___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_440__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_440__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_441                (0x00AAA9C8)
#define   WMAC0_HWSCH_R0_TESTBUS_441___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_441__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_441__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_442                (0x00AAA9CC)
#define   WMAC0_HWSCH_R0_TESTBUS_442___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_442__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_442__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_443                (0x00AAA9D0)
#define   WMAC0_HWSCH_R0_TESTBUS_443___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_443__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_443__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_444                (0x00AAA9D4)
#define   WMAC0_HWSCH_R0_TESTBUS_444___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_444__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_444__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_445                (0x00AAA9D8)
#define   WMAC0_HWSCH_R0_TESTBUS_445___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_445__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_445__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_446                (0x00AAA9DC)
#define   WMAC0_HWSCH_R0_TESTBUS_446___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_446__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_446__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_447                (0x00AAA9E0)
#define   WMAC0_HWSCH_R0_TESTBUS_447___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_447__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_447__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_448                (0x00AAA9E4)
#define   WMAC0_HWSCH_R0_TESTBUS_448___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_448__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_448__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_449                (0x00AAA9E8)
#define   WMAC0_HWSCH_R0_TESTBUS_449___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_449__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_449__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_450                (0x00AAA9EC)
#define   WMAC0_HWSCH_R0_TESTBUS_450___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_450__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_450__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_451                (0x00AAA9F0)
#define   WMAC0_HWSCH_R0_TESTBUS_451___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_451__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_451__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_452                (0x00AAA9F4)
#define   WMAC0_HWSCH_R0_TESTBUS_452___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_452__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_452__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_453                (0x00AAA9F8)
#define   WMAC0_HWSCH_R0_TESTBUS_453___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_453__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_453__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_454                (0x00AAA9FC)
#define   WMAC0_HWSCH_R0_TESTBUS_454___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_454__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_454__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_455                (0x00AAAA00)
#define   WMAC0_HWSCH_R0_TESTBUS_455___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_455__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_455__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_456                (0x00AAAA04)
#define   WMAC0_HWSCH_R0_TESTBUS_456___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_456__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_456__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_457                (0x00AAAA08)
#define   WMAC0_HWSCH_R0_TESTBUS_457___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_457__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_457__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_458                (0x00AAAA0C)
#define   WMAC0_HWSCH_R0_TESTBUS_458___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_458__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_458__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_459                (0x00AAAA10)
#define   WMAC0_HWSCH_R0_TESTBUS_459___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_459__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_459__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_460                (0x00AAAA14)
#define   WMAC0_HWSCH_R0_TESTBUS_460___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_460__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_460__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_461                (0x00AAAA18)
#define   WMAC0_HWSCH_R0_TESTBUS_461___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_461__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_461__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_462                (0x00AAAA1C)
#define   WMAC0_HWSCH_R0_TESTBUS_462___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_462__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_462__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_463                (0x00AAAA20)
#define   WMAC0_HWSCH_R0_TESTBUS_463___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_463__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_463__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_464                (0x00AAAA24)
#define   WMAC0_HWSCH_R0_TESTBUS_464___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_464__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_464__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_465                (0x00AAAA28)
#define   WMAC0_HWSCH_R0_TESTBUS_465___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_465__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_465__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_466                (0x00AAAA2C)
#define   WMAC0_HWSCH_R0_TESTBUS_466___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_466__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_466__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_467                (0x00AAAA30)
#define   WMAC0_HWSCH_R0_TESTBUS_467___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_467__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_467__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_468                (0x00AAAA34)
#define   WMAC0_HWSCH_R0_TESTBUS_468___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_468__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_468__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_469                (0x00AAAA38)
#define   WMAC0_HWSCH_R0_TESTBUS_469___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_469__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_469__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_470                (0x00AAAA3C)
#define   WMAC0_HWSCH_R0_TESTBUS_470___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_470__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_470__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_471                (0x00AAAA40)
#define   WMAC0_HWSCH_R0_TESTBUS_471___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_471__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_471__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_472                (0x00AAAA44)
#define   WMAC0_HWSCH_R0_TESTBUS_472___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_472__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_472__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_473                (0x00AAAA48)
#define   WMAC0_HWSCH_R0_TESTBUS_473___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_473__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_473__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_474                (0x00AAAA4C)
#define   WMAC0_HWSCH_R0_TESTBUS_474___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_474__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_474__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_475                (0x00AAAA50)
#define   WMAC0_HWSCH_R0_TESTBUS_475___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_475__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_475__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_476                (0x00AAAA54)
#define   WMAC0_HWSCH_R0_TESTBUS_476___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_476__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_476__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_477                (0x00AAAA58)
#define   WMAC0_HWSCH_R0_TESTBUS_477___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_477__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_477__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_478                (0x00AAAA5C)
#define   WMAC0_HWSCH_R0_TESTBUS_478___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_478__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_478__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_479                (0x00AAAA60)
#define   WMAC0_HWSCH_R0_TESTBUS_479___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_479__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_479__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_480                (0x00AAAA64)
#define   WMAC0_HWSCH_R0_TESTBUS_480___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_480__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_480__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_481                (0x00AAAA68)
#define   WMAC0_HWSCH_R0_TESTBUS_481___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_481__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_481__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_482                (0x00AAAA6C)
#define   WMAC0_HWSCH_R0_TESTBUS_482___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_482__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_482__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_483                (0x00AAAA70)
#define   WMAC0_HWSCH_R0_TESTBUS_483___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_483__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_483__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_484                (0x00AAAA74)
#define   WMAC0_HWSCH_R0_TESTBUS_484___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_484__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_484__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_485                (0x00AAAA78)
#define   WMAC0_HWSCH_R0_TESTBUS_485___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_485__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_485__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_486                (0x00AAAA7C)
#define   WMAC0_HWSCH_R0_TESTBUS_486___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_486__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_486__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_487                (0x00AAAA80)
#define   WMAC0_HWSCH_R0_TESTBUS_487___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_487__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_487__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_488                (0x00AAAA84)
#define   WMAC0_HWSCH_R0_TESTBUS_488___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_488__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_488__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_489                (0x00AAAA88)
#define   WMAC0_HWSCH_R0_TESTBUS_489___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_489__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_489__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_490                (0x00AAAA8C)
#define   WMAC0_HWSCH_R0_TESTBUS_490___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_490__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_490__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_491                (0x00AAAA90)
#define   WMAC0_HWSCH_R0_TESTBUS_491___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_491__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_491__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_492                (0x00AAAA94)
#define   WMAC0_HWSCH_R0_TESTBUS_492___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_492__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_492__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_493                (0x00AAAA98)
#define   WMAC0_HWSCH_R0_TESTBUS_493___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_493__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_493__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_494                (0x00AAAA9C)
#define   WMAC0_HWSCH_R0_TESTBUS_494___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_494__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_494__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_495                (0x00AAAAA0)
#define   WMAC0_HWSCH_R0_TESTBUS_495___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_495__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_495__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_496                (0x00AAAAA4)
#define   WMAC0_HWSCH_R0_TESTBUS_496___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_496__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_496__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_497                (0x00AAAAA8)
#define   WMAC0_HWSCH_R0_TESTBUS_497___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_497__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_497__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_498                (0x00AAAAAC)
#define   WMAC0_HWSCH_R0_TESTBUS_498___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_498__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_498__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_499                (0x00AAAAB0)
#define   WMAC0_HWSCH_R0_TESTBUS_499___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_499__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_499__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_500                (0x00AAAAB4)
#define   WMAC0_HWSCH_R0_TESTBUS_500___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_500__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_500__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_501                (0x00AAAAB8)
#define   WMAC0_HWSCH_R0_TESTBUS_501___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_501__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_501__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_502                (0x00AAAABC)
#define   WMAC0_HWSCH_R0_TESTBUS_502___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_502__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_502__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_503                (0x00AAAAC0)
#define   WMAC0_HWSCH_R0_TESTBUS_503___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_503__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_503__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_504                (0x00AAAAC4)
#define   WMAC0_HWSCH_R0_TESTBUS_504___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_504__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_504__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_505                (0x00AAAAC8)
#define   WMAC0_HWSCH_R0_TESTBUS_505___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_505__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_505__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_506                (0x00AAAACC)
#define   WMAC0_HWSCH_R0_TESTBUS_506___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_506__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_506__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_507                (0x00AAAAD0)
#define   WMAC0_HWSCH_R0_TESTBUS_507___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_507__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_507__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_508                (0x00AAAAD4)
#define   WMAC0_HWSCH_R0_TESTBUS_508___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_508__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_508__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_509                (0x00AAAAD8)
#define   WMAC0_HWSCH_R0_TESTBUS_509___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_509__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_509__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_510                (0x00AAAADC)
#define   WMAC0_HWSCH_R0_TESTBUS_510___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_510__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_510__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_511                (0x00AAAAE0)
#define   WMAC0_HWSCH_R0_TESTBUS_511___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_511__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_511__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_512                (0x00AAAAE4)
#define   WMAC0_HWSCH_R0_TESTBUS_512___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_512__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_512__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_513                (0x00AAAAE8)
#define   WMAC0_HWSCH_R0_TESTBUS_513___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_513__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_513__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_514                (0x00AAAAEC)
#define   WMAC0_HWSCH_R0_TESTBUS_514___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_514__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_514__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_515                (0x00AAAAF0)
#define   WMAC0_HWSCH_R0_TESTBUS_515___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_515__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_515__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_516                (0x00AAAAF4)
#define   WMAC0_HWSCH_R0_TESTBUS_516___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_516__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_516__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_517                (0x00AAAAF8)
#define   WMAC0_HWSCH_R0_TESTBUS_517___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_517__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_517__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_518                (0x00AAAAFC)
#define   WMAC0_HWSCH_R0_TESTBUS_518___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_518__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_518__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_519                (0x00AAAB00)
#define   WMAC0_HWSCH_R0_TESTBUS_519___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_519__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_519__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_520                (0x00AAAB04)
#define   WMAC0_HWSCH_R0_TESTBUS_520___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_520__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_520__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_521                (0x00AAAB08)
#define   WMAC0_HWSCH_R0_TESTBUS_521___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_521__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_521__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_522                (0x00AAAB0C)
#define   WMAC0_HWSCH_R0_TESTBUS_522___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_522__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_522__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_523                (0x00AAAB10)
#define   WMAC0_HWSCH_R0_TESTBUS_523___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_523__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_523__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_524                (0x00AAAB14)
#define   WMAC0_HWSCH_R0_TESTBUS_524___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_524__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_524__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_525                (0x00AAAB18)
#define   WMAC0_HWSCH_R0_TESTBUS_525___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_525__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_525__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_526                (0x00AAAB1C)
#define   WMAC0_HWSCH_R0_TESTBUS_526___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_526__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_526__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_527                (0x00AAAB20)
#define   WMAC0_HWSCH_R0_TESTBUS_527___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_527__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_527__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_528                (0x00AAAB24)
#define   WMAC0_HWSCH_R0_TESTBUS_528___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_528__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_528__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_529                (0x00AAAB28)
#define   WMAC0_HWSCH_R0_TESTBUS_529___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_529__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_529__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_530                (0x00AAAB2C)
#define   WMAC0_HWSCH_R0_TESTBUS_530___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_530__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_530__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_531                (0x00AAAB30)
#define   WMAC0_HWSCH_R0_TESTBUS_531___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_531__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_531__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_532                (0x00AAAB34)
#define   WMAC0_HWSCH_R0_TESTBUS_532___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_532__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_532__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_533                (0x00AAAB38)
#define   WMAC0_HWSCH_R0_TESTBUS_533___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_533__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_533__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_534                (0x00AAAB3C)
#define   WMAC0_HWSCH_R0_TESTBUS_534___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_534__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_534__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_535                (0x00AAAB40)
#define   WMAC0_HWSCH_R0_TESTBUS_535___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_535__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_535__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_536                (0x00AAAB44)
#define   WMAC0_HWSCH_R0_TESTBUS_536___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_536__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_536__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_537                (0x00AAAB48)
#define   WMAC0_HWSCH_R0_TESTBUS_537___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_537__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_537__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_538                (0x00AAAB4C)
#define   WMAC0_HWSCH_R0_TESTBUS_538___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_538__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_538__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_539                (0x00AAAB50)
#define   WMAC0_HWSCH_R0_TESTBUS_539___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_539__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_539__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_540                (0x00AAAB54)
#define   WMAC0_HWSCH_R0_TESTBUS_540___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_540__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_540__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_541                (0x00AAAB58)
#define   WMAC0_HWSCH_R0_TESTBUS_541___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_541__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_541__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_542                (0x00AAAB5C)
#define   WMAC0_HWSCH_R0_TESTBUS_542___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_542__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_542__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_543                (0x00AAAB60)
#define   WMAC0_HWSCH_R0_TESTBUS_543___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_543__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_543__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_544                (0x00AAAB64)
#define   WMAC0_HWSCH_R0_TESTBUS_544___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_544__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_544__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_545                (0x00AAAB68)
#define   WMAC0_HWSCH_R0_TESTBUS_545___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_545__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_545__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_546                (0x00AAAB6C)
#define   WMAC0_HWSCH_R0_TESTBUS_546___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_546__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_546__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_547                (0x00AAAB70)
#define   WMAC0_HWSCH_R0_TESTBUS_547___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_547__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_547__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_548                (0x00AAAB74)
#define   WMAC0_HWSCH_R0_TESTBUS_548___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_548__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_548__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_549                (0x00AAAB78)
#define   WMAC0_HWSCH_R0_TESTBUS_549___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_549__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_549__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_550                (0x00AAAB7C)
#define   WMAC0_HWSCH_R0_TESTBUS_550___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_550__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_550__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_551                (0x00AAAB80)
#define   WMAC0_HWSCH_R0_TESTBUS_551___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_551__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_551__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_552                (0x00AAAB84)
#define   WMAC0_HWSCH_R0_TESTBUS_552___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_552__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_552__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_553                (0x00AAAB88)
#define   WMAC0_HWSCH_R0_TESTBUS_553___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_553__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_553__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_554                (0x00AAAB8C)
#define   WMAC0_HWSCH_R0_TESTBUS_554___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_554__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_554__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_555                (0x00AAAB90)
#define   WMAC0_HWSCH_R0_TESTBUS_555___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_555__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_555__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_556                (0x00AAAB94)
#define   WMAC0_HWSCH_R0_TESTBUS_556___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_556__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_556__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_557                (0x00AAAB98)
#define   WMAC0_HWSCH_R0_TESTBUS_557___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_557__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_557__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_558                (0x00AAAB9C)
#define   WMAC0_HWSCH_R0_TESTBUS_558___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_558__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_558__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_559                (0x00AAABA0)
#define   WMAC0_HWSCH_R0_TESTBUS_559___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_559__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_559__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_560                (0x00AAABA4)
#define   WMAC0_HWSCH_R0_TESTBUS_560___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_560__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_560__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_561                (0x00AAABA8)
#define   WMAC0_HWSCH_R0_TESTBUS_561___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_561__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_561__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_562                (0x00AAABAC)
#define   WMAC0_HWSCH_R0_TESTBUS_562___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_562__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_562__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_563                (0x00AAABB0)
#define   WMAC0_HWSCH_R0_TESTBUS_563___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_563__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_563__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_564                (0x00AAABB4)
#define   WMAC0_HWSCH_R0_TESTBUS_564___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_564__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_564__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_565                (0x00AAABB8)
#define   WMAC0_HWSCH_R0_TESTBUS_565___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_565__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_565__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_566                (0x00AAABBC)
#define   WMAC0_HWSCH_R0_TESTBUS_566___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_566__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_566__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_567                (0x00AAABC0)
#define   WMAC0_HWSCH_R0_TESTBUS_567___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_567__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_567__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_568                (0x00AAABC4)
#define   WMAC0_HWSCH_R0_TESTBUS_568___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_568__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_568__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_569                (0x00AAABC8)
#define   WMAC0_HWSCH_R0_TESTBUS_569___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_569__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_569__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_570                (0x00AAABCC)
#define   WMAC0_HWSCH_R0_TESTBUS_570___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_570__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_570__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_571                (0x00AAABD0)
#define   WMAC0_HWSCH_R0_TESTBUS_571___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_571__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_571__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_572                (0x00AAABD4)
#define   WMAC0_HWSCH_R0_TESTBUS_572___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_572__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_572__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_573                (0x00AAABD8)
#define   WMAC0_HWSCH_R0_TESTBUS_573___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_573__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_573__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_574                (0x00AAABDC)
#define   WMAC0_HWSCH_R0_TESTBUS_574___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_574__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_574__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_575                (0x00AAABE0)
#define   WMAC0_HWSCH_R0_TESTBUS_575___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_575__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_575__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_576                (0x00AAABE4)
#define   WMAC0_HWSCH_R0_TESTBUS_576___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_576__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_576__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_577                (0x00AAABE8)
#define   WMAC0_HWSCH_R0_TESTBUS_577___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_577__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_577__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_578                (0x00AAABEC)
#define   WMAC0_HWSCH_R0_TESTBUS_578___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_578__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_578__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_579                (0x00AAABF0)
#define   WMAC0_HWSCH_R0_TESTBUS_579___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_579__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_579__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_580                (0x00AAABF4)
#define   WMAC0_HWSCH_R0_TESTBUS_580___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_580__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_580__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_581                (0x00AAABF8)
#define   WMAC0_HWSCH_R0_TESTBUS_581___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_581__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_581__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_582                (0x00AAABFC)
#define   WMAC0_HWSCH_R0_TESTBUS_582___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_582__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_582__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_583                (0x00AAAC00)
#define   WMAC0_HWSCH_R0_TESTBUS_583___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_583__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_583__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_584                (0x00AAAC04)
#define   WMAC0_HWSCH_R0_TESTBUS_584___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_584__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_584__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_585                (0x00AAAC08)
#define   WMAC0_HWSCH_R0_TESTBUS_585___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_585__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_585__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_586                (0x00AAAC0C)
#define   WMAC0_HWSCH_R0_TESTBUS_586___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_586__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_586__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_587                (0x00AAAC10)
#define   WMAC0_HWSCH_R0_TESTBUS_587___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_587__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_587__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_588                (0x00AAAC14)
#define   WMAC0_HWSCH_R0_TESTBUS_588___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_588__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_588__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_589                (0x00AAAC18)
#define   WMAC0_HWSCH_R0_TESTBUS_589___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_589__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_589__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_590                (0x00AAAC1C)
#define   WMAC0_HWSCH_R0_TESTBUS_590___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_590__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_590__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_591                (0x00AAAC20)
#define   WMAC0_HWSCH_R0_TESTBUS_591___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_591__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_591__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_592                (0x00AAAC24)
#define   WMAC0_HWSCH_R0_TESTBUS_592___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_592__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_592__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_593                (0x00AAAC28)
#define   WMAC0_HWSCH_R0_TESTBUS_593___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_593__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_593__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_594                (0x00AAAC2C)
#define   WMAC0_HWSCH_R0_TESTBUS_594___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_594__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_594__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_595                (0x00AAAC30)
#define   WMAC0_HWSCH_R0_TESTBUS_595___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_595__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_595__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_596                (0x00AAAC34)
#define   WMAC0_HWSCH_R0_TESTBUS_596___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_596__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_596__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_597                (0x00AAAC38)
#define   WMAC0_HWSCH_R0_TESTBUS_597___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_597__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_597__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_598                (0x00AAAC3C)
#define   WMAC0_HWSCH_R0_TESTBUS_598___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_598__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_598__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_599                (0x00AAAC40)
#define   WMAC0_HWSCH_R0_TESTBUS_599___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_599__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_599__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_600                (0x00AAAC44)
#define   WMAC0_HWSCH_R0_TESTBUS_600___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_600__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_600__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_601                (0x00AAAC48)
#define   WMAC0_HWSCH_R0_TESTBUS_601___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_601__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_601__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_602                (0x00AAAC4C)
#define   WMAC0_HWSCH_R0_TESTBUS_602___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_602__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_602__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_603                (0x00AAAC50)
#define   WMAC0_HWSCH_R0_TESTBUS_603___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_603__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_603__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_604                (0x00AAAC54)
#define   WMAC0_HWSCH_R0_TESTBUS_604___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_604__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_604__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_605                (0x00AAAC58)
#define   WMAC0_HWSCH_R0_TESTBUS_605___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_605__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_605__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_606                (0x00AAAC5C)
#define   WMAC0_HWSCH_R0_TESTBUS_606___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_606__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_606__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_607                (0x00AAAC60)
#define   WMAC0_HWSCH_R0_TESTBUS_607___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_607__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_607__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_608                (0x00AAAC64)
#define   WMAC0_HWSCH_R0_TESTBUS_608___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_608__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_608__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_609                (0x00AAAC68)
#define   WMAC0_HWSCH_R0_TESTBUS_609___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_609__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_609__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_610                (0x00AAAC6C)
#define   WMAC0_HWSCH_R0_TESTBUS_610___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_610__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_610__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_611                (0x00AAAC70)
#define   WMAC0_HWSCH_R0_TESTBUS_611___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_611__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_611__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_612                (0x00AAAC74)
#define   WMAC0_HWSCH_R0_TESTBUS_612___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_612__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_612__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_613                (0x00AAAC78)
#define   WMAC0_HWSCH_R0_TESTBUS_613___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_613__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_613__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_614                (0x00AAAC7C)
#define   WMAC0_HWSCH_R0_TESTBUS_614___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_614__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_614__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_615                (0x00AAAC80)
#define   WMAC0_HWSCH_R0_TESTBUS_615___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_615__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_615__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_616                (0x00AAAC84)
#define   WMAC0_HWSCH_R0_TESTBUS_616___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_616__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_616__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_617                (0x00AAAC88)
#define   WMAC0_HWSCH_R0_TESTBUS_617___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_617__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_617__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_618                (0x00AAAC8C)
#define   WMAC0_HWSCH_R0_TESTBUS_618___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_618__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_618__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_619                (0x00AAAC90)
#define   WMAC0_HWSCH_R0_TESTBUS_619___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_619__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_619__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_620                (0x00AAAC94)
#define   WMAC0_HWSCH_R0_TESTBUS_620___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_620__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_620__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_621                (0x00AAAC98)
#define   WMAC0_HWSCH_R0_TESTBUS_621___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_621__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_621__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_622                (0x00AAAC9C)
#define   WMAC0_HWSCH_R0_TESTBUS_622___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_622__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_622__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_623                (0x00AAACA0)
#define   WMAC0_HWSCH_R0_TESTBUS_623___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_623__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_623__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_624                (0x00AAACA4)
#define   WMAC0_HWSCH_R0_TESTBUS_624___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_624__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_624__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_625                (0x00AAACA8)
#define   WMAC0_HWSCH_R0_TESTBUS_625___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_625__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_625__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_626                (0x00AAACAC)
#define   WMAC0_HWSCH_R0_TESTBUS_626___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_626__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_626__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_627                (0x00AAACB0)
#define   WMAC0_HWSCH_R0_TESTBUS_627___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_627__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_627__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_628                (0x00AAACB4)
#define   WMAC0_HWSCH_R0_TESTBUS_628___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_628__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_628__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_629                (0x00AAACB8)
#define   WMAC0_HWSCH_R0_TESTBUS_629___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_629__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_629__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_630                (0x00AAACBC)
#define   WMAC0_HWSCH_R0_TESTBUS_630___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_630__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_630__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_631                (0x00AAACC0)
#define   WMAC0_HWSCH_R0_TESTBUS_631___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_631__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_631__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_632                (0x00AAACC4)
#define   WMAC0_HWSCH_R0_TESTBUS_632___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_632__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_632__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_633                (0x00AAACC8)
#define   WMAC0_HWSCH_R0_TESTBUS_633___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_633__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_633__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_634                (0x00AAACCC)
#define   WMAC0_HWSCH_R0_TESTBUS_634___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_634__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_634__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_635                (0x00AAACD0)
#define   WMAC0_HWSCH_R0_TESTBUS_635___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_635__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_635__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_636                (0x00AAACD4)
#define   WMAC0_HWSCH_R0_TESTBUS_636___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_636__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_636__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_637                (0x00AAACD8)
#define   WMAC0_HWSCH_R0_TESTBUS_637___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_637__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_637__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_638                (0x00AAACDC)
#define   WMAC0_HWSCH_R0_TESTBUS_638___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_638__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_638__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_639                (0x00AAACE0)
#define   WMAC0_HWSCH_R0_TESTBUS_639___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_639__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_639__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_640                (0x00AAACE4)
#define   WMAC0_HWSCH_R0_TESTBUS_640___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_640__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_640__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_641                (0x00AAACE8)
#define   WMAC0_HWSCH_R0_TESTBUS_641___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_641__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_641__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_642                (0x00AAACEC)
#define   WMAC0_HWSCH_R0_TESTBUS_642___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_642__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_642__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_643                (0x00AAACF0)
#define   WMAC0_HWSCH_R0_TESTBUS_643___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_643__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_643__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_644                (0x00AAACF4)
#define   WMAC0_HWSCH_R0_TESTBUS_644___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_644__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_644__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_645                (0x00AAACF8)
#define   WMAC0_HWSCH_R0_TESTBUS_645___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_645__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_645__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_646                (0x00AAACFC)
#define   WMAC0_HWSCH_R0_TESTBUS_646___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_646__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_646__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_647                (0x00AAAD00)
#define   WMAC0_HWSCH_R0_TESTBUS_647___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_647__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_647__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_648                (0x00AAAD04)
#define   WMAC0_HWSCH_R0_TESTBUS_648___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_648__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_648__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_649                (0x00AAAD08)
#define   WMAC0_HWSCH_R0_TESTBUS_649___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_649__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_649__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_650                (0x00AAAD0C)
#define   WMAC0_HWSCH_R0_TESTBUS_650___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_650__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_650__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_651                (0x00AAAD10)
#define   WMAC0_HWSCH_R0_TESTBUS_651___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_651__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_651__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_652                (0x00AAAD14)
#define   WMAC0_HWSCH_R0_TESTBUS_652___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_652__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_652__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_653                (0x00AAAD18)
#define   WMAC0_HWSCH_R0_TESTBUS_653___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_653__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_653__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_654                (0x00AAAD1C)
#define   WMAC0_HWSCH_R0_TESTBUS_654___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_654__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_654__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_655                (0x00AAAD20)
#define   WMAC0_HWSCH_R0_TESTBUS_655___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_655__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_655__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_656                (0x00AAAD24)
#define   WMAC0_HWSCH_R0_TESTBUS_656___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_656__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_656__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_657                (0x00AAAD28)
#define   WMAC0_HWSCH_R0_TESTBUS_657___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_657__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_657__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_658                (0x00AAAD2C)
#define   WMAC0_HWSCH_R0_TESTBUS_658___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_658__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_658__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_659                (0x00AAAD30)
#define   WMAC0_HWSCH_R0_TESTBUS_659___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_659__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_659__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_660                (0x00AAAD34)
#define   WMAC0_HWSCH_R0_TESTBUS_660___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_660__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_660__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_661                (0x00AAAD38)
#define   WMAC0_HWSCH_R0_TESTBUS_661___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_661__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_661__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_662                (0x00AAAD3C)
#define   WMAC0_HWSCH_R0_TESTBUS_662___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_662__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_662__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_663                (0x00AAAD40)
#define   WMAC0_HWSCH_R0_TESTBUS_663___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_663__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_663__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_664                (0x00AAAD44)
#define   WMAC0_HWSCH_R0_TESTBUS_664___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_664__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_664__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_665                (0x00AAAD48)
#define   WMAC0_HWSCH_R0_TESTBUS_665___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_665__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_665__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_666                (0x00AAAD4C)
#define   WMAC0_HWSCH_R0_TESTBUS_666___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_666__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_666__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_667                (0x00AAAD50)
#define   WMAC0_HWSCH_R0_TESTBUS_667___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_667__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_667__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_668                (0x00AAAD54)
#define   WMAC0_HWSCH_R0_TESTBUS_668___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_668__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_668__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_669                (0x00AAAD58)
#define   WMAC0_HWSCH_R0_TESTBUS_669___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_669__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_669__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_670                (0x00AAAD5C)
#define   WMAC0_HWSCH_R0_TESTBUS_670___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_670__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_670__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_671                (0x00AAAD60)
#define   WMAC0_HWSCH_R0_TESTBUS_671___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_671__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_671__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_672                (0x00AAAD64)
#define   WMAC0_HWSCH_R0_TESTBUS_672___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_672__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_672__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_673                (0x00AAAD68)
#define   WMAC0_HWSCH_R0_TESTBUS_673___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_673__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_673__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_674                (0x00AAAD6C)
#define   WMAC0_HWSCH_R0_TESTBUS_674___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_674__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_674__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_675                (0x00AAAD70)
#define   WMAC0_HWSCH_R0_TESTBUS_675___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_675__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_675__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_676                (0x00AAAD74)
#define   WMAC0_HWSCH_R0_TESTBUS_676___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_676__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_676__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_677                (0x00AAAD78)
#define   WMAC0_HWSCH_R0_TESTBUS_677___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_677__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_677__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_678                (0x00AAAD7C)
#define   WMAC0_HWSCH_R0_TESTBUS_678___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_678__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_678__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_679                (0x00AAAD80)
#define   WMAC0_HWSCH_R0_TESTBUS_679___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_679__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_679__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_680                (0x00AAAD84)
#define   WMAC0_HWSCH_R0_TESTBUS_680___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_680__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_680__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_681                (0x00AAAD88)
#define   WMAC0_HWSCH_R0_TESTBUS_681___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_681__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_681__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_682                (0x00AAAD8C)
#define   WMAC0_HWSCH_R0_TESTBUS_682___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_682__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_682__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_683                (0x00AAAD90)
#define   WMAC0_HWSCH_R0_TESTBUS_683___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_683__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_683__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_684                (0x00AAAD94)
#define   WMAC0_HWSCH_R0_TESTBUS_684___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_684__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_684__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_685                (0x00AAAD98)
#define   WMAC0_HWSCH_R0_TESTBUS_685___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_685__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_685__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_686                (0x00AAAD9C)
#define   WMAC0_HWSCH_R0_TESTBUS_686___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_686__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_686__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_687                (0x00AAADA0)
#define   WMAC0_HWSCH_R0_TESTBUS_687___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_687__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_687__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_688                (0x00AAADA4)
#define   WMAC0_HWSCH_R0_TESTBUS_688___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_688__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_688__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_689                (0x00AAADA8)
#define   WMAC0_HWSCH_R0_TESTBUS_689___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_689__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_689__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_690                (0x00AAADAC)
#define   WMAC0_HWSCH_R0_TESTBUS_690___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_690__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_690__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_691                (0x00AAADB0)
#define   WMAC0_HWSCH_R0_TESTBUS_691___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_691__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_691__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_692                (0x00AAADB4)
#define   WMAC0_HWSCH_R0_TESTBUS_692___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_692__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_692__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_693                (0x00AAADB8)
#define   WMAC0_HWSCH_R0_TESTBUS_693___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_693__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_693__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_694                (0x00AAADBC)
#define   WMAC0_HWSCH_R0_TESTBUS_694___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_694__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_694__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_695                (0x00AAADC0)
#define   WMAC0_HWSCH_R0_TESTBUS_695___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_695__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_695__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_696                (0x00AAADC4)
#define   WMAC0_HWSCH_R0_TESTBUS_696___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_696__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_696__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_697                (0x00AAADC8)
#define   WMAC0_HWSCH_R0_TESTBUS_697___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_697__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_697__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_698                (0x00AAADCC)
#define   WMAC0_HWSCH_R0_TESTBUS_698___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_698__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_698__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_699                (0x00AAADD0)
#define   WMAC0_HWSCH_R0_TESTBUS_699___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_699__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_699__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_700                (0x00AAADD4)
#define   WMAC0_HWSCH_R0_TESTBUS_700___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_700__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_700__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_701                (0x00AAADD8)
#define   WMAC0_HWSCH_R0_TESTBUS_701___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_701__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_701__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_702                (0x00AAADDC)
#define   WMAC0_HWSCH_R0_TESTBUS_702___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_702__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_702__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_703                (0x00AAADE0)
#define   WMAC0_HWSCH_R0_TESTBUS_703___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_703__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_703__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_704                (0x00AAADE4)
#define   WMAC0_HWSCH_R0_TESTBUS_704___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_704__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_704__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_705                (0x00AAADE8)
#define   WMAC0_HWSCH_R0_TESTBUS_705___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_705__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_705__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_706                (0x00AAADEC)
#define   WMAC0_HWSCH_R0_TESTBUS_706___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_706__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_706__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_707                (0x00AAADF0)
#define   WMAC0_HWSCH_R0_TESTBUS_707___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_707__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_707__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_708                (0x00AAADF4)
#define   WMAC0_HWSCH_R0_TESTBUS_708___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_708__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_708__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_709                (0x00AAADF8)
#define   WMAC0_HWSCH_R0_TESTBUS_709___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_709__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_709__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_710                (0x00AAADFC)
#define   WMAC0_HWSCH_R0_TESTBUS_710___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_710__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_710__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_711                (0x00AAAE00)
#define   WMAC0_HWSCH_R0_TESTBUS_711___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_711__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_711__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_712                (0x00AAAE04)
#define   WMAC0_HWSCH_R0_TESTBUS_712___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_712__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_712__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_713                (0x00AAAE08)
#define   WMAC0_HWSCH_R0_TESTBUS_713___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_713__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_713__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_714                (0x00AAAE0C)
#define   WMAC0_HWSCH_R0_TESTBUS_714___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_714__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_714__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_715                (0x00AAAE10)
#define   WMAC0_HWSCH_R0_TESTBUS_715___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_715__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_715__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_716                (0x00AAAE14)
#define   WMAC0_HWSCH_R0_TESTBUS_716___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_716__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_716__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_717                (0x00AAAE18)
#define   WMAC0_HWSCH_R0_TESTBUS_717___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_717__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_717__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_718                (0x00AAAE1C)
#define   WMAC0_HWSCH_R0_TESTBUS_718___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_718__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_718__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_719                (0x00AAAE20)
#define   WMAC0_HWSCH_R0_TESTBUS_719___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_719__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_719__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_720                (0x00AAAE24)
#define   WMAC0_HWSCH_R0_TESTBUS_720___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_720__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_720__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_721                (0x00AAAE28)
#define   WMAC0_HWSCH_R0_TESTBUS_721___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_721__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_721__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_722                (0x00AAAE2C)
#define   WMAC0_HWSCH_R0_TESTBUS_722___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_722__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_722__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_723                (0x00AAAE30)
#define   WMAC0_HWSCH_R0_TESTBUS_723___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_723__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_723__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_724                (0x00AAAE34)
#define   WMAC0_HWSCH_R0_TESTBUS_724___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_724__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_724__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_725                (0x00AAAE38)
#define   WMAC0_HWSCH_R0_TESTBUS_725___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_725__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_725__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_726                (0x00AAAE3C)
#define   WMAC0_HWSCH_R0_TESTBUS_726___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_726__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_726__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_727                (0x00AAAE40)
#define   WMAC0_HWSCH_R0_TESTBUS_727___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_727__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_727__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_728                (0x00AAAE44)
#define   WMAC0_HWSCH_R0_TESTBUS_728___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_728__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_728__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_729                (0x00AAAE48)
#define   WMAC0_HWSCH_R0_TESTBUS_729___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_729__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_729__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_730                (0x00AAAE4C)
#define   WMAC0_HWSCH_R0_TESTBUS_730___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_730__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_730__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_731                (0x00AAAE50)
#define   WMAC0_HWSCH_R0_TESTBUS_731___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_731__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_731__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_732                (0x00AAAE54)
#define   WMAC0_HWSCH_R0_TESTBUS_732___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_732__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_732__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_733                (0x00AAAE58)
#define   WMAC0_HWSCH_R0_TESTBUS_733___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_733__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_733__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_734                (0x00AAAE5C)
#define   WMAC0_HWSCH_R0_TESTBUS_734___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_734__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_734__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_735                (0x00AAAE60)
#define   WMAC0_HWSCH_R0_TESTBUS_735___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_735__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_735__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_736                (0x00AAAE64)
#define   WMAC0_HWSCH_R0_TESTBUS_736___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_736__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_736__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_737                (0x00AAAE68)
#define   WMAC0_HWSCH_R0_TESTBUS_737___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_737__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_737__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_738                (0x00AAAE6C)
#define   WMAC0_HWSCH_R0_TESTBUS_738___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_738__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_738__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_739                (0x00AAAE70)
#define   WMAC0_HWSCH_R0_TESTBUS_739___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_739__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_739__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_740                (0x00AAAE74)
#define   WMAC0_HWSCH_R0_TESTBUS_740___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_740__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_740__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_741                (0x00AAAE78)
#define   WMAC0_HWSCH_R0_TESTBUS_741___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_741__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_741__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_742                (0x00AAAE7C)
#define   WMAC0_HWSCH_R0_TESTBUS_742___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_742__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_742__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_743                (0x00AAAE80)
#define   WMAC0_HWSCH_R0_TESTBUS_743___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_743__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_743__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_744                (0x00AAAE84)
#define   WMAC0_HWSCH_R0_TESTBUS_744___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_744__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_744__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_745                (0x00AAAE88)
#define   WMAC0_HWSCH_R0_TESTBUS_745___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_745__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_745__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_746                (0x00AAAE8C)
#define   WMAC0_HWSCH_R0_TESTBUS_746___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_746__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_746__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_747                (0x00AAAE90)
#define   WMAC0_HWSCH_R0_TESTBUS_747___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_747__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_747__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_748                (0x00AAAE94)
#define   WMAC0_HWSCH_R0_TESTBUS_748___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_748__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_748__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_749                (0x00AAAE98)
#define   WMAC0_HWSCH_R0_TESTBUS_749___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_749__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_749__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_750                (0x00AAAE9C)
#define   WMAC0_HWSCH_R0_TESTBUS_750___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_750__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_750__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_751                (0x00AAAEA0)
#define   WMAC0_HWSCH_R0_TESTBUS_751___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_751__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_751__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_752                (0x00AAAEA4)
#define   WMAC0_HWSCH_R0_TESTBUS_752___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_752__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_752__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_753                (0x00AAAEA8)
#define   WMAC0_HWSCH_R0_TESTBUS_753___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_753__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_753__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_754                (0x00AAAEAC)
#define   WMAC0_HWSCH_R0_TESTBUS_754___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_754__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_754__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_755                (0x00AAAEB0)
#define   WMAC0_HWSCH_R0_TESTBUS_755___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_755__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_755__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_756                (0x00AAAEB4)
#define   WMAC0_HWSCH_R0_TESTBUS_756___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_756__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_756__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_757                (0x00AAAEB8)
#define   WMAC0_HWSCH_R0_TESTBUS_757___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_757__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_757__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_758                (0x00AAAEBC)
#define   WMAC0_HWSCH_R0_TESTBUS_758___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_758__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_758__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_759                (0x00AAAEC0)
#define   WMAC0_HWSCH_R0_TESTBUS_759___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_759__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_759__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_760                (0x00AAAEC4)
#define   WMAC0_HWSCH_R0_TESTBUS_760___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_760__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_760__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_761                (0x00AAAEC8)
#define   WMAC0_HWSCH_R0_TESTBUS_761___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_761__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_761__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_762                (0x00AAAECC)
#define   WMAC0_HWSCH_R0_TESTBUS_762___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_762__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_762__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_763                (0x00AAAED0)
#define   WMAC0_HWSCH_R0_TESTBUS_763___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_763__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_763__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_764                (0x00AAAED4)
#define   WMAC0_HWSCH_R0_TESTBUS_764___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_764__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_764__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_765                (0x00AAAED8)
#define   WMAC0_HWSCH_R0_TESTBUS_765___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_765__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_765__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_766                (0x00AAAEDC)
#define   WMAC0_HWSCH_R0_TESTBUS_766___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_766__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_766__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_767                (0x00AAAEE0)
#define   WMAC0_HWSCH_R0_TESTBUS_767___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_767__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_767__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_768                (0x00AAAEE4)
#define   WMAC0_HWSCH_R0_TESTBUS_768___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_768__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_768__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_769                (0x00AAAEE8)
#define   WMAC0_HWSCH_R0_TESTBUS_769___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_769__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_769__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_770                (0x00AAAEEC)
#define   WMAC0_HWSCH_R0_TESTBUS_770___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_770__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_770__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_771                (0x00AAAEF0)
#define   WMAC0_HWSCH_R0_TESTBUS_771___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_771__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_771__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_772                (0x00AAAEF4)
#define   WMAC0_HWSCH_R0_TESTBUS_772___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_772__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_772__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_773                (0x00AAAEF8)
#define   WMAC0_HWSCH_R0_TESTBUS_773___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_773__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_773__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_774                (0x00AAAEFC)
#define   WMAC0_HWSCH_R0_TESTBUS_774___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_774__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_774__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_775                (0x00AAAF00)
#define   WMAC0_HWSCH_R0_TESTBUS_775___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_775__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_775__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_776                (0x00AAAF04)
#define   WMAC0_HWSCH_R0_TESTBUS_776___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_776__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_776__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_777                (0x00AAAF08)
#define   WMAC0_HWSCH_R0_TESTBUS_777___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_777__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_777__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_778                (0x00AAAF0C)
#define   WMAC0_HWSCH_R0_TESTBUS_778___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_778__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_778__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_779                (0x00AAAF10)
#define   WMAC0_HWSCH_R0_TESTBUS_779___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_779__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_779__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_780                (0x00AAAF14)
#define   WMAC0_HWSCH_R0_TESTBUS_780___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_780__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_780__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_781                (0x00AAAF18)
#define   WMAC0_HWSCH_R0_TESTBUS_781___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_781__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_781__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_782                (0x00AAAF1C)
#define   WMAC0_HWSCH_R0_TESTBUS_782___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_782__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_782__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_783                (0x00AAAF20)
#define   WMAC0_HWSCH_R0_TESTBUS_783___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_783__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_783__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_784                (0x00AAAF24)
#define   WMAC0_HWSCH_R0_TESTBUS_784___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_784__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_784__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_785                (0x00AAAF28)
#define   WMAC0_HWSCH_R0_TESTBUS_785___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_785__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_785__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_786                (0x00AAAF2C)
#define   WMAC0_HWSCH_R0_TESTBUS_786___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_786__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_786__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_787                (0x00AAAF30)
#define   WMAC0_HWSCH_R0_TESTBUS_787___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_787__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_787__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_788                (0x00AAAF34)
#define   WMAC0_HWSCH_R0_TESTBUS_788___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_788__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_788__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_789                (0x00AAAF38)
#define   WMAC0_HWSCH_R0_TESTBUS_789___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_789__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_789__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_790                (0x00AAAF3C)
#define   WMAC0_HWSCH_R0_TESTBUS_790___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_790__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_790__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_791                (0x00AAAF40)
#define   WMAC0_HWSCH_R0_TESTBUS_791___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_791__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_791__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_792                (0x00AAAF44)
#define   WMAC0_HWSCH_R0_TESTBUS_792___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_792__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_792__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_793                (0x00AAAF48)
#define   WMAC0_HWSCH_R0_TESTBUS_793___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_793__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_793__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_794                (0x00AAAF4C)
#define   WMAC0_HWSCH_R0_TESTBUS_794___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_794__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_794__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_795                (0x00AAAF50)
#define   WMAC0_HWSCH_R0_TESTBUS_795___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_795__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_795__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_796                (0x00AAAF54)
#define   WMAC0_HWSCH_R0_TESTBUS_796___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_796__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_796__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_797                (0x00AAAF58)
#define   WMAC0_HWSCH_R0_TESTBUS_797___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_797__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_797__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_798                (0x00AAAF5C)
#define   WMAC0_HWSCH_R0_TESTBUS_798___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_798__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_798__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_799                (0x00AAAF60)
#define   WMAC0_HWSCH_R0_TESTBUS_799___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_799__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_799__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_800                (0x00AAAF64)
#define   WMAC0_HWSCH_R0_TESTBUS_800___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_800__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_800__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_801                (0x00AAAF68)
#define   WMAC0_HWSCH_R0_TESTBUS_801___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_801__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_801__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_802                (0x00AAAF6C)
#define   WMAC0_HWSCH_R0_TESTBUS_802___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_802__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_802__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_803                (0x00AAAF70)
#define   WMAC0_HWSCH_R0_TESTBUS_803___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_803__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_803__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_804                (0x00AAAF74)
#define   WMAC0_HWSCH_R0_TESTBUS_804___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_804__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_804__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_805                (0x00AAAF78)
#define   WMAC0_HWSCH_R0_TESTBUS_805___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_805__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_805__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_806                (0x00AAAF7C)
#define   WMAC0_HWSCH_R0_TESTBUS_806___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_806__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_806__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_807                (0x00AAAF80)
#define   WMAC0_HWSCH_R0_TESTBUS_807___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_807__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_807__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_808                (0x00AAAF84)
#define   WMAC0_HWSCH_R0_TESTBUS_808___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_808__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_808__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_809                (0x00AAAF88)
#define   WMAC0_HWSCH_R0_TESTBUS_809___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_809__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_809__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_810                (0x00AAAF8C)
#define   WMAC0_HWSCH_R0_TESTBUS_810___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_810__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_810__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_811                (0x00AAAF90)
#define   WMAC0_HWSCH_R0_TESTBUS_811___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_811__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_811__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_812                (0x00AAAF94)
#define   WMAC0_HWSCH_R0_TESTBUS_812___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_812__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_812__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_813                (0x00AAAF98)
#define   WMAC0_HWSCH_R0_TESTBUS_813___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_813__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_813__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_814                (0x00AAAF9C)
#define   WMAC0_HWSCH_R0_TESTBUS_814___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_814__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_814__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_815                (0x00AAAFA0)
#define   WMAC0_HWSCH_R0_TESTBUS_815___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_815__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_815__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_816                (0x00AAAFA4)
#define   WMAC0_HWSCH_R0_TESTBUS_816___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_816__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_816__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_817                (0x00AAAFA8)
#define   WMAC0_HWSCH_R0_TESTBUS_817___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_817__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_817__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_818                (0x00AAAFAC)
#define   WMAC0_HWSCH_R0_TESTBUS_818___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_818__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_818__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_819                (0x00AAAFB0)
#define   WMAC0_HWSCH_R0_TESTBUS_819___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_819__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_819__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_820                (0x00AAAFB4)
#define   WMAC0_HWSCH_R0_TESTBUS_820___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_820__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_820__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_821                (0x00AAAFB8)
#define   WMAC0_HWSCH_R0_TESTBUS_821___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_821__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_821__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_822                (0x00AAAFBC)
#define   WMAC0_HWSCH_R0_TESTBUS_822___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_822__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_822__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_823                (0x00AAAFC0)
#define   WMAC0_HWSCH_R0_TESTBUS_823___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_823__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_823__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_824                (0x00AAAFC4)
#define   WMAC0_HWSCH_R0_TESTBUS_824___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_824__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_824__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_825                (0x00AAAFC8)
#define   WMAC0_HWSCH_R0_TESTBUS_825___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_825__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_825__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_826                (0x00AAAFCC)
#define   WMAC0_HWSCH_R0_TESTBUS_826___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_826__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_826__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_827                (0x00AAAFD0)
#define   WMAC0_HWSCH_R0_TESTBUS_827___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_827__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_827__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_828                (0x00AAAFD4)
#define   WMAC0_HWSCH_R0_TESTBUS_828___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_828__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_828__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_829                (0x00AAAFD8)
#define   WMAC0_HWSCH_R0_TESTBUS_829___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_829__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_829__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_830                (0x00AAAFDC)
#define   WMAC0_HWSCH_R0_TESTBUS_830___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_830__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_830__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_831                (0x00AAAFE0)
#define   WMAC0_HWSCH_R0_TESTBUS_831___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_831__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_831__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_832                (0x00AAAFE4)
#define   WMAC0_HWSCH_R0_TESTBUS_832___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_832__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_832__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_833                (0x00AAAFE8)
#define   WMAC0_HWSCH_R0_TESTBUS_833___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_833__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_833__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_834                (0x00AAAFEC)
#define   WMAC0_HWSCH_R0_TESTBUS_834___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_834__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_834__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_835                (0x00AAAFF0)
#define   WMAC0_HWSCH_R0_TESTBUS_835___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_835__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_835__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_836                (0x00AAAFF4)
#define   WMAC0_HWSCH_R0_TESTBUS_836___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_836__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_836__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_837                (0x00AAAFF8)
#define   WMAC0_HWSCH_R0_TESTBUS_837___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_837__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_837__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_838                (0x00AAAFFC)
#define   WMAC0_HWSCH_R0_TESTBUS_838___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_838__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_838__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_839                (0x00AAB000)
#define   WMAC0_HWSCH_R0_TESTBUS_839___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_839__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_839__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_840                (0x00AAB004)
#define   WMAC0_HWSCH_R0_TESTBUS_840___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_840__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_840__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_841                (0x00AAB008)
#define   WMAC0_HWSCH_R0_TESTBUS_841___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_841__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_841__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_842                (0x00AAB00C)
#define   WMAC0_HWSCH_R0_TESTBUS_842___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_842__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_842__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_843                (0x00AAB010)
#define   WMAC0_HWSCH_R0_TESTBUS_843___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_843__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_843__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_844                (0x00AAB014)
#define   WMAC0_HWSCH_R0_TESTBUS_844___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_844__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_844__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_845                (0x00AAB018)
#define   WMAC0_HWSCH_R0_TESTBUS_845___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_845__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_845__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_846                (0x00AAB01C)
#define   WMAC0_HWSCH_R0_TESTBUS_846___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_846__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_846__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_847                (0x00AAB020)
#define   WMAC0_HWSCH_R0_TESTBUS_847___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_847__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_847__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_848                (0x00AAB024)
#define   WMAC0_HWSCH_R0_TESTBUS_848___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_848__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_848__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_849                (0x00AAB028)
#define   WMAC0_HWSCH_R0_TESTBUS_849___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_849__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_849__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_850                (0x00AAB02C)
#define   WMAC0_HWSCH_R0_TESTBUS_850___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_850__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_850__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_851                (0x00AAB030)
#define   WMAC0_HWSCH_R0_TESTBUS_851___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_851__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_851__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_852                (0x00AAB034)
#define   WMAC0_HWSCH_R0_TESTBUS_852___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_852__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_852__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_853                (0x00AAB038)
#define   WMAC0_HWSCH_R0_TESTBUS_853___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_853__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_853__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_854                (0x00AAB03C)
#define   WMAC0_HWSCH_R0_TESTBUS_854___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_854__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_854__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_855                (0x00AAB040)
#define   WMAC0_HWSCH_R0_TESTBUS_855___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_855__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_855__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_856                (0x00AAB044)
#define   WMAC0_HWSCH_R0_TESTBUS_856___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_856__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_856__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_857                (0x00AAB048)
#define   WMAC0_HWSCH_R0_TESTBUS_857___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_857__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_857__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_858                (0x00AAB04C)
#define   WMAC0_HWSCH_R0_TESTBUS_858___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_858__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_858__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_859                (0x00AAB050)
#define   WMAC0_HWSCH_R0_TESTBUS_859___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_859__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_859__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_860                (0x00AAB054)
#define   WMAC0_HWSCH_R0_TESTBUS_860___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_860__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_860__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_861                (0x00AAB058)
#define   WMAC0_HWSCH_R0_TESTBUS_861___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_861__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_861__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_862                (0x00AAB05C)
#define   WMAC0_HWSCH_R0_TESTBUS_862___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_862__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_862__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_863                (0x00AAB060)
#define   WMAC0_HWSCH_R0_TESTBUS_863___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_863__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_863__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_864                (0x00AAB064)
#define   WMAC0_HWSCH_R0_TESTBUS_864___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_864__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_864__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_865                (0x00AAB068)
#define   WMAC0_HWSCH_R0_TESTBUS_865___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_865__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_865__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_866                (0x00AAB06C)
#define   WMAC0_HWSCH_R0_TESTBUS_866___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_866__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_866__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_867                (0x00AAB070)
#define   WMAC0_HWSCH_R0_TESTBUS_867___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_867__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_867__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_868                (0x00AAB074)
#define   WMAC0_HWSCH_R0_TESTBUS_868___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_868__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_868__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_869                (0x00AAB078)
#define   WMAC0_HWSCH_R0_TESTBUS_869___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_869__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_869__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_870                (0x00AAB07C)
#define   WMAC0_HWSCH_R0_TESTBUS_870___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_870__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_870__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_871                (0x00AAB080)
#define   WMAC0_HWSCH_R0_TESTBUS_871___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_871__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_871__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_872                (0x00AAB084)
#define   WMAC0_HWSCH_R0_TESTBUS_872___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_872__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_872__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_873                (0x00AAB088)
#define   WMAC0_HWSCH_R0_TESTBUS_873___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_873__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_873__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_874                (0x00AAB08C)
#define   WMAC0_HWSCH_R0_TESTBUS_874___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_874__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_874__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_875                (0x00AAB090)
#define   WMAC0_HWSCH_R0_TESTBUS_875___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_875__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_875__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_876                (0x00AAB094)
#define   WMAC0_HWSCH_R0_TESTBUS_876___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_876__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_876__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_877                (0x00AAB098)
#define   WMAC0_HWSCH_R0_TESTBUS_877___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_877__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_877__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_878                (0x00AAB09C)
#define   WMAC0_HWSCH_R0_TESTBUS_878___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_878__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_878__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_879                (0x00AAB0A0)
#define   WMAC0_HWSCH_R0_TESTBUS_879___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_879__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_879__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_880                (0x00AAB0A4)
#define   WMAC0_HWSCH_R0_TESTBUS_880___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_880__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_880__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_881                (0x00AAB0A8)
#define   WMAC0_HWSCH_R0_TESTBUS_881___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_881__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_881__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_882                (0x00AAB0AC)
#define   WMAC0_HWSCH_R0_TESTBUS_882___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_882__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_882__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_883                (0x00AAB0B0)
#define   WMAC0_HWSCH_R0_TESTBUS_883___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_883__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_883__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_884                (0x00AAB0B4)
#define   WMAC0_HWSCH_R0_TESTBUS_884___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_884__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_884__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_885                (0x00AAB0B8)
#define   WMAC0_HWSCH_R0_TESTBUS_885___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_885__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_885__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_886                (0x00AAB0BC)
#define   WMAC0_HWSCH_R0_TESTBUS_886___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_886__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_886__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_887                (0x00AAB0C0)
#define   WMAC0_HWSCH_R0_TESTBUS_887___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_887__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_887__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_888                (0x00AAB0C4)
#define   WMAC0_HWSCH_R0_TESTBUS_888___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_888__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_888__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_889                (0x00AAB0C8)
#define   WMAC0_HWSCH_R0_TESTBUS_889___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_889__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_889__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_890                (0x00AAB0CC)
#define   WMAC0_HWSCH_R0_TESTBUS_890___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_890__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_890__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_891                (0x00AAB0D0)
#define   WMAC0_HWSCH_R0_TESTBUS_891___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_891__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_891__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_892                (0x00AAB0D4)
#define   WMAC0_HWSCH_R0_TESTBUS_892___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_892__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_892__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_893                (0x00AAB0D8)
#define   WMAC0_HWSCH_R0_TESTBUS_893___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_893__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_893__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_894                (0x00AAB0DC)
#define   WMAC0_HWSCH_R0_TESTBUS_894___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_894__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_894__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_895                (0x00AAB0E0)
#define   WMAC0_HWSCH_R0_TESTBUS_895___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_895__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_895__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_896                (0x00AAB0E4)
#define   WMAC0_HWSCH_R0_TESTBUS_896___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_896__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_896__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_897                (0x00AAB0E8)
#define   WMAC0_HWSCH_R0_TESTBUS_897___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_897__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_897__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_898                (0x00AAB0EC)
#define   WMAC0_HWSCH_R0_TESTBUS_898___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_898__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_898__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_899                (0x00AAB0F0)
#define   WMAC0_HWSCH_R0_TESTBUS_899___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_899__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_899__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_900                (0x00AAB0F4)
#define   WMAC0_HWSCH_R0_TESTBUS_900___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_900__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_900__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_901                (0x00AAB0F8)
#define   WMAC0_HWSCH_R0_TESTBUS_901___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_901__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_901__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_902                (0x00AAB0FC)
#define   WMAC0_HWSCH_R0_TESTBUS_902___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_902__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_902__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_903                (0x00AAB100)
#define   WMAC0_HWSCH_R0_TESTBUS_903___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_903__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_903__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_904                (0x00AAB104)
#define   WMAC0_HWSCH_R0_TESTBUS_904___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_904__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_904__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_905                (0x00AAB108)
#define   WMAC0_HWSCH_R0_TESTBUS_905___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_905__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_905__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_906                (0x00AAB10C)
#define   WMAC0_HWSCH_R0_TESTBUS_906___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_906__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_906__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_907                (0x00AAB110)
#define   WMAC0_HWSCH_R0_TESTBUS_907___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_907__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_907__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_908                (0x00AAB114)
#define   WMAC0_HWSCH_R0_TESTBUS_908___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_908__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_908__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_909                (0x00AAB118)
#define   WMAC0_HWSCH_R0_TESTBUS_909___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_909__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_909__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_910                (0x00AAB11C)
#define   WMAC0_HWSCH_R0_TESTBUS_910___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_910__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_910__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_911                (0x00AAB120)
#define   WMAC0_HWSCH_R0_TESTBUS_911___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_911__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_911__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_912                (0x00AAB124)
#define   WMAC0_HWSCH_R0_TESTBUS_912___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_912__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_912__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_913                (0x00AAB128)
#define   WMAC0_HWSCH_R0_TESTBUS_913___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_913__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_913__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_914                (0x00AAB12C)
#define   WMAC0_HWSCH_R0_TESTBUS_914___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_914__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_914__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_915                (0x00AAB130)
#define   WMAC0_HWSCH_R0_TESTBUS_915___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_915__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_915__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_916                (0x00AAB134)
#define   WMAC0_HWSCH_R0_TESTBUS_916___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_916__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_916__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_917                (0x00AAB138)
#define   WMAC0_HWSCH_R0_TESTBUS_917___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_917__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_917__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_918                (0x00AAB13C)
#define   WMAC0_HWSCH_R0_TESTBUS_918___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_918__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_918__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_919                (0x00AAB140)
#define   WMAC0_HWSCH_R0_TESTBUS_919___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_919__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_919__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_920                (0x00AAB144)
#define   WMAC0_HWSCH_R0_TESTBUS_920___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_920__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_920__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_921                (0x00AAB148)
#define   WMAC0_HWSCH_R0_TESTBUS_921___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_921__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_921__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_922                (0x00AAB14C)
#define   WMAC0_HWSCH_R0_TESTBUS_922___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_922__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_922__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_923                (0x00AAB150)
#define   WMAC0_HWSCH_R0_TESTBUS_923___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_923__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_923__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_924                (0x00AAB154)
#define   WMAC0_HWSCH_R0_TESTBUS_924___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_924__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_924__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_925                (0x00AAB158)
#define   WMAC0_HWSCH_R0_TESTBUS_925___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_925__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_925__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_926                (0x00AAB15C)
#define   WMAC0_HWSCH_R0_TESTBUS_926___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_926__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_926__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_927                (0x00AAB160)
#define   WMAC0_HWSCH_R0_TESTBUS_927___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_927__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_927__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_928                (0x00AAB164)
#define   WMAC0_HWSCH_R0_TESTBUS_928___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_928__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_928__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_929                (0x00AAB168)
#define   WMAC0_HWSCH_R0_TESTBUS_929___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_929__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_929__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_930                (0x00AAB16C)
#define   WMAC0_HWSCH_R0_TESTBUS_930___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_930__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_930__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_931                (0x00AAB170)
#define   WMAC0_HWSCH_R0_TESTBUS_931___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_931__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_931__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_932                (0x00AAB174)
#define   WMAC0_HWSCH_R0_TESTBUS_932___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_932__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_932__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_933                (0x00AAB178)
#define   WMAC0_HWSCH_R0_TESTBUS_933___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_933__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_933__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_934                (0x00AAB17C)
#define   WMAC0_HWSCH_R0_TESTBUS_934___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_934__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_934__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_935                (0x00AAB180)
#define   WMAC0_HWSCH_R0_TESTBUS_935___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_935__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_935__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_936                (0x00AAB184)
#define   WMAC0_HWSCH_R0_TESTBUS_936___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_936__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_936__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_937                (0x00AAB188)
#define   WMAC0_HWSCH_R0_TESTBUS_937___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_937__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_937__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_938                (0x00AAB18C)
#define   WMAC0_HWSCH_R0_TESTBUS_938___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_938__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_938__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_939                (0x00AAB190)
#define   WMAC0_HWSCH_R0_TESTBUS_939___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_939__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_939__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_940                (0x00AAB194)
#define   WMAC0_HWSCH_R0_TESTBUS_940___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_940__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_940__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_941                (0x00AAB198)
#define   WMAC0_HWSCH_R0_TESTBUS_941___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_941__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_941__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_942                (0x00AAB19C)
#define   WMAC0_HWSCH_R0_TESTBUS_942___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_942__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_942__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_943                (0x00AAB1A0)
#define   WMAC0_HWSCH_R0_TESTBUS_943___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_943__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_943__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_944                (0x00AAB1A4)
#define   WMAC0_HWSCH_R0_TESTBUS_944___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_944__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_944__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_945                (0x00AAB1A8)
#define   WMAC0_HWSCH_R0_TESTBUS_945___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_945__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_945__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_946                (0x00AAB1AC)
#define   WMAC0_HWSCH_R0_TESTBUS_946___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_946__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_946__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_947                (0x00AAB1B0)
#define   WMAC0_HWSCH_R0_TESTBUS_947___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_947__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_947__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_948                (0x00AAB1B4)
#define   WMAC0_HWSCH_R0_TESTBUS_948___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_948__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_948__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_949                (0x00AAB1B8)
#define   WMAC0_HWSCH_R0_TESTBUS_949___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_949__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_949__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_950                (0x00AAB1BC)
#define   WMAC0_HWSCH_R0_TESTBUS_950___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_950__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_950__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_951                (0x00AAB1C0)
#define   WMAC0_HWSCH_R0_TESTBUS_951___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_951__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_951__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_952                (0x00AAB1C4)
#define   WMAC0_HWSCH_R0_TESTBUS_952___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_952__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_952__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_953                (0x00AAB1C8)
#define   WMAC0_HWSCH_R0_TESTBUS_953___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_953__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_953__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_954                (0x00AAB1CC)
#define   WMAC0_HWSCH_R0_TESTBUS_954___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_954__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_954__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_955                (0x00AAB1D0)
#define   WMAC0_HWSCH_R0_TESTBUS_955___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_955__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_955__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_956                (0x00AAB1D4)
#define   WMAC0_HWSCH_R0_TESTBUS_956___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_956__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_956__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_957                (0x00AAB1D8)
#define   WMAC0_HWSCH_R0_TESTBUS_957___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_957__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_957__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_958                (0x00AAB1DC)
#define   WMAC0_HWSCH_R0_TESTBUS_958___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_958__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_958__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_959                (0x00AAB1E0)
#define   WMAC0_HWSCH_R0_TESTBUS_959___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_959__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_959__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_960                (0x00AAB1E4)
#define   WMAC0_HWSCH_R0_TESTBUS_960___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_960__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_960__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_961                (0x00AAB1E8)
#define   WMAC0_HWSCH_R0_TESTBUS_961___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_961__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_961__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_962                (0x00AAB1EC)
#define   WMAC0_HWSCH_R0_TESTBUS_962___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_962__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_962__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_963                (0x00AAB1F0)
#define   WMAC0_HWSCH_R0_TESTBUS_963___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_963__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_963__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_964                (0x00AAB1F4)
#define   WMAC0_HWSCH_R0_TESTBUS_964___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_964__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_964__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_965                (0x00AAB1F8)
#define   WMAC0_HWSCH_R0_TESTBUS_965___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_965__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_965__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_966                (0x00AAB1FC)
#define   WMAC0_HWSCH_R0_TESTBUS_966___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_966__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_966__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_967                (0x00AAB200)
#define   WMAC0_HWSCH_R0_TESTBUS_967___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_967__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_967__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_968                (0x00AAB204)
#define   WMAC0_HWSCH_R0_TESTBUS_968___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_968__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_968__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_969                (0x00AAB208)
#define   WMAC0_HWSCH_R0_TESTBUS_969___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_969__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_969__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_970                (0x00AAB20C)
#define   WMAC0_HWSCH_R0_TESTBUS_970___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_970__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_970__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_971                (0x00AAB210)
#define   WMAC0_HWSCH_R0_TESTBUS_971___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_971__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_971__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_972                (0x00AAB214)
#define   WMAC0_HWSCH_R0_TESTBUS_972___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_972__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_972__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_973                (0x00AAB218)
#define   WMAC0_HWSCH_R0_TESTBUS_973___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_973__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_973__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_974                (0x00AAB21C)
#define   WMAC0_HWSCH_R0_TESTBUS_974___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_974__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_974__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_975                (0x00AAB220)
#define   WMAC0_HWSCH_R0_TESTBUS_975___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_975__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_975__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_976                (0x00AAB224)
#define   WMAC0_HWSCH_R0_TESTBUS_976___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_976__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_976__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_977                (0x00AAB228)
#define   WMAC0_HWSCH_R0_TESTBUS_977___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_977__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_977__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_978                (0x00AAB22C)
#define   WMAC0_HWSCH_R0_TESTBUS_978___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_978__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_978__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_979                (0x00AAB230)
#define   WMAC0_HWSCH_R0_TESTBUS_979___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_979__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_979__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_980                (0x00AAB234)
#define   WMAC0_HWSCH_R0_TESTBUS_980___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_980__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_980__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_981                (0x00AAB238)
#define   WMAC0_HWSCH_R0_TESTBUS_981___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_981__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_981__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_982                (0x00AAB23C)
#define   WMAC0_HWSCH_R0_TESTBUS_982___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_982__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_982__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_983                (0x00AAB240)
#define   WMAC0_HWSCH_R0_TESTBUS_983___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_983__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_983__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_984                (0x00AAB244)
#define   WMAC0_HWSCH_R0_TESTBUS_984___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_984__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_984__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_985                (0x00AAB248)
#define   WMAC0_HWSCH_R0_TESTBUS_985___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_985__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_985__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_986                (0x00AAB24C)
#define   WMAC0_HWSCH_R0_TESTBUS_986___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_986__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_986__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_987                (0x00AAB250)
#define   WMAC0_HWSCH_R0_TESTBUS_987___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_987__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_987__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_988                (0x00AAB254)
#define   WMAC0_HWSCH_R0_TESTBUS_988___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_988__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_988__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_989                (0x00AAB258)
#define   WMAC0_HWSCH_R0_TESTBUS_989___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_989__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_989__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_990                (0x00AAB25C)
#define   WMAC0_HWSCH_R0_TESTBUS_990___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_990__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_990__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_991                (0x00AAB260)
#define   WMAC0_HWSCH_R0_TESTBUS_991___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_991__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_991__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_992                (0x00AAB264)
#define   WMAC0_HWSCH_R0_TESTBUS_992___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_992__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_992__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_993                (0x00AAB268)
#define   WMAC0_HWSCH_R0_TESTBUS_993___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_993__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_993__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_994                (0x00AAB26C)
#define   WMAC0_HWSCH_R0_TESTBUS_994___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_994__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_994__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_995                (0x00AAB270)
#define   WMAC0_HWSCH_R0_TESTBUS_995___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_995__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_995__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_996                (0x00AAB274)
#define   WMAC0_HWSCH_R0_TESTBUS_996___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_996__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_996__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_997                (0x00AAB278)
#define   WMAC0_HWSCH_R0_TESTBUS_997___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_997__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_997__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_998                (0x00AAB27C)
#define   WMAC0_HWSCH_R0_TESTBUS_998___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_998__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_998__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_999                (0x00AAB280)
#define   WMAC0_HWSCH_R0_TESTBUS_999___RWC          QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_999__DATA___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_999__DATA___S                 0
#define WMAC0_HWSCH_R0_TESTBUS_1000               (0x00AAB284)
#define   WMAC0_HWSCH_R0_TESTBUS_1000___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1000__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1000__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1001               (0x00AAB288)
#define   WMAC0_HWSCH_R0_TESTBUS_1001___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1001__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1001__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1002               (0x00AAB28C)
#define   WMAC0_HWSCH_R0_TESTBUS_1002___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1002__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1002__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1003               (0x00AAB290)
#define   WMAC0_HWSCH_R0_TESTBUS_1003___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1003__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1003__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1004               (0x00AAB294)
#define   WMAC0_HWSCH_R0_TESTBUS_1004___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1004__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1004__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1005               (0x00AAB298)
#define   WMAC0_HWSCH_R0_TESTBUS_1005___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1005__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1005__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1006               (0x00AAB29C)
#define   WMAC0_HWSCH_R0_TESTBUS_1006___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1006__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1006__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1007               (0x00AAB2A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1007___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1007__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1007__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1008               (0x00AAB2A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1008___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1008__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1008__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1009               (0x00AAB2A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1009___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1009__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1009__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1010               (0x00AAB2AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1010___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1010__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1010__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1011               (0x00AAB2B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1011___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1011__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1011__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1012               (0x00AAB2B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1012___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1012__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1012__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1013               (0x00AAB2B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1013___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1013__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1013__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1014               (0x00AAB2BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1014___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1014__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1014__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1015               (0x00AAB2C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1015___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1015__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1015__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1016               (0x00AAB2C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1016___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1016__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1016__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1017               (0x00AAB2C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1017___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1017__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1017__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1018               (0x00AAB2CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1018___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1018__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1018__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1019               (0x00AAB2D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1019___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1019__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1019__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1020               (0x00AAB2D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1020___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1020__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1020__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1021               (0x00AAB2D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1021___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1021__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1021__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1022               (0x00AAB2DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1022___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1022__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1022__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1023               (0x00AAB2E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1023___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1023__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1023__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1024               (0x00AAB2E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1024___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1024__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1024__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1025               (0x00AAB2E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1025___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1025__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1025__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1026               (0x00AAB2EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1026___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1026__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1026__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1027               (0x00AAB2F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1027___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1027__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1027__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1028               (0x00AAB2F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1028___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1028__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1028__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1029               (0x00AAB2F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1029___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1029__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1029__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1030               (0x00AAB2FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1030___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1030__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1030__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1031               (0x00AAB300)
#define   WMAC0_HWSCH_R0_TESTBUS_1031___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1031__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1031__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1032               (0x00AAB304)
#define   WMAC0_HWSCH_R0_TESTBUS_1032___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1032__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1032__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1033               (0x00AAB308)
#define   WMAC0_HWSCH_R0_TESTBUS_1033___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1033__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1033__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1034               (0x00AAB30C)
#define   WMAC0_HWSCH_R0_TESTBUS_1034___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1034__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1034__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1035               (0x00AAB310)
#define   WMAC0_HWSCH_R0_TESTBUS_1035___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1035__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1035__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1036               (0x00AAB314)
#define   WMAC0_HWSCH_R0_TESTBUS_1036___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1036__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1036__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1037               (0x00AAB318)
#define   WMAC0_HWSCH_R0_TESTBUS_1037___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1037__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1037__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1038               (0x00AAB31C)
#define   WMAC0_HWSCH_R0_TESTBUS_1038___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1038__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1038__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1039               (0x00AAB320)
#define   WMAC0_HWSCH_R0_TESTBUS_1039___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1039__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1039__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1040               (0x00AAB324)
#define   WMAC0_HWSCH_R0_TESTBUS_1040___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1040__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1040__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1041               (0x00AAB328)
#define   WMAC0_HWSCH_R0_TESTBUS_1041___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1041__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1041__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1042               (0x00AAB32C)
#define   WMAC0_HWSCH_R0_TESTBUS_1042___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1042__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1042__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1043               (0x00AAB330)
#define   WMAC0_HWSCH_R0_TESTBUS_1043___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1043__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1043__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1044               (0x00AAB334)
#define   WMAC0_HWSCH_R0_TESTBUS_1044___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1044__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1044__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1045               (0x00AAB338)
#define   WMAC0_HWSCH_R0_TESTBUS_1045___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1045__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1045__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1046               (0x00AAB33C)
#define   WMAC0_HWSCH_R0_TESTBUS_1046___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1046__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1046__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1047               (0x00AAB340)
#define   WMAC0_HWSCH_R0_TESTBUS_1047___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1047__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1047__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1048               (0x00AAB344)
#define   WMAC0_HWSCH_R0_TESTBUS_1048___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1048__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1048__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1049               (0x00AAB348)
#define   WMAC0_HWSCH_R0_TESTBUS_1049___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1049__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1049__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1050               (0x00AAB34C)
#define   WMAC0_HWSCH_R0_TESTBUS_1050___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1050__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1050__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1051               (0x00AAB350)
#define   WMAC0_HWSCH_R0_TESTBUS_1051___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1051__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1051__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1052               (0x00AAB354)
#define   WMAC0_HWSCH_R0_TESTBUS_1052___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1052__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1052__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1053               (0x00AAB358)
#define   WMAC0_HWSCH_R0_TESTBUS_1053___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1053__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1053__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1054               (0x00AAB35C)
#define   WMAC0_HWSCH_R0_TESTBUS_1054___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1054__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1054__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1055               (0x00AAB360)
#define   WMAC0_HWSCH_R0_TESTBUS_1055___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1055__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1055__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1056               (0x00AAB364)
#define   WMAC0_HWSCH_R0_TESTBUS_1056___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1056__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1056__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1057               (0x00AAB368)
#define   WMAC0_HWSCH_R0_TESTBUS_1057___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1057__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1057__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1058               (0x00AAB36C)
#define   WMAC0_HWSCH_R0_TESTBUS_1058___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1058__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1058__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1059               (0x00AAB370)
#define   WMAC0_HWSCH_R0_TESTBUS_1059___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1059__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1059__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1060               (0x00AAB374)
#define   WMAC0_HWSCH_R0_TESTBUS_1060___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1060__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1060__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1061               (0x00AAB378)
#define   WMAC0_HWSCH_R0_TESTBUS_1061___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1061__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1061__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1062               (0x00AAB37C)
#define   WMAC0_HWSCH_R0_TESTBUS_1062___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1062__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1062__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1063               (0x00AAB380)
#define   WMAC0_HWSCH_R0_TESTBUS_1063___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1063__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1063__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1064               (0x00AAB384)
#define   WMAC0_HWSCH_R0_TESTBUS_1064___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1064__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1064__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1065               (0x00AAB388)
#define   WMAC0_HWSCH_R0_TESTBUS_1065___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1065__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1065__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1066               (0x00AAB38C)
#define   WMAC0_HWSCH_R0_TESTBUS_1066___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1066__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1066__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1067               (0x00AAB390)
#define   WMAC0_HWSCH_R0_TESTBUS_1067___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1067__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1067__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1068               (0x00AAB394)
#define   WMAC0_HWSCH_R0_TESTBUS_1068___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1068__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1068__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1069               (0x00AAB398)
#define   WMAC0_HWSCH_R0_TESTBUS_1069___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1069__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1069__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1070               (0x00AAB39C)
#define   WMAC0_HWSCH_R0_TESTBUS_1070___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1070__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1070__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1071               (0x00AAB3A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1071___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1071__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1071__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1072               (0x00AAB3A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1072___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1072__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1072__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1073               (0x00AAB3A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1073___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1073__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1073__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1074               (0x00AAB3AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1074___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1074__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1074__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1075               (0x00AAB3B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1075___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1075__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1075__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1076               (0x00AAB3B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1076___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1076__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1076__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1077               (0x00AAB3B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1077___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1077__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1077__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1078               (0x00AAB3BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1078___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1078__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1078__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1079               (0x00AAB3C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1079___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1079__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1079__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1080               (0x00AAB3C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1080___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1080__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1080__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1081               (0x00AAB3C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1081___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1081__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1081__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1082               (0x00AAB3CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1082___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1082__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1082__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1083               (0x00AAB3D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1083___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1083__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1083__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1084               (0x00AAB3D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1084___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1084__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1084__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1085               (0x00AAB3D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1085___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1085__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1085__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1086               (0x00AAB3DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1086___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1086__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1086__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1087               (0x00AAB3E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1087___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1087__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1087__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1088               (0x00AAB3E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1088___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1088__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1088__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1089               (0x00AAB3E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1089___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1089__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1089__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1090               (0x00AAB3EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1090___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1090__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1090__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1091               (0x00AAB3F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1091___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1091__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1091__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1092               (0x00AAB3F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1092___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1092__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1092__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1093               (0x00AAB3F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1093___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1093__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1093__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1094               (0x00AAB3FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1094___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1094__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1094__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1095               (0x00AAB400)
#define   WMAC0_HWSCH_R0_TESTBUS_1095___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1095__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1095__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1096               (0x00AAB404)
#define   WMAC0_HWSCH_R0_TESTBUS_1096___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1096__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1096__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1097               (0x00AAB408)
#define   WMAC0_HWSCH_R0_TESTBUS_1097___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1097__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1097__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1098               (0x00AAB40C)
#define   WMAC0_HWSCH_R0_TESTBUS_1098___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1098__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1098__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1099               (0x00AAB410)
#define   WMAC0_HWSCH_R0_TESTBUS_1099___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1099__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1099__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1100               (0x00AAB414)
#define   WMAC0_HWSCH_R0_TESTBUS_1100___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1100__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1100__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1101               (0x00AAB418)
#define   WMAC0_HWSCH_R0_TESTBUS_1101___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1101__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1101__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1102               (0x00AAB41C)
#define   WMAC0_HWSCH_R0_TESTBUS_1102___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1102__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1102__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1103               (0x00AAB420)
#define   WMAC0_HWSCH_R0_TESTBUS_1103___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1103__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1103__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1104               (0x00AAB424)
#define   WMAC0_HWSCH_R0_TESTBUS_1104___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1104__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1104__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1105               (0x00AAB428)
#define   WMAC0_HWSCH_R0_TESTBUS_1105___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1105__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1105__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1106               (0x00AAB42C)
#define   WMAC0_HWSCH_R0_TESTBUS_1106___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1106__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1106__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1107               (0x00AAB430)
#define   WMAC0_HWSCH_R0_TESTBUS_1107___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1107__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1107__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1108               (0x00AAB434)
#define   WMAC0_HWSCH_R0_TESTBUS_1108___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1108__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1108__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1109               (0x00AAB438)
#define   WMAC0_HWSCH_R0_TESTBUS_1109___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1109__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1109__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1110               (0x00AAB43C)
#define   WMAC0_HWSCH_R0_TESTBUS_1110___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1110__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1110__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1111               (0x00AAB440)
#define   WMAC0_HWSCH_R0_TESTBUS_1111___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1111__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1111__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1112               (0x00AAB444)
#define   WMAC0_HWSCH_R0_TESTBUS_1112___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1112__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1112__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1113               (0x00AAB448)
#define   WMAC0_HWSCH_R0_TESTBUS_1113___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1113__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1113__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1114               (0x00AAB44C)
#define   WMAC0_HWSCH_R0_TESTBUS_1114___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1114__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1114__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1115               (0x00AAB450)
#define   WMAC0_HWSCH_R0_TESTBUS_1115___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1115__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1115__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1116               (0x00AAB454)
#define   WMAC0_HWSCH_R0_TESTBUS_1116___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1116__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1116__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1117               (0x00AAB458)
#define   WMAC0_HWSCH_R0_TESTBUS_1117___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1117__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1117__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1118               (0x00AAB45C)
#define   WMAC0_HWSCH_R0_TESTBUS_1118___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1118__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1118__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1119               (0x00AAB460)
#define   WMAC0_HWSCH_R0_TESTBUS_1119___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1119__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1119__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1120               (0x00AAB464)
#define   WMAC0_HWSCH_R0_TESTBUS_1120___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1120__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1120__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1121               (0x00AAB468)
#define   WMAC0_HWSCH_R0_TESTBUS_1121___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1121__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1121__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1122               (0x00AAB46C)
#define   WMAC0_HWSCH_R0_TESTBUS_1122___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1122__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1122__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1123               (0x00AAB470)
#define   WMAC0_HWSCH_R0_TESTBUS_1123___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1123__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1123__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1124               (0x00AAB474)
#define   WMAC0_HWSCH_R0_TESTBUS_1124___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1124__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1124__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1125               (0x00AAB478)
#define   WMAC0_HWSCH_R0_TESTBUS_1125___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1125__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1125__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1126               (0x00AAB47C)
#define   WMAC0_HWSCH_R0_TESTBUS_1126___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1126__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1126__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1127               (0x00AAB480)
#define   WMAC0_HWSCH_R0_TESTBUS_1127___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1127__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1127__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1128               (0x00AAB484)
#define   WMAC0_HWSCH_R0_TESTBUS_1128___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1128__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1128__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1129               (0x00AAB488)
#define   WMAC0_HWSCH_R0_TESTBUS_1129___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1129__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1129__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1130               (0x00AAB48C)
#define   WMAC0_HWSCH_R0_TESTBUS_1130___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1130__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1130__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1131               (0x00AAB490)
#define   WMAC0_HWSCH_R0_TESTBUS_1131___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1131__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1131__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1132               (0x00AAB494)
#define   WMAC0_HWSCH_R0_TESTBUS_1132___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1132__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1132__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1133               (0x00AAB498)
#define   WMAC0_HWSCH_R0_TESTBUS_1133___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1133__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1133__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1134               (0x00AAB49C)
#define   WMAC0_HWSCH_R0_TESTBUS_1134___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1134__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1134__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1135               (0x00AAB4A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1135___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1135__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1135__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1136               (0x00AAB4A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1136___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1136__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1136__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1137               (0x00AAB4A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1137___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1137__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1137__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1138               (0x00AAB4AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1138___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1138__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1138__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1139               (0x00AAB4B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1139___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1139__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1139__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1140               (0x00AAB4B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1140___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1140__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1140__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1141               (0x00AAB4B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1141___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1141__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1141__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1142               (0x00AAB4BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1142___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1142__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1142__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1143               (0x00AAB4C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1143___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1143__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1143__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1144               (0x00AAB4C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1144___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1144__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1144__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1145               (0x00AAB4C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1145___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1145__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1145__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1146               (0x00AAB4CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1146___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1146__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1146__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1147               (0x00AAB4D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1147___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1147__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1147__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1148               (0x00AAB4D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1148___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1148__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1148__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1149               (0x00AAB4D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1149___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1149__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1149__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1150               (0x00AAB4DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1150___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1150__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1150__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1151               (0x00AAB4E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1151___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1151__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1151__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1152               (0x00AAB4E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1152___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1152__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1152__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1153               (0x00AAB4E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1153___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1153__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1153__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1154               (0x00AAB4EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1154___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1154__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1154__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1155               (0x00AAB4F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1155___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1155__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1155__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1156               (0x00AAB4F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1156___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1156__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1156__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1157               (0x00AAB4F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1157___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1157__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1157__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1158               (0x00AAB4FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1158___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1158__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1158__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1159               (0x00AAB500)
#define   WMAC0_HWSCH_R0_TESTBUS_1159___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1159__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1159__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1160               (0x00AAB504)
#define   WMAC0_HWSCH_R0_TESTBUS_1160___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1160__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1160__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1161               (0x00AAB508)
#define   WMAC0_HWSCH_R0_TESTBUS_1161___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1161__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1161__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1162               (0x00AAB50C)
#define   WMAC0_HWSCH_R0_TESTBUS_1162___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1162__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1162__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1163               (0x00AAB510)
#define   WMAC0_HWSCH_R0_TESTBUS_1163___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1163__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1163__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1164               (0x00AAB514)
#define   WMAC0_HWSCH_R0_TESTBUS_1164___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1164__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1164__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1165               (0x00AAB518)
#define   WMAC0_HWSCH_R0_TESTBUS_1165___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1165__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1165__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1166               (0x00AAB51C)
#define   WMAC0_HWSCH_R0_TESTBUS_1166___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1166__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1166__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1167               (0x00AAB520)
#define   WMAC0_HWSCH_R0_TESTBUS_1167___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1167__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1167__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1168               (0x00AAB524)
#define   WMAC0_HWSCH_R0_TESTBUS_1168___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1168__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1168__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1169               (0x00AAB528)
#define   WMAC0_HWSCH_R0_TESTBUS_1169___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1169__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1169__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1170               (0x00AAB52C)
#define   WMAC0_HWSCH_R0_TESTBUS_1170___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1170__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1170__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1171               (0x00AAB530)
#define   WMAC0_HWSCH_R0_TESTBUS_1171___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1171__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1171__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1172               (0x00AAB534)
#define   WMAC0_HWSCH_R0_TESTBUS_1172___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1172__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1172__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1173               (0x00AAB538)
#define   WMAC0_HWSCH_R0_TESTBUS_1173___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1173__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1173__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1174               (0x00AAB53C)
#define   WMAC0_HWSCH_R0_TESTBUS_1174___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1174__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1174__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1175               (0x00AAB540)
#define   WMAC0_HWSCH_R0_TESTBUS_1175___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1175__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1175__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1176               (0x00AAB544)
#define   WMAC0_HWSCH_R0_TESTBUS_1176___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1176__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1176__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1177               (0x00AAB548)
#define   WMAC0_HWSCH_R0_TESTBUS_1177___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1177__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1177__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1178               (0x00AAB54C)
#define   WMAC0_HWSCH_R0_TESTBUS_1178___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1178__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1178__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1179               (0x00AAB550)
#define   WMAC0_HWSCH_R0_TESTBUS_1179___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1179__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1179__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1180               (0x00AAB554)
#define   WMAC0_HWSCH_R0_TESTBUS_1180___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1180__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1180__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1181               (0x00AAB558)
#define   WMAC0_HWSCH_R0_TESTBUS_1181___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1181__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1181__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1182               (0x00AAB55C)
#define   WMAC0_HWSCH_R0_TESTBUS_1182___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1182__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1182__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1183               (0x00AAB560)
#define   WMAC0_HWSCH_R0_TESTBUS_1183___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1183__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1183__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1184               (0x00AAB564)
#define   WMAC0_HWSCH_R0_TESTBUS_1184___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1184__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1184__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1185               (0x00AAB568)
#define   WMAC0_HWSCH_R0_TESTBUS_1185___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1185__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1185__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1186               (0x00AAB56C)
#define   WMAC0_HWSCH_R0_TESTBUS_1186___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1186__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1186__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1187               (0x00AAB570)
#define   WMAC0_HWSCH_R0_TESTBUS_1187___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1187__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1187__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1188               (0x00AAB574)
#define   WMAC0_HWSCH_R0_TESTBUS_1188___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1188__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1188__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1189               (0x00AAB578)
#define   WMAC0_HWSCH_R0_TESTBUS_1189___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1189__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1189__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1190               (0x00AAB57C)
#define   WMAC0_HWSCH_R0_TESTBUS_1190___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1190__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1190__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1191               (0x00AAB580)
#define   WMAC0_HWSCH_R0_TESTBUS_1191___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1191__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1191__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1192               (0x00AAB584)
#define   WMAC0_HWSCH_R0_TESTBUS_1192___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1192__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1192__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1193               (0x00AAB588)
#define   WMAC0_HWSCH_R0_TESTBUS_1193___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1193__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1193__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1194               (0x00AAB58C)
#define   WMAC0_HWSCH_R0_TESTBUS_1194___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1194__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1194__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1195               (0x00AAB590)
#define   WMAC0_HWSCH_R0_TESTBUS_1195___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1195__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1195__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1196               (0x00AAB594)
#define   WMAC0_HWSCH_R0_TESTBUS_1196___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1196__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1196__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1197               (0x00AAB598)
#define   WMAC0_HWSCH_R0_TESTBUS_1197___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1197__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1197__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1198               (0x00AAB59C)
#define   WMAC0_HWSCH_R0_TESTBUS_1198___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1198__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1198__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1199               (0x00AAB5A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1199___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1199__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1199__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1200               (0x00AAB5A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1200___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1200__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1200__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1201               (0x00AAB5A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1201___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1201__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1201__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1202               (0x00AAB5AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1202___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1202__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1202__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1203               (0x00AAB5B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1203___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1203__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1203__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1204               (0x00AAB5B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1204___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1204__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1204__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1205               (0x00AAB5B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1205___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1205__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1205__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1206               (0x00AAB5BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1206___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1206__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1206__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1207               (0x00AAB5C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1207___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1207__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1207__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1208               (0x00AAB5C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1208___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1208__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1208__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1209               (0x00AAB5C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1209___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1209__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1209__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1210               (0x00AAB5CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1210___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1210__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1210__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1211               (0x00AAB5D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1211___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1211__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1211__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1212               (0x00AAB5D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1212___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1212__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1212__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1213               (0x00AAB5D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1213___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1213__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1213__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1214               (0x00AAB5DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1214___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1214__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1214__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1215               (0x00AAB5E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1215___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1215__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1215__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1216               (0x00AAB5E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1216___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1216__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1216__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1217               (0x00AAB5E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1217___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1217__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1217__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1218               (0x00AAB5EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1218___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1218__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1218__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1219               (0x00AAB5F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1219___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1219__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1219__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1220               (0x00AAB5F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1220___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1220__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1220__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1221               (0x00AAB5F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1221___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1221__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1221__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1222               (0x00AAB5FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1222___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1222__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1222__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1223               (0x00AAB600)
#define   WMAC0_HWSCH_R0_TESTBUS_1223___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1223__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1223__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1224               (0x00AAB604)
#define   WMAC0_HWSCH_R0_TESTBUS_1224___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1224__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1224__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1225               (0x00AAB608)
#define   WMAC0_HWSCH_R0_TESTBUS_1225___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1225__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1225__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1226               (0x00AAB60C)
#define   WMAC0_HWSCH_R0_TESTBUS_1226___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1226__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1226__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1227               (0x00AAB610)
#define   WMAC0_HWSCH_R0_TESTBUS_1227___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1227__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1227__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1228               (0x00AAB614)
#define   WMAC0_HWSCH_R0_TESTBUS_1228___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1228__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1228__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1229               (0x00AAB618)
#define   WMAC0_HWSCH_R0_TESTBUS_1229___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1229__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1229__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1230               (0x00AAB61C)
#define   WMAC0_HWSCH_R0_TESTBUS_1230___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1230__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1230__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1231               (0x00AAB620)
#define   WMAC0_HWSCH_R0_TESTBUS_1231___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1231__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1231__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1232               (0x00AAB624)
#define   WMAC0_HWSCH_R0_TESTBUS_1232___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1232__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1232__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1233               (0x00AAB628)
#define   WMAC0_HWSCH_R0_TESTBUS_1233___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1233__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1233__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1234               (0x00AAB62C)
#define   WMAC0_HWSCH_R0_TESTBUS_1234___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1234__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1234__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1235               (0x00AAB630)
#define   WMAC0_HWSCH_R0_TESTBUS_1235___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1235__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1235__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1236               (0x00AAB634)
#define   WMAC0_HWSCH_R0_TESTBUS_1236___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1236__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1236__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1237               (0x00AAB638)
#define   WMAC0_HWSCH_R0_TESTBUS_1237___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1237__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1237__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1238               (0x00AAB63C)
#define   WMAC0_HWSCH_R0_TESTBUS_1238___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1238__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1238__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1239               (0x00AAB640)
#define   WMAC0_HWSCH_R0_TESTBUS_1239___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1239__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1239__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1240               (0x00AAB644)
#define   WMAC0_HWSCH_R0_TESTBUS_1240___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1240__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1240__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1241               (0x00AAB648)
#define   WMAC0_HWSCH_R0_TESTBUS_1241___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1241__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1241__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1242               (0x00AAB64C)
#define   WMAC0_HWSCH_R0_TESTBUS_1242___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1242__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1242__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1243               (0x00AAB650)
#define   WMAC0_HWSCH_R0_TESTBUS_1243___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1243__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1243__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1244               (0x00AAB654)
#define   WMAC0_HWSCH_R0_TESTBUS_1244___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1244__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1244__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1245               (0x00AAB658)
#define   WMAC0_HWSCH_R0_TESTBUS_1245___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1245__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1245__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1246               (0x00AAB65C)
#define   WMAC0_HWSCH_R0_TESTBUS_1246___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1246__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1246__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1247               (0x00AAB660)
#define   WMAC0_HWSCH_R0_TESTBUS_1247___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1247__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1247__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1248               (0x00AAB664)
#define   WMAC0_HWSCH_R0_TESTBUS_1248___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1248__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1248__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1249               (0x00AAB668)
#define   WMAC0_HWSCH_R0_TESTBUS_1249___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1249__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1249__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1250               (0x00AAB66C)
#define   WMAC0_HWSCH_R0_TESTBUS_1250___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1250__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1250__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1251               (0x00AAB670)
#define   WMAC0_HWSCH_R0_TESTBUS_1251___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1251__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1251__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1252               (0x00AAB674)
#define   WMAC0_HWSCH_R0_TESTBUS_1252___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1252__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1252__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1253               (0x00AAB678)
#define   WMAC0_HWSCH_R0_TESTBUS_1253___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1253__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1253__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1254               (0x00AAB67C)
#define   WMAC0_HWSCH_R0_TESTBUS_1254___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1254__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1254__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1255               (0x00AAB680)
#define   WMAC0_HWSCH_R0_TESTBUS_1255___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1255__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1255__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1256               (0x00AAB684)
#define   WMAC0_HWSCH_R0_TESTBUS_1256___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1256__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1256__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1257               (0x00AAB688)
#define   WMAC0_HWSCH_R0_TESTBUS_1257___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1257__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1257__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1258               (0x00AAB68C)
#define   WMAC0_HWSCH_R0_TESTBUS_1258___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1258__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1258__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1259               (0x00AAB690)
#define   WMAC0_HWSCH_R0_TESTBUS_1259___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1259__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1259__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1260               (0x00AAB694)
#define   WMAC0_HWSCH_R0_TESTBUS_1260___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1260__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1260__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1261               (0x00AAB698)
#define   WMAC0_HWSCH_R0_TESTBUS_1261___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1261__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1261__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1262               (0x00AAB69C)
#define   WMAC0_HWSCH_R0_TESTBUS_1262___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1262__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1262__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1263               (0x00AAB6A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1263___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1263__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1263__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1264               (0x00AAB6A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1264___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1264__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1264__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1265               (0x00AAB6A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1265___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1265__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1265__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1266               (0x00AAB6AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1266___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1266__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1266__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1267               (0x00AAB6B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1267___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1267__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1267__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1268               (0x00AAB6B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1268___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1268__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1268__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1269               (0x00AAB6B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1269___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1269__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1269__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1270               (0x00AAB6BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1270___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1270__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1270__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1271               (0x00AAB6C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1271___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1271__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1271__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1272               (0x00AAB6C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1272___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1272__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1272__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1273               (0x00AAB6C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1273___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1273__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1273__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1274               (0x00AAB6CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1274___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1274__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1274__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1275               (0x00AAB6D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1275___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1275__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1275__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1276               (0x00AAB6D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1276___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1276__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1276__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1277               (0x00AAB6D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1277___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1277__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1277__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1278               (0x00AAB6DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1278___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1278__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1278__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1279               (0x00AAB6E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1279___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1279__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1279__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1280               (0x00AAB6E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1280___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1280__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1280__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1281               (0x00AAB6E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1281___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1281__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1281__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1282               (0x00AAB6EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1282___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1282__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1282__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1283               (0x00AAB6F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1283___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1283__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1283__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1284               (0x00AAB6F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1284___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1284__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1284__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1285               (0x00AAB6F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1285___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1285__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1285__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1286               (0x00AAB6FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1286___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1286__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1286__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1287               (0x00AAB700)
#define   WMAC0_HWSCH_R0_TESTBUS_1287___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1287__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1287__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1288               (0x00AAB704)
#define   WMAC0_HWSCH_R0_TESTBUS_1288___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1288__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1288__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1289               (0x00AAB708)
#define   WMAC0_HWSCH_R0_TESTBUS_1289___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1289__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1289__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1290               (0x00AAB70C)
#define   WMAC0_HWSCH_R0_TESTBUS_1290___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1290__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1290__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1291               (0x00AAB710)
#define   WMAC0_HWSCH_R0_TESTBUS_1291___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1291__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1291__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1292               (0x00AAB714)
#define   WMAC0_HWSCH_R0_TESTBUS_1292___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1292__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1292__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1293               (0x00AAB718)
#define   WMAC0_HWSCH_R0_TESTBUS_1293___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1293__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1293__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1294               (0x00AAB71C)
#define   WMAC0_HWSCH_R0_TESTBUS_1294___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1294__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1294__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1295               (0x00AAB720)
#define   WMAC0_HWSCH_R0_TESTBUS_1295___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1295__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1295__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1296               (0x00AAB724)
#define   WMAC0_HWSCH_R0_TESTBUS_1296___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1296__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1296__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1297               (0x00AAB728)
#define   WMAC0_HWSCH_R0_TESTBUS_1297___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1297__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1297__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1298               (0x00AAB72C)
#define   WMAC0_HWSCH_R0_TESTBUS_1298___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1298__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1298__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1299               (0x00AAB730)
#define   WMAC0_HWSCH_R0_TESTBUS_1299___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1299__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1299__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1300               (0x00AAB734)
#define   WMAC0_HWSCH_R0_TESTBUS_1300___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1300__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1300__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1301               (0x00AAB738)
#define   WMAC0_HWSCH_R0_TESTBUS_1301___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1301__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1301__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1302               (0x00AAB73C)
#define   WMAC0_HWSCH_R0_TESTBUS_1302___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1302__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1302__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1303               (0x00AAB740)
#define   WMAC0_HWSCH_R0_TESTBUS_1303___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1303__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1303__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1304               (0x00AAB744)
#define   WMAC0_HWSCH_R0_TESTBUS_1304___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1304__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1304__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1305               (0x00AAB748)
#define   WMAC0_HWSCH_R0_TESTBUS_1305___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1305__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1305__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1306               (0x00AAB74C)
#define   WMAC0_HWSCH_R0_TESTBUS_1306___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1306__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1306__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1307               (0x00AAB750)
#define   WMAC0_HWSCH_R0_TESTBUS_1307___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1307__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1307__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1308               (0x00AAB754)
#define   WMAC0_HWSCH_R0_TESTBUS_1308___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1308__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1308__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1309               (0x00AAB758)
#define   WMAC0_HWSCH_R0_TESTBUS_1309___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1309__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1309__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1310               (0x00AAB75C)
#define   WMAC0_HWSCH_R0_TESTBUS_1310___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1310__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1310__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1311               (0x00AAB760)
#define   WMAC0_HWSCH_R0_TESTBUS_1311___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1311__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1311__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1312               (0x00AAB764)
#define   WMAC0_HWSCH_R0_TESTBUS_1312___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1312__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1312__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1313               (0x00AAB768)
#define   WMAC0_HWSCH_R0_TESTBUS_1313___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1313__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1313__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1314               (0x00AAB76C)
#define   WMAC0_HWSCH_R0_TESTBUS_1314___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1314__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1314__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1315               (0x00AAB770)
#define   WMAC0_HWSCH_R0_TESTBUS_1315___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1315__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1315__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1316               (0x00AAB774)
#define   WMAC0_HWSCH_R0_TESTBUS_1316___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1316__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1316__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1317               (0x00AAB778)
#define   WMAC0_HWSCH_R0_TESTBUS_1317___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1317__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1317__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1318               (0x00AAB77C)
#define   WMAC0_HWSCH_R0_TESTBUS_1318___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1318__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1318__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1319               (0x00AAB780)
#define   WMAC0_HWSCH_R0_TESTBUS_1319___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1319__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1319__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1320               (0x00AAB784)
#define   WMAC0_HWSCH_R0_TESTBUS_1320___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1320__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1320__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1321               (0x00AAB788)
#define   WMAC0_HWSCH_R0_TESTBUS_1321___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1321__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1321__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1322               (0x00AAB78C)
#define   WMAC0_HWSCH_R0_TESTBUS_1322___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1322__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1322__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1323               (0x00AAB790)
#define   WMAC0_HWSCH_R0_TESTBUS_1323___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1323__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1323__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1324               (0x00AAB794)
#define   WMAC0_HWSCH_R0_TESTBUS_1324___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1324__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1324__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1325               (0x00AAB798)
#define   WMAC0_HWSCH_R0_TESTBUS_1325___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1325__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1325__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1326               (0x00AAB79C)
#define   WMAC0_HWSCH_R0_TESTBUS_1326___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1326__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1326__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1327               (0x00AAB7A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1327___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1327__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1327__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1328               (0x00AAB7A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1328___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1328__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1328__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1329               (0x00AAB7A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1329___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1329__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1329__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1330               (0x00AAB7AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1330___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1330__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1330__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1331               (0x00AAB7B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1331___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1331__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1331__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1332               (0x00AAB7B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1332___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1332__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1332__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1333               (0x00AAB7B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1333___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1333__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1333__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1334               (0x00AAB7BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1334___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1334__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1334__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1335               (0x00AAB7C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1335___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1335__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1335__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1336               (0x00AAB7C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1336___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1336__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1336__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1337               (0x00AAB7C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1337___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1337__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1337__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1338               (0x00AAB7CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1338___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1338__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1338__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1339               (0x00AAB7D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1339___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1339__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1339__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1340               (0x00AAB7D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1340___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1340__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1340__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1341               (0x00AAB7D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1341___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1341__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1341__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1342               (0x00AAB7DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1342___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1342__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1342__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1343               (0x00AAB7E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1343___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1343__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1343__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1344               (0x00AAB7E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1344___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1344__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1344__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1345               (0x00AAB7E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1345___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1345__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1345__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1346               (0x00AAB7EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1346___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1346__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1346__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1347               (0x00AAB7F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1347___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1347__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1347__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1348               (0x00AAB7F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1348___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1348__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1348__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1349               (0x00AAB7F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1349___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1349__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1349__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1350               (0x00AAB7FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1350___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1350__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1350__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1351               (0x00AAB800)
#define   WMAC0_HWSCH_R0_TESTBUS_1351___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1351__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1351__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1352               (0x00AAB804)
#define   WMAC0_HWSCH_R0_TESTBUS_1352___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1352__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1352__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1353               (0x00AAB808)
#define   WMAC0_HWSCH_R0_TESTBUS_1353___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1353__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1353__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1354               (0x00AAB80C)
#define   WMAC0_HWSCH_R0_TESTBUS_1354___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1354__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1354__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1355               (0x00AAB810)
#define   WMAC0_HWSCH_R0_TESTBUS_1355___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1355__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1355__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1356               (0x00AAB814)
#define   WMAC0_HWSCH_R0_TESTBUS_1356___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1356__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1356__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1357               (0x00AAB818)
#define   WMAC0_HWSCH_R0_TESTBUS_1357___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1357__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1357__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1358               (0x00AAB81C)
#define   WMAC0_HWSCH_R0_TESTBUS_1358___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1358__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1358__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1359               (0x00AAB820)
#define   WMAC0_HWSCH_R0_TESTBUS_1359___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1359__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1359__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1360               (0x00AAB824)
#define   WMAC0_HWSCH_R0_TESTBUS_1360___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1360__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1360__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1361               (0x00AAB828)
#define   WMAC0_HWSCH_R0_TESTBUS_1361___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1361__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1361__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1362               (0x00AAB82C)
#define   WMAC0_HWSCH_R0_TESTBUS_1362___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1362__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1362__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1363               (0x00AAB830)
#define   WMAC0_HWSCH_R0_TESTBUS_1363___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1363__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1363__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1364               (0x00AAB834)
#define   WMAC0_HWSCH_R0_TESTBUS_1364___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1364__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1364__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1365               (0x00AAB838)
#define   WMAC0_HWSCH_R0_TESTBUS_1365___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1365__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1365__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1366               (0x00AAB83C)
#define   WMAC0_HWSCH_R0_TESTBUS_1366___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1366__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1366__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1367               (0x00AAB840)
#define   WMAC0_HWSCH_R0_TESTBUS_1367___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1367__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1367__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1368               (0x00AAB844)
#define   WMAC0_HWSCH_R0_TESTBUS_1368___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1368__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1368__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1369               (0x00AAB848)
#define   WMAC0_HWSCH_R0_TESTBUS_1369___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1369__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1369__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1370               (0x00AAB84C)
#define   WMAC0_HWSCH_R0_TESTBUS_1370___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1370__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1370__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1371               (0x00AAB850)
#define   WMAC0_HWSCH_R0_TESTBUS_1371___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1371__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1371__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1372               (0x00AAB854)
#define   WMAC0_HWSCH_R0_TESTBUS_1372___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1372__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1372__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1373               (0x00AAB858)
#define   WMAC0_HWSCH_R0_TESTBUS_1373___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1373__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1373__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1374               (0x00AAB85C)
#define   WMAC0_HWSCH_R0_TESTBUS_1374___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1374__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1374__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1375               (0x00AAB860)
#define   WMAC0_HWSCH_R0_TESTBUS_1375___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1375__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1375__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1376               (0x00AAB864)
#define   WMAC0_HWSCH_R0_TESTBUS_1376___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1376__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1376__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1377               (0x00AAB868)
#define   WMAC0_HWSCH_R0_TESTBUS_1377___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1377__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1377__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1378               (0x00AAB86C)
#define   WMAC0_HWSCH_R0_TESTBUS_1378___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1378__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1378__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1379               (0x00AAB870)
#define   WMAC0_HWSCH_R0_TESTBUS_1379___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1379__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1379__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1380               (0x00AAB874)
#define   WMAC0_HWSCH_R0_TESTBUS_1380___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1380__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1380__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1381               (0x00AAB878)
#define   WMAC0_HWSCH_R0_TESTBUS_1381___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1381__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1381__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1382               (0x00AAB87C)
#define   WMAC0_HWSCH_R0_TESTBUS_1382___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1382__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1382__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1383               (0x00AAB880)
#define   WMAC0_HWSCH_R0_TESTBUS_1383___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1383__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1383__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1384               (0x00AAB884)
#define   WMAC0_HWSCH_R0_TESTBUS_1384___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1384__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1384__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1385               (0x00AAB888)
#define   WMAC0_HWSCH_R0_TESTBUS_1385___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1385__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1385__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1386               (0x00AAB88C)
#define   WMAC0_HWSCH_R0_TESTBUS_1386___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1386__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1386__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1387               (0x00AAB890)
#define   WMAC0_HWSCH_R0_TESTBUS_1387___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1387__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1387__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1388               (0x00AAB894)
#define   WMAC0_HWSCH_R0_TESTBUS_1388___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1388__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1388__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1389               (0x00AAB898)
#define   WMAC0_HWSCH_R0_TESTBUS_1389___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1389__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1389__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1390               (0x00AAB89C)
#define   WMAC0_HWSCH_R0_TESTBUS_1390___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1390__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1390__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1391               (0x00AAB8A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1391___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1391__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1391__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1392               (0x00AAB8A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1392___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1392__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1392__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1393               (0x00AAB8A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1393___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1393__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1393__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1394               (0x00AAB8AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1394___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1394__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1394__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1395               (0x00AAB8B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1395___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1395__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1395__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1396               (0x00AAB8B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1396___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1396__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1396__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1397               (0x00AAB8B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1397___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1397__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1397__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1398               (0x00AAB8BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1398___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1398__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1398__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1399               (0x00AAB8C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1399___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1399__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1399__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1400               (0x00AAB8C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1400___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1400__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1400__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1401               (0x00AAB8C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1401___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1401__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1401__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1402               (0x00AAB8CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1402___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1402__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1402__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1403               (0x00AAB8D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1403___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1403__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1403__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1404               (0x00AAB8D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1404___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1404__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1404__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1405               (0x00AAB8D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1405___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1405__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1405__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1406               (0x00AAB8DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1406___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1406__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1406__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1407               (0x00AAB8E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1407___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1407__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1407__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1408               (0x00AAB8E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1408___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1408__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1408__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1409               (0x00AAB8E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1409___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1409__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1409__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1410               (0x00AAB8EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1410___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1410__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1410__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1411               (0x00AAB8F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1411___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1411__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1411__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1412               (0x00AAB8F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1412___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1412__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1412__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1413               (0x00AAB8F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1413___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1413__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1413__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1414               (0x00AAB8FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1414___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1414__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1414__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1415               (0x00AAB900)
#define   WMAC0_HWSCH_R0_TESTBUS_1415___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1415__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1415__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1416               (0x00AAB904)
#define   WMAC0_HWSCH_R0_TESTBUS_1416___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1416__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1416__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1417               (0x00AAB908)
#define   WMAC0_HWSCH_R0_TESTBUS_1417___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1417__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1417__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1418               (0x00AAB90C)
#define   WMAC0_HWSCH_R0_TESTBUS_1418___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1418__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1418__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1419               (0x00AAB910)
#define   WMAC0_HWSCH_R0_TESTBUS_1419___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1419__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1419__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1420               (0x00AAB914)
#define   WMAC0_HWSCH_R0_TESTBUS_1420___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1420__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1420__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1421               (0x00AAB918)
#define   WMAC0_HWSCH_R0_TESTBUS_1421___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1421__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1421__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1422               (0x00AAB91C)
#define   WMAC0_HWSCH_R0_TESTBUS_1422___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1422__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1422__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1423               (0x00AAB920)
#define   WMAC0_HWSCH_R0_TESTBUS_1423___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1423__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1423__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1424               (0x00AAB924)
#define   WMAC0_HWSCH_R0_TESTBUS_1424___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1424__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1424__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1425               (0x00AAB928)
#define   WMAC0_HWSCH_R0_TESTBUS_1425___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1425__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1425__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1426               (0x00AAB92C)
#define   WMAC0_HWSCH_R0_TESTBUS_1426___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1426__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1426__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1427               (0x00AAB930)
#define   WMAC0_HWSCH_R0_TESTBUS_1427___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1427__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1427__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1428               (0x00AAB934)
#define   WMAC0_HWSCH_R0_TESTBUS_1428___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1428__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1428__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1429               (0x00AAB938)
#define   WMAC0_HWSCH_R0_TESTBUS_1429___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1429__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1429__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1430               (0x00AAB93C)
#define   WMAC0_HWSCH_R0_TESTBUS_1430___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1430__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1430__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1431               (0x00AAB940)
#define   WMAC0_HWSCH_R0_TESTBUS_1431___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1431__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1431__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1432               (0x00AAB944)
#define   WMAC0_HWSCH_R0_TESTBUS_1432___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1432__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1432__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1433               (0x00AAB948)
#define   WMAC0_HWSCH_R0_TESTBUS_1433___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1433__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1433__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1434               (0x00AAB94C)
#define   WMAC0_HWSCH_R0_TESTBUS_1434___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1434__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1434__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1435               (0x00AAB950)
#define   WMAC0_HWSCH_R0_TESTBUS_1435___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1435__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1435__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1436               (0x00AAB954)
#define   WMAC0_HWSCH_R0_TESTBUS_1436___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1436__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1436__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1437               (0x00AAB958)
#define   WMAC0_HWSCH_R0_TESTBUS_1437___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1437__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1437__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1438               (0x00AAB95C)
#define   WMAC0_HWSCH_R0_TESTBUS_1438___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1438__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1438__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1439               (0x00AAB960)
#define   WMAC0_HWSCH_R0_TESTBUS_1439___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1439__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1439__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1440               (0x00AAB964)
#define   WMAC0_HWSCH_R0_TESTBUS_1440___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1440__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1440__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1441               (0x00AAB968)
#define   WMAC0_HWSCH_R0_TESTBUS_1441___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1441__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1441__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1442               (0x00AAB96C)
#define   WMAC0_HWSCH_R0_TESTBUS_1442___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1442__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1442__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1443               (0x00AAB970)
#define   WMAC0_HWSCH_R0_TESTBUS_1443___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1443__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1443__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1444               (0x00AAB974)
#define   WMAC0_HWSCH_R0_TESTBUS_1444___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1444__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1444__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1445               (0x00AAB978)
#define   WMAC0_HWSCH_R0_TESTBUS_1445___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1445__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1445__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1446               (0x00AAB97C)
#define   WMAC0_HWSCH_R0_TESTBUS_1446___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1446__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1446__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1447               (0x00AAB980)
#define   WMAC0_HWSCH_R0_TESTBUS_1447___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1447__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1447__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1448               (0x00AAB984)
#define   WMAC0_HWSCH_R0_TESTBUS_1448___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1448__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1448__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1449               (0x00AAB988)
#define   WMAC0_HWSCH_R0_TESTBUS_1449___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1449__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1449__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1450               (0x00AAB98C)
#define   WMAC0_HWSCH_R0_TESTBUS_1450___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1450__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1450__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1451               (0x00AAB990)
#define   WMAC0_HWSCH_R0_TESTBUS_1451___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1451__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1451__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1452               (0x00AAB994)
#define   WMAC0_HWSCH_R0_TESTBUS_1452___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1452__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1452__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1453               (0x00AAB998)
#define   WMAC0_HWSCH_R0_TESTBUS_1453___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1453__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1453__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1454               (0x00AAB99C)
#define   WMAC0_HWSCH_R0_TESTBUS_1454___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1454__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1454__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1455               (0x00AAB9A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1455___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1455__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1455__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1456               (0x00AAB9A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1456___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1456__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1456__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1457               (0x00AAB9A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1457___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1457__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1457__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1458               (0x00AAB9AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1458___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1458__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1458__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1459               (0x00AAB9B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1459___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1459__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1459__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1460               (0x00AAB9B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1460___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1460__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1460__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1461               (0x00AAB9B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1461___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1461__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1461__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1462               (0x00AAB9BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1462___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1462__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1462__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1463               (0x00AAB9C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1463___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1463__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1463__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1464               (0x00AAB9C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1464___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1464__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1464__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1465               (0x00AAB9C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1465___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1465__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1465__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1466               (0x00AAB9CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1466___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1466__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1466__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1467               (0x00AAB9D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1467___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1467__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1467__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1468               (0x00AAB9D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1468___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1468__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1468__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1469               (0x00AAB9D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1469___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1469__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1469__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1470               (0x00AAB9DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1470___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1470__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1470__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1471               (0x00AAB9E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1471___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1471__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1471__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1472               (0x00AAB9E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1472___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1472__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1472__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1473               (0x00AAB9E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1473___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1473__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1473__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1474               (0x00AAB9EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1474___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1474__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1474__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1475               (0x00AAB9F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1475___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1475__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1475__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1476               (0x00AAB9F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1476___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1476__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1476__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1477               (0x00AAB9F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1477___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1477__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1477__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1478               (0x00AAB9FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1478___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1478__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1478__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1479               (0x00AABA00)
#define   WMAC0_HWSCH_R0_TESTBUS_1479___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1479__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1479__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1480               (0x00AABA04)
#define   WMAC0_HWSCH_R0_TESTBUS_1480___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1480__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1480__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1481               (0x00AABA08)
#define   WMAC0_HWSCH_R0_TESTBUS_1481___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1481__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1481__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1482               (0x00AABA0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1482___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1482__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1482__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1483               (0x00AABA10)
#define   WMAC0_HWSCH_R0_TESTBUS_1483___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1483__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1483__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1484               (0x00AABA14)
#define   WMAC0_HWSCH_R0_TESTBUS_1484___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1484__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1484__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1485               (0x00AABA18)
#define   WMAC0_HWSCH_R0_TESTBUS_1485___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1485__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1485__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1486               (0x00AABA1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1486___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1486__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1486__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1487               (0x00AABA20)
#define   WMAC0_HWSCH_R0_TESTBUS_1487___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1487__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1487__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1488               (0x00AABA24)
#define   WMAC0_HWSCH_R0_TESTBUS_1488___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1488__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1488__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1489               (0x00AABA28)
#define   WMAC0_HWSCH_R0_TESTBUS_1489___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1489__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1489__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1490               (0x00AABA2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1490___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1490__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1490__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1491               (0x00AABA30)
#define   WMAC0_HWSCH_R0_TESTBUS_1491___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1491__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1491__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1492               (0x00AABA34)
#define   WMAC0_HWSCH_R0_TESTBUS_1492___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1492__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1492__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1493               (0x00AABA38)
#define   WMAC0_HWSCH_R0_TESTBUS_1493___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1493__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1493__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1494               (0x00AABA3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1494___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1494__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1494__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1495               (0x00AABA40)
#define   WMAC0_HWSCH_R0_TESTBUS_1495___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1495__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1495__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1496               (0x00AABA44)
#define   WMAC0_HWSCH_R0_TESTBUS_1496___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1496__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1496__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1497               (0x00AABA48)
#define   WMAC0_HWSCH_R0_TESTBUS_1497___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1497__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1497__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1498               (0x00AABA4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1498___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1498__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1498__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1499               (0x00AABA50)
#define   WMAC0_HWSCH_R0_TESTBUS_1499___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1499__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1499__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1500               (0x00AABA54)
#define   WMAC0_HWSCH_R0_TESTBUS_1500___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1500__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1500__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1501               (0x00AABA58)
#define   WMAC0_HWSCH_R0_TESTBUS_1501___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1501__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1501__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1502               (0x00AABA5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1502___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1502__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1502__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1503               (0x00AABA60)
#define   WMAC0_HWSCH_R0_TESTBUS_1503___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1503__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1503__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1504               (0x00AABA64)
#define   WMAC0_HWSCH_R0_TESTBUS_1504___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1504__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1504__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1505               (0x00AABA68)
#define   WMAC0_HWSCH_R0_TESTBUS_1505___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1505__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1505__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1506               (0x00AABA6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1506___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1506__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1506__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1507               (0x00AABA70)
#define   WMAC0_HWSCH_R0_TESTBUS_1507___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1507__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1507__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1508               (0x00AABA74)
#define   WMAC0_HWSCH_R0_TESTBUS_1508___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1508__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1508__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1509               (0x00AABA78)
#define   WMAC0_HWSCH_R0_TESTBUS_1509___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1509__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1509__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1510               (0x00AABA7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1510___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1510__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1510__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1511               (0x00AABA80)
#define   WMAC0_HWSCH_R0_TESTBUS_1511___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1511__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1511__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1512               (0x00AABA84)
#define   WMAC0_HWSCH_R0_TESTBUS_1512___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1512__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1512__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1513               (0x00AABA88)
#define   WMAC0_HWSCH_R0_TESTBUS_1513___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1513__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1513__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1514               (0x00AABA8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1514___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1514__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1514__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1515               (0x00AABA90)
#define   WMAC0_HWSCH_R0_TESTBUS_1515___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1515__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1515__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1516               (0x00AABA94)
#define   WMAC0_HWSCH_R0_TESTBUS_1516___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1516__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1516__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1517               (0x00AABA98)
#define   WMAC0_HWSCH_R0_TESTBUS_1517___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1517__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1517__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1518               (0x00AABA9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1518___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1518__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1518__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1519               (0x00AABAA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1519___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1519__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1519__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1520               (0x00AABAA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1520___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1520__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1520__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1521               (0x00AABAA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1521___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1521__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1521__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1522               (0x00AABAAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1522___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1522__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1522__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1523               (0x00AABAB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1523___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1523__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1523__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1524               (0x00AABAB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1524___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1524__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1524__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1525               (0x00AABAB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1525___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1525__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1525__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1526               (0x00AABABC)
#define   WMAC0_HWSCH_R0_TESTBUS_1526___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1526__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1526__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1527               (0x00AABAC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1527___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1527__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1527__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1528               (0x00AABAC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1528___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1528__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1528__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1529               (0x00AABAC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1529___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1529__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1529__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1530               (0x00AABACC)
#define   WMAC0_HWSCH_R0_TESTBUS_1530___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1530__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1530__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1531               (0x00AABAD0)
#define   WMAC0_HWSCH_R0_TESTBUS_1531___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1531__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1531__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1532               (0x00AABAD4)
#define   WMAC0_HWSCH_R0_TESTBUS_1532___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1532__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1532__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1533               (0x00AABAD8)
#define   WMAC0_HWSCH_R0_TESTBUS_1533___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1533__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1533__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1534               (0x00AABADC)
#define   WMAC0_HWSCH_R0_TESTBUS_1534___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1534__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1534__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1535               (0x00AABAE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1535___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1535__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1535__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1536               (0x00AABAE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1536___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1536__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1536__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1537               (0x00AABAE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1537___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1537__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1537__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1538               (0x00AABAEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1538___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1538__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1538__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1539               (0x00AABAF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1539___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1539__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1539__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1540               (0x00AABAF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1540___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1540__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1540__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1541               (0x00AABAF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1541___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1541__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1541__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1542               (0x00AABAFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1542___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1542__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1542__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1543               (0x00AABB00)
#define   WMAC0_HWSCH_R0_TESTBUS_1543___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1543__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1543__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1544               (0x00AABB04)
#define   WMAC0_HWSCH_R0_TESTBUS_1544___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1544__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1544__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1545               (0x00AABB08)
#define   WMAC0_HWSCH_R0_TESTBUS_1545___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1545__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1545__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1546               (0x00AABB0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1546___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1546__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1546__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1547               (0x00AABB10)
#define   WMAC0_HWSCH_R0_TESTBUS_1547___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1547__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1547__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1548               (0x00AABB14)
#define   WMAC0_HWSCH_R0_TESTBUS_1548___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1548__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1548__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1549               (0x00AABB18)
#define   WMAC0_HWSCH_R0_TESTBUS_1549___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1549__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1549__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1550               (0x00AABB1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1550___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1550__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1550__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1551               (0x00AABB20)
#define   WMAC0_HWSCH_R0_TESTBUS_1551___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1551__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1551__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1552               (0x00AABB24)
#define   WMAC0_HWSCH_R0_TESTBUS_1552___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1552__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1552__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1553               (0x00AABB28)
#define   WMAC0_HWSCH_R0_TESTBUS_1553___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1553__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1553__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1554               (0x00AABB2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1554___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1554__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1554__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1555               (0x00AABB30)
#define   WMAC0_HWSCH_R0_TESTBUS_1555___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1555__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1555__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1556               (0x00AABB34)
#define   WMAC0_HWSCH_R0_TESTBUS_1556___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1556__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1556__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1557               (0x00AABB38)
#define   WMAC0_HWSCH_R0_TESTBUS_1557___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1557__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1557__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1558               (0x00AABB3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1558___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1558__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1558__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1559               (0x00AABB40)
#define   WMAC0_HWSCH_R0_TESTBUS_1559___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1559__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1559__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1560               (0x00AABB44)
#define   WMAC0_HWSCH_R0_TESTBUS_1560___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1560__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1560__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1561               (0x00AABB48)
#define   WMAC0_HWSCH_R0_TESTBUS_1561___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1561__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1561__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1562               (0x00AABB4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1562___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1562__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1562__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1563               (0x00AABB50)
#define   WMAC0_HWSCH_R0_TESTBUS_1563___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1563__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1563__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1564               (0x00AABB54)
#define   WMAC0_HWSCH_R0_TESTBUS_1564___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1564__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1564__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1565               (0x00AABB58)
#define   WMAC0_HWSCH_R0_TESTBUS_1565___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1565__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1565__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1566               (0x00AABB5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1566___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1566__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1566__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1567               (0x00AABB60)
#define   WMAC0_HWSCH_R0_TESTBUS_1567___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1567__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1567__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1568               (0x00AABB64)
#define   WMAC0_HWSCH_R0_TESTBUS_1568___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1568__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1568__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1569               (0x00AABB68)
#define   WMAC0_HWSCH_R0_TESTBUS_1569___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1569__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1569__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1570               (0x00AABB6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1570___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1570__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1570__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1571               (0x00AABB70)
#define   WMAC0_HWSCH_R0_TESTBUS_1571___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1571__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1571__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1572               (0x00AABB74)
#define   WMAC0_HWSCH_R0_TESTBUS_1572___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1572__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1572__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1573               (0x00AABB78)
#define   WMAC0_HWSCH_R0_TESTBUS_1573___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1573__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1573__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1574               (0x00AABB7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1574___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1574__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1574__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1575               (0x00AABB80)
#define   WMAC0_HWSCH_R0_TESTBUS_1575___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1575__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1575__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1576               (0x00AABB84)
#define   WMAC0_HWSCH_R0_TESTBUS_1576___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1576__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1576__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1577               (0x00AABB88)
#define   WMAC0_HWSCH_R0_TESTBUS_1577___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1577__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1577__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1578               (0x00AABB8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1578___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1578__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1578__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1579               (0x00AABB90)
#define   WMAC0_HWSCH_R0_TESTBUS_1579___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1579__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1579__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1580               (0x00AABB94)
#define   WMAC0_HWSCH_R0_TESTBUS_1580___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1580__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1580__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1581               (0x00AABB98)
#define   WMAC0_HWSCH_R0_TESTBUS_1581___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1581__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1581__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1582               (0x00AABB9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1582___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1582__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1582__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1583               (0x00AABBA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1583___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1583__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1583__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1584               (0x00AABBA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1584___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1584__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1584__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1585               (0x00AABBA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1585___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1585__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1585__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1586               (0x00AABBAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1586___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1586__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1586__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1587               (0x00AABBB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1587___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1587__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1587__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1588               (0x00AABBB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1588___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1588__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1588__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1589               (0x00AABBB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1589___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1589__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1589__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1590               (0x00AABBBC)
#define   WMAC0_HWSCH_R0_TESTBUS_1590___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1590__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1590__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1591               (0x00AABBC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1591___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1591__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1591__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1592               (0x00AABBC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1592___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1592__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1592__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1593               (0x00AABBC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1593___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1593__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1593__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1594               (0x00AABBCC)
#define   WMAC0_HWSCH_R0_TESTBUS_1594___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1594__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1594__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1595               (0x00AABBD0)
#define   WMAC0_HWSCH_R0_TESTBUS_1595___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1595__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1595__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1596               (0x00AABBD4)
#define   WMAC0_HWSCH_R0_TESTBUS_1596___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1596__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1596__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1597               (0x00AABBD8)
#define   WMAC0_HWSCH_R0_TESTBUS_1597___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1597__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1597__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1598               (0x00AABBDC)
#define   WMAC0_HWSCH_R0_TESTBUS_1598___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1598__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1598__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1599               (0x00AABBE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1599___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1599__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1599__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1600               (0x00AABBE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1600___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1600__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1600__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1601               (0x00AABBE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1601___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1601__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1601__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1602               (0x00AABBEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1602___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1602__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1602__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1603               (0x00AABBF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1603___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1603__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1603__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1604               (0x00AABBF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1604___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1604__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1604__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1605               (0x00AABBF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1605___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1605__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1605__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1606               (0x00AABBFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1606___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1606__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1606__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1607               (0x00AABC00)
#define   WMAC0_HWSCH_R0_TESTBUS_1607___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1607__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1607__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1608               (0x00AABC04)
#define   WMAC0_HWSCH_R0_TESTBUS_1608___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1608__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1608__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1609               (0x00AABC08)
#define   WMAC0_HWSCH_R0_TESTBUS_1609___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1609__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1609__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1610               (0x00AABC0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1610___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1610__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1610__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1611               (0x00AABC10)
#define   WMAC0_HWSCH_R0_TESTBUS_1611___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1611__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1611__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1612               (0x00AABC14)
#define   WMAC0_HWSCH_R0_TESTBUS_1612___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1612__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1612__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1613               (0x00AABC18)
#define   WMAC0_HWSCH_R0_TESTBUS_1613___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1613__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1613__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1614               (0x00AABC1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1614___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1614__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1614__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1615               (0x00AABC20)
#define   WMAC0_HWSCH_R0_TESTBUS_1615___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1615__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1615__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1616               (0x00AABC24)
#define   WMAC0_HWSCH_R0_TESTBUS_1616___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1616__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1616__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1617               (0x00AABC28)
#define   WMAC0_HWSCH_R0_TESTBUS_1617___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1617__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1617__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1618               (0x00AABC2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1618___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1618__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1618__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1619               (0x00AABC30)
#define   WMAC0_HWSCH_R0_TESTBUS_1619___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1619__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1619__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1620               (0x00AABC34)
#define   WMAC0_HWSCH_R0_TESTBUS_1620___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1620__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1620__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1621               (0x00AABC38)
#define   WMAC0_HWSCH_R0_TESTBUS_1621___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1621__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1621__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1622               (0x00AABC3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1622___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1622__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1622__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1623               (0x00AABC40)
#define   WMAC0_HWSCH_R0_TESTBUS_1623___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1623__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1623__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1624               (0x00AABC44)
#define   WMAC0_HWSCH_R0_TESTBUS_1624___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1624__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1624__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1625               (0x00AABC48)
#define   WMAC0_HWSCH_R0_TESTBUS_1625___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1625__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1625__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1626               (0x00AABC4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1626___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1626__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1626__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1627               (0x00AABC50)
#define   WMAC0_HWSCH_R0_TESTBUS_1627___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1627__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1627__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1628               (0x00AABC54)
#define   WMAC0_HWSCH_R0_TESTBUS_1628___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1628__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1628__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1629               (0x00AABC58)
#define   WMAC0_HWSCH_R0_TESTBUS_1629___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1629__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1629__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1630               (0x00AABC5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1630___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1630__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1630__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1631               (0x00AABC60)
#define   WMAC0_HWSCH_R0_TESTBUS_1631___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1631__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1631__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1632               (0x00AABC64)
#define   WMAC0_HWSCH_R0_TESTBUS_1632___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1632__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1632__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1633               (0x00AABC68)
#define   WMAC0_HWSCH_R0_TESTBUS_1633___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1633__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1633__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1634               (0x00AABC6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1634___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1634__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1634__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1635               (0x00AABC70)
#define   WMAC0_HWSCH_R0_TESTBUS_1635___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1635__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1635__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1636               (0x00AABC74)
#define   WMAC0_HWSCH_R0_TESTBUS_1636___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1636__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1636__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1637               (0x00AABC78)
#define   WMAC0_HWSCH_R0_TESTBUS_1637___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1637__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1637__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1638               (0x00AABC7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1638___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1638__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1638__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1639               (0x00AABC80)
#define   WMAC0_HWSCH_R0_TESTBUS_1639___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1639__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1639__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1640               (0x00AABC84)
#define   WMAC0_HWSCH_R0_TESTBUS_1640___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1640__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1640__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1641               (0x00AABC88)
#define   WMAC0_HWSCH_R0_TESTBUS_1641___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1641__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1641__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1642               (0x00AABC8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1642___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1642__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1642__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1643               (0x00AABC90)
#define   WMAC0_HWSCH_R0_TESTBUS_1643___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1643__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1643__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1644               (0x00AABC94)
#define   WMAC0_HWSCH_R0_TESTBUS_1644___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1644__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1644__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1645               (0x00AABC98)
#define   WMAC0_HWSCH_R0_TESTBUS_1645___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1645__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1645__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1646               (0x00AABC9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1646___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1646__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1646__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1647               (0x00AABCA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1647___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1647__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1647__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1648               (0x00AABCA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1648___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1648__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1648__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1649               (0x00AABCA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1649___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1649__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1649__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1650               (0x00AABCAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1650___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1650__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1650__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1651               (0x00AABCB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1651___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1651__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1651__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1652               (0x00AABCB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1652___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1652__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1652__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1653               (0x00AABCB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1653___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1653__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1653__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1654               (0x00AABCBC)
#define   WMAC0_HWSCH_R0_TESTBUS_1654___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1654__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1654__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1655               (0x00AABCC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1655___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1655__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1655__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1656               (0x00AABCC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1656___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1656__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1656__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1657               (0x00AABCC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1657___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1657__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1657__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1658               (0x00AABCCC)
#define   WMAC0_HWSCH_R0_TESTBUS_1658___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1658__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1658__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1659               (0x00AABCD0)
#define   WMAC0_HWSCH_R0_TESTBUS_1659___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1659__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1659__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1660               (0x00AABCD4)
#define   WMAC0_HWSCH_R0_TESTBUS_1660___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1660__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1660__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1661               (0x00AABCD8)
#define   WMAC0_HWSCH_R0_TESTBUS_1661___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1661__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1661__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1662               (0x00AABCDC)
#define   WMAC0_HWSCH_R0_TESTBUS_1662___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1662__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1662__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1663               (0x00AABCE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1663___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1663__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1663__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1664               (0x00AABCE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1664___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1664__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1664__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1665               (0x00AABCE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1665___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1665__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1665__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1666               (0x00AABCEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1666___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1666__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1666__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1667               (0x00AABCF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1667___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1667__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1667__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1668               (0x00AABCF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1668___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1668__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1668__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1669               (0x00AABCF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1669___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1669__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1669__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1670               (0x00AABCFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1670___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1670__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1670__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1671               (0x00AABD00)
#define   WMAC0_HWSCH_R0_TESTBUS_1671___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1671__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1671__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1672               (0x00AABD04)
#define   WMAC0_HWSCH_R0_TESTBUS_1672___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1672__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1672__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1673               (0x00AABD08)
#define   WMAC0_HWSCH_R0_TESTBUS_1673___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1673__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1673__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1674               (0x00AABD0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1674___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1674__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1674__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1675               (0x00AABD10)
#define   WMAC0_HWSCH_R0_TESTBUS_1675___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1675__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1675__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1676               (0x00AABD14)
#define   WMAC0_HWSCH_R0_TESTBUS_1676___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1676__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1676__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1677               (0x00AABD18)
#define   WMAC0_HWSCH_R0_TESTBUS_1677___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1677__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1677__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1678               (0x00AABD1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1678___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1678__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1678__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1679               (0x00AABD20)
#define   WMAC0_HWSCH_R0_TESTBUS_1679___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1679__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1679__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1680               (0x00AABD24)
#define   WMAC0_HWSCH_R0_TESTBUS_1680___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1680__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1680__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1681               (0x00AABD28)
#define   WMAC0_HWSCH_R0_TESTBUS_1681___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1681__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1681__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1682               (0x00AABD2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1682___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1682__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1682__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1683               (0x00AABD30)
#define   WMAC0_HWSCH_R0_TESTBUS_1683___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1683__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1683__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1684               (0x00AABD34)
#define   WMAC0_HWSCH_R0_TESTBUS_1684___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1684__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1684__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1685               (0x00AABD38)
#define   WMAC0_HWSCH_R0_TESTBUS_1685___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1685__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1685__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1686               (0x00AABD3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1686___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1686__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1686__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1687               (0x00AABD40)
#define   WMAC0_HWSCH_R0_TESTBUS_1687___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1687__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1687__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1688               (0x00AABD44)
#define   WMAC0_HWSCH_R0_TESTBUS_1688___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1688__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1688__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1689               (0x00AABD48)
#define   WMAC0_HWSCH_R0_TESTBUS_1689___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1689__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1689__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1690               (0x00AABD4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1690___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1690__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1690__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1691               (0x00AABD50)
#define   WMAC0_HWSCH_R0_TESTBUS_1691___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1691__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1691__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1692               (0x00AABD54)
#define   WMAC0_HWSCH_R0_TESTBUS_1692___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1692__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1692__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1693               (0x00AABD58)
#define   WMAC0_HWSCH_R0_TESTBUS_1693___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1693__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1693__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1694               (0x00AABD5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1694___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1694__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1694__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1695               (0x00AABD60)
#define   WMAC0_HWSCH_R0_TESTBUS_1695___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1695__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1695__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1696               (0x00AABD64)
#define   WMAC0_HWSCH_R0_TESTBUS_1696___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1696__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1696__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1697               (0x00AABD68)
#define   WMAC0_HWSCH_R0_TESTBUS_1697___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1697__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1697__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1698               (0x00AABD6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1698___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1698__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1698__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1699               (0x00AABD70)
#define   WMAC0_HWSCH_R0_TESTBUS_1699___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1699__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1699__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1700               (0x00AABD74)
#define   WMAC0_HWSCH_R0_TESTBUS_1700___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1700__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1700__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1701               (0x00AABD78)
#define   WMAC0_HWSCH_R0_TESTBUS_1701___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1701__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1701__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1702               (0x00AABD7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1702___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1702__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1702__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1703               (0x00AABD80)
#define   WMAC0_HWSCH_R0_TESTBUS_1703___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1703__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1703__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1704               (0x00AABD84)
#define   WMAC0_HWSCH_R0_TESTBUS_1704___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1704__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1704__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1705               (0x00AABD88)
#define   WMAC0_HWSCH_R0_TESTBUS_1705___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1705__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1705__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1706               (0x00AABD8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1706___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1706__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1706__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1707               (0x00AABD90)
#define   WMAC0_HWSCH_R0_TESTBUS_1707___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1707__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1707__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1708               (0x00AABD94)
#define   WMAC0_HWSCH_R0_TESTBUS_1708___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1708__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1708__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1709               (0x00AABD98)
#define   WMAC0_HWSCH_R0_TESTBUS_1709___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1709__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1709__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1710               (0x00AABD9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1710___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1710__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1710__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1711               (0x00AABDA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1711___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1711__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1711__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1712               (0x00AABDA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1712___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1712__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1712__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1713               (0x00AABDA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1713___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1713__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1713__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1714               (0x00AABDAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1714___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1714__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1714__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1715               (0x00AABDB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1715___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1715__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1715__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1716               (0x00AABDB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1716___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1716__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1716__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1717               (0x00AABDB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1717___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1717__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1717__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1718               (0x00AABDBC)
#define   WMAC0_HWSCH_R0_TESTBUS_1718___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1718__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1718__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1719               (0x00AABDC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1719___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1719__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1719__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1720               (0x00AABDC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1720___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1720__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1720__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1721               (0x00AABDC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1721___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1721__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1721__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1722               (0x00AABDCC)
#define   WMAC0_HWSCH_R0_TESTBUS_1722___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1722__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1722__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1723               (0x00AABDD0)
#define   WMAC0_HWSCH_R0_TESTBUS_1723___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1723__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1723__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1724               (0x00AABDD4)
#define   WMAC0_HWSCH_R0_TESTBUS_1724___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1724__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1724__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1725               (0x00AABDD8)
#define   WMAC0_HWSCH_R0_TESTBUS_1725___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1725__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1725__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1726               (0x00AABDDC)
#define   WMAC0_HWSCH_R0_TESTBUS_1726___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1726__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1726__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1727               (0x00AABDE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1727___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1727__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1727__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1728               (0x00AABDE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1728___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1728__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1728__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1729               (0x00AABDE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1729___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1729__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1729__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1730               (0x00AABDEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1730___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1730__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1730__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1731               (0x00AABDF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1731___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1731__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1731__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1732               (0x00AABDF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1732___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1732__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1732__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1733               (0x00AABDF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1733___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1733__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1733__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1734               (0x00AABDFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1734___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1734__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1734__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1735               (0x00AABE00)
#define   WMAC0_HWSCH_R0_TESTBUS_1735___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1735__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1735__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1736               (0x00AABE04)
#define   WMAC0_HWSCH_R0_TESTBUS_1736___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1736__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1736__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1737               (0x00AABE08)
#define   WMAC0_HWSCH_R0_TESTBUS_1737___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1737__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1737__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1738               (0x00AABE0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1738___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1738__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1738__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1739               (0x00AABE10)
#define   WMAC0_HWSCH_R0_TESTBUS_1739___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1739__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1739__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1740               (0x00AABE14)
#define   WMAC0_HWSCH_R0_TESTBUS_1740___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1740__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1740__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1741               (0x00AABE18)
#define   WMAC0_HWSCH_R0_TESTBUS_1741___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1741__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1741__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1742               (0x00AABE1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1742___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1742__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1742__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1743               (0x00AABE20)
#define   WMAC0_HWSCH_R0_TESTBUS_1743___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1743__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1743__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1744               (0x00AABE24)
#define   WMAC0_HWSCH_R0_TESTBUS_1744___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1744__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1744__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1745               (0x00AABE28)
#define   WMAC0_HWSCH_R0_TESTBUS_1745___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1745__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1745__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1746               (0x00AABE2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1746___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1746__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1746__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1747               (0x00AABE30)
#define   WMAC0_HWSCH_R0_TESTBUS_1747___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1747__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1747__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1748               (0x00AABE34)
#define   WMAC0_HWSCH_R0_TESTBUS_1748___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1748__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1748__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1749               (0x00AABE38)
#define   WMAC0_HWSCH_R0_TESTBUS_1749___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1749__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1749__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1750               (0x00AABE3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1750___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1750__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1750__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1751               (0x00AABE40)
#define   WMAC0_HWSCH_R0_TESTBUS_1751___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1751__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1751__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1752               (0x00AABE44)
#define   WMAC0_HWSCH_R0_TESTBUS_1752___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1752__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1752__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1753               (0x00AABE48)
#define   WMAC0_HWSCH_R0_TESTBUS_1753___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1753__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1753__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1754               (0x00AABE4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1754___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1754__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1754__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1755               (0x00AABE50)
#define   WMAC0_HWSCH_R0_TESTBUS_1755___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1755__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1755__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1756               (0x00AABE54)
#define   WMAC0_HWSCH_R0_TESTBUS_1756___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1756__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1756__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1757               (0x00AABE58)
#define   WMAC0_HWSCH_R0_TESTBUS_1757___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1757__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1757__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1758               (0x00AABE5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1758___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1758__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1758__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1759               (0x00AABE60)
#define   WMAC0_HWSCH_R0_TESTBUS_1759___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1759__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1759__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1760               (0x00AABE64)
#define   WMAC0_HWSCH_R0_TESTBUS_1760___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1760__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1760__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1761               (0x00AABE68)
#define   WMAC0_HWSCH_R0_TESTBUS_1761___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1761__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1761__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1762               (0x00AABE6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1762___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1762__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1762__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1763               (0x00AABE70)
#define   WMAC0_HWSCH_R0_TESTBUS_1763___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1763__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1763__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1764               (0x00AABE74)
#define   WMAC0_HWSCH_R0_TESTBUS_1764___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1764__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1764__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1765               (0x00AABE78)
#define   WMAC0_HWSCH_R0_TESTBUS_1765___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1765__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1765__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1766               (0x00AABE7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1766___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1766__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1766__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1767               (0x00AABE80)
#define   WMAC0_HWSCH_R0_TESTBUS_1767___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1767__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1767__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1768               (0x00AABE84)
#define   WMAC0_HWSCH_R0_TESTBUS_1768___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1768__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1768__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1769               (0x00AABE88)
#define   WMAC0_HWSCH_R0_TESTBUS_1769___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1769__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1769__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1770               (0x00AABE8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1770___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1770__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1770__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1771               (0x00AABE90)
#define   WMAC0_HWSCH_R0_TESTBUS_1771___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1771__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1771__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1772               (0x00AABE94)
#define   WMAC0_HWSCH_R0_TESTBUS_1772___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1772__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1772__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1773               (0x00AABE98)
#define   WMAC0_HWSCH_R0_TESTBUS_1773___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1773__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1773__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1774               (0x00AABE9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1774___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1774__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1774__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1775               (0x00AABEA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1775___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1775__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1775__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1776               (0x00AABEA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1776___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1776__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1776__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1777               (0x00AABEA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1777___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1777__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1777__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1778               (0x00AABEAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1778___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1778__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1778__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1779               (0x00AABEB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1779___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1779__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1779__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1780               (0x00AABEB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1780___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1780__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1780__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1781               (0x00AABEB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1781___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1781__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1781__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1782               (0x00AABEBC)
#define   WMAC0_HWSCH_R0_TESTBUS_1782___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1782__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1782__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1783               (0x00AABEC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1783___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1783__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1783__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1784               (0x00AABEC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1784___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1784__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1784__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1785               (0x00AABEC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1785___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1785__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1785__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1786               (0x00AABECC)
#define   WMAC0_HWSCH_R0_TESTBUS_1786___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1786__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1786__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1787               (0x00AABED0)
#define   WMAC0_HWSCH_R0_TESTBUS_1787___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1787__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1787__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1788               (0x00AABED4)
#define   WMAC0_HWSCH_R0_TESTBUS_1788___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1788__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1788__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1789               (0x00AABED8)
#define   WMAC0_HWSCH_R0_TESTBUS_1789___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1789__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1789__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1790               (0x00AABEDC)
#define   WMAC0_HWSCH_R0_TESTBUS_1790___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1790__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1790__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1791               (0x00AABEE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1791___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1791__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1791__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1792               (0x00AABEE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1792___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1792__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1792__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1793               (0x00AABEE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1793___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1793__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1793__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1794               (0x00AABEEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1794___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1794__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1794__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1795               (0x00AABEF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1795___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1795__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1795__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1796               (0x00AABEF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1796___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1796__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1796__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1797               (0x00AABEF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1797___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1797__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1797__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1798               (0x00AABEFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1798___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1798__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1798__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1799               (0x00AABF00)
#define   WMAC0_HWSCH_R0_TESTBUS_1799___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1799__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1799__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1800               (0x00AABF04)
#define   WMAC0_HWSCH_R0_TESTBUS_1800___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1800__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1800__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1801               (0x00AABF08)
#define   WMAC0_HWSCH_R0_TESTBUS_1801___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1801__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1801__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1802               (0x00AABF0C)
#define   WMAC0_HWSCH_R0_TESTBUS_1802___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1802__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1802__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1803               (0x00AABF10)
#define   WMAC0_HWSCH_R0_TESTBUS_1803___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1803__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1803__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1804               (0x00AABF14)
#define   WMAC0_HWSCH_R0_TESTBUS_1804___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1804__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1804__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1805               (0x00AABF18)
#define   WMAC0_HWSCH_R0_TESTBUS_1805___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1805__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1805__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1806               (0x00AABF1C)
#define   WMAC0_HWSCH_R0_TESTBUS_1806___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1806__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1806__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1807               (0x00AABF20)
#define   WMAC0_HWSCH_R0_TESTBUS_1807___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1807__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1807__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1808               (0x00AABF24)
#define   WMAC0_HWSCH_R0_TESTBUS_1808___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1808__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1808__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1809               (0x00AABF28)
#define   WMAC0_HWSCH_R0_TESTBUS_1809___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1809__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1809__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1810               (0x00AABF2C)
#define   WMAC0_HWSCH_R0_TESTBUS_1810___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1810__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1810__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1811               (0x00AABF30)
#define   WMAC0_HWSCH_R0_TESTBUS_1811___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1811__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1811__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1812               (0x00AABF34)
#define   WMAC0_HWSCH_R0_TESTBUS_1812___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1812__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1812__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1813               (0x00AABF38)
#define   WMAC0_HWSCH_R0_TESTBUS_1813___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1813__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1813__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1814               (0x00AABF3C)
#define   WMAC0_HWSCH_R0_TESTBUS_1814___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1814__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1814__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1815               (0x00AABF40)
#define   WMAC0_HWSCH_R0_TESTBUS_1815___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1815__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1815__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1816               (0x00AABF44)
#define   WMAC0_HWSCH_R0_TESTBUS_1816___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1816__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1816__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1817               (0x00AABF48)
#define   WMAC0_HWSCH_R0_TESTBUS_1817___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1817__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1817__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1818               (0x00AABF4C)
#define   WMAC0_HWSCH_R0_TESTBUS_1818___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1818__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1818__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1819               (0x00AABF50)
#define   WMAC0_HWSCH_R0_TESTBUS_1819___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1819__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1819__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1820               (0x00AABF54)
#define   WMAC0_HWSCH_R0_TESTBUS_1820___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1820__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1820__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1821               (0x00AABF58)
#define   WMAC0_HWSCH_R0_TESTBUS_1821___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1821__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1821__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1822               (0x00AABF5C)
#define   WMAC0_HWSCH_R0_TESTBUS_1822___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1822__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1822__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1823               (0x00AABF60)
#define   WMAC0_HWSCH_R0_TESTBUS_1823___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1823__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1823__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1824               (0x00AABF64)
#define   WMAC0_HWSCH_R0_TESTBUS_1824___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1824__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1824__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1825               (0x00AABF68)
#define   WMAC0_HWSCH_R0_TESTBUS_1825___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1825__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1825__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1826               (0x00AABF6C)
#define   WMAC0_HWSCH_R0_TESTBUS_1826___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1826__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1826__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1827               (0x00AABF70)
#define   WMAC0_HWSCH_R0_TESTBUS_1827___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1827__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1827__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1828               (0x00AABF74)
#define   WMAC0_HWSCH_R0_TESTBUS_1828___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1828__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1828__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1829               (0x00AABF78)
#define   WMAC0_HWSCH_R0_TESTBUS_1829___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1829__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1829__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1830               (0x00AABF7C)
#define   WMAC0_HWSCH_R0_TESTBUS_1830___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1830__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1830__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1831               (0x00AABF80)
#define   WMAC0_HWSCH_R0_TESTBUS_1831___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1831__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1831__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1832               (0x00AABF84)
#define   WMAC0_HWSCH_R0_TESTBUS_1832___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1832__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1832__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1833               (0x00AABF88)
#define   WMAC0_HWSCH_R0_TESTBUS_1833___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1833__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1833__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1834               (0x00AABF8C)
#define   WMAC0_HWSCH_R0_TESTBUS_1834___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1834__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1834__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1835               (0x00AABF90)
#define   WMAC0_HWSCH_R0_TESTBUS_1835___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1835__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1835__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1836               (0x00AABF94)
#define   WMAC0_HWSCH_R0_TESTBUS_1836___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1836__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1836__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1837               (0x00AABF98)
#define   WMAC0_HWSCH_R0_TESTBUS_1837___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1837__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1837__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1838               (0x00AABF9C)
#define   WMAC0_HWSCH_R0_TESTBUS_1838___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1838__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1838__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1839               (0x00AABFA0)
#define   WMAC0_HWSCH_R0_TESTBUS_1839___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1839__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1839__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1840               (0x00AABFA4)
#define   WMAC0_HWSCH_R0_TESTBUS_1840___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1840__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1840__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1841               (0x00AABFA8)
#define   WMAC0_HWSCH_R0_TESTBUS_1841___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1841__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1841__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1842               (0x00AABFAC)
#define   WMAC0_HWSCH_R0_TESTBUS_1842___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1842__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1842__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1843               (0x00AABFB0)
#define   WMAC0_HWSCH_R0_TESTBUS_1843___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1843__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1843__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1844               (0x00AABFB4)
#define   WMAC0_HWSCH_R0_TESTBUS_1844___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1844__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1844__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1845               (0x00AABFB8)
#define   WMAC0_HWSCH_R0_TESTBUS_1845___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1845__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1845__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1846               (0x00AABFBC)
#define   WMAC0_HWSCH_R0_TESTBUS_1846___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1846__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1846__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1847               (0x00AABFC0)
#define   WMAC0_HWSCH_R0_TESTBUS_1847___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1847__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1847__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1848               (0x00AABFC4)
#define   WMAC0_HWSCH_R0_TESTBUS_1848___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1848__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1848__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1849               (0x00AABFC8)
#define   WMAC0_HWSCH_R0_TESTBUS_1849___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1849__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1849__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1850               (0x00AABFCC)
#define   WMAC0_HWSCH_R0_TESTBUS_1850___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1850__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1850__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1851               (0x00AABFD0)
#define   WMAC0_HWSCH_R0_TESTBUS_1851___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1851__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1851__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1852               (0x00AABFD4)
#define   WMAC0_HWSCH_R0_TESTBUS_1852___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1852__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1852__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1853               (0x00AABFD8)
#define   WMAC0_HWSCH_R0_TESTBUS_1853___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1853__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1853__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1854               (0x00AABFDC)
#define   WMAC0_HWSCH_R0_TESTBUS_1854___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1854__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1854__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1855               (0x00AABFE0)
#define   WMAC0_HWSCH_R0_TESTBUS_1855___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1855__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1855__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1856               (0x00AABFE4)
#define   WMAC0_HWSCH_R0_TESTBUS_1856___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1856__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1856__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1857               (0x00AABFE8)
#define   WMAC0_HWSCH_R0_TESTBUS_1857___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1857__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1857__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1858               (0x00AABFEC)
#define   WMAC0_HWSCH_R0_TESTBUS_1858___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1858__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1858__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1859               (0x00AABFF0)
#define   WMAC0_HWSCH_R0_TESTBUS_1859___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1859__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1859__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1860               (0x00AABFF4)
#define   WMAC0_HWSCH_R0_TESTBUS_1860___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1860__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1860__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1861               (0x00AABFF8)
#define   WMAC0_HWSCH_R0_TESTBUS_1861___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1861__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1861__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1862               (0x00AABFFC)
#define   WMAC0_HWSCH_R0_TESTBUS_1862___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1862__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1862__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1863               (0x00AAC000)
#define   WMAC0_HWSCH_R0_TESTBUS_1863___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1863__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1863__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1864               (0x00AAC004)
#define   WMAC0_HWSCH_R0_TESTBUS_1864___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1864__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1864__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1865               (0x00AAC008)
#define   WMAC0_HWSCH_R0_TESTBUS_1865___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1865__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1865__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1866               (0x00AAC00C)
#define   WMAC0_HWSCH_R0_TESTBUS_1866___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1866__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1866__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1867               (0x00AAC010)
#define   WMAC0_HWSCH_R0_TESTBUS_1867___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1867__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1867__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1868               (0x00AAC014)
#define   WMAC0_HWSCH_R0_TESTBUS_1868___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1868__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1868__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1869               (0x00AAC018)
#define   WMAC0_HWSCH_R0_TESTBUS_1869___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1869__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1869__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1870               (0x00AAC01C)
#define   WMAC0_HWSCH_R0_TESTBUS_1870___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1870__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1870__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1871               (0x00AAC020)
#define   WMAC0_HWSCH_R0_TESTBUS_1871___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1871__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1871__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1872               (0x00AAC024)
#define   WMAC0_HWSCH_R0_TESTBUS_1872___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1872__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1872__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1873               (0x00AAC028)
#define   WMAC0_HWSCH_R0_TESTBUS_1873___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1873__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1873__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1874               (0x00AAC02C)
#define   WMAC0_HWSCH_R0_TESTBUS_1874___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1874__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1874__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1875               (0x00AAC030)
#define   WMAC0_HWSCH_R0_TESTBUS_1875___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1875__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1875__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1876               (0x00AAC034)
#define   WMAC0_HWSCH_R0_TESTBUS_1876___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1876__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1876__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1877               (0x00AAC038)
#define   WMAC0_HWSCH_R0_TESTBUS_1877___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1877__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1877__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1878               (0x00AAC03C)
#define   WMAC0_HWSCH_R0_TESTBUS_1878___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1878__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1878__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1879               (0x00AAC040)
#define   WMAC0_HWSCH_R0_TESTBUS_1879___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1879__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1879__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1880               (0x00AAC044)
#define   WMAC0_HWSCH_R0_TESTBUS_1880___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1880__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1880__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1881               (0x00AAC048)
#define   WMAC0_HWSCH_R0_TESTBUS_1881___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1881__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1881__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1882               (0x00AAC04C)
#define   WMAC0_HWSCH_R0_TESTBUS_1882___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1882__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1882__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1883               (0x00AAC050)
#define   WMAC0_HWSCH_R0_TESTBUS_1883___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1883__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1883__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1884               (0x00AAC054)
#define   WMAC0_HWSCH_R0_TESTBUS_1884___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1884__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1884__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1885               (0x00AAC058)
#define   WMAC0_HWSCH_R0_TESTBUS_1885___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1885__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1885__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1886               (0x00AAC05C)
#define   WMAC0_HWSCH_R0_TESTBUS_1886___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1886__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1886__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1887               (0x00AAC060)
#define   WMAC0_HWSCH_R0_TESTBUS_1887___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1887__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1887__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1888               (0x00AAC064)
#define   WMAC0_HWSCH_R0_TESTBUS_1888___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1888__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1888__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1889               (0x00AAC068)
#define   WMAC0_HWSCH_R0_TESTBUS_1889___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1889__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1889__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1890               (0x00AAC06C)
#define   WMAC0_HWSCH_R0_TESTBUS_1890___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1890__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1890__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1891               (0x00AAC070)
#define   WMAC0_HWSCH_R0_TESTBUS_1891___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1891__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1891__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1892               (0x00AAC074)
#define   WMAC0_HWSCH_R0_TESTBUS_1892___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1892__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1892__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1893               (0x00AAC078)
#define   WMAC0_HWSCH_R0_TESTBUS_1893___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1893__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1893__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1894               (0x00AAC07C)
#define   WMAC0_HWSCH_R0_TESTBUS_1894___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1894__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1894__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1895               (0x00AAC080)
#define   WMAC0_HWSCH_R0_TESTBUS_1895___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1895__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1895__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1896               (0x00AAC084)
#define   WMAC0_HWSCH_R0_TESTBUS_1896___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1896__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1896__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1897               (0x00AAC088)
#define   WMAC0_HWSCH_R0_TESTBUS_1897___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1897__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1897__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1898               (0x00AAC08C)
#define   WMAC0_HWSCH_R0_TESTBUS_1898___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1898__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1898__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1899               (0x00AAC090)
#define   WMAC0_HWSCH_R0_TESTBUS_1899___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1899__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1899__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1900               (0x00AAC094)
#define   WMAC0_HWSCH_R0_TESTBUS_1900___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1900__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1900__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1901               (0x00AAC098)
#define   WMAC0_HWSCH_R0_TESTBUS_1901___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1901__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1901__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1902               (0x00AAC09C)
#define   WMAC0_HWSCH_R0_TESTBUS_1902___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1902__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1902__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1903               (0x00AAC0A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1903___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1903__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1903__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1904               (0x00AAC0A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1904___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1904__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1904__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1905               (0x00AAC0A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1905___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1905__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1905__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1906               (0x00AAC0AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1906___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1906__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1906__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1907               (0x00AAC0B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1907___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1907__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1907__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1908               (0x00AAC0B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1908___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1908__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1908__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1909               (0x00AAC0B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1909___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1909__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1909__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1910               (0x00AAC0BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1910___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1910__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1910__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1911               (0x00AAC0C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1911___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1911__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1911__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1912               (0x00AAC0C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1912___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1912__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1912__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1913               (0x00AAC0C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1913___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1913__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1913__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1914               (0x00AAC0CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1914___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1914__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1914__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1915               (0x00AAC0D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1915___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1915__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1915__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1916               (0x00AAC0D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1916___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1916__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1916__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1917               (0x00AAC0D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1917___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1917__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1917__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1918               (0x00AAC0DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1918___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1918__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1918__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1919               (0x00AAC0E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1919___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1919__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1919__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1920               (0x00AAC0E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1920___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1920__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1920__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1921               (0x00AAC0E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1921___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1921__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1921__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1922               (0x00AAC0EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1922___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1922__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1922__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1923               (0x00AAC0F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1923___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1923__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1923__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1924               (0x00AAC0F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1924___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1924__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1924__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1925               (0x00AAC0F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1925___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1925__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1925__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1926               (0x00AAC0FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1926___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1926__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1926__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1927               (0x00AAC100)
#define   WMAC0_HWSCH_R0_TESTBUS_1927___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1927__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1927__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1928               (0x00AAC104)
#define   WMAC0_HWSCH_R0_TESTBUS_1928___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1928__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1928__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1929               (0x00AAC108)
#define   WMAC0_HWSCH_R0_TESTBUS_1929___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1929__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1929__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1930               (0x00AAC10C)
#define   WMAC0_HWSCH_R0_TESTBUS_1930___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1930__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1930__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1931               (0x00AAC110)
#define   WMAC0_HWSCH_R0_TESTBUS_1931___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1931__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1931__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1932               (0x00AAC114)
#define   WMAC0_HWSCH_R0_TESTBUS_1932___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1932__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1932__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1933               (0x00AAC118)
#define   WMAC0_HWSCH_R0_TESTBUS_1933___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1933__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1933__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1934               (0x00AAC11C)
#define   WMAC0_HWSCH_R0_TESTBUS_1934___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1934__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1934__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1935               (0x00AAC120)
#define   WMAC0_HWSCH_R0_TESTBUS_1935___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1935__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1935__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1936               (0x00AAC124)
#define   WMAC0_HWSCH_R0_TESTBUS_1936___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1936__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1936__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1937               (0x00AAC128)
#define   WMAC0_HWSCH_R0_TESTBUS_1937___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1937__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1937__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1938               (0x00AAC12C)
#define   WMAC0_HWSCH_R0_TESTBUS_1938___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1938__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1938__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1939               (0x00AAC130)
#define   WMAC0_HWSCH_R0_TESTBUS_1939___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1939__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1939__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1940               (0x00AAC134)
#define   WMAC0_HWSCH_R0_TESTBUS_1940___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1940__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1940__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1941               (0x00AAC138)
#define   WMAC0_HWSCH_R0_TESTBUS_1941___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1941__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1941__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1942               (0x00AAC13C)
#define   WMAC0_HWSCH_R0_TESTBUS_1942___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1942__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1942__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1943               (0x00AAC140)
#define   WMAC0_HWSCH_R0_TESTBUS_1943___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1943__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1943__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1944               (0x00AAC144)
#define   WMAC0_HWSCH_R0_TESTBUS_1944___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1944__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1944__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1945               (0x00AAC148)
#define   WMAC0_HWSCH_R0_TESTBUS_1945___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1945__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1945__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1946               (0x00AAC14C)
#define   WMAC0_HWSCH_R0_TESTBUS_1946___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1946__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1946__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1947               (0x00AAC150)
#define   WMAC0_HWSCH_R0_TESTBUS_1947___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1947__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1947__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1948               (0x00AAC154)
#define   WMAC0_HWSCH_R0_TESTBUS_1948___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1948__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1948__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1949               (0x00AAC158)
#define   WMAC0_HWSCH_R0_TESTBUS_1949___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1949__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1949__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1950               (0x00AAC15C)
#define   WMAC0_HWSCH_R0_TESTBUS_1950___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1950__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1950__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1951               (0x00AAC160)
#define   WMAC0_HWSCH_R0_TESTBUS_1951___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1951__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1951__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1952               (0x00AAC164)
#define   WMAC0_HWSCH_R0_TESTBUS_1952___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1952__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1952__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1953               (0x00AAC168)
#define   WMAC0_HWSCH_R0_TESTBUS_1953___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1953__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1953__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1954               (0x00AAC16C)
#define   WMAC0_HWSCH_R0_TESTBUS_1954___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1954__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1954__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1955               (0x00AAC170)
#define   WMAC0_HWSCH_R0_TESTBUS_1955___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1955__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1955__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1956               (0x00AAC174)
#define   WMAC0_HWSCH_R0_TESTBUS_1956___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1956__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1956__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1957               (0x00AAC178)
#define   WMAC0_HWSCH_R0_TESTBUS_1957___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1957__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1957__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1958               (0x00AAC17C)
#define   WMAC0_HWSCH_R0_TESTBUS_1958___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1958__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1958__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1959               (0x00AAC180)
#define   WMAC0_HWSCH_R0_TESTBUS_1959___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1959__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1959__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1960               (0x00AAC184)
#define   WMAC0_HWSCH_R0_TESTBUS_1960___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1960__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1960__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1961               (0x00AAC188)
#define   WMAC0_HWSCH_R0_TESTBUS_1961___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1961__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1961__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1962               (0x00AAC18C)
#define   WMAC0_HWSCH_R0_TESTBUS_1962___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1962__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1962__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1963               (0x00AAC190)
#define   WMAC0_HWSCH_R0_TESTBUS_1963___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1963__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1963__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1964               (0x00AAC194)
#define   WMAC0_HWSCH_R0_TESTBUS_1964___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1964__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1964__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1965               (0x00AAC198)
#define   WMAC0_HWSCH_R0_TESTBUS_1965___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1965__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1965__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1966               (0x00AAC19C)
#define   WMAC0_HWSCH_R0_TESTBUS_1966___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1966__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1966__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1967               (0x00AAC1A0)
#define   WMAC0_HWSCH_R0_TESTBUS_1967___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1967__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1967__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1968               (0x00AAC1A4)
#define   WMAC0_HWSCH_R0_TESTBUS_1968___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1968__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1968__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1969               (0x00AAC1A8)
#define   WMAC0_HWSCH_R0_TESTBUS_1969___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1969__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1969__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1970               (0x00AAC1AC)
#define   WMAC0_HWSCH_R0_TESTBUS_1970___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1970__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1970__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1971               (0x00AAC1B0)
#define   WMAC0_HWSCH_R0_TESTBUS_1971___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1971__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1971__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1972               (0x00AAC1B4)
#define   WMAC0_HWSCH_R0_TESTBUS_1972___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1972__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1972__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1973               (0x00AAC1B8)
#define   WMAC0_HWSCH_R0_TESTBUS_1973___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1973__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1973__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1974               (0x00AAC1BC)
#define   WMAC0_HWSCH_R0_TESTBUS_1974___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1974__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1974__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1975               (0x00AAC1C0)
#define   WMAC0_HWSCH_R0_TESTBUS_1975___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1975__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1975__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1976               (0x00AAC1C4)
#define   WMAC0_HWSCH_R0_TESTBUS_1976___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1976__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1976__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1977               (0x00AAC1C8)
#define   WMAC0_HWSCH_R0_TESTBUS_1977___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1977__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1977__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1978               (0x00AAC1CC)
#define   WMAC0_HWSCH_R0_TESTBUS_1978___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1978__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1978__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1979               (0x00AAC1D0)
#define   WMAC0_HWSCH_R0_TESTBUS_1979___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1979__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1979__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1980               (0x00AAC1D4)
#define   WMAC0_HWSCH_R0_TESTBUS_1980___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1980__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1980__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1981               (0x00AAC1D8)
#define   WMAC0_HWSCH_R0_TESTBUS_1981___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1981__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1981__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1982               (0x00AAC1DC)
#define   WMAC0_HWSCH_R0_TESTBUS_1982___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1982__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1982__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1983               (0x00AAC1E0)
#define   WMAC0_HWSCH_R0_TESTBUS_1983___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1983__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1983__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1984               (0x00AAC1E4)
#define   WMAC0_HWSCH_R0_TESTBUS_1984___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1984__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1984__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1985               (0x00AAC1E8)
#define   WMAC0_HWSCH_R0_TESTBUS_1985___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1985__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1985__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1986               (0x00AAC1EC)
#define   WMAC0_HWSCH_R0_TESTBUS_1986___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1986__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1986__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1987               (0x00AAC1F0)
#define   WMAC0_HWSCH_R0_TESTBUS_1987___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1987__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1987__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1988               (0x00AAC1F4)
#define   WMAC0_HWSCH_R0_TESTBUS_1988___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1988__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1988__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1989               (0x00AAC1F8)
#define   WMAC0_HWSCH_R0_TESTBUS_1989___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1989__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1989__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1990               (0x00AAC1FC)
#define   WMAC0_HWSCH_R0_TESTBUS_1990___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1990__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1990__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1991               (0x00AAC200)
#define   WMAC0_HWSCH_R0_TESTBUS_1991___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1991__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1991__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1992               (0x00AAC204)
#define   WMAC0_HWSCH_R0_TESTBUS_1992___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1992__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1992__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1993               (0x00AAC208)
#define   WMAC0_HWSCH_R0_TESTBUS_1993___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1993__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1993__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1994               (0x00AAC20C)
#define   WMAC0_HWSCH_R0_TESTBUS_1994___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1994__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1994__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1995               (0x00AAC210)
#define   WMAC0_HWSCH_R0_TESTBUS_1995___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1995__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1995__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1996               (0x00AAC214)
#define   WMAC0_HWSCH_R0_TESTBUS_1996___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1996__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1996__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1997               (0x00AAC218)
#define   WMAC0_HWSCH_R0_TESTBUS_1997___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1997__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1997__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1998               (0x00AAC21C)
#define   WMAC0_HWSCH_R0_TESTBUS_1998___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1998__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1998__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_1999               (0x00AAC220)
#define   WMAC0_HWSCH_R0_TESTBUS_1999___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_1999__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_1999__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2000               (0x00AAC224)
#define   WMAC0_HWSCH_R0_TESTBUS_2000___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2000__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2000__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2001               (0x00AAC228)
#define   WMAC0_HWSCH_R0_TESTBUS_2001___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2001__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2001__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2002               (0x00AAC22C)
#define   WMAC0_HWSCH_R0_TESTBUS_2002___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2002__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2002__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2003               (0x00AAC230)
#define   WMAC0_HWSCH_R0_TESTBUS_2003___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2003__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2003__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2004               (0x00AAC234)
#define   WMAC0_HWSCH_R0_TESTBUS_2004___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2004__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2004__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2005               (0x00AAC238)
#define   WMAC0_HWSCH_R0_TESTBUS_2005___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2005__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2005__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2006               (0x00AAC23C)
#define   WMAC0_HWSCH_R0_TESTBUS_2006___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2006__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2006__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2007               (0x00AAC240)
#define   WMAC0_HWSCH_R0_TESTBUS_2007___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2007__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2007__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2008               (0x00AAC244)
#define   WMAC0_HWSCH_R0_TESTBUS_2008___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2008__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2008__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2009               (0x00AAC248)
#define   WMAC0_HWSCH_R0_TESTBUS_2009___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2009__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2009__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2010               (0x00AAC24C)
#define   WMAC0_HWSCH_R0_TESTBUS_2010___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2010__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2010__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2011               (0x00AAC250)
#define   WMAC0_HWSCH_R0_TESTBUS_2011___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2011__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2011__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2012               (0x00AAC254)
#define   WMAC0_HWSCH_R0_TESTBUS_2012___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2012__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2012__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2013               (0x00AAC258)
#define   WMAC0_HWSCH_R0_TESTBUS_2013___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2013__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2013__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2014               (0x00AAC25C)
#define   WMAC0_HWSCH_R0_TESTBUS_2014___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2014__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2014__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2015               (0x00AAC260)
#define   WMAC0_HWSCH_R0_TESTBUS_2015___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2015__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2015__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2016               (0x00AAC264)
#define   WMAC0_HWSCH_R0_TESTBUS_2016___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2016__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2016__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2017               (0x00AAC268)
#define   WMAC0_HWSCH_R0_TESTBUS_2017___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2017__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2017__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2018               (0x00AAC26C)
#define   WMAC0_HWSCH_R0_TESTBUS_2018___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2018__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2018__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2019               (0x00AAC270)
#define   WMAC0_HWSCH_R0_TESTBUS_2019___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2019__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2019__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2020               (0x00AAC274)
#define   WMAC0_HWSCH_R0_TESTBUS_2020___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2020__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2020__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2021               (0x00AAC278)
#define   WMAC0_HWSCH_R0_TESTBUS_2021___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2021__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2021__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2022               (0x00AAC27C)
#define   WMAC0_HWSCH_R0_TESTBUS_2022___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2022__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2022__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2023               (0x00AAC280)
#define   WMAC0_HWSCH_R0_TESTBUS_2023___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2023__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2023__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2024               (0x00AAC284)
#define   WMAC0_HWSCH_R0_TESTBUS_2024___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2024__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2024__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2025               (0x00AAC288)
#define   WMAC0_HWSCH_R0_TESTBUS_2025___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2025__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2025__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2026               (0x00AAC28C)
#define   WMAC0_HWSCH_R0_TESTBUS_2026___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2026__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2026__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2027               (0x00AAC290)
#define   WMAC0_HWSCH_R0_TESTBUS_2027___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2027__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2027__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2028               (0x00AAC294)
#define   WMAC0_HWSCH_R0_TESTBUS_2028___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2028__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2028__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2029               (0x00AAC298)
#define   WMAC0_HWSCH_R0_TESTBUS_2029___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2029__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2029__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2030               (0x00AAC29C)
#define   WMAC0_HWSCH_R0_TESTBUS_2030___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2030__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2030__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2031               (0x00AAC2A0)
#define   WMAC0_HWSCH_R0_TESTBUS_2031___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2031__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2031__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2032               (0x00AAC2A4)
#define   WMAC0_HWSCH_R0_TESTBUS_2032___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2032__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2032__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2033               (0x00AAC2A8)
#define   WMAC0_HWSCH_R0_TESTBUS_2033___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2033__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2033__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2034               (0x00AAC2AC)
#define   WMAC0_HWSCH_R0_TESTBUS_2034___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2034__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2034__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2035               (0x00AAC2B0)
#define   WMAC0_HWSCH_R0_TESTBUS_2035___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2035__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2035__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2036               (0x00AAC2B4)
#define   WMAC0_HWSCH_R0_TESTBUS_2036___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2036__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2036__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2037               (0x00AAC2B8)
#define   WMAC0_HWSCH_R0_TESTBUS_2037___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2037__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2037__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2038               (0x00AAC2BC)
#define   WMAC0_HWSCH_R0_TESTBUS_2038___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2038__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2038__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2039               (0x00AAC2C0)
#define   WMAC0_HWSCH_R0_TESTBUS_2039___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2039__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2039__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2040               (0x00AAC2C4)
#define   WMAC0_HWSCH_R0_TESTBUS_2040___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2040__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2040__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2041               (0x00AAC2C8)
#define   WMAC0_HWSCH_R0_TESTBUS_2041___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2041__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2041__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2042               (0x00AAC2CC)
#define   WMAC0_HWSCH_R0_TESTBUS_2042___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2042__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2042__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2043               (0x00AAC2D0)
#define   WMAC0_HWSCH_R0_TESTBUS_2043___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2043__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2043__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2044               (0x00AAC2D4)
#define   WMAC0_HWSCH_R0_TESTBUS_2044___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2044__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2044__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2045               (0x00AAC2D8)
#define   WMAC0_HWSCH_R0_TESTBUS_2045___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2045__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2045__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2046               (0x00AAC2DC)
#define   WMAC0_HWSCH_R0_TESTBUS_2046___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2046__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2046__DATA___S                0
#define WMAC0_HWSCH_R0_TESTBUS_2047               (0x00AAC2E0)
#define   WMAC0_HWSCH_R0_TESTBUS_2047___RWC         QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TESTBUS_2047__DATA___M  0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TESTBUS_2047__DATA___S                0

#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL           (0x00AAC2E4)
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___POR  0x0003FFFF
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___POR 0x3FFFF
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___M 0x80000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___S              31
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___M 0x40000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___S              30
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___M 0x20000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___S              29
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___M 0x10000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___S              28
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___M 0x08000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___S              27
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___M 0x04000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___S              26
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___M 0x02000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___S              25
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___M 0x01000000
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___S              24
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___S               0
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___M    0xFF03FFFF   
#define   WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___S                  0

#define WMAC0_HWSCH_R0_AXI_ERR_STATUS             (0x00AAC2E8)
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS___POR    0x00000000
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___POR 0x0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___M 0x00000080
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___S               7
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___M 0x00000040
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___S               6
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___M 0x00000020
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___S               5
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___M 0x00000010
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___S               4
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___M 0x00000008
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___S               3
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___M 0x00000004
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___S               2
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___M 0x00000002
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___S               1
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___M 0x00000001
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___S               0
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS___M      0x000000FF   
#define   WMAC0_HWSCH_R0_AXI_ERR_STATUS___S                    0

#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS        (0x00AAC2EC)
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___M 0x00000008
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___S               3
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___M 0x00000004
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___S               2
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___M 0x00000002
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___S               1
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___M 0x00000001
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___S               0
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___M 0x0000000F   
#define   WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___S               0

#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0       (0x00AAC2F0)
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___M 0x00020000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___S              17
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___M 0x00010000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___S              16
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___M 0x00008000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___S              15
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___M 0x00004000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___S              14
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___M 0x00002000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___S              13
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___M 0x00001000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___S              12
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___M 0x00000800
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___S              11
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___M 0x00000400
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___S              10
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___M 0x00000200
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___S               9
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___M 0x00000100
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___S               8
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___M 0x00000080
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___S               7
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___M 0x00000040
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___S               6
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___M 0x00000020
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___S               5
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___M 0x00000010
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___S               4
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___M 0x00000008
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___S               3
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___M 0x00000004
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___S               2
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___M 0x00000002
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___S               1
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___M 0x00000001
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___S               0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___S               0

#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1       (0x00AAC2F4)
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___M 0x00008000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___S              15
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___M 0x00004000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___S              14
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___M 0x00002000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___S              13
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___M 0x00001000
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___S              12
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___M 0x00000800
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___S              11
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___M 0x00000400
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___S              10
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___M 0x00000200
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___S               9
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___M 0x00000100
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___S               8
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___M 0x00000080
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___S               7
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___M 0x00000040
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___S               6
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___M 0x00000020
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___S               5
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___M 0x00000010
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___S               4
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___M 0x00000008
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___S               3
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___M 0x00000004
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___S               2
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___M 0x00000002
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___S               1
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___M 0x00000001
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___S               0
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___S               0

#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL           (0x00AAC2F8)
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL___POR  0x00000000
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___POR 0x00000000
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___S               0
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL___S                  0

#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2          (0x00AAC2FC)
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___POR 0x00000000
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___POR 0x00000000
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___S               0
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___S                 0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0 (0x00AAC300)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1 (0x00AAC304)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2 (0x00AAC308)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3 (0x00AAC30C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4 (0x00AAC310)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5 (0x00AAC314)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6 (0x00AAC318)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7 (0x00AAC31C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8 (0x00AAC320)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9 (0x00AAC324)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10 (0x00AAC328)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11 (0x00AAC32C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12 (0x00AAC330)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13 (0x00AAC334)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14 (0x00AAC338)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15 (0x00AAC33C)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16 (0x00AAC340)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___S               0

#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17 (0x00AAC344)
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___POR 0x00000000
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___M 0x000000FF   
#define   WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB   (0x00AAC350)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___M 0x000000FF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___M 0x000000FF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___S               0

#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n(n) (0x00AAC354+0x4*(n))
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n_nMIN 0    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n_nMAX 31   
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n_ELEM 32   
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n___POR  0x00000000
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___S               0
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_n___S                  0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_0           (0x00AAC354)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_0___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_0__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_0__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_1           (0x00AAC358)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_1___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_1__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_1__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_2           (0x00AAC35C)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_2___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_2__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_2__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_3           (0x00AAC360)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_3___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_3__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_3__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_4           (0x00AAC364)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_4___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_4__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_4__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_5           (0x00AAC368)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_5___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_5__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_5__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_6           (0x00AAC36C)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_6___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_6__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_6__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_7           (0x00AAC370)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_7___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_7__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_7__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_8           (0x00AAC374)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_8___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_8__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_8__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_9           (0x00AAC378)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_9___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_9__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_9__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_10          (0x00AAC37C)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_10___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_10__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_10__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_11          (0x00AAC380)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_11___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_11__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_11__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_12          (0x00AAC384)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_12___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_12__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_12__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_13          (0x00AAC388)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_13___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_13__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_13__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_14          (0x00AAC38C)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_14___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_14__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_14__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_15          (0x00AAC390)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_15___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_15__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_15__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_16          (0x00AAC394)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_16___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_16__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_16__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_17          (0x00AAC398)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_17___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_17__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_17__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_18          (0x00AAC39C)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_18___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_18__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_18__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_19          (0x00AAC3A0)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_19___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_19__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_19__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_20          (0x00AAC3A4)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_20___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_20__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_20__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_21          (0x00AAC3A8)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_21___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_21__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_21__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_22          (0x00AAC3AC)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_22___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_22__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_22__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_23          (0x00AAC3B0)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_23___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_23__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_23__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_24          (0x00AAC3B4)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_24___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_24__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_24__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_25          (0x00AAC3B8)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_25___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_25__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_25__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_26          (0x00AAC3BC)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_26___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_26__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_26__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_27          (0x00AAC3C0)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_27___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_27__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_27__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_28          (0x00AAC3C4)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_28___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_28__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_28__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_29          (0x00AAC3C8)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_29___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_29__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_29__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_30          (0x00AAC3CC)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_30___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_30__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_30__DATA___S               0
#define WMAC0_HWSCH_R0_GENERIC_TIMERS_31          (0x00AAC3D0)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_31___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_31__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_31__DATA___S               0

#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE        (0x00AAC3D4)
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___POR 0x00100000
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___POR 0x00100
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___POR 0x0
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___POR 0x00
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___M 0xFFFFF000
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___S              12
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___M 0x00000700
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___S               8
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___M 0x000000FF
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___S               0
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___M 0xFFFFF7FF   
#define   WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___S               0

#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n(n) (0x00AAC3D8+0x4*(n))
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_nMIN 0    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_nMAX 3    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_ELEM 4    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___S               0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___S               0
#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0   (0x00AAC3D8)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0__VALUE___S               0
#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1   (0x00AAC3DC)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1__VALUE___S               0
#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2   (0x00AAC3E0)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2__VALUE___S               0
#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3   (0x00AAC3E4)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3__VALUE___S               0

#define WMAC0_HWSCH_R0_TSF_UPDATE                 (0x00AAC3E8)
#define   WMAC0_HWSCH_R0_TSF_UPDATE___RWC           QCSR_REG_WO    
#define   WMAC0_HWSCH_R0_TSF_UPDATE___POR        0x00000000
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___POR 0x0
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___M 0x00000004
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___S               2
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___M 0x00000002
#define   WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___S               1
#define   WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___M 0x00000001
#define   WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___S               0
#define   WMAC0_HWSCH_R0_TSF_UPDATE___M          0x00000007   
#define   WMAC0_HWSCH_R0_TSF_UPDATE___S                        0

#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL (0x00AAC3EC)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___POR 0x00000000
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___POR 0x00
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___M 0x000000FF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___S               0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___M 0x000000FF   
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___S               0

#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL (0x00AAC3F0)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___POR 0x000001A9
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___POR 0x1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___POR 0x1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___POR 0x1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___POR 0x1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___POR 0x0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___POR 0x0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___POR 0x1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___M 0x00000100
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___S               8
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___M 0x00000080
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___S               7
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___M 0x00000060
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___S               5
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___M 0x00000018
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___S               3
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___M 0x00000004
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___S               2
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___M 0x00000002
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___S               1
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___M 0x00000001
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___S               0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___M 0x000001FF   
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___S               0

#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT      (0x00AAC3F4)
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___POR 0x0000009F
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___POR 0x0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___POR 0x0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___POR 0x09F
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___M 0x0003C000
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___S              14
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___M 0x00003C00
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___S              10
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___M 0x000003FF
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___S               0
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___S               0

#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n(n) (0x00AAC3F8+0x4*(n))
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_nMIN 0    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_nMAX 9    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_ELEM 10   
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___S               0
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0        (0x00AAC3F8)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1        (0x00AAC3FC)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2        (0x00AAC400)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3        (0x00AAC404)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4        (0x00AAC408)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5        (0x00AAC40C)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6        (0x00AAC410)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7        (0x00AAC414)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8        (0x00AAC418)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8__VALUE___S               0
#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9        (0x00AAC41C)
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9__VALUE___S               0

#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS             (0x00AAC420)
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___POR    0x005C005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___S              16
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___S               0
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___S                    0

#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS            (0x00AAC424)
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___POR   0x005C005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___S              16
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___S               0
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___S                   0

#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS            (0x00AAC428)
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___POR   0x005C005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___S              16
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___S               0
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___S                   0

#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED          (0x00AAC42C)
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___POR 0x0000005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___POR 0x005C
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___S               0
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___M   0x0000FFFF   
#define   WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___S                 0

#define WMAC0_HWSCH_R0_INVALID_APB_ACC            (0x00AAC430)
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC___RWC      QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC___POR   0x00000000
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___POR 0x00000
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___M 0x0001FFFF
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___S               0
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC___M     0x0001FFFF   
#define   WMAC0_HWSCH_R0_INVALID_APB_ACC___S                   0

#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT (0x00AAC434)
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___POR 0x00000000
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___POR 0x00000000
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___S               0
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___S               0

#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0           (0x00AAC438)
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___POR  0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___S               0
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___S                  0

#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1           (0x00AAC43C)
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___POR  0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___S               0
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___S                  0

#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2           (0x00AAC440)
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___POR  0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___S               0
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___S                  0

#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3           (0x00AAC444)
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___POR  0x00000000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___POR 0x000
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___M 0x00000FFF
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___S               0
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___M    0x00000FFF   
#define   WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___S                  0

#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME (0x00AAC448)
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___POR 0x00000000
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___POR 0x0000
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___POR 0x0000
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___S              16
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___S               0
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___S               0

#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL          (0x00AAC44C)
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___POR 0xFFFFFFFC
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___POR 0x3FFFFFFF
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___M 0xFFFFFFFC
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___S               2
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___M 0x00000003
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___S               0
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___S                 0

#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL    (0x00AAC450)
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___POR 0xFFFFFFFC
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___POR 0x3FFFFFFF
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___POR 0x0
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___M 0xFFFFFFFC
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___S               2
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___M 0x00000003
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___S               0
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___S               0

#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT (0x00AAC454)
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___POR 0x00000000
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___S               0
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___S               0

#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC         (0x00AAC458)
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___POR 0x00000000
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___M 0x00000003
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___S               0
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___M  0x00000003   
#define   WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___S                0

#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS (0x00AAC45C)
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___POR 0x00010040
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___POR 0x0001
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___POR 0x0040
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___S              16
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___S               0
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT     (0x00AAC460)
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___POR 0x00001F40
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___POR 0x1F40
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB   (0x00AAC464)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB   (0x00AAC468)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___S               8
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___M 0x00FFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID         (0x00AAC46C)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___M 0x0000FF00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___S               8
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___M  0x0000FFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___S                0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS     (0x00AAC470)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S              16
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC       (0x00AAC474)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___POR 0x00000080
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___S              22
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___S              14
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___S              12
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___S               8
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___S               7
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___S               6
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S               5
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S               4
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___S               3
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___S               2
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___S               1
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___M 0x03FFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB (0x00AAC478)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB (0x00AAC47C)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___M 0x000000FF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP (0x00AAC488)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S              16
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S              15
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS (0x00AAC48C)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S              16
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S              15
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER (0x00AAC490)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB (0x00AAC4AC)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB (0x00AAC4B0)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S               8
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA  (0x00AAC4B4)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET (0x00AAC4B8)
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___S               0

#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n(n) (0x00AAC4BC+0x4*(n))
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_nMIN 0    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_nMAX 15   
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_ELEM 16   
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___POR 0x0
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___POR 0x0
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___POR 0x00
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___POR 0x0
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___POR 0x0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___S               0
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___M  0x01BFFFFF   
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___S                0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0         (0x00AAC4BC)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1         (0x00AAC4C0)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2         (0x00AAC4C4)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3         (0x00AAC4C8)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4         (0x00AAC4CC)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5         (0x00AAC4D0)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6         (0x00AAC4D4)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7         (0x00AAC4D8)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8         (0x00AAC4DC)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9         (0x00AAC4E0)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9___RWC   QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10        (0x00AAC4E4)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11        (0x00AAC4E8)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12        (0x00AAC4EC)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13        (0x00AAC4F0)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14        (0x00AAC4F4)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PEER_ID___S               0
#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15        (0x00AAC4F8)
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15___RWC  QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__LOCK___M 0x01000000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__LOCK___S              24
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__VALID___M 0x00800000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__VALID___S              23
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__WEIGHT___M 0x003E0000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__WEIGHT___S              17
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PEER_ID___S               0

#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO           (0x00AAC504)
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___RWC     QCSR_REG_WO    
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___POR  0x00000000
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___POR 0x0
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___POR 0x0
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___POR 0x0000
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___M 0x00020000
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___S              17
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___M 0x00010000
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___S              16
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___S               0
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___M    0x0003FFFF   
#define   WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___S                  0

#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n(n) (0x00AAC508+0x4*(n))
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_nMIN 0    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_nMAX 35   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_ELEM 36   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___S                 0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0          (0x00AAC508)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1          (0x00AAC50C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2          (0x00AAC510)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3          (0x00AAC514)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4          (0x00AAC518)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5          (0x00AAC51C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6          (0x00AAC520)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7          (0x00AAC524)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8          (0x00AAC528)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9          (0x00AAC52C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10         (0x00AAC530)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11         (0x00AAC534)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12         (0x00AAC538)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13         (0x00AAC53C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14         (0x00AAC540)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15         (0x00AAC544)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16         (0x00AAC548)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17         (0x00AAC54C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18         (0x00AAC550)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19         (0x00AAC554)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20         (0x00AAC558)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21         (0x00AAC55C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22         (0x00AAC560)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23         (0x00AAC564)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24         (0x00AAC568)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25         (0x00AAC56C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26         (0x00AAC570)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27         (0x00AAC574)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28         (0x00AAC578)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29         (0x00AAC57C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30         (0x00AAC580)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31         (0x00AAC584)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32         (0x00AAC588)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33         (0x00AAC58C)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34         (0x00AAC590)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35         (0x00AAC594)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35__LUT_VALUE___S               0

#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n(n) (0x00AAC5A8+0x4*(n))
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_nMIN 0    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_nMAX 7    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_ELEM 8    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___POR 0x00111100
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___POR 0x00111100
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___S                 0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0          (0x00AAC5A8)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1          (0x00AAC5AC)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2          (0x00AAC5B0)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3          (0x00AAC5B4)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4          (0x00AAC5B8)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5          (0x00AAC5BC)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6          (0x00AAC5C0)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7          (0x00AAC5C4)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7__LUT_VALUE___S               0

#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX             (0x00AAC5C8)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX___POR    0x00000200
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___POR 0x1
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___POR 0x000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___M 0x00000600
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___S               9
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___M 0x000001FF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX___M      0x000007FF   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_COEX___S                    0

#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS             (0x00AAC5CC)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___POR    0x00000000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___M 0x00000007
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___M      0x00000007   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___S                    0

#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n(n) (0x00AAC5D0+0x4*(n))
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_nMIN 0    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_nMAX 1    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_ELEM 2    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___S                 0
#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0          (0x00AAC5D0)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0__LUT_VALUE___S               0
#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1          (0x00AAC5D4)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1__LUT_VALUE___S               0

#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD (0x00AAC5D8)
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___POR 0x00000000
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___S               0
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___S               0

#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR         (0x00AAC5DC)
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___POR 0x000001C0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___POR 0x1C0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___M 0x000003FF
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___M  0x000003FF   
#define   WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___S                0

#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n(n) (0x00AAC5E0+0x4*(n))
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMIN 0    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMAX 9    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_ELEM 10   
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___POR  0x00000000
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___S               0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___S                  0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_0           (0x00AAC5E0)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_0___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_0__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_0__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_1           (0x00AAC5E4)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_1___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_1__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_1__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_2           (0x00AAC5E8)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_2___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_2__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_2__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_3           (0x00AAC5EC)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_3___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_3__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_3__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_4           (0x00AAC5F0)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_4___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_4__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_4__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_5           (0x00AAC5F4)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_5___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_5__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_5__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_6           (0x00AAC5F8)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_6___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_6__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_6__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_7           (0x00AAC5FC)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_7___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_7__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_7__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_8           (0x00AAC600)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_8___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_8__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_8__CNT_VALUE___S               0
#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9           (0x00AAC604)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_9___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___S               0

#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK              (0x00AAC608)
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK___POR     0x00000000
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___M 0x00000001
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___S               0
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK___M       0x00000001   
#define   WMAC0_HWSCH_R0_TQM_FLUSH_ACK___S                     0

#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR       (0x00AAC60C)
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___POR 0x00000000
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___S               0
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB (0x00AAC610)
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___M 0x000000FF   
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB (0x00AAC614)
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___S               0

#define WMAC0_HWSCH_R0_SFM_BLK_CTRL               (0x00AAC618)
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL___POR      0x00040020
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___POR 0x0
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___POR 0x04
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___POR 0x0
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___POR 0x20
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___M 0x01000000
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___S              24
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___M 0x00FF0000
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___S              16
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___M 0x00000100
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___S               8
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___M 0x000000FF
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___S               0
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL___M        0x01FF01FF   
#define   WMAC0_HWSCH_R0_SFM_BLK_CTRL___S                      0

#define WMAC0_HWSCH_R0_INBSS_NAV_CNT              (0x00AAC61C)
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT___POR     0x00000000
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___POR 0x00000000
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___S               0
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_INBSS_NAV_CNT___S                     0

#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT (0x00AAC620)
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___S               0
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___S               0

#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL      (0x00AAC624)
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___POR 0x0077000F
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___POR 0x0EE
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___POR 0x0
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___POR 0x00F
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___M 0x07FF8000
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___S              15
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___M 0x00001000
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___S              12
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___M 0x00000FFF
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___S               0
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___M 0x07FF9FFF   
#define   WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___S               0

#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n(n) (0x00AAC628+0x4*(n))
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMIN 0    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMAX 4    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_ELEM 5    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___S               0
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___S               0
#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0 (0x00AAC628)
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___S               0
#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1 (0x00AAC62C)
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___S               0
#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2 (0x00AAC630)
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___S               0
#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3 (0x00AAC634)
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___S               0
#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4 (0x00AAC638)
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___S               0

#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU     (0x00AAC63C)
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___POR 0x0000000C
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___POR 0x06
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___M 0x0000003E
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___S               1
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___M 0x00000001
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___S               0
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___M 0x0000003F   
#define   WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___S               0

#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR              (0x00AAC640)
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR___POR     0x00000000
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___POR 0x000000
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___M 0x00FFFFFF
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___S               0
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR___M       0x00FFFFFF   
#define   WMAC0_HWSCH_R0_DEBUG_SFM_CLR___S                     0

#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL        (0x00AAC644)
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___POR 0x00000000
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___POR 0x0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___M 0x00000100
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___S               8
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___M 0x000000C0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___S               6
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___M 0x00000030
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___S               4
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___M 0x00000008
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___S               3
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___M 0x00000004
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___S               2
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___M 0x00000002
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___S               1
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___M 0x00000001
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___S               0
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___M 0x000001FF   
#define   WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___S               0

#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL (0x00AAC648)
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___POR 0x00000000
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___POR 0x00000
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___S               0
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___S               0

#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR   (0x00AAC64C)
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___POR 0x00000000
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___S               0
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___S               0

#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE        (0x00AAC650)
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___POR 0x00000004
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___POR 0x04
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___M 0x0000001F
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___S               0
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___M 0x0000001F   
#define   WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___S               0

#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET (0x00AAC654)
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___POR 0x00000000
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___M 0x00003FFF
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___S               0
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___M 0x00003FFF   
#define   WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___S               0

#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE  (0x00AAC658)
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___POR 0x027FFFFB
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___POR 0x0
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___POR 0x027FFFFB
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___M 0x80000000
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___S              31
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___M 0x7FFFFFFF
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___S               0
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___S               0

#define WMAC0_HWSCH_R0_SPR_REG                    (0x00AAC65C)
#define   WMAC0_HWSCH_R0_SPR_REG___RWC              QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SPR_REG___POR           0x00000009
#define   WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___POR  0x00000009
#define   WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___M    0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___S                  0
#define   WMAC0_HWSCH_R0_SPR_REG___M             0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SPR_REG___S                           0

#define WMAC0_HWSCH_R0_SPR_EXT_REG                (0x00AAC660)
#define   WMAC0_HWSCH_R0_SPR_EXT_REG___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SPR_EXT_REG___POR       0xFFFF0000
#define   WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___POR 0xFFFF0000
#define   WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___S               0
#define   WMAC0_HWSCH_R0_SPR_EXT_REG___M         0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SPR_EXT_REG___S                       0

#define WMAC0_HWSCH_R0_SPR2_REG                   (0x00AAC664)
#define   WMAC0_HWSCH_R0_SPR2_REG___RWC             QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SPR2_REG___POR          0x00000000
#define   WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___POR 0x00000000
#define   WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___M   0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___S                 0
#define   WMAC0_HWSCH_R0_SPR2_REG___M            0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SPR2_REG___S                          0

#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL (0x00AAC668)
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___POR 0x00000000
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___POR 0x00000
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___S               0
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___S               0

#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF (0x00AAC66C)
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___POR 0x00000000
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___POR 0x00000
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___S               0
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___S               0

#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0 (0x00AAC670)
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___M 0xFF000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___S              24
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___M 0x00FF0000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___S              16
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___S               8
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___M 0x000000FF
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___S               0
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___S               0

#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1 (0x00AAC674)
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___M 0xFF000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___S              24
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___M 0x00FF0000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___S              16
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___S               8
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___M 0x000000FF
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___S               0
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___S               0

#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2 (0x00AAC678)
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___POR 0x00000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___M 0xFF000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___S              24
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___M 0x00FF0000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___S              16
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___S               8
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___M 0x000000FF
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___S               0
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___S               0

#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3 (0x00AAC67C)
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___POR 0x00000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___M 0xFF000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___S              24
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___M 0x00FF0000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___S              16
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___S               8
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___M 0x000000FF
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___S               0
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___S               0

#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4 (0x00AAC680)
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___POR 0x00000000
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___POR 0x00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___S               8
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___M 0x000000FF
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___S               0
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___S               0

#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0 (0x00AAC684)
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___POR 0x00000400
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___POR 0x0400
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___S               0
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___S               0

#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1 (0x00AAC688)
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___POR 0x00000
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___S               0
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___S               0

#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL      (0x00AAC68C)
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___POR 0x00000000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___POR 0x0
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___POR 0x0
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___POR 0x0
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___POR 0x0
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___POR 0x0000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___M 0x00080000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___S              19
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___M 0x00040000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___S              18
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___M 0x00020000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___S              17
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___M 0x00010000
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___S              16
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___S               0
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___M 0x000FFFFF   
#define   WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___S               0

#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL      (0x00AAC690)
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___POR 0x00000000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___POR 0x0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___M 0x00020000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___S              17
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___M 0x00010000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___S              16
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___M 0x00008000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___S              15
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___M 0x00004000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___S              14
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___M 0x00002000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___S              13
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___M 0x00001000
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___S              12
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___M 0x00000800
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___S              11
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___M 0x00000400
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___S              10
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___M 0x00000200
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___S               9
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___M 0x00000100
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___S               8
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___M 0x00000080
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___S               7
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___M 0x00000040
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___S               6
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___M 0x00000020
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___S               5
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___M 0x00000010
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___S               4
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___M 0x00000008
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___S               3
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___M 0x00000004
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___S               2
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___M 0x00000002
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___S               1
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___M 0x00000001
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___S               0
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___S               0

#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2            (0x00AAC694)
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2___POR   0x00000000
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___POR 0x00000000
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___S               0
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CW_ACTION_CTRL2___S                   0

#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0  (0x00AAC698)
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___M 0xC0000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___S              30
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___M 0x30000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___S              28
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___M 0x0C000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___S              26
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___M 0x03000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___S              24
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___M 0x00C00000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___S              22
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___M 0x00300000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___S              20
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___M 0x000C0000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___S              18
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___M 0x00030000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___S              16
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___M 0x0000C000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___S              14
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___M 0x00003000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___S              12
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___M 0x00000C00
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___S              10
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___M 0x00000300
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___S               8
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___M 0x000000C0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___S               6
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___M 0x00000030
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___S               4
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___M 0x0000000C
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___S               2
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___M 0x00000003
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___S               0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___S               0

#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1  (0x00AAC69C)
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___M 0x00300000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___S              20
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___M 0x000C0000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___S              18
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___M 0x00030000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___S              16
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___M 0x0000C000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___S              14
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___M 0x00003000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___S              12
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___M 0x00000C00
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___S              10
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___M 0x00000300
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___S               8
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___M 0x000000C0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___S               6
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___M 0x00000030
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___S               4
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___M 0x0000000C
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___S               2
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___M 0x00000003
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___S               0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___M 0x003FFFFF   
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___S               0

#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2  (0x00AAC6A0)
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___POR 0xFFFFFF03
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___POR 0xFF
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___POR 0xFF
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___POR 0xFF
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___POR 0x03
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___M 0xFF000000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___S              24
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___M 0x00FF0000
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___S              16
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___M 0x0000FF00
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___S               8
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___S               0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___S               0

#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3  (0x00AAC6A4)
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___POR 0x00000005
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___POR 0x1
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___M 0x00000004
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___S               2
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___M 0x00000002
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___S               1
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___M 0x00000001
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___S               0
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___M 0x00000007   
#define   WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___S               0

#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES   (0x00AAC6A8)
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___POR 0x00000010
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___POR 0x0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___POR 0x1
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___POR 0x0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___POR 0x0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___POR 0x0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___POR 0x0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___M 0x00000020
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___S               5
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___M 0x00000010
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___S               4
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___M 0x00000008
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___S               3
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___M 0x00000004
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___S               2
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___M 0x00000002
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___S               1
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___M 0x00000001
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___S               0
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___M 0x0000003F   
#define   WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___S               0

#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT    (0x00AAC6AC)
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___POR 0x000112C0
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___POR 0x0
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___POR 0x01
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___POR 0x12C0
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___M 0x01000000
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___S              24
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___M 0x00FF0000
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___S              16
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___S               0
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___M 0x01FFFFFF   
#define   WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___S               0

#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0     (0x00AAC6B0)
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___POR 0x00000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___S               0

#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1     (0x00AAC6B4)
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___POR 0x0000
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___S               0

#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER   (0x00AAC6B8)
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___S               0

#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER   (0x00AAC6BC)
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___S               0

#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER (0x00AAC6C0)
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___S               0

#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER (0x00AAC6C4)
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___S               0

#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER (0x00AAC6C8)
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___S               0

#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER (0x00AAC6CC)
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___S               0
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___S               0

#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0       (0x00AAC6D0)
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___POR 0x00000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___S               0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___S               0

#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1       (0x00AAC6D4)
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___POR 0x00000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___S               0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___S               0

#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2       (0x00AAC6D8)
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___POR 0x40020020
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___POR 0x1
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___POR 0x0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___POR 0x00
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___POR 0x0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___POR 0x0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___POR 0x0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___POR 0x2
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___POR 0x0020
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___M 0x40000000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___S              30
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___M 0x20000000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___S              29
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___M 0x1FC00000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___S              22
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___M 0x00200000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___S              21
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___M 0x00100000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___S              20
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___M 0x00080000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___S              19
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___M 0x00070000
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___S              16
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___S               0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___M 0x7FFFFFFF   
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___S               0

#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3       (0x00AAC6DC)
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___POR 0x00000009
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___POR 0x09
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___M 0x0000003F
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___S               0
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___M 0x0000003F   
#define   WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___S               0

#define WMAC0_HWSCH_R0_SW_MSG_CTRL                (0x00AAC6E0)
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL___POR       0x00000000
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___POR 0x0
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___POR 0x0
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___M 0x80000000
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___S              31
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___M 0x00000001
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___S               0
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL___M         0x80000001   
#define   WMAC0_HWSCH_R0_SW_MSG_CTRL___S                       0

#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0           (0x00AAC6E4)
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___POR  0x00000000
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___S               0
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___S                  0

#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1           (0x00AAC6E8)
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___POR  0x00000000
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___POR 0x00000000
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___S               0
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___S                  0

#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG      (0x00AAC6EC)
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___POR 0x00000010
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___POR 0x08
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___M 0x0000003E
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___S               1
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___M 0x00000001
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___M 0x0000003F   
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS    (0x00AAC6F0)
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___M 0x00FF0000
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___S              16
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___M 0x0000FF00
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___S               8
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___M 0x000000FF
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___M 0x00FFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG      (0x00AAC6F4)
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___M 0x00000001
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___M 0x00000001   
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___S               0

#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS    (0x00AAC6F8)
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___POR 0x00000000
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___M 0x00FF0000
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___S              16
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___M 0x0000FF00
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___S               8
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___M 0x000000FF
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___S               0
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___M 0x00FFFFFF   
#define   WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___S               0

#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS          (0x00AAC6FC)
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___POR 0x00000000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___POR 0x0000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___M 0x01000000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___S              24
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___M 0x00800000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___S              23
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___M 0x00400000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___S              22
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___M 0x00200000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___S              21
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___M 0x00100000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___S              20
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___M 0x00080000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___S              19
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___M 0x00040000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___S              18
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___M 0x00020000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___S              17
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___M 0x00010000
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___S              16
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___S               0
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___M   0x01FFFFFF   
#define   WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___S                 0

#define WMAC0_HWSCH_R0_FILTER_LUT_DATA            (0x00AAC700)
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA___POR   0x00000000
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___POR 0x0
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___POR 0x0000
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___M 0x00040000
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___S              18
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___M 0x00020000
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___S              17
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___M 0x00010000
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___S              16
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___S               0
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA___M     0x0007FFFF   
#define   WMAC0_HWSCH_R0_FILTER_LUT_DATA___S                   0

#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n(n) (0x00AAC704+0x4*(n))
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMIN 0    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMAX 17   
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_ELEM 18   
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___POR 0x0
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___POR 0x0
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___S               0
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___M 0x0000001F   
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0   (0x00AAC704)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1   (0x00AAC708)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2   (0x00AAC70C)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3   (0x00AAC710)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4   (0x00AAC714)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5   (0x00AAC718)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6   (0x00AAC71C)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7   (0x00AAC720)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8   (0x00AAC724)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9   (0x00AAC728)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10  (0x00AAC72C)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11  (0x00AAC730)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12  (0x00AAC734)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13  (0x00AAC738)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14  (0x00AAC73C)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15  (0x00AAC740)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16  (0x00AAC744)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___S               0
#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17  (0x00AAC748)
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___S               1
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___M 0x00000001
#define   WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___S               0

#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG        (0x00AAC74C)
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___POR 0x00000010
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___POR 0x1
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___M 0x00000010
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___S               4
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___M 0x00000008
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___S               3
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___M 0x00000004
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___S               2
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___M 0x00000002
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___S               1
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___M 0x00000001
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___S               0
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___M 0x0000001F   
#define   WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___S               0

#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL           (0x00AAC750)
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___POR  0x0083C600
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___POR 0x08
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___POR 0x3C
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___POR 0x3
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___POR 0x0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___M 0x80000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___S              31
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___M 0x40000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___S              30
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___M 0x20000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___S              29
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___M 0x10000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___S              28
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___M 0x08000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___S              27
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___M 0x04000000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___S              26
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___M 0x03F00000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___S              20
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___M 0x00080000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___S              19
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___M 0x0007F000
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___S              12
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___M 0x00000E00
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___S               9
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___M 0x00000100
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___S               8
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___M 0x000000C0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___S               6
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___M 0x00000020
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___S               5
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___M 0x00000010
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___S               4
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___M 0x0000000C
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___S               2
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___M 0x00000002
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___S               1
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___M 0x00000001
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___S               0
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___S                  0

#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE (0x00AAC754)
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___POR 0x00000000
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___POR 0x00000
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___S               0
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___S               0

#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE       (0x00AAC758)
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___POR 0x00000000
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___POR 0x00000
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___S               0
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION (0x00AAC75C)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___POR 0x00800080
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___POR 0x0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___POR 0x0100
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___POR 0x0080
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___M 0x80000000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___S              31
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___M 0x3FFF8000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___S              15
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___M 0x00007FFF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___M 0xBFFFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___S               0

#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS (0x00AAC760)
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___POR 0x00000000
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___POR 0x0
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___POR 0x0
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___M 0x00000002
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___S               1
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___M 0x00000001
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___S               0
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___M 0x00000003   
#define   WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___S               0

#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER (0x00AAC764)
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___POR 0x00000000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___POR 0x00
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___S              16
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___M 0x0000FF00
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___S               8
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___M 0x000000FF
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___S               0
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___S               0

#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL         (0x00AAC768)
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___POR 0x00000000
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___M 0x00000001
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___S               0
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___M  0x00000001   
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___S                0

#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n(n) (0x00AAC76C+0x4*(n))
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMIN 0    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMAX 3    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_ELEM 4    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___POR 0x00000000
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___POR 0x00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___POR 0x00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___M 0x00003F00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___S               8
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___S               0
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___M 0x00003FFF   
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___S               0
#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0        (0x00AAC76C)
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___M 0x00003F00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___S               8
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___S               0
#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1        (0x00AAC770)
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___M 0x00003F00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___S               8
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___S               0
#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2        (0x00AAC774)
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___M 0x00003F00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___S               8
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___S               0
#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3        (0x00AAC778)
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3___RWC  QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___M 0x00003F00
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___S               8
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___S               0

#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP   (0x00AAC77C)
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___POR 0x00010001
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___POR 0x0001
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___M 0x00010000
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___S              16
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___S               0
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___M 0x0001FFFF   
#define   WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___S               0

#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT          (0x00AAC780)
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___POR 0xFF17FFFF
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___POR 0xFF
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___POR 0x1
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___POR 0x0
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___POR 0x1
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___POR 0x1
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___POR 0x1
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___POR 0xFFFF
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___M 0xFF000000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___S              24
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___M 0x00100000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___S              20
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___M 0x00080000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___S              19
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___M 0x00040000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___S              18
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___M 0x00020000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___S              17
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___M 0x00010000
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___S              16
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___M 0x0000FFFF
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___S               0
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___M   0xFF1FFFFF   
#define   WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___S                 0

#define WMAC0_HWSCH_R0_SR_ERR_STATUS              (0x00AAC784)
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS___POR     0x00000000
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___POR 0x0
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___POR 0x0
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___POR 0x0
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___POR 0x0
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___M 0x00000008
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___S               3
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___M 0x00000004
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___S               2
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___M 0x00000002
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___S               1
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___M 0x00000001
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___S               0
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS___M       0x0000000F   
#define   WMAC0_HWSCH_R0_SR_ERR_STATUS___S                     0

#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0 (0x00AAC788)
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___POR 0x000FFFFF
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___M 0x00080000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___S              19
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___M 0x00040000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___S              18
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___M 0x00020000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___S              17
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___M 0x00010000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___S              16
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___M 0x00008000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___S              15
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___M 0x00004000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___S              14
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___M 0x00002000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___S              13
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___M 0x00001000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___S              12
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___M 0x00000800
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___S              11
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___M 0x00000400
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___S              10
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___M 0x00000200
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___S               9
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___M 0x00000100
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___S               8
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___M 0x00000080
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___S               7
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___M 0x00000040
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___S               6
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___M 0x00000020
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___S               5
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___M 0x00000010
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___S               4
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___M 0x00000008
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___S               3
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___M 0x00000004
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___S               2
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___M 0x00000002
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___S               1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___M 0x00000001
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___S               0
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___M 0x000FFFFF   
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___S               0

#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1 (0x00AAC78C)
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___POR 0x00007FFF
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___POR 0x1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___M 0x00004000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___S              14
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___M 0x00002000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___S              13
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___M 0x00001000
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___S              12
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___M 0x00000800
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___S              11
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___M 0x00000400
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___S              10
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___M 0x00000200
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___S               9
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___M 0x00000100
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___S               8
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___M 0x00000080
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___S               7
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___M 0x00000040
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___S               6
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___M 0x00000020
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___S               5
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___M 0x00000010
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___S               4
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___M 0x00000008
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___S               3
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___M 0x00000004
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___S               2
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___M 0x00000002
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___S               1
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___M 0x00000001
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___S               0
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___M 0x00007FFF   
#define   WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___S               0

#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0 (0x00AAC790)
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___POR 0x00000
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___S               0
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___S               0

#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1 (0x00AAC794)
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___POR 0x00000
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___S               0
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___S               0

#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0              (0x00AAC798)
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0___POR     0x00000000
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___POR 0x00
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___POR 0x00
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___M 0x0000FF00
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___S               8
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___M 0x000000FF
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___S               0
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0___M       0x0000FFFF   
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_0___S                     0

#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1              (0x00AAC79C)
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1___POR     0x00000000
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___POR 0x00000
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___S               0
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1___M       0x0003FFFF   
#define   WMAC0_HWSCH_R0_ILP_CTRL_IX_1___S                     0

#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL            (0x00AAC7A0)
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___POR   0x00000006
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___POR 0x1
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___POR 0x1
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___POR 0x0
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___M 0x00000004
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___S               2
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___M 0x00000002
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___S               1
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___M 0x00000001
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___S               0
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___M     0x00000007   
#define   WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___S                   0

#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0 (0x00AAC7A4)
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___POR 0x00000
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___S               0
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___S               0

#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1 (0x00AAC7A8)
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___POR 0x00000
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___M 0x0003FFFF
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___S               0
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___M 0x0003FFFF   
#define   WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___S               0

#define WMAC0_HWSCH_R1_LFSR_DATA_1_0              (0x00AAE000)
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0___RWC        QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0___POR     0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_1_0___S                     0

#define WMAC0_HWSCH_R1_LFSR_DATA_3_2              (0x00AAE004)
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2___RWC        QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2___POR     0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_3_2___S                     0

#define WMAC0_HWSCH_R1_LFSR_DATA_5_4              (0x00AAE008)
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4___RWC        QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4___POR     0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_5_4___S                     0

#define WMAC0_HWSCH_R1_LFSR_DATA_7_6              (0x00AAE00C)
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6___RWC        QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6___POR     0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_7_6___S                     0

#define WMAC0_HWSCH_R1_LFSR_DATA_9_8              (0x00AAE010)
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8___RWC        QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8___POR     0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8___M       0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_9_8___S                     0

#define WMAC0_HWSCH_R1_LFSR_DATA_11_10            (0x00AAE014)
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10___RWC      QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10___POR   0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_11_10___S                   0

#define WMAC0_HWSCH_R1_LFSR_DATA_13_12            (0x00AAE018)
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12___RWC      QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12___POR   0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_13_12___S                   0

#define WMAC0_HWSCH_R1_LFSR_DATA_15_14            (0x00AAE01C)
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14___RWC      QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14___POR   0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_15_14___S                   0

#define WMAC0_HWSCH_R1_LFSR_DATA_17_16            (0x00AAE020)
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16___RWC      QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16___POR   0x00000000
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___POR 0x0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___S              16
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___S               0
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16___M     0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_LFSR_DATA_17_16___S                   0

#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL            (0x00AAE028)
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL___RWC      QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL___POR   0x0003FFFF
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___POR 0x0
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___POR 0x3FFFF
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___M 0x80000000
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___S              31
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___M 0x0003FFFF
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___S               0
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL___M     0x8003FFFF   
#define   WMAC0_HWSCH_R1_MGMT_STATS_CTRL___S                   0

#define WMAC0_HWSCH_R1_ACK_PASS_STATS             (0x00AAE02C)
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS___POR    0x00000000
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS___M      0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_ACK_PASS_STATS___S                    0

#define WMAC0_HWSCH_R1_RETRY_STATS                (0x00AAE030)
#define   WMAC0_HWSCH_R1_RETRY_STATS___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_RETRY_STATS___POR       0x00000000
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_RETRY_STATS___M         0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_RETRY_STATS___S                       0

#define WMAC0_HWSCH_R1_REQUEUE_STATS              (0x00AAE034)
#define   WMAC0_HWSCH_R1_REQUEUE_STATS___RWC        QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_REQUEUE_STATS___POR     0x00000000
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_REQUEUE_STATS___M       0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_REQUEUE_STATS___S                     0

#define WMAC0_HWSCH_R1_FILTER_STATS               (0x00AAE038)
#define   WMAC0_HWSCH_R1_FILTER_STATS___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_FILTER_STATS___POR      0x00000000
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_FILTER_STATS___M        0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_FILTER_STATS___S                      0

#define WMAC0_HWSCH_R1_BSPLIT_STATS               (0x00AAE03C)
#define   WMAC0_HWSCH_R1_BSPLIT_STATS___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_BSPLIT_STATS___POR      0x00000000
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_BSPLIT_STATS___M        0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_BSPLIT_STATS___S                      0

#define WMAC0_HWSCH_R1_FLUSH_STATS                (0x00AAE040)
#define   WMAC0_HWSCH_R1_FLUSH_STATS___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_FLUSH_STATS___POR       0x00000000
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___POR 0x00000
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___POR 0x000
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___M 0x3FFFF000
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___S              12
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___M 0x00000FFF
#define   WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_FLUSH_STATS___M         0x3FFFFFFF   
#define   WMAC0_HWSCH_R1_FLUSH_STATS___S                       0

#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS      (0x00AAE044)
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___POR 0x00000000
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___POR 0x00
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___M 0x000000FF
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___S               0
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___M 0x000000FF   
#define   WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___S               0

#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG       (0x00AAE048)
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___POR 0x00000000
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___POR 0x0
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___POR 0x0
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___M 0x00000002
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___S               1
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___M 0x00000001
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___S               0
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___M 0x00000003   
#define   WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___S               0

#define WMAC0_HWSCH_R1_SR_SRP_STATS_0             (0x00AAE04C)
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0___POR    0x00000000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___S              16
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___S               0
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_0___S                    0

#define WMAC0_HWSCH_R1_SR_SRP_STATS_1             (0x00AAE050)
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1___POR    0x00000000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___S              16
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___S               0
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_1___S                    0

#define WMAC0_HWSCH_R1_SR_SRP_STATS_2             (0x00AAE054)
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2___POR    0x00000000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___S              16
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___S               0
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_2___S                    0

#define WMAC0_HWSCH_R1_SR_SRP_STATS_3             (0x00AAE058)
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3___POR    0x00000000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___S              16
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___S               0
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SR_SRP_STATS_3___S                    0

#define WMAC0_HWSCH_R1_NAV_STATS_0                (0x00AAE05C)
#define   WMAC0_HWSCH_R1_NAV_STATS_0___RWC          QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_NAV_STATS_0___POR       0x00000000
#define   WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___S              16
#define   WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___S               0
#define   WMAC0_HWSCH_R1_NAV_STATS_0___M         0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_NAV_STATS_0___S                       0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0           (0x00AAE060)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___M 0xFFFFFFFC
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___S               2
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___M    0xFFFFFFFC   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___S                  2

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1           (0x00AAE064)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2           (0x00AAE068)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___POR 0x000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___M 0x000001FF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___M    0x000001FF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3           (0x00AAE06C)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4           (0x00AAE070)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5           (0x00AAE074)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6           (0x00AAE078)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___POR 0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___M    0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7           (0x00AAE07C)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___POR 0x0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___M 0x00000007
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___M    0x00000007   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___S                  0

#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8           (0x00AAE080)
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___POR  0x00000000
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___POR 0x0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___M 0x0000000F
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___S               0
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___M    0x0000000F   
#define   WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___S                  0

#define WMAC0_HWSCH_R1_TLV_IF_STATS               (0x00AAE084)
#define   WMAC0_HWSCH_R1_TLV_IF_STATS___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_TLV_IF_STATS___POR      0x00000000
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___S              16
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___S               0
#define   WMAC0_HWSCH_R1_TLV_IF_STATS___M        0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_TLV_IF_STATS___S                      0

#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0         (0x00AAE088)
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___POR 0x00000000
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___S               0
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___S                0

#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1         (0x00AAE08C)
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___POR 0x00000000
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___S               0
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___M  0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___S                0

#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS          (0x00AAE090)
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___POR 0x00000000
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___S              16
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___S               0
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___M   0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___S                 0

#define WMAC0_HWSCH_R1_AXI_STATS                  (0x00AAE094)
#define   WMAC0_HWSCH_R1_AXI_STATS___RWC            QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_AXI_STATS___POR         0x00000000
#define   WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___POR 0x0
#define   WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___POR 0x0000
#define   WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___M 0x80000000
#define   WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___S              31
#define   WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___S               0
#define   WMAC0_HWSCH_R1_AXI_STATS___M           0x8000FFFF   
#define   WMAC0_HWSCH_R1_AXI_STATS___S                         0

#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n(n) (0x00AAE098+0x4*(n))
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_nMIN 0    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_nMAX 19   
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_ELEM 20   
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___POR 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___POR 0xFF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___S               0
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___M   0x000000FF   
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___S                 0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0          (0x00AAE098)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1          (0x00AAE09C)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2          (0x00AAE0A0)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3          (0x00AAE0A4)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4          (0x00AAE0A8)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5          (0x00AAE0AC)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6          (0x00AAE0B0)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7          (0x00AAE0B4)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8          (0x00AAE0B8)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9          (0x00AAE0BC)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10         (0x00AAE0C0)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11         (0x00AAE0C4)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12         (0x00AAE0C8)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13         (0x00AAE0CC)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14         (0x00AAE0D0)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15         (0x00AAE0D4)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16         (0x00AAE0D8)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17         (0x00AAE0DC)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18         (0x00AAE0E0)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18__SELECT___S               0
#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19         (0x00AAE0E4)
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19__SELECT___M 0x000000FF
#define   WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19__SELECT___S               0

#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL  (0x00AAE0E8)
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL (0x00AAE0EC)
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___POR 0x00200000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___POR 0x0
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___POR 0x0
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___POR 0x008
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___POR 0x000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___POR 0x000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___M 0xE0000000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___S              29
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___M 0x10000000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___S              28
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___M 0x0FFC0000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___S              18
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___M 0x0003FE00
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___S               9
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___M 0x000001FF
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___S               0
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___S               0

#define WMAC0_HWSCH_R1_APT_CTRL_SPR               (0x00AAE0F0)
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR___RWC         QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR___POR      0x00000000
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___POR 0x00
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___POR 0x00
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___M 0x0000FF00
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___S               8
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___M 0x000000FF
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___S               0
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR___M        0x0000FFFF   
#define   WMAC0_HWSCH_R1_APT_CTRL_SPR___S                      0

#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS           (0x00AAE0F4)
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS___RWC     QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS___POR  0x00000000
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___POR 0x0000
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___S               0
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS___M    0x0000FFFF   
#define   WMAC0_HWSCH_R1_LMODE_VIOL_STATS___S                  0

#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD       (0x00AAE0F8)
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___POR 0x00000016
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___POR 0x16
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___M 0x0000001F
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___S               0
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___M 0x0000001F   
#define   WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___S               0

#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS      (0x00AAE0FC)
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___POR 0x00000000
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___POR 0x0000
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___POR 0x0000
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___S              16
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___S               0
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___S               0

#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT             (0x00AAE100)
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT___RWC       QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT___POR    0x00000000
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___POR 0x0000
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___POR 0x0000
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___M 0xFFFF0000
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___S              16
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___M 0x0000FFFF
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___S               0
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT___M      0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_HWSCH_SPR_STAT___S                    0

#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR     (0x00AAE104)
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___POR 0x0E0E0E0E
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___M 0xFF000000
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___S              24
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___M 0x00FF0000
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___S              16
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___M 0x0000FF00
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___S               8
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___M 0x000000FF
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___S               0
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___M 0xFFFFFFFF   
#define   WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___S               0

#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR          (0x00AAE108)
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___RWC    QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___POR 0x00000E0E
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___POR 0x0
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___POR 0x00
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___POR 0x0E
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___M 0x01000000
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___S              24
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___M 0x00FF0000
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___S              16
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___M 0x0000FF00
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___S               8
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___M 0x000000FF
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___S               0
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___M   0x01FFFFFF   
#define   WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___S                 0

#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR   (0x00AAE10C)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___RWC QCSR_REG_WO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___POR 0x00000000
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___POR 0x0
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___M 0x00000001
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___S               0
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___M 0x00000001   
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___S               0

#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n(n) (0x00AAE110+0x4*(n))
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_nMIN 0    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_nMAX 7    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_ELEM 8    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___POR 0x00000000
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___POR 0x00
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___S               0
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___M 0x000000FF   
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0     (0x00AAE110)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1     (0x00AAE114)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2     (0x00AAE118)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3     (0x00AAE11C)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4     (0x00AAE120)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5     (0x00AAE124)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6     (0x00AAE128)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6__ERROR_INTR_CODE___S               0
#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7     (0x00AAE12C)
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7__ERROR_INTR_CODE___M 0x000000FF
#define   WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7__ERROR_INTR_CODE___S               0

#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2 (0x00AAE130)
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___POR 0x00000000
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___POR 0x0
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___M 0x00000001
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___S               0
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___M 0x00000001   
#define   WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0     (0x00AAF000)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1     (0x00AAF004)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2     (0x00AAF008)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3     (0x00AAF00C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4     (0x00AAF010)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5     (0x00AAF014)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6     (0x00AAF018)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7     (0x00AAF01C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8     (0x00AAF020)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9     (0x00AAF024)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10    (0x00AAF028)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11    (0x00AAF02C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12    (0x00AAF030)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13    (0x00AAF034)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14    (0x00AAF038)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15    (0x00AAF03C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16    (0x00AAF040)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17    (0x00AAF044)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0     (0x00AAF050)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1     (0x00AAF054)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2     (0x00AAF058)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3     (0x00AAF05C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4     (0x00AAF060)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5     (0x00AAF064)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6     (0x00AAF068)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7     (0x00AAF06C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8     (0x00AAF070)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9     (0x00AAF074)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10    (0x00AAF078)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11    (0x00AAF07C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12    (0x00AAF080)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13    (0x00AAF084)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14    (0x00AAF088)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15    (0x00AAF08C)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16    (0x00AAF090)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___S               0

#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17    (0x00AAF094)
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___POR 0x00000000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___S               0

#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD       (0x00AAF0A0)
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___RWC QCSR_REG_RO    
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___POR 0x00000000
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___S               0
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___S               0

#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL       (0x00AAF0A4)
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___RWC QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___POR 0x00000000
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___POR 0x0000
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___S               0
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___M 0x0000FFFF   
#define   WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___S               0

#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP         (0x00AAF0A8)
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___POR 0x00000000
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___POR 0x0000
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___S               0
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___M  0x0000FFFF   
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___S                0

#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP         (0x00AAF0AC)
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___RWC   QCSR_REG_RW    
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___POR 0x00000000
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___POR 0x0000
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___S               0
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___M  0x0000FFFF   
#define   WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___S                0

#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE           (0x00AB0000)
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE___RWC     QCSR_REG_RW    
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE___POR  0x00000000
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___POR 0x0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___M 0x00000040
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___S               6
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___M 0x00000020
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___S               5
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___M 0x00000010
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___S               4
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___M 0x00000008
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___S               3
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___M 0x00000004
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___S               2
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___M 0x00000002
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___S               1
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___M 0x00000001
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___S               0
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE___M    0x8000007F   
#define   WMAC0_MXI_R0_CLOCK_GATE_DISABLE___S                  0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0       (0x00AB0004)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___POR 0x0000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___M 0x38000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___S              27
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___M 0x04000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___S              26
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___M 0x02000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___S              25
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___M 0x01FFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0       (0x00AB0008)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1       (0x00AB000C)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___POR 0x0000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___M 0x38000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___S              27
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___M 0x04000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___S              26
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___M 0x02000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___S              25
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___M 0x01FFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1       (0x00AB0010)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2       (0x00AB0014)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___POR 0x0000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___M 0x38000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___S              27
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___M 0x04000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___S              26
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___M 0x02000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___S              25
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___M 0x01FFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2       (0x00AB0018)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3       (0x00AB001C)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___POR 0x0000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___M 0x38000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___S              27
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___M 0x04000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___S              26
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___M 0x02000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___S              25
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___M 0x01FFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___S               0

#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3       (0x00AB0020)
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0       (0x00AB0024)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___M 0x00070000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___S              16
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___M 0x00000100
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___S               8
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___M 0x00000001
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___M 0x00070101   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0    (0x00AB0028)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___M 0x3FFFFFFF
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0       (0x00AB002C)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1       (0x00AB0030)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___POR 0x0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___M 0x00070000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___S              16
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___M 0x00000100
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___S               8
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___M 0x00000001
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___M 0x00070101   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1    (0x00AB0034)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___M 0x3FFFFFFF
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___M 0x3FFFFFFF   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___S               0

#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1       (0x00AB0038)
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___S               0
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___S               0

#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER          (0x00AB003C)
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER___RWC    QCSR_REG_RW    
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___POR 0x00000000
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___S               0
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER___M   0xFFFFFFFF   
#define   WMAC0_MXI_R0_MXI_S_PARE_REGISTER___S                 0

#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER       (0x00AB0040)
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___S               0

#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER       (0x00AB0044)
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___M 0x000000FF   
#define   WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___S               0

#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0      (0x00AB0048)
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___POR 0x00000211
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S               9
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S               4
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___M 0x00000FFF   
#define   WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___S               0

#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK   (0x00AB004C)
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___M 0x00000001   
#define   WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___S               0

#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE  (0x00AB0050)
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S              31
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___S              11
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S              10
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S               9
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S               7
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S               6
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S               5
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S               4
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S               3
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S               2
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___S               1
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF   
#define   WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS        (0x00AB0054)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___RWC  QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S              24
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___M 0x01010101   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS       (0x00AB0058)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___M 0x003F3F3F   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL (0x00AB005C)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S              24
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL (0x00AB0060)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S              24
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL    (0x00AB0064)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___POR 0x00240000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S              27
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S              26
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S              25
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S              24
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S              23
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S              20
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S              17
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S               9
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S               1
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL    (0x00AB0068)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS     (0x00AB006C)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___M 0x0000FFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS   (0x00AB0070)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL (0x00AB0074)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL (0x00AB0078)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S              17
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S              16
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00AB007C)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00AB0080)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00AB0084)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00AB0088)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S               0

#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL (0x00AB008C)
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S              15
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S               8
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S               7
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S               0
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F   
#define   WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___S               0

#define WMAC0_MXI_R1_TESTBUS_CTRL                 (0x00AB1000)
#define   WMAC0_MXI_R1_TESTBUS_CTRL___RWC           QCSR_REG_RW    
#define   WMAC0_MXI_R1_TESTBUS_CTRL___POR        0x00000000
#define   WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0
#define   WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00
#define   WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x00010000
#define   WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S              16
#define   WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000001F
#define   WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S               0
#define   WMAC0_MXI_R1_TESTBUS_CTRL___M          0x0001001F   
#define   WMAC0_MXI_R1_TESTBUS_CTRL___S                        0

#define WMAC0_MXI_R1_EVENTMASK_IX_0               (0x00AB1004)
#define   WMAC0_MXI_R1_EVENTMASK_IX_0___RWC         QCSR_REG_RW    
#define   WMAC0_MXI_R1_EVENTMASK_IX_0___POR      0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___M  0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___S                0
#define   WMAC0_MXI_R1_EVENTMASK_IX_0___M        0xFFFFFFFF   
#define   WMAC0_MXI_R1_EVENTMASK_IX_0___S                      0

#define WMAC0_MXI_R1_EVENTMASK_IX_1               (0x00AB1008)
#define   WMAC0_MXI_R1_EVENTMASK_IX_1___RWC         QCSR_REG_RW    
#define   WMAC0_MXI_R1_EVENTMASK_IX_1___POR      0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___M  0xFFFFFFFF
#define   WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___S                0
#define   WMAC0_MXI_R1_EVENTMASK_IX_1___M        0xFFFFFFFF   
#define   WMAC0_MXI_R1_EVENTMASK_IX_1___S                      0

#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL    (0x00AB100C)
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW    
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S              17
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S               2
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S               1
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S               0
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF   
#define   WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___S               0

#define WMAC0_MXI_R1_END_OF_TEST_CHECK            (0x00AB1010)
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK___RWC      QCSR_REG_RW    
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK___POR   0x00000000
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S               0
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK___M     0x00000001   
#define   WMAC0_MXI_R1_END_OF_TEST_CHECK___S                   0

#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n(n) (0x00AB3000+0x4*(n))
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n_nMIN 0    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n_nMAX 9    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n_ELEM 10   
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n___POR   0x00000010
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___POR 0x010
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___S               0
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n___M     0x000003FF   
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_n___S                   0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_0            (0x00AB3000)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_0___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_0__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_1            (0x00AB3004)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_1___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_1__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_2            (0x00AB3008)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_2___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_2__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_3            (0x00AB300C)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_3___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_3__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_4            (0x00AB3010)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_4___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_4__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_5            (0x00AB3014)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_5___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_5__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_6            (0x00AB3018)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_6___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_6__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_7            (0x00AB301C)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_7___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_7__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_8            (0x00AB3020)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_8___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_8__VALUE___S               0
#define WMAC0_SFM_R0_MINIMUM_BUFFERS_9            (0x00AB3024)
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_9___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MINIMUM_BUFFERS_9__VALUE___S               0

#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n(n) (0x00AB3028+0x4*(n))
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_nMIN 0    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_nMAX 9    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_ELEM 10   
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___POR   0x00000190
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___POR 0x190
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___S               0
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___M     0x000003FF   
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___S                   0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_0            (0x00AB3028)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_0___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_0__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_1            (0x00AB302C)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_1___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_1__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_2            (0x00AB3030)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_2___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_2__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_3            (0x00AB3034)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_3___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_3__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_4            (0x00AB3038)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_4___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_4__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_5            (0x00AB303C)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_5___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_5__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_6            (0x00AB3040)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_6___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_6__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_7            (0x00AB3044)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_7___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_7__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_8            (0x00AB3048)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_8___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_8__VALUE___S               0
#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_9            (0x00AB304C)
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_9___RWC      QCSR_REG_RW    
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_MAXIMUM_BUFFERS_9__VALUE___S               0

#define WMAC0_SFM_R0_BUSY_BUFFERS_n(n)   (0x00AB3050+0x4*(n))
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n_nMIN 0    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n_nMAX 9    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n_ELEM 10   
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n___POR      0x00000000
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___POR 0x000
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___S               0
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n___M        0x000003FF   
#define   WMAC0_SFM_R0_BUSY_BUFFERS_n___S                      0
#define WMAC0_SFM_R0_BUSY_BUFFERS_0               (0x00AB3050)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_0___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_0__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_1               (0x00AB3054)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_1___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_1__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_2               (0x00AB3058)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_2___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_2__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_3               (0x00AB305C)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_3___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_3__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_4               (0x00AB3060)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_4___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_4__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_5               (0x00AB3064)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_5___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_5__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_6               (0x00AB3068)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_6___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_6__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_7               (0x00AB306C)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_7___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_7__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_8               (0x00AB3070)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_8___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_8__VALUE___S               0
#define WMAC0_SFM_R0_BUSY_BUFFERS_9               (0x00AB3074)
#define   WMAC0_SFM_R0_BUSY_BUFFERS_9___RWC         QCSR_REG_RO    
#define   WMAC0_SFM_R0_BUSY_BUFFERS_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_BUSY_BUFFERS_9__VALUE___S               0

#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n(n) (0x00AB3078+0x4*(n))
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_nMIN 0    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_nMAX 9    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_ELEM 10   
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___POR 0x00000000
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___POR 0x000
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___S               0
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___M   0x000003FF   
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___S                 0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_0          (0x00AB3078)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_0___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_0__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_1          (0x00AB307C)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_1___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_1__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_2          (0x00AB3080)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_2___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_2__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_3          (0x00AB3084)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_3___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_3__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_4          (0x00AB3088)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_4___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_4__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_5          (0x00AB308C)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_5___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_5__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_6          (0x00AB3090)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_6___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_6__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_7          (0x00AB3094)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_7___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_7__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_8          (0x00AB3098)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_8___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_8__VALUE___S               0
#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_9          (0x00AB309C)
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_9___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_ALLOCATED_BUFFERS_9__VALUE___S               0

#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n(n) (0x00AB30A0+0x4*(n))
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_nMIN 0    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_nMAX 9    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_ELEM 10   
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___POR 0x00000000
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___POR 0x000
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___S               0
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___M   0x000003FF   
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___S                 0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_0          (0x00AB30A0)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_0___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_0__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_1          (0x00AB30A4)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_1___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_1__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_2          (0x00AB30A8)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_2___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_2__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_3          (0x00AB30AC)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_3___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_3__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_4          (0x00AB30B0)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_4___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_4__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_5          (0x00AB30B4)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_5___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_5__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_6          (0x00AB30B8)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_6___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_6__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_7          (0x00AB30BC)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_7___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_7__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_8          (0x00AB30C0)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_8___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_8__VALUE___S               0
#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_9          (0x00AB30C4)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_9___RWC    QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_9__VALUE___S               0

#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS           (0x00AB30C8)
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS___RWC     QCSR_REG_RW    
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS___POR  0x00000000
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___M 0x00000200
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___S               9
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___M 0x00000100
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___S               8
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___M 0x00000080
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___S               7
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___M 0x00000040
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___S               6
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___M 0x00000020
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___S               5
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___M 0x00000010
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___S               4
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___M 0x00000008
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___S               3
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___M 0x00000004
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___S               2
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___M 0x00000002
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___S               1
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___M 0x00000001
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___S               0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS___M    0x000003FF   
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS___S                  0

#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE      (0x00AB30CC)
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___POR 0x00000000
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___POR 0x0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___M 0x00000200
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___S               9
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___M 0x00000100
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___S               8
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___M 0x00000080
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___S               7
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___M 0x00000040
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___S               6
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___M 0x00000020
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___S               5
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___M 0x00000010
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___S               4
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___M 0x00000008
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___S               3
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___M 0x00000004
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___S               2
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___M 0x00000002
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___S               1
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___M 0x00000001
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___S               0
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___M 0x000003FF   
#define   WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___S               0

#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL       (0x00AB30D0)
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___POR 0x00000100
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___POR 0x100
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___S               0
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___M 0x000003FF   
#define   WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___S               0

#define WMAC0_SFM_R0_HW_INIT                      (0x00AB30D4)
#define   WMAC0_SFM_R0_HW_INIT___RWC                QCSR_REG_RW    
#define   WMAC0_SFM_R0_HW_INIT___POR             0x00000000
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___POR 0x0
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___POR 0x0
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___M 0x00000002
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___S               1
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___M 0x00000001
#define   WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___S               0
#define   WMAC0_SFM_R0_HW_INIT___M               0x00000003   
#define   WMAC0_SFM_R0_HW_INIT___S                             0

#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS      (0x00AB30D8)
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___POR 0x00000320
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___POR 0x320
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___M 0x000003FF
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___S               0
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___M 0x000003FF   
#define   WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n(n) (0x00AB30DC+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_nMAX 2    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_ELEM 3    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0    (0x00AB30DC)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1    (0x00AB30E0)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2    (0x00AB30E4)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1      (0x00AB3178)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n(n) (0x00AB317C+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_nMAX 2    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_ELEM 3    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0    (0x00AB317C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1    (0x00AB3180)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2    (0x00AB3184)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n(n) (0x00AB3210+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_nMAX 2    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_ELEM 3    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0    (0x00AB3210)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1    (0x00AB3214)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2    (0x00AB3218)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n(n) (0x00AB321C+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_nMAX 25   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_ELEM 26   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0    (0x00AB321C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1    (0x00AB3220)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2    (0x00AB3224)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3    (0x00AB3228)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4    (0x00AB322C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5    (0x00AB3230)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6    (0x00AB3234)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7    (0x00AB3238)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8    (0x00AB323C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9    (0x00AB3240)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10   (0x00AB3244)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11   (0x00AB3248)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12   (0x00AB324C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13   (0x00AB3250)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14   (0x00AB3254)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15   (0x00AB3258)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16   (0x00AB325C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17   (0x00AB3260)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18   (0x00AB3264)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19   (0x00AB3268)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20   (0x00AB326C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21   (0x00AB3270)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22   (0x00AB3274)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23   (0x00AB3278)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24   (0x00AB327C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25   (0x00AB3280)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n(n) (0x00AB3288+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_nMAX 3    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_ELEM 4    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0    (0x00AB3288)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1    (0x00AB328C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2    (0x00AB3290)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3    (0x00AB3294)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n(n) (0x00AB331C+0x4*(n))
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_nMIN 0    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_nMAX 2    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_ELEM 3    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0    (0x00AB331C)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1    (0x00AB3320)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1__VALUE___S               0
#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2    (0x00AB3324)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2__VALUE___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7      (0x00AB33B0)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8      (0x00AB33B4)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___S               0

#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9      (0x00AB3448)
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___POR 0x00000000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___S               0
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___M 0x00007FFF   
#define   WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___S               0

#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR         (0x00AB344C)
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___RWC   QCSR_REG_RO    
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___POR 0x00000000
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___S              16
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___S               0
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___M  0xFFFFFFFF   
#define   WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___S                0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n(n) (0x00AB3450+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0 (0x00AB3450)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1 (0x00AB3454)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2 (0x00AB3458)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n(n) (0x00AB34E4+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0 (0x00AB34E4)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__SAVED_HEAD___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1 (0x00AB34E8)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__SAVED_HEAD___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2 (0x00AB34EC)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__SAVED_HEAD___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n(n) (0x00AB3578+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0 (0x00AB3578)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1 (0x00AB357C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2 (0x00AB3580)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n(n) (0x00AB3584+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0 (0x00AB3584)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__SAVED_HEAD___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1 (0x00AB3588)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__SAVED_HEAD___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2 (0x00AB358C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__NEXT_HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__NEXT_HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__SAVED_HEAD___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__SAVED_HEAD___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n(n) (0x00AB3590+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0 (0x00AB3590)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1 (0x00AB3594)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2 (0x00AB3598)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1 (0x00AB362C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n(n) (0x00AB3630+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_nMAX 25   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_ELEM 26   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0 (0x00AB3630)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1 (0x00AB3634)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2 (0x00AB3638)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3 (0x00AB363C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4 (0x00AB3640)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5 (0x00AB3644)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6 (0x00AB3648)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7 (0x00AB364C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8 (0x00AB3650)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9 (0x00AB3654)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10 (0x00AB3658)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11 (0x00AB365C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12 (0x00AB3660)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13 (0x00AB3664)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14 (0x00AB3668)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15 (0x00AB366C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16 (0x00AB3670)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17 (0x00AB3674)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18 (0x00AB3678)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19 (0x00AB367C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20 (0x00AB3680)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21 (0x00AB3684)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22 (0x00AB3688)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23 (0x00AB368C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24 (0x00AB3690)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25 (0x00AB3694)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n(n) (0x00AB369C+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_nMAX 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_ELEM 4    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0 (0x00AB369C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1 (0x00AB36A0)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2 (0x00AB36A4)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3 (0x00AB36A8)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n(n) (0x00AB3730+0x4*(n))
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_nMIN 0    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_nMAX 2    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_ELEM 3    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0 (0x00AB3730)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1 (0x00AB3734)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__TAIL___S               0
#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2 (0x00AB3738)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__TAIL___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7 (0x00AB37C4)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8 (0x00AB37C8)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___S               0

#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9 (0x00AB385C)
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___POR 0x00000000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___POR 0x0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___M 0xFFFF0000
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___S              16
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___M 0x0000FFFF
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___S               0
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___M 0xFFFFFFFF   
#define   WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___S               0

#define WMAC0_SFM_R0_RRI_TABLE_ADDR               (0x00AB3860)
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR___POR      0x00000000
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___M 0x00007FFF
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___S               0
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR___M        0x00007FFF   
#define   WMAC0_SFM_R0_RRI_TABLE_ADDR___S                      0

#define WMAC0_SFM_R0_RRI_TABLE_DATA               (0x00AB3864)
#define   WMAC0_SFM_R0_RRI_TABLE_DATA___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_TABLE_DATA___POR      0x00000000
#define   WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___POR 0x00000000
#define   WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___M 0xFFFFFFFF
#define   WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___S               0
#define   WMAC0_SFM_R0_RRI_TABLE_DATA___M        0xFFFFFFFF   
#define   WMAC0_SFM_R0_RRI_TABLE_DATA___S                      0

#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC           (0x00AB3868)
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___RWC     QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___POR  0x00000000
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___POR 0x0
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___M 0x00000001
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___S               0
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___M    0x00000001   
#define   WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___S                  0

#define WMAC0_SFM_R0_CMEM_CONTROL                 (0x00AB386C)
#define   WMAC0_SFM_R0_CMEM_CONTROL___RWC           QCSR_REG_RW    
#define   WMAC0_SFM_R0_CMEM_CONTROL___POR        0x00000000
#define   WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___POR 0x0
#define   WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___POR 0x0
#define   WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___M 0x00000002
#define   WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___S               1
#define   WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___M 0x00000001
#define   WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___S               0
#define   WMAC0_SFM_R0_CMEM_CONTROL___M          0x00000003   
#define   WMAC0_SFM_R0_CMEM_CONTROL___S                        0

#define WMAC0_SFM_R0_CMEM_ADDR                    (0x00AB3870)
#define   WMAC0_SFM_R0_CMEM_ADDR___RWC              QCSR_REG_RW    
#define   WMAC0_SFM_R0_CMEM_ADDR___POR           0x00000000
#define   WMAC0_SFM_R0_CMEM_ADDR__VALUE___POR    0x0000
#define   WMAC0_SFM_R0_CMEM_ADDR__VALUE___M      0x00007FFF
#define   WMAC0_SFM_R0_CMEM_ADDR__VALUE___S                    0
#define   WMAC0_SFM_R0_CMEM_ADDR___M             0x00007FFF   
#define   WMAC0_SFM_R0_CMEM_ADDR___S                           0

#define WMAC0_SFM_R0_CMEM_DATA                    (0x00AB3874)
#define   WMAC0_SFM_R0_CMEM_DATA___RWC              QCSR_REG_RW    
#define   WMAC0_SFM_R0_CMEM_DATA___POR           0x00000000
#define   WMAC0_SFM_R0_CMEM_DATA__VALUE___POR    0x00000000
#define   WMAC0_SFM_R0_CMEM_DATA__VALUE___M      0xFFFFFFFF
#define   WMAC0_SFM_R0_CMEM_DATA__VALUE___S                    0
#define   WMAC0_SFM_R0_CMEM_DATA___M             0xFFFFFFFF   
#define   WMAC0_SFM_R0_CMEM_DATA___S                           0

#define WMAC0_SFM_R0_CMEM_DATA_33_32              (0x00AB3878)
#define   WMAC0_SFM_R0_CMEM_DATA_33_32___RWC        QCSR_REG_RW    
#define   WMAC0_SFM_R0_CMEM_DATA_33_32___POR     0x00000000
#define   WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___POR 0x0
#define   WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___M 0x00000003
#define   WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___S               0
#define   WMAC0_SFM_R0_CMEM_DATA_33_32___M       0x00000003   
#define   WMAC0_SFM_R0_CMEM_DATA_33_32___S                     0

#define WMAC0_SFM_R0_LMEM_ADDR                    (0x00AB387C)
#define   WMAC0_SFM_R0_LMEM_ADDR___RWC              QCSR_REG_RW    
#define   WMAC0_SFM_R0_LMEM_ADDR___POR           0x00000000
#define   WMAC0_SFM_R0_LMEM_ADDR__VALUE___POR    0x000
#define   WMAC0_SFM_R0_LMEM_ADDR__VALUE___M      0x000003FF
#define   WMAC0_SFM_R0_LMEM_ADDR__VALUE___S                    0
#define   WMAC0_SFM_R0_LMEM_ADDR___M             0x000003FF   
#define   WMAC0_SFM_R0_LMEM_ADDR___S                           0

#define WMAC0_SFM_R0_LMEM_DATA                    (0x00AB3880)
#define   WMAC0_SFM_R0_LMEM_DATA___RWC              QCSR_REG_RW    
#define   WMAC0_SFM_R0_LMEM_DATA___POR           0x00000000
#define   WMAC0_SFM_R0_LMEM_DATA__VALUE___POR    0x00000
#define   WMAC0_SFM_R0_LMEM_DATA__VALUE___M      0x000FFFFF
#define   WMAC0_SFM_R0_LMEM_DATA__VALUE___S                    0
#define   WMAC0_SFM_R0_LMEM_DATA___M             0x000FFFFF   
#define   WMAC0_SFM_R0_LMEM_DATA___S                           0

#define WMAC0_SFM_R0_RRI_START_ADDR               (0x00AB3884)
#define   WMAC0_SFM_R0_RRI_START_ADDR___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_START_ADDR___POR      0x00000000
#define   WMAC0_SFM_R0_RRI_START_ADDR__VALUE___POR 0x0000
#define   WMAC0_SFM_R0_RRI_START_ADDR__VALUE___M 0x0000FFFF
#define   WMAC0_SFM_R0_RRI_START_ADDR__VALUE___S               0
#define   WMAC0_SFM_R0_RRI_START_ADDR___M        0x0000FFFF   
#define   WMAC0_SFM_R0_RRI_START_ADDR___S                      0

#define WMAC0_SFM_R0_RRI_ACCESS_CTRL              (0x00AB3888)
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL___RWC        QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL___POR     0x00000001
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___POR 0x1
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___M 0x00000001
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___S               0
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL___M       0x00000001   
#define   WMAC0_SFM_R0_RRI_ACCESS_CTRL___S                     0

#define WMAC0_SFM_R0_SW_ACCESS_CTRL               (0x00AB388C)
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL___POR      0xFFFF0000
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___POR 0xFFFF
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___POR 0x0000
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___POR 0x0
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___M  0xFFFF0000
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___S               16
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___M  0x0000FFFE
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___S                1
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___M 0x00000001
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___S               0
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL___M        0xFFFFFFFF   
#define   WMAC0_SFM_R0_SW_ACCESS_CTRL___S                      0

#define WMAC0_SFM_R0_CLK_GATE_DISABLE             (0x00AB3890)
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE___POR    0x80000000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x1
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___POR 0x00
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___POR 0x0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S              31
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___M 0x7F800000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___S              23
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___M 0x00400000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___S              22
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___M 0x00200000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___S              21
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___M 0x00100000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___S              20
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___M 0x00080000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___S              19
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___M 0x00040000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___S              18
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___M 0x00020000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___S              17
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___M 0x00010000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___S              16
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___M 0x00008000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___S              15
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___M 0x00004000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___S              14
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___M 0x00002000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___S              13
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___M 0x00001000
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___S              12
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___M 0x00000800
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___S              11
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___M 0x00000400
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___S              10
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___M 0x00000200
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___S               9
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___M 0x00000100
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___S               8
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___M 0x00000080
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___S               7
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___M 0x00000040
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___S               6
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___M 0x00000020
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___S               5
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___M 0x00000010
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___S               4
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___M 0x00000008
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___S               3
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___M 0x00000004
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___S               2
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___M 0x00000002
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___S               1
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___M 0x00000001
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___S               0
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE___M      0xFFFFFFFF   
#define   WMAC0_SFM_R0_CLK_GATE_DISABLE___S                    0

#define WMAC0_SFM_R0_RRI_MODE                     (0x00AB3894)
#define   WMAC0_SFM_R0_RRI_MODE___RWC               QCSR_REG_RW    
#define   WMAC0_SFM_R0_RRI_MODE___POR            0x00000001
#define   WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___POR 0x0
#define   WMAC0_SFM_R0_RRI_MODE__ENABLE___POR    0x1
#define   WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___M 0x00000002
#define   WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___S               1
#define   WMAC0_SFM_R0_RRI_MODE__ENABLE___M      0x00000001
#define   WMAC0_SFM_R0_RRI_MODE__ENABLE___S                    0
#define   WMAC0_SFM_R0_RRI_MODE___M              0x00000003   
#define   WMAC0_SFM_R0_RRI_MODE___S                            0

#define WMAC0_SFM_R1_WATCHDOG                     (0x00AB4000)
#define   WMAC0_SFM_R1_WATCHDOG___RWC               QCSR_REG_RW    
#define   WMAC0_SFM_R1_WATCHDOG___POR            0x0000FFFF
#define   WMAC0_SFM_R1_WATCHDOG__STATUS___POR    0x0000
#define   WMAC0_SFM_R1_WATCHDOG__LIMIT___POR     0xFFFF
#define   WMAC0_SFM_R1_WATCHDOG__STATUS___M      0xFFFF0000
#define   WMAC0_SFM_R1_WATCHDOG__STATUS___S                   16
#define   WMAC0_SFM_R1_WATCHDOG__LIMIT___M       0x0000FFFF
#define   WMAC0_SFM_R1_WATCHDOG__LIMIT___S                     0
#define   WMAC0_SFM_R1_WATCHDOG___M              0xFFFFFFFF   
#define   WMAC0_SFM_R1_WATCHDOG___S                            0

#define WMAC0_SFM_R1_EVENTMASK_IX_0               (0x00AB4004)
#define   WMAC0_SFM_R1_EVENTMASK_IX_0___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R1_EVENTMASK_IX_0___POR      0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___M  0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___S                0
#define   WMAC0_SFM_R1_EVENTMASK_IX_0___M        0xFFFFFFFF   
#define   WMAC0_SFM_R1_EVENTMASK_IX_0___S                      0

#define WMAC0_SFM_R1_EVENTMASK_IX_1               (0x00AB4008)
#define   WMAC0_SFM_R1_EVENTMASK_IX_1___RWC         QCSR_REG_RW    
#define   WMAC0_SFM_R1_EVENTMASK_IX_1___POR      0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___M  0xFFFFFFFF
#define   WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___S                0
#define   WMAC0_SFM_R1_EVENTMASK_IX_1___M        0xFFFFFFFF   
#define   WMAC0_SFM_R1_EVENTMASK_IX_1___S                      0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0             (0x00AB400C)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX0___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1             (0x00AB4010)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX1___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2             (0x00AB4014)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX2___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3             (0x00AB4018)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX3___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4             (0x00AB401C)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX4___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5             (0x00AB4020)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX5___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6             (0x00AB4024)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX6___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7             (0x00AB4028)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX7___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8             (0x00AB402C)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX8___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9             (0x00AB4030)
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9___RWC       QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9___M      0x0000001F   
#define   WMAC0_SFM_R1_TESTBUS_CTRL_IX9___S                    0

#define WMAC0_SFM_R1_TESTBUS_CTRL                 (0x00AB4034)
#define   WMAC0_SFM_R1_TESTBUS_CTRL___RWC           QCSR_REG_RW    
#define   WMAC0_SFM_R1_TESTBUS_CTRL___POR        0x00000000
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___POR 0x0000
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___POR 0x0
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___POR 0x0
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___M 0xFFFE0000
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___S              17
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___M 0x0001C000
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___S              14
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___M 0x00003C00
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___S              10
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___M 0x000003E0
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___S               5
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___M 0x0000001F
#define   WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___S               0
#define   WMAC0_SFM_R1_TESTBUS_CTRL___M          0xFFFFFFFF   
#define   WMAC0_SFM_R1_TESTBUS_CTRL___S                        0

#define WMAC0_SFM_R1_TESTBUS_OUT_LOW              (0x00AB4038)
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW___RWC        QCSR_REG_RO    
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW___POR     0x00000000
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___POR 0x00000000
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___M 0xFFFFFFFF
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___S               0
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW___M       0xFFFFFFFF   
#define   WMAC0_SFM_R1_TESTBUS_OUT_LOW___S                     0

#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH             (0x00AB403C)
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH___RWC       QCSR_REG_RO    
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH___POR    0x00000000
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___POR 0x00
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___S               0
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH___M      0x000000FF   
#define   WMAC0_SFM_R1_TESTBUS_OUT_HIGH___S                    0

#define WMAC0_SFM_R1_SETUP_DEBUG                  (0x00AB4040)
#define   WMAC0_SFM_R1_SETUP_DEBUG___RWC            QCSR_REG_RO    
#define   WMAC0_SFM_R1_SETUP_DEBUG___POR         0x00000000
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___POR 0x00
#define   WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___POR 0x00
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___POR 0x0
#define   WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___POR 0x0
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___M 0x0003FC00
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___S              10
#define   WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___M 0x000003FC
#define   WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___S               2
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___M 0x00000002
#define   WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___S               1
#define   WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___M 0x00000001
#define   WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___S               0
#define   WMAC0_SFM_R1_SETUP_DEBUG___M           0x0003FFFF   
#define   WMAC0_SFM_R1_SETUP_DEBUG___S                         0

#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n(n) (0x00AB4044+0x4*(n))
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_nMIN 0    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_nMAX 9    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_ELEM 10   
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___POR  0x00000000
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___POR 0x00
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___S               0
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___M    0x000000FF   
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___S                  0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_0           (0x00AB4044)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_0___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_0__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_0__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_1           (0x00AB4048)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_1___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_1__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_1__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_2           (0x00AB404C)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_2___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_2__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_2__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_3           (0x00AB4050)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_3___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_3__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_3__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_4           (0x00AB4054)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_4___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_4__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_4__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_5           (0x00AB4058)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_5___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_5__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_5__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_6           (0x00AB405C)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_6___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_6__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_6__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_7           (0x00AB4060)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_7___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_7__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_7__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_8           (0x00AB4064)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_8___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_8__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_8__VALUE___S               0
#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_9           (0x00AB4068)
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_9___RWC     QCSR_REG_RO    
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_9__VALUE___M 0x000000FF
#define   WMAC0_SFM_R1_FLUSH_FSM_STATUS_9__VALUE___S               0

#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n(n) (0x00AB406C+0x4*(n))
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_nMIN 0    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_nMAX 9    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_ELEM 10   
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___POR 0x00000000
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___POR 0x0000
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___S               0
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___M 0x00001FFF   
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0 (0x00AB406C)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1 (0x00AB4070)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2 (0x00AB4074)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3 (0x00AB4078)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4 (0x00AB407C)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5 (0x00AB4080)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6 (0x00AB4084)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7 (0x00AB4088)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8 (0x00AB408C)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8__VALUE___S               0
#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9 (0x00AB4090)
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9__VALUE___M 0x00001FFF
#define   WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS           (0x00AB4094)
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS___RWC     QCSR_REG_RW    
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS___POR  0x00000000
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___POR 0x00
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___POR 0x00
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___M 0xFC000000
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___S              26
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___M 0x03FF0000
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___S              16
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___M 0x0000FC00
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___S              10
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___S               0
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS___M    0xFFFFFFFF   
#define   WMAC0_SFM_R1_WR_RD_ERROR_STATUS___S                  0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n(n) (0x00AB4098+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_nMAX 2    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_ELEM 3    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0       (0x00AB4098)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1       (0x00AB409C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2       (0x00AB40A0)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1         (0x00AB4134)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___RWC   QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___M  0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___S                0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n(n) (0x00AB4138+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_nMAX 2    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_ELEM 3    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0       (0x00AB4138)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1       (0x00AB413C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2       (0x00AB4140)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n(n) (0x00AB41CC+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_nMAX 2    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_ELEM 3    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0       (0x00AB41CC)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1       (0x00AB41D0)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2       (0x00AB41D4)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n(n) (0x00AB41D8+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_nMAX 25   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_ELEM 26   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0       (0x00AB41D8)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1       (0x00AB41DC)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2       (0x00AB41E0)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3       (0x00AB41E4)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4       (0x00AB41E8)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5       (0x00AB41EC)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6       (0x00AB41F0)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7       (0x00AB41F4)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8       (0x00AB41F8)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9       (0x00AB41FC)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10      (0x00AB4200)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11      (0x00AB4204)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12      (0x00AB4208)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13      (0x00AB420C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14      (0x00AB4210)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15      (0x00AB4214)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16      (0x00AB4218)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17      (0x00AB421C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18      (0x00AB4220)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19      (0x00AB4224)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20      (0x00AB4228)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21      (0x00AB422C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22      (0x00AB4230)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23      (0x00AB4234)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24      (0x00AB4238)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25      (0x00AB423C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n(n) (0x00AB4244+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_nMAX 3    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_ELEM 4    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0       (0x00AB4244)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1       (0x00AB4248)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2       (0x00AB424C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3       (0x00AB4250)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n(n) (0x00AB42D8+0x4*(n))
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_nMIN 0    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_nMAX 2    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_ELEM 3    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___M 0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0       (0x00AB42D8)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1       (0x00AB42DC)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1__VALUE___S               0
#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2       (0x00AB42E0)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2__VALUE___S               0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7         (0x00AB436C)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___RWC   QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___M  0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___S                0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8         (0x00AB4370)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___RWC   QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___M  0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___S                0

#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9         (0x00AB4404)
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___RWC   QCSR_REG_RO    
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___POR 0x00000000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___POR 0x000
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___M 0x000003FF
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___S               0
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___M  0x000003FF   
#define   WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___S                0

#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS      (0x00AB4408)
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___POR 0x00000000
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___POR 0x00
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___M 0x0000003F
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___S               0
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___M 0x0000003F   
#define   WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___S               0

#define WMAC0_SFM_R1_MEM_EMPTY                    (0x00AB440C)
#define   WMAC0_SFM_R1_MEM_EMPTY___RWC              QCSR_REG_RO    
#define   WMAC0_SFM_R1_MEM_EMPTY___POR           0x000007FF
#define   WMAC0_SFM_R1_MEM_EMPTY__TOTAL___POR    0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___POR  0x1
#define   WMAC0_SFM_R1_MEM_EMPTY__TOTAL___M      0x00000400
#define   WMAC0_SFM_R1_MEM_EMPTY__TOTAL___S                   10
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___M    0x00000200
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___S                  9
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___M    0x00000100
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___S                  8
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___M    0x00000080
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___S                  7
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___M    0x00000040
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___S                  6
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___M    0x00000020
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___S                  5
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___M    0x00000010
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___S                  4
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___M    0x00000008
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___S                  3
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___M    0x00000004
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___S                  2
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___M    0x00000002
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___S                  1
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___M    0x00000001
#define   WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___S                  0
#define   WMAC0_SFM_R1_MEM_EMPTY___M             0x000007FF   
#define   WMAC0_SFM_R1_MEM_EMPTY___S                           0

#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n(n) (0x00AB4410+0x4*(n))
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_nMIN 0    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_nMAX 9    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_ELEM 10   
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___POR 0x000000FF
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___POR 0xF
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___POR 0xF
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___S               0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___M 0x000000FF   
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0     (0x00AB4410)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1     (0x00AB4414)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2     (0x00AB4418)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3     (0x00AB441C)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4     (0x00AB4420)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5     (0x00AB4424)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6     (0x00AB4428)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7     (0x00AB442C)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8     (0x00AB4430)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9     (0x00AB4434)
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9___RWC QCSR_REG_RW    
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__RD___M 0x000000F0
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__RD___S               4
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__WR___M 0x0000000F
#define   WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__WR___S               0

#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n(n) (0x00AB4438+0x4*(n))
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_nMIN 0    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_nMAX 9    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_ELEM 10   
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___POR 0x00000000
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___POR 0x0
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___POR 0x0
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___S               0
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___M 0x00000003   
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0       (0x00AB4438)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1       (0x00AB443C)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2       (0x00AB4440)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3       (0x00AB4444)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4       (0x00AB4448)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5       (0x00AB444C)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6       (0x00AB4450)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7       (0x00AB4454)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8       (0x00AB4458)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__WR___S               0
#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9       (0x00AB445C)
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9___RWC QCSR_REG_RO    
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__RD___M 0x00000002
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__RD___S               1
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__WR___M 0x00000001
#define   WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__WR___S               0


#define DBG                         (0x00B90000)

#define DBG_CSR_ROM_WORD                          (0x00B90000)
#define   DBG_CSR_ROM_WORD___RWC                    QCSR_REG_RO    
#define   DBG_CSR_ROM_WORD___POR                 0x00001007
#define   DBG_CSR_ROM_WORD__ADDR_OFFSET___POR    0x00001
#define   DBG_CSR_ROM_WORD__PWRDMNID___POR       0x00
#define   DBG_CSR_ROM_WORD__PWRDMNID_VAL___POR   0x1
#define   DBG_CSR_ROM_WORD__FORMAT___POR         0x1
#define   DBG_CSR_ROM_WORD__PRESENT___POR        0x1
#define   DBG_CSR_ROM_WORD__ADDR_OFFSET___M      0xFFFFF000
#define   DBG_CSR_ROM_WORD__ADDR_OFFSET___S                   12
#define   DBG_CSR_ROM_WORD__PWRDMNID___M         0x000001F0
#define   DBG_CSR_ROM_WORD__PWRDMNID___S                       4
#define   DBG_CSR_ROM_WORD__PWRDMNID_VAL___M     0x00000004
#define   DBG_CSR_ROM_WORD__PWRDMNID_VAL___S                   2
#define   DBG_CSR_ROM_WORD__FORMAT___M           0x00000002
#define   DBG_CSR_ROM_WORD__FORMAT___S                         1
#define   DBG_CSR_ROM_WORD__PRESENT___M          0x00000001
#define   DBG_CSR_ROM_WORD__PRESENT___S                        0
#define   DBG_CSR_ROM_WORD___M                   0xFFFFF1F7   
#define   DBG_CSR_ROM_WORD___S                                 0

#define DBG_TSGEN_ROM_WORD                        (0x00B90004)
#define   DBG_TSGEN_ROM_WORD___RWC                  QCSR_REG_RO    
#define   DBG_TSGEN_ROM_WORD___POR               0x00002007
#define   DBG_TSGEN_ROM_WORD__ADDR_OFFSET___POR  0x00002
#define   DBG_TSGEN_ROM_WORD__PWRDMNID___POR     0x00
#define   DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_TSGEN_ROM_WORD__FORMAT___POR       0x1
#define   DBG_TSGEN_ROM_WORD__PRESENT___POR      0x1
#define   DBG_TSGEN_ROM_WORD__ADDR_OFFSET___M    0xFFFFF000
#define   DBG_TSGEN_ROM_WORD__ADDR_OFFSET___S                 12
#define   DBG_TSGEN_ROM_WORD__PWRDMNID___M       0x000001F0
#define   DBG_TSGEN_ROM_WORD__PWRDMNID___S                     4
#define   DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___M   0x00000004
#define   DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___S                 2
#define   DBG_TSGEN_ROM_WORD__FORMAT___M         0x00000002
#define   DBG_TSGEN_ROM_WORD__FORMAT___S                       1
#define   DBG_TSGEN_ROM_WORD__PRESENT___M        0x00000001
#define   DBG_TSGEN_ROM_WORD__PRESENT___S                      0
#define   DBG_TSGEN_ROM_WORD___M                 0xFFFFF1F7   
#define   DBG_TSGEN_ROM_WORD___S                               0

#define DBG_CTI_DBG_ROM_WORD                      (0x00B90008)
#define   DBG_CTI_DBG_ROM_WORD___RWC                QCSR_REG_RO    
#define   DBG_CTI_DBG_ROM_WORD___POR             0x00004007
#define   DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___POR 0x00004
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID___POR   0x00
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_CTI_DBG_ROM_WORD__FORMAT___POR     0x1
#define   DBG_CTI_DBG_ROM_WORD__PRESENT___POR    0x1
#define   DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___M  0xFFFFF000
#define   DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___S               12
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID___M     0x000001F0
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID___S                   4
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_CTI_DBG_ROM_WORD__FORMAT___M       0x00000002
#define   DBG_CTI_DBG_ROM_WORD__FORMAT___S                     1
#define   DBG_CTI_DBG_ROM_WORD__PRESENT___M      0x00000001
#define   DBG_CTI_DBG_ROM_WORD__PRESENT___S                    0
#define   DBG_CTI_DBG_ROM_WORD___M               0xFFFFF1F7   
#define   DBG_CTI_DBG_ROM_WORD___S                             0

#define DBG_CTI_NOC_ROM_WORD                      (0x00B9000C)
#define   DBG_CTI_NOC_ROM_WORD___RWC                QCSR_REG_RO    
#define   DBG_CTI_NOC_ROM_WORD___POR             0x00005007
#define   DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___POR 0x00005
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID___POR   0x00
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_CTI_NOC_ROM_WORD__FORMAT___POR     0x1
#define   DBG_CTI_NOC_ROM_WORD__PRESENT___POR    0x1
#define   DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___M  0xFFFFF000
#define   DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___S               12
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID___M     0x000001F0
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID___S                   4
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_CTI_NOC_ROM_WORD__FORMAT___M       0x00000002
#define   DBG_CTI_NOC_ROM_WORD__FORMAT___S                     1
#define   DBG_CTI_NOC_ROM_WORD__PRESENT___M      0x00000001
#define   DBG_CTI_NOC_ROM_WORD__PRESENT___S                    0
#define   DBG_CTI_NOC_ROM_WORD___M               0xFFFFF1F7   
#define   DBG_CTI_NOC_ROM_WORD___S                             0

#define DBG_CTI_INTR_ROM_WORD                     (0x00B90010)
#define   DBG_CTI_INTR_ROM_WORD___RWC               QCSR_REG_RO    
#define   DBG_CTI_INTR_ROM_WORD___POR            0x00006007
#define   DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___POR 0x00006
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID___POR  0x00
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_CTI_INTR_ROM_WORD__FORMAT___POR    0x1
#define   DBG_CTI_INTR_ROM_WORD__PRESENT___POR   0x1
#define   DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID___M    0x000001F0
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID___S                  4
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_CTI_INTR_ROM_WORD__FORMAT___M      0x00000002
#define   DBG_CTI_INTR_ROM_WORD__FORMAT___S                    1
#define   DBG_CTI_INTR_ROM_WORD__PRESENT___M     0x00000001
#define   DBG_CTI_INTR_ROM_WORD__PRESENT___S                   0
#define   DBG_CTI_INTR_ROM_WORD___M              0xFFFFF1F7   
#define   DBG_CTI_INTR_ROM_WORD___S                            0

#define DBG_TPDM_CSR_ROM_WORD                     (0x00B90014)
#define   DBG_TPDM_CSR_ROM_WORD___RWC               QCSR_REG_RO    
#define   DBG_TPDM_CSR_ROM_WORD___POR            0x00011007
#define   DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___POR 0x00011
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID___POR  0x00
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_TPDM_CSR_ROM_WORD__FORMAT___POR    0x1
#define   DBG_TPDM_CSR_ROM_WORD__PRESENT___POR   0x1
#define   DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID___M    0x000001F0
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID___S                  4
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_TPDM_CSR_ROM_WORD__FORMAT___M      0x00000002
#define   DBG_TPDM_CSR_ROM_WORD__FORMAT___S                    1
#define   DBG_TPDM_CSR_ROM_WORD__PRESENT___M     0x00000001
#define   DBG_TPDM_CSR_ROM_WORD__PRESENT___S                   0
#define   DBG_TPDM_CSR_ROM_WORD___M              0xFFFFF1F7   
#define   DBG_TPDM_CSR_ROM_WORD___S                            0

#define DBG_TPDA_CSR_ROM_WORD                     (0x00B90018)
#define   DBG_TPDA_CSR_ROM_WORD___RWC               QCSR_REG_RO    
#define   DBG_TPDA_CSR_ROM_WORD___POR            0x00012007
#define   DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___POR 0x00012
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID___POR  0x00
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_TPDA_CSR_ROM_WORD__FORMAT___POR    0x1
#define   DBG_TPDA_CSR_ROM_WORD__PRESENT___POR   0x1
#define   DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID___M    0x000001F0
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID___S                  4
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_TPDA_CSR_ROM_WORD__FORMAT___M      0x00000002
#define   DBG_TPDA_CSR_ROM_WORD__FORMAT___S                    1
#define   DBG_TPDA_CSR_ROM_WORD__PRESENT___M     0x00000001
#define   DBG_TPDA_CSR_ROM_WORD__PRESENT___S                   0
#define   DBG_TPDA_CSR_ROM_WORD___M              0xFFFFF1F7   
#define   DBG_TPDA_CSR_ROM_WORD___S                            0

#define DBG_FUN_ROM_WORD                          (0x00B9001C)
#define   DBG_FUN_ROM_WORD___RWC                    QCSR_REG_RO    
#define   DBG_FUN_ROM_WORD___POR                 0x00013007
#define   DBG_FUN_ROM_WORD__ADDR_OFFSET___POR    0x00013
#define   DBG_FUN_ROM_WORD__PWRDMNID___POR       0x00
#define   DBG_FUN_ROM_WORD__PWRDMNID_VAL___POR   0x1
#define   DBG_FUN_ROM_WORD__FORMAT___POR         0x1
#define   DBG_FUN_ROM_WORD__PRESENT___POR        0x1
#define   DBG_FUN_ROM_WORD__ADDR_OFFSET___M      0xFFFFF000
#define   DBG_FUN_ROM_WORD__ADDR_OFFSET___S                   12
#define   DBG_FUN_ROM_WORD__PWRDMNID___M         0x000001F0
#define   DBG_FUN_ROM_WORD__PWRDMNID___S                       4
#define   DBG_FUN_ROM_WORD__PWRDMNID_VAL___M     0x00000004
#define   DBG_FUN_ROM_WORD__PWRDMNID_VAL___S                   2
#define   DBG_FUN_ROM_WORD__FORMAT___M           0x00000002
#define   DBG_FUN_ROM_WORD__FORMAT___S                         1
#define   DBG_FUN_ROM_WORD__PRESENT___M          0x00000001
#define   DBG_FUN_ROM_WORD__PRESENT___S                        0
#define   DBG_FUN_ROM_WORD___M                   0xFFFFF1F7   
#define   DBG_FUN_ROM_WORD___S                                 0

#define DBG_ETBETF_ROM_WORD                       (0x00B90020)
#define   DBG_ETBETF_ROM_WORD___RWC                 QCSR_REG_RO    
#define   DBG_ETBETF_ROM_WORD___POR              0x00014007
#define   DBG_ETBETF_ROM_WORD__ADDR_OFFSET___POR 0x00014
#define   DBG_ETBETF_ROM_WORD__PWRDMNID___POR    0x00
#define   DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_ETBETF_ROM_WORD__FORMAT___POR      0x1
#define   DBG_ETBETF_ROM_WORD__PRESENT___POR     0x1
#define   DBG_ETBETF_ROM_WORD__ADDR_OFFSET___M   0xFFFFF000
#define   DBG_ETBETF_ROM_WORD__ADDR_OFFSET___S                12
#define   DBG_ETBETF_ROM_WORD__PWRDMNID___M      0x000001F0
#define   DBG_ETBETF_ROM_WORD__PWRDMNID___S                    4
#define   DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___M  0x00000004
#define   DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___S                2
#define   DBG_ETBETF_ROM_WORD__FORMAT___M        0x00000002
#define   DBG_ETBETF_ROM_WORD__FORMAT___S                      1
#define   DBG_ETBETF_ROM_WORD__PRESENT___M       0x00000001
#define   DBG_ETBETF_ROM_WORD__PRESENT___S                     0
#define   DBG_ETBETF_ROM_WORD___M                0xFFFFF1F7   
#define   DBG_ETBETF_ROM_WORD___S                              0

#define DBG_OUTFUN_ROM_WORD                       (0x00B90024)
#define   DBG_OUTFUN_ROM_WORD___RWC                 QCSR_REG_RO    
#define   DBG_OUTFUN_ROM_WORD___POR              0x00016007
#define   DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___POR 0x00016
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID___POR    0x00
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_OUTFUN_ROM_WORD__FORMAT___POR      0x1
#define   DBG_OUTFUN_ROM_WORD__PRESENT___POR     0x1
#define   DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___M   0xFFFFF000
#define   DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___S                12
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID___M      0x000001F0
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID___S                    4
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___M  0x00000004
#define   DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___S                2
#define   DBG_OUTFUN_ROM_WORD__FORMAT___M        0x00000002
#define   DBG_OUTFUN_ROM_WORD__FORMAT___S                      1
#define   DBG_OUTFUN_ROM_WORD__PRESENT___M       0x00000001
#define   DBG_OUTFUN_ROM_WORD__PRESENT___S                     0
#define   DBG_OUTFUN_ROM_WORD___M                0xFFFFF1F7   
#define   DBG_OUTFUN_ROM_WORD___S                              0

#define DBG_GPWRREQ_ROM_WORD                      (0x00B90028)
#define   DBG_GPWRREQ_ROM_WORD___RWC                QCSR_REG_RO    
#define   DBG_GPWRREQ_ROM_WORD___POR             0x0007E047
#define   DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___POR 0x0007E
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID___POR   0x04
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_GPWRREQ_ROM_WORD__FORMAT___POR     0x1
#define   DBG_GPWRREQ_ROM_WORD__PRESENT___POR    0x1
#define   DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___M  0xFFFFF000
#define   DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___S               12
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID___M     0x000001F0
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID___S                   4
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_GPWRREQ_ROM_WORD__FORMAT___M       0x00000002
#define   DBG_GPWRREQ_ROM_WORD__FORMAT___S                     1
#define   DBG_GPWRREQ_ROM_WORD__PRESENT___M      0x00000001
#define   DBG_GPWRREQ_ROM_WORD__PRESENT___S                    0
#define   DBG_GPWRREQ_ROM_WORD___M               0xFFFFF1F7   
#define   DBG_GPWRREQ_ROM_WORD___S                             0

#define DBG_PHYA_FUN_ROM_WORD                     (0x00B9002C)
#define   DBG_PHYA_FUN_ROM_WORD___RWC               QCSR_REG_RO    
#define   DBG_PHYA_FUN_ROM_WORD___POR            0x00054027
#define   DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___POR 0x54
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID___POR  0x02
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_FUN_ROM_WORD__FORMAT___POR    0x1
#define   DBG_PHYA_FUN_ROM_WORD__PRESENT___POR   0x1
#define   DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID___M    0x000001F0
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID___S                  4
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_FUN_ROM_WORD__FORMAT___M      0x00000002
#define   DBG_PHYA_FUN_ROM_WORD__FORMAT___S                    1
#define   DBG_PHYA_FUN_ROM_WORD__PRESENT___M     0x00000001
#define   DBG_PHYA_FUN_ROM_WORD__PRESENT___S                   0
#define   DBG_PHYA_FUN_ROM_WORD___M              0xFFFFF1F7   
#define   DBG_PHYA_FUN_ROM_WORD___S                            0

#define DBG_PHYA_CTI_ROM_WORD                     (0x00B90030)
#define   DBG_PHYA_CTI_ROM_WORD___RWC               QCSR_REG_RO    
#define   DBG_PHYA_CTI_ROM_WORD___POR            0x00055027
#define   DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___POR 0x55
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID___POR  0x02
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_CTI_ROM_WORD__FORMAT___POR    0x1
#define   DBG_PHYA_CTI_ROM_WORD__PRESENT___POR   0x1
#define   DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID___M    0x000001F0
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID___S                  4
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_CTI_ROM_WORD__FORMAT___M      0x00000002
#define   DBG_PHYA_CTI_ROM_WORD__FORMAT___S                    1
#define   DBG_PHYA_CTI_ROM_WORD__PRESENT___M     0x00000001
#define   DBG_PHYA_CTI_ROM_WORD__PRESENT___S                   0
#define   DBG_PHYA_CTI_ROM_WORD___M              0xFFFFF1F7   
#define   DBG_PHYA_CTI_ROM_WORD___S                            0

#define DBG_PHYA_M3_ITM_ROM_WORD                  (0x00B90034)
#define   DBG_PHYA_M3_ITM_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_ITM_ROM_WORD___POR         0x00058027
#define   DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___POR 0x58
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_ITM_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_ITM_ROM_WORD___S                         0

#define DBG_PHYA_M3_DWT_ROM_WORD                  (0x00B90038)
#define   DBG_PHYA_M3_DWT_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_DWT_ROM_WORD___POR         0x00059027
#define   DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___POR 0x59
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_DWT_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_DWT_ROM_WORD___S                         0

#define DBG_PHYA_M3_FPB_ROM_WORD                  (0x00B9003C)
#define   DBG_PHYA_M3_FPB_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_FPB_ROM_WORD___POR         0x0005A027
#define   DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___POR 0x5A
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_FPB_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_FPB_ROM_WORD___S                         0

#define DBG_PHYA_M3_SCS_ROM_WORD                  (0x00B90040)
#define   DBG_PHYA_M3_SCS_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_SCS_ROM_WORD___POR         0x0005B027
#define   DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___POR 0x5B
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_SCS_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_SCS_ROM_WORD___S                         0

#define DBG_PHYA_M3_ETM_ROM_WORD                  (0x00B90044)
#define   DBG_PHYA_M3_ETM_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_ETM_ROM_WORD___POR         0x0005C027
#define   DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___POR 0x5C
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_ETM_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_ETM_ROM_WORD___S                         0

#define DBG_PHYA_M3_CTI_ROM_WORD                  (0x00B90048)
#define   DBG_PHYA_M3_CTI_ROM_WORD___RWC            QCSR_REG_RO    
#define   DBG_PHYA_M3_CTI_ROM_WORD___POR         0x0005D027
#define   DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___POR 0x5D
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___POR 0x02
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___POR 0x1
#define   DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___POR 0x1
#define   DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___POR 0x1
#define   DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000
#define   DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___S              12
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___M 0x000001F0
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___S               4
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___M 0x00000004
#define   DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___S               2
#define   DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___M   0x00000002
#define   DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___S                 1
#define   DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___M  0x00000001
#define   DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___S                0
#define   DBG_PHYA_M3_CTI_ROM_WORD___M           0xFFFFF1F7   
#define   DBG_PHYA_M3_CTI_ROM_WORD___S                         0

#define DBG_DAPROM_TABLE_END                      (0x00B90080)
#define   DBG_DAPROM_TABLE_END___RWC                QCSR_REG_RO    
#define   DBG_DAPROM_TABLE_END___POR             0x00000000
#define   DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___POR 0x00000000
#define   DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___M 0xFFFFFFFF
#define   DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___S               0
#define   DBG_DAPROM_TABLE_END___M               0xFFFFFFFF   
#define   DBG_DAPROM_TABLE_END___S                             0

#define DBG_DAPROM_MEMTYPE                        (0x00B90FCC)
#define   DBG_DAPROM_MEMTYPE___RWC                  QCSR_REG_RO    
#define   DBG_DAPROM_MEMTYPE___POR               0x00000001
#define   DBG_DAPROM_MEMTYPE__SYSMEM___POR       0x1
#define   DBG_DAPROM_MEMTYPE__SYSMEM___M         0x00000001
#define   DBG_DAPROM_MEMTYPE__SYSMEM___S                       0
#define   DBG_DAPROM_MEMTYPE___M                 0x00000001   
#define   DBG_DAPROM_MEMTYPE___S                               0

#define DBG_DAPROM_PERIPHERAL_ID4                 (0x00B90FD0)
#define   DBG_DAPROM_PERIPHERAL_ID4___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID4___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID4__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID4__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID4__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___S               4
#define   DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___M 0x0000000F
#define   DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___S               0
#define   DBG_DAPROM_PERIPHERAL_ID4___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID4___S                        0

#define DBG_DAPROM_PERIPHERAL_ID5                 (0x00B90FD4)
#define   DBG_DAPROM_PERIPHERAL_ID5___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID5___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID5__RFU___POR   0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID5__SBZ___POR   0x0
#define   DBG_DAPROM_PERIPHERAL_ID5__RFU___M     0xFFFFFFFE
#define   DBG_DAPROM_PERIPHERAL_ID5__RFU___S                   1
#define   DBG_DAPROM_PERIPHERAL_ID5__SBZ___M     0x00000001
#define   DBG_DAPROM_PERIPHERAL_ID5__SBZ___S                   0
#define   DBG_DAPROM_PERIPHERAL_ID5___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID5___S                        0

#define DBG_DAPROM_PERIPHERAL_ID6                 (0x00B90FD8)
#define   DBG_DAPROM_PERIPHERAL_ID6___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID6___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID6__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID6__SBZ___POR   0x00
#define   DBG_DAPROM_PERIPHERAL_ID6__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID6__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID6__SBZ___M     0x000000FF
#define   DBG_DAPROM_PERIPHERAL_ID6__SBZ___S                   0
#define   DBG_DAPROM_PERIPHERAL_ID6___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID6___S                        0

#define DBG_DAPROM_PERIPHERAL_ID7                 (0x00B90FDC)
#define   DBG_DAPROM_PERIPHERAL_ID7___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID7___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID7__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID7__SBZ___POR   0x00
#define   DBG_DAPROM_PERIPHERAL_ID7__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID7__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID7__SBZ___M     0x000000FF
#define   DBG_DAPROM_PERIPHERAL_ID7__SBZ___S                   0
#define   DBG_DAPROM_PERIPHERAL_ID7___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID7___S                        0

#define DBG_DAPROM_PERIPHERAL_ID0                 (0x00B90FE0)
#define   DBG_DAPROM_PERIPHERAL_ID0___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID0___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID0__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID0__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID0__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___M 0x000000FF
#define   DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___S               0
#define   DBG_DAPROM_PERIPHERAL_ID0___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID0___S                        0

#define DBG_DAPROM_PERIPHERAL_ID1                 (0x00B90FE4)
#define   DBG_DAPROM_PERIPHERAL_ID1___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID1___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID1__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID1__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID1__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___M 0x000000F0
#define   DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___S               4
#define   DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___M 0x0000000F
#define   DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___S               0
#define   DBG_DAPROM_PERIPHERAL_ID1___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID1___S                        0

#define DBG_DAPROM_PERIPHERAL_ID2                 (0x00B90FE8)
#define   DBG_DAPROM_PERIPHERAL_ID2___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID2___POR        0x0000000F
#define   DBG_DAPROM_PERIPHERAL_ID2__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___POR 0x1
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___POR 0x7
#define   DBG_DAPROM_PERIPHERAL_ID2__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID2__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___M 0x000000F0
#define   DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___S               4
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___M 0x00000008
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___S               3
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___M 0x00000007
#define   DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___S               0
#define   DBG_DAPROM_PERIPHERAL_ID2___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID2___S                        0

#define DBG_DAPROM_PERIPHERAL_ID3                 (0x00B90FEC)
#define   DBG_DAPROM_PERIPHERAL_ID3___RWC           QCSR_REG_RO    
#define   DBG_DAPROM_PERIPHERAL_ID3___POR        0x00000000
#define   DBG_DAPROM_PERIPHERAL_ID3__RFU___POR   0x000000
#define   DBG_DAPROM_PERIPHERAL_ID3__REV_AND___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___POR 0x0
#define   DBG_DAPROM_PERIPHERAL_ID3__RFU___M     0xFFFFFF00
#define   DBG_DAPROM_PERIPHERAL_ID3__RFU___S                   8
#define   DBG_DAPROM_PERIPHERAL_ID3__REV_AND___M 0x000000F0
#define   DBG_DAPROM_PERIPHERAL_ID3__REV_AND___S               4
#define   DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___M 0x0000000F
#define   DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___S               0
#define   DBG_DAPROM_PERIPHERAL_ID3___M          0xFFFFFFFF   
#define   DBG_DAPROM_PERIPHERAL_ID3___S                        0

#define DBG_DAPROM_COMPONENT_ID0                  (0x00B90FF0)
#define   DBG_DAPROM_COMPONENT_ID0___RWC            QCSR_REG_RO    
#define   DBG_DAPROM_COMPONENT_ID0___POR         0x0000000D
#define   DBG_DAPROM_COMPONENT_ID0__RFU___POR    0x000000
#define   DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___POR 0x0D
#define   DBG_DAPROM_COMPONENT_ID0__RFU___M      0xFFFFFF00
#define   DBG_DAPROM_COMPONENT_ID0__RFU___S                    8
#define   DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___M 0x000000FF
#define   DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___S               0
#define   DBG_DAPROM_COMPONENT_ID0___M           0xFFFFFFFF   
#define   DBG_DAPROM_COMPONENT_ID0___S                         0

#define DBG_DAPROM_COMPONENT_ID1                  (0x00B90FF4)
#define   DBG_DAPROM_COMPONENT_ID1___RWC            QCSR_REG_RO    
#define   DBG_DAPROM_COMPONENT_ID1___POR         0x00000010
#define   DBG_DAPROM_COMPONENT_ID1__RFU___POR    0x000000
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___POR 0x1
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___POR 0x0
#define   DBG_DAPROM_COMPONENT_ID1__RFU___M      0xFFFFFF00
#define   DBG_DAPROM_COMPONENT_ID1__RFU___S                    8
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___S               4
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___M 0x0000000F
#define   DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___S               0
#define   DBG_DAPROM_COMPONENT_ID1___M           0xFFFFFFFF   
#define   DBG_DAPROM_COMPONENT_ID1___S                         0

#define DBG_DAPROM_COMPONENT_ID2                  (0x00B90FF8)
#define   DBG_DAPROM_COMPONENT_ID2___RWC            QCSR_REG_RO    
#define   DBG_DAPROM_COMPONENT_ID2___POR         0x00000005
#define   DBG_DAPROM_COMPONENT_ID2__RFU___POR    0x000000
#define   DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___POR 0x05
#define   DBG_DAPROM_COMPONENT_ID2__RFU___M      0xFFFFFF00
#define   DBG_DAPROM_COMPONENT_ID2__RFU___S                    8
#define   DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___S               0
#define   DBG_DAPROM_COMPONENT_ID2___M           0xFFFFFFFF   
#define   DBG_DAPROM_COMPONENT_ID2___S                         0

#define DBG_DAPROM_COMPONENT_ID3                  (0x00B90FFC)
#define   DBG_DAPROM_COMPONENT_ID3___RWC            QCSR_REG_RO    
#define   DBG_DAPROM_COMPONENT_ID3___POR         0x000000B1
#define   DBG_DAPROM_COMPONENT_ID3__RFU___POR    0x000000
#define   DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_DAPROM_COMPONENT_ID3__RFU___M      0xFFFFFF00
#define   DBG_DAPROM_COMPONENT_ID3__RFU___S                    8
#define   DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___S               0
#define   DBG_DAPROM_COMPONENT_ID3___M           0xFFFFFFFF   
#define   DBG_DAPROM_COMPONENT_ID3___S                         0

#define DBG_CSR_PRESERVEETF                       (0x00B91000)
#define   DBG_CSR_PRESERVEETF___RWC                 QCSR_REG_RO    
#define   DBG_CSR_PRESERVEETF___POR              0x00000000
#define   DBG_CSR_PRESERVEETF__STS_MEMERR___POR  0x0
#define   DBG_CSR_PRESERVEETF__AFVALIDS___POR    0x0
#define   DBG_CSR_PRESERVEETF__STS_EMPTY___POR   0x0
#define   DBG_CSR_PRESERVEETF__ACQCOMP___POR     0x0
#define   DBG_CSR_PRESERVEETF__STS_TMCREADY___POR 0x0
#define   DBG_CSR_PRESERVEETF__STS_TRIGGERED___POR 0x0
#define   DBG_CSR_PRESERVEETF__FULL___POR        0x0
#define   DBG_CSR_PRESERVEETF__RWP_PRESERVE___POR 0x0000
#define   DBG_CSR_PRESERVEETF__STS_MEMERR___M    0x00400000
#define   DBG_CSR_PRESERVEETF__STS_MEMERR___S                 22
#define   DBG_CSR_PRESERVEETF__AFVALIDS___M      0x00200000
#define   DBG_CSR_PRESERVEETF__AFVALIDS___S                   21
#define   DBG_CSR_PRESERVEETF__STS_EMPTY___M     0x00100000
#define   DBG_CSR_PRESERVEETF__STS_EMPTY___S                  20
#define   DBG_CSR_PRESERVEETF__ACQCOMP___M       0x00080000
#define   DBG_CSR_PRESERVEETF__ACQCOMP___S                    19
#define   DBG_CSR_PRESERVEETF__STS_TMCREADY___M  0x00040000
#define   DBG_CSR_PRESERVEETF__STS_TMCREADY___S               18
#define   DBG_CSR_PRESERVEETF__STS_TRIGGERED___M 0x00020000
#define   DBG_CSR_PRESERVEETF__STS_TRIGGERED___S              17
#define   DBG_CSR_PRESERVEETF__FULL___M          0x00010000
#define   DBG_CSR_PRESERVEETF__FULL___S                       16
#define   DBG_CSR_PRESERVEETF__RWP_PRESERVE___M  0x0000FFFF
#define   DBG_CSR_PRESERVEETF__RWP_PRESERVE___S                0
#define   DBG_CSR_PRESERVEETF___M                0x007FFFFF   
#define   DBG_CSR_PRESERVEETF___S                              0

#define DBG_CSR_TRC_CFG                           (0x00B91004)
#define   DBG_CSR_TRC_CFG___RWC                     QCSR_REG_RW    
#define   DBG_CSR_TRC_CFG___POR                  0x00000000
#define   DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___POR 0x0
#define   DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___POR 0x0
#define   DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___POR 0x0
#define   DBG_CSR_TRC_CFG__AFV_SW_EN___POR       0x0
#define   DBG_CSR_TRC_CFG__CMB_OWNER___POR       0x0
#define   DBG_CSR_TRC_CFG__MEM_OWNER___POR       0x0
#define   DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___M  0x00000200
#define   DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___S                9
#define   DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN__DISABLED             0x0
#define   DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN__ENABLED             0x1
#define   DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___M 0x00000100
#define   DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___S               8
#define   DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN__DISABLED             0x0
#define   DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN__ENABLED             0x1
#define   DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___M  0x00000080
#define   DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___S                7
#define   DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN__DISABLED             0x0
#define   DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN__ENABLED             0x1
#define   DBG_CSR_TRC_CFG__AFV_SW_EN___M         0x00000040
#define   DBG_CSR_TRC_CFG__AFV_SW_EN___S                       6
#define   DBG_CSR_TRC_CFG__AFV_SW_EN__DISABLED               0x0
#define   DBG_CSR_TRC_CFG__AFV_SW_EN__ENABLED                0x1
#define   DBG_CSR_TRC_CFG__CMB_OWNER___M         0x00000038
#define   DBG_CSR_TRC_CFG__CMB_OWNER___S                       3
#define   DBG_CSR_TRC_CFG__CMB_OWNER__ARB                    0x0
#define   DBG_CSR_TRC_CFG__CMB_OWNER__TRACER                 0x1
#define   DBG_CSR_TRC_CFG__CMB_OWNER__APBMON                 0x3
#define   DBG_CSR_TRC_CFG__CMB_OWNER__SWGEN                  0x5
#define   DBG_CSR_TRC_CFG__CMB_OWNER__DATDUMPR               0x7
#define   DBG_CSR_TRC_CFG__MEM_OWNER___M         0x00000003
#define   DBG_CSR_TRC_CFG__MEM_OWNER___S                       0
#define   DBG_CSR_TRC_CFG__MEM_OWNER__ETB                    0x0
#define   DBG_CSR_TRC_CFG__MEM_OWNER__APB                    0x1
#define   DBG_CSR_TRC_CFG___M                    0x000003FB   
#define   DBG_CSR_TRC_CFG___S                                  0

#define DBG_CSR_TSTMP_CFG                         (0x00B91008)
#define   DBG_CSR_TSTMP_CFG___RWC                   QCSR_REG_RW    
#define   DBG_CSR_TSTMP_CFG___POR                0x00000039
#define   DBG_CSR_TSTMP_CFG__INTP_BYPASS___POR   0x1
#define   DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___POR 0x1
#define   DBG_CSR_TSTMP_CFG__SLP_CORR_EN___POR   0x1
#define   DBG_CSR_TSTMP_CFG__SOURCE___POR        0x1
#define   DBG_CSR_TSTMP_CFG__INTP_BYPASS___M     0x00000020
#define   DBG_CSR_TSTMP_CFG__INTP_BYPASS___S                   5
#define   DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___M 0x00000010
#define   DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___S               4
#define   DBG_CSR_TSTMP_CFG__SLP_CORR_EN___M     0x00000008
#define   DBG_CSR_TSTMP_CFG__SLP_CORR_EN___S                   3
#define   DBG_CSR_TSTMP_CFG__SLP_CORR_EN__NOCORRECTION             0x0
#define   DBG_CSR_TSTMP_CFG__SLP_CORR_EN__CORRECT4TIMEINSLP             0x1
#define   DBG_CSR_TSTMP_CFG__SOURCE___M          0x00000007
#define   DBG_CSR_TSTMP_CFG__SOURCE___S                        0
#define   DBG_CSR_TSTMP_CFG__SOURCE__QDSS                    0x0
#define   DBG_CSR_TSTMP_CFG__SOURCE__QTMR                    0x1
#define   DBG_CSR_TSTMP_CFG__SOURCE__WCSSDBG                 0x2
#define   DBG_CSR_TSTMP_CFG__SOURCE__AUTO_QDSS_WCSSDBG             0x3
#define   DBG_CSR_TSTMP_CFG__SOURCE__AUTO_QTMR_WCSSDBG             0x4
#define   DBG_CSR_TSTMP_CFG___M                  0x0000003F   
#define   DBG_CSR_TSTMP_CFG___S                                0

#define DBG_CSR_QDSS_TS_FREQ                      (0x00B9100C)
#define   DBG_CSR_QDSS_TS_FREQ___RWC                QCSR_REG_RW    
#define   DBG_CSR_QDSS_TS_FREQ___POR             0x00000000
#define   DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___POR 0x00000000
#define   DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___M   0xFFFFFFFF
#define   DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___S                 0
#define   DBG_CSR_QDSS_TS_FREQ___M               0xFFFFFFFF   
#define   DBG_CSR_QDSS_TS_FREQ___S                             0

#define DBG_CSR_QDSS_TSTMP_VAL_LO                 (0x00B91010)
#define   DBG_CSR_QDSS_TSTMP_VAL_LO___RWC           QCSR_REG_RO    
#define   DBG_CSR_QDSS_TSTMP_VAL_LO___POR        0x00000000
#define   DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000
#define   DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF
#define   DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___S               0
#define   DBG_CSR_QDSS_TSTMP_VAL_LO___M          0xFFFFFFFF   
#define   DBG_CSR_QDSS_TSTMP_VAL_LO___S                        0

#define DBG_CSR_QDSS_TSTMP_VAL_HI                 (0x00B91014)
#define   DBG_CSR_QDSS_TSTMP_VAL_HI___RWC           QCSR_REG_RO    
#define   DBG_CSR_QDSS_TSTMP_VAL_HI___POR        0x00000000
#define   DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000
#define   DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF
#define   DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___S               0
#define   DBG_CSR_QDSS_TSTMP_VAL_HI___M          0xFFFFFFFF   
#define   DBG_CSR_QDSS_TSTMP_VAL_HI___S                        0

#define DBG_CSR_INT_TSTMP_VAL_LO                  (0x00B91018)
#define   DBG_CSR_INT_TSTMP_VAL_LO___RWC            QCSR_REG_RO    
#define   DBG_CSR_INT_TSTMP_VAL_LO___POR         0x00000000
#define   DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000
#define   DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF
#define   DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___S               0
#define   DBG_CSR_INT_TSTMP_VAL_LO___M           0xFFFFFFFF   
#define   DBG_CSR_INT_TSTMP_VAL_LO___S                         0

#define DBG_CSR_INT_TSTMP_VAL_HI                  (0x00B9101C)
#define   DBG_CSR_INT_TSTMP_VAL_HI___RWC            QCSR_REG_RO    
#define   DBG_CSR_INT_TSTMP_VAL_HI___POR         0x00000000
#define   DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000
#define   DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF
#define   DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___S               0
#define   DBG_CSR_INT_TSTMP_VAL_HI___M           0xFFFFFFFF   
#define   DBG_CSR_INT_TSTMP_VAL_HI___S                         0

#define DBG_CSR_SWGEN_DSB                         (0x00B91020)
#define   DBG_CSR_SWGEN_DSB___RWC                   QCSR_REG_WO    
#define   DBG_CSR_SWGEN_DSB___POR                0x00000000
#define   DBG_CSR_SWGEN_DSB__EVENT7___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT6___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT5___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT4___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT3___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT2___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT1___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT0___POR        0x0
#define   DBG_CSR_SWGEN_DSB__EVENT7___M          0x00000080
#define   DBG_CSR_SWGEN_DSB__EVENT7___S                        7
#define   DBG_CSR_SWGEN_DSB__EVENT6___M          0x00000040
#define   DBG_CSR_SWGEN_DSB__EVENT6___S                        6
#define   DBG_CSR_SWGEN_DSB__EVENT5___M          0x00000020
#define   DBG_CSR_SWGEN_DSB__EVENT5___S                        5
#define   DBG_CSR_SWGEN_DSB__EVENT4___M          0x00000010
#define   DBG_CSR_SWGEN_DSB__EVENT4___S                        4
#define   DBG_CSR_SWGEN_DSB__EVENT3___M          0x00000008
#define   DBG_CSR_SWGEN_DSB__EVENT3___S                        3
#define   DBG_CSR_SWGEN_DSB__EVENT2___M          0x00000004
#define   DBG_CSR_SWGEN_DSB__EVENT2___S                        2
#define   DBG_CSR_SWGEN_DSB__EVENT1___M          0x00000002
#define   DBG_CSR_SWGEN_DSB__EVENT1___S                        1
#define   DBG_CSR_SWGEN_DSB__EVENT0___M          0x00000001
#define   DBG_CSR_SWGEN_DSB__EVENT0___S                        0
#define   DBG_CSR_SWGEN_DSB___M                  0x000000FF   
#define   DBG_CSR_SWGEN_DSB___S                                0

#define DBG_CSR_CLK_INFO                          (0x00B91024)
#define   DBG_CSR_CLK_INFO___RWC                    QCSR_REG_RO    
#define   DBG_CSR_CLK_INFO___POR                 0x00303000
#define   DBG_CSR_CLK_INFO__DAPBUS_DIV___POR     0x3
#define   DBG_CSR_CLK_INFO__TSTMP_DIV___POR      0x0
#define   DBG_CSR_CLK_INFO__APB_DIV___POR        0x3
#define   DBG_CSR_CLK_INFO__ATB_DIV___POR        0x00
#define   DBG_CSR_CLK_INFO__SRC___POR            0x0
#define   DBG_CSR_CLK_INFO__DAPBUS_DIV___M       0x00F00000
#define   DBG_CSR_CLK_INFO__DAPBUS_DIV___S                    20
#define   DBG_CSR_CLK_INFO__TSTMP_DIV___M        0x000F0000
#define   DBG_CSR_CLK_INFO__TSTMP_DIV___S                     16
#define   DBG_CSR_CLK_INFO__APB_DIV___M          0x0000F000
#define   DBG_CSR_CLK_INFO__APB_DIV___S                       12
#define   DBG_CSR_CLK_INFO__ATB_DIV___M          0x000001F0
#define   DBG_CSR_CLK_INFO__ATB_DIV___S                        4
#define   DBG_CSR_CLK_INFO__SRC___M              0x00000001
#define   DBG_CSR_CLK_INFO__SRC___S                            0
#define   DBG_CSR_CLK_INFO__SRC__PLL                         0x0
#define   DBG_CSR_CLK_INFO__SRC__XO                          0x1
#define   DBG_CSR_CLK_INFO___M                   0x00FFF1F1   
#define   DBG_CSR_CLK_INFO___S                                 0

#define DBG_CSR_CXO_FREQ                          (0x00B91028)
#define   DBG_CSR_CXO_FREQ___RWC                    QCSR_REG_RW    
#define   DBG_CSR_CXO_FREQ___POR                 0x0249F000
#define   DBG_CSR_CXO_FREQ__FREQ___POR           0x249F000
#define   DBG_CSR_CXO_FREQ__FREQ___M             0x03FFFFFF
#define   DBG_CSR_CXO_FREQ__FREQ___S                           0
#define   DBG_CSR_CXO_FREQ___M                   0x03FFFFFF   
#define   DBG_CSR_CXO_FREQ___S                                 0

#define DBG_CSR_CXO_FREQ_IN_KHZ                   (0x00B9102C)
#define   DBG_CSR_CXO_FREQ_IN_KHZ___RWC             QCSR_REG_RW    
#define   DBG_CSR_CXO_FREQ_IN_KHZ___POR          0x00009600
#define   DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___POR    0x9600
#define   DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___M      0x0000FFFF
#define   DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___S                    0
#define   DBG_CSR_CXO_FREQ_IN_KHZ___M            0x0000FFFF   
#define   DBG_CSR_CXO_FREQ_IN_KHZ___S                          0

#define DBG_CSR_SPARE                             (0x00B91030)
#define   DBG_CSR_SPARE___RWC                       QCSR_REG_RW    
#define   DBG_CSR_SPARE___POR                    0x00000000
#define   DBG_CSR_SPARE__SPARE___POR             0x00000000
#define   DBG_CSR_SPARE__SPARE___M               0xFFFFFFFF
#define   DBG_CSR_SPARE__SPARE___S                             0
#define   DBG_CSR_SPARE___M                      0xFFFFFFFF   
#define   DBG_CSR_SPARE___S                                    0

#define DBG_CSR_IPCAT                             (0x00B91034)
#define   DBG_CSR_IPCAT___RWC                       QCSR_REG_RO    
#define   DBG_CSR_IPCAT___POR                    0x10000000
#define   DBG_CSR_IPCAT__MAJ___POR               0x1
#define   DBG_CSR_IPCAT__MIN___POR               0x000
#define   DBG_CSR_IPCAT__STEP___POR              0x0000
#define   DBG_CSR_IPCAT__MAJ___M                 0xF0000000
#define   DBG_CSR_IPCAT__MAJ___S                              28
#define   DBG_CSR_IPCAT__MIN___M                 0x0FFF0000
#define   DBG_CSR_IPCAT__MIN___S                              16
#define   DBG_CSR_IPCAT__STEP___M                0x0000FFFF
#define   DBG_CSR_IPCAT__STEP___S                              0
#define   DBG_CSR_IPCAT___M                      0xFFFFFFFF   
#define   DBG_CSR_IPCAT___S                                    0

#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR        (0x00B91038)
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___RWC  QCSR_REG_RW    
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___POR 0x00000000
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___POR 0x00
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___M 0x00FE0000
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___S              17
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___M 0x00FE0000   
#define   DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___S              17

#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR        (0x00B9103C)
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___RWC  QCSR_REG_RW    
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___POR 0x00000000
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___POR 0x00
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___M 0x00FE0000
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___S              17
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___M 0x00FE0000   
#define   DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___S              17

#define DBG_CSR_LPI_IFC_OWNER                     (0x00B91040)
#define   DBG_CSR_LPI_IFC_OWNER___RWC               QCSR_REG_RW    
#define   DBG_CSR_LPI_IFC_OWNER___POR            0x00000000
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_APB___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_APB___POR  0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_NTS___POR   0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_ATB___POR   0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_APB___POR   0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___M    0x00002000
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___S                 13
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_NTS__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_NTS__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___M    0x00001000
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___S                 12
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_ATB__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_ATB__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___M    0x00000800
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___S                 11
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_DAP__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_DAP__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_APB___M    0x00000400
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_APB___S                 10
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_APB__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYB_APB__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___M    0x00000100
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___S                  8
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_NTS__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_NTS__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___M    0x00000080
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___S                  7
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_ATB__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_ATB__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___M    0x00000040
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___S                  6
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_DAP__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_DAP__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_APB___M    0x00000020
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_APB___S                  5
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_APB__PMM               0x0
#define   DBG_CSR_LPI_IFC_OWNER__PHYA_APB__CSR               0x1
#define   DBG_CSR_LPI_IFC_OWNER__NOC_NTS___M     0x00000008
#define   DBG_CSR_LPI_IFC_OWNER__NOC_NTS___S                   3
#define   DBG_CSR_LPI_IFC_OWNER__NOC_NTS__PMM                0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_NTS__CSR                0x1
#define   DBG_CSR_LPI_IFC_OWNER__NOC_ATB___M     0x00000004
#define   DBG_CSR_LPI_IFC_OWNER__NOC_ATB___S                   2
#define   DBG_CSR_LPI_IFC_OWNER__NOC_ATB__PMM                0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_ATB__CSR                0x1
#define   DBG_CSR_LPI_IFC_OWNER__NOC_APB___M     0x00000002
#define   DBG_CSR_LPI_IFC_OWNER__NOC_APB___S                   1
#define   DBG_CSR_LPI_IFC_OWNER__NOC_APB__PMM                0x0
#define   DBG_CSR_LPI_IFC_OWNER__NOC_APB__CSR                0x1
#define   DBG_CSR_LPI_IFC_OWNER___M              0x00003DEE   
#define   DBG_CSR_LPI_IFC_OWNER___S                            1

#define DBG_CSR_LPI_IFC_SW_CSYSREQ                (0x00B91044)
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ___RWC          QCSR_REG_RW    
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ___POR       0x00003DEE
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___M 0x00002000
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___S              13
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___M 0x00001000
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___S              12
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___M 0x00000800
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___S              11
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___M 0x00000400
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___S              10
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___M 0x00000100
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___S               8
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___M 0x00000080
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___S               7
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___M 0x00000040
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___S               6
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___M 0x00000020
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___S               5
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___M 0x00000008
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___S               3
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___M 0x00000004
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___S               2
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___M 0x00000002
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___S               1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ___M         0x00003DEE   
#define   DBG_CSR_LPI_IFC_SW_CSYSREQ___S                       1

#define DBG_CSR_LPI_IFC_CSYSREQ_STAT              (0x00B91048)
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT___RWC        QCSR_REG_RO    
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT___POR     0x00003FFF
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___M 0x00002000
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___S              13
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___M 0x00001000
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___S              12
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___M 0x00000800
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___S              11
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___M 0x00000400
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___S              10
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___M 0x00000200
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___S               9
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___M 0x00000100
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___S               8
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___M 0x00000080
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___S               7
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___M 0x00000040
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___S               6
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___M 0x00000020
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___S               5
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___M 0x00000010
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___S               4
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___M 0x00000008
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___S               3
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___M 0x00000004
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___S               2
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___M 0x00000002
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___S               1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___M 0x00000001
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___S               0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT___M       0x00003FFF   
#define   DBG_CSR_LPI_IFC_CSYSREQ_STAT___S                     0

#define DBG_CSR_LPI_IFC_CSYSACK_STAT              (0x00B9104C)
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT___RWC        QCSR_REG_RO    
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT___POR     0x00003FFF
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___POR 0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___M 0x00002000
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___S              13
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___M 0x00001000
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___S              12
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___M 0x00000800
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___S              11
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___M 0x00000400
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___S              10
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___M 0x00000200
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___S               9
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___M 0x00000100
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___S               8
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___M 0x00000080
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___S               7
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___M 0x00000040
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___S               6
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___M 0x00000020
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___S               5
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___M 0x00000010
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___S               4
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___M 0x00000008
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___S               3
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___M 0x00000004
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___S               2
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___M 0x00000002
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___S               1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___M  0x00000001
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___S                0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC__PWRDWN             0x0
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC__PWRUP             0x1
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT___M       0x00003FFF   
#define   DBG_CSR_LPI_IFC_CSYSACK_STAT___S                     0

#define DBG_CSR_LPI_IFC_CACTIVE_STAT              (0x00B91050)
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT___RWC        QCSR_REG_RO    
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT___POR     0x00003FFF
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___POR 0x1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___M 0x00002000
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___S              13
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___M 0x00001000
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___S              12
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___M 0x00000800
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___S              11
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___M 0x00000400
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___S              10
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___M 0x00000200
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___S               9
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___M 0x00000100
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___S               8
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___M 0x00000080
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___S               7
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___M 0x00000040
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___S               6
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___M 0x00000020
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___S               5
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___M 0x00000010
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___S               4
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___M 0x00000008
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___S               3
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___M 0x00000004
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___S               2
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___M 0x00000002
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___S               1
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___M  0x00000001
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___S                0
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT___M       0x00003FFF   
#define   DBG_CSR_LPI_IFC_CACTIVE_STAT___S                     0

#define DBG_CSR_TIMER                             (0x00B91054)
#define   DBG_CSR_TIMER___RWC                       QCSR_REG_RW    
#define   DBG_CSR_TIMER___POR                    0x00000000
#define   DBG_CSR_TIMER__VALUE___POR             0x00000000
#define   DBG_CSR_TIMER__VALUE___M               0xFFFFFFFF
#define   DBG_CSR_TIMER__VALUE___S                             0
#define   DBG_CSR_TIMER___M                      0xFFFFFFFF   
#define   DBG_CSR_TIMER___S                                    0

#define DBG_CSR_PMM_TRC_CFG                       (0x00B91058)
#define   DBG_CSR_PMM_TRC_CFG___RWC                 QCSR_REG_RW    
#define   DBG_CSR_PMM_TRC_CFG___POR              0x00004F9C
#define   DBG_CSR_PMM_TRC_CFG__ATID1___POR       0x4F
#define   DBG_CSR_PMM_TRC_CFG__ATID0___POR       0x4E
#define   DBG_CSR_PMM_TRC_CFG__MODE___POR        0x0
#define   DBG_CSR_PMM_TRC_CFG__ATID1___M         0x00007F00
#define   DBG_CSR_PMM_TRC_CFG__ATID1___S                       8
#define   DBG_CSR_PMM_TRC_CFG__ATID0___M         0x000000FE
#define   DBG_CSR_PMM_TRC_CFG__ATID0___S                       1
#define   DBG_CSR_PMM_TRC_CFG__MODE___M          0x00000001
#define   DBG_CSR_PMM_TRC_CFG__MODE___S                        0
#define   DBG_CSR_PMM_TRC_CFG__MODE__CMB                     0x0
#define   DBG_CSR_PMM_TRC_CFG__MODE__ATB                     0x1
#define   DBG_CSR_PMM_TRC_CFG___M                0x00007FFF   
#define   DBG_CSR_PMM_TRC_CFG___S                              0

#define DBG_CSR_TGU_CFG                           (0x00B9105C)
#define   DBG_CSR_TGU_CFG___RWC                     QCSR_REG_RW    
#define   DBG_CSR_TGU_CFG___POR                  0x00000000
#define   DBG_CSR_TGU_CFG__SRC_SEL___POR         0x0
#define   DBG_CSR_TGU_CFG__EN___POR              0x0
#define   DBG_CSR_TGU_CFG__SRC_SEL___M           0x0000001E
#define   DBG_CSR_TGU_CFG__SRC_SEL___S                         1
#define   DBG_CSR_TGU_CFG__SRC_SEL__MACEVENT                 0x0
#define   DBG_CSR_TGU_CFG__SRC_SEL__MACTLV                   0x1
#define   DBG_CSR_TGU_CFG__SRC_SEL__MACTBUS                  0x2
#define   DBG_CSR_TGU_CFG__SRC_SEL__PMM                      0x3
#define   DBG_CSR_TGU_CFG__SRC_SEL__PHYA                     0x4
#define   DBG_CSR_TGU_CFG__SRC_SEL__PHYB                     0x5
#define   DBG_CSR_TGU_CFG__SRC_SEL__APBMON                   0x6
#define   DBG_CSR_TGU_CFG__SRC_SEL__DATDUMPR                 0x7
#define   DBG_CSR_TGU_CFG__SRC_SEL__SWGENCMB                 0x8
#define   DBG_CSR_TGU_CFG__EN___M                0x00000001
#define   DBG_CSR_TGU_CFG__EN___S                              0
#define   DBG_CSR_TGU_CFG__EN__DISABLED                      0x0
#define   DBG_CSR_TGU_CFG__EN__ENABLED                       0x1
#define   DBG_CSR_TGU_CFG___M                    0x0000001F   
#define   DBG_CSR_TGU_CFG___S                                  0

#define DBG_CSR_PHYA_TGU_CFG                      (0x00B91060)
#define   DBG_CSR_PHYA_TGU_CFG___RWC                QCSR_REG_RW    
#define   DBG_CSR_PHYA_TGU_CFG___POR             0x000000F0
#define   DBG_CSR_PHYA_TGU_CFG__ATID___POR       0x00
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_POL___POR   0xF
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_EN___POR    0x0
#define   DBG_CSR_PHYA_TGU_CFG__ATID___M         0x0000FE00
#define   DBG_CSR_PHYA_TGU_CFG__ATID___S                       9
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___M  0x00000100
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___S                8
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_POL___M     0x000000F0
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_POL___S                   4
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_EN___M      0x0000000F
#define   DBG_CSR_PHYA_TGU_CFG__TRIG_EN___S                    0
#define   DBG_CSR_PHYA_TGU_CFG___M               0x0000FFFF   
#define   DBG_CSR_PHYA_TGU_CFG___S                             0

#define DBG_CSR_PHYB_TGU_CFG                      (0x00B91064)
#define   DBG_CSR_PHYB_TGU_CFG___RWC                QCSR_REG_RW    
#define   DBG_CSR_PHYB_TGU_CFG___POR             0x000000F0
#define   DBG_CSR_PHYB_TGU_CFG__ATID___POR       0x00
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_POL___POR   0xF
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_EN___POR    0x0
#define   DBG_CSR_PHYB_TGU_CFG__ATID___M         0x0000FE00
#define   DBG_CSR_PHYB_TGU_CFG__ATID___S                       9
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___M  0x00000100
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___S                8
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_POL___M     0x000000F0
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_POL___S                   4
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_EN___M      0x0000000F
#define   DBG_CSR_PHYB_TGU_CFG__TRIG_EN___S                    0
#define   DBG_CSR_PHYB_TGU_CFG___M               0x0000FFFF   
#define   DBG_CSR_PHYB_TGU_CFG___S                             0

#define DBG_CSR_PMM_TGU_CFG                       (0x00B91068)
#define   DBG_CSR_PMM_TGU_CFG___RWC                 QCSR_REG_RW    
#define   DBG_CSR_PMM_TGU_CFG___POR              0x000000F0
#define   DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_PMM_TGU_CFG__TRIG_POL___POR    0xF
#define   DBG_CSR_PMM_TGU_CFG__TRIG_EN___POR     0x0
#define   DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___M   0x00000100
#define   DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___S                 8
#define   DBG_CSR_PMM_TGU_CFG__TRIG_POL___M      0x000000F0
#define   DBG_CSR_PMM_TGU_CFG__TRIG_POL___S                    4
#define   DBG_CSR_PMM_TGU_CFG__TRIG_EN___M       0x0000000F
#define   DBG_CSR_PMM_TGU_CFG__TRIG_EN___S                     0
#define   DBG_CSR_PMM_TGU_CFG___M                0x000001FF   
#define   DBG_CSR_PMM_TGU_CFG___S                              0

#define DBG_CSR_APBMON_TGU_CFG                    (0x00B9106C)
#define   DBG_CSR_APBMON_TGU_CFG___RWC              QCSR_REG_RW    
#define   DBG_CSR_APBMON_TGU_CFG___POR           0x000000F0
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_EN___POR  0x0
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_POL___M   0x000000F0
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_POL___S                 4
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_EN___M    0x0000000F
#define   DBG_CSR_APBMON_TGU_CFG__TRIG_EN___S                  0
#define   DBG_CSR_APBMON_TGU_CFG___M             0x000001FF   
#define   DBG_CSR_APBMON_TGU_CFG___S                           0

#define DBG_CSR_DATDUMPR_TGU_CFG                  (0x00B91070)
#define   DBG_CSR_DATDUMPR_TGU_CFG___RWC            QCSR_REG_RW    
#define   DBG_CSR_DATDUMPR_TGU_CFG___POR         0x000000F0
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___POR 0x0
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___M 0x000000F0
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___S               4
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___M  0x0000000F
#define   DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___S                0
#define   DBG_CSR_DATDUMPR_TGU_CFG___M           0x000001FF   
#define   DBG_CSR_DATDUMPR_TGU_CFG___S                         0

#define DBG_CSR_SWGENCMB_TGU_CFG                  (0x00B91074)
#define   DBG_CSR_SWGENCMB_TGU_CFG___RWC            QCSR_REG_RW    
#define   DBG_CSR_SWGENCMB_TGU_CFG___POR         0x000000F0
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___POR 0x0
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___M 0x000000F0
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___S               4
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___M  0x0000000F
#define   DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___S                0
#define   DBG_CSR_SWGENCMB_TGU_CFG___M           0x000001FF   
#define   DBG_CSR_SWGENCMB_TGU_CFG___S                         0

#define DBG_CSR_QTMR_TSTMP_VAL_LO                 (0x00B91078)
#define   DBG_CSR_QTMR_TSTMP_VAL_LO___RWC           QCSR_REG_RO    
#define   DBG_CSR_QTMR_TSTMP_VAL_LO___POR        0x00000000
#define   DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000
#define   DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF
#define   DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___S               0
#define   DBG_CSR_QTMR_TSTMP_VAL_LO___M          0xFFFFFFFF   
#define   DBG_CSR_QTMR_TSTMP_VAL_LO___S                        0

#define DBG_CSR_QTMR_TSTMP_VAL_HI                 (0x00B9107C)
#define   DBG_CSR_QTMR_TSTMP_VAL_HI___RWC           QCSR_REG_RO    
#define   DBG_CSR_QTMR_TSTMP_VAL_HI___POR        0x00000000
#define   DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000
#define   DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF
#define   DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___S               0
#define   DBG_CSR_QTMR_TSTMP_VAL_HI___M          0xFFFFFFFF   
#define   DBG_CSR_QTMR_TSTMP_VAL_HI___S                        0

#define DBG_CSR_DATDUMPER_CTRL                    (0x00B91200)
#define   DBG_CSR_DATDUMPER_CTRL___RWC              QCSR_REG_RW    
#define   DBG_CSR_DATDUMPER_CTRL___POR           0x00000000
#define   DBG_CSR_DATDUMPER_CTRL__BUSY___POR     0x0
#define   DBG_CSR_DATDUMPER_CTRL__DESCR_EN___POR 0x0
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___POR 0x0
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___POR 0x0
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___POR 0x0
#define   DBG_CSR_DATDUMPER_CTRL__TRIGEN___POR   0x0
#define   DBG_CSR_DATDUMPER_CTRL__SWSTART___POR  0x0
#define   DBG_CSR_DATDUMPER_CTRL__BUSY___M       0x00000040
#define   DBG_CSR_DATDUMPER_CTRL__BUSY___S                     6
#define   DBG_CSR_DATDUMPER_CTRL__DESCR_EN___M   0x00000020
#define   DBG_CSR_DATDUMPER_CTRL__DESCR_EN___S                 5
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___M 0x00000010
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___S               4
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___M 0x00000008
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___S               3
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___M 0x00000004
#define   DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___S               2
#define   DBG_CSR_DATDUMPER_CTRL__TRIGEN___M     0x00000002
#define   DBG_CSR_DATDUMPER_CTRL__TRIGEN___S                   1
#define   DBG_CSR_DATDUMPER_CTRL__SWSTART___M    0x00000001
#define   DBG_CSR_DATDUMPER_CTRL__SWSTART___S                  0
#define   DBG_CSR_DATDUMPER_CTRL___M             0x0000007F   
#define   DBG_CSR_DATDUMPER_CTRL___S                           0

#define DBG_CSR_DATDUMPER_START_ADDR              (0x00B91204)
#define   DBG_CSR_DATDUMPER_START_ADDR___RWC        QCSR_REG_RW    
#define   DBG_CSR_DATDUMPER_START_ADDR___POR     0x00000000
#define   DBG_CSR_DATDUMPER_START_ADDR__ADDR___POR 0x000000
#define   DBG_CSR_DATDUMPER_START_ADDR__ADDR___M 0x00FFFFFF
#define   DBG_CSR_DATDUMPER_START_ADDR__ADDR___S               0
#define   DBG_CSR_DATDUMPER_START_ADDR___M       0x00FFFFFF   
#define   DBG_CSR_DATDUMPER_START_ADDR___S                     0

#define DBG_CSR_DATDUMPER_END_ADDR                (0x00B91208)
#define   DBG_CSR_DATDUMPER_END_ADDR___RWC          QCSR_REG_RW    
#define   DBG_CSR_DATDUMPER_END_ADDR___POR       0x00000000
#define   DBG_CSR_DATDUMPER_END_ADDR__ADDR___POR 0x000000
#define   DBG_CSR_DATDUMPER_END_ADDR__ADDR___M   0x00FFFFFF
#define   DBG_CSR_DATDUMPER_END_ADDR__ADDR___S                 0
#define   DBG_CSR_DATDUMPER_END_ADDR___M         0x00FFFFFF   
#define   DBG_CSR_DATDUMPER_END_ADDR___S                       0

#define DBG_CSR_DATDUMPER_DISCARD_VALUE           (0x00B9120C)
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE___RWC     QCSR_REG_RW    
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE___POR  0x00000000
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___POR 0x00000000
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___M 0xFFFFFFFF
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___S               0
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE___M    0xFFFFFFFF   
#define   DBG_CSR_DATDUMPER_DISCARD_VALUE___S                  0

#define DBG_CSR_DATDUMPER_LAST_ADDR               (0x00B91210)
#define   DBG_CSR_DATDUMPER_LAST_ADDR___RWC         QCSR_REG_RO    
#define   DBG_CSR_DATDUMPER_LAST_ADDR___POR      0x00000000
#define   DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___POR 0x000000
#define   DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___M  0x00FFFFFF
#define   DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___S                0
#define   DBG_CSR_DATDUMPER_LAST_ADDR___M        0x00FFFFFF   
#define   DBG_CSR_DATDUMPER_LAST_ADDR___S                      0

#define DBG_CSR_DATDUMPER_LAST_DATA               (0x00B91214)
#define   DBG_CSR_DATDUMPER_LAST_DATA___RWC         QCSR_REG_RO    
#define   DBG_CSR_DATDUMPER_LAST_DATA___POR      0x00000000
#define   DBG_CSR_DATDUMPER_LAST_DATA__DATA___POR 0x00000000
#define   DBG_CSR_DATDUMPER_LAST_DATA__DATA___M  0xFFFFFFFF
#define   DBG_CSR_DATDUMPER_LAST_DATA__DATA___S                0
#define   DBG_CSR_DATDUMPER_LAST_DATA___M        0xFFFFFFFF   
#define   DBG_CSR_DATDUMPER_LAST_DATA___S                      0

#define DBG_CSR_DATDUMPER_LAST_RESP               (0x00B91218)
#define   DBG_CSR_DATDUMPER_LAST_RESP___RWC         QCSR_REG_RO    
#define   DBG_CSR_DATDUMPER_LAST_RESP___POR      0x00000000
#define   DBG_CSR_DATDUMPER_LAST_RESP__RESP___POR 0x0
#define   DBG_CSR_DATDUMPER_LAST_RESP__RESP___M  0x00000001
#define   DBG_CSR_DATDUMPER_LAST_RESP__RESP___S                0
#define   DBG_CSR_DATDUMPER_LAST_RESP__RESP__OKAY             0x0
#define   DBG_CSR_DATDUMPER_LAST_RESP__RESP__ERROR             0x1
#define   DBG_CSR_DATDUMPER_LAST_RESP___M        0x00000001   
#define   DBG_CSR_DATDUMPER_LAST_RESP___S                      0

#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR          (0x00B9121C)
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___RWC    QCSR_REG_RW    
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___POR 0x00000000
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___POR 0x000000
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___M 0x00FFFFFF
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___S               0
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___M   0x00FFFFFF   
#define   DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___S                 0

#define DBG_CSR_APBMON_DSB_MATCH0_CTRL            (0x00B91400)
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL___RWC      QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL___POR   0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___M 0x00000040
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___S               6
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___M 0x00000020
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___S               5
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___M 0x00000010
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___S               4
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___M 0x00000008
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___S               3
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___M 0x00000004
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___S               2
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___M 0x00000002
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___S               1
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___M 0x00000001
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL___M     0x0000007F   
#define   DBG_CSR_APBMON_DSB_MATCH0_CTRL___S                   0

#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK      (0x00B91404)
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___POR 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___POR 0xFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___S               0

#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO        (0x00B91408)
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___RWC  QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___POR 0x000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___S               0

#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI        (0x00B9140C)
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___RWC  QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___POR 0x000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___S               0

#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS         (0x00B91410)
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS___RWC   QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___M 0x00020000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___S              17
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE__OKAY             0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE__ERROR             0x1
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___M 0x00010000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___S              16
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE__READ             0x0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE__WRITE             0x1
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___M 0x00008000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___S              15
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___M 0x00004000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___S              14
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___M 0x00002000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___S              13
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___M 0x00001000
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___S              12
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___M 0x00000800
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___S              11
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___M 0x00000400
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___S              10
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___M 0x00000200
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___S               9
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___M 0x00000100
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___S               8
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___M 0x00000080
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___S               7
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___M 0x00000040
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___S               6
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___M 0x00000020
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___S               5
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___M 0x00000010
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___S               4
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___M 0x00000008
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___S               3
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___M 0x00000004
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___S               2
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___M 0x00000002
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___S               1
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___M 0x00000001
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS___M  0x0003FFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_DETAILS___S                0

#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK      (0x00B91414)
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___POR 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___M 0xFFFFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___S               0

#define DBG_CSR_APBMON_DSB_MATCH0_PDATA           (0x00B91418)
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA___RWC     QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA___POR  0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___S               0
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA___M    0xFFFFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH0_PDATA___S                  0

#define DBG_CSR_APBMON_DSB_MATCH1_CTRL            (0x00B9141C)
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL___RWC      QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL___POR   0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___M 0x00000040
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___S               6
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___M 0x00000020
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___S               5
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___M 0x00000010
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___S               4
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___M 0x00000008
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___S               3
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___M 0x00000004
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___S               2
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___M 0x00000002
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___S               1
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___M 0x00000001
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL___M     0x0000007F   
#define   DBG_CSR_APBMON_DSB_MATCH1_CTRL___S                   0

#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK      (0x00B91420)
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___POR 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___POR 0xFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___S               0

#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO        (0x00B91424)
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___RWC  QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___POR 0x000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___S               0

#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI        (0x00B91428)
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___RWC  QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___POR 0x000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___M 0x00FFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___S               0

#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS         (0x00B9142C)
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS___RWC   QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___POR 0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___M 0x00020000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___S              17
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE__OKAY             0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE__ERROR             0x1
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___M 0x00010000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___S              16
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE__READ             0x0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE__WRITE             0x1
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___M 0x00008000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___S              15
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___M 0x00004000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___S              14
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___M 0x00002000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___S              13
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___M 0x00001000
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___S              12
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___M 0x00000800
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___S              11
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___M 0x00000400
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___S              10
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___M 0x00000200
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___S               9
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___M 0x00000100
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___S               8
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___M 0x00000080
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___S               7
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___M 0x00000040
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___S               6
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___M 0x00000020
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___S               5
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___M 0x00000010
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___S               4
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___M 0x00000008
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___S               3
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___M 0x00000004
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___S               2
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___M 0x00000002
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___S               1
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___M 0x00000001
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS___M  0x0003FFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_DETAILS___S                0

#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK      (0x00B91430)
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___POR 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___M 0xFFFFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___S               0

#define DBG_CSR_APBMON_DSB_MATCH1_PDATA           (0x00B91434)
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA___RWC     QCSR_REG_RW    
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA___POR  0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___POR 0x00000000
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___S               0
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA___M    0xFFFFFFFF   
#define   DBG_CSR_APBMON_DSB_MATCH1_PDATA___S                  0

#define DBG_CSR_APBMON_MAX_LATENCY                (0x00B91438)
#define   DBG_CSR_APBMON_MAX_LATENCY___RWC          QCSR_REG_RW    
#define   DBG_CSR_APBMON_MAX_LATENCY___POR       0x00000400
#define   DBG_CSR_APBMON_MAX_LATENCY__LATENCY___POR 0x00400
#define   DBG_CSR_APBMON_MAX_LATENCY__LATENCY___M 0x0001FFFF
#define   DBG_CSR_APBMON_MAX_LATENCY__LATENCY___S               0
#define   DBG_CSR_APBMON_MAX_LATENCY___M         0x0001FFFF   
#define   DBG_CSR_APBMON_MAX_LATENCY___S                       0

#define DBG_CSR_APBMON_CMB_CFG                    (0x00B9143C)
#define   DBG_CSR_APBMON_CMB_CFG___RWC              QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_CFG___POR           0x00000000
#define   DBG_CSR_APBMON_CMB_CFG__DATA_EN___POR  0x0
#define   DBG_CSR_APBMON_CMB_CFG__ENABLE___POR   0x0
#define   DBG_CSR_APBMON_CMB_CFG__DATA_EN___M    0x00000002
#define   DBG_CSR_APBMON_CMB_CFG__DATA_EN___S                  1
#define   DBG_CSR_APBMON_CMB_CFG__ENABLE___M     0x00000001
#define   DBG_CSR_APBMON_CMB_CFG__ENABLE___S                   0
#define   DBG_CSR_APBMON_CMB_CFG___M             0x00000003   
#define   DBG_CSR_APBMON_CMB_CFG___S                           0

#define DBG_CSR_APBMON_CMB_MATCH_CTRL             (0x00B91440)
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL___RWC       QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL___POR    0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___M 0x00000040
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___S               6
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___M 0x00000020
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___S               5
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___M 0x00000010
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___S               4
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___M 0x00000008
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___S               3
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___M 0x00000004
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___S               2
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___M 0x00000002
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___S               1
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___M 0x00000001
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL___M      0x0000007F   
#define   DBG_CSR_APBMON_CMB_MATCH_CTRL___S                    0

#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK       (0x00B91444)
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___POR 0x000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___M 0x00FFFFFF
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___M 0x00FFFFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___S               0

#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO         (0x00B91448)
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___RWC   QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___POR 0x000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___M 0x00FFFFFF
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___M  0x00FFFFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___S                0

#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI         (0x00B9144C)
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___RWC   QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___POR 0x000000
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___M 0x00FFFFFF
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___M  0x00FFFFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___S                0

#define DBG_CSR_APBMON_CMB_MATCH_DETAILS          (0x00B91450)
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS___RWC    QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___POR 0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___M 0x00020000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___S              17
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE__OKAY             0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE__ERROR             0x1
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___M 0x00010000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___S              16
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE__READ             0x0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE__WRITE             0x1
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___M 0x00008000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___S              15
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___M 0x00004000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___S              14
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___M 0x00002000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___S              13
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___M 0x00001000
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___S              12
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___M 0x00000800
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___S              11
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___M 0x00000400
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___S              10
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___M 0x00000200
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___S               9
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___M 0x00000100
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___S               8
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___M 0x00000080
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___S               7
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___M 0x00000040
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___S               6
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___M 0x00000020
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___S               5
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___M 0x00000010
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___S               4
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___M 0x00000008
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___S               3
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___M 0x00000004
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___S               2
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___M 0x00000002
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___S               1
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___M 0x00000001
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS___M   0x0003FFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_DETAILS___S                 0

#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK       (0x00B91454)
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___RWC QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___M 0xFFFFFFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___S               0

#define DBG_CSR_APBMON_CMB_MATCH_PDATA            (0x00B91458)
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA___RWC      QCSR_REG_RW    
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA___POR   0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___POR 0x00000000
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___S               0
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA___M     0xFFFFFFFF   
#define   DBG_CSR_APBMON_CMB_MATCH_PDATA___S                   0

#define DBG_CSR_APBMON_LST_XFER_ADDR              (0x00B9145C)
#define   DBG_CSR_APBMON_LST_XFER_ADDR___RWC        QCSR_REG_RO    
#define   DBG_CSR_APBMON_LST_XFER_ADDR___POR     0x00000000
#define   DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___POR 0x000000
#define   DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___M 0x00FFFFFF
#define   DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___S               0
#define   DBG_CSR_APBMON_LST_XFER_ADDR___M       0x00FFFFFF   
#define   DBG_CSR_APBMON_LST_XFER_ADDR___S                     0

#define DBG_CSR_APBMON_LST_XFER_DETAILS           (0x00B91460)
#define   DBG_CSR_APBMON_LST_XFER_DETAILS___RWC     QCSR_REG_RO    
#define   DBG_CSR_APBMON_LST_XFER_DETAILS___POR  0x00000000
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___POR 0x00000
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___POR 0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___POR 0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___POR 0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___M 0x01FFFFC0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___S               6
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___M 0x00000020
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___S               5
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE__OKAY             0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE__ERROR             0x1
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___M 0x00000010
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___S               4
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE__READ             0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE__WRITE             0x1
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___M 0x0000000F
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___S               0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__PHYA             0x0
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__UMAC             0x1
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WMAC0             0x2
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__TSLV             0x3
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCMN             0x4
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCMN_CORE             0x5
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WFSSPMM             0x6
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__TOPPMM             0x7
#define   DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCSS_DBG             0x8
#define   DBG_CSR_APBMON_LST_XFER_DETAILS___M    0x01FFFFFF   
#define   DBG_CSR_APBMON_LST_XFER_DETAILS___S                  0

#define DBG_CSR_APBMON_LST_XFER_DATA              (0x00B91464)
#define   DBG_CSR_APBMON_LST_XFER_DATA___RWC        QCSR_REG_RO    
#define   DBG_CSR_APBMON_LST_XFER_DATA___POR     0x00000000
#define   DBG_CSR_APBMON_LST_XFER_DATA__DATA___POR 0x00000000
#define   DBG_CSR_APBMON_LST_XFER_DATA__DATA___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_LST_XFER_DATA__DATA___S               0
#define   DBG_CSR_APBMON_LST_XFER_DATA___M       0xFFFFFFFF   
#define   DBG_CSR_APBMON_LST_XFER_DATA___S                     0

#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO          (0x00B91468)
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO___RWC    QCSR_REG_RO    
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO___POR 0x00000000
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___POR 0x00000000
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___S               0
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO___M   0xFFFFFFFF   
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_LO___S                 0

#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI          (0x00B9146C)
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI___RWC    QCSR_REG_RO    
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI___POR 0x00000000
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___POR 0x00000000
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___S               0
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI___M   0xFFFFFFFF   
#define   DBG_CSR_APBMON_LST_XFER_TSTMP_HI___S                 0

#define DBG_CSR_INTR_EDGE_SEL0                    (0x00B91800)
#define   DBG_CSR_INTR_EDGE_SEL0___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL0___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL0___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL0___S                           0

#define DBG_CSR_INTR_EDGE_SEL1                    (0x00B91804)
#define   DBG_CSR_INTR_EDGE_SEL1___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL1___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL1___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL1___S                           0

#define DBG_CSR_INTR_EDGE_SEL2                    (0x00B91808)
#define   DBG_CSR_INTR_EDGE_SEL2___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL2___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL2___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL2___S                           0

#define DBG_CSR_INTR_EDGE_SEL3                    (0x00B9180C)
#define   DBG_CSR_INTR_EDGE_SEL3___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL3___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL3___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL3___S                           0

#define DBG_CSR_INTR_EDGE_SEL4                    (0x00B91810)
#define   DBG_CSR_INTR_EDGE_SEL4___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL4___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL4___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL4___S                           0

#define DBG_CSR_INTR_EDGE_SEL5                    (0x00B91814)
#define   DBG_CSR_INTR_EDGE_SEL5___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL5___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL5___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL5___S                           0

#define DBG_CSR_INTR_EDGE_SEL6                    (0x00B91818)
#define   DBG_CSR_INTR_EDGE_SEL6___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL6___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL6___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL6___S                           0

#define DBG_CSR_INTR_EDGE_SEL7                    (0x00B9181C)
#define   DBG_CSR_INTR_EDGE_SEL7___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL7___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL7___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL7___S                           0

#define DBG_CSR_INTR_EDGE_SEL8                    (0x00B91820)
#define   DBG_CSR_INTR_EDGE_SEL8___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL8___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL8___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL8___S                           0

#define DBG_CSR_INTR_EDGE_SEL9                    (0x00B91824)
#define   DBG_CSR_INTR_EDGE_SEL9___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL9___POR           0x00000000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL9___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL9___S                           0

#define DBG_CSR_INTR_EDGE_SEL10                   (0x00B91828)
#define   DBG_CSR_INTR_EDGE_SEL10___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL10___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL10___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL10___S                          0

#define DBG_CSR_INTR_EDGE_SEL11                   (0x00B9182C)
#define   DBG_CSR_INTR_EDGE_SEL11___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL11___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL11___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL11___S                          0

#define DBG_CSR_INTR_EDGE_SEL12                   (0x00B91830)
#define   DBG_CSR_INTR_EDGE_SEL12___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL12___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL12___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL12___S                          0

#define DBG_CSR_INTR_EDGE_SEL13                   (0x00B91834)
#define   DBG_CSR_INTR_EDGE_SEL13___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL13___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL13___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL13___S                          0

#define DBG_CSR_INTR_EDGE_SEL14                   (0x00B91838)
#define   DBG_CSR_INTR_EDGE_SEL14___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL14___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL14___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL14___S                          0

#define DBG_CSR_INTR_EDGE_SEL15                   (0x00B9183C)
#define   DBG_CSR_INTR_EDGE_SEL15___RWC             QCSR_REG_RW    
#define   DBG_CSR_INTR_EDGE_SEL15___POR          0x00000000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___POR 0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___M 0xC0000000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___S              30
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___M 0x30000000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___S              28
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___M 0x0C000000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___S              26
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___M 0x03000000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___S              24
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___M 0x00C00000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___S              22
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___M 0x00300000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___S              20
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___M 0x000C0000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___S              18
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___M 0x00030000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___S              16
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___M 0x0000C000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___S              14
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___M 0x00003000
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___S              12
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___M 0x00000C00
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___S              10
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___M 0x00000300
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___S               8
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___M 0x000000C0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___S               6
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___M 0x00000030
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___S               4
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___M 0x0000000C
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___S               2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___M 0x00000003
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___S               0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__RSNG_EDGE             0x0
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__FLNG_EDGE             0x1
#define   DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__EITHER_EDGE             0x2
#define   DBG_CSR_INTR_EDGE_SEL15___M            0xFFFFFFFF   
#define   DBG_CSR_INTR_EDGE_SEL15___S                          0

#define DBG_CSR_INTR_DSB_SEL0                     (0x00B91840)
#define   DBG_CSR_INTR_DSB_SEL0___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL0___POR            0x03020100
#define   DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___POR 0x03
#define   DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___POR 0x02
#define   DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___POR 0x01
#define   DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___POR 0x00
#define   DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL0___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL0___S                            0

#define DBG_CSR_INTR_DSB_SEL1                     (0x00B91844)
#define   DBG_CSR_INTR_DSB_SEL1___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL1___POR            0x07060504
#define   DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___POR 0x07
#define   DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___POR 0x06
#define   DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___POR 0x05
#define   DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___POR 0x04
#define   DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL1___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL1___S                            0

#define DBG_CSR_INTR_DSB_SEL2                     (0x00B91848)
#define   DBG_CSR_INTR_DSB_SEL2___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL2___POR            0x0B0A0908
#define   DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___POR 0x0B
#define   DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___POR 0x0A
#define   DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___POR 0x09
#define   DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___POR 0x08
#define   DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL2___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL2___S                            0

#define DBG_CSR_INTR_DSB_SEL3                     (0x00B9184C)
#define   DBG_CSR_INTR_DSB_SEL3___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL3___POR            0x0F0E0D0C
#define   DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___POR 0x0F
#define   DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___POR 0x0E
#define   DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___POR 0x0D
#define   DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___POR 0x0C
#define   DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL3___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL3___S                            0

#define DBG_CSR_INTR_DSB_SEL4                     (0x00B91850)
#define   DBG_CSR_INTR_DSB_SEL4___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL4___POR            0x13121110
#define   DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___POR 0x13
#define   DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___POR 0x12
#define   DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___POR 0x11
#define   DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___POR 0x10
#define   DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL4___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL4___S                            0

#define DBG_CSR_INTR_DSB_SEL5                     (0x00B91854)
#define   DBG_CSR_INTR_DSB_SEL5___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL5___POR            0x17161514
#define   DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___POR 0x17
#define   DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___POR 0x16
#define   DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___POR 0x15
#define   DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___POR 0x14
#define   DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL5___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL5___S                            0

#define DBG_CSR_INTR_DSB_SEL6                     (0x00B91858)
#define   DBG_CSR_INTR_DSB_SEL6___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL6___POR            0x1B1A1918
#define   DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___POR 0x1B
#define   DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___POR 0x1A
#define   DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___POR 0x19
#define   DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___POR 0x18
#define   DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL6___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL6___S                            0

#define DBG_CSR_INTR_DSB_SEL7                     (0x00B9185C)
#define   DBG_CSR_INTR_DSB_SEL7___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL7___POR            0x1F1E1D1C
#define   DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___POR 0x1F
#define   DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___POR 0x1E
#define   DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___POR 0x1D
#define   DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___POR 0x1C
#define   DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL7___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL7___S                            0

#define DBG_CSR_INTR_DSB_SEL8                     (0x00B91860)
#define   DBG_CSR_INTR_DSB_SEL8___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL8___POR            0x23222120
#define   DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___POR 0x23
#define   DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___POR 0x22
#define   DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___POR 0x21
#define   DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___POR 0x20
#define   DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL8___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL8___S                            0

#define DBG_CSR_INTR_DSB_SEL9                     (0x00B91864)
#define   DBG_CSR_INTR_DSB_SEL9___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL9___POR            0x27262524
#define   DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___POR 0x27
#define   DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___POR 0x26
#define   DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___POR 0x25
#define   DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___POR 0x24
#define   DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL9___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL9___S                            0

#define DBG_CSR_INTR_DSB_SEL10                    (0x00B91868)
#define   DBG_CSR_INTR_DSB_SEL10___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL10___POR           0x2B2A2928
#define   DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___POR 0x2B
#define   DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___POR 0x2A
#define   DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___POR 0x29
#define   DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___POR 0x28
#define   DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL10___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL10___S                           0

#define DBG_CSR_INTR_DSB_SEL11                    (0x00B9186C)
#define   DBG_CSR_INTR_DSB_SEL11___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL11___POR           0x2F2E2D2C
#define   DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___POR 0x2F
#define   DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___POR 0x2E
#define   DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___POR 0x2D
#define   DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___POR 0x2C
#define   DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL11___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL11___S                           0

#define DBG_CSR_INTR_DSB_SEL12                    (0x00B91870)
#define   DBG_CSR_INTR_DSB_SEL12___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL12___POR           0x33323130
#define   DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___POR 0x33
#define   DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___POR 0x32
#define   DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___POR 0x31
#define   DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___POR 0x30
#define   DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL12___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL12___S                           0

#define DBG_CSR_INTR_DSB_SEL13                    (0x00B91874)
#define   DBG_CSR_INTR_DSB_SEL13___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL13___POR           0x37363534
#define   DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___POR 0x37
#define   DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___POR 0x36
#define   DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___POR 0x35
#define   DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___POR 0x34
#define   DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL13___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL13___S                           0

#define DBG_CSR_INTR_DSB_SEL14                    (0x00B91878)
#define   DBG_CSR_INTR_DSB_SEL14___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL14___POR           0x3B3A3938
#define   DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___POR 0x3B
#define   DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___POR 0x3A
#define   DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___POR 0x39
#define   DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___POR 0x38
#define   DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL14___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL14___S                           0

#define DBG_CSR_INTR_DSB_SEL15                    (0x00B9187C)
#define   DBG_CSR_INTR_DSB_SEL15___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_DSB_SEL15___POR           0x3F3E3D3C
#define   DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___POR 0x3F
#define   DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___POR 0x3E
#define   DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___POR 0x3D
#define   DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___POR 0x3C
#define   DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___M 0xFF000000
#define   DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___S              24
#define   DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___S              16
#define   DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___S               8
#define   DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___M 0x000000FF
#define   DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___S               0
#define   DBG_CSR_INTR_DSB_SEL15___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_DSB_SEL15___S                           0

#define DBG_CSR_INTR_CTI_SEL0                     (0x00B91880)
#define   DBG_CSR_INTR_CTI_SEL0___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL0___POR            0x03020100
#define   DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___POR 0x03
#define   DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___POR 0x02
#define   DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___POR 0x01
#define   DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___POR 0x00
#define   DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL0___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL0___S                            0

#define DBG_CSR_INTR_CTI_SEL1                     (0x00B91884)
#define   DBG_CSR_INTR_CTI_SEL1___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL1___POR            0x07060504
#define   DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___POR 0x07
#define   DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___POR 0x06
#define   DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___POR 0x05
#define   DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___POR 0x04
#define   DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL1___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL1___S                            0

#define DBG_CSR_INTR_CTI_SEL2                     (0x00B91888)
#define   DBG_CSR_INTR_CTI_SEL2___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL2___POR            0x0B0A0908
#define   DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___POR 0x0B
#define   DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___POR 0x0A
#define   DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___POR 0x09
#define   DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___POR 0x08
#define   DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL2___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL2___S                            0

#define DBG_CSR_INTR_CTI_SEL3                     (0x00B9188C)
#define   DBG_CSR_INTR_CTI_SEL3___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL3___POR            0x0F0E0D0C
#define   DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___POR 0x0F
#define   DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___POR 0x0E
#define   DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___POR 0x0D
#define   DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___POR 0x0C
#define   DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL3___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL3___S                            0

#define DBG_CSR_INTR_CTI_SEL4                     (0x00B91890)
#define   DBG_CSR_INTR_CTI_SEL4___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL4___POR            0x13121110
#define   DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___POR 0x13
#define   DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___POR 0x12
#define   DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___POR 0x11
#define   DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___POR 0x10
#define   DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL4___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL4___S                            0

#define DBG_CSR_INTR_CTI_SEL5                     (0x00B91894)
#define   DBG_CSR_INTR_CTI_SEL5___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL5___POR            0x17161514
#define   DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___POR 0x17
#define   DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___POR 0x16
#define   DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___POR 0x15
#define   DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___POR 0x14
#define   DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL5___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL5___S                            0

#define DBG_CSR_INTR_CTI_SEL6                     (0x00B91898)
#define   DBG_CSR_INTR_CTI_SEL6___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL6___POR            0x1B1A1918
#define   DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___POR 0x1B
#define   DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___POR 0x1A
#define   DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___POR 0x19
#define   DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___POR 0x18
#define   DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL6___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL6___S                            0

#define DBG_CSR_INTR_CTI_SEL7                     (0x00B9189C)
#define   DBG_CSR_INTR_CTI_SEL7___RWC               QCSR_REG_RW    
#define   DBG_CSR_INTR_CTI_SEL7___POR            0x1F1E1D1C
#define   DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___POR 0x1F
#define   DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___POR 0x1E
#define   DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___POR 0x1D
#define   DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___POR 0x1C
#define   DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___M 0xFF000000
#define   DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___S              24
#define   DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___M 0x00FF0000
#define   DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___S              16
#define   DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___M 0x0000FF00
#define   DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___S               8
#define   DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___M 0x000000FF
#define   DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___S               0
#define   DBG_CSR_INTR_CTI_SEL7___M              0xFFFFFFFF   
#define   DBG_CSR_INTR_CTI_SEL7___S                            0

#define DBG_CSR_INTR_ANY_MASK0                    (0x00B918C0)
#define   DBG_CSR_INTR_ANY_MASK0___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK0___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK0___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK0___S                           0

#define DBG_CSR_INTR_ANY_MASK1                    (0x00B918C4)
#define   DBG_CSR_INTR_ANY_MASK1___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK1___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK1___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK1___S                           0

#define DBG_CSR_INTR_ANY_MASK2                    (0x00B918C8)
#define   DBG_CSR_INTR_ANY_MASK2___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK2___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK2___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK2___S                           0

#define DBG_CSR_INTR_ANY_MASK3                    (0x00B918CC)
#define   DBG_CSR_INTR_ANY_MASK3___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK3___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK3___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK3___S                           0

#define DBG_CSR_INTR_ANY_MASK4                    (0x00B918D0)
#define   DBG_CSR_INTR_ANY_MASK4___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK4___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK4___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK4___S                           0

#define DBG_CSR_INTR_ANY_MASK5                    (0x00B918D4)
#define   DBG_CSR_INTR_ANY_MASK5___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK5___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK5___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK5___S                           0

#define DBG_CSR_INTR_ANY_MASK6                    (0x00B918D8)
#define   DBG_CSR_INTR_ANY_MASK6___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK6___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK6___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK6___S                           0

#define DBG_CSR_INTR_ANY_MASK7                    (0x00B918DC)
#define   DBG_CSR_INTR_ANY_MASK7___RWC              QCSR_REG_RW    
#define   DBG_CSR_INTR_ANY_MASK7___POR           0xFFFFFFFF
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___POR 0x1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___M 0x80000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___S              31
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___M 0x40000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___S              30
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___M 0x20000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___S              29
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___M 0x10000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___S              28
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___M 0x08000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___S              27
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___M 0x04000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___S              26
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___M 0x02000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___S              25
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___M 0x01000000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___S              24
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___M 0x00800000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___S              23
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___M 0x00400000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___S              22
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___M 0x00200000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___S              21
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___M 0x00100000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___S              20
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___M 0x00080000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___S              19
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___M 0x00040000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___S              18
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___M 0x00020000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___S              17
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___M 0x00010000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___S              16
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___M 0x00008000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___S              15
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___M 0x00004000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___S              14
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___M 0x00002000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___S              13
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___M 0x00001000
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___S              12
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___M 0x00000800
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___S              11
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___M 0x00000400
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___S              10
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___M 0x00000200
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___S               9
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___M 0x00000100
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___S               8
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___M 0x00000080
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___S               7
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___M 0x00000040
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___S               6
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___M 0x00000020
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___S               5
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___M 0x00000010
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___S               4
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___M 0x00000008
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___S               3
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___M 0x00000004
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___S               2
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___M 0x00000002
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___S               1
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___M 0x00000001
#define   DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___S               0
#define   DBG_CSR_INTR_ANY_MASK7___M             0xFFFFFFFF   
#define   DBG_CSR_INTR_ANY_MASK7___S                           0

#define DBG_CSR_CS_ITCTL                          (0x00B91F00)
#define   DBG_CSR_CS_ITCTL___RWC                    QCSR_REG_RO    
#define   DBG_CSR_CS_ITCTL___POR                 0x00000000
#define   DBG_CSR_CS_ITCTL__RFU___POR            0x00000000
#define   DBG_CSR_CS_ITCTL__RFU___M              0xFFFFFFFF
#define   DBG_CSR_CS_ITCTL__RFU___S                            0
#define   DBG_CSR_CS_ITCTL___M                   0xFFFFFFFF   
#define   DBG_CSR_CS_ITCTL___S                                 0

#define DBG_CSR_CS_CLAIMSET                       (0x00B91FA0)
#define   DBG_CSR_CS_CLAIMSET___RWC                 QCSR_REG_RO    
#define   DBG_CSR_CS_CLAIMSET___POR              0x00000000
#define   DBG_CSR_CS_CLAIMSET__RFU___POR         0x00000000
#define   DBG_CSR_CS_CLAIMSET__RFU___M           0xFFFFFFFF
#define   DBG_CSR_CS_CLAIMSET__RFU___S                         0
#define   DBG_CSR_CS_CLAIMSET___M                0xFFFFFFFF   
#define   DBG_CSR_CS_CLAIMSET___S                              0

#define DBG_CSR_CS_CLAIMCLR                       (0x00B91FA4)
#define   DBG_CSR_CS_CLAIMCLR___RWC                 QCSR_REG_RO    
#define   DBG_CSR_CS_CLAIMCLR___POR              0x00000000
#define   DBG_CSR_CS_CLAIMCLR__RFU___POR         0x00000000
#define   DBG_CSR_CS_CLAIMCLR__RFU___M           0xFFFFFFFF
#define   DBG_CSR_CS_CLAIMCLR__RFU___S                         0
#define   DBG_CSR_CS_CLAIMCLR___M                0xFFFFFFFF   
#define   DBG_CSR_CS_CLAIMCLR___S                              0

#define DBG_CSR_CS_LOCKACCESS                     (0x00B91FB0)
#define   DBG_CSR_CS_LOCKACCESS___RWC               QCSR_REG_RO    
#define   DBG_CSR_CS_LOCKACCESS___POR            0x00000000
#define   DBG_CSR_CS_LOCKACCESS__RFU___POR       0x00000000
#define   DBG_CSR_CS_LOCKACCESS__RFU___M         0xFFFFFFFF
#define   DBG_CSR_CS_LOCKACCESS__RFU___S                       0
#define   DBG_CSR_CS_LOCKACCESS___M              0xFFFFFFFF   
#define   DBG_CSR_CS_LOCKACCESS___S                            0

#define DBG_CSR_CS_LOCKSTATUS                     (0x00B91FB4)
#define   DBG_CSR_CS_LOCKSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CSR_CS_LOCKSTATUS___POR            0x00000000
#define   DBG_CSR_CS_LOCKSTATUS__RFU___POR       0x00000000
#define   DBG_CSR_CS_LOCKSTATUS__RFU___M         0xFFFFFFFF
#define   DBG_CSR_CS_LOCKSTATUS__RFU___S                       0
#define   DBG_CSR_CS_LOCKSTATUS___M              0xFFFFFFFF   
#define   DBG_CSR_CS_LOCKSTATUS___S                            0

#define DBG_CSR_CS_AUTHSTATUS                     (0x00B91FB8)
#define   DBG_CSR_CS_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CSR_CS_AUTHSTATUS___POR            0x00000000
#define   DBG_CSR_CS_AUTHSTATUS__SI___POR        0x0
#define   DBG_CSR_CS_AUTHSTATUS__NSI___POR       0x0
#define   DBG_CSR_CS_AUTHSTATUS__SNI___POR       0x0
#define   DBG_CSR_CS_AUTHSTATUS__NSNI___POR      0x0
#define   DBG_CSR_CS_AUTHSTATUS__SI___M          0x000000C0
#define   DBG_CSR_CS_AUTHSTATUS__SI___S                        6
#define   DBG_CSR_CS_AUTHSTATUS__NSI___M         0x00000030
#define   DBG_CSR_CS_AUTHSTATUS__NSI___S                       4
#define   DBG_CSR_CS_AUTHSTATUS__SNI___M         0x0000000C
#define   DBG_CSR_CS_AUTHSTATUS__SNI___S                       2
#define   DBG_CSR_CS_AUTHSTATUS__NSNI___M        0x00000003
#define   DBG_CSR_CS_AUTHSTATUS__NSNI___S                      0
#define   DBG_CSR_CS_AUTHSTATUS___M              0x000000FF   
#define   DBG_CSR_CS_AUTHSTATUS___S                            0

#define DBG_CSR_CS_DEVARCH                        (0x00B91FBC)
#define   DBG_CSR_CS_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CSR_CS_DEVARCH___POR               0x0E100000
#define   DBG_CSR_CS_DEVARCH__ARCHITECT___POR    0x070
#define   DBG_CSR_CS_DEVARCH__PRESENT___POR      0x1
#define   DBG_CSR_CS_DEVARCH__REVISION___POR     0x0
#define   DBG_CSR_CS_DEVARCH__ARCHID___POR       0x0000
#define   DBG_CSR_CS_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CSR_CS_DEVARCH__ARCHITECT___S                   21
#define   DBG_CSR_CS_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CSR_CS_DEVARCH__PRESENT___S                     20
#define   DBG_CSR_CS_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CSR_CS_DEVARCH__REVISION___S                    16
#define   DBG_CSR_CS_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CSR_CS_DEVARCH__ARCHID___S                       0
#define   DBG_CSR_CS_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CSR_CS_DEVARCH___S                               0

#define DBG_CSR_CS_DEVID2                         (0x00B91FC0)
#define   DBG_CSR_CS_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CSR_CS_DEVID2___POR                0x00000000
#define   DBG_CSR_CS_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CSR_CS_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CSR_CS_DEVID2__IMPLDEF___S                       0
#define   DBG_CSR_CS_DEVID2___M                  0x00000001   
#define   DBG_CSR_CS_DEVID2___S                                0

#define DBG_CSR_CS_DEVID1                         (0x00B91FC4)
#define   DBG_CSR_CS_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CSR_CS_DEVID1___POR                0x00000000
#define   DBG_CSR_CS_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CSR_CS_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CSR_CS_DEVID1__IMPLDEF___S                       0
#define   DBG_CSR_CS_DEVID1___M                  0x00000001   
#define   DBG_CSR_CS_DEVID1___S                                0

#define DBG_CSR_CS_DEVICEID                       (0x00B91FC8)
#define   DBG_CSR_CS_DEVICEID___RWC                 QCSR_REG_RO    
#define   DBG_CSR_CS_DEVICEID___POR              0x00000000
#define   DBG_CSR_CS_DEVICEID__RFU___POR         0x000000
#define   DBG_CSR_CS_DEVICEID__DEVID___POR       0x00
#define   DBG_CSR_CS_DEVICEID__RFU___M           0xFFFFFF00
#define   DBG_CSR_CS_DEVICEID__RFU___S                         8
#define   DBG_CSR_CS_DEVICEID__DEVID___M         0x000000FF
#define   DBG_CSR_CS_DEVICEID__DEVID___S                       0
#define   DBG_CSR_CS_DEVICEID___M                0xFFFFFFFF   
#define   DBG_CSR_CS_DEVICEID___S                              0

#define DBG_CSR_CS_DEVICETYPE                     (0x00B91FCC)
#define   DBG_CSR_CS_DEVICETYPE___RWC               QCSR_REG_RO    
#define   DBG_CSR_CS_DEVICETYPE___POR            0x00000004
#define   DBG_CSR_CS_DEVICETYPE__RFU___POR       0x000000
#define   DBG_CSR_CS_DEVICETYPE__SUBTYPE___POR   0x0
#define   DBG_CSR_CS_DEVICETYPE__MAJTYPE___POR   0x4
#define   DBG_CSR_CS_DEVICETYPE__RFU___M         0xFFFFFF00
#define   DBG_CSR_CS_DEVICETYPE__RFU___S                       8
#define   DBG_CSR_CS_DEVICETYPE__SUBTYPE___M     0x000000F0
#define   DBG_CSR_CS_DEVICETYPE__SUBTYPE___S                   4
#define   DBG_CSR_CS_DEVICETYPE__MAJTYPE___M     0x0000000F
#define   DBG_CSR_CS_DEVICETYPE__MAJTYPE___S                   0
#define   DBG_CSR_CS_DEVICETYPE___M              0xFFFFFFFF   
#define   DBG_CSR_CS_DEVICETYPE___S                            0

#define DBG_CSR_CS_PERIPHID4                      (0x00B91FD0)
#define   DBG_CSR_CS_PERIPHID4___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID4___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID4__RFU___POR        0x000000
#define   DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0
#define   DBG_CSR_CS_PERIPHID4__RFU___M          0xFFFFFF00
#define   DBG_CSR_CS_PERIPHID4__RFU___S                        8
#define   DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___S               4
#define   DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___S               0
#define   DBG_CSR_CS_PERIPHID4___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID4___S                             0

#define DBG_CSR_CS_PERIPHID5                      (0x00B91FD4)
#define   DBG_CSR_CS_PERIPHID5___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID5___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID5__RFU___POR        0x00000000
#define   DBG_CSR_CS_PERIPHID5__RFU___M          0xFFFFFFFF
#define   DBG_CSR_CS_PERIPHID5__RFU___S                        0
#define   DBG_CSR_CS_PERIPHID5___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID5___S                             0

#define DBG_CSR_CS_PERIPHID6                      (0x00B91FD8)
#define   DBG_CSR_CS_PERIPHID6___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID6___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID6__RFU___POR        0x00000000
#define   DBG_CSR_CS_PERIPHID6__RFU___M          0xFFFFFFFF
#define   DBG_CSR_CS_PERIPHID6__RFU___S                        0
#define   DBG_CSR_CS_PERIPHID6___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID6___S                             0

#define DBG_CSR_CS_PERIPHID7                      (0x00B91FDC)
#define   DBG_CSR_CS_PERIPHID7___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID7___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID7__RFU___POR        0x00000000
#define   DBG_CSR_CS_PERIPHID7__RFU___M          0xFFFFFFFF
#define   DBG_CSR_CS_PERIPHID7__RFU___S                        0
#define   DBG_CSR_CS_PERIPHID7___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID7___S                             0

#define DBG_CSR_CS_PERIPHID0                      (0x00B91FE0)
#define   DBG_CSR_CS_PERIPHID0___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID0___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID0__RFU___POR        0x000000
#define   DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___POR 0x00
#define   DBG_CSR_CS_PERIPHID0__RFU___M          0xFFFFFF00
#define   DBG_CSR_CS_PERIPHID0__RFU___S                        8
#define   DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___M  0x000000FF
#define   DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___S                0
#define   DBG_CSR_CS_PERIPHID0___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID0___S                             0

#define DBG_CSR_CS_PERIPHID1                      (0x00B91FE4)
#define   DBG_CSR_CS_PERIPHID1___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID1___POR             0x00000004
#define   DBG_CSR_CS_PERIPHID1__RFU___POR        0x000000
#define   DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___POR 0x0
#define   DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___POR 0x4
#define   DBG_CSR_CS_PERIPHID1__RFU___M          0xFFFFFF00
#define   DBG_CSR_CS_PERIPHID1__RFU___S                        8
#define   DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___S               4
#define   DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___M 0x0000000F
#define   DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___S               0
#define   DBG_CSR_CS_PERIPHID1___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID1___S                             0

#define DBG_CSR_CS_PERIPHID2                      (0x00B91FE8)
#define   DBG_CSR_CS_PERIPHID2___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID2___POR             0x00000018
#define   DBG_CSR_CS_PERIPHID2__RFU___POR        0x000000
#define   DBG_CSR_CS_PERIPHID2__MAJREV___POR     0x1
#define   DBG_CSR_CS_PERIPHID2__JEDEC___POR      0x1
#define   DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___POR 0x0
#define   DBG_CSR_CS_PERIPHID2__RFU___M          0xFFFFFF00
#define   DBG_CSR_CS_PERIPHID2__RFU___S                        8
#define   DBG_CSR_CS_PERIPHID2__MAJREV___M       0x000000F0
#define   DBG_CSR_CS_PERIPHID2__MAJREV___S                     4
#define   DBG_CSR_CS_PERIPHID2__JEDEC___M        0x00000008
#define   DBG_CSR_CS_PERIPHID2__JEDEC___S                      3
#define   DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___S               0
#define   DBG_CSR_CS_PERIPHID2___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID2___S                             0

#define DBG_CSR_CS_PERIPHID3                      (0x00B91FEC)
#define   DBG_CSR_CS_PERIPHID3___RWC                QCSR_REG_RO    
#define   DBG_CSR_CS_PERIPHID3___POR             0x00000000
#define   DBG_CSR_CS_PERIPHID3__RFU___POR        0x000000
#define   DBG_CSR_CS_PERIPHID3__REV_AND___POR    0x0
#define   DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_CSR_CS_PERIPHID3__RFU___M          0xFFFFFF00
#define   DBG_CSR_CS_PERIPHID3__RFU___S                        8
#define   DBG_CSR_CS_PERIPHID3__REV_AND___M      0x000000F0
#define   DBG_CSR_CS_PERIPHID3__REV_AND___S                    4
#define   DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___S               0
#define   DBG_CSR_CS_PERIPHID3___M               0xFFFFFFFF   
#define   DBG_CSR_CS_PERIPHID3___S                             0

#define DBG_CSR_CS_COMPID0                        (0x00B91FF0)
#define   DBG_CSR_CS_COMPID0___RWC                  QCSR_REG_RO    
#define   DBG_CSR_CS_COMPID0___POR               0x0000000D
#define   DBG_CSR_CS_COMPID0__RFU___POR          0x000000
#define   DBG_CSR_CS_COMPID0__PREAMBLE_7_0___POR 0x0D
#define   DBG_CSR_CS_COMPID0__RFU___M            0xFFFFFF00
#define   DBG_CSR_CS_COMPID0__RFU___S                          8
#define   DBG_CSR_CS_COMPID0__PREAMBLE_7_0___M   0x000000FF
#define   DBG_CSR_CS_COMPID0__PREAMBLE_7_0___S                 0
#define   DBG_CSR_CS_COMPID0___M                 0xFFFFFFFF   
#define   DBG_CSR_CS_COMPID0___S                               0

#define DBG_CSR_CS_COMPID1                        (0x00B91FF4)
#define   DBG_CSR_CS_COMPID1___RWC                  QCSR_REG_RO    
#define   DBG_CSR_CS_COMPID1___POR               0x00000090
#define   DBG_CSR_CS_COMPID1__RFU___POR          0x000000
#define   DBG_CSR_CS_COMPID1__PREAMBLE_15_12___POR 0x9
#define   DBG_CSR_CS_COMPID1__PREAMBLE_11_8___POR 0x0
#define   DBG_CSR_CS_COMPID1__RFU___M            0xFFFFFF00
#define   DBG_CSR_CS_COMPID1__RFU___S                          8
#define   DBG_CSR_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_CSR_CS_COMPID1__PREAMBLE_15_12___S               4
#define   DBG_CSR_CS_COMPID1__PREAMBLE_11_8___M  0x0000000F
#define   DBG_CSR_CS_COMPID1__PREAMBLE_11_8___S                0
#define   DBG_CSR_CS_COMPID1___M                 0xFFFFFFFF   
#define   DBG_CSR_CS_COMPID1___S                               0

#define DBG_CSR_CS_COMPID2                        (0x00B91FF8)
#define   DBG_CSR_CS_COMPID2___RWC                  QCSR_REG_RO    
#define   DBG_CSR_CS_COMPID2___POR               0x00000005
#define   DBG_CSR_CS_COMPID2__RFU___POR          0x000000
#define   DBG_CSR_CS_COMPID2__PREAMBLE_23_16___POR 0x05
#define   DBG_CSR_CS_COMPID2__RFU___M            0xFFFFFF00
#define   DBG_CSR_CS_COMPID2__RFU___S                          8
#define   DBG_CSR_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_CSR_CS_COMPID2__PREAMBLE_23_16___S               0
#define   DBG_CSR_CS_COMPID2___M                 0xFFFFFFFF   
#define   DBG_CSR_CS_COMPID2___S                               0

#define DBG_CSR_CS_COMPID3                        (0x00B91FFC)
#define   DBG_CSR_CS_COMPID3___RWC                  QCSR_REG_RO    
#define   DBG_CSR_CS_COMPID3___POR               0x000000B1
#define   DBG_CSR_CS_COMPID3__RFU___POR          0x000000
#define   DBG_CSR_CS_COMPID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_CSR_CS_COMPID3__RFU___M            0xFFFFFF00
#define   DBG_CSR_CS_COMPID3__RFU___S                          8
#define   DBG_CSR_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_CSR_CS_COMPID3__PREAMBLE_31_24___S               0
#define   DBG_CSR_CS_COMPID3___M                 0xFFFFFFFF   
#define   DBG_CSR_CS_COMPID3___S                               0

#define DBG_TSGEN_CNTCR                           (0x00B92000)
#define   DBG_TSGEN_CNTCR___RWC                     QCSR_REG_RW    
#define   DBG_TSGEN_CNTCR___POR                  0x00000000
#define   DBG_TSGEN_CNTCR__CNTCR_HDBG___POR      0x0
#define   DBG_TSGEN_CNTCR__CNTCR_EN___POR        0x0
#define   DBG_TSGEN_CNTCR__CNTCR_HDBG___M        0x00000002
#define   DBG_TSGEN_CNTCR__CNTCR_HDBG___S                      1
#define   DBG_TSGEN_CNTCR__CNTCR_HDBG__LOW                   0x0
#define   DBG_TSGEN_CNTCR__CNTCR_HDBG__HIGH                  0x1
#define   DBG_TSGEN_CNTCR__CNTCR_EN___M          0x00000001
#define   DBG_TSGEN_CNTCR__CNTCR_EN___S                        0
#define   DBG_TSGEN_CNTCR__CNTCR_EN__LOW                     0x0
#define   DBG_TSGEN_CNTCR__CNTCR_EN__HIGH                    0x1
#define   DBG_TSGEN_CNTCR___M                    0x00000003   
#define   DBG_TSGEN_CNTCR___S                                  0

#define DBG_TSGEN_CNTSR                           (0x00B92004)
#define   DBG_TSGEN_CNTSR___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_CNTSR___POR                  0x00000000
#define   DBG_TSGEN_CNTSR__CNTSR_DBGH___POR      0x0
#define   DBG_TSGEN_CNTSR__CNTSR_DBGH___M        0x00000002
#define   DBG_TSGEN_CNTSR__CNTSR_DBGH___S                      1
#define   DBG_TSGEN_CNTSR__CNTSR_DBGH__LOW                   0x0
#define   DBG_TSGEN_CNTSR__CNTSR_DBGH__HIGH                  0x1
#define   DBG_TSGEN_CNTSR___M                    0x00000002   
#define   DBG_TSGEN_CNTSR___S                                  1

#define DBG_TSGEN_CNTCVL                          (0x00B92008)
#define   DBG_TSGEN_CNTCVL___RWC                    QCSR_REG_RW    
#define   DBG_TSGEN_CNTCVL___POR                 0x00000000
#define   DBG_TSGEN_CNTCVL__CNTCVL_L_32___POR    0x00000000
#define   DBG_TSGEN_CNTCVL__CNTCVL_L_32___M      0xFFFFFFFF
#define   DBG_TSGEN_CNTCVL__CNTCVL_L_32___S                    0
#define   DBG_TSGEN_CNTCVL___M                   0xFFFFFFFF   
#define   DBG_TSGEN_CNTCVL___S                                 0

#define DBG_TSGEN_CNTCVU                          (0x00B9200C)
#define   DBG_TSGEN_CNTCVU___RWC                    QCSR_REG_RW    
#define   DBG_TSGEN_CNTCVU___POR                 0x00000000
#define   DBG_TSGEN_CNTCVU__CNTCVU_U_32___POR    0x00000000
#define   DBG_TSGEN_CNTCVU__CNTCVU_U_32___M      0xFFFFFFFF
#define   DBG_TSGEN_CNTCVU__CNTCVU_U_32___S                    0
#define   DBG_TSGEN_CNTCVU___M                   0xFFFFFFFF   
#define   DBG_TSGEN_CNTCVU___S                                 0

#define DBG_TSGEN_CNTFID0                         (0x00B92020)
#define   DBG_TSGEN_CNTFID0___RWC                   QCSR_REG_RW    
#define   DBG_TSGEN_CNTFID0___POR                0x00000000
#define   DBG_TSGEN_CNTFID0__CNTFID0___POR       0x00000000
#define   DBG_TSGEN_CNTFID0__CNTFID0___M         0xFFFFFFFF
#define   DBG_TSGEN_CNTFID0__CNTFID0___S                       0
#define   DBG_TSGEN_CNTFID0___M                  0xFFFFFFFF   
#define   DBG_TSGEN_CNTFID0___S                                0

#define DBG_TSGEN_PIDR0                           (0x00B92FE0)
#define   DBG_TSGEN_PIDR0___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_PIDR0___POR                  0x00000001
#define   DBG_TSGEN_PIDR0__PART_0___POR          0x01
#define   DBG_TSGEN_PIDR0__PART_0___M            0x000000FF
#define   DBG_TSGEN_PIDR0__PART_0___S                          0
#define   DBG_TSGEN_PIDR0__PART_0__TIME_STAMP_GENERATOR_PART_NUMBER_BITS7TO0            0x01
#define   DBG_TSGEN_PIDR0___M                    0x000000FF   
#define   DBG_TSGEN_PIDR0___S                                  0

#define DBG_TSGEN_PIDR1                           (0x00B92FE4)
#define   DBG_TSGEN_PIDR1___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_PIDR1___POR                  0x000000B1
#define   DBG_TSGEN_PIDR1__DES_0___POR           0xB
#define   DBG_TSGEN_PIDR1__PART_1___POR          0x1
#define   DBG_TSGEN_PIDR1__DES_0___M             0x000000F0
#define   DBG_TSGEN_PIDR1__DES_0___S                           4
#define   DBG_TSGEN_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_BITS7TO0             0xB
#define   DBG_TSGEN_PIDR1__PART_1___M            0x0000000F
#define   DBG_TSGEN_PIDR1__PART_1___S                          0
#define   DBG_TSGEN_PIDR1__PART_1__TIME_STAMP_GENERATOR_PART_NUMBER_BITS11TO8             0x1
#define   DBG_TSGEN_PIDR1___M                    0x000000FF   
#define   DBG_TSGEN_PIDR1___S                                  0

#define DBG_TSGEN_PIDR2                           (0x00B92FE8)
#define   DBG_TSGEN_PIDR2___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_PIDR2___POR                  0x0000000B
#define   DBG_TSGEN_PIDR2__REVISION___POR        0x0
#define   DBG_TSGEN_PIDR2__JEDEC___POR           0x1
#define   DBG_TSGEN_PIDR2__DES_1___POR           0x3
#define   DBG_TSGEN_PIDR2__REVISION___M          0x000000F0
#define   DBG_TSGEN_PIDR2__REVISION___S                        4
#define   DBG_TSGEN_PIDR2__REVISION__R0P1                    0x1
#define   DBG_TSGEN_PIDR2__JEDEC___M             0x00000008
#define   DBG_TSGEN_PIDR2__JEDEC___S                           3
#define   DBG_TSGEN_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_TSGEN_PIDR2__DES_1___M             0x00000007
#define   DBG_TSGEN_PIDR2__DES_1___S                           0
#define   DBG_TSGEN_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_BITS6TO4             0x3
#define   DBG_TSGEN_PIDR2___M                    0x000000FF   
#define   DBG_TSGEN_PIDR2___S                                  0

#define DBG_TSGEN_PIDR3                           (0x00B92FEC)
#define   DBG_TSGEN_PIDR3___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_PIDR3___POR                  0x00000000
#define   DBG_TSGEN_PIDR3__REVAND___POR          0x0
#define   DBG_TSGEN_PIDR3__CMOD___POR            0x0
#define   DBG_TSGEN_PIDR3__REVAND___M            0x000000F0
#define   DBG_TSGEN_PIDR3__REVAND___S                          4
#define   DBG_TSGEN_PIDR3__REVAND__NO_MODS                   0x0
#define   DBG_TSGEN_PIDR3__CMOD___M              0x0000000F
#define   DBG_TSGEN_PIDR3__CMOD___S                            0
#define   DBG_TSGEN_PIDR3__CMOD__NO_MODS                     0x0
#define   DBG_TSGEN_PIDR3___M                    0x000000FF   
#define   DBG_TSGEN_PIDR3___S                                  0

#define DBG_TSGEN_PIDR4                           (0x00B92FD0)
#define   DBG_TSGEN_PIDR4___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_PIDR4___POR                  0x00000004
#define   DBG_TSGEN_PIDR4__SIZE___POR            0x0
#define   DBG_TSGEN_PIDR4__DES_2___POR           0x4
#define   DBG_TSGEN_PIDR4__SIZE___M              0x000000F0
#define   DBG_TSGEN_PIDR4__SIZE___S                            4
#define   DBG_TSGEN_PIDR4__SIZE__SIZE_4KB                    0x0
#define   DBG_TSGEN_PIDR4__DES_2___M             0x0000000F
#define   DBG_TSGEN_PIDR4__DES_2___S                           0
#define   DBG_TSGEN_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_TSGEN_PIDR4___M                    0x000000FF   
#define   DBG_TSGEN_PIDR4___S                                  0

#define DBG_TSGEN_PIDR5                           (0x00B92FD4)
#define   DBG_TSGEN_PIDR5___RWC                     QCSR_REG_RW    
#define   DBG_TSGEN_PIDR5__PIDR5___M             0xFFFFFFFF
#define   DBG_TSGEN_PIDR5__PIDR5___S                           0
#define   DBG_TSGEN_PIDR5___M                    0xFFFFFFFF   
#define   DBG_TSGEN_PIDR5___S                                  0

#define DBG_TSGEN_PIDR6                           (0x00B92FD8)
#define   DBG_TSGEN_PIDR6___RWC                     QCSR_REG_RW    
#define   DBG_TSGEN_PIDR6__PIDR6___M             0xFFFFFFFF
#define   DBG_TSGEN_PIDR6__PIDR6___S                           0
#define   DBG_TSGEN_PIDR6___M                    0xFFFFFFFF   
#define   DBG_TSGEN_PIDR6___S                                  0

#define DBG_TSGEN_PIDR7                           (0x00B92FDC)
#define   DBG_TSGEN_PIDR7___RWC                     QCSR_REG_RW    
#define   DBG_TSGEN_PIDR7__PIDR7___M             0xFFFFFFFF
#define   DBG_TSGEN_PIDR7__PIDR7___S                           0
#define   DBG_TSGEN_PIDR7___M                    0xFFFFFFFF   
#define   DBG_TSGEN_PIDR7___S                                  0

#define DBG_TSGEN_CIDR0                           (0x00B92FF0)
#define   DBG_TSGEN_CIDR0___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_CIDR0___POR                  0x0000000D
#define   DBG_TSGEN_CIDR0__PRMBL_0___POR         0x0D
#define   DBG_TSGEN_CIDR0__PRMBL_0___M           0x000000FF
#define   DBG_TSGEN_CIDR0__PRMBL_0___S                         0
#define   DBG_TSGEN_CIDR0__PRMBL_0__ID_VALUE_0D             0x0D
#define   DBG_TSGEN_CIDR0___M                    0x000000FF   
#define   DBG_TSGEN_CIDR0___S                                  0

#define DBG_TSGEN_CIDR1                           (0x00B92FF4)
#define   DBG_TSGEN_CIDR1___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_CIDR1___POR                  0x000000F0
#define   DBG_TSGEN_CIDR1__CLASS___POR           0xF
#define   DBG_TSGEN_CIDR1__PRMBL_1___POR         0x0
#define   DBG_TSGEN_CIDR1__CLASS___M             0x000000F0
#define   DBG_TSGEN_CIDR1__CLASS___S                           4
#define   DBG_TSGEN_CIDR1__CLASS__PRIMECELL_COMPONENT             0xF
#define   DBG_TSGEN_CIDR1__PRMBL_1___M           0x0000000F
#define   DBG_TSGEN_CIDR1__PRMBL_1___S                         0
#define   DBG_TSGEN_CIDR1__PRMBL_1__ID_VALUE_0               0x0
#define   DBG_TSGEN_CIDR1___M                    0x000000FF   
#define   DBG_TSGEN_CIDR1___S                                  0

#define DBG_TSGEN_CIDR2                           (0x00B92FF8)
#define   DBG_TSGEN_CIDR2___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_CIDR2___POR                  0x00000005
#define   DBG_TSGEN_CIDR2__PRMBL_2___POR         0x05
#define   DBG_TSGEN_CIDR2__PRMBL_2___M           0x000000FF
#define   DBG_TSGEN_CIDR2__PRMBL_2___S                         0
#define   DBG_TSGEN_CIDR2__PRMBL_2__ID_VALUE_05             0x05
#define   DBG_TSGEN_CIDR2___M                    0x000000FF   
#define   DBG_TSGEN_CIDR2___S                                  0

#define DBG_TSGEN_CIDR3                           (0x00B92FFC)
#define   DBG_TSGEN_CIDR3___RWC                     QCSR_REG_RO    
#define   DBG_TSGEN_CIDR3___POR                  0x000000B1
#define   DBG_TSGEN_CIDR3__PRMBL_3___POR         0xB1
#define   DBG_TSGEN_CIDR3__PRMBL_3___M           0x000000FF
#define   DBG_TSGEN_CIDR3__PRMBL_3___S                         0
#define   DBG_TSGEN_CIDR3__PRMBL_3__ID_VALUE_B1             0xB1
#define   DBG_TSGEN_CIDR3___M                    0x000000FF   
#define   DBG_TSGEN_CIDR3___S                                  0

#define DBG_CTIDBG_CTICONTROL                     (0x00B94000)
#define   DBG_CTIDBG_CTICONTROL___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTICONTROL___POR            0x00000000
#define   DBG_CTIDBG_CTICONTROL__GLBEN___POR     0x0
#define   DBG_CTIDBG_CTICONTROL__GLBEN___M       0x00000001
#define   DBG_CTIDBG_CTICONTROL__GLBEN___S                     0
#define   DBG_CTIDBG_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_CTIDBG_CTICONTROL__GLBEN__ENABLED              0x1
#define   DBG_CTIDBG_CTICONTROL___M              0x00000001   
#define   DBG_CTIDBG_CTICONTROL___S                            0

#define DBG_CTIDBG_CTIINTACK                      (0x00B94010)
#define   DBG_CTIDBG_CTIINTACK___RWC                QCSR_REG_WO    
#define   DBG_CTIDBG_CTIINTACK___POR             0x00000000
#define   DBG_CTIDBG_CTIINTACK__INTACK___POR     0x00000000
#define   DBG_CTIDBG_CTIINTACK__INTACK___M       0xFFFFFFFF
#define   DBG_CTIDBG_CTIINTACK__INTACK___S                     0
#define   DBG_CTIDBG_CTIINTACK___M               0xFFFFFFFF   
#define   DBG_CTIDBG_CTIINTACK___S                             0

#define DBG_CTIDBG_CTIAPPSET                      (0x00B94014)
#define   DBG_CTIDBG_CTIAPPSET___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIAPPSET___POR             0x00000000
#define   DBG_CTIDBG_CTIAPPSET__APPSET___POR     0x00
#define   DBG_CTIDBG_CTIAPPSET__APPSET___M       0x000000FF
#define   DBG_CTIDBG_CTIAPPSET__APPSET___S                     0
#define   DBG_CTIDBG_CTIAPPSET___M               0x000000FF   
#define   DBG_CTIDBG_CTIAPPSET___S                             0

#define DBG_CTIDBG_CTIAPPCLEAR                    (0x00B94018)
#define   DBG_CTIDBG_CTIAPPCLEAR___RWC              QCSR_REG_WO    
#define   DBG_CTIDBG_CTIAPPCLEAR___POR           0x00000000
#define   DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___M   0x000000FF
#define   DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___S                 0
#define   DBG_CTIDBG_CTIAPPCLEAR___M             0x000000FF   
#define   DBG_CTIDBG_CTIAPPCLEAR___S                           0

#define DBG_CTIDBG_CTIAPPPULSE                    (0x00B9401C)
#define   DBG_CTIDBG_CTIAPPPULSE___RWC              QCSR_REG_WO    
#define   DBG_CTIDBG_CTIAPPPULSE___POR           0x00000000
#define   DBG_CTIDBG_CTIAPPPULSE__APPULSE___POR  0x00
#define   DBG_CTIDBG_CTIAPPPULSE__APPULSE___M    0x000000FF
#define   DBG_CTIDBG_CTIAPPPULSE__APPULSE___S                  0
#define   DBG_CTIDBG_CTIAPPPULSE___M             0x000000FF   
#define   DBG_CTIDBG_CTIAPPPULSE___S                           0

#define DBG_CTIDBG_CTIINEN0                       (0x00B94020)
#define   DBG_CTIDBG_CTIINEN0___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN0___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN0__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN0__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN0__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN0___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN0___S                              0

#define DBG_CTIDBG_CTIINEN1                       (0x00B94024)
#define   DBG_CTIDBG_CTIINEN1___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN1___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN1__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN1__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN1__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN1___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN1___S                              0

#define DBG_CTIDBG_CTIINEN2                       (0x00B94028)
#define   DBG_CTIDBG_CTIINEN2___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN2___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN2__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN2__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN2__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN2___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN2___S                              0

#define DBG_CTIDBG_CTIINEN3                       (0x00B9402C)
#define   DBG_CTIDBG_CTIINEN3___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN3___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN3__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN3__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN3__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN3___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN3___S                              0

#define DBG_CTIDBG_CTIINEN4                       (0x00B94030)
#define   DBG_CTIDBG_CTIINEN4___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN4___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN4__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN4__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN4__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN4___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN4___S                              0

#define DBG_CTIDBG_CTIINEN5                       (0x00B94034)
#define   DBG_CTIDBG_CTIINEN5___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN5___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN5__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN5__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN5__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN5___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN5___S                              0

#define DBG_CTIDBG_CTIINEN6                       (0x00B94038)
#define   DBG_CTIDBG_CTIINEN6___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN6___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN6__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN6__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN6__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN6___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN6___S                              0

#define DBG_CTIDBG_CTIINEN7                       (0x00B9403C)
#define   DBG_CTIDBG_CTIINEN7___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN7___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN7__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN7__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN7__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN7___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN7___S                              0

#define DBG_CTIDBG_CTIINEN8                       (0x00B94040)
#define   DBG_CTIDBG_CTIINEN8___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN8___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN8__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN8__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN8__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN8___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN8___S                              0

#define DBG_CTIDBG_CTIINEN9                       (0x00B94044)
#define   DBG_CTIDBG_CTIINEN9___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN9___POR              0x00000000
#define   DBG_CTIDBG_CTIINEN9__TRIGINEN___POR    0x00
#define   DBG_CTIDBG_CTIINEN9__TRIGINEN___M      0x000000FF
#define   DBG_CTIDBG_CTIINEN9__TRIGINEN___S                    0
#define   DBG_CTIDBG_CTIINEN9___M                0x000000FF   
#define   DBG_CTIDBG_CTIINEN9___S                              0

#define DBG_CTIDBG_CTIINEN10                      (0x00B94048)
#define   DBG_CTIDBG_CTIINEN10___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN10___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN10__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN10__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN10__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN10___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN10___S                             0

#define DBG_CTIDBG_CTIINEN11                      (0x00B9404C)
#define   DBG_CTIDBG_CTIINEN11___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN11___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN11__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN11__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN11__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN11___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN11___S                             0

#define DBG_CTIDBG_CTIINEN12                      (0x00B94050)
#define   DBG_CTIDBG_CTIINEN12___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN12___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN12__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN12__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN12__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN12___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN12___S                             0

#define DBG_CTIDBG_CTIINEN13                      (0x00B94054)
#define   DBG_CTIDBG_CTIINEN13___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN13___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN13__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN13__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN13__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN13___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN13___S                             0

#define DBG_CTIDBG_CTIINEN14                      (0x00B94058)
#define   DBG_CTIDBG_CTIINEN14___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN14___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN14__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN14__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN14__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN14___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN14___S                             0

#define DBG_CTIDBG_CTIINEN15                      (0x00B9405C)
#define   DBG_CTIDBG_CTIINEN15___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN15___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN15__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN15__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN15__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN15___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN15___S                             0

#define DBG_CTIDBG_CTIINEN16                      (0x00B94060)
#define   DBG_CTIDBG_CTIINEN16___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN16___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN16__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN16__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN16__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN16___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN16___S                             0

#define DBG_CTIDBG_CTIINEN17                      (0x00B94064)
#define   DBG_CTIDBG_CTIINEN17___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN17___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN17__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN17__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN17__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN17___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN17___S                             0

#define DBG_CTIDBG_CTIINEN18                      (0x00B94068)
#define   DBG_CTIDBG_CTIINEN18___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN18___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN18__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN18__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN18__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN18___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN18___S                             0

#define DBG_CTIDBG_CTIINEN19                      (0x00B9406C)
#define   DBG_CTIDBG_CTIINEN19___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN19___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN19__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN19__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN19__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN19___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN19___S                             0

#define DBG_CTIDBG_CTIINEN20                      (0x00B94070)
#define   DBG_CTIDBG_CTIINEN20___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN20___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN20__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN20__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN20__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN20___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN20___S                             0

#define DBG_CTIDBG_CTIINEN21                      (0x00B94074)
#define   DBG_CTIDBG_CTIINEN21___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN21___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN21__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN21__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN21__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN21___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN21___S                             0

#define DBG_CTIDBG_CTIINEN22                      (0x00B94078)
#define   DBG_CTIDBG_CTIINEN22___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN22___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN22__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN22__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN22__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN22___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN22___S                             0

#define DBG_CTIDBG_CTIINEN23                      (0x00B9407C)
#define   DBG_CTIDBG_CTIINEN23___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN23___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN23__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN23__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN23__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN23___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN23___S                             0

#define DBG_CTIDBG_CTIINEN24                      (0x00B94080)
#define   DBG_CTIDBG_CTIINEN24___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN24___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN24__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN24__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN24__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN24___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN24___S                             0

#define DBG_CTIDBG_CTIINEN25                      (0x00B94084)
#define   DBG_CTIDBG_CTIINEN25___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN25___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN25__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN25__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN25__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN25___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN25___S                             0

#define DBG_CTIDBG_CTIINEN26                      (0x00B94088)
#define   DBG_CTIDBG_CTIINEN26___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN26___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN26__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN26__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN26__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN26___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN26___S                             0

#define DBG_CTIDBG_CTIINEN27                      (0x00B9408C)
#define   DBG_CTIDBG_CTIINEN27___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN27___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN27__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN27__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN27__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN27___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN27___S                             0

#define DBG_CTIDBG_CTIINEN28                      (0x00B94090)
#define   DBG_CTIDBG_CTIINEN28___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN28___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN28__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN28__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN28__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN28___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN28___S                             0

#define DBG_CTIDBG_CTIINEN29                      (0x00B94094)
#define   DBG_CTIDBG_CTIINEN29___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN29___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN29__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN29__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN29__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN29___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN29___S                             0

#define DBG_CTIDBG_CTIINEN30                      (0x00B94098)
#define   DBG_CTIDBG_CTIINEN30___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN30___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN30__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN30__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN30__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN30___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN30___S                             0

#define DBG_CTIDBG_CTIINEN31                      (0x00B9409C)
#define   DBG_CTIDBG_CTIINEN31___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIINEN31___POR             0x00000000
#define   DBG_CTIDBG_CTIINEN31__TRIGINEN___POR   0x00
#define   DBG_CTIDBG_CTIINEN31__TRIGINEN___M     0x000000FF
#define   DBG_CTIDBG_CTIINEN31__TRIGINEN___S                   0
#define   DBG_CTIDBG_CTIINEN31___M               0x000000FF   
#define   DBG_CTIDBG_CTIINEN31___S                             0

#define DBG_CTIDBG_CTIOUTEN0                      (0x00B940A0)
#define   DBG_CTIDBG_CTIOUTEN0___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN0___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN0___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN0___S                             0

#define DBG_CTIDBG_CTIOUTEN1                      (0x00B940A4)
#define   DBG_CTIDBG_CTIOUTEN1___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN1___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN1___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN1___S                             0

#define DBG_CTIDBG_CTIOUTEN2                      (0x00B940A8)
#define   DBG_CTIDBG_CTIOUTEN2___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN2___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN2___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN2___S                             0

#define DBG_CTIDBG_CTIOUTEN3                      (0x00B940AC)
#define   DBG_CTIDBG_CTIOUTEN3___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN3___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN3___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN3___S                             0

#define DBG_CTIDBG_CTIOUTEN4                      (0x00B940B0)
#define   DBG_CTIDBG_CTIOUTEN4___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN4___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN4___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN4___S                             0

#define DBG_CTIDBG_CTIOUTEN5                      (0x00B940B4)
#define   DBG_CTIDBG_CTIOUTEN5___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN5___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN5___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN5___S                             0

#define DBG_CTIDBG_CTIOUTEN6                      (0x00B940B8)
#define   DBG_CTIDBG_CTIOUTEN6___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN6___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN6___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN6___S                             0

#define DBG_CTIDBG_CTIOUTEN7                      (0x00B940BC)
#define   DBG_CTIDBG_CTIOUTEN7___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN7___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN7___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN7___S                             0

#define DBG_CTIDBG_CTIOUTEN8                      (0x00B940C0)
#define   DBG_CTIDBG_CTIOUTEN8___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN8___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN8___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN8___S                             0

#define DBG_CTIDBG_CTIOUTEN9                      (0x00B940C4)
#define   DBG_CTIDBG_CTIOUTEN9___RWC                QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN9___POR             0x00000000
#define   DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___POR  0x00
#define   DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___S                  0
#define   DBG_CTIDBG_CTIOUTEN9___M               0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN9___S                             0

#define DBG_CTIDBG_CTIOUTEN10                     (0x00B940C8)
#define   DBG_CTIDBG_CTIOUTEN10___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN10___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN10___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN10___S                            0

#define DBG_CTIDBG_CTIOUTEN11                     (0x00B940CC)
#define   DBG_CTIDBG_CTIOUTEN11___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN11___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN11___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN11___S                            0

#define DBG_CTIDBG_CTIOUTEN12                     (0x00B940D0)
#define   DBG_CTIDBG_CTIOUTEN12___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN12___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN12___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN12___S                            0

#define DBG_CTIDBG_CTIOUTEN13                     (0x00B940D4)
#define   DBG_CTIDBG_CTIOUTEN13___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN13___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN13___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN13___S                            0

#define DBG_CTIDBG_CTIOUTEN14                     (0x00B940D8)
#define   DBG_CTIDBG_CTIOUTEN14___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN14___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN14___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN14___S                            0

#define DBG_CTIDBG_CTIOUTEN15                     (0x00B940DC)
#define   DBG_CTIDBG_CTIOUTEN15___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN15___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN15___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN15___S                            0

#define DBG_CTIDBG_CTIOUTEN16                     (0x00B940E0)
#define   DBG_CTIDBG_CTIOUTEN16___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN16___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN16___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN16___S                            0

#define DBG_CTIDBG_CTIOUTEN17                     (0x00B940E4)
#define   DBG_CTIDBG_CTIOUTEN17___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN17___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN17___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN17___S                            0

#define DBG_CTIDBG_CTIOUTEN18                     (0x00B940E8)
#define   DBG_CTIDBG_CTIOUTEN18___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN18___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN18___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN18___S                            0

#define DBG_CTIDBG_CTIOUTEN19                     (0x00B940EC)
#define   DBG_CTIDBG_CTIOUTEN19___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN19___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN19___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN19___S                            0

#define DBG_CTIDBG_CTIOUTEN20                     (0x00B940F0)
#define   DBG_CTIDBG_CTIOUTEN20___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN20___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN20___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN20___S                            0

#define DBG_CTIDBG_CTIOUTEN21                     (0x00B940F4)
#define   DBG_CTIDBG_CTIOUTEN21___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN21___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN21___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN21___S                            0

#define DBG_CTIDBG_CTIOUTEN22                     (0x00B940F8)
#define   DBG_CTIDBG_CTIOUTEN22___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN22___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN22___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN22___S                            0

#define DBG_CTIDBG_CTIOUTEN23                     (0x00B940FC)
#define   DBG_CTIDBG_CTIOUTEN23___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN23___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN23___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN23___S                            0

#define DBG_CTIDBG_CTIOUTEN24                     (0x00B94100)
#define   DBG_CTIDBG_CTIOUTEN24___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN24___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN24___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN24___S                            0

#define DBG_CTIDBG_CTIOUTEN25                     (0x00B94104)
#define   DBG_CTIDBG_CTIOUTEN25___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN25___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN25___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN25___S                            0

#define DBG_CTIDBG_CTIOUTEN26                     (0x00B94108)
#define   DBG_CTIDBG_CTIOUTEN26___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN26___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN26___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN26___S                            0

#define DBG_CTIDBG_CTIOUTEN27                     (0x00B9410C)
#define   DBG_CTIDBG_CTIOUTEN27___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN27___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN27___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN27___S                            0

#define DBG_CTIDBG_CTIOUTEN28                     (0x00B94110)
#define   DBG_CTIDBG_CTIOUTEN28___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN28___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN28___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN28___S                            0

#define DBG_CTIDBG_CTIOUTEN29                     (0x00B94114)
#define   DBG_CTIDBG_CTIOUTEN29___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN29___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN29___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN29___S                            0

#define DBG_CTIDBG_CTIOUTEN30                     (0x00B94118)
#define   DBG_CTIDBG_CTIOUTEN30___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN30___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN30___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN30___S                            0

#define DBG_CTIDBG_CTIOUTEN31                     (0x00B9411C)
#define   DBG_CTIDBG_CTIOUTEN31___RWC               QCSR_REG_RW    
#define   DBG_CTIDBG_CTIOUTEN31___POR            0x00000000
#define   DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___POR 0x00
#define   DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___S                 0
#define   DBG_CTIDBG_CTIOUTEN31___M              0x000000FF   
#define   DBG_CTIDBG_CTIOUTEN31___S                            0

#define DBG_CTIDBG_CTITRIGINSTATUS                (0x00B94130)
#define   DBG_CTIDBG_CTITRIGINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_CTIDBG_CTITRIGINSTATUS__TRIGINSTATUS___M 0xFFFFFFFF
#define   DBG_CTIDBG_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_CTIDBG_CTITRIGINSTATUS___M         0xFFFFFFFF   
#define   DBG_CTIDBG_CTITRIGINSTATUS___S                       0

#define DBG_CTIDBG_CTITRIGOUTSTATUS               (0x00B94134)
#define   DBG_CTIDBG_CTITRIGOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_CTIDBG_CTITRIGOUTSTATUS___POR      0x00000000
#define   DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00000000
#define   DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0xFFFFFFFF
#define   DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_CTIDBG_CTITRIGOUTSTATUS___M        0xFFFFFFFF   
#define   DBG_CTIDBG_CTITRIGOUTSTATUS___S                      0

#define DBG_CTIDBG_CTICHINSTATUS                  (0x00B94138)
#define   DBG_CTIDBG_CTICHINSTATUS___RWC            QCSR_REG_RO    
#define   DBG_CTIDBG_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_CTIDBG_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_CTIDBG_CTICHINSTATUS___M           0x000000FF   
#define   DBG_CTIDBG_CTICHINSTATUS___S                         0

#define DBG_CTIDBG_CTICHOUTSTATUS                 (0x00B9413C)
#define   DBG_CTIDBG_CTICHOUTSTATUS___RWC           QCSR_REG_RO    
#define   DBG_CTIDBG_CTICHOUTSTATUS___POR        0x00000000
#define   DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_CTIDBG_CTICHOUTSTATUS___M          0x000000FF   
#define   DBG_CTIDBG_CTICHOUTSTATUS___S                        0

#define DBG_CTIDBG_CTIGATE                        (0x00B94140)
#define   DBG_CTIDBG_CTIGATE___RWC                  QCSR_REG_RW    
#define   DBG_CTIDBG_CTIGATE___POR               0x000000FF
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN7___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN6___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN5___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN4___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN3___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN2___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN1___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN0___POR   0x1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN7___M     0x00000080
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN7___S                   7
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN6___M     0x00000040
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN6___S                   6
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN5___M     0x00000020
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN5___S                   5
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN4___M     0x00000010
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN4___S                   4
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN3___M     0x00000008
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN3___S                   3
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN2___M     0x00000004
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN2___S                   2
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN1___M     0x00000002
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN1___S                   1
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN0___M     0x00000001
#define   DBG_CTIDBG_CTIGATE__CTIGATEEN0___S                   0
#define   DBG_CTIDBG_CTIGATE___M                 0x000000FF   
#define   DBG_CTIDBG_CTIGATE___S                               0

#define DBG_CTIDBG_ASICCTL                        (0x00B94144)
#define   DBG_CTIDBG_ASICCTL___RWC                  QCSR_REG_RW    
#define   DBG_CTIDBG_ASICCTL___POR               0x00000000
#define   DBG_CTIDBG_ASICCTL__ASICCTL___POR      0x00000000
#define   DBG_CTIDBG_ASICCTL__ASICCTL___M        0xFFFFFFFF
#define   DBG_CTIDBG_ASICCTL__ASICCTL___S                      0
#define   DBG_CTIDBG_ASICCTL___M                 0xFFFFFFFF   
#define   DBG_CTIDBG_ASICCTL___S                               0

#define DBG_CTIDBG_ITCHINACK                      (0x00B94EDC)
#define   DBG_CTIDBG_ITCHINACK___RWC                QCSR_REG_WO    
#define   DBG_CTIDBG_ITCHINACK___POR             0x00000000
#define   DBG_CTIDBG_ITCHINACK__CTCHINACK___POR  0x00
#define   DBG_CTIDBG_ITCHINACK__CTCHINACK___M    0x000000FF
#define   DBG_CTIDBG_ITCHINACK__CTCHINACK___S                  0
#define   DBG_CTIDBG_ITCHINACK___M               0x000000FF   
#define   DBG_CTIDBG_ITCHINACK___S                             0

#define DBG_CTIDBG_ITTRIGINACK                    (0x00B94EE0)
#define   DBG_CTIDBG_ITTRIGINACK___RWC              QCSR_REG_WO    
#define   DBG_CTIDBG_ITTRIGINACK___POR           0x00000000
#define   DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___POR 0x00000000
#define   DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___M 0xFFFFFFFF
#define   DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_CTIDBG_ITTRIGINACK___M             0xFFFFFFFF   
#define   DBG_CTIDBG_ITTRIGINACK___S                           0

#define DBG_CTIDBG_ITCHOUT                        (0x00B94EE4)
#define   DBG_CTIDBG_ITCHOUT___RWC                  QCSR_REG_WO    
#define   DBG_CTIDBG_ITCHOUT___POR               0x00000000
#define   DBG_CTIDBG_ITCHOUT__CTCHOUT___POR      0x00
#define   DBG_CTIDBG_ITCHOUT__CTCHOUT___M        0x000000FF
#define   DBG_CTIDBG_ITCHOUT__CTCHOUT___S                      0
#define   DBG_CTIDBG_ITCHOUT___M                 0x000000FF   
#define   DBG_CTIDBG_ITCHOUT___S                               0

#define DBG_CTIDBG_ITTRIGOUT                      (0x00B94EE8)
#define   DBG_CTIDBG_ITTRIGOUT___RWC                QCSR_REG_WO    
#define   DBG_CTIDBG_ITTRIGOUT___POR             0x00000000
#define   DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___POR  0x00000000
#define   DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___M    0xFFFFFFFF
#define   DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___S                  0
#define   DBG_CTIDBG_ITTRIGOUT___M               0xFFFFFFFF   
#define   DBG_CTIDBG_ITTRIGOUT___S                             0

#define DBG_CTIDBG_ITCHOUTACK                     (0x00B94EEC)
#define   DBG_CTIDBG_ITCHOUTACK___RWC               QCSR_REG_RO    
#define   DBG_CTIDBG_ITCHOUTACK___POR            0x00000000
#define   DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___M  0x000000FF
#define   DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___S                0
#define   DBG_CTIDBG_ITCHOUTACK___M              0x000000FF   
#define   DBG_CTIDBG_ITCHOUTACK___S                            0

#define DBG_CTIDBG_ITTRIGOUTACK                   (0x00B94EF0)
#define   DBG_CTIDBG_ITTRIGOUTACK___RWC             QCSR_REG_RO    
#define   DBG_CTIDBG_ITTRIGOUTACK___POR          0x00000000
#define   DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00000000
#define   DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___M 0xFFFFFFFF
#define   DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_CTIDBG_ITTRIGOUTACK___M            0xFFFFFFFF   
#define   DBG_CTIDBG_ITTRIGOUTACK___S                          0

#define DBG_CTIDBG_ITCHIN                         (0x00B94EF4)
#define   DBG_CTIDBG_ITCHIN___RWC                   QCSR_REG_RO    
#define   DBG_CTIDBG_ITCHIN___POR                0x00000000
#define   DBG_CTIDBG_ITCHIN__CTCHIN___POR        0x00
#define   DBG_CTIDBG_ITCHIN__CTCHIN___M          0x000000FF
#define   DBG_CTIDBG_ITCHIN__CTCHIN___S                        0
#define   DBG_CTIDBG_ITCHIN___M                  0x000000FF   
#define   DBG_CTIDBG_ITCHIN___S                                0

#define DBG_CTIDBG_ITTRIGIN                       (0x00B94EF8)
#define   DBG_CTIDBG_ITTRIGIN___RWC                 QCSR_REG_RO    
#define   DBG_CTIDBG_ITTRIGIN___POR              0x00000000
#define   DBG_CTIDBG_ITTRIGIN__CTTRIGIN___POR    0x00000000
#define   DBG_CTIDBG_ITTRIGIN__CTTRIGIN___M      0xFFFFFFFF
#define   DBG_CTIDBG_ITTRIGIN__CTTRIGIN___S                    0
#define   DBG_CTIDBG_ITTRIGIN___M                0xFFFFFFFF   
#define   DBG_CTIDBG_ITTRIGIN___S                              0

#define DBG_CTIDBG_ITCTRL                         (0x00B94F00)
#define   DBG_CTIDBG_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_CTIDBG_ITCTRL___POR                0x00000000
#define   DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_CTIDBG_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_CTIDBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_CTIDBG_ITCTRL___M                  0x00000001   
#define   DBG_CTIDBG_ITCTRL___S                                0

#define DBG_CTIDBG_CLAIMSET                       (0x00B94FA0)
#define   DBG_CTIDBG_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CLAIMSET___POR              0x0000000F
#define   DBG_CTIDBG_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_CTIDBG_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_CTIDBG_CLAIMSET__CLAIMSET___S                    0
#define   DBG_CTIDBG_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_CTIDBG_CLAIMSET___M                0x0000000F   
#define   DBG_CTIDBG_CLAIMSET___S                              0

#define DBG_CTIDBG_CLAIMCLR                       (0x00B94FA4)
#define   DBG_CTIDBG_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_CTIDBG_CLAIMCLR___POR              0x00000000
#define   DBG_CTIDBG_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_CTIDBG_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_CTIDBG_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_CTIDBG_CLAIMCLR___M                0x0000000F   
#define   DBG_CTIDBG_CLAIMCLR___S                              0

#define DBG_CTIDBG_DEVAFF0                        (0x00B94FA8)
#define   DBG_CTIDBG_DEVAFF0___RWC                  QCSR_REG_RO    
#define   DBG_CTIDBG_DEVAFF0___POR               0x00000000
#define   DBG_CTIDBG_DEVAFF0__VAL___POR          0x00000000
#define   DBG_CTIDBG_DEVAFF0__VAL___M            0xFFFFFFFF
#define   DBG_CTIDBG_DEVAFF0__VAL___S                          0
#define   DBG_CTIDBG_DEVAFF0___M                 0xFFFFFFFF   
#define   DBG_CTIDBG_DEVAFF0___S                               0

#define DBG_CTIDBG_DEVAFF1                        (0x00B94FAC)
#define   DBG_CTIDBG_DEVAFF1___RWC                  QCSR_REG_RO    
#define   DBG_CTIDBG_DEVAFF1___POR               0x00000000
#define   DBG_CTIDBG_DEVAFF1__VAL___POR          0x00000000
#define   DBG_CTIDBG_DEVAFF1__VAL___M            0xFFFFFFFF
#define   DBG_CTIDBG_DEVAFF1__VAL___S                          0
#define   DBG_CTIDBG_DEVAFF1___M                 0xFFFFFFFF   
#define   DBG_CTIDBG_DEVAFF1___S                               0

#define DBG_CTIDBG_LAR                            (0x00B94FB0)
#define   DBG_CTIDBG_LAR___RWC                      QCSR_REG_WO    
#define   DBG_CTIDBG_LAR__ACCESS_W___M           0xFFFFFFFF
#define   DBG_CTIDBG_LAR__ACCESS_W___S                         0
#define   DBG_CTIDBG_LAR__ACCESS_W__UNLOCK            0xC5ACCE55
#define   DBG_CTIDBG_LAR___M                     0xFFFFFFFF   
#define   DBG_CTIDBG_LAR___S                                   0

#define DBG_CTIDBG_LSR                            (0x00B94FB4)
#define   DBG_CTIDBG_LSR___RWC                      QCSR_REG_RO    
#define   DBG_CTIDBG_LSR___POR                   0x00000003
#define   DBG_CTIDBG_LSR__LOCKTYPE___POR         0x0
#define   DBG_CTIDBG_LSR__LOCKGRANT___POR        0x1
#define   DBG_CTIDBG_LSR__LOCKEXIST___POR        0x1
#define   DBG_CTIDBG_LSR__LOCKTYPE___M           0x00000004
#define   DBG_CTIDBG_LSR__LOCKTYPE___S                         2
#define   DBG_CTIDBG_LSR__LOCKTYPE__SIZE_32BIT               0x0
#define   DBG_CTIDBG_LSR__LOCKGRANT___M          0x00000002
#define   DBG_CTIDBG_LSR__LOCKGRANT___S                        1
#define   DBG_CTIDBG_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_CTIDBG_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_CTIDBG_LSR__LOCKEXIST___M          0x00000001
#define   DBG_CTIDBG_LSR__LOCKEXIST___S                        0
#define   DBG_CTIDBG_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_CTIDBG_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_CTIDBG_LSR___M                     0x00000007   
#define   DBG_CTIDBG_LSR___S                                   0

#define DBG_CTIDBG_AUTHSTATUS                     (0x00B94FB8)
#define   DBG_CTIDBG_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CTIDBG_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_CTIDBG_AUTHSTATUS__SNID___S                      6
#define   DBG_CTIDBG_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIDBG_AUTHSTATUS__SID___M         0x00000030
#define   DBG_CTIDBG_AUTHSTATUS__SID___S                       4
#define   DBG_CTIDBG_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIDBG_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_CTIDBG_AUTHSTATUS__NSNID___S                     2
#define   DBG_CTIDBG_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_CTIDBG_AUTHSTATUS__NSNID__ENABLED              0x3
#define   DBG_CTIDBG_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_CTIDBG_AUTHSTATUS__NSID___S                      0
#define   DBG_CTIDBG_AUTHSTATUS__NSID__DISABLED              0x2
#define   DBG_CTIDBG_AUTHSTATUS__NSID__ENABLED               0x3
#define   DBG_CTIDBG_AUTHSTATUS___M              0x000000FF   
#define   DBG_CTIDBG_AUTHSTATUS___S                            0

#define DBG_CTIDBG_DEVARCH                        (0x00B94FBC)
#define   DBG_CTIDBG_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CTIDBG_DEVARCH___POR               0x8EF00A14
#define   DBG_CTIDBG_DEVARCH__ARCHITECT___POR    0x477
#define   DBG_CTIDBG_DEVARCH__PRESENT___POR      0x1
#define   DBG_CTIDBG_DEVARCH__REVISION___POR     0x0
#define   DBG_CTIDBG_DEVARCH__ARCHID___POR       0x0A14
#define   DBG_CTIDBG_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CTIDBG_DEVARCH__ARCHITECT___S                   21
#define   DBG_CTIDBG_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CTIDBG_DEVARCH__PRESENT___S                     20
#define   DBG_CTIDBG_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CTIDBG_DEVARCH__REVISION___S                    16
#define   DBG_CTIDBG_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CTIDBG_DEVARCH__ARCHID___S                       0
#define   DBG_CTIDBG_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CTIDBG_DEVARCH___S                               0

#define DBG_CTIDBG_DEVID2                         (0x00B94FC0)
#define   DBG_CTIDBG_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CTIDBG_DEVID2___POR                0x00000000
#define   DBG_CTIDBG_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CTIDBG_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CTIDBG_DEVID2__IMPLDEF___S                       0
#define   DBG_CTIDBG_DEVID2___M                  0x00000001   
#define   DBG_CTIDBG_DEVID2___S                                0

#define DBG_CTIDBG_DEVID1                         (0x00B94FC4)
#define   DBG_CTIDBG_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CTIDBG_DEVID1___POR                0x00000000
#define   DBG_CTIDBG_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CTIDBG_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CTIDBG_DEVID1__IMPLDEF___S                       0
#define   DBG_CTIDBG_DEVID1___M                  0x00000001   
#define   DBG_CTIDBG_DEVID1___S                                0

#define DBG_CTIDBG_DEVID                          (0x00B94FC8)
#define   DBG_CTIDBG_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_DEVID___POR                 0x00082000
#define   DBG_CTIDBG_DEVID__NUMCH___POR          0x8
#define   DBG_CTIDBG_DEVID__NUMTRIG___POR        0x20
#define   DBG_CTIDBG_DEVID__EXTMUXNUM___POR      0x00
#define   DBG_CTIDBG_DEVID__NUMCH___M            0x003F0000
#define   DBG_CTIDBG_DEVID__NUMCH___S                         16
#define   DBG_CTIDBG_DEVID__NUMTRIG___M          0x0000FF00
#define   DBG_CTIDBG_DEVID__NUMTRIG___S                        8
#define   DBG_CTIDBG_DEVID__EXTMUXNUM___M        0x0000001F
#define   DBG_CTIDBG_DEVID__EXTMUXNUM___S                      0
#define   DBG_CTIDBG_DEVID___M                   0x003FFF1F   
#define   DBG_CTIDBG_DEVID___S                                 0

#define DBG_CTIDBG_DEVTYPE                        (0x00B94FCC)
#define   DBG_CTIDBG_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_CTIDBG_DEVTYPE___POR               0x00000014
#define   DBG_CTIDBG_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___POR   0x4
#define   DBG_CTIDBG_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_CTIDBG_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_CTIDBG_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_CTIDBG_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_CTIDBG_DEVTYPE___M                 0x000000FF   
#define   DBG_CTIDBG_DEVTYPE___S                               0

#define DBG_CTIDBG_PIDR0                          (0x00B94FE0)
#define   DBG_CTIDBG_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_PIDR0___POR                 0x00000006
#define   DBG_CTIDBG_PIDR0__PART_0___POR         0x06
#define   DBG_CTIDBG_PIDR0__PART_0___M           0x000000FF
#define   DBG_CTIDBG_PIDR0__PART_0___S                         0
#define   DBG_CTIDBG_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_CTIDBG_PIDR0___M                   0x000000FF   
#define   DBG_CTIDBG_PIDR0___S                                 0

#define DBG_CTIDBG_PIDR1                          (0x00B94FE4)
#define   DBG_CTIDBG_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_PIDR1___POR                 0x000000B9
#define   DBG_CTIDBG_PIDR1__DES_0___POR          0xB
#define   DBG_CTIDBG_PIDR1__PART_1___POR         0x9
#define   DBG_CTIDBG_PIDR1__DES_0___M            0x000000F0
#define   DBG_CTIDBG_PIDR1__DES_0___S                          4
#define   DBG_CTIDBG_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_CTIDBG_PIDR1__PART_1___M           0x0000000F
#define   DBG_CTIDBG_PIDR1__PART_1___S                         0
#define   DBG_CTIDBG_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_CTIDBG_PIDR1___M                   0x000000FF   
#define   DBG_CTIDBG_PIDR1___S                                 0

#define DBG_CTIDBG_PIDR2                          (0x00B94FE8)
#define   DBG_CTIDBG_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_PIDR2___POR                 0x0000004B
#define   DBG_CTIDBG_PIDR2__REVISION___POR       0x4
#define   DBG_CTIDBG_PIDR2__JEDEC___POR          0x1
#define   DBG_CTIDBG_PIDR2__DES_1___POR          0x3
#define   DBG_CTIDBG_PIDR2__REVISION___M         0x000000F0
#define   DBG_CTIDBG_PIDR2__REVISION___S                       4
#define   DBG_CTIDBG_PIDR2__REVISION__R0P4                   0x4
#define   DBG_CTIDBG_PIDR2__REVISION__R0P5                   0x5
#define   DBG_CTIDBG_PIDR2__JEDEC___M            0x00000008
#define   DBG_CTIDBG_PIDR2__JEDEC___S                          3
#define   DBG_CTIDBG_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_CTIDBG_PIDR2__DES_1___M            0x00000007
#define   DBG_CTIDBG_PIDR2__DES_1___S                          0
#define   DBG_CTIDBG_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_CTIDBG_PIDR2___M                   0x000000FF   
#define   DBG_CTIDBG_PIDR2___S                                 0

#define DBG_CTIDBG_PIDR3                          (0x00B94FEC)
#define   DBG_CTIDBG_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_PIDR3___POR                 0x00000000
#define   DBG_CTIDBG_PIDR3__REVAND___POR         0x0
#define   DBG_CTIDBG_PIDR3__CMOD___POR           0x0
#define   DBG_CTIDBG_PIDR3__REVAND___M           0x000000F0
#define   DBG_CTIDBG_PIDR3__REVAND___S                         4
#define   DBG_CTIDBG_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_CTIDBG_PIDR3__CMOD___M             0x0000000F
#define   DBG_CTIDBG_PIDR3__CMOD___S                           0
#define   DBG_CTIDBG_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_CTIDBG_PIDR3___M                   0x000000FF   
#define   DBG_CTIDBG_PIDR3___S                                 0

#define DBG_CTIDBG_PIDR4                          (0x00B94FD0)
#define   DBG_CTIDBG_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_PIDR4___POR                 0x00000004
#define   DBG_CTIDBG_PIDR4__SIZE___POR           0x0
#define   DBG_CTIDBG_PIDR4__DES_2___POR          0x4
#define   DBG_CTIDBG_PIDR4__SIZE___M             0x000000F0
#define   DBG_CTIDBG_PIDR4__SIZE___S                           4
#define   DBG_CTIDBG_PIDR4__SIZE__SIZE_4KB                   0x0
#define   DBG_CTIDBG_PIDR4__DES_2___M            0x0000000F
#define   DBG_CTIDBG_PIDR4__DES_2___S                          0
#define   DBG_CTIDBG_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_CTIDBG_PIDR4___M                   0x000000FF   
#define   DBG_CTIDBG_PIDR4___S                                 0

#define DBG_CTIDBG_PIDR5                          (0x00B94FD4)
#define   DBG_CTIDBG_PIDR5___RWC                    QCSR_REG_RW    
#define   DBG_CTIDBG_PIDR5__PERIPHID5___M        0xFFFFFFFF
#define   DBG_CTIDBG_PIDR5__PERIPHID5___S                      0
#define   DBG_CTIDBG_PIDR5___M                   0xFFFFFFFF   
#define   DBG_CTIDBG_PIDR5___S                                 0

#define DBG_CTIDBG_PIDR6                          (0x00B94FD8)
#define   DBG_CTIDBG_PIDR6___RWC                    QCSR_REG_RW    
#define   DBG_CTIDBG_PIDR6__PERIPHID6___M        0xFFFFFFFF
#define   DBG_CTIDBG_PIDR6__PERIPHID6___S                      0
#define   DBG_CTIDBG_PIDR6___M                   0xFFFFFFFF   
#define   DBG_CTIDBG_PIDR6___S                                 0

#define DBG_CTIDBG_PIDR7                          (0x00B94FDC)
#define   DBG_CTIDBG_PIDR7___RWC                    QCSR_REG_RW    
#define   DBG_CTIDBG_PIDR7__PERIPHID7___M        0xFFFFFFFF
#define   DBG_CTIDBG_PIDR7__PERIPHID7___S                      0
#define   DBG_CTIDBG_PIDR7___M                   0xFFFFFFFF   
#define   DBG_CTIDBG_PIDR7___S                                 0

#define DBG_CTIDBG_CIDR0                          (0x00B94FF0)
#define   DBG_CTIDBG_CIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_CIDR0___POR                 0x0000000D
#define   DBG_CTIDBG_CIDR0__PRMBL_0___POR        0x0D
#define   DBG_CTIDBG_CIDR0__PRMBL_0___M          0x000000FF
#define   DBG_CTIDBG_CIDR0__PRMBL_0___S                        0
#define   DBG_CTIDBG_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_CTIDBG_CIDR0___M                   0x000000FF   
#define   DBG_CTIDBG_CIDR0___S                                 0

#define DBG_CTIDBG_CIDR1                          (0x00B94FF4)
#define   DBG_CTIDBG_CIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_CIDR1___POR                 0x00000090
#define   DBG_CTIDBG_CIDR1__CLASS___POR          0x9
#define   DBG_CTIDBG_CIDR1__PRMBL_1___POR        0x0
#define   DBG_CTIDBG_CIDR1__CLASS___M            0x000000F0
#define   DBG_CTIDBG_CIDR1__CLASS___S                          4
#define   DBG_CTIDBG_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_CTIDBG_CIDR1__PRMBL_1___M          0x0000000F
#define   DBG_CTIDBG_CIDR1__PRMBL_1___S                        0
#define   DBG_CTIDBG_CIDR1__PRMBL_1__ID_VALUE_0              0x0
#define   DBG_CTIDBG_CIDR1___M                   0x000000FF   
#define   DBG_CTIDBG_CIDR1___S                                 0

#define DBG_CTIDBG_CIDR2                          (0x00B94FF8)
#define   DBG_CTIDBG_CIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_CIDR2___POR                 0x00000005
#define   DBG_CTIDBG_CIDR2__PRMBL_2___POR        0x05
#define   DBG_CTIDBG_CIDR2__PRMBL_2___M          0x000000FF
#define   DBG_CTIDBG_CIDR2__PRMBL_2___S                        0
#define   DBG_CTIDBG_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_CTIDBG_CIDR2___M                   0x000000FF   
#define   DBG_CTIDBG_CIDR2___S                                 0

#define DBG_CTIDBG_CIDR3                          (0x00B94FFC)
#define   DBG_CTIDBG_CIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIDBG_CIDR3___POR                 0x000000B1
#define   DBG_CTIDBG_CIDR3__PRMBL_3___POR        0xB1
#define   DBG_CTIDBG_CIDR3__PRMBL_3___M          0x000000FF
#define   DBG_CTIDBG_CIDR3__PRMBL_3___S                        0
#define   DBG_CTIDBG_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_CTIDBG_CIDR3___M                   0x000000FF   
#define   DBG_CTIDBG_CIDR3___S                                 0

#define DBG_CTINOC_CTICONTROL                     (0x00B95000)
#define   DBG_CTINOC_CTICONTROL___RWC               QCSR_REG_RW    
#define   DBG_CTINOC_CTICONTROL___POR            0x00000000
#define   DBG_CTINOC_CTICONTROL__GLBEN___POR     0x0
#define   DBG_CTINOC_CTICONTROL__GLBEN___M       0x00000001
#define   DBG_CTINOC_CTICONTROL__GLBEN___S                     0
#define   DBG_CTINOC_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_CTINOC_CTICONTROL__GLBEN__ENABLED              0x1
#define   DBG_CTINOC_CTICONTROL___M              0x00000001   
#define   DBG_CTINOC_CTICONTROL___S                            0

#define DBG_CTINOC_CTIINTACK                      (0x00B95010)
#define   DBG_CTINOC_CTIINTACK___RWC                QCSR_REG_WO    
#define   DBG_CTINOC_CTIINTACK___POR             0x00000000
#define   DBG_CTINOC_CTIINTACK__INTACK___POR     0x00
#define   DBG_CTINOC_CTIINTACK__INTACK___M       0x000000FF
#define   DBG_CTINOC_CTIINTACK__INTACK___S                     0
#define   DBG_CTINOC_CTIINTACK___M               0x000000FF   
#define   DBG_CTINOC_CTIINTACK___S                             0

#define DBG_CTINOC_CTIAPPSET                      (0x00B95014)
#define   DBG_CTINOC_CTIAPPSET___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIAPPSET___POR             0x00000000
#define   DBG_CTINOC_CTIAPPSET__APPSET___POR     0x00
#define   DBG_CTINOC_CTIAPPSET__APPSET___M       0x000000FF
#define   DBG_CTINOC_CTIAPPSET__APPSET___S                     0
#define   DBG_CTINOC_CTIAPPSET___M               0x000000FF   
#define   DBG_CTINOC_CTIAPPSET___S                             0

#define DBG_CTINOC_CTIAPPCLEAR                    (0x00B95018)
#define   DBG_CTINOC_CTIAPPCLEAR___RWC              QCSR_REG_WO    
#define   DBG_CTINOC_CTIAPPCLEAR___POR           0x00000000
#define   DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___M   0x000000FF
#define   DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___S                 0
#define   DBG_CTINOC_CTIAPPCLEAR___M             0x000000FF   
#define   DBG_CTINOC_CTIAPPCLEAR___S                           0

#define DBG_CTINOC_CTIAPPPULSE                    (0x00B9501C)
#define   DBG_CTINOC_CTIAPPPULSE___RWC              QCSR_REG_WO    
#define   DBG_CTINOC_CTIAPPPULSE___POR           0x00000000
#define   DBG_CTINOC_CTIAPPPULSE__APPULSE___POR  0x00
#define   DBG_CTINOC_CTIAPPPULSE__APPULSE___M    0x000000FF
#define   DBG_CTINOC_CTIAPPPULSE__APPULSE___S                  0
#define   DBG_CTINOC_CTIAPPPULSE___M             0x000000FF   
#define   DBG_CTINOC_CTIAPPPULSE___S                           0

#define DBG_CTINOC_CTIINEN0                       (0x00B95020)
#define   DBG_CTINOC_CTIINEN0___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN0___POR              0x00000000
#define   DBG_CTINOC_CTIINEN0__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN0__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN0__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN0___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN0___S                              0

#define DBG_CTINOC_CTIINEN1                       (0x00B95024)
#define   DBG_CTINOC_CTIINEN1___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN1___POR              0x00000000
#define   DBG_CTINOC_CTIINEN1__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN1__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN1__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN1___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN1___S                              0

#define DBG_CTINOC_CTIINEN2                       (0x00B95028)
#define   DBG_CTINOC_CTIINEN2___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN2___POR              0x00000000
#define   DBG_CTINOC_CTIINEN2__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN2__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN2__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN2___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN2___S                              0

#define DBG_CTINOC_CTIINEN3                       (0x00B9502C)
#define   DBG_CTINOC_CTIINEN3___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN3___POR              0x00000000
#define   DBG_CTINOC_CTIINEN3__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN3__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN3__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN3___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN3___S                              0

#define DBG_CTINOC_CTIINEN4                       (0x00B95030)
#define   DBG_CTINOC_CTIINEN4___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN4___POR              0x00000000
#define   DBG_CTINOC_CTIINEN4__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN4__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN4__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN4___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN4___S                              0

#define DBG_CTINOC_CTIINEN5                       (0x00B95034)
#define   DBG_CTINOC_CTIINEN5___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN5___POR              0x00000000
#define   DBG_CTINOC_CTIINEN5__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN5__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN5__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN5___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN5___S                              0

#define DBG_CTINOC_CTIINEN6                       (0x00B95038)
#define   DBG_CTINOC_CTIINEN6___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN6___POR              0x00000000
#define   DBG_CTINOC_CTIINEN6__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN6__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN6__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN6___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN6___S                              0

#define DBG_CTINOC_CTIINEN7                       (0x00B9503C)
#define   DBG_CTINOC_CTIINEN7___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CTIINEN7___POR              0x00000000
#define   DBG_CTINOC_CTIINEN7__TRIGINEN___POR    0x00
#define   DBG_CTINOC_CTIINEN7__TRIGINEN___M      0x000000FF
#define   DBG_CTINOC_CTIINEN7__TRIGINEN___S                    0
#define   DBG_CTINOC_CTIINEN7___M                0x000000FF   
#define   DBG_CTINOC_CTIINEN7___S                              0

#define DBG_CTINOC_CTIOUTEN0                      (0x00B950A0)
#define   DBG_CTINOC_CTIOUTEN0___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN0___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN0___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN0___S                             0

#define DBG_CTINOC_CTIOUTEN1                      (0x00B950A4)
#define   DBG_CTINOC_CTIOUTEN1___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN1___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN1___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN1___S                             0

#define DBG_CTINOC_CTIOUTEN2                      (0x00B950A8)
#define   DBG_CTINOC_CTIOUTEN2___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN2___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN2___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN2___S                             0

#define DBG_CTINOC_CTIOUTEN3                      (0x00B950AC)
#define   DBG_CTINOC_CTIOUTEN3___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN3___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN3___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN3___S                             0

#define DBG_CTINOC_CTIOUTEN4                      (0x00B950B0)
#define   DBG_CTINOC_CTIOUTEN4___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN4___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN4___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN4___S                             0

#define DBG_CTINOC_CTIOUTEN5                      (0x00B950B4)
#define   DBG_CTINOC_CTIOUTEN5___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN5___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN5___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN5___S                             0

#define DBG_CTINOC_CTIOUTEN6                      (0x00B950B8)
#define   DBG_CTINOC_CTIOUTEN6___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN6___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN6___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN6___S                             0

#define DBG_CTINOC_CTIOUTEN7                      (0x00B950BC)
#define   DBG_CTINOC_CTIOUTEN7___RWC                QCSR_REG_RW    
#define   DBG_CTINOC_CTIOUTEN7___POR             0x00000000
#define   DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___POR  0x00
#define   DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___M    0x000000FF
#define   DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___S                  0
#define   DBG_CTINOC_CTIOUTEN7___M               0x000000FF   
#define   DBG_CTINOC_CTIOUTEN7___S                             0

#define DBG_CTINOC_CTITRIGINSTATUS                (0x00B95130)
#define   DBG_CTINOC_CTITRIGINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_CTINOC_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000000FF
#define   DBG_CTINOC_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_CTINOC_CTITRIGINSTATUS___M         0x000000FF   
#define   DBG_CTINOC_CTITRIGINSTATUS___S                       0

#define DBG_CTINOC_CTITRIGOUTSTATUS               (0x00B95134)
#define   DBG_CTINOC_CTITRIGOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_CTINOC_CTITRIGOUTSTATUS___POR      0x00000000
#define   DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00
#define   DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000000FF
#define   DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_CTINOC_CTITRIGOUTSTATUS___M        0x000000FF   
#define   DBG_CTINOC_CTITRIGOUTSTATUS___S                      0

#define DBG_CTINOC_CTICHINSTATUS                  (0x00B95138)
#define   DBG_CTINOC_CTICHINSTATUS___RWC            QCSR_REG_RO    
#define   DBG_CTINOC_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_CTINOC_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_CTINOC_CTICHINSTATUS___M           0x000000FF   
#define   DBG_CTINOC_CTICHINSTATUS___S                         0

#define DBG_CTINOC_CTICHOUTSTATUS                 (0x00B9513C)
#define   DBG_CTINOC_CTICHOUTSTATUS___RWC           QCSR_REG_RO    
#define   DBG_CTINOC_CTICHOUTSTATUS___POR        0x00000000
#define   DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_CTINOC_CTICHOUTSTATUS___M          0x000000FF   
#define   DBG_CTINOC_CTICHOUTSTATUS___S                        0

#define DBG_CTINOC_CTIGATE                        (0x00B95140)
#define   DBG_CTINOC_CTIGATE___RWC                  QCSR_REG_RW    
#define   DBG_CTINOC_CTIGATE___POR               0x000000FF
#define   DBG_CTINOC_CTIGATE__CTIGATEEN7___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN6___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN5___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN4___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN3___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN2___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN1___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN0___POR   0x1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN7___M     0x00000080
#define   DBG_CTINOC_CTIGATE__CTIGATEEN7___S                   7
#define   DBG_CTINOC_CTIGATE__CTIGATEEN6___M     0x00000040
#define   DBG_CTINOC_CTIGATE__CTIGATEEN6___S                   6
#define   DBG_CTINOC_CTIGATE__CTIGATEEN5___M     0x00000020
#define   DBG_CTINOC_CTIGATE__CTIGATEEN5___S                   5
#define   DBG_CTINOC_CTIGATE__CTIGATEEN4___M     0x00000010
#define   DBG_CTINOC_CTIGATE__CTIGATEEN4___S                   4
#define   DBG_CTINOC_CTIGATE__CTIGATEEN3___M     0x00000008
#define   DBG_CTINOC_CTIGATE__CTIGATEEN3___S                   3
#define   DBG_CTINOC_CTIGATE__CTIGATEEN2___M     0x00000004
#define   DBG_CTINOC_CTIGATE__CTIGATEEN2___S                   2
#define   DBG_CTINOC_CTIGATE__CTIGATEEN1___M     0x00000002
#define   DBG_CTINOC_CTIGATE__CTIGATEEN1___S                   1
#define   DBG_CTINOC_CTIGATE__CTIGATEEN0___M     0x00000001
#define   DBG_CTINOC_CTIGATE__CTIGATEEN0___S                   0
#define   DBG_CTINOC_CTIGATE___M                 0x000000FF   
#define   DBG_CTINOC_CTIGATE___S                               0

#define DBG_CTINOC_ASICCTL                        (0x00B95144)
#define   DBG_CTINOC_ASICCTL___RWC                  QCSR_REG_RW    
#define   DBG_CTINOC_ASICCTL___POR               0x00000000
#define   DBG_CTINOC_ASICCTL__ASICCTL___POR      0x00000000
#define   DBG_CTINOC_ASICCTL__ASICCTL___M        0xFFFFFFFF
#define   DBG_CTINOC_ASICCTL__ASICCTL___S                      0
#define   DBG_CTINOC_ASICCTL___M                 0xFFFFFFFF   
#define   DBG_CTINOC_ASICCTL___S                               0

#define DBG_CTINOC_ITCHINACK                      (0x00B95EDC)
#define   DBG_CTINOC_ITCHINACK___RWC                QCSR_REG_WO    
#define   DBG_CTINOC_ITCHINACK___POR             0x00000000
#define   DBG_CTINOC_ITCHINACK__CTCHINACK___POR  0x00
#define   DBG_CTINOC_ITCHINACK__CTCHINACK___M    0x000000FF
#define   DBG_CTINOC_ITCHINACK__CTCHINACK___S                  0
#define   DBG_CTINOC_ITCHINACK___M               0x000000FF   
#define   DBG_CTINOC_ITCHINACK___S                             0

#define DBG_CTINOC_ITTRIGINACK                    (0x00B95EE0)
#define   DBG_CTINOC_ITTRIGINACK___RWC              QCSR_REG_WO    
#define   DBG_CTINOC_ITTRIGINACK___POR           0x00000000
#define   DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___POR 0x00
#define   DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___M 0x000000FF
#define   DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_CTINOC_ITTRIGINACK___M             0x000000FF   
#define   DBG_CTINOC_ITTRIGINACK___S                           0

#define DBG_CTINOC_ITCHOUT                        (0x00B95EE4)
#define   DBG_CTINOC_ITCHOUT___RWC                  QCSR_REG_WO    
#define   DBG_CTINOC_ITCHOUT___POR               0x00000000
#define   DBG_CTINOC_ITCHOUT__CTCHOUT___POR      0x00
#define   DBG_CTINOC_ITCHOUT__CTCHOUT___M        0x000000FF
#define   DBG_CTINOC_ITCHOUT__CTCHOUT___S                      0
#define   DBG_CTINOC_ITCHOUT___M                 0x000000FF   
#define   DBG_CTINOC_ITCHOUT___S                               0

#define DBG_CTINOC_ITTRIGOUT                      (0x00B95EE8)
#define   DBG_CTINOC_ITTRIGOUT___RWC                QCSR_REG_WO    
#define   DBG_CTINOC_ITTRIGOUT___POR             0x00000000
#define   DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___POR  0x00
#define   DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___M    0x000000FF
#define   DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___S                  0
#define   DBG_CTINOC_ITTRIGOUT___M               0x000000FF   
#define   DBG_CTINOC_ITTRIGOUT___S                             0

#define DBG_CTINOC_ITCHOUTACK                     (0x00B95EEC)
#define   DBG_CTINOC_ITCHOUTACK___RWC               QCSR_REG_RO    
#define   DBG_CTINOC_ITCHOUTACK___POR            0x00000000
#define   DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___M  0x000000FF
#define   DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___S                0
#define   DBG_CTINOC_ITCHOUTACK___M              0x000000FF   
#define   DBG_CTINOC_ITCHOUTACK___S                            0

#define DBG_CTINOC_ITTRIGOUTACK                   (0x00B95EF0)
#define   DBG_CTINOC_ITTRIGOUTACK___RWC             QCSR_REG_RO    
#define   DBG_CTINOC_ITTRIGOUTACK___POR          0x00000000
#define   DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00
#define   DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000000FF
#define   DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_CTINOC_ITTRIGOUTACK___M            0x000000FF   
#define   DBG_CTINOC_ITTRIGOUTACK___S                          0

#define DBG_CTINOC_ITCHIN                         (0x00B95EF4)
#define   DBG_CTINOC_ITCHIN___RWC                   QCSR_REG_RO    
#define   DBG_CTINOC_ITCHIN___POR                0x00000000
#define   DBG_CTINOC_ITCHIN__CTCHIN___POR        0x00
#define   DBG_CTINOC_ITCHIN__CTCHIN___M          0x000000FF
#define   DBG_CTINOC_ITCHIN__CTCHIN___S                        0
#define   DBG_CTINOC_ITCHIN___M                  0x000000FF   
#define   DBG_CTINOC_ITCHIN___S                                0

#define DBG_CTINOC_ITTRIGIN                       (0x00B95EF8)
#define   DBG_CTINOC_ITTRIGIN___RWC                 QCSR_REG_RO    
#define   DBG_CTINOC_ITTRIGIN___POR              0x00000000
#define   DBG_CTINOC_ITTRIGIN__CTTRIGIN___POR    0x00
#define   DBG_CTINOC_ITTRIGIN__CTTRIGIN___M      0x000000FF
#define   DBG_CTINOC_ITTRIGIN__CTTRIGIN___S                    0
#define   DBG_CTINOC_ITTRIGIN___M                0x000000FF   
#define   DBG_CTINOC_ITTRIGIN___S                              0

#define DBG_CTINOC_ITCTRL                         (0x00B95F00)
#define   DBG_CTINOC_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_CTINOC_ITCTRL___POR                0x00000000
#define   DBG_CTINOC_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_CTINOC_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_CTINOC_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_CTINOC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_CTINOC_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_CTINOC_ITCTRL___M                  0x00000001   
#define   DBG_CTINOC_ITCTRL___S                                0

#define DBG_CTINOC_CLAIMSET                       (0x00B95FA0)
#define   DBG_CTINOC_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CLAIMSET___POR              0x0000000F
#define   DBG_CTINOC_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_CTINOC_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_CTINOC_CLAIMSET__CLAIMSET___S                    0
#define   DBG_CTINOC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_CTINOC_CLAIMSET___M                0x0000000F   
#define   DBG_CTINOC_CLAIMSET___S                              0

#define DBG_CTINOC_CLAIMCLR                       (0x00B95FA4)
#define   DBG_CTINOC_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_CTINOC_CLAIMCLR___POR              0x00000000
#define   DBG_CTINOC_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_CTINOC_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_CTINOC_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_CTINOC_CLAIMCLR___M                0x0000000F   
#define   DBG_CTINOC_CLAIMCLR___S                              0

#define DBG_CTINOC_DEVAFF0                        (0x00B95FA8)
#define   DBG_CTINOC_DEVAFF0___RWC                  QCSR_REG_RO    
#define   DBG_CTINOC_DEVAFF0___POR               0x00000000
#define   DBG_CTINOC_DEVAFF0__VAL___POR          0x00000000
#define   DBG_CTINOC_DEVAFF0__VAL___M            0xFFFFFFFF
#define   DBG_CTINOC_DEVAFF0__VAL___S                          0
#define   DBG_CTINOC_DEVAFF0___M                 0xFFFFFFFF   
#define   DBG_CTINOC_DEVAFF0___S                               0

#define DBG_CTINOC_DEVAFF1                        (0x00B95FAC)
#define   DBG_CTINOC_DEVAFF1___RWC                  QCSR_REG_RO    
#define   DBG_CTINOC_DEVAFF1___POR               0x00000000
#define   DBG_CTINOC_DEVAFF1__VAL___POR          0x00000000
#define   DBG_CTINOC_DEVAFF1__VAL___M            0xFFFFFFFF
#define   DBG_CTINOC_DEVAFF1__VAL___S                          0
#define   DBG_CTINOC_DEVAFF1___M                 0xFFFFFFFF   
#define   DBG_CTINOC_DEVAFF1___S                               0

#define DBG_CTINOC_LAR                            (0x00B95FB0)
#define   DBG_CTINOC_LAR___RWC                      QCSR_REG_WO    
#define   DBG_CTINOC_LAR__ACCESS_W___M           0xFFFFFFFF
#define   DBG_CTINOC_LAR__ACCESS_W___S                         0
#define   DBG_CTINOC_LAR__ACCESS_W__UNLOCK            0xC5ACCE55
#define   DBG_CTINOC_LAR___M                     0xFFFFFFFF   
#define   DBG_CTINOC_LAR___S                                   0

#define DBG_CTINOC_LSR                            (0x00B95FB4)
#define   DBG_CTINOC_LSR___RWC                      QCSR_REG_RO    
#define   DBG_CTINOC_LSR___POR                   0x00000003
#define   DBG_CTINOC_LSR__LOCKTYPE___POR         0x0
#define   DBG_CTINOC_LSR__LOCKGRANT___POR        0x1
#define   DBG_CTINOC_LSR__LOCKEXIST___POR        0x1
#define   DBG_CTINOC_LSR__LOCKTYPE___M           0x00000004
#define   DBG_CTINOC_LSR__LOCKTYPE___S                         2
#define   DBG_CTINOC_LSR__LOCKTYPE__SIZE_32BIT               0x0
#define   DBG_CTINOC_LSR__LOCKGRANT___M          0x00000002
#define   DBG_CTINOC_LSR__LOCKGRANT___S                        1
#define   DBG_CTINOC_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_CTINOC_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_CTINOC_LSR__LOCKEXIST___M          0x00000001
#define   DBG_CTINOC_LSR__LOCKEXIST___S                        0
#define   DBG_CTINOC_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_CTINOC_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_CTINOC_LSR___M                     0x00000007   
#define   DBG_CTINOC_LSR___S                                   0

#define DBG_CTINOC_AUTHSTATUS                     (0x00B95FB8)
#define   DBG_CTINOC_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CTINOC_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_CTINOC_AUTHSTATUS__SNID___S                      6
#define   DBG_CTINOC_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_CTINOC_AUTHSTATUS__SID___M         0x00000030
#define   DBG_CTINOC_AUTHSTATUS__SID___S                       4
#define   DBG_CTINOC_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_CTINOC_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_CTINOC_AUTHSTATUS__NSNID___S                     2
#define   DBG_CTINOC_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_CTINOC_AUTHSTATUS__NSNID__ENABLED              0x3
#define   DBG_CTINOC_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_CTINOC_AUTHSTATUS__NSID___S                      0
#define   DBG_CTINOC_AUTHSTATUS__NSID__DISABLED              0x2
#define   DBG_CTINOC_AUTHSTATUS__NSID__ENABLED               0x3
#define   DBG_CTINOC_AUTHSTATUS___M              0x000000FF   
#define   DBG_CTINOC_AUTHSTATUS___S                            0

#define DBG_CTINOC_DEVARCH                        (0x00B95FBC)
#define   DBG_CTINOC_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CTINOC_DEVARCH___POR               0x8EF00A14
#define   DBG_CTINOC_DEVARCH__ARCHITECT___POR    0x477
#define   DBG_CTINOC_DEVARCH__PRESENT___POR      0x1
#define   DBG_CTINOC_DEVARCH__REVISION___POR     0x0
#define   DBG_CTINOC_DEVARCH__ARCHID___POR       0x0A14
#define   DBG_CTINOC_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CTINOC_DEVARCH__ARCHITECT___S                   21
#define   DBG_CTINOC_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CTINOC_DEVARCH__PRESENT___S                     20
#define   DBG_CTINOC_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CTINOC_DEVARCH__REVISION___S                    16
#define   DBG_CTINOC_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CTINOC_DEVARCH__ARCHID___S                       0
#define   DBG_CTINOC_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CTINOC_DEVARCH___S                               0

#define DBG_CTINOC_DEVID2                         (0x00B95FC0)
#define   DBG_CTINOC_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CTINOC_DEVID2___POR                0x00000000
#define   DBG_CTINOC_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CTINOC_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CTINOC_DEVID2__IMPLDEF___S                       0
#define   DBG_CTINOC_DEVID2___M                  0x00000001   
#define   DBG_CTINOC_DEVID2___S                                0

#define DBG_CTINOC_DEVID1                         (0x00B95FC4)
#define   DBG_CTINOC_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CTINOC_DEVID1___POR                0x00000000
#define   DBG_CTINOC_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CTINOC_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CTINOC_DEVID1__IMPLDEF___S                       0
#define   DBG_CTINOC_DEVID1___M                  0x00000001   
#define   DBG_CTINOC_DEVID1___S                                0

#define DBG_CTINOC_DEVID                          (0x00B95FC8)
#define   DBG_CTINOC_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_DEVID___POR                 0x00080800
#define   DBG_CTINOC_DEVID__NUMCH___POR          0x8
#define   DBG_CTINOC_DEVID__NUMTRIG___POR        0x8
#define   DBG_CTINOC_DEVID__EXTMUXNUM___POR      0x00
#define   DBG_CTINOC_DEVID__NUMCH___M            0x003F0000
#define   DBG_CTINOC_DEVID__NUMCH___S                         16
#define   DBG_CTINOC_DEVID__NUMTRIG___M          0x0000FF00
#define   DBG_CTINOC_DEVID__NUMTRIG___S                        8
#define   DBG_CTINOC_DEVID__EXTMUXNUM___M        0x0000001F
#define   DBG_CTINOC_DEVID__EXTMUXNUM___S                      0
#define   DBG_CTINOC_DEVID___M                   0x003FFF1F   
#define   DBG_CTINOC_DEVID___S                                 0

#define DBG_CTINOC_DEVTYPE                        (0x00B95FCC)
#define   DBG_CTINOC_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_CTINOC_DEVTYPE___POR               0x00000014
#define   DBG_CTINOC_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_CTINOC_DEVTYPE__MAJOR_TYPE___POR   0x4
#define   DBG_CTINOC_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_CTINOC_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_CTINOC_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_CTINOC_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_CTINOC_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_CTINOC_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_CTINOC_DEVTYPE___M                 0x000000FF   
#define   DBG_CTINOC_DEVTYPE___S                               0

#define DBG_CTINOC_PIDR0                          (0x00B95FE0)
#define   DBG_CTINOC_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_PIDR0___POR                 0x00000006
#define   DBG_CTINOC_PIDR0__PART_0___POR         0x06
#define   DBG_CTINOC_PIDR0__PART_0___M           0x000000FF
#define   DBG_CTINOC_PIDR0__PART_0___S                         0
#define   DBG_CTINOC_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_CTINOC_PIDR0___M                   0x000000FF   
#define   DBG_CTINOC_PIDR0___S                                 0

#define DBG_CTINOC_PIDR1                          (0x00B95FE4)
#define   DBG_CTINOC_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_PIDR1___POR                 0x000000B9
#define   DBG_CTINOC_PIDR1__DES_0___POR          0xB
#define   DBG_CTINOC_PIDR1__PART_1___POR         0x9
#define   DBG_CTINOC_PIDR1__DES_0___M            0x000000F0
#define   DBG_CTINOC_PIDR1__DES_0___S                          4
#define   DBG_CTINOC_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_CTINOC_PIDR1__PART_1___M           0x0000000F
#define   DBG_CTINOC_PIDR1__PART_1___S                         0
#define   DBG_CTINOC_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_CTINOC_PIDR1___M                   0x000000FF   
#define   DBG_CTINOC_PIDR1___S                                 0

#define DBG_CTINOC_PIDR2                          (0x00B95FE8)
#define   DBG_CTINOC_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_PIDR2___POR                 0x0000004B
#define   DBG_CTINOC_PIDR2__REVISION___POR       0x4
#define   DBG_CTINOC_PIDR2__JEDEC___POR          0x1
#define   DBG_CTINOC_PIDR2__DES_1___POR          0x3
#define   DBG_CTINOC_PIDR2__REVISION___M         0x000000F0
#define   DBG_CTINOC_PIDR2__REVISION___S                       4
#define   DBG_CTINOC_PIDR2__REVISION__R0P4                   0x4
#define   DBG_CTINOC_PIDR2__REVISION__R0P5                   0x5
#define   DBG_CTINOC_PIDR2__JEDEC___M            0x00000008
#define   DBG_CTINOC_PIDR2__JEDEC___S                          3
#define   DBG_CTINOC_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_CTINOC_PIDR2__DES_1___M            0x00000007
#define   DBG_CTINOC_PIDR2__DES_1___S                          0
#define   DBG_CTINOC_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_CTINOC_PIDR2___M                   0x000000FF   
#define   DBG_CTINOC_PIDR2___S                                 0

#define DBG_CTINOC_PIDR3                          (0x00B95FEC)
#define   DBG_CTINOC_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_PIDR3___POR                 0x00000000
#define   DBG_CTINOC_PIDR3__REVAND___POR         0x0
#define   DBG_CTINOC_PIDR3__CMOD___POR           0x0
#define   DBG_CTINOC_PIDR3__REVAND___M           0x000000F0
#define   DBG_CTINOC_PIDR3__REVAND___S                         4
#define   DBG_CTINOC_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_CTINOC_PIDR3__CMOD___M             0x0000000F
#define   DBG_CTINOC_PIDR3__CMOD___S                           0
#define   DBG_CTINOC_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_CTINOC_PIDR3___M                   0x000000FF   
#define   DBG_CTINOC_PIDR3___S                                 0

#define DBG_CTINOC_PIDR4                          (0x00B95FD0)
#define   DBG_CTINOC_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_PIDR4___POR                 0x00000004
#define   DBG_CTINOC_PIDR4__SIZE___POR           0x0
#define   DBG_CTINOC_PIDR4__DES_2___POR          0x4
#define   DBG_CTINOC_PIDR4__SIZE___M             0x000000F0
#define   DBG_CTINOC_PIDR4__SIZE___S                           4
#define   DBG_CTINOC_PIDR4__SIZE__SIZE_4KB                   0x0
#define   DBG_CTINOC_PIDR4__DES_2___M            0x0000000F
#define   DBG_CTINOC_PIDR4__DES_2___S                          0
#define   DBG_CTINOC_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_CTINOC_PIDR4___M                   0x000000FF   
#define   DBG_CTINOC_PIDR4___S                                 0

#define DBG_CTINOC_PIDR5                          (0x00B95FD4)
#define   DBG_CTINOC_PIDR5___RWC                    QCSR_REG_RW    
#define   DBG_CTINOC_PIDR5__PERIPHID5___M        0xFFFFFFFF
#define   DBG_CTINOC_PIDR5__PERIPHID5___S                      0
#define   DBG_CTINOC_PIDR5___M                   0xFFFFFFFF   
#define   DBG_CTINOC_PIDR5___S                                 0

#define DBG_CTINOC_PIDR6                          (0x00B95FD8)
#define   DBG_CTINOC_PIDR6___RWC                    QCSR_REG_RW    
#define   DBG_CTINOC_PIDR6__PERIPHID6___M        0xFFFFFFFF
#define   DBG_CTINOC_PIDR6__PERIPHID6___S                      0
#define   DBG_CTINOC_PIDR6___M                   0xFFFFFFFF   
#define   DBG_CTINOC_PIDR6___S                                 0

#define DBG_CTINOC_PIDR7                          (0x00B95FDC)
#define   DBG_CTINOC_PIDR7___RWC                    QCSR_REG_RW    
#define   DBG_CTINOC_PIDR7__PERIPHID7___M        0xFFFFFFFF
#define   DBG_CTINOC_PIDR7__PERIPHID7___S                      0
#define   DBG_CTINOC_PIDR7___M                   0xFFFFFFFF   
#define   DBG_CTINOC_PIDR7___S                                 0

#define DBG_CTINOC_CIDR0                          (0x00B95FF0)
#define   DBG_CTINOC_CIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_CIDR0___POR                 0x0000000D
#define   DBG_CTINOC_CIDR0__PRMBL_0___POR        0x0D
#define   DBG_CTINOC_CIDR0__PRMBL_0___M          0x000000FF
#define   DBG_CTINOC_CIDR0__PRMBL_0___S                        0
#define   DBG_CTINOC_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_CTINOC_CIDR0___M                   0x000000FF   
#define   DBG_CTINOC_CIDR0___S                                 0

#define DBG_CTINOC_CIDR1                          (0x00B95FF4)
#define   DBG_CTINOC_CIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_CIDR1___POR                 0x00000090
#define   DBG_CTINOC_CIDR1__CLASS___POR          0x9
#define   DBG_CTINOC_CIDR1__PRMBL_1___POR        0x0
#define   DBG_CTINOC_CIDR1__CLASS___M            0x000000F0
#define   DBG_CTINOC_CIDR1__CLASS___S                          4
#define   DBG_CTINOC_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_CTINOC_CIDR1__PRMBL_1___M          0x0000000F
#define   DBG_CTINOC_CIDR1__PRMBL_1___S                        0
#define   DBG_CTINOC_CIDR1__PRMBL_1__ID_VALUE_0              0x0
#define   DBG_CTINOC_CIDR1___M                   0x000000FF   
#define   DBG_CTINOC_CIDR1___S                                 0

#define DBG_CTINOC_CIDR2                          (0x00B95FF8)
#define   DBG_CTINOC_CIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_CIDR2___POR                 0x00000005
#define   DBG_CTINOC_CIDR2__PRMBL_2___POR        0x05
#define   DBG_CTINOC_CIDR2__PRMBL_2___M          0x000000FF
#define   DBG_CTINOC_CIDR2__PRMBL_2___S                        0
#define   DBG_CTINOC_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_CTINOC_CIDR2___M                   0x000000FF   
#define   DBG_CTINOC_CIDR2___S                                 0

#define DBG_CTINOC_CIDR3                          (0x00B95FFC)
#define   DBG_CTINOC_CIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTINOC_CIDR3___POR                 0x000000B1
#define   DBG_CTINOC_CIDR3__PRMBL_3___POR        0xB1
#define   DBG_CTINOC_CIDR3__PRMBL_3___M          0x000000FF
#define   DBG_CTINOC_CIDR3__PRMBL_3___S                        0
#define   DBG_CTINOC_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_CTINOC_CIDR3___M                   0x000000FF   
#define   DBG_CTINOC_CIDR3___S                                 0

#define DBG_CTIIRQ_CTICONTROL                     (0x00B96000)
#define   DBG_CTIIRQ_CTICONTROL___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTICONTROL___POR            0x00000000
#define   DBG_CTIIRQ_CTICONTROL__GLBEN___POR     0x0
#define   DBG_CTIIRQ_CTICONTROL__GLBEN___M       0x00000001
#define   DBG_CTIIRQ_CTICONTROL__GLBEN___S                     0
#define   DBG_CTIIRQ_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_CTIIRQ_CTICONTROL__GLBEN__ENABLED              0x1
#define   DBG_CTIIRQ_CTICONTROL___M              0x00000001   
#define   DBG_CTIIRQ_CTICONTROL___S                            0

#define DBG_CTIIRQ_CTIINTACK                      (0x00B96010)
#define   DBG_CTIIRQ_CTIINTACK___RWC                QCSR_REG_WO    
#define   DBG_CTIIRQ_CTIINTACK___POR             0x00000000
#define   DBG_CTIIRQ_CTIINTACK__INTACK___POR     0x00000000
#define   DBG_CTIIRQ_CTIINTACK__INTACK___M       0xFFFFFFFF
#define   DBG_CTIIRQ_CTIINTACK__INTACK___S                     0
#define   DBG_CTIIRQ_CTIINTACK___M               0xFFFFFFFF   
#define   DBG_CTIIRQ_CTIINTACK___S                             0

#define DBG_CTIIRQ_CTIAPPSET                      (0x00B96014)
#define   DBG_CTIIRQ_CTIAPPSET___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIAPPSET___POR             0x00000000
#define   DBG_CTIIRQ_CTIAPPSET__APPSET___POR     0x00
#define   DBG_CTIIRQ_CTIAPPSET__APPSET___M       0x000000FF
#define   DBG_CTIIRQ_CTIAPPSET__APPSET___S                     0
#define   DBG_CTIIRQ_CTIAPPSET___M               0x000000FF   
#define   DBG_CTIIRQ_CTIAPPSET___S                             0

#define DBG_CTIIRQ_CTIAPPCLEAR                    (0x00B96018)
#define   DBG_CTIIRQ_CTIAPPCLEAR___RWC              QCSR_REG_WO    
#define   DBG_CTIIRQ_CTIAPPCLEAR___POR           0x00000000
#define   DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___M   0x000000FF
#define   DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___S                 0
#define   DBG_CTIIRQ_CTIAPPCLEAR___M             0x000000FF   
#define   DBG_CTIIRQ_CTIAPPCLEAR___S                           0

#define DBG_CTIIRQ_CTIAPPPULSE                    (0x00B9601C)
#define   DBG_CTIIRQ_CTIAPPPULSE___RWC              QCSR_REG_WO    
#define   DBG_CTIIRQ_CTIAPPPULSE___POR           0x00000000
#define   DBG_CTIIRQ_CTIAPPPULSE__APPULSE___POR  0x00
#define   DBG_CTIIRQ_CTIAPPPULSE__APPULSE___M    0x000000FF
#define   DBG_CTIIRQ_CTIAPPPULSE__APPULSE___S                  0
#define   DBG_CTIIRQ_CTIAPPPULSE___M             0x000000FF   
#define   DBG_CTIIRQ_CTIAPPPULSE___S                           0

#define DBG_CTIIRQ_CTIINEN0                       (0x00B96020)
#define   DBG_CTIIRQ_CTIINEN0___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN0___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN0__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN0__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN0__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN0___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN0___S                              0

#define DBG_CTIIRQ_CTIINEN1                       (0x00B96024)
#define   DBG_CTIIRQ_CTIINEN1___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN1___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN1__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN1__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN1__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN1___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN1___S                              0

#define DBG_CTIIRQ_CTIINEN2                       (0x00B96028)
#define   DBG_CTIIRQ_CTIINEN2___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN2___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN2__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN2__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN2__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN2___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN2___S                              0

#define DBG_CTIIRQ_CTIINEN3                       (0x00B9602C)
#define   DBG_CTIIRQ_CTIINEN3___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN3___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN3__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN3__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN3__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN3___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN3___S                              0

#define DBG_CTIIRQ_CTIINEN4                       (0x00B96030)
#define   DBG_CTIIRQ_CTIINEN4___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN4___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN4__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN4__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN4__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN4___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN4___S                              0

#define DBG_CTIIRQ_CTIINEN5                       (0x00B96034)
#define   DBG_CTIIRQ_CTIINEN5___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN5___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN5__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN5__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN5__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN5___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN5___S                              0

#define DBG_CTIIRQ_CTIINEN6                       (0x00B96038)
#define   DBG_CTIIRQ_CTIINEN6___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN6___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN6__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN6__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN6__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN6___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN6___S                              0

#define DBG_CTIIRQ_CTIINEN7                       (0x00B9603C)
#define   DBG_CTIIRQ_CTIINEN7___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN7___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN7__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN7__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN7__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN7___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN7___S                              0

#define DBG_CTIIRQ_CTIINEN8                       (0x00B96040)
#define   DBG_CTIIRQ_CTIINEN8___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN8___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN8__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN8__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN8__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN8___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN8___S                              0

#define DBG_CTIIRQ_CTIINEN9                       (0x00B96044)
#define   DBG_CTIIRQ_CTIINEN9___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN9___POR              0x00000000
#define   DBG_CTIIRQ_CTIINEN9__TRIGINEN___POR    0x00
#define   DBG_CTIIRQ_CTIINEN9__TRIGINEN___M      0x000000FF
#define   DBG_CTIIRQ_CTIINEN9__TRIGINEN___S                    0
#define   DBG_CTIIRQ_CTIINEN9___M                0x000000FF   
#define   DBG_CTIIRQ_CTIINEN9___S                              0

#define DBG_CTIIRQ_CTIINEN10                      (0x00B96048)
#define   DBG_CTIIRQ_CTIINEN10___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN10___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN10__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN10__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN10__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN10___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN10___S                             0

#define DBG_CTIIRQ_CTIINEN11                      (0x00B9604C)
#define   DBG_CTIIRQ_CTIINEN11___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN11___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN11__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN11__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN11__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN11___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN11___S                             0

#define DBG_CTIIRQ_CTIINEN12                      (0x00B96050)
#define   DBG_CTIIRQ_CTIINEN12___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN12___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN12__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN12__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN12__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN12___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN12___S                             0

#define DBG_CTIIRQ_CTIINEN13                      (0x00B96054)
#define   DBG_CTIIRQ_CTIINEN13___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN13___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN13__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN13__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN13__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN13___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN13___S                             0

#define DBG_CTIIRQ_CTIINEN14                      (0x00B96058)
#define   DBG_CTIIRQ_CTIINEN14___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN14___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN14__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN14__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN14__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN14___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN14___S                             0

#define DBG_CTIIRQ_CTIINEN15                      (0x00B9605C)
#define   DBG_CTIIRQ_CTIINEN15___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN15___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN15__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN15__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN15__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN15___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN15___S                             0

#define DBG_CTIIRQ_CTIINEN16                      (0x00B96060)
#define   DBG_CTIIRQ_CTIINEN16___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN16___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN16__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN16__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN16__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN16___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN16___S                             0

#define DBG_CTIIRQ_CTIINEN17                      (0x00B96064)
#define   DBG_CTIIRQ_CTIINEN17___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN17___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN17__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN17__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN17__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN17___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN17___S                             0

#define DBG_CTIIRQ_CTIINEN18                      (0x00B96068)
#define   DBG_CTIIRQ_CTIINEN18___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN18___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN18__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN18__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN18__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN18___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN18___S                             0

#define DBG_CTIIRQ_CTIINEN19                      (0x00B9606C)
#define   DBG_CTIIRQ_CTIINEN19___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN19___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN19__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN19__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN19__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN19___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN19___S                             0

#define DBG_CTIIRQ_CTIINEN20                      (0x00B96070)
#define   DBG_CTIIRQ_CTIINEN20___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN20___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN20__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN20__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN20__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN20___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN20___S                             0

#define DBG_CTIIRQ_CTIINEN21                      (0x00B96074)
#define   DBG_CTIIRQ_CTIINEN21___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN21___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN21__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN21__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN21__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN21___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN21___S                             0

#define DBG_CTIIRQ_CTIINEN22                      (0x00B96078)
#define   DBG_CTIIRQ_CTIINEN22___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN22___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN22__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN22__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN22__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN22___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN22___S                             0

#define DBG_CTIIRQ_CTIINEN23                      (0x00B9607C)
#define   DBG_CTIIRQ_CTIINEN23___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN23___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN23__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN23__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN23__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN23___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN23___S                             0

#define DBG_CTIIRQ_CTIINEN24                      (0x00B96080)
#define   DBG_CTIIRQ_CTIINEN24___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN24___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN24__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN24__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN24__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN24___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN24___S                             0

#define DBG_CTIIRQ_CTIINEN25                      (0x00B96084)
#define   DBG_CTIIRQ_CTIINEN25___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN25___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN25__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN25__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN25__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN25___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN25___S                             0

#define DBG_CTIIRQ_CTIINEN26                      (0x00B96088)
#define   DBG_CTIIRQ_CTIINEN26___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN26___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN26__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN26__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN26__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN26___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN26___S                             0

#define DBG_CTIIRQ_CTIINEN27                      (0x00B9608C)
#define   DBG_CTIIRQ_CTIINEN27___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN27___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN27__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN27__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN27__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN27___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN27___S                             0

#define DBG_CTIIRQ_CTIINEN28                      (0x00B96090)
#define   DBG_CTIIRQ_CTIINEN28___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN28___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN28__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN28__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN28__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN28___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN28___S                             0

#define DBG_CTIIRQ_CTIINEN29                      (0x00B96094)
#define   DBG_CTIIRQ_CTIINEN29___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN29___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN29__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN29__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN29__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN29___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN29___S                             0

#define DBG_CTIIRQ_CTIINEN30                      (0x00B96098)
#define   DBG_CTIIRQ_CTIINEN30___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN30___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN30__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN30__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN30__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN30___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN30___S                             0

#define DBG_CTIIRQ_CTIINEN31                      (0x00B9609C)
#define   DBG_CTIIRQ_CTIINEN31___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIINEN31___POR             0x00000000
#define   DBG_CTIIRQ_CTIINEN31__TRIGINEN___POR   0x00
#define   DBG_CTIIRQ_CTIINEN31__TRIGINEN___M     0x000000FF
#define   DBG_CTIIRQ_CTIINEN31__TRIGINEN___S                   0
#define   DBG_CTIIRQ_CTIINEN31___M               0x000000FF   
#define   DBG_CTIIRQ_CTIINEN31___S                             0

#define DBG_CTIIRQ_CTIOUTEN0                      (0x00B960A0)
#define   DBG_CTIIRQ_CTIOUTEN0___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN0___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN0___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN0___S                             0

#define DBG_CTIIRQ_CTIOUTEN1                      (0x00B960A4)
#define   DBG_CTIIRQ_CTIOUTEN1___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN1___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN1___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN1___S                             0

#define DBG_CTIIRQ_CTIOUTEN2                      (0x00B960A8)
#define   DBG_CTIIRQ_CTIOUTEN2___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN2___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN2___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN2___S                             0

#define DBG_CTIIRQ_CTIOUTEN3                      (0x00B960AC)
#define   DBG_CTIIRQ_CTIOUTEN3___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN3___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN3___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN3___S                             0

#define DBG_CTIIRQ_CTIOUTEN4                      (0x00B960B0)
#define   DBG_CTIIRQ_CTIOUTEN4___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN4___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN4___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN4___S                             0

#define DBG_CTIIRQ_CTIOUTEN5                      (0x00B960B4)
#define   DBG_CTIIRQ_CTIOUTEN5___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN5___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN5___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN5___S                             0

#define DBG_CTIIRQ_CTIOUTEN6                      (0x00B960B8)
#define   DBG_CTIIRQ_CTIOUTEN6___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN6___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN6___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN6___S                             0

#define DBG_CTIIRQ_CTIOUTEN7                      (0x00B960BC)
#define   DBG_CTIIRQ_CTIOUTEN7___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN7___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN7___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN7___S                             0

#define DBG_CTIIRQ_CTIOUTEN8                      (0x00B960C0)
#define   DBG_CTIIRQ_CTIOUTEN8___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN8___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN8___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN8___S                             0

#define DBG_CTIIRQ_CTIOUTEN9                      (0x00B960C4)
#define   DBG_CTIIRQ_CTIOUTEN9___RWC                QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN9___POR             0x00000000
#define   DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___POR  0x00
#define   DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___S                  0
#define   DBG_CTIIRQ_CTIOUTEN9___M               0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN9___S                             0

#define DBG_CTIIRQ_CTIOUTEN10                     (0x00B960C8)
#define   DBG_CTIIRQ_CTIOUTEN10___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN10___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN10___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN10___S                            0

#define DBG_CTIIRQ_CTIOUTEN11                     (0x00B960CC)
#define   DBG_CTIIRQ_CTIOUTEN11___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN11___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN11___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN11___S                            0

#define DBG_CTIIRQ_CTIOUTEN12                     (0x00B960D0)
#define   DBG_CTIIRQ_CTIOUTEN12___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN12___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN12___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN12___S                            0

#define DBG_CTIIRQ_CTIOUTEN13                     (0x00B960D4)
#define   DBG_CTIIRQ_CTIOUTEN13___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN13___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN13___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN13___S                            0

#define DBG_CTIIRQ_CTIOUTEN14                     (0x00B960D8)
#define   DBG_CTIIRQ_CTIOUTEN14___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN14___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN14___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN14___S                            0

#define DBG_CTIIRQ_CTIOUTEN15                     (0x00B960DC)
#define   DBG_CTIIRQ_CTIOUTEN15___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN15___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN15___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN15___S                            0

#define DBG_CTIIRQ_CTIOUTEN16                     (0x00B960E0)
#define   DBG_CTIIRQ_CTIOUTEN16___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN16___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN16___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN16___S                            0

#define DBG_CTIIRQ_CTIOUTEN17                     (0x00B960E4)
#define   DBG_CTIIRQ_CTIOUTEN17___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN17___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN17___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN17___S                            0

#define DBG_CTIIRQ_CTIOUTEN18                     (0x00B960E8)
#define   DBG_CTIIRQ_CTIOUTEN18___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN18___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN18___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN18___S                            0

#define DBG_CTIIRQ_CTIOUTEN19                     (0x00B960EC)
#define   DBG_CTIIRQ_CTIOUTEN19___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN19___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN19___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN19___S                            0

#define DBG_CTIIRQ_CTIOUTEN20                     (0x00B960F0)
#define   DBG_CTIIRQ_CTIOUTEN20___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN20___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN20___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN20___S                            0

#define DBG_CTIIRQ_CTIOUTEN21                     (0x00B960F4)
#define   DBG_CTIIRQ_CTIOUTEN21___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN21___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN21___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN21___S                            0

#define DBG_CTIIRQ_CTIOUTEN22                     (0x00B960F8)
#define   DBG_CTIIRQ_CTIOUTEN22___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN22___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN22___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN22___S                            0

#define DBG_CTIIRQ_CTIOUTEN23                     (0x00B960FC)
#define   DBG_CTIIRQ_CTIOUTEN23___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN23___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN23___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN23___S                            0

#define DBG_CTIIRQ_CTIOUTEN24                     (0x00B96100)
#define   DBG_CTIIRQ_CTIOUTEN24___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN24___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN24___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN24___S                            0

#define DBG_CTIIRQ_CTIOUTEN25                     (0x00B96104)
#define   DBG_CTIIRQ_CTIOUTEN25___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN25___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN25___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN25___S                            0

#define DBG_CTIIRQ_CTIOUTEN26                     (0x00B96108)
#define   DBG_CTIIRQ_CTIOUTEN26___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN26___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN26___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN26___S                            0

#define DBG_CTIIRQ_CTIOUTEN27                     (0x00B9610C)
#define   DBG_CTIIRQ_CTIOUTEN27___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN27___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN27___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN27___S                            0

#define DBG_CTIIRQ_CTIOUTEN28                     (0x00B96110)
#define   DBG_CTIIRQ_CTIOUTEN28___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN28___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN28___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN28___S                            0

#define DBG_CTIIRQ_CTIOUTEN29                     (0x00B96114)
#define   DBG_CTIIRQ_CTIOUTEN29___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN29___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN29___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN29___S                            0

#define DBG_CTIIRQ_CTIOUTEN30                     (0x00B96118)
#define   DBG_CTIIRQ_CTIOUTEN30___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN30___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN30___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN30___S                            0

#define DBG_CTIIRQ_CTIOUTEN31                     (0x00B9611C)
#define   DBG_CTIIRQ_CTIOUTEN31___RWC               QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIOUTEN31___POR            0x00000000
#define   DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___POR 0x00
#define   DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___S                 0
#define   DBG_CTIIRQ_CTIOUTEN31___M              0x000000FF   
#define   DBG_CTIIRQ_CTIOUTEN31___S                            0

#define DBG_CTIIRQ_CTITRIGINSTATUS                (0x00B96130)
#define   DBG_CTIIRQ_CTITRIGINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_CTIIRQ_CTITRIGINSTATUS__TRIGINSTATUS___M 0xFFFFFFFF
#define   DBG_CTIIRQ_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_CTIIRQ_CTITRIGINSTATUS___M         0xFFFFFFFF   
#define   DBG_CTIIRQ_CTITRIGINSTATUS___S                       0

#define DBG_CTIIRQ_CTITRIGOUTSTATUS               (0x00B96134)
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS___POR      0x00000000
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00000000
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0xFFFFFFFF
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS___M        0xFFFFFFFF   
#define   DBG_CTIIRQ_CTITRIGOUTSTATUS___S                      0

#define DBG_CTIIRQ_CTICHINSTATUS                  (0x00B96138)
#define   DBG_CTIIRQ_CTICHINSTATUS___RWC            QCSR_REG_RO    
#define   DBG_CTIIRQ_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_CTIIRQ_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_CTIIRQ_CTICHINSTATUS___M           0x000000FF   
#define   DBG_CTIIRQ_CTICHINSTATUS___S                         0

#define DBG_CTIIRQ_CTICHOUTSTATUS                 (0x00B9613C)
#define   DBG_CTIIRQ_CTICHOUTSTATUS___RWC           QCSR_REG_RO    
#define   DBG_CTIIRQ_CTICHOUTSTATUS___POR        0x00000000
#define   DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_CTIIRQ_CTICHOUTSTATUS___M          0x000000FF   
#define   DBG_CTIIRQ_CTICHOUTSTATUS___S                        0

#define DBG_CTIIRQ_CTIGATE                        (0x00B96140)
#define   DBG_CTIIRQ_CTIGATE___RWC                  QCSR_REG_RW    
#define   DBG_CTIIRQ_CTIGATE___POR               0x000000FF
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN7___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN6___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN5___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN4___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN3___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN2___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN1___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN0___POR   0x1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN7___M     0x00000080
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN7___S                   7
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN6___M     0x00000040
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN6___S                   6
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN5___M     0x00000020
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN5___S                   5
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN4___M     0x00000010
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN4___S                   4
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN3___M     0x00000008
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN3___S                   3
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN2___M     0x00000004
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN2___S                   2
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN1___M     0x00000002
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN1___S                   1
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN0___M     0x00000001
#define   DBG_CTIIRQ_CTIGATE__CTIGATEEN0___S                   0
#define   DBG_CTIIRQ_CTIGATE___M                 0x000000FF   
#define   DBG_CTIIRQ_CTIGATE___S                               0

#define DBG_CTIIRQ_ASICCTL                        (0x00B96144)
#define   DBG_CTIIRQ_ASICCTL___RWC                  QCSR_REG_RW    
#define   DBG_CTIIRQ_ASICCTL___POR               0x00000000
#define   DBG_CTIIRQ_ASICCTL__ASICCTL___POR      0x00000000
#define   DBG_CTIIRQ_ASICCTL__ASICCTL___M        0xFFFFFFFF
#define   DBG_CTIIRQ_ASICCTL__ASICCTL___S                      0
#define   DBG_CTIIRQ_ASICCTL___M                 0xFFFFFFFF   
#define   DBG_CTIIRQ_ASICCTL___S                               0

#define DBG_CTIIRQ_ITCHINACK                      (0x00B96EDC)
#define   DBG_CTIIRQ_ITCHINACK___RWC                QCSR_REG_WO    
#define   DBG_CTIIRQ_ITCHINACK___POR             0x00000000
#define   DBG_CTIIRQ_ITCHINACK__CTCHINACK___POR  0x00
#define   DBG_CTIIRQ_ITCHINACK__CTCHINACK___M    0x000000FF
#define   DBG_CTIIRQ_ITCHINACK__CTCHINACK___S                  0
#define   DBG_CTIIRQ_ITCHINACK___M               0x000000FF   
#define   DBG_CTIIRQ_ITCHINACK___S                             0

#define DBG_CTIIRQ_ITTRIGINACK                    (0x00B96EE0)
#define   DBG_CTIIRQ_ITTRIGINACK___RWC              QCSR_REG_WO    
#define   DBG_CTIIRQ_ITTRIGINACK___POR           0x00000000
#define   DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___POR 0x00000000
#define   DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___M 0xFFFFFFFF
#define   DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_CTIIRQ_ITTRIGINACK___M             0xFFFFFFFF   
#define   DBG_CTIIRQ_ITTRIGINACK___S                           0

#define DBG_CTIIRQ_ITCHOUT                        (0x00B96EE4)
#define   DBG_CTIIRQ_ITCHOUT___RWC                  QCSR_REG_WO    
#define   DBG_CTIIRQ_ITCHOUT___POR               0x00000000
#define   DBG_CTIIRQ_ITCHOUT__CTCHOUT___POR      0x00
#define   DBG_CTIIRQ_ITCHOUT__CTCHOUT___M        0x000000FF
#define   DBG_CTIIRQ_ITCHOUT__CTCHOUT___S                      0
#define   DBG_CTIIRQ_ITCHOUT___M                 0x000000FF   
#define   DBG_CTIIRQ_ITCHOUT___S                               0

#define DBG_CTIIRQ_ITTRIGOUT                      (0x00B96EE8)
#define   DBG_CTIIRQ_ITTRIGOUT___RWC                QCSR_REG_WO    
#define   DBG_CTIIRQ_ITTRIGOUT___POR             0x00000000
#define   DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___POR  0x00000000
#define   DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___M    0xFFFFFFFF
#define   DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___S                  0
#define   DBG_CTIIRQ_ITTRIGOUT___M               0xFFFFFFFF   
#define   DBG_CTIIRQ_ITTRIGOUT___S                             0

#define DBG_CTIIRQ_ITCHOUTACK                     (0x00B96EEC)
#define   DBG_CTIIRQ_ITCHOUTACK___RWC               QCSR_REG_RO    
#define   DBG_CTIIRQ_ITCHOUTACK___POR            0x00000000
#define   DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___M  0x000000FF
#define   DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___S                0
#define   DBG_CTIIRQ_ITCHOUTACK___M              0x000000FF   
#define   DBG_CTIIRQ_ITCHOUTACK___S                            0

#define DBG_CTIIRQ_ITTRIGOUTACK                   (0x00B96EF0)
#define   DBG_CTIIRQ_ITTRIGOUTACK___RWC             QCSR_REG_RO    
#define   DBG_CTIIRQ_ITTRIGOUTACK___POR          0x00000000
#define   DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00000000
#define   DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___M 0xFFFFFFFF
#define   DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_CTIIRQ_ITTRIGOUTACK___M            0xFFFFFFFF   
#define   DBG_CTIIRQ_ITTRIGOUTACK___S                          0

#define DBG_CTIIRQ_ITCHIN                         (0x00B96EF4)
#define   DBG_CTIIRQ_ITCHIN___RWC                   QCSR_REG_RO    
#define   DBG_CTIIRQ_ITCHIN___POR                0x00000000
#define   DBG_CTIIRQ_ITCHIN__CTCHIN___POR        0x00
#define   DBG_CTIIRQ_ITCHIN__CTCHIN___M          0x000000FF
#define   DBG_CTIIRQ_ITCHIN__CTCHIN___S                        0
#define   DBG_CTIIRQ_ITCHIN___M                  0x000000FF   
#define   DBG_CTIIRQ_ITCHIN___S                                0

#define DBG_CTIIRQ_ITTRIGIN                       (0x00B96EF8)
#define   DBG_CTIIRQ_ITTRIGIN___RWC                 QCSR_REG_RO    
#define   DBG_CTIIRQ_ITTRIGIN___POR              0x00000000
#define   DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___POR    0x00000000
#define   DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___M      0xFFFFFFFF
#define   DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___S                    0
#define   DBG_CTIIRQ_ITTRIGIN___M                0xFFFFFFFF   
#define   DBG_CTIIRQ_ITTRIGIN___S                              0

#define DBG_CTIIRQ_ITCTRL                         (0x00B96F00)
#define   DBG_CTIIRQ_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_CTIIRQ_ITCTRL___POR                0x00000000
#define   DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_CTIIRQ_ITCTRL___M                  0x00000001   
#define   DBG_CTIIRQ_ITCTRL___S                                0

#define DBG_CTIIRQ_CLAIMSET                       (0x00B96FA0)
#define   DBG_CTIIRQ_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CLAIMSET___POR              0x0000000F
#define   DBG_CTIIRQ_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_CTIIRQ_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_CTIIRQ_CLAIMSET__CLAIMSET___S                    0
#define   DBG_CTIIRQ_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_CTIIRQ_CLAIMSET___M                0x0000000F   
#define   DBG_CTIIRQ_CLAIMSET___S                              0

#define DBG_CTIIRQ_CLAIMCLR                       (0x00B96FA4)
#define   DBG_CTIIRQ_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_CTIIRQ_CLAIMCLR___POR              0x00000000
#define   DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_CTIIRQ_CLAIMCLR___M                0x0000000F   
#define   DBG_CTIIRQ_CLAIMCLR___S                              0

#define DBG_CTIIRQ_DEVAFF0                        (0x00B96FA8)
#define   DBG_CTIIRQ_DEVAFF0___RWC                  QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVAFF0___POR               0x00000000
#define   DBG_CTIIRQ_DEVAFF0__VAL___POR          0x00000000
#define   DBG_CTIIRQ_DEVAFF0__VAL___M            0xFFFFFFFF
#define   DBG_CTIIRQ_DEVAFF0__VAL___S                          0
#define   DBG_CTIIRQ_DEVAFF0___M                 0xFFFFFFFF   
#define   DBG_CTIIRQ_DEVAFF0___S                               0

#define DBG_CTIIRQ_DEVAFF1                        (0x00B96FAC)
#define   DBG_CTIIRQ_DEVAFF1___RWC                  QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVAFF1___POR               0x00000000
#define   DBG_CTIIRQ_DEVAFF1__VAL___POR          0x00000000
#define   DBG_CTIIRQ_DEVAFF1__VAL___M            0xFFFFFFFF
#define   DBG_CTIIRQ_DEVAFF1__VAL___S                          0
#define   DBG_CTIIRQ_DEVAFF1___M                 0xFFFFFFFF   
#define   DBG_CTIIRQ_DEVAFF1___S                               0

#define DBG_CTIIRQ_LAR                            (0x00B96FB0)
#define   DBG_CTIIRQ_LAR___RWC                      QCSR_REG_WO    
#define   DBG_CTIIRQ_LAR__ACCESS_W___M           0xFFFFFFFF
#define   DBG_CTIIRQ_LAR__ACCESS_W___S                         0
#define   DBG_CTIIRQ_LAR__ACCESS_W__UNLOCK            0xC5ACCE55
#define   DBG_CTIIRQ_LAR___M                     0xFFFFFFFF   
#define   DBG_CTIIRQ_LAR___S                                   0

#define DBG_CTIIRQ_LSR                            (0x00B96FB4)
#define   DBG_CTIIRQ_LSR___RWC                      QCSR_REG_RO    
#define   DBG_CTIIRQ_LSR___POR                   0x00000003
#define   DBG_CTIIRQ_LSR__LOCKTYPE___POR         0x0
#define   DBG_CTIIRQ_LSR__LOCKGRANT___POR        0x1
#define   DBG_CTIIRQ_LSR__LOCKEXIST___POR        0x1
#define   DBG_CTIIRQ_LSR__LOCKTYPE___M           0x00000004
#define   DBG_CTIIRQ_LSR__LOCKTYPE___S                         2
#define   DBG_CTIIRQ_LSR__LOCKTYPE__SIZE_32BIT               0x0
#define   DBG_CTIIRQ_LSR__LOCKGRANT___M          0x00000002
#define   DBG_CTIIRQ_LSR__LOCKGRANT___S                        1
#define   DBG_CTIIRQ_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_CTIIRQ_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_CTIIRQ_LSR__LOCKEXIST___M          0x00000001
#define   DBG_CTIIRQ_LSR__LOCKEXIST___S                        0
#define   DBG_CTIIRQ_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_CTIIRQ_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_CTIIRQ_LSR___M                     0x00000007   
#define   DBG_CTIIRQ_LSR___S                                   0

#define DBG_CTIIRQ_AUTHSTATUS                     (0x00B96FB8)
#define   DBG_CTIIRQ_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CTIIRQ_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_CTIIRQ_AUTHSTATUS__SNID___S                      6
#define   DBG_CTIIRQ_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIIRQ_AUTHSTATUS__SID___M         0x00000030
#define   DBG_CTIIRQ_AUTHSTATUS__SID___S                       4
#define   DBG_CTIIRQ_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIIRQ_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_CTIIRQ_AUTHSTATUS__NSNID___S                     2
#define   DBG_CTIIRQ_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_CTIIRQ_AUTHSTATUS__NSNID__ENABLED              0x3
#define   DBG_CTIIRQ_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_CTIIRQ_AUTHSTATUS__NSID___S                      0
#define   DBG_CTIIRQ_AUTHSTATUS__NSID__DISABLED              0x2
#define   DBG_CTIIRQ_AUTHSTATUS__NSID__ENABLED               0x3
#define   DBG_CTIIRQ_AUTHSTATUS___M              0x000000FF   
#define   DBG_CTIIRQ_AUTHSTATUS___S                            0

#define DBG_CTIIRQ_DEVARCH                        (0x00B96FBC)
#define   DBG_CTIIRQ_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVARCH___POR               0x8EF00A14
#define   DBG_CTIIRQ_DEVARCH__ARCHITECT___POR    0x477
#define   DBG_CTIIRQ_DEVARCH__PRESENT___POR      0x1
#define   DBG_CTIIRQ_DEVARCH__REVISION___POR     0x0
#define   DBG_CTIIRQ_DEVARCH__ARCHID___POR       0x0A14
#define   DBG_CTIIRQ_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CTIIRQ_DEVARCH__ARCHITECT___S                   21
#define   DBG_CTIIRQ_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CTIIRQ_DEVARCH__PRESENT___S                     20
#define   DBG_CTIIRQ_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CTIIRQ_DEVARCH__REVISION___S                    16
#define   DBG_CTIIRQ_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CTIIRQ_DEVARCH__ARCHID___S                       0
#define   DBG_CTIIRQ_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CTIIRQ_DEVARCH___S                               0

#define DBG_CTIIRQ_DEVID2                         (0x00B96FC0)
#define   DBG_CTIIRQ_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVID2___POR                0x00000000
#define   DBG_CTIIRQ_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CTIIRQ_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CTIIRQ_DEVID2__IMPLDEF___S                       0
#define   DBG_CTIIRQ_DEVID2___M                  0x00000001   
#define   DBG_CTIIRQ_DEVID2___S                                0

#define DBG_CTIIRQ_DEVID1                         (0x00B96FC4)
#define   DBG_CTIIRQ_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVID1___POR                0x00000000
#define   DBG_CTIIRQ_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CTIIRQ_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CTIIRQ_DEVID1__IMPLDEF___S                       0
#define   DBG_CTIIRQ_DEVID1___M                  0x00000001   
#define   DBG_CTIIRQ_DEVID1___S                                0

#define DBG_CTIIRQ_DEVID                          (0x00B96FC8)
#define   DBG_CTIIRQ_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVID___POR                 0x00082000
#define   DBG_CTIIRQ_DEVID__NUMCH___POR          0x8
#define   DBG_CTIIRQ_DEVID__NUMTRIG___POR        0x20
#define   DBG_CTIIRQ_DEVID__EXTMUXNUM___POR      0x00
#define   DBG_CTIIRQ_DEVID__NUMCH___M            0x003F0000
#define   DBG_CTIIRQ_DEVID__NUMCH___S                         16
#define   DBG_CTIIRQ_DEVID__NUMTRIG___M          0x0000FF00
#define   DBG_CTIIRQ_DEVID__NUMTRIG___S                        8
#define   DBG_CTIIRQ_DEVID__EXTMUXNUM___M        0x0000001F
#define   DBG_CTIIRQ_DEVID__EXTMUXNUM___S                      0
#define   DBG_CTIIRQ_DEVID___M                   0x003FFF1F   
#define   DBG_CTIIRQ_DEVID___S                                 0

#define DBG_CTIIRQ_DEVTYPE                        (0x00B96FCC)
#define   DBG_CTIIRQ_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_CTIIRQ_DEVTYPE___POR               0x00000014
#define   DBG_CTIIRQ_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___POR   0x4
#define   DBG_CTIIRQ_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_CTIIRQ_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_CTIIRQ_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_CTIIRQ_DEVTYPE___M                 0x000000FF   
#define   DBG_CTIIRQ_DEVTYPE___S                               0

#define DBG_CTIIRQ_PIDR0                          (0x00B96FE0)
#define   DBG_CTIIRQ_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_PIDR0___POR                 0x00000006
#define   DBG_CTIIRQ_PIDR0__PART_0___POR         0x06
#define   DBG_CTIIRQ_PIDR0__PART_0___M           0x000000FF
#define   DBG_CTIIRQ_PIDR0__PART_0___S                         0
#define   DBG_CTIIRQ_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_CTIIRQ_PIDR0___M                   0x000000FF   
#define   DBG_CTIIRQ_PIDR0___S                                 0

#define DBG_CTIIRQ_PIDR1                          (0x00B96FE4)
#define   DBG_CTIIRQ_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_PIDR1___POR                 0x000000B9
#define   DBG_CTIIRQ_PIDR1__DES_0___POR          0xB
#define   DBG_CTIIRQ_PIDR1__PART_1___POR         0x9
#define   DBG_CTIIRQ_PIDR1__DES_0___M            0x000000F0
#define   DBG_CTIIRQ_PIDR1__DES_0___S                          4
#define   DBG_CTIIRQ_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_CTIIRQ_PIDR1__PART_1___M           0x0000000F
#define   DBG_CTIIRQ_PIDR1__PART_1___S                         0
#define   DBG_CTIIRQ_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_CTIIRQ_PIDR1___M                   0x000000FF   
#define   DBG_CTIIRQ_PIDR1___S                                 0

#define DBG_CTIIRQ_PIDR2                          (0x00B96FE8)
#define   DBG_CTIIRQ_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_PIDR2___POR                 0x0000004B
#define   DBG_CTIIRQ_PIDR2__REVISION___POR       0x4
#define   DBG_CTIIRQ_PIDR2__JEDEC___POR          0x1
#define   DBG_CTIIRQ_PIDR2__DES_1___POR          0x3
#define   DBG_CTIIRQ_PIDR2__REVISION___M         0x000000F0
#define   DBG_CTIIRQ_PIDR2__REVISION___S                       4
#define   DBG_CTIIRQ_PIDR2__REVISION__R0P4                   0x4
#define   DBG_CTIIRQ_PIDR2__REVISION__R0P5                   0x5
#define   DBG_CTIIRQ_PIDR2__JEDEC___M            0x00000008
#define   DBG_CTIIRQ_PIDR2__JEDEC___S                          3
#define   DBG_CTIIRQ_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_CTIIRQ_PIDR2__DES_1___M            0x00000007
#define   DBG_CTIIRQ_PIDR2__DES_1___S                          0
#define   DBG_CTIIRQ_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_CTIIRQ_PIDR2___M                   0x000000FF   
#define   DBG_CTIIRQ_PIDR2___S                                 0

#define DBG_CTIIRQ_PIDR3                          (0x00B96FEC)
#define   DBG_CTIIRQ_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_PIDR3___POR                 0x00000000
#define   DBG_CTIIRQ_PIDR3__REVAND___POR         0x0
#define   DBG_CTIIRQ_PIDR3__CMOD___POR           0x0
#define   DBG_CTIIRQ_PIDR3__REVAND___M           0x000000F0
#define   DBG_CTIIRQ_PIDR3__REVAND___S                         4
#define   DBG_CTIIRQ_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_CTIIRQ_PIDR3__CMOD___M             0x0000000F
#define   DBG_CTIIRQ_PIDR3__CMOD___S                           0
#define   DBG_CTIIRQ_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_CTIIRQ_PIDR3___M                   0x000000FF   
#define   DBG_CTIIRQ_PIDR3___S                                 0

#define DBG_CTIIRQ_PIDR4                          (0x00B96FD0)
#define   DBG_CTIIRQ_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_PIDR4___POR                 0x00000004
#define   DBG_CTIIRQ_PIDR4__SIZE___POR           0x0
#define   DBG_CTIIRQ_PIDR4__DES_2___POR          0x4
#define   DBG_CTIIRQ_PIDR4__SIZE___M             0x000000F0
#define   DBG_CTIIRQ_PIDR4__SIZE___S                           4
#define   DBG_CTIIRQ_PIDR4__SIZE__SIZE_4KB                   0x0
#define   DBG_CTIIRQ_PIDR4__DES_2___M            0x0000000F
#define   DBG_CTIIRQ_PIDR4__DES_2___S                          0
#define   DBG_CTIIRQ_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_CTIIRQ_PIDR4___M                   0x000000FF   
#define   DBG_CTIIRQ_PIDR4___S                                 0

#define DBG_CTIIRQ_PIDR5                          (0x00B96FD4)
#define   DBG_CTIIRQ_PIDR5___RWC                    QCSR_REG_RW    
#define   DBG_CTIIRQ_PIDR5__PERIPHID5___M        0xFFFFFFFF
#define   DBG_CTIIRQ_PIDR5__PERIPHID5___S                      0
#define   DBG_CTIIRQ_PIDR5___M                   0xFFFFFFFF   
#define   DBG_CTIIRQ_PIDR5___S                                 0

#define DBG_CTIIRQ_PIDR6                          (0x00B96FD8)
#define   DBG_CTIIRQ_PIDR6___RWC                    QCSR_REG_RW    
#define   DBG_CTIIRQ_PIDR6__PERIPHID6___M        0xFFFFFFFF
#define   DBG_CTIIRQ_PIDR6__PERIPHID6___S                      0
#define   DBG_CTIIRQ_PIDR6___M                   0xFFFFFFFF   
#define   DBG_CTIIRQ_PIDR6___S                                 0

#define DBG_CTIIRQ_PIDR7                          (0x00B96FDC)
#define   DBG_CTIIRQ_PIDR7___RWC                    QCSR_REG_RW    
#define   DBG_CTIIRQ_PIDR7__PERIPHID7___M        0xFFFFFFFF
#define   DBG_CTIIRQ_PIDR7__PERIPHID7___S                      0
#define   DBG_CTIIRQ_PIDR7___M                   0xFFFFFFFF   
#define   DBG_CTIIRQ_PIDR7___S                                 0

#define DBG_CTIIRQ_CIDR0                          (0x00B96FF0)
#define   DBG_CTIIRQ_CIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_CIDR0___POR                 0x0000000D
#define   DBG_CTIIRQ_CIDR0__PRMBL_0___POR        0x0D
#define   DBG_CTIIRQ_CIDR0__PRMBL_0___M          0x000000FF
#define   DBG_CTIIRQ_CIDR0__PRMBL_0___S                        0
#define   DBG_CTIIRQ_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_CTIIRQ_CIDR0___M                   0x000000FF   
#define   DBG_CTIIRQ_CIDR0___S                                 0

#define DBG_CTIIRQ_CIDR1                          (0x00B96FF4)
#define   DBG_CTIIRQ_CIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_CIDR1___POR                 0x00000090
#define   DBG_CTIIRQ_CIDR1__CLASS___POR          0x9
#define   DBG_CTIIRQ_CIDR1__PRMBL_1___POR        0x0
#define   DBG_CTIIRQ_CIDR1__CLASS___M            0x000000F0
#define   DBG_CTIIRQ_CIDR1__CLASS___S                          4
#define   DBG_CTIIRQ_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_CTIIRQ_CIDR1__PRMBL_1___M          0x0000000F
#define   DBG_CTIIRQ_CIDR1__PRMBL_1___S                        0
#define   DBG_CTIIRQ_CIDR1__PRMBL_1__ID_VALUE_0              0x0
#define   DBG_CTIIRQ_CIDR1___M                   0x000000FF   
#define   DBG_CTIIRQ_CIDR1___S                                 0

#define DBG_CTIIRQ_CIDR2                          (0x00B96FF8)
#define   DBG_CTIIRQ_CIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_CIDR2___POR                 0x00000005
#define   DBG_CTIIRQ_CIDR2__PRMBL_2___POR        0x05
#define   DBG_CTIIRQ_CIDR2__PRMBL_2___M          0x000000FF
#define   DBG_CTIIRQ_CIDR2__PRMBL_2___S                        0
#define   DBG_CTIIRQ_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_CTIIRQ_CIDR2___M                   0x000000FF   
#define   DBG_CTIIRQ_CIDR2___S                                 0

#define DBG_CTIIRQ_CIDR3                          (0x00B96FFC)
#define   DBG_CTIIRQ_CIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIIRQ_CIDR3___POR                 0x000000B1
#define   DBG_CTIIRQ_CIDR3__PRMBL_3___POR        0xB1
#define   DBG_CTIIRQ_CIDR3__PRMBL_3___M          0x000000FF
#define   DBG_CTIIRQ_CIDR3__PRMBL_3___S                        0
#define   DBG_CTIIRQ_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_CTIIRQ_CIDR3___M                   0x000000FF   
#define   DBG_CTIIRQ_CIDR3___S                                 0

#define DBG_EVENT_MACEVENT_CFG                    (0x00BB0000)
#define   DBG_EVENT_MACEVENT_CFG___RWC              QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_CFG___POR           0x00003BE3
#define   DBG_EVENT_MACEVENT_CFG__LMAC0_EN___POR 0x1
#define   DBG_EVENT_MACEVENT_CFG__UMAC_EN___POR  0x1
#define   DBG_EVENT_MACEVENT_CFG__ATID___POR     0x5F
#define   DBG_EVENT_MACEVENT_CFG__TRANSPORT___POR 0x0
#define   DBG_EVENT_MACEVENT_CFG__TRCCFG___POR   0x0
#define   DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___POR 0x0
#define   DBG_EVENT_MACEVENT_CFG__TSTMP_EN___POR 0x1
#define   DBG_EVENT_MACEVENT_CFG__ENABLE___POR   0x1
#define   DBG_EVENT_MACEVENT_CFG__LMAC0_EN___M   0x00002000
#define   DBG_EVENT_MACEVENT_CFG__LMAC0_EN___S                13
#define   DBG_EVENT_MACEVENT_CFG__UMAC_EN___M    0x00001000
#define   DBG_EVENT_MACEVENT_CFG__UMAC_EN___S                 12
#define   DBG_EVENT_MACEVENT_CFG__ATID___M       0x00000FE0
#define   DBG_EVENT_MACEVENT_CFG__ATID___S                     5
#define   DBG_EVENT_MACEVENT_CFG__TRANSPORT___M  0x00000010
#define   DBG_EVENT_MACEVENT_CFG__TRANSPORT___S                4
#define   DBG_EVENT_MACEVENT_CFG__TRANSPORT__CMB             0x0
#define   DBG_EVENT_MACEVENT_CFG__TRANSPORT__ATB             0x1
#define   DBG_EVENT_MACEVENT_CFG__TRCCFG___M     0x00000008
#define   DBG_EVENT_MACEVENT_CFG__TRCCFG___S                   3
#define   DBG_EVENT_MACEVENT_CFG__TRCCFG__CFG0               0x0
#define   DBG_EVENT_MACEVENT_CFG__TRCCFG__CFG1               0x1
#define   DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___M 0x00000004
#define   DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___S               2
#define   DBG_EVENT_MACEVENT_CFG__TSTMP_EN___M   0x00000002
#define   DBG_EVENT_MACEVENT_CFG__TSTMP_EN___S                 1
#define   DBG_EVENT_MACEVENT_CFG__ENABLE___M     0x00000001
#define   DBG_EVENT_MACEVENT_CFG__ENABLE___S                   0
#define   DBG_EVENT_MACEVENT_CFG___M             0x00003FFF   
#define   DBG_EVENT_MACEVENT_CFG___S                           0

#define DBG_EVENT_MACEVENT_TGU_CFG                (0x00BB0004)
#define   DBG_EVENT_MACEVENT_TGU_CFG___RWC          QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_TGU_CFG___POR       0x000000F0
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___POR 0x0
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___M 0x000000F0
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___S               4
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___M 0x0000000F
#define   DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___S               0
#define   DBG_EVENT_MACEVENT_TGU_CFG___M         0x000001FF   
#define   DBG_EVENT_MACEVENT_TGU_CFG___S                       0

#define DBG_EVENT_MACEVENT_MATCH0_DATA            (0x00BB0008)
#define   DBG_EVENT_MACEVENT_MATCH0_DATA___RWC      QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH0_DATA___POR   0x00000000
#define   DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___POR 0x00000000
#define   DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___M 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___S               0
#define   DBG_EVENT_MACEVENT_MATCH0_DATA___M     0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_MATCH0_DATA___S                   0

#define DBG_EVENT_MACEVENT_MATCH0_DATAH           (0x00BB000C)
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH___RWC     QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH___POR  0x00000000
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___POR 0x0
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___M 0x00000001
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___S               0
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH___M    0x00000001   
#define   DBG_EVENT_MACEVENT_MATCH0_DATAH___S                  0

#define DBG_EVENT_MACEVENT_MATCH0_MASK            (0x00BB0010)
#define   DBG_EVENT_MACEVENT_MATCH0_MASK___RWC      QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH0_MASK___POR   0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___M 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___S               0
#define   DBG_EVENT_MACEVENT_MATCH0_MASK___M     0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_MATCH0_MASK___S                   0

#define DBG_EVENT_MACEVENT_MATCH0_MASKH           (0x00BB0014)
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH___RWC     QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH___POR  0x00000001
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___POR 0x1
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___M 0x00000001
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___S               0
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH___M    0x00000001   
#define   DBG_EVENT_MACEVENT_MATCH0_MASKH___S                  0

#define DBG_EVENT_MACEVENT_MATCH1_DATA            (0x00BB0018)
#define   DBG_EVENT_MACEVENT_MATCH1_DATA___RWC      QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH1_DATA___POR   0x00000000
#define   DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___POR 0x00000000
#define   DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___M 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___S               0
#define   DBG_EVENT_MACEVENT_MATCH1_DATA___M     0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_MATCH1_DATA___S                   0

#define DBG_EVENT_MACEVENT_MATCH1_DATAH           (0x00BB001C)
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH___RWC     QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH___POR  0x00000000
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___POR 0x0
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___M 0x00000001
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___S               0
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH___M    0x00000001   
#define   DBG_EVENT_MACEVENT_MATCH1_DATAH___S                  0

#define DBG_EVENT_MACEVENT_MATCH1_MASK            (0x00BB0020)
#define   DBG_EVENT_MACEVENT_MATCH1_MASK___RWC      QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH1_MASK___POR   0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___M 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___S               0
#define   DBG_EVENT_MACEVENT_MATCH1_MASK___M     0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_MATCH1_MASK___S                   0

#define DBG_EVENT_MACEVENT_MATCH1_MASKH           (0x00BB0024)
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH___RWC     QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH___POR  0x00000001
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___POR 0x1
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___M 0x00000001
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___S               0
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH___M    0x00000001   
#define   DBG_EVENT_MACEVENT_MATCH1_MASKH___S                  0

#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK  (0x00BB0028)
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___POR 0x0000000F
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___M 0x0000000F   
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK (0x00BB002C)
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___POR 0x0000FFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___M 0x0000FFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0 (0x00BB0030)
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___M 0x80000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___S              31
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___M 0x40000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___S              30
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___M 0x20000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___S              29
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___M 0x10000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___S              28
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___M 0x08000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___S              27
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___M 0x04000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___S              26
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___M 0x02000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___S              25
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___M 0x01000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___S              24
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___M 0x00800000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___S              23
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___M 0x00400000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___S              22
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___M 0x00200000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___S              21
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___M 0x00100000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___S              20
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___M 0x00080000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___S              19
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___M 0x00040000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___S              18
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___M 0x00020000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___S              17
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___M 0x00010000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___S              16
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___M 0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1 (0x00BB0034)
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___M 0x80000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___S              31
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___M 0x40000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___S              30
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___M 0x20000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___S              29
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___M 0x10000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___S              28
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___M 0x08000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___S              27
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___M 0x04000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___S              26
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___M 0x02000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___S              25
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___M 0x01000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___S              24
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___M 0x00800000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___S              23
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___M 0x00400000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___S              22
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___M 0x00200000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___S              21
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___M 0x00100000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___S              20
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___M 0x00080000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___S              19
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___M 0x00040000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___S              18
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___M 0x00020000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___S              17
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___M 0x00010000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___S              16
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___M 0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK  (0x00BB0038)
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___POR 0x0000000F
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___M 0x0000000F   
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK (0x00BB003C)
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___POR 0x0000FFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___M 0x0000FFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0 (0x00BB0040)
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___M 0x80000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___S              31
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___M 0x40000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___S              30
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___M 0x20000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___S              29
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___M 0x10000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___S              28
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___M 0x08000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___S              27
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___M 0x04000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___S              26
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___M 0x02000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___S              25
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___M 0x01000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___S              24
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___M 0x00800000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___S              23
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___M 0x00400000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___S              22
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___M 0x00200000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___S              21
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___M 0x00100000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___S              20
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___M 0x00080000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___S              19
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___M 0x00040000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___S              18
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___M 0x00020000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___S              17
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___M 0x00010000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___S              16
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___M 0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___S               0

#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1 (0x00BB0044)
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___RWC QCSR_REG_RW    
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___POR 0xFFFFFFFF
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___POR 0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___M 0x80000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___S              31
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___M 0x40000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___S              30
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___M 0x20000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___S              29
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___M 0x10000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___S              28
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___M 0x08000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___S              27
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___M 0x04000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___S              26
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___M 0x02000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___S              25
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___M 0x01000000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___S              24
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___M 0x00800000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___S              23
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___M 0x00400000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___S              22
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___M 0x00200000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___S              21
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___M 0x00100000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___S              20
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___M 0x00080000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___S              19
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___M 0x00040000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___S              18
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___M 0x00020000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___S              17
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___M 0x00010000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___S              16
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___M 0x00008000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___S              15
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___M 0x00004000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___S              14
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___M 0x00002000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___S              13
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___M 0x00001000
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___S              12
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___M 0x00000800
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___S              11
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___M 0x00000400
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___S              10
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___M 0x00000200
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___S               9
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___M 0x00000100
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___S               8
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___M 0x00000080
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___S               7
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___M 0x00000040
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___S               6
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___M 0x00000020
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___S               5
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___M 0x00000010
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___S               4
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___M 0x00000008
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___S               3
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___M 0x00000004
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___S               2
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___M 0x00000002
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___S               1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___M 0x00000001
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___S               0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32__DISABLE             0x0
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32__ENABLE             0x1
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___M 0xFFFFFFFF   
#define   DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___S               0

#define DBG_EVENT_CS_ITCTL                        (0x00BB0F00)
#define   DBG_EVENT_CS_ITCTL___RWC                  QCSR_REG_RO    
#define   DBG_EVENT_CS_ITCTL___POR               0x00000000
#define   DBG_EVENT_CS_ITCTL__RFU___POR          0x00000000
#define   DBG_EVENT_CS_ITCTL__RFU___M            0xFFFFFFFF
#define   DBG_EVENT_CS_ITCTL__RFU___S                          0
#define   DBG_EVENT_CS_ITCTL___M                 0xFFFFFFFF   
#define   DBG_EVENT_CS_ITCTL___S                               0

#define DBG_EVENT_CS_CLAIMSET                     (0x00BB0FA0)
#define   DBG_EVENT_CS_CLAIMSET___RWC               QCSR_REG_RO    
#define   DBG_EVENT_CS_CLAIMSET___POR            0x00000000
#define   DBG_EVENT_CS_CLAIMSET__RFU___POR       0x00000000
#define   DBG_EVENT_CS_CLAIMSET__RFU___M         0xFFFFFFFF
#define   DBG_EVENT_CS_CLAIMSET__RFU___S                       0
#define   DBG_EVENT_CS_CLAIMSET___M              0xFFFFFFFF   
#define   DBG_EVENT_CS_CLAIMSET___S                            0

#define DBG_EVENT_CS_CLAIMCLR                     (0x00BB0FA4)
#define   DBG_EVENT_CS_CLAIMCLR___RWC               QCSR_REG_RO    
#define   DBG_EVENT_CS_CLAIMCLR___POR            0x00000000
#define   DBG_EVENT_CS_CLAIMCLR__RFU___POR       0x00000000
#define   DBG_EVENT_CS_CLAIMCLR__RFU___M         0xFFFFFFFF
#define   DBG_EVENT_CS_CLAIMCLR__RFU___S                       0
#define   DBG_EVENT_CS_CLAIMCLR___M              0xFFFFFFFF   
#define   DBG_EVENT_CS_CLAIMCLR___S                            0

#define DBG_EVENT_CS_LOCKACCESS                   (0x00BB0FB0)
#define   DBG_EVENT_CS_LOCKACCESS___RWC             QCSR_REG_RO    
#define   DBG_EVENT_CS_LOCKACCESS___POR          0x00000000
#define   DBG_EVENT_CS_LOCKACCESS__RFU___POR     0x00000000
#define   DBG_EVENT_CS_LOCKACCESS__RFU___M       0xFFFFFFFF
#define   DBG_EVENT_CS_LOCKACCESS__RFU___S                     0
#define   DBG_EVENT_CS_LOCKACCESS___M            0xFFFFFFFF   
#define   DBG_EVENT_CS_LOCKACCESS___S                          0

#define DBG_EVENT_CS_LOCKSTATUS                   (0x00BB0FB4)
#define   DBG_EVENT_CS_LOCKSTATUS___RWC             QCSR_REG_RO    
#define   DBG_EVENT_CS_LOCKSTATUS___POR          0x00000000
#define   DBG_EVENT_CS_LOCKSTATUS__RFU___POR     0x00000000
#define   DBG_EVENT_CS_LOCKSTATUS__RFU___M       0xFFFFFFFF
#define   DBG_EVENT_CS_LOCKSTATUS__RFU___S                     0
#define   DBG_EVENT_CS_LOCKSTATUS___M            0xFFFFFFFF   
#define   DBG_EVENT_CS_LOCKSTATUS___S                          0

#define DBG_EVENT_CS_AUTHSTATUS                   (0x00BB0FB8)
#define   DBG_EVENT_CS_AUTHSTATUS___RWC             QCSR_REG_RO    
#define   DBG_EVENT_CS_AUTHSTATUS__SI___M        0x000000C0
#define   DBG_EVENT_CS_AUTHSTATUS__SI___S                      6
#define   DBG_EVENT_CS_AUTHSTATUS__NSI___M       0x00000030
#define   DBG_EVENT_CS_AUTHSTATUS__NSI___S                     4
#define   DBG_EVENT_CS_AUTHSTATUS__SNI___M       0x0000000C
#define   DBG_EVENT_CS_AUTHSTATUS__SNI___S                     2
#define   DBG_EVENT_CS_AUTHSTATUS__NSNI___M      0x00000003
#define   DBG_EVENT_CS_AUTHSTATUS__NSNI___S                    0
#define   DBG_EVENT_CS_AUTHSTATUS___M            0x000000FF   
#define   DBG_EVENT_CS_AUTHSTATUS___S                          0

#define DBG_EVENT_CS_DEVARCH                      (0x00BB0FBC)
#define   DBG_EVENT_CS_DEVARCH___RWC                QCSR_REG_RO    
#define   DBG_EVENT_CS_DEVARCH___POR             0x0E100000
#define   DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0
#define   DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70
#define   DBG_EVENT_CS_DEVARCH__PRESENT___POR    0x1
#define   DBG_EVENT_CS_DEVARCH__REV___POR        0x0
#define   DBG_EVENT_CS_DEVARCH__ARCHID___POR     0x0000
#define   DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000
#define   DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___S              28
#define   DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000
#define   DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___S              21
#define   DBG_EVENT_CS_DEVARCH__PRESENT___M      0x00100000
#define   DBG_EVENT_CS_DEVARCH__PRESENT___S                   20
#define   DBG_EVENT_CS_DEVARCH__REV___M          0x000F0000
#define   DBG_EVENT_CS_DEVARCH__REV___S                       16
#define   DBG_EVENT_CS_DEVARCH__ARCHID___M       0x0000FFFF
#define   DBG_EVENT_CS_DEVARCH__ARCHID___S                     0
#define   DBG_EVENT_CS_DEVARCH___M               0xFFFFFFFF   
#define   DBG_EVENT_CS_DEVARCH___S                             0

#define DBG_EVENT_CS_DEVICEID                     (0x00BB0FC8)
#define   DBG_EVENT_CS_DEVICEID___RWC               QCSR_REG_RO    
#define   DBG_EVENT_CS_DEVICEID___POR            0x00000000
#define   DBG_EVENT_CS_DEVICEID__RFU___POR       0x000000
#define   DBG_EVENT_CS_DEVICEID__DEVID___POR     0x00
#define   DBG_EVENT_CS_DEVICEID__RFU___M         0xFFFFFF00
#define   DBG_EVENT_CS_DEVICEID__RFU___S                       8
#define   DBG_EVENT_CS_DEVICEID__DEVID___M       0x000000FF
#define   DBG_EVENT_CS_DEVICEID__DEVID___S                     0
#define   DBG_EVENT_CS_DEVICEID___M              0xFFFFFFFF   
#define   DBG_EVENT_CS_DEVICEID___S                            0

#define DBG_EVENT_CS_DEVICETYPE                   (0x00BB0FCC)
#define   DBG_EVENT_CS_DEVICETYPE___RWC             QCSR_REG_RO    
#define   DBG_EVENT_CS_DEVICETYPE___POR          0x00000003
#define   DBG_EVENT_CS_DEVICETYPE__RFU___POR     0x000000
#define   DBG_EVENT_CS_DEVICETYPE__SUBTYPE___POR 0x0
#define   DBG_EVENT_CS_DEVICETYPE__MAJTYPE___POR 0x3
#define   DBG_EVENT_CS_DEVICETYPE__RFU___M       0xFFFFFF00
#define   DBG_EVENT_CS_DEVICETYPE__RFU___S                     8
#define   DBG_EVENT_CS_DEVICETYPE__SUBTYPE___M   0x000000F0
#define   DBG_EVENT_CS_DEVICETYPE__SUBTYPE___S                 4
#define   DBG_EVENT_CS_DEVICETYPE__MAJTYPE___M   0x0000000F
#define   DBG_EVENT_CS_DEVICETYPE__MAJTYPE___S                 0
#define   DBG_EVENT_CS_DEVICETYPE___M            0xFFFFFFFF   
#define   DBG_EVENT_CS_DEVICETYPE___S                          0

#define DBG_EVENT_CS_PERIPHID4                    (0x00BB0FD0)
#define   DBG_EVENT_CS_PERIPHID4___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID4___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID4__RFU___POR      0x000000
#define   DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0
#define   DBG_EVENT_CS_PERIPHID4__RFU___M        0xFFFFFF00
#define   DBG_EVENT_CS_PERIPHID4__RFU___S                      8
#define   DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___S               4
#define   DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___S               0
#define   DBG_EVENT_CS_PERIPHID4___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID4___S                           0

#define DBG_EVENT_CS_PERIPHID5                    (0x00BB0FD4)
#define   DBG_EVENT_CS_PERIPHID5___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID5___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID5__RFU___POR      0x00000000
#define   DBG_EVENT_CS_PERIPHID5__RFU___M        0xFFFFFFFF
#define   DBG_EVENT_CS_PERIPHID5__RFU___S                      0
#define   DBG_EVENT_CS_PERIPHID5___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID5___S                           0

#define DBG_EVENT_CS_PERIPHID6                    (0x00BB0FD8)
#define   DBG_EVENT_CS_PERIPHID6___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID6___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID6__RFU___POR      0x00000000
#define   DBG_EVENT_CS_PERIPHID6__RFU___M        0xFFFFFFFF
#define   DBG_EVENT_CS_PERIPHID6__RFU___S                      0
#define   DBG_EVENT_CS_PERIPHID6___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID6___S                           0

#define DBG_EVENT_CS_PERIPHID7                    (0x00BB0FDC)
#define   DBG_EVENT_CS_PERIPHID7___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID7___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID7__RFU___POR      0x00000000
#define   DBG_EVENT_CS_PERIPHID7__RFU___M        0xFFFFFFFF
#define   DBG_EVENT_CS_PERIPHID7__RFU___S                      0
#define   DBG_EVENT_CS_PERIPHID7___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID7___S                           0

#define DBG_EVENT_CS_PERIPHID0                    (0x00BB0FE0)
#define   DBG_EVENT_CS_PERIPHID0___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID0___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID0__RFU___POR      0x000000
#define   DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___POR 0x0
#define   DBG_EVENT_CS_PERIPHID0__RFU___M        0xFFFFFF00
#define   DBG_EVENT_CS_PERIPHID0__RFU___S                      8
#define   DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF
#define   DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___S               0
#define   DBG_EVENT_CS_PERIPHID0___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID0___S                           0

#define DBG_EVENT_CS_PERIPHID1                    (0x00BB0FE4)
#define   DBG_EVENT_CS_PERIPHID1___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID1___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID1__RFU___POR      0x000000
#define   DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0
#define   DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___POR 0x0
#define   DBG_EVENT_CS_PERIPHID1__RFU___M        0xFFFFFF00
#define   DBG_EVENT_CS_PERIPHID1__RFU___S                      8
#define   DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0
#define   DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___S               4
#define   DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F
#define   DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___S               0
#define   DBG_EVENT_CS_PERIPHID1___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID1___S                           0

#define DBG_EVENT_CS_PERIPHID2                    (0x00BB0FE8)
#define   DBG_EVENT_CS_PERIPHID2___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID2___POR           0x0000000F
#define   DBG_EVENT_CS_PERIPHID2__RFU___POR      0x000000
#define   DBG_EVENT_CS_PERIPHID2__PERIPH_REV___POR 0x0
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ASS___POR 0x1
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7
#define   DBG_EVENT_CS_PERIPHID2__RFU___M        0xFFFFFF00
#define   DBG_EVENT_CS_PERIPHID2__RFU___S                      8
#define   DBG_EVENT_CS_PERIPHID2__PERIPH_REV___M 0x000000F0
#define   DBG_EVENT_CS_PERIPHID2__PERIPH_REV___S               4
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ASS___M 0x00000008
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ASS___S               3
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007
#define   DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___S               0
#define   DBG_EVENT_CS_PERIPHID2___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID2___S                           0

#define DBG_EVENT_CS_PERIPHID3                    (0x00BB0FEC)
#define   DBG_EVENT_CS_PERIPHID3___RWC              QCSR_REG_RO    
#define   DBG_EVENT_CS_PERIPHID3___POR           0x00000000
#define   DBG_EVENT_CS_PERIPHID3__RFU___POR      0x000000
#define   DBG_EVENT_CS_PERIPHID3__REV_AND___POR  0x0
#define   DBG_EVENT_CS_PERIPHID3__MODIFIED___POR 0x0
#define   DBG_EVENT_CS_PERIPHID3__RFU___M        0xFFFFFF00
#define   DBG_EVENT_CS_PERIPHID3__RFU___S                      8
#define   DBG_EVENT_CS_PERIPHID3__REV_AND___M    0x000000F0
#define   DBG_EVENT_CS_PERIPHID3__REV_AND___S                  4
#define   DBG_EVENT_CS_PERIPHID3__MODIFIED___M   0x0000000F
#define   DBG_EVENT_CS_PERIPHID3__MODIFIED___S                 0
#define   DBG_EVENT_CS_PERIPHID3___M             0xFFFFFFFF   
#define   DBG_EVENT_CS_PERIPHID3___S                           0

#define DBG_EVENT_CS_COMPID0                      (0x00BB0FF0)
#define   DBG_EVENT_CS_COMPID0___RWC                QCSR_REG_RO    
#define   DBG_EVENT_CS_COMPID0___POR             0x0000000D
#define   DBG_EVENT_CS_COMPID0__RFU___POR        0x000000
#define   DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___POR 0x0D
#define   DBG_EVENT_CS_COMPID0__RFU___M          0xFFFFFF00
#define   DBG_EVENT_CS_COMPID0__RFU___S                        8
#define   DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___M 0x000000FF
#define   DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___S               0
#define   DBG_EVENT_CS_COMPID0___M               0xFFFFFFFF   
#define   DBG_EVENT_CS_COMPID0___S                             0

#define DBG_EVENT_CS_COMPID1                      (0x00BB0FF4)
#define   DBG_EVENT_CS_COMPID1___RWC                QCSR_REG_RO    
#define   DBG_EVENT_CS_COMPID1___POR             0x00000090
#define   DBG_EVENT_CS_COMPID1__RFU___POR        0x000000
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___POR 0x9
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___POR 0x0
#define   DBG_EVENT_CS_COMPID1__RFU___M          0xFFFFFF00
#define   DBG_EVENT_CS_COMPID1__RFU___S                        8
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___S               4
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F
#define   DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___S               0
#define   DBG_EVENT_CS_COMPID1___M               0xFFFFFFFF   
#define   DBG_EVENT_CS_COMPID1___S                             0

#define DBG_EVENT_CS_COMPID2                      (0x00BB0FF8)
#define   DBG_EVENT_CS_COMPID2___RWC                QCSR_REG_RO    
#define   DBG_EVENT_CS_COMPID2___POR             0x00000005
#define   DBG_EVENT_CS_COMPID2__RFU___POR        0x000000
#define   DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___POR 0x05
#define   DBG_EVENT_CS_COMPID2__RFU___M          0xFFFFFF00
#define   DBG_EVENT_CS_COMPID2__RFU___S                        8
#define   DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___S               0
#define   DBG_EVENT_CS_COMPID2___M               0xFFFFFFFF   
#define   DBG_EVENT_CS_COMPID2___S                             0

#define DBG_EVENT_CS_COMPID3                      (0x00BB0FFC)
#define   DBG_EVENT_CS_COMPID3___RWC                QCSR_REG_RO    
#define   DBG_EVENT_CS_COMPID3___POR             0x000000B1
#define   DBG_EVENT_CS_COMPID3__RFU___POR        0x000000
#define   DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_EVENT_CS_COMPID3__RFU___M          0xFFFFFF00
#define   DBG_EVENT_CS_COMPID3__RFU___S                        8
#define   DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___S               0
#define   DBG_EVENT_CS_COMPID3___M               0xFFFFFFFF   
#define   DBG_EVENT_CS_COMPID3___S                             0

#define DBG_EVENTFUN_CTRL_REG                     (0x00BB1000)
#define   DBG_EVENTFUN_CTRL_REG___RWC               QCSR_REG_RW    
#define   DBG_EVENTFUN_CTRL_REG___POR            0x00000300
#define   DBG_EVENTFUN_CTRL_REG__HT___POR        0x3
#define   DBG_EVENTFUN_CTRL_REG__ENS7___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS6___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS5___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS4___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS3___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS2___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS1___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS0___POR      0x0
#define   DBG_EVENTFUN_CTRL_REG__HT___M          0x00000F00
#define   DBG_EVENTFUN_CTRL_REG__HT___S                        8
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X0                  0x0
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X1                  0x1
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X2                  0x2
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X3                  0x3
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X4                  0x4
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X5                  0x5
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X6                  0x6
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X7                  0x7
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X8                  0x8
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0X9                  0x9
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0XA                  0xA
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0XB                  0xB
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0XC                  0xC
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0XD                  0xD
#define   DBG_EVENTFUN_CTRL_REG__HT__HT_0XE                  0xE
#define   DBG_EVENTFUN_CTRL_REG__ENS7___M        0x00000080
#define   DBG_EVENTFUN_CTRL_REG__ENS7___S                      7
#define   DBG_EVENTFUN_CTRL_REG__ENS7__ENS7_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS7__ENS7_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS6___M        0x00000040
#define   DBG_EVENTFUN_CTRL_REG__ENS6___S                      6
#define   DBG_EVENTFUN_CTRL_REG__ENS6__ENS6_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS6__ENS6_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS5___M        0x00000020
#define   DBG_EVENTFUN_CTRL_REG__ENS5___S                      5
#define   DBG_EVENTFUN_CTRL_REG__ENS5__ENS5_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS5__ENS5_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS4___M        0x00000010
#define   DBG_EVENTFUN_CTRL_REG__ENS4___S                      4
#define   DBG_EVENTFUN_CTRL_REG__ENS4__ENS4_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS4__ENS4_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS3___M        0x00000008
#define   DBG_EVENTFUN_CTRL_REG__ENS3___S                      3
#define   DBG_EVENTFUN_CTRL_REG__ENS3__ENS3_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS3__ENS3_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS2___M        0x00000004
#define   DBG_EVENTFUN_CTRL_REG__ENS2___S                      2
#define   DBG_EVENTFUN_CTRL_REG__ENS2__ENS2_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS2__ENS2_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS1___M        0x00000002
#define   DBG_EVENTFUN_CTRL_REG__ENS1___S                      1
#define   DBG_EVENTFUN_CTRL_REG__ENS1__ENS1_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS1__ENS1_1                0x1
#define   DBG_EVENTFUN_CTRL_REG__ENS0___M        0x00000001
#define   DBG_EVENTFUN_CTRL_REG__ENS0___S                      0
#define   DBG_EVENTFUN_CTRL_REG__ENS0__ENS0_0                0x0
#define   DBG_EVENTFUN_CTRL_REG__ENS0__ENS0_1                0x1
#define   DBG_EVENTFUN_CTRL_REG___M              0x00000FFF   
#define   DBG_EVENTFUN_CTRL_REG___S                            0

#define DBG_EVENTFUN_PRIORITY_CTRL_REG            (0x00BB1004)
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG___RWC      QCSR_REG_RW    
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG___POR   0x00000000
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___S              21
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___S              18
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___S              15
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___S              12
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___S               9
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___S               6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG___M     0x00FFFFFF   
#define   DBG_EVENTFUN_PRIORITY_CTRL_REG___S                   0

#define DBG_EVENTFUN_ITATBDATA0                   (0x00BB1EEC)
#define   DBG_EVENTFUN_ITATBDATA0___RWC             QCSR_REG_RW    
#define   DBG_EVENTFUN_ITATBDATA0___POR          0x00000000
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA31___POR 0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA15___POR 0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA7___POR 0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA0___POR 0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA31___M  0x00000010
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA31___S                4
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_EVENTFUN_ITATBDATA0__ATDATAM23___M 0x00000008
#define   DBG_EVENTFUN_ITATBDATA0__ATDATAM23___S               3
#define   DBG_EVENTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA15___M  0x00000004
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA15___S                2
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA7___M   0x00000002
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA7___S                 1
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA0___M   0x00000001
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA0___S                 0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_EVENTFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_EVENTFUN_ITATBDATA0___M            0x0000001F   
#define   DBG_EVENTFUN_ITATBDATA0___S                          0

#define DBG_EVENTFUN_ITATBCTR2                    (0x00BB1EF0)
#define   DBG_EVENTFUN_ITATBCTR2___RWC              QCSR_REG_RW    
#define   DBG_EVENTFUN_ITATBCTR2___POR           0x00000000
#define   DBG_EVENTFUN_ITATBCTR2__AFVALID___POR  0x0
#define   DBG_EVENTFUN_ITATBCTR2__ATREADY___POR  0x0
#define   DBG_EVENTFUN_ITATBCTR2__AFVALID___M    0x00000002
#define   DBG_EVENTFUN_ITATBCTR2__AFVALID___S                  1
#define   DBG_EVENTFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_EVENTFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_EVENTFUN_ITATBCTR2__ATREADY___M    0x00000001
#define   DBG_EVENTFUN_ITATBCTR2__ATREADY___S                  0
#define   DBG_EVENTFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_EVENTFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_EVENTFUN_ITATBCTR2___M             0x00000003   
#define   DBG_EVENTFUN_ITATBCTR2___S                           0

#define DBG_EVENTFUN_ITATBCTR1                    (0x00BB1EF4)
#define   DBG_EVENTFUN_ITATBCTR1___RWC              QCSR_REG_RW    
#define   DBG_EVENTFUN_ITATBCTR1__ATID___M       0x0000007F
#define   DBG_EVENTFUN_ITATBCTR1__ATID___S                     0
#define   DBG_EVENTFUN_ITATBCTR1___M             0x0000007F   
#define   DBG_EVENTFUN_ITATBCTR1___S                           0

#define DBG_EVENTFUN_ITATBCTR0                    (0x00BB1EF8)
#define   DBG_EVENTFUN_ITATBCTR0___RWC              QCSR_REG_RW    
#define   DBG_EVENTFUN_ITATBCTR0___POR           0x00000000
#define   DBG_EVENTFUN_ITATBCTR0__ATBYTES___POR  0x0
#define   DBG_EVENTFUN_ITATBCTR0__AFREADY___POR  0x0
#define   DBG_EVENTFUN_ITATBCTR0__ATVALID___POR  0x0
#define   DBG_EVENTFUN_ITATBCTR0__ATBYTES___M    0x00000300
#define   DBG_EVENTFUN_ITATBCTR0__ATBYTES___S                  8
#define   DBG_EVENTFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_EVENTFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_EVENTFUN_ITATBCTR0__AFREADY___M    0x00000002
#define   DBG_EVENTFUN_ITATBCTR0__AFREADY___S                  1
#define   DBG_EVENTFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_EVENTFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_EVENTFUN_ITATBCTR0__ATVALID___M    0x00000001
#define   DBG_EVENTFUN_ITATBCTR0__ATVALID___S                  0
#define   DBG_EVENTFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_EVENTFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_EVENTFUN_ITATBCTR0___M             0x00000303   
#define   DBG_EVENTFUN_ITATBCTR0___S                           0

#define DBG_EVENTFUN_ITCTRL                       (0x00BB1F00)
#define   DBG_EVENTFUN_ITCTRL___RWC                 QCSR_REG_RW    
#define   DBG_EVENTFUN_ITCTRL___POR              0x00000000
#define   DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_EVENTFUN_ITCTRL___M                0x00000001   
#define   DBG_EVENTFUN_ITCTRL___S                              0

#define DBG_EVENTFUN_CLAIMSET                     (0x00BB1FA0)
#define   DBG_EVENTFUN_CLAIMSET___RWC               QCSR_REG_RW    
#define   DBG_EVENTFUN_CLAIMSET___POR            0x0000000F
#define   DBG_EVENTFUN_CLAIMSET__CLAIMSET___POR  0xF
#define   DBG_EVENTFUN_CLAIMSET__CLAIMSET___M    0x0000000F
#define   DBG_EVENTFUN_CLAIMSET__CLAIMSET___S                  0
#define   DBG_EVENTFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_EVENTFUN_CLAIMSET___M              0x0000000F   
#define   DBG_EVENTFUN_CLAIMSET___S                            0

#define DBG_EVENTFUN_CLAIMCLR                     (0x00BB1FA4)
#define   DBG_EVENTFUN_CLAIMCLR___RWC               QCSR_REG_RW    
#define   DBG_EVENTFUN_CLAIMCLR___POR            0x00000000
#define   DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___POR  0x0
#define   DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___M    0x0000000F
#define   DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___S                  0
#define   DBG_EVENTFUN_CLAIMCLR___M              0x0000000F   
#define   DBG_EVENTFUN_CLAIMCLR___S                            0

#define DBG_EVENTFUN_LOCKACCESS                   (0x00BB1FB0)
#define   DBG_EVENTFUN_LOCKACCESS___RWC             QCSR_REG_WO    
#define   DBG_EVENTFUN_LOCKACCESS__KEY___M       0xFFFFFFFF
#define   DBG_EVENTFUN_LOCKACCESS__KEY___S                     0
#define   DBG_EVENTFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_EVENTFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_EVENTFUN_LOCKACCESS___M            0xFFFFFFFF   
#define   DBG_EVENTFUN_LOCKACCESS___S                          0

#define DBG_EVENTFUN_LOCKSTATUS                   (0x00BB1FB4)
#define   DBG_EVENTFUN_LOCKSTATUS___RWC             QCSR_REG_RO    
#define   DBG_EVENTFUN_LOCKSTATUS___POR          0x00000003
#define   DBG_EVENTFUN_LOCKSTATUS__NTT___POR     0x0
#define   DBG_EVENTFUN_LOCKSTATUS__SLK___POR     0x1
#define   DBG_EVENTFUN_LOCKSTATUS__SLI___POR     0x1
#define   DBG_EVENTFUN_LOCKSTATUS__NTT___M       0x00000004
#define   DBG_EVENTFUN_LOCKSTATUS__NTT___S                     2
#define   DBG_EVENTFUN_LOCKSTATUS__NTT__NTT_0X0              0x0
#define   DBG_EVENTFUN_LOCKSTATUS__SLK___M       0x00000002
#define   DBG_EVENTFUN_LOCKSTATUS__SLK___S                     1
#define   DBG_EVENTFUN_LOCKSTATUS__SLK__SLK_0X0              0x0
#define   DBG_EVENTFUN_LOCKSTATUS__SLK__SLK_0X1              0x1
#define   DBG_EVENTFUN_LOCKSTATUS__SLI___M       0x00000001
#define   DBG_EVENTFUN_LOCKSTATUS__SLI___S                     0
#define   DBG_EVENTFUN_LOCKSTATUS__SLI__SLI_0X0              0x0
#define   DBG_EVENTFUN_LOCKSTATUS__SLI__SLI_0X1              0x1
#define   DBG_EVENTFUN_LOCKSTATUS___M            0x00000007   
#define   DBG_EVENTFUN_LOCKSTATUS___S                          0

#define DBG_EVENTFUN_AUTHSTATUS                   (0x00BB1FB8)
#define   DBG_EVENTFUN_AUTHSTATUS___RWC             QCSR_REG_RO    
#define   DBG_EVENTFUN_AUTHSTATUS___POR          0x00000000
#define   DBG_EVENTFUN_AUTHSTATUS__SNID___POR    0x0
#define   DBG_EVENTFUN_AUTHSTATUS__SID___POR     0x0
#define   DBG_EVENTFUN_AUTHSTATUS__NSNID___POR   0x0
#define   DBG_EVENTFUN_AUTHSTATUS__NSID___POR    0x0
#define   DBG_EVENTFUN_AUTHSTATUS__SNID___M      0x000000C0
#define   DBG_EVENTFUN_AUTHSTATUS__SNID___S                    6
#define   DBG_EVENTFUN_AUTHSTATUS__SNID__SNID_0X0             0x0
#define   DBG_EVENTFUN_AUTHSTATUS__SID___M       0x00000030
#define   DBG_EVENTFUN_AUTHSTATUS__SID___S                     4
#define   DBG_EVENTFUN_AUTHSTATUS__SID__SID_0X0              0x0
#define   DBG_EVENTFUN_AUTHSTATUS__NSNID___M     0x0000000C
#define   DBG_EVENTFUN_AUTHSTATUS__NSNID___S                   2
#define   DBG_EVENTFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_EVENTFUN_AUTHSTATUS__NSID___M      0x00000003
#define   DBG_EVENTFUN_AUTHSTATUS__NSID___S                    0
#define   DBG_EVENTFUN_AUTHSTATUS__NSID__NSID_0X0             0x0
#define   DBG_EVENTFUN_AUTHSTATUS___M            0x000000FF   
#define   DBG_EVENTFUN_AUTHSTATUS___S                          0

#define DBG_EVENTFUN_DEVID                        (0x00BB1FC8)
#define   DBG_EVENTFUN_DEVID___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_DEVID___POR               0x00000038
#define   DBG_EVENTFUN_DEVID__SCHEME___POR       0x3
#define   DBG_EVENTFUN_DEVID__PORTCOUNT___POR    0x8
#define   DBG_EVENTFUN_DEVID__SCHEME___M         0x000000F0
#define   DBG_EVENTFUN_DEVID__SCHEME___S                       4
#define   DBG_EVENTFUN_DEVID__SCHEME__SCHEME_0X3             0x3
#define   DBG_EVENTFUN_DEVID__PORTCOUNT___M      0x0000000F
#define   DBG_EVENTFUN_DEVID__PORTCOUNT___S                    0
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_EVENTFUN_DEVID___M                 0x000000FF   
#define   DBG_EVENTFUN_DEVID___S                               0

#define DBG_EVENTFUN_DEVTYPE                      (0x00BB1FCC)
#define   DBG_EVENTFUN_DEVTYPE___RWC                QCSR_REG_RO    
#define   DBG_EVENTFUN_DEVTYPE___POR             0x00000012
#define   DBG_EVENTFUN_DEVTYPE__SUB_TYPE___POR   0x1
#define   DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___POR 0x2
#define   DBG_EVENTFUN_DEVTYPE__SUB_TYPE___M     0x000000F0
#define   DBG_EVENTFUN_DEVTYPE__SUB_TYPE___S                   4
#define   DBG_EVENTFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___M   0x0000000F
#define   DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___S                 0
#define   DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_EVENTFUN_DEVTYPE___M               0x000000FF   
#define   DBG_EVENTFUN_DEVTYPE___S                             0

#define DBG_EVENTFUN_PIDR0                        (0x00BB1FE0)
#define   DBG_EVENTFUN_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_PIDR0___POR               0x00000008
#define   DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_EVENTFUN_PIDR0___M                 0x000000FF   
#define   DBG_EVENTFUN_PIDR0___S                               0

#define DBG_EVENTFUN_PIDR1                        (0x00BB1FE4)
#define   DBG_EVENTFUN_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_PIDR1___POR               0x000000B9
#define   DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0
#define   DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___S               4
#define   DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_EVENTFUN_PIDR1___M                 0x000000FF   
#define   DBG_EVENTFUN_PIDR1___S                               0

#define DBG_EVENTFUN_PIDR2                        (0x00BB1FE8)
#define   DBG_EVENTFUN_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_PIDR2___POR               0x0000003B
#define   DBG_EVENTFUN_PIDR2__REVISION___POR     0x3
#define   DBG_EVENTFUN_PIDR2__JEDEC___POR        0x1
#define   DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_EVENTFUN_PIDR2__REVISION___M       0x000000F0
#define   DBG_EVENTFUN_PIDR2__REVISION___S                     4
#define   DBG_EVENTFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_EVENTFUN_PIDR2__JEDEC___M          0x00000008
#define   DBG_EVENTFUN_PIDR2__JEDEC___S                        3
#define   DBG_EVENTFUN_PIDR2__JEDEC__JEDEC_0X1               0x1
#define   DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007
#define   DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___S               0
#define   DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_EVENTFUN_PIDR2___M                 0x000000FF   
#define   DBG_EVENTFUN_PIDR2___S                               0

#define DBG_EVENTFUN_PIDR3                        (0x00BB1FEC)
#define   DBG_EVENTFUN_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_PIDR3___POR               0x00000000
#define   DBG_EVENTFUN_PIDR3__REVAND___POR       0x0
#define   DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_EVENTFUN_PIDR3__REVAND___M         0x000000F0
#define   DBG_EVENTFUN_PIDR3__REVAND___S                       4
#define   DBG_EVENTFUN_PIDR3__REVAND__REVAND_0X0             0x0
#define   DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_EVENTFUN_PIDR3___M                 0x000000FF   
#define   DBG_EVENTFUN_PIDR3___S                               0

#define DBG_EVENTFUN_PIDR4                        (0x00BB1FD0)
#define   DBG_EVENTFUN_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_EVENTFUN_PIDR4___POR               0x00000004
#define   DBG_EVENTFUN_PIDR4__FOURKB_COUNT___POR 0x0
#define   DBG_EVENTFUN_PIDR4__JEP106_CONT___POR  0x4
#define   DBG_EVENTFUN_PIDR4__FOURKB_COUNT___M   0x000000F0
#define   DBG_EVENTFUN_PIDR4__FOURKB_COUNT___S                 4
#define   DBG_EVENTFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_EVENTFUN_PIDR4__JEP106_CONT___M    0x0000000F
#define   DBG_EVENTFUN_PIDR4__JEP106_CONT___S                  0
#define   DBG_EVENTFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_EVENTFUN_PIDR4___M                 0x000000FF   
#define   DBG_EVENTFUN_PIDR4___S                               0

#define DBG_EVENTFUN_PERIPHID5                    (0x00BB1FD4)
#define   DBG_EVENTFUN_PERIPHID5___RWC              QCSR_REG_RO    
#define   DBG_EVENTFUN_PERIPHID5___POR           0x00000000
#define   DBG_EVENTFUN_PERIPHID5__PERIPHID5___POR 0x00000000
#define   DBG_EVENTFUN_PERIPHID5__PERIPHID5___M  0xFFFFFFFF
#define   DBG_EVENTFUN_PERIPHID5__PERIPHID5___S                0
#define   DBG_EVENTFUN_PERIPHID5___M             0xFFFFFFFF   
#define   DBG_EVENTFUN_PERIPHID5___S                           0

#define DBG_EVENTFUN_PERIPHID6                    (0x00BB1FD8)
#define   DBG_EVENTFUN_PERIPHID6___RWC              QCSR_REG_RO    
#define   DBG_EVENTFUN_PERIPHID6___POR           0x00000000
#define   DBG_EVENTFUN_PERIPHID6__PERIPHID6___POR 0x00000000
#define   DBG_EVENTFUN_PERIPHID6__PERIPHID6___M  0xFFFFFFFF
#define   DBG_EVENTFUN_PERIPHID6__PERIPHID6___S                0
#define   DBG_EVENTFUN_PERIPHID6___M             0xFFFFFFFF   
#define   DBG_EVENTFUN_PERIPHID6___S                           0

#define DBG_EVENTFUN_PERIPHID7                    (0x00BB1FDC)
#define   DBG_EVENTFUN_PERIPHID7___RWC              QCSR_REG_RO    
#define   DBG_EVENTFUN_PERIPHID7___POR           0x00000000
#define   DBG_EVENTFUN_PERIPHID7__PERIPHID7___POR 0x00000000
#define   DBG_EVENTFUN_PERIPHID7__PERIPHID7___M  0xFFFFFFFF
#define   DBG_EVENTFUN_PERIPHID7__PERIPHID7___S                0
#define   DBG_EVENTFUN_PERIPHID7___M             0xFFFFFFFF   
#define   DBG_EVENTFUN_PERIPHID7___S                           0

#define DBG_EVENTFUN_CID0                         (0x00BB1FF0)
#define   DBG_EVENTFUN_CID0___RWC                   QCSR_REG_RO    
#define   DBG_EVENTFUN_CID0___POR                0x0000000D
#define   DBG_EVENTFUN_CID0__PREAMBLE___POR      0x0D
#define   DBG_EVENTFUN_CID0__PREAMBLE___M        0x000000FF
#define   DBG_EVENTFUN_CID0__PREAMBLE___S                      0
#define   DBG_EVENTFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_EVENTFUN_CID0___M                  0x000000FF   
#define   DBG_EVENTFUN_CID0___S                                0

#define DBG_EVENTFUN_CID1                         (0x00BB1FF4)
#define   DBG_EVENTFUN_CID1___RWC                   QCSR_REG_RO    
#define   DBG_EVENTFUN_CID1___POR                0x00000090
#define   DBG_EVENTFUN_CID1__CLASS___POR         0x9
#define   DBG_EVENTFUN_CID1__PREAMBLE___POR      0x0
#define   DBG_EVENTFUN_CID1__CLASS___M           0x000000F0
#define   DBG_EVENTFUN_CID1__CLASS___S                         4
#define   DBG_EVENTFUN_CID1__CLASS__CLASS_0X9                0x9
#define   DBG_EVENTFUN_CID1__PREAMBLE___M        0x0000000F
#define   DBG_EVENTFUN_CID1__PREAMBLE___S                      0
#define   DBG_EVENTFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_EVENTFUN_CID1___M                  0x000000FF   
#define   DBG_EVENTFUN_CID1___S                                0

#define DBG_EVENTFUN_CID2                         (0x00BB1FF8)
#define   DBG_EVENTFUN_CID2___RWC                   QCSR_REG_RO    
#define   DBG_EVENTFUN_CID2___POR                0x00000005
#define   DBG_EVENTFUN_CID2__PREAMBLE___POR      0x05
#define   DBG_EVENTFUN_CID2__PREAMBLE___M        0x000000FF
#define   DBG_EVENTFUN_CID2__PREAMBLE___S                      0
#define   DBG_EVENTFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_EVENTFUN_CID2___M                  0x000000FF   
#define   DBG_EVENTFUN_CID2___S                                0

#define DBG_EVENTFUN_CID3                         (0x00BB1FFC)
#define   DBG_EVENTFUN_CID3___RWC                   QCSR_REG_RO    
#define   DBG_EVENTFUN_CID3___POR                0x000000B1
#define   DBG_EVENTFUN_CID3__PREAMBLE___POR      0xB1
#define   DBG_EVENTFUN_CID3__PREAMBLE___M        0x000000FF
#define   DBG_EVENTFUN_CID3__PREAMBLE___S                      0
#define   DBG_EVENTFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_EVENTFUN_CID3___M                  0x000000FF   
#define   DBG_EVENTFUN_CID3___S                                0

#define DBG_TLV_MACTLV_CFG                        (0x00BB2000)
#define   DBG_TLV_MACTLV_CFG___RWC                  QCSR_REG_RW    
#define   DBG_TLV_MACTLV_CFG___POR               0x00000DE3
#define   DBG_TLV_MACTLV_CFG__LMAC0_EN___POR     0x1
#define   DBG_TLV_MACTLV_CFG__ATID___POR         0x5E
#define   DBG_TLV_MACTLV_CFG__TRANSPORT___POR    0x0
#define   DBG_TLV_MACTLV_CFG__COLTRIG_EN___POR   0x0
#define   DBG_TLV_MACTLV_CFG__TSTMP_EN___POR     0x1
#define   DBG_TLV_MACTLV_CFG__ENABLE___POR       0x1
#define   DBG_TLV_MACTLV_CFG__LMAC0_EN___M       0x00000800
#define   DBG_TLV_MACTLV_CFG__LMAC0_EN___S                    11
#define   DBG_TLV_MACTLV_CFG__ATID___M           0x000007F0
#define   DBG_TLV_MACTLV_CFG__ATID___S                         4
#define   DBG_TLV_MACTLV_CFG__TRANSPORT___M      0x00000008
#define   DBG_TLV_MACTLV_CFG__TRANSPORT___S                    3
#define   DBG_TLV_MACTLV_CFG__TRANSPORT__CMB                 0x0
#define   DBG_TLV_MACTLV_CFG__TRANSPORT__ATB                 0x1
#define   DBG_TLV_MACTLV_CFG__COLTRIG_EN___M     0x00000004
#define   DBG_TLV_MACTLV_CFG__COLTRIG_EN___S                   2
#define   DBG_TLV_MACTLV_CFG__TSTMP_EN___M       0x00000002
#define   DBG_TLV_MACTLV_CFG__TSTMP_EN___S                     1
#define   DBG_TLV_MACTLV_CFG__ENABLE___M         0x00000001
#define   DBG_TLV_MACTLV_CFG__ENABLE___S                       0
#define   DBG_TLV_MACTLV_CFG___M                 0x00000FFF   
#define   DBG_TLV_MACTLV_CFG___S                               0

#define DBG_TLV_MACTLV_TGU_CFG                    (0x00BB2004)
#define   DBG_TLV_MACTLV_TGU_CFG___RWC              QCSR_REG_RW    
#define   DBG_TLV_MACTLV_TGU_CFG___POR           0x000000F0
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___POR  0x0
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___M   0x000000F0
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___S                 4
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___M    0x0000000F
#define   DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___S                  0
#define   DBG_TLV_MACTLV_TGU_CFG___M             0x000001FF   
#define   DBG_TLV_MACTLV_TGU_CFG___S                           0

#define DBG_TLV_MACTLV_MATCH0_DATA                (0x00BB2008)
#define   DBG_TLV_MACTLV_MATCH0_DATA___RWC          QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH0_DATA___POR       0x00000000
#define   DBG_TLV_MACTLV_MATCH0_DATA__DATA___POR 0x00000000
#define   DBG_TLV_MACTLV_MATCH0_DATA__DATA___M   0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH0_DATA__DATA___S                 0
#define   DBG_TLV_MACTLV_MATCH0_DATA___M         0xFFFFFFFF   
#define   DBG_TLV_MACTLV_MATCH0_DATA___S                       0

#define DBG_TLV_MACTLV_MATCH0_DATAH               (0x00BB200C)
#define   DBG_TLV_MACTLV_MATCH0_DATAH___RWC         QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH0_DATAH___POR      0x00000000
#define   DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___POR 0x00000
#define   DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___M 0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___S               0
#define   DBG_TLV_MACTLV_MATCH0_DATAH___M        0x0001FFFF   
#define   DBG_TLV_MACTLV_MATCH0_DATAH___S                      0

#define DBG_TLV_MACTLV_MATCH0_MASK                (0x00BB2010)
#define   DBG_TLV_MACTLV_MATCH0_MASK___RWC          QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH0_MASK___POR       0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH0_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH0_MASK__MASK___M   0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH0_MASK__MASK___S                 0
#define   DBG_TLV_MACTLV_MATCH0_MASK___M         0xFFFFFFFF   
#define   DBG_TLV_MACTLV_MATCH0_MASK___S                       0

#define DBG_TLV_MACTLV_MATCH0_MASKH               (0x00BB2014)
#define   DBG_TLV_MACTLV_MATCH0_MASKH___RWC         QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH0_MASKH___POR      0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___POR 0x1FFFF
#define   DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___M 0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___S               0
#define   DBG_TLV_MACTLV_MATCH0_MASKH___M        0x0001FFFF   
#define   DBG_TLV_MACTLV_MATCH0_MASKH___S                      0

#define DBG_TLV_MACTLV_MATCH1_DATA                (0x00BB2018)
#define   DBG_TLV_MACTLV_MATCH1_DATA___RWC          QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH1_DATA___POR       0x00000000
#define   DBG_TLV_MACTLV_MATCH1_DATA__DATA___POR 0x00000000
#define   DBG_TLV_MACTLV_MATCH1_DATA__DATA___M   0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH1_DATA__DATA___S                 0
#define   DBG_TLV_MACTLV_MATCH1_DATA___M         0xFFFFFFFF   
#define   DBG_TLV_MACTLV_MATCH1_DATA___S                       0

#define DBG_TLV_MACTLV_MATCH1_DATAH               (0x00BB201C)
#define   DBG_TLV_MACTLV_MATCH1_DATAH___RWC         QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH1_DATAH___POR      0x00000000
#define   DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___POR 0x00000
#define   DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___M 0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___S               0
#define   DBG_TLV_MACTLV_MATCH1_DATAH___M        0x0001FFFF   
#define   DBG_TLV_MACTLV_MATCH1_DATAH___S                      0

#define DBG_TLV_MACTLV_MATCH1_MASK                (0x00BB2020)
#define   DBG_TLV_MACTLV_MATCH1_MASK___RWC          QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH1_MASK___POR       0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH1_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH1_MASK__MASK___M   0xFFFFFFFF
#define   DBG_TLV_MACTLV_MATCH1_MASK__MASK___S                 0
#define   DBG_TLV_MACTLV_MATCH1_MASK___M         0xFFFFFFFF   
#define   DBG_TLV_MACTLV_MATCH1_MASK___S                       0

#define DBG_TLV_MACTLV_MATCH1_MASKH               (0x00BB2024)
#define   DBG_TLV_MACTLV_MATCH1_MASKH___RWC         QCSR_REG_RW    
#define   DBG_TLV_MACTLV_MATCH1_MASKH___POR      0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___POR 0x1FFFF
#define   DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___M 0x0001FFFF
#define   DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___S               0
#define   DBG_TLV_MACTLV_MATCH1_MASKH___M        0x0001FFFF   
#define   DBG_TLV_MACTLV_MATCH1_MASKH___S                      0

#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK       (0x00BB2028)
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___POR 0x0000000F
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___M 0x0000000F   
#define   DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0     (0x00BB2040)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1     (0x00BB2044)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2     (0x00BB2048)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3     (0x00BB204C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4     (0x00BB2050)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5     (0x00BB2054)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6     (0x00BB2058)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7     (0x00BB205C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8     (0x00BB2060)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9     (0x00BB2064)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10    (0x00BB2068)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11    (0x00BB206C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12    (0x00BB2070)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13    (0x00BB2074)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14    (0x00BB2078)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15    (0x00BB207C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480__DISABLE             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480__ENABLE             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0 (0x00BB2080)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1 (0x00BB2084)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2 (0x00BB2088)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3 (0x00BB208C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4 (0x00BB2090)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5 (0x00BB2094)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6 (0x00BB2098)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7 (0x00BB209C)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8 (0x00BB20A0)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9 (0x00BB20A4)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10 (0x00BB20A8)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11 (0x00BB20AC)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12 (0x00BB20B0)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13 (0x00BB20B4)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14 (0x00BB20B8)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___S               0

#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15 (0x00BB20BC)
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___RWC QCSR_REG_RW    
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___POR 0xFFFFFFFF
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___POR 0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___M 0x80000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___S              31
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___M 0x40000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___S              30
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___M 0x20000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___S              29
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___M 0x10000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___S              28
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___M 0x08000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___S              27
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___M 0x04000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___S              26
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___M 0x02000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___S              25
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___M 0x01000000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___S              24
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___M 0x00800000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___S              23
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___M 0x00400000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___S              22
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___M 0x00200000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___S              21
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___M 0x00100000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___S              20
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___M 0x00080000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___S              19
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___M 0x00040000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___S              18
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___M 0x00020000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___S              17
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___M 0x00010000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___S              16
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___M 0x00008000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___S              15
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___M 0x00004000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___S              14
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___M 0x00002000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___S              13
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___M 0x00001000
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___S              12
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___M 0x00000800
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___S              11
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___M 0x00000400
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___S              10
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___M 0x00000200
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___S               9
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___M 0x00000100
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___S               8
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___M 0x00000080
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___S               7
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___M 0x00000040
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___S               6
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___M 0x00000020
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___S               5
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___M 0x00000010
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___S               4
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___M 0x00000008
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___S               3
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___M 0x00000004
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___S               2
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___M 0x00000002
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___S               1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___M 0x00000001
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___S               0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480__HDRPLUSDATA             0x0
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480__HDRONLY             0x1
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___M 0xFFFFFFFF   
#define   DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___S               0

#define DBG_TLV_CS_ITCTL                          (0x00BB2F00)
#define   DBG_TLV_CS_ITCTL___RWC                    QCSR_REG_RO    
#define   DBG_TLV_CS_ITCTL___POR                 0x00000000
#define   DBG_TLV_CS_ITCTL__RFU___POR            0x00000000
#define   DBG_TLV_CS_ITCTL__RFU___M              0xFFFFFFFF
#define   DBG_TLV_CS_ITCTL__RFU___S                            0
#define   DBG_TLV_CS_ITCTL___M                   0xFFFFFFFF   
#define   DBG_TLV_CS_ITCTL___S                                 0

#define DBG_TLV_CS_CLAIMSET                       (0x00BB2FA0)
#define   DBG_TLV_CS_CLAIMSET___RWC                 QCSR_REG_RO    
#define   DBG_TLV_CS_CLAIMSET___POR              0x00000000
#define   DBG_TLV_CS_CLAIMSET__RFU___POR         0x00000000
#define   DBG_TLV_CS_CLAIMSET__RFU___M           0xFFFFFFFF
#define   DBG_TLV_CS_CLAIMSET__RFU___S                         0
#define   DBG_TLV_CS_CLAIMSET___M                0xFFFFFFFF   
#define   DBG_TLV_CS_CLAIMSET___S                              0

#define DBG_TLV_CS_CLAIMCLR                       (0x00BB2FA4)
#define   DBG_TLV_CS_CLAIMCLR___RWC                 QCSR_REG_RO    
#define   DBG_TLV_CS_CLAIMCLR___POR              0x00000000
#define   DBG_TLV_CS_CLAIMCLR__RFU___POR         0x00000000
#define   DBG_TLV_CS_CLAIMCLR__RFU___M           0xFFFFFFFF
#define   DBG_TLV_CS_CLAIMCLR__RFU___S                         0
#define   DBG_TLV_CS_CLAIMCLR___M                0xFFFFFFFF   
#define   DBG_TLV_CS_CLAIMCLR___S                              0

#define DBG_TLV_CS_LOCKACCESS                     (0x00BB2FB0)
#define   DBG_TLV_CS_LOCKACCESS___RWC               QCSR_REG_RO    
#define   DBG_TLV_CS_LOCKACCESS___POR            0x00000000
#define   DBG_TLV_CS_LOCKACCESS__RFU___POR       0x00000000
#define   DBG_TLV_CS_LOCKACCESS__RFU___M         0xFFFFFFFF
#define   DBG_TLV_CS_LOCKACCESS__RFU___S                       0
#define   DBG_TLV_CS_LOCKACCESS___M              0xFFFFFFFF   
#define   DBG_TLV_CS_LOCKACCESS___S                            0

#define DBG_TLV_CS_LOCKSTATUS                     (0x00BB2FB4)
#define   DBG_TLV_CS_LOCKSTATUS___RWC               QCSR_REG_RO    
#define   DBG_TLV_CS_LOCKSTATUS___POR            0x00000000
#define   DBG_TLV_CS_LOCKSTATUS__RFU___POR       0x00000000
#define   DBG_TLV_CS_LOCKSTATUS__RFU___M         0xFFFFFFFF
#define   DBG_TLV_CS_LOCKSTATUS__RFU___S                       0
#define   DBG_TLV_CS_LOCKSTATUS___M              0xFFFFFFFF   
#define   DBG_TLV_CS_LOCKSTATUS___S                            0

#define DBG_TLV_CS_AUTHSTATUS                     (0x00BB2FB8)
#define   DBG_TLV_CS_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_TLV_CS_AUTHSTATUS__SI___M          0x000000C0
#define   DBG_TLV_CS_AUTHSTATUS__SI___S                        6
#define   DBG_TLV_CS_AUTHSTATUS__NSI___M         0x00000030
#define   DBG_TLV_CS_AUTHSTATUS__NSI___S                       4
#define   DBG_TLV_CS_AUTHSTATUS__SNI___M         0x0000000C
#define   DBG_TLV_CS_AUTHSTATUS__SNI___S                       2
#define   DBG_TLV_CS_AUTHSTATUS__NSNI___M        0x00000003
#define   DBG_TLV_CS_AUTHSTATUS__NSNI___S                      0
#define   DBG_TLV_CS_AUTHSTATUS___M              0x000000FF   
#define   DBG_TLV_CS_AUTHSTATUS___S                            0

#define DBG_TLV_CS_DEVARCH                        (0x00BB2FBC)
#define   DBG_TLV_CS_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_TLV_CS_DEVARCH___POR               0x0E100000
#define   DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0
#define   DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70
#define   DBG_TLV_CS_DEVARCH__PRESENT___POR      0x1
#define   DBG_TLV_CS_DEVARCH__REV___POR          0x0
#define   DBG_TLV_CS_DEVARCH__ARCHID___POR       0x0000
#define   DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000
#define   DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___S              28
#define   DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000
#define   DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___S              21
#define   DBG_TLV_CS_DEVARCH__PRESENT___M        0x00100000
#define   DBG_TLV_CS_DEVARCH__PRESENT___S                     20
#define   DBG_TLV_CS_DEVARCH__REV___M            0x000F0000
#define   DBG_TLV_CS_DEVARCH__REV___S                         16
#define   DBG_TLV_CS_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_TLV_CS_DEVARCH__ARCHID___S                       0
#define   DBG_TLV_CS_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_TLV_CS_DEVARCH___S                               0

#define DBG_TLV_CS_DEVICEID                       (0x00BB2FC8)
#define   DBG_TLV_CS_DEVICEID___RWC                 QCSR_REG_RO    
#define   DBG_TLV_CS_DEVICEID___POR              0x00000000
#define   DBG_TLV_CS_DEVICEID__RFU___POR         0x000000
#define   DBG_TLV_CS_DEVICEID__DEVID___POR       0x00
#define   DBG_TLV_CS_DEVICEID__RFU___M           0xFFFFFF00
#define   DBG_TLV_CS_DEVICEID__RFU___S                         8
#define   DBG_TLV_CS_DEVICEID__DEVID___M         0x000000FF
#define   DBG_TLV_CS_DEVICEID__DEVID___S                       0
#define   DBG_TLV_CS_DEVICEID___M                0xFFFFFFFF   
#define   DBG_TLV_CS_DEVICEID___S                              0

#define DBG_TLV_CS_DEVICETYPE                     (0x00BB2FCC)
#define   DBG_TLV_CS_DEVICETYPE___RWC               QCSR_REG_RO    
#define   DBG_TLV_CS_DEVICETYPE___POR            0x00000003
#define   DBG_TLV_CS_DEVICETYPE__RFU___POR       0x000000
#define   DBG_TLV_CS_DEVICETYPE__SUBTYPE___POR   0x0
#define   DBG_TLV_CS_DEVICETYPE__MAJTYPE___POR   0x3
#define   DBG_TLV_CS_DEVICETYPE__RFU___M         0xFFFFFF00
#define   DBG_TLV_CS_DEVICETYPE__RFU___S                       8
#define   DBG_TLV_CS_DEVICETYPE__SUBTYPE___M     0x000000F0
#define   DBG_TLV_CS_DEVICETYPE__SUBTYPE___S                   4
#define   DBG_TLV_CS_DEVICETYPE__MAJTYPE___M     0x0000000F
#define   DBG_TLV_CS_DEVICETYPE__MAJTYPE___S                   0
#define   DBG_TLV_CS_DEVICETYPE___M              0xFFFFFFFF   
#define   DBG_TLV_CS_DEVICETYPE___S                            0

#define DBG_TLV_CS_PERIPHID4                      (0x00BB2FD0)
#define   DBG_TLV_CS_PERIPHID4___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID4___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID4__RFU___POR        0x000000
#define   DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0
#define   DBG_TLV_CS_PERIPHID4__RFU___M          0xFFFFFF00
#define   DBG_TLV_CS_PERIPHID4__RFU___S                        8
#define   DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___S               4
#define   DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___S               0
#define   DBG_TLV_CS_PERIPHID4___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID4___S                             0

#define DBG_TLV_CS_PERIPHID5                      (0x00BB2FD4)
#define   DBG_TLV_CS_PERIPHID5___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID5___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID5__RFU___POR        0x00000000
#define   DBG_TLV_CS_PERIPHID5__RFU___M          0xFFFFFFFF
#define   DBG_TLV_CS_PERIPHID5__RFU___S                        0
#define   DBG_TLV_CS_PERIPHID5___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID5___S                             0

#define DBG_TLV_CS_PERIPHID6                      (0x00BB2FD8)
#define   DBG_TLV_CS_PERIPHID6___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID6___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID6__RFU___POR        0x00000000
#define   DBG_TLV_CS_PERIPHID6__RFU___M          0xFFFFFFFF
#define   DBG_TLV_CS_PERIPHID6__RFU___S                        0
#define   DBG_TLV_CS_PERIPHID6___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID6___S                             0

#define DBG_TLV_CS_PERIPHID7                      (0x00BB2FDC)
#define   DBG_TLV_CS_PERIPHID7___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID7___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID7__RFU___POR        0x00000000
#define   DBG_TLV_CS_PERIPHID7__RFU___M          0xFFFFFFFF
#define   DBG_TLV_CS_PERIPHID7__RFU___S                        0
#define   DBG_TLV_CS_PERIPHID7___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID7___S                             0

#define DBG_TLV_CS_PERIPHID0                      (0x00BB2FE0)
#define   DBG_TLV_CS_PERIPHID0___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID0___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID0__RFU___POR        0x000000
#define   DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___POR 0x0
#define   DBG_TLV_CS_PERIPHID0__RFU___M          0xFFFFFF00
#define   DBG_TLV_CS_PERIPHID0__RFU___S                        8
#define   DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___M  0x000000FF
#define   DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___S                0
#define   DBG_TLV_CS_PERIPHID0___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID0___S                             0

#define DBG_TLV_CS_PERIPHID1                      (0x00BB2FE4)
#define   DBG_TLV_CS_PERIPHID1___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID1___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID1__RFU___POR        0x000000
#define   DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0
#define   DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___POR 0x0
#define   DBG_TLV_CS_PERIPHID1__RFU___M          0xFFFFFF00
#define   DBG_TLV_CS_PERIPHID1__RFU___S                        8
#define   DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0
#define   DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___S               4
#define   DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F
#define   DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___S               0
#define   DBG_TLV_CS_PERIPHID1___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID1___S                             0

#define DBG_TLV_CS_PERIPHID2                      (0x00BB2FE8)
#define   DBG_TLV_CS_PERIPHID2___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID2___POR             0x0000000F
#define   DBG_TLV_CS_PERIPHID2__RFU___POR        0x000000
#define   DBG_TLV_CS_PERIPHID2__PERIPH_REV___POR 0x0
#define   DBG_TLV_CS_PERIPHID2__JEP106_ASS___POR 0x1
#define   DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7
#define   DBG_TLV_CS_PERIPHID2__RFU___M          0xFFFFFF00
#define   DBG_TLV_CS_PERIPHID2__RFU___S                        8
#define   DBG_TLV_CS_PERIPHID2__PERIPH_REV___M   0x000000F0
#define   DBG_TLV_CS_PERIPHID2__PERIPH_REV___S                 4
#define   DBG_TLV_CS_PERIPHID2__JEP106_ASS___M   0x00000008
#define   DBG_TLV_CS_PERIPHID2__JEP106_ASS___S                 3
#define   DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007
#define   DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___S               0
#define   DBG_TLV_CS_PERIPHID2___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID2___S                             0

#define DBG_TLV_CS_PERIPHID3                      (0x00BB2FEC)
#define   DBG_TLV_CS_PERIPHID3___RWC                QCSR_REG_RO    
#define   DBG_TLV_CS_PERIPHID3___POR             0x00000000
#define   DBG_TLV_CS_PERIPHID3__RFU___POR        0x000000
#define   DBG_TLV_CS_PERIPHID3__REV_AND___POR    0x0
#define   DBG_TLV_CS_PERIPHID3__MODIFIED___POR   0x0
#define   DBG_TLV_CS_PERIPHID3__RFU___M          0xFFFFFF00
#define   DBG_TLV_CS_PERIPHID3__RFU___S                        8
#define   DBG_TLV_CS_PERIPHID3__REV_AND___M      0x000000F0
#define   DBG_TLV_CS_PERIPHID3__REV_AND___S                    4
#define   DBG_TLV_CS_PERIPHID3__MODIFIED___M     0x0000000F
#define   DBG_TLV_CS_PERIPHID3__MODIFIED___S                   0
#define   DBG_TLV_CS_PERIPHID3___M               0xFFFFFFFF   
#define   DBG_TLV_CS_PERIPHID3___S                             0

#define DBG_TLV_CS_COMPID0                        (0x00BB2FF0)
#define   DBG_TLV_CS_COMPID0___RWC                  QCSR_REG_RO    
#define   DBG_TLV_CS_COMPID0___POR               0x0000000D
#define   DBG_TLV_CS_COMPID0__RFU___POR          0x000000
#define   DBG_TLV_CS_COMPID0__PREAMBLE_7_0___POR 0x0D
#define   DBG_TLV_CS_COMPID0__RFU___M            0xFFFFFF00
#define   DBG_TLV_CS_COMPID0__RFU___S                          8
#define   DBG_TLV_CS_COMPID0__PREAMBLE_7_0___M   0x000000FF
#define   DBG_TLV_CS_COMPID0__PREAMBLE_7_0___S                 0
#define   DBG_TLV_CS_COMPID0___M                 0xFFFFFFFF   
#define   DBG_TLV_CS_COMPID0___S                               0

#define DBG_TLV_CS_COMPID1                        (0x00BB2FF4)
#define   DBG_TLV_CS_COMPID1___RWC                  QCSR_REG_RO    
#define   DBG_TLV_CS_COMPID1___POR               0x00000090
#define   DBG_TLV_CS_COMPID1__RFU___POR          0x000000
#define   DBG_TLV_CS_COMPID1__PREAMBLE_15_12___POR 0x9
#define   DBG_TLV_CS_COMPID1__PREAMBLE_11_8___POR 0x0
#define   DBG_TLV_CS_COMPID1__RFU___M            0xFFFFFF00
#define   DBG_TLV_CS_COMPID1__RFU___S                          8
#define   DBG_TLV_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_TLV_CS_COMPID1__PREAMBLE_15_12___S               4
#define   DBG_TLV_CS_COMPID1__PREAMBLE_11_8___M  0x0000000F
#define   DBG_TLV_CS_COMPID1__PREAMBLE_11_8___S                0
#define   DBG_TLV_CS_COMPID1___M                 0xFFFFFFFF   
#define   DBG_TLV_CS_COMPID1___S                               0

#define DBG_TLV_CS_COMPID2                        (0x00BB2FF8)
#define   DBG_TLV_CS_COMPID2___RWC                  QCSR_REG_RO    
#define   DBG_TLV_CS_COMPID2___POR               0x00000005
#define   DBG_TLV_CS_COMPID2__RFU___POR          0x000000
#define   DBG_TLV_CS_COMPID2__PREAMBLE_23_16___POR 0x05
#define   DBG_TLV_CS_COMPID2__RFU___M            0xFFFFFF00
#define   DBG_TLV_CS_COMPID2__RFU___S                          8
#define   DBG_TLV_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_TLV_CS_COMPID2__PREAMBLE_23_16___S               0
#define   DBG_TLV_CS_COMPID2___M                 0xFFFFFFFF   
#define   DBG_TLV_CS_COMPID2___S                               0

#define DBG_TLV_CS_COMPID3                        (0x00BB2FFC)
#define   DBG_TLV_CS_COMPID3___RWC                  QCSR_REG_RO    
#define   DBG_TLV_CS_COMPID3___POR               0x000000B1
#define   DBG_TLV_CS_COMPID3__RFU___POR          0x000000
#define   DBG_TLV_CS_COMPID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_TLV_CS_COMPID3__RFU___M            0xFFFFFF00
#define   DBG_TLV_CS_COMPID3__RFU___S                          8
#define   DBG_TLV_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_TLV_CS_COMPID3__PREAMBLE_31_24___S               0
#define   DBG_TLV_CS_COMPID3___M                 0xFFFFFFFF   
#define   DBG_TLV_CS_COMPID3___S                               0

#define DBG_TLVFUN_CTRL_REG                       (0x00BB3000)
#define   DBG_TLVFUN_CTRL_REG___RWC                 QCSR_REG_RW    
#define   DBG_TLVFUN_CTRL_REG___POR              0x00000300
#define   DBG_TLVFUN_CTRL_REG__HT___POR          0x3
#define   DBG_TLVFUN_CTRL_REG__ENS7___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS6___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS5___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS4___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS3___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS2___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS1___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__ENS0___POR        0x0
#define   DBG_TLVFUN_CTRL_REG__HT___M            0x00000F00
#define   DBG_TLVFUN_CTRL_REG__HT___S                          8
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X0                    0x0
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X1                    0x1
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X2                    0x2
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X3                    0x3
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X4                    0x4
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X5                    0x5
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X6                    0x6
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X7                    0x7
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X8                    0x8
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0X9                    0x9
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0XA                    0xA
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0XB                    0xB
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0XC                    0xC
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0XD                    0xD
#define   DBG_TLVFUN_CTRL_REG__HT__HT_0XE                    0xE
#define   DBG_TLVFUN_CTRL_REG__ENS7___M          0x00000080
#define   DBG_TLVFUN_CTRL_REG__ENS7___S                        7
#define   DBG_TLVFUN_CTRL_REG__ENS7__ENS7_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS7__ENS7_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS6___M          0x00000040
#define   DBG_TLVFUN_CTRL_REG__ENS6___S                        6
#define   DBG_TLVFUN_CTRL_REG__ENS6__ENS6_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS6__ENS6_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS5___M          0x00000020
#define   DBG_TLVFUN_CTRL_REG__ENS5___S                        5
#define   DBG_TLVFUN_CTRL_REG__ENS5__ENS5_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS5__ENS5_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS4___M          0x00000010
#define   DBG_TLVFUN_CTRL_REG__ENS4___S                        4
#define   DBG_TLVFUN_CTRL_REG__ENS4__ENS4_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS4__ENS4_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS3___M          0x00000008
#define   DBG_TLVFUN_CTRL_REG__ENS3___S                        3
#define   DBG_TLVFUN_CTRL_REG__ENS3__ENS3_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS3__ENS3_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS2___M          0x00000004
#define   DBG_TLVFUN_CTRL_REG__ENS2___S                        2
#define   DBG_TLVFUN_CTRL_REG__ENS2__ENS2_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS2__ENS2_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS1___M          0x00000002
#define   DBG_TLVFUN_CTRL_REG__ENS1___S                        1
#define   DBG_TLVFUN_CTRL_REG__ENS1__ENS1_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS1__ENS1_1                  0x1
#define   DBG_TLVFUN_CTRL_REG__ENS0___M          0x00000001
#define   DBG_TLVFUN_CTRL_REG__ENS0___S                        0
#define   DBG_TLVFUN_CTRL_REG__ENS0__ENS0_0                  0x0
#define   DBG_TLVFUN_CTRL_REG__ENS0__ENS0_1                  0x1
#define   DBG_TLVFUN_CTRL_REG___M                0x00000FFF   
#define   DBG_TLVFUN_CTRL_REG___S                              0

#define DBG_TLVFUN_PRIORITY_CTRL_REG              (0x00BB3004)
#define   DBG_TLVFUN_PRIORITY_CTRL_REG___RWC        QCSR_REG_RW    
#define   DBG_TLVFUN_PRIORITY_CTRL_REG___POR     0x00000000
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___S              21
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___S              18
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___S              15
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___S              12
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___S               9
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___S               6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_TLVFUN_PRIORITY_CTRL_REG___M       0x00FFFFFF   
#define   DBG_TLVFUN_PRIORITY_CTRL_REG___S                     0

#define DBG_TLVFUN_ITATBDATA0                     (0x00BB3EEC)
#define   DBG_TLVFUN_ITATBDATA0___RWC               QCSR_REG_RW    
#define   DBG_TLVFUN_ITATBDATA0___POR            0x00000000
#define   DBG_TLVFUN_ITATBDATA0__ATDATA31___POR  0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA15___POR  0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA7___POR   0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA0___POR   0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA31___M    0x00000010
#define   DBG_TLVFUN_ITATBDATA0__ATDATA31___S                  4
#define   DBG_TLVFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_TLVFUN_ITATBDATA0__ATDATAM23___M   0x00000008
#define   DBG_TLVFUN_ITATBDATA0__ATDATAM23___S                 3
#define   DBG_TLVFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_TLVFUN_ITATBDATA0__ATDATA15___M    0x00000004
#define   DBG_TLVFUN_ITATBDATA0__ATDATA15___S                  2
#define   DBG_TLVFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_TLVFUN_ITATBDATA0__ATDATA7___M     0x00000002
#define   DBG_TLVFUN_ITATBDATA0__ATDATA7___S                   1
#define   DBG_TLVFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_TLVFUN_ITATBDATA0__ATDATA0___M     0x00000001
#define   DBG_TLVFUN_ITATBDATA0__ATDATA0___S                   0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_TLVFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_TLVFUN_ITATBDATA0___M              0x0000001F   
#define   DBG_TLVFUN_ITATBDATA0___S                            0

#define DBG_TLVFUN_ITATBCTR2                      (0x00BB3EF0)
#define   DBG_TLVFUN_ITATBCTR2___RWC                QCSR_REG_RW    
#define   DBG_TLVFUN_ITATBCTR2___POR             0x00000000
#define   DBG_TLVFUN_ITATBCTR2__AFVALID___POR    0x0
#define   DBG_TLVFUN_ITATBCTR2__ATREADY___POR    0x0
#define   DBG_TLVFUN_ITATBCTR2__AFVALID___M      0x00000002
#define   DBG_TLVFUN_ITATBCTR2__AFVALID___S                    1
#define   DBG_TLVFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_TLVFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_TLVFUN_ITATBCTR2__ATREADY___M      0x00000001
#define   DBG_TLVFUN_ITATBCTR2__ATREADY___S                    0
#define   DBG_TLVFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_TLVFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_TLVFUN_ITATBCTR2___M               0x00000003   
#define   DBG_TLVFUN_ITATBCTR2___S                             0

#define DBG_TLVFUN_ITATBCTR1                      (0x00BB3EF4)
#define   DBG_TLVFUN_ITATBCTR1___RWC                QCSR_REG_RW    
#define   DBG_TLVFUN_ITATBCTR1__ATID___M         0x0000007F
#define   DBG_TLVFUN_ITATBCTR1__ATID___S                       0
#define   DBG_TLVFUN_ITATBCTR1___M               0x0000007F   
#define   DBG_TLVFUN_ITATBCTR1___S                             0

#define DBG_TLVFUN_ITATBCTR0                      (0x00BB3EF8)
#define   DBG_TLVFUN_ITATBCTR0___RWC                QCSR_REG_RW    
#define   DBG_TLVFUN_ITATBCTR0___POR             0x00000000
#define   DBG_TLVFUN_ITATBCTR0__ATBYTES___POR    0x0
#define   DBG_TLVFUN_ITATBCTR0__AFREADY___POR    0x0
#define   DBG_TLVFUN_ITATBCTR0__ATVALID___POR    0x0
#define   DBG_TLVFUN_ITATBCTR0__ATBYTES___M      0x00000300
#define   DBG_TLVFUN_ITATBCTR0__ATBYTES___S                    8
#define   DBG_TLVFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_TLVFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_TLVFUN_ITATBCTR0__AFREADY___M      0x00000002
#define   DBG_TLVFUN_ITATBCTR0__AFREADY___S                    1
#define   DBG_TLVFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_TLVFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_TLVFUN_ITATBCTR0__ATVALID___M      0x00000001
#define   DBG_TLVFUN_ITATBCTR0__ATVALID___S                    0
#define   DBG_TLVFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_TLVFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_TLVFUN_ITATBCTR0___M               0x00000303   
#define   DBG_TLVFUN_ITATBCTR0___S                             0

#define DBG_TLVFUN_ITCTRL                         (0x00BB3F00)
#define   DBG_TLVFUN_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_TLVFUN_ITCTRL___POR                0x00000000
#define   DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_TLVFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_TLVFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_TLVFUN_ITCTRL___M                  0x00000001   
#define   DBG_TLVFUN_ITCTRL___S                                0

#define DBG_TLVFUN_CLAIMSET                       (0x00BB3FA0)
#define   DBG_TLVFUN_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_TLVFUN_CLAIMSET___POR              0x0000000F
#define   DBG_TLVFUN_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_TLVFUN_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_TLVFUN_CLAIMSET__CLAIMSET___S                    0
#define   DBG_TLVFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_TLVFUN_CLAIMSET___M                0x0000000F   
#define   DBG_TLVFUN_CLAIMSET___S                              0

#define DBG_TLVFUN_CLAIMCLR                       (0x00BB3FA4)
#define   DBG_TLVFUN_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_TLVFUN_CLAIMCLR___POR              0x00000000
#define   DBG_TLVFUN_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_TLVFUN_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_TLVFUN_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_TLVFUN_CLAIMCLR___M                0x0000000F   
#define   DBG_TLVFUN_CLAIMCLR___S                              0

#define DBG_TLVFUN_LOCKACCESS                     (0x00BB3FB0)
#define   DBG_TLVFUN_LOCKACCESS___RWC               QCSR_REG_WO    
#define   DBG_TLVFUN_LOCKACCESS__KEY___M         0xFFFFFFFF
#define   DBG_TLVFUN_LOCKACCESS__KEY___S                       0
#define   DBG_TLVFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_TLVFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_TLVFUN_LOCKACCESS___M              0xFFFFFFFF   
#define   DBG_TLVFUN_LOCKACCESS___S                            0

#define DBG_TLVFUN_LOCKSTATUS                     (0x00BB3FB4)
#define   DBG_TLVFUN_LOCKSTATUS___RWC               QCSR_REG_RO    
#define   DBG_TLVFUN_LOCKSTATUS___POR            0x00000003
#define   DBG_TLVFUN_LOCKSTATUS__NTT___POR       0x0
#define   DBG_TLVFUN_LOCKSTATUS__SLK___POR       0x1
#define   DBG_TLVFUN_LOCKSTATUS__SLI___POR       0x1
#define   DBG_TLVFUN_LOCKSTATUS__NTT___M         0x00000004
#define   DBG_TLVFUN_LOCKSTATUS__NTT___S                       2
#define   DBG_TLVFUN_LOCKSTATUS__NTT__NTT_0X0                0x0
#define   DBG_TLVFUN_LOCKSTATUS__SLK___M         0x00000002
#define   DBG_TLVFUN_LOCKSTATUS__SLK___S                       1
#define   DBG_TLVFUN_LOCKSTATUS__SLK__SLK_0X0                0x0
#define   DBG_TLVFUN_LOCKSTATUS__SLK__SLK_0X1                0x1
#define   DBG_TLVFUN_LOCKSTATUS__SLI___M         0x00000001
#define   DBG_TLVFUN_LOCKSTATUS__SLI___S                       0
#define   DBG_TLVFUN_LOCKSTATUS__SLI__SLI_0X0                0x0
#define   DBG_TLVFUN_LOCKSTATUS__SLI__SLI_0X1                0x1
#define   DBG_TLVFUN_LOCKSTATUS___M              0x00000007   
#define   DBG_TLVFUN_LOCKSTATUS___S                            0

#define DBG_TLVFUN_AUTHSTATUS                     (0x00BB3FB8)
#define   DBG_TLVFUN_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_TLVFUN_AUTHSTATUS___POR            0x00000000
#define   DBG_TLVFUN_AUTHSTATUS__SNID___POR      0x0
#define   DBG_TLVFUN_AUTHSTATUS__SID___POR       0x0
#define   DBG_TLVFUN_AUTHSTATUS__NSNID___POR     0x0
#define   DBG_TLVFUN_AUTHSTATUS__NSID___POR      0x0
#define   DBG_TLVFUN_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_TLVFUN_AUTHSTATUS__SNID___S                      6
#define   DBG_TLVFUN_AUTHSTATUS__SNID__SNID_0X0              0x0
#define   DBG_TLVFUN_AUTHSTATUS__SID___M         0x00000030
#define   DBG_TLVFUN_AUTHSTATUS__SID___S                       4
#define   DBG_TLVFUN_AUTHSTATUS__SID__SID_0X0                0x0
#define   DBG_TLVFUN_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_TLVFUN_AUTHSTATUS__NSNID___S                     2
#define   DBG_TLVFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_TLVFUN_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_TLVFUN_AUTHSTATUS__NSID___S                      0
#define   DBG_TLVFUN_AUTHSTATUS__NSID__NSID_0X0              0x0
#define   DBG_TLVFUN_AUTHSTATUS___M              0x000000FF   
#define   DBG_TLVFUN_AUTHSTATUS___S                            0

#define DBG_TLVFUN_DEVID                          (0x00BB3FC8)
#define   DBG_TLVFUN_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_DEVID___POR                 0x00000038
#define   DBG_TLVFUN_DEVID__SCHEME___POR         0x3
#define   DBG_TLVFUN_DEVID__PORTCOUNT___POR      0x8
#define   DBG_TLVFUN_DEVID__SCHEME___M           0x000000F0
#define   DBG_TLVFUN_DEVID__SCHEME___S                         4
#define   DBG_TLVFUN_DEVID__SCHEME__SCHEME_0X3               0x3
#define   DBG_TLVFUN_DEVID__PORTCOUNT___M        0x0000000F
#define   DBG_TLVFUN_DEVID__PORTCOUNT___S                      0
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_TLVFUN_DEVID___M                   0x000000FF   
#define   DBG_TLVFUN_DEVID___S                                 0

#define DBG_TLVFUN_DEVTYPE                        (0x00BB3FCC)
#define   DBG_TLVFUN_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_TLVFUN_DEVTYPE___POR               0x00000012
#define   DBG_TLVFUN_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___POR   0x2
#define   DBG_TLVFUN_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_TLVFUN_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_TLVFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_TLVFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_TLVFUN_DEVTYPE___M                 0x000000FF   
#define   DBG_TLVFUN_DEVTYPE___S                               0

#define DBG_TLVFUN_PIDR0                          (0x00BB3FE0)
#define   DBG_TLVFUN_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_PIDR0___POR                 0x00000008
#define   DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_TLVFUN_PIDR0___M                   0x000000FF   
#define   DBG_TLVFUN_PIDR0___S                                 0

#define DBG_TLVFUN_PIDR1                          (0x00BB3FE4)
#define   DBG_TLVFUN_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_PIDR1___POR                 0x000000B9
#define   DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___M  0x000000F0
#define   DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___S                4
#define   DBG_TLVFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_TLVFUN_PIDR1___M                   0x000000FF   
#define   DBG_TLVFUN_PIDR1___S                                 0

#define DBG_TLVFUN_PIDR2                          (0x00BB3FE8)
#define   DBG_TLVFUN_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_PIDR2___POR                 0x0000003B
#define   DBG_TLVFUN_PIDR2__REVISION___POR       0x3
#define   DBG_TLVFUN_PIDR2__JEDEC___POR          0x1
#define   DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_TLVFUN_PIDR2__REVISION___M         0x000000F0
#define   DBG_TLVFUN_PIDR2__REVISION___S                       4
#define   DBG_TLVFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_TLVFUN_PIDR2__JEDEC___M            0x00000008
#define   DBG_TLVFUN_PIDR2__JEDEC___S                          3
#define   DBG_TLVFUN_PIDR2__JEDEC__JEDEC_0X1                 0x1
#define   DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___M  0x00000007
#define   DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___S                0
#define   DBG_TLVFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_TLVFUN_PIDR2___M                   0x000000FF   
#define   DBG_TLVFUN_PIDR2___S                                 0

#define DBG_TLVFUN_PIDR3                          (0x00BB3FEC)
#define   DBG_TLVFUN_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_PIDR3___POR                 0x00000000
#define   DBG_TLVFUN_PIDR3__REVAND___POR         0x0
#define   DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_TLVFUN_PIDR3__REVAND___M           0x000000F0
#define   DBG_TLVFUN_PIDR3__REVAND___S                         4
#define   DBG_TLVFUN_PIDR3__REVAND__REVAND_0X0               0x0
#define   DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_TLVFUN_PIDR3___M                   0x000000FF   
#define   DBG_TLVFUN_PIDR3___S                                 0

#define DBG_TLVFUN_PIDR4                          (0x00BB3FD0)
#define   DBG_TLVFUN_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_TLVFUN_PIDR4___POR                 0x00000004
#define   DBG_TLVFUN_PIDR4__FOURKB_COUNT___POR   0x0
#define   DBG_TLVFUN_PIDR4__JEP106_CONT___POR    0x4
#define   DBG_TLVFUN_PIDR4__FOURKB_COUNT___M     0x000000F0
#define   DBG_TLVFUN_PIDR4__FOURKB_COUNT___S                   4
#define   DBG_TLVFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_TLVFUN_PIDR4__JEP106_CONT___M      0x0000000F
#define   DBG_TLVFUN_PIDR4__JEP106_CONT___S                    0
#define   DBG_TLVFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_TLVFUN_PIDR4___M                   0x000000FF   
#define   DBG_TLVFUN_PIDR4___S                                 0

#define DBG_TLVFUN_PERIPHID5                      (0x00BB3FD4)
#define   DBG_TLVFUN_PERIPHID5___RWC                QCSR_REG_RO    
#define   DBG_TLVFUN_PERIPHID5___POR             0x00000000
#define   DBG_TLVFUN_PERIPHID5__PERIPHID5___POR  0x00000000
#define   DBG_TLVFUN_PERIPHID5__PERIPHID5___M    0xFFFFFFFF
#define   DBG_TLVFUN_PERIPHID5__PERIPHID5___S                  0
#define   DBG_TLVFUN_PERIPHID5___M               0xFFFFFFFF   
#define   DBG_TLVFUN_PERIPHID5___S                             0

#define DBG_TLVFUN_PERIPHID6                      (0x00BB3FD8)
#define   DBG_TLVFUN_PERIPHID6___RWC                QCSR_REG_RO    
#define   DBG_TLVFUN_PERIPHID6___POR             0x00000000
#define   DBG_TLVFUN_PERIPHID6__PERIPHID6___POR  0x00000000
#define   DBG_TLVFUN_PERIPHID6__PERIPHID6___M    0xFFFFFFFF
#define   DBG_TLVFUN_PERIPHID6__PERIPHID6___S                  0
#define   DBG_TLVFUN_PERIPHID6___M               0xFFFFFFFF   
#define   DBG_TLVFUN_PERIPHID6___S                             0

#define DBG_TLVFUN_PERIPHID7                      (0x00BB3FDC)
#define   DBG_TLVFUN_PERIPHID7___RWC                QCSR_REG_RO    
#define   DBG_TLVFUN_PERIPHID7___POR             0x00000000
#define   DBG_TLVFUN_PERIPHID7__PERIPHID7___POR  0x00000000
#define   DBG_TLVFUN_PERIPHID7__PERIPHID7___M    0xFFFFFFFF
#define   DBG_TLVFUN_PERIPHID7__PERIPHID7___S                  0
#define   DBG_TLVFUN_PERIPHID7___M               0xFFFFFFFF   
#define   DBG_TLVFUN_PERIPHID7___S                             0

#define DBG_TLVFUN_CID0                           (0x00BB3FF0)
#define   DBG_TLVFUN_CID0___RWC                     QCSR_REG_RO    
#define   DBG_TLVFUN_CID0___POR                  0x0000000D
#define   DBG_TLVFUN_CID0__PREAMBLE___POR        0x0D
#define   DBG_TLVFUN_CID0__PREAMBLE___M          0x000000FF
#define   DBG_TLVFUN_CID0__PREAMBLE___S                        0
#define   DBG_TLVFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_TLVFUN_CID0___M                    0x000000FF   
#define   DBG_TLVFUN_CID0___S                                  0

#define DBG_TLVFUN_CID1                           (0x00BB3FF4)
#define   DBG_TLVFUN_CID1___RWC                     QCSR_REG_RO    
#define   DBG_TLVFUN_CID1___POR                  0x00000090
#define   DBG_TLVFUN_CID1__CLASS___POR           0x9
#define   DBG_TLVFUN_CID1__PREAMBLE___POR        0x0
#define   DBG_TLVFUN_CID1__CLASS___M             0x000000F0
#define   DBG_TLVFUN_CID1__CLASS___S                           4
#define   DBG_TLVFUN_CID1__CLASS__CLASS_0X9                  0x9
#define   DBG_TLVFUN_CID1__PREAMBLE___M          0x0000000F
#define   DBG_TLVFUN_CID1__PREAMBLE___S                        0
#define   DBG_TLVFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_TLVFUN_CID1___M                    0x000000FF   
#define   DBG_TLVFUN_CID1___S                                  0

#define DBG_TLVFUN_CID2                           (0x00BB3FF8)
#define   DBG_TLVFUN_CID2___RWC                     QCSR_REG_RO    
#define   DBG_TLVFUN_CID2___POR                  0x00000005
#define   DBG_TLVFUN_CID2__PREAMBLE___POR        0x05
#define   DBG_TLVFUN_CID2__PREAMBLE___M          0x000000FF
#define   DBG_TLVFUN_CID2__PREAMBLE___S                        0
#define   DBG_TLVFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_TLVFUN_CID2___M                    0x000000FF   
#define   DBG_TLVFUN_CID2___S                                  0

#define DBG_TLVFUN_CID3                           (0x00BB3FFC)
#define   DBG_TLVFUN_CID3___RWC                     QCSR_REG_RO    
#define   DBG_TLVFUN_CID3___POR                  0x000000B1
#define   DBG_TLVFUN_CID3__PREAMBLE___POR        0xB1
#define   DBG_TLVFUN_CID3__PREAMBLE___M          0x000000FF
#define   DBG_TLVFUN_CID3__PREAMBLE___S                        0
#define   DBG_TLVFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_TLVFUN_CID3___M                    0x000000FF   
#define   DBG_TLVFUN_CID3___S                                  0

#define DBG_TBUS_MACTBUS_CFG                      (0x00BB4000)
#define   DBG_TBUS_MACTBUS_CFG___RWC                QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_CFG___POR             0x00003BA7
#define   DBG_TBUS_MACTBUS_CFG__LMAC0_EN___POR   0x1
#define   DBG_TBUS_MACTBUS_CFG__UMAC_EN___POR    0x1
#define   DBG_TBUS_MACTBUS_CFG__ATID___POR       0x5D
#define   DBG_TBUS_MACTBUS_CFG__TRANSPORT___POR  0x0
#define   DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___POR 0x0
#define   DBG_TBUS_MACTBUS_CFG__TSTMP_EN___POR   0x1
#define   DBG_TBUS_MACTBUS_CFG__TRCONCHG___POR   0x1
#define   DBG_TBUS_MACTBUS_CFG__ENABLE___POR     0x1
#define   DBG_TBUS_MACTBUS_CFG__LMAC0_EN___M     0x00002000
#define   DBG_TBUS_MACTBUS_CFG__LMAC0_EN___S                  13
#define   DBG_TBUS_MACTBUS_CFG__UMAC_EN___M      0x00001000
#define   DBG_TBUS_MACTBUS_CFG__UMAC_EN___S                   12
#define   DBG_TBUS_MACTBUS_CFG__ATID___M         0x00000FE0
#define   DBG_TBUS_MACTBUS_CFG__ATID___S                       5
#define   DBG_TBUS_MACTBUS_CFG__TRANSPORT___M    0x00000010
#define   DBG_TBUS_MACTBUS_CFG__TRANSPORT___S                  4
#define   DBG_TBUS_MACTBUS_CFG__TRANSPORT__CMB               0x0
#define   DBG_TBUS_MACTBUS_CFG__TRANSPORT__ATB               0x1
#define   DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___M   0x00000008
#define   DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___S                 3
#define   DBG_TBUS_MACTBUS_CFG__TSTMP_EN___M     0x00000004
#define   DBG_TBUS_MACTBUS_CFG__TSTMP_EN___S                   2
#define   DBG_TBUS_MACTBUS_CFG__TRCONCHG___M     0x00000002
#define   DBG_TBUS_MACTBUS_CFG__TRCONCHG___S                   1
#define   DBG_TBUS_MACTBUS_CFG__TRCONCHG__TRACEALL             0x0
#define   DBG_TBUS_MACTBUS_CFG__TRCONCHG__TRACECHG             0x1
#define   DBG_TBUS_MACTBUS_CFG__ENABLE___M       0x00000001
#define   DBG_TBUS_MACTBUS_CFG__ENABLE___S                     0
#define   DBG_TBUS_MACTBUS_CFG___M               0x00003FFF   
#define   DBG_TBUS_MACTBUS_CFG___S                             0

#define DBG_TBUS_MACTBUS_TGU_CFG                  (0x00BB4004)
#define   DBG_TBUS_MACTBUS_TGU_CFG___RWC            QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_TGU_CFG___POR         0x000000F0
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___POR 0x0
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___POR 0xF
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___POR 0x0
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___M 0x00000100
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___S               8
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___M 0x000000F0
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___S               4
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___M  0x0000000F
#define   DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___S                0
#define   DBG_TBUS_MACTBUS_TGU_CFG___M           0x000001FF   
#define   DBG_TBUS_MACTBUS_TGU_CFG___S                         0

#define DBG_TBUS_MACTBUS_MATCH0_DATA              (0x00BB4008)
#define   DBG_TBUS_MACTBUS_MATCH0_DATA___RWC        QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH0_DATA___POR     0x00000000
#define   DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___POR 0x00000000
#define   DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___M 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___S               0
#define   DBG_TBUS_MACTBUS_MATCH0_DATA___M       0xFFFFFFFF   
#define   DBG_TBUS_MACTBUS_MATCH0_DATA___S                     0

#define DBG_TBUS_MACTBUS_MATCH0_DATAH             (0x00BB400C)
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH___RWC       QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH___POR    0x00000000
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___POR 0x000
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___M 0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___S               0
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH___M      0x00000FFF   
#define   DBG_TBUS_MACTBUS_MATCH0_DATAH___S                    0

#define DBG_TBUS_MACTBUS_MATCH0_MASK              (0x00BB4010)
#define   DBG_TBUS_MACTBUS_MATCH0_MASK___RWC        QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH0_MASK___POR     0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___M 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___S               0
#define   DBG_TBUS_MACTBUS_MATCH0_MASK___M       0xFFFFFFFF   
#define   DBG_TBUS_MACTBUS_MATCH0_MASK___S                     0

#define DBG_TBUS_MACTBUS_MATCH0_MASKH             (0x00BB4014)
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH___RWC       QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH___POR    0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___POR 0xFFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___M 0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___S               0
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH___M      0x00000FFF   
#define   DBG_TBUS_MACTBUS_MATCH0_MASKH___S                    0

#define DBG_TBUS_MACTBUS_MATCH1_DATA              (0x00BB4018)
#define   DBG_TBUS_MACTBUS_MATCH1_DATA___RWC        QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH1_DATA___POR     0x00000000
#define   DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___POR 0x00000000
#define   DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___M 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___S               0
#define   DBG_TBUS_MACTBUS_MATCH1_DATA___M       0xFFFFFFFF   
#define   DBG_TBUS_MACTBUS_MATCH1_DATA___S                     0

#define DBG_TBUS_MACTBUS_MATCH1_DATAH             (0x00BB401C)
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH___RWC       QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH___POR    0x00000000
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___POR 0x000
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___M 0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___S               0
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH___M      0x00000FFF   
#define   DBG_TBUS_MACTBUS_MATCH1_DATAH___S                    0

#define DBG_TBUS_MACTBUS_MATCH1_MASK              (0x00BB4020)
#define   DBG_TBUS_MACTBUS_MATCH1_MASK___RWC        QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH1_MASK___POR     0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___POR 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___M 0xFFFFFFFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___S               0
#define   DBG_TBUS_MACTBUS_MATCH1_MASK___M       0xFFFFFFFF   
#define   DBG_TBUS_MACTBUS_MATCH1_MASK___S                     0

#define DBG_TBUS_MACTBUS_MATCH1_MASKH             (0x00BB4024)
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH___RWC       QCSR_REG_RW    
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH___POR    0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___POR 0xFFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___M 0x00000FFF
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___S               0
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH___M      0x00000FFF   
#define   DBG_TBUS_MACTBUS_MATCH1_MASKH___S                    0

#define DBG_TBUS_CS_ITCTL                         (0x00BB4F00)
#define   DBG_TBUS_CS_ITCTL___RWC                   QCSR_REG_RO    
#define   DBG_TBUS_CS_ITCTL___POR                0x00000000
#define   DBG_TBUS_CS_ITCTL__RFU___POR           0x00000000
#define   DBG_TBUS_CS_ITCTL__RFU___M             0xFFFFFFFF
#define   DBG_TBUS_CS_ITCTL__RFU___S                           0
#define   DBG_TBUS_CS_ITCTL___M                  0xFFFFFFFF   
#define   DBG_TBUS_CS_ITCTL___S                                0

#define DBG_TBUS_CS_CLAIMSET                      (0x00BB4FA0)
#define   DBG_TBUS_CS_CLAIMSET___RWC                QCSR_REG_RO    
#define   DBG_TBUS_CS_CLAIMSET___POR             0x00000000
#define   DBG_TBUS_CS_CLAIMSET__RFU___POR        0x00000000
#define   DBG_TBUS_CS_CLAIMSET__RFU___M          0xFFFFFFFF
#define   DBG_TBUS_CS_CLAIMSET__RFU___S                        0
#define   DBG_TBUS_CS_CLAIMSET___M               0xFFFFFFFF   
#define   DBG_TBUS_CS_CLAIMSET___S                             0

#define DBG_TBUS_CS_CLAIMCLR                      (0x00BB4FA4)
#define   DBG_TBUS_CS_CLAIMCLR___RWC                QCSR_REG_RO    
#define   DBG_TBUS_CS_CLAIMCLR___POR             0x00000000
#define   DBG_TBUS_CS_CLAIMCLR__RFU___POR        0x00000000
#define   DBG_TBUS_CS_CLAIMCLR__RFU___M          0xFFFFFFFF
#define   DBG_TBUS_CS_CLAIMCLR__RFU___S                        0
#define   DBG_TBUS_CS_CLAIMCLR___M               0xFFFFFFFF   
#define   DBG_TBUS_CS_CLAIMCLR___S                             0

#define DBG_TBUS_CS_LOCKACCESS                    (0x00BB4FB0)
#define   DBG_TBUS_CS_LOCKACCESS___RWC              QCSR_REG_RO    
#define   DBG_TBUS_CS_LOCKACCESS___POR           0x00000000
#define   DBG_TBUS_CS_LOCKACCESS__RFU___POR      0x00000000
#define   DBG_TBUS_CS_LOCKACCESS__RFU___M        0xFFFFFFFF
#define   DBG_TBUS_CS_LOCKACCESS__RFU___S                      0
#define   DBG_TBUS_CS_LOCKACCESS___M             0xFFFFFFFF   
#define   DBG_TBUS_CS_LOCKACCESS___S                           0

#define DBG_TBUS_CS_LOCKSTATUS                    (0x00BB4FB4)
#define   DBG_TBUS_CS_LOCKSTATUS___RWC              QCSR_REG_RO    
#define   DBG_TBUS_CS_LOCKSTATUS___POR           0x00000000
#define   DBG_TBUS_CS_LOCKSTATUS__RFU___POR      0x00000000
#define   DBG_TBUS_CS_LOCKSTATUS__RFU___M        0xFFFFFFFF
#define   DBG_TBUS_CS_LOCKSTATUS__RFU___S                      0
#define   DBG_TBUS_CS_LOCKSTATUS___M             0xFFFFFFFF   
#define   DBG_TBUS_CS_LOCKSTATUS___S                           0

#define DBG_TBUS_CS_AUTHSTATUS                    (0x00BB4FB8)
#define   DBG_TBUS_CS_AUTHSTATUS___RWC              QCSR_REG_RO    
#define   DBG_TBUS_CS_AUTHSTATUS__SI___M         0x000000C0
#define   DBG_TBUS_CS_AUTHSTATUS__SI___S                       6
#define   DBG_TBUS_CS_AUTHSTATUS__NSI___M        0x00000030
#define   DBG_TBUS_CS_AUTHSTATUS__NSI___S                      4
#define   DBG_TBUS_CS_AUTHSTATUS__SNI___M        0x0000000C
#define   DBG_TBUS_CS_AUTHSTATUS__SNI___S                      2
#define   DBG_TBUS_CS_AUTHSTATUS__NSNI___M       0x00000003
#define   DBG_TBUS_CS_AUTHSTATUS__NSNI___S                     0
#define   DBG_TBUS_CS_AUTHSTATUS___M             0x000000FF   
#define   DBG_TBUS_CS_AUTHSTATUS___S                           0

#define DBG_TBUS_CS_DEVARCH                       (0x00BB4FBC)
#define   DBG_TBUS_CS_DEVARCH___RWC                 QCSR_REG_RO    
#define   DBG_TBUS_CS_DEVARCH___POR              0x0E100000
#define   DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0
#define   DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70
#define   DBG_TBUS_CS_DEVARCH__PRESENT___POR     0x1
#define   DBG_TBUS_CS_DEVARCH__REV___POR         0x0
#define   DBG_TBUS_CS_DEVARCH__ARCHID___POR      0x0000
#define   DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000
#define   DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___S              28
#define   DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000
#define   DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___S              21
#define   DBG_TBUS_CS_DEVARCH__PRESENT___M       0x00100000
#define   DBG_TBUS_CS_DEVARCH__PRESENT___S                    20
#define   DBG_TBUS_CS_DEVARCH__REV___M           0x000F0000
#define   DBG_TBUS_CS_DEVARCH__REV___S                        16
#define   DBG_TBUS_CS_DEVARCH__ARCHID___M        0x0000FFFF
#define   DBG_TBUS_CS_DEVARCH__ARCHID___S                      0
#define   DBG_TBUS_CS_DEVARCH___M                0xFFFFFFFF   
#define   DBG_TBUS_CS_DEVARCH___S                              0

#define DBG_TBUS_CS_DEVICEID                      (0x00BB4FC8)
#define   DBG_TBUS_CS_DEVICEID___RWC                QCSR_REG_RO    
#define   DBG_TBUS_CS_DEVICEID___POR             0x00000000
#define   DBG_TBUS_CS_DEVICEID__RFU___POR        0x000000
#define   DBG_TBUS_CS_DEVICEID__DEVID___POR      0x00
#define   DBG_TBUS_CS_DEVICEID__RFU___M          0xFFFFFF00
#define   DBG_TBUS_CS_DEVICEID__RFU___S                        8
#define   DBG_TBUS_CS_DEVICEID__DEVID___M        0x000000FF
#define   DBG_TBUS_CS_DEVICEID__DEVID___S                      0
#define   DBG_TBUS_CS_DEVICEID___M               0xFFFFFFFF   
#define   DBG_TBUS_CS_DEVICEID___S                             0

#define DBG_TBUS_CS_DEVICETYPE                    (0x00BB4FCC)
#define   DBG_TBUS_CS_DEVICETYPE___RWC              QCSR_REG_RO    
#define   DBG_TBUS_CS_DEVICETYPE___POR           0x00000003
#define   DBG_TBUS_CS_DEVICETYPE__RFU___POR      0x000000
#define   DBG_TBUS_CS_DEVICETYPE__SUBTYPE___POR  0x0
#define   DBG_TBUS_CS_DEVICETYPE__MAJTYPE___POR  0x3
#define   DBG_TBUS_CS_DEVICETYPE__RFU___M        0xFFFFFF00
#define   DBG_TBUS_CS_DEVICETYPE__RFU___S                      8
#define   DBG_TBUS_CS_DEVICETYPE__SUBTYPE___M    0x000000F0
#define   DBG_TBUS_CS_DEVICETYPE__SUBTYPE___S                  4
#define   DBG_TBUS_CS_DEVICETYPE__MAJTYPE___M    0x0000000F
#define   DBG_TBUS_CS_DEVICETYPE__MAJTYPE___S                  0
#define   DBG_TBUS_CS_DEVICETYPE___M             0xFFFFFFFF   
#define   DBG_TBUS_CS_DEVICETYPE___S                           0

#define DBG_TBUS_CS_PERIPHID4                     (0x00BB4FD0)
#define   DBG_TBUS_CS_PERIPHID4___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID4___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID4__RFU___POR       0x000000
#define   DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0
#define   DBG_TBUS_CS_PERIPHID4__RFU___M         0xFFFFFF00
#define   DBG_TBUS_CS_PERIPHID4__RFU___S                       8
#define   DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___S               4
#define   DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___S               0
#define   DBG_TBUS_CS_PERIPHID4___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID4___S                            0

#define DBG_TBUS_CS_PERIPHID5                     (0x00BB4FD4)
#define   DBG_TBUS_CS_PERIPHID5___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID5___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID5__RFU___POR       0x00000000
#define   DBG_TBUS_CS_PERIPHID5__RFU___M         0xFFFFFFFF
#define   DBG_TBUS_CS_PERIPHID5__RFU___S                       0
#define   DBG_TBUS_CS_PERIPHID5___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID5___S                            0

#define DBG_TBUS_CS_PERIPHID6                     (0x00BB4FD8)
#define   DBG_TBUS_CS_PERIPHID6___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID6___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID6__RFU___POR       0x00000000
#define   DBG_TBUS_CS_PERIPHID6__RFU___M         0xFFFFFFFF
#define   DBG_TBUS_CS_PERIPHID6__RFU___S                       0
#define   DBG_TBUS_CS_PERIPHID6___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID6___S                            0

#define DBG_TBUS_CS_PERIPHID7                     (0x00BB4FDC)
#define   DBG_TBUS_CS_PERIPHID7___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID7___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID7__RFU___POR       0x00000000
#define   DBG_TBUS_CS_PERIPHID7__RFU___M         0xFFFFFFFF
#define   DBG_TBUS_CS_PERIPHID7__RFU___S                       0
#define   DBG_TBUS_CS_PERIPHID7___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID7___S                            0

#define DBG_TBUS_CS_PERIPHID0                     (0x00BB4FE0)
#define   DBG_TBUS_CS_PERIPHID0___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID0___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID0__RFU___POR       0x000000
#define   DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___POR 0x0
#define   DBG_TBUS_CS_PERIPHID0__RFU___M         0xFFFFFF00
#define   DBG_TBUS_CS_PERIPHID0__RFU___S                       8
#define   DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF
#define   DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___S               0
#define   DBG_TBUS_CS_PERIPHID0___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID0___S                            0

#define DBG_TBUS_CS_PERIPHID1                     (0x00BB4FE4)
#define   DBG_TBUS_CS_PERIPHID1___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID1___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID1__RFU___POR       0x000000
#define   DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0
#define   DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___POR 0x0
#define   DBG_TBUS_CS_PERIPHID1__RFU___M         0xFFFFFF00
#define   DBG_TBUS_CS_PERIPHID1__RFU___S                       8
#define   DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0
#define   DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___S               4
#define   DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F
#define   DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___S               0
#define   DBG_TBUS_CS_PERIPHID1___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID1___S                            0

#define DBG_TBUS_CS_PERIPHID2                     (0x00BB4FE8)
#define   DBG_TBUS_CS_PERIPHID2___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID2___POR            0x0000000F
#define   DBG_TBUS_CS_PERIPHID2__RFU___POR       0x000000
#define   DBG_TBUS_CS_PERIPHID2__PERIPH_REV___POR 0x0
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ASS___POR 0x1
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7
#define   DBG_TBUS_CS_PERIPHID2__RFU___M         0xFFFFFF00
#define   DBG_TBUS_CS_PERIPHID2__RFU___S                       8
#define   DBG_TBUS_CS_PERIPHID2__PERIPH_REV___M  0x000000F0
#define   DBG_TBUS_CS_PERIPHID2__PERIPH_REV___S                4
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ASS___M  0x00000008
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ASS___S                3
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007
#define   DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___S               0
#define   DBG_TBUS_CS_PERIPHID2___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID2___S                            0

#define DBG_TBUS_CS_PERIPHID3                     (0x00BB4FEC)
#define   DBG_TBUS_CS_PERIPHID3___RWC               QCSR_REG_RO    
#define   DBG_TBUS_CS_PERIPHID3___POR            0x00000000
#define   DBG_TBUS_CS_PERIPHID3__RFU___POR       0x000000
#define   DBG_TBUS_CS_PERIPHID3__REV_AND___POR   0x0
#define   DBG_TBUS_CS_PERIPHID3__MODIFIED___POR  0x0
#define   DBG_TBUS_CS_PERIPHID3__RFU___M         0xFFFFFF00
#define   DBG_TBUS_CS_PERIPHID3__RFU___S                       8
#define   DBG_TBUS_CS_PERIPHID3__REV_AND___M     0x000000F0
#define   DBG_TBUS_CS_PERIPHID3__REV_AND___S                   4
#define   DBG_TBUS_CS_PERIPHID3__MODIFIED___M    0x0000000F
#define   DBG_TBUS_CS_PERIPHID3__MODIFIED___S                  0
#define   DBG_TBUS_CS_PERIPHID3___M              0xFFFFFFFF   
#define   DBG_TBUS_CS_PERIPHID3___S                            0

#define DBG_TBUS_CS_COMPID0                       (0x00BB4FF0)
#define   DBG_TBUS_CS_COMPID0___RWC                 QCSR_REG_RO    
#define   DBG_TBUS_CS_COMPID0___POR              0x0000000D
#define   DBG_TBUS_CS_COMPID0__RFU___POR         0x000000
#define   DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___POR 0x0D
#define   DBG_TBUS_CS_COMPID0__RFU___M           0xFFFFFF00
#define   DBG_TBUS_CS_COMPID0__RFU___S                         8
#define   DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___M  0x000000FF
#define   DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___S                0
#define   DBG_TBUS_CS_COMPID0___M                0xFFFFFFFF   
#define   DBG_TBUS_CS_COMPID0___S                              0

#define DBG_TBUS_CS_COMPID1                       (0x00BB4FF4)
#define   DBG_TBUS_CS_COMPID1___RWC                 QCSR_REG_RO    
#define   DBG_TBUS_CS_COMPID1___POR              0x00000090
#define   DBG_TBUS_CS_COMPID1__RFU___POR         0x000000
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___POR 0x9
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___POR 0x0
#define   DBG_TBUS_CS_COMPID1__RFU___M           0xFFFFFF00
#define   DBG_TBUS_CS_COMPID1__RFU___S                         8
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___S               4
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F
#define   DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___S               0
#define   DBG_TBUS_CS_COMPID1___M                0xFFFFFFFF   
#define   DBG_TBUS_CS_COMPID1___S                              0

#define DBG_TBUS_CS_COMPID2                       (0x00BB4FF8)
#define   DBG_TBUS_CS_COMPID2___RWC                 QCSR_REG_RO    
#define   DBG_TBUS_CS_COMPID2___POR              0x00000005
#define   DBG_TBUS_CS_COMPID2__RFU___POR         0x000000
#define   DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___POR 0x05
#define   DBG_TBUS_CS_COMPID2__RFU___M           0xFFFFFF00
#define   DBG_TBUS_CS_COMPID2__RFU___S                         8
#define   DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___S               0
#define   DBG_TBUS_CS_COMPID2___M                0xFFFFFFFF   
#define   DBG_TBUS_CS_COMPID2___S                              0

#define DBG_TBUS_CS_COMPID3                       (0x00BB4FFC)
#define   DBG_TBUS_CS_COMPID3___RWC                 QCSR_REG_RO    
#define   DBG_TBUS_CS_COMPID3___POR              0x000000B1
#define   DBG_TBUS_CS_COMPID3__RFU___POR         0x000000
#define   DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_TBUS_CS_COMPID3__RFU___M           0xFFFFFF00
#define   DBG_TBUS_CS_COMPID3__RFU___S                         8
#define   DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___S               0
#define   DBG_TBUS_CS_COMPID3___M                0xFFFFFFFF   
#define   DBG_TBUS_CS_COMPID3___S                              0

#define DBG_TBUSFUN_CTRL_REG                      (0x00BB5000)
#define   DBG_TBUSFUN_CTRL_REG___RWC                QCSR_REG_RW    
#define   DBG_TBUSFUN_CTRL_REG___POR             0x00000300
#define   DBG_TBUSFUN_CTRL_REG__HT___POR         0x3
#define   DBG_TBUSFUN_CTRL_REG__ENS7___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS6___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS5___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS4___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS3___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS2___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS1___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS0___POR       0x0
#define   DBG_TBUSFUN_CTRL_REG__HT___M           0x00000F00
#define   DBG_TBUSFUN_CTRL_REG__HT___S                         8
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X0                   0x0
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X1                   0x1
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X2                   0x2
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X3                   0x3
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X4                   0x4
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X5                   0x5
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X6                   0x6
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X7                   0x7
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X8                   0x8
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0X9                   0x9
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0XA                   0xA
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0XB                   0xB
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0XC                   0xC
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0XD                   0xD
#define   DBG_TBUSFUN_CTRL_REG__HT__HT_0XE                   0xE
#define   DBG_TBUSFUN_CTRL_REG__ENS7___M         0x00000080
#define   DBG_TBUSFUN_CTRL_REG__ENS7___S                       7
#define   DBG_TBUSFUN_CTRL_REG__ENS7__ENS7_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS7__ENS7_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS6___M         0x00000040
#define   DBG_TBUSFUN_CTRL_REG__ENS6___S                       6
#define   DBG_TBUSFUN_CTRL_REG__ENS6__ENS6_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS6__ENS6_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS5___M         0x00000020
#define   DBG_TBUSFUN_CTRL_REG__ENS5___S                       5
#define   DBG_TBUSFUN_CTRL_REG__ENS5__ENS5_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS5__ENS5_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS4___M         0x00000010
#define   DBG_TBUSFUN_CTRL_REG__ENS4___S                       4
#define   DBG_TBUSFUN_CTRL_REG__ENS4__ENS4_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS4__ENS4_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS3___M         0x00000008
#define   DBG_TBUSFUN_CTRL_REG__ENS3___S                       3
#define   DBG_TBUSFUN_CTRL_REG__ENS3__ENS3_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS3__ENS3_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS2___M         0x00000004
#define   DBG_TBUSFUN_CTRL_REG__ENS2___S                       2
#define   DBG_TBUSFUN_CTRL_REG__ENS2__ENS2_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS2__ENS2_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS1___M         0x00000002
#define   DBG_TBUSFUN_CTRL_REG__ENS1___S                       1
#define   DBG_TBUSFUN_CTRL_REG__ENS1__ENS1_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS1__ENS1_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG__ENS0___M         0x00000001
#define   DBG_TBUSFUN_CTRL_REG__ENS0___S                       0
#define   DBG_TBUSFUN_CTRL_REG__ENS0__ENS0_0                 0x0
#define   DBG_TBUSFUN_CTRL_REG__ENS0__ENS0_1                 0x1
#define   DBG_TBUSFUN_CTRL_REG___M               0x00000FFF   
#define   DBG_TBUSFUN_CTRL_REG___S                             0

#define DBG_TBUSFUN_PRIORITY_CTRL_REG             (0x00BB5004)
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG___RWC       QCSR_REG_RW    
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG___POR    0x00000000
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___S              21
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___S              18
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___S              15
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___S              12
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___S               9
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___S               6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG___M      0x00FFFFFF   
#define   DBG_TBUSFUN_PRIORITY_CTRL_REG___S                    0

#define DBG_TBUSFUN_ITATBDATA0                    (0x00BB5EEC)
#define   DBG_TBUSFUN_ITATBDATA0___RWC              QCSR_REG_RW    
#define   DBG_TBUSFUN_ITATBDATA0___POR           0x00000000
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA31___POR 0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA15___POR 0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA7___POR  0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA0___POR  0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA31___M   0x00000010
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA31___S                 4
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_TBUSFUN_ITATBDATA0__ATDATAM23___M  0x00000008
#define   DBG_TBUSFUN_ITATBDATA0__ATDATAM23___S                3
#define   DBG_TBUSFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA15___M   0x00000004
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA15___S                 2
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA7___M    0x00000002
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA7___S                  1
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA0___M    0x00000001
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA0___S                  0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_TBUSFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_TBUSFUN_ITATBDATA0___M             0x0000001F   
#define   DBG_TBUSFUN_ITATBDATA0___S                           0

#define DBG_TBUSFUN_ITATBCTR2                     (0x00BB5EF0)
#define   DBG_TBUSFUN_ITATBCTR2___RWC               QCSR_REG_RW    
#define   DBG_TBUSFUN_ITATBCTR2___POR            0x00000000
#define   DBG_TBUSFUN_ITATBCTR2__AFVALID___POR   0x0
#define   DBG_TBUSFUN_ITATBCTR2__ATREADY___POR   0x0
#define   DBG_TBUSFUN_ITATBCTR2__AFVALID___M     0x00000002
#define   DBG_TBUSFUN_ITATBCTR2__AFVALID___S                   1
#define   DBG_TBUSFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_TBUSFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_TBUSFUN_ITATBCTR2__ATREADY___M     0x00000001
#define   DBG_TBUSFUN_ITATBCTR2__ATREADY___S                   0
#define   DBG_TBUSFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_TBUSFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_TBUSFUN_ITATBCTR2___M              0x00000003   
#define   DBG_TBUSFUN_ITATBCTR2___S                            0

#define DBG_TBUSFUN_ITATBCTR1                     (0x00BB5EF4)
#define   DBG_TBUSFUN_ITATBCTR1___RWC               QCSR_REG_RW    
#define   DBG_TBUSFUN_ITATBCTR1__ATID___M        0x0000007F
#define   DBG_TBUSFUN_ITATBCTR1__ATID___S                      0
#define   DBG_TBUSFUN_ITATBCTR1___M              0x0000007F   
#define   DBG_TBUSFUN_ITATBCTR1___S                            0

#define DBG_TBUSFUN_ITATBCTR0                     (0x00BB5EF8)
#define   DBG_TBUSFUN_ITATBCTR0___RWC               QCSR_REG_RW    
#define   DBG_TBUSFUN_ITATBCTR0___POR            0x00000000
#define   DBG_TBUSFUN_ITATBCTR0__ATBYTES___POR   0x0
#define   DBG_TBUSFUN_ITATBCTR0__AFREADY___POR   0x0
#define   DBG_TBUSFUN_ITATBCTR0__ATVALID___POR   0x0
#define   DBG_TBUSFUN_ITATBCTR0__ATBYTES___M     0x00000300
#define   DBG_TBUSFUN_ITATBCTR0__ATBYTES___S                   8
#define   DBG_TBUSFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_TBUSFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_TBUSFUN_ITATBCTR0__AFREADY___M     0x00000002
#define   DBG_TBUSFUN_ITATBCTR0__AFREADY___S                   1
#define   DBG_TBUSFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_TBUSFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_TBUSFUN_ITATBCTR0__ATVALID___M     0x00000001
#define   DBG_TBUSFUN_ITATBCTR0__ATVALID___S                   0
#define   DBG_TBUSFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_TBUSFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_TBUSFUN_ITATBCTR0___M              0x00000303   
#define   DBG_TBUSFUN_ITATBCTR0___S                            0

#define DBG_TBUSFUN_ITCTRL                        (0x00BB5F00)
#define   DBG_TBUSFUN_ITCTRL___RWC                  QCSR_REG_RW    
#define   DBG_TBUSFUN_ITCTRL___POR               0x00000000
#define   DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_TBUSFUN_ITCTRL___M                 0x00000001   
#define   DBG_TBUSFUN_ITCTRL___S                               0

#define DBG_TBUSFUN_CLAIMSET                      (0x00BB5FA0)
#define   DBG_TBUSFUN_CLAIMSET___RWC                QCSR_REG_RW    
#define   DBG_TBUSFUN_CLAIMSET___POR             0x0000000F
#define   DBG_TBUSFUN_CLAIMSET__CLAIMSET___POR   0xF
#define   DBG_TBUSFUN_CLAIMSET__CLAIMSET___M     0x0000000F
#define   DBG_TBUSFUN_CLAIMSET__CLAIMSET___S                   0
#define   DBG_TBUSFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_TBUSFUN_CLAIMSET___M               0x0000000F   
#define   DBG_TBUSFUN_CLAIMSET___S                             0

#define DBG_TBUSFUN_CLAIMCLR                      (0x00BB5FA4)
#define   DBG_TBUSFUN_CLAIMCLR___RWC                QCSR_REG_RW    
#define   DBG_TBUSFUN_CLAIMCLR___POR             0x00000000
#define   DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___POR   0x0
#define   DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___M     0x0000000F
#define   DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___S                   0
#define   DBG_TBUSFUN_CLAIMCLR___M               0x0000000F   
#define   DBG_TBUSFUN_CLAIMCLR___S                             0

#define DBG_TBUSFUN_LOCKACCESS                    (0x00BB5FB0)
#define   DBG_TBUSFUN_LOCKACCESS___RWC              QCSR_REG_WO    
#define   DBG_TBUSFUN_LOCKACCESS__KEY___M        0xFFFFFFFF
#define   DBG_TBUSFUN_LOCKACCESS__KEY___S                      0
#define   DBG_TBUSFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_TBUSFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_TBUSFUN_LOCKACCESS___M             0xFFFFFFFF   
#define   DBG_TBUSFUN_LOCKACCESS___S                           0

#define DBG_TBUSFUN_LOCKSTATUS                    (0x00BB5FB4)
#define   DBG_TBUSFUN_LOCKSTATUS___RWC              QCSR_REG_RO    
#define   DBG_TBUSFUN_LOCKSTATUS___POR           0x00000003
#define   DBG_TBUSFUN_LOCKSTATUS__NTT___POR      0x0
#define   DBG_TBUSFUN_LOCKSTATUS__SLK___POR      0x1
#define   DBG_TBUSFUN_LOCKSTATUS__SLI___POR      0x1
#define   DBG_TBUSFUN_LOCKSTATUS__NTT___M        0x00000004
#define   DBG_TBUSFUN_LOCKSTATUS__NTT___S                      2
#define   DBG_TBUSFUN_LOCKSTATUS__NTT__NTT_0X0               0x0
#define   DBG_TBUSFUN_LOCKSTATUS__SLK___M        0x00000002
#define   DBG_TBUSFUN_LOCKSTATUS__SLK___S                      1
#define   DBG_TBUSFUN_LOCKSTATUS__SLK__SLK_0X0               0x0
#define   DBG_TBUSFUN_LOCKSTATUS__SLK__SLK_0X1               0x1
#define   DBG_TBUSFUN_LOCKSTATUS__SLI___M        0x00000001
#define   DBG_TBUSFUN_LOCKSTATUS__SLI___S                      0
#define   DBG_TBUSFUN_LOCKSTATUS__SLI__SLI_0X0               0x0
#define   DBG_TBUSFUN_LOCKSTATUS__SLI__SLI_0X1               0x1
#define   DBG_TBUSFUN_LOCKSTATUS___M             0x00000007   
#define   DBG_TBUSFUN_LOCKSTATUS___S                           0

#define DBG_TBUSFUN_AUTHSTATUS                    (0x00BB5FB8)
#define   DBG_TBUSFUN_AUTHSTATUS___RWC              QCSR_REG_RO    
#define   DBG_TBUSFUN_AUTHSTATUS___POR           0x00000000
#define   DBG_TBUSFUN_AUTHSTATUS__SNID___POR     0x0
#define   DBG_TBUSFUN_AUTHSTATUS__SID___POR      0x0
#define   DBG_TBUSFUN_AUTHSTATUS__NSNID___POR    0x0
#define   DBG_TBUSFUN_AUTHSTATUS__NSID___POR     0x0
#define   DBG_TBUSFUN_AUTHSTATUS__SNID___M       0x000000C0
#define   DBG_TBUSFUN_AUTHSTATUS__SNID___S                     6
#define   DBG_TBUSFUN_AUTHSTATUS__SNID__SNID_0X0             0x0
#define   DBG_TBUSFUN_AUTHSTATUS__SID___M        0x00000030
#define   DBG_TBUSFUN_AUTHSTATUS__SID___S                      4
#define   DBG_TBUSFUN_AUTHSTATUS__SID__SID_0X0               0x0
#define   DBG_TBUSFUN_AUTHSTATUS__NSNID___M      0x0000000C
#define   DBG_TBUSFUN_AUTHSTATUS__NSNID___S                    2
#define   DBG_TBUSFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_TBUSFUN_AUTHSTATUS__NSID___M       0x00000003
#define   DBG_TBUSFUN_AUTHSTATUS__NSID___S                     0
#define   DBG_TBUSFUN_AUTHSTATUS__NSID__NSID_0X0             0x0
#define   DBG_TBUSFUN_AUTHSTATUS___M             0x000000FF   
#define   DBG_TBUSFUN_AUTHSTATUS___S                           0

#define DBG_TBUSFUN_DEVID                         (0x00BB5FC8)
#define   DBG_TBUSFUN_DEVID___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_DEVID___POR                0x00000038
#define   DBG_TBUSFUN_DEVID__SCHEME___POR        0x3
#define   DBG_TBUSFUN_DEVID__PORTCOUNT___POR     0x8
#define   DBG_TBUSFUN_DEVID__SCHEME___M          0x000000F0
#define   DBG_TBUSFUN_DEVID__SCHEME___S                        4
#define   DBG_TBUSFUN_DEVID__SCHEME__SCHEME_0X3              0x3
#define   DBG_TBUSFUN_DEVID__PORTCOUNT___M       0x0000000F
#define   DBG_TBUSFUN_DEVID__PORTCOUNT___S                     0
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_TBUSFUN_DEVID___M                  0x000000FF   
#define   DBG_TBUSFUN_DEVID___S                                0

#define DBG_TBUSFUN_DEVTYPE                       (0x00BB5FCC)
#define   DBG_TBUSFUN_DEVTYPE___RWC                 QCSR_REG_RO    
#define   DBG_TBUSFUN_DEVTYPE___POR              0x00000012
#define   DBG_TBUSFUN_DEVTYPE__SUB_TYPE___POR    0x1
#define   DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___POR  0x2
#define   DBG_TBUSFUN_DEVTYPE__SUB_TYPE___M      0x000000F0
#define   DBG_TBUSFUN_DEVTYPE__SUB_TYPE___S                    4
#define   DBG_TBUSFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___M    0x0000000F
#define   DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___S                  0
#define   DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_TBUSFUN_DEVTYPE___M                0x000000FF   
#define   DBG_TBUSFUN_DEVTYPE___S                              0

#define DBG_TBUSFUN_PIDR0                         (0x00BB5FE0)
#define   DBG_TBUSFUN_PIDR0___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_PIDR0___POR                0x00000008
#define   DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_TBUSFUN_PIDR0___M                  0x000000FF   
#define   DBG_TBUSFUN_PIDR0___S                                0

#define DBG_TBUSFUN_PIDR1                         (0x00BB5FE4)
#define   DBG_TBUSFUN_PIDR1___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_PIDR1___POR                0x000000B9
#define   DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0
#define   DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___S               4
#define   DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_TBUSFUN_PIDR1___M                  0x000000FF   
#define   DBG_TBUSFUN_PIDR1___S                                0

#define DBG_TBUSFUN_PIDR2                         (0x00BB5FE8)
#define   DBG_TBUSFUN_PIDR2___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_PIDR2___POR                0x0000003B
#define   DBG_TBUSFUN_PIDR2__REVISION___POR      0x3
#define   DBG_TBUSFUN_PIDR2__JEDEC___POR         0x1
#define   DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_TBUSFUN_PIDR2__REVISION___M        0x000000F0
#define   DBG_TBUSFUN_PIDR2__REVISION___S                      4
#define   DBG_TBUSFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_TBUSFUN_PIDR2__JEDEC___M           0x00000008
#define   DBG_TBUSFUN_PIDR2__JEDEC___S                         3
#define   DBG_TBUSFUN_PIDR2__JEDEC__JEDEC_0X1                0x1
#define   DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007
#define   DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___S               0
#define   DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_TBUSFUN_PIDR2___M                  0x000000FF   
#define   DBG_TBUSFUN_PIDR2___S                                0

#define DBG_TBUSFUN_PIDR3                         (0x00BB5FEC)
#define   DBG_TBUSFUN_PIDR3___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_PIDR3___POR                0x00000000
#define   DBG_TBUSFUN_PIDR3__REVAND___POR        0x0
#define   DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_TBUSFUN_PIDR3__REVAND___M          0x000000F0
#define   DBG_TBUSFUN_PIDR3__REVAND___S                        4
#define   DBG_TBUSFUN_PIDR3__REVAND__REVAND_0X0              0x0
#define   DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_TBUSFUN_PIDR3___M                  0x000000FF   
#define   DBG_TBUSFUN_PIDR3___S                                0

#define DBG_TBUSFUN_PIDR4                         (0x00BB5FD0)
#define   DBG_TBUSFUN_PIDR4___RWC                   QCSR_REG_RO    
#define   DBG_TBUSFUN_PIDR4___POR                0x00000004
#define   DBG_TBUSFUN_PIDR4__FOURKB_COUNT___POR  0x0
#define   DBG_TBUSFUN_PIDR4__JEP106_CONT___POR   0x4
#define   DBG_TBUSFUN_PIDR4__FOURKB_COUNT___M    0x000000F0
#define   DBG_TBUSFUN_PIDR4__FOURKB_COUNT___S                  4
#define   DBG_TBUSFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_TBUSFUN_PIDR4__JEP106_CONT___M     0x0000000F
#define   DBG_TBUSFUN_PIDR4__JEP106_CONT___S                   0
#define   DBG_TBUSFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_TBUSFUN_PIDR4___M                  0x000000FF   
#define   DBG_TBUSFUN_PIDR4___S                                0

#define DBG_TBUSFUN_PERIPHID5                     (0x00BB5FD4)
#define   DBG_TBUSFUN_PERIPHID5___RWC               QCSR_REG_RO    
#define   DBG_TBUSFUN_PERIPHID5___POR            0x00000000
#define   DBG_TBUSFUN_PERIPHID5__PERIPHID5___POR 0x00000000
#define   DBG_TBUSFUN_PERIPHID5__PERIPHID5___M   0xFFFFFFFF
#define   DBG_TBUSFUN_PERIPHID5__PERIPHID5___S                 0
#define   DBG_TBUSFUN_PERIPHID5___M              0xFFFFFFFF   
#define   DBG_TBUSFUN_PERIPHID5___S                            0

#define DBG_TBUSFUN_PERIPHID6                     (0x00BB5FD8)
#define   DBG_TBUSFUN_PERIPHID6___RWC               QCSR_REG_RO    
#define   DBG_TBUSFUN_PERIPHID6___POR            0x00000000
#define   DBG_TBUSFUN_PERIPHID6__PERIPHID6___POR 0x00000000
#define   DBG_TBUSFUN_PERIPHID6__PERIPHID6___M   0xFFFFFFFF
#define   DBG_TBUSFUN_PERIPHID6__PERIPHID6___S                 0
#define   DBG_TBUSFUN_PERIPHID6___M              0xFFFFFFFF   
#define   DBG_TBUSFUN_PERIPHID6___S                            0

#define DBG_TBUSFUN_PERIPHID7                     (0x00BB5FDC)
#define   DBG_TBUSFUN_PERIPHID7___RWC               QCSR_REG_RO    
#define   DBG_TBUSFUN_PERIPHID7___POR            0x00000000
#define   DBG_TBUSFUN_PERIPHID7__PERIPHID7___POR 0x00000000
#define   DBG_TBUSFUN_PERIPHID7__PERIPHID7___M   0xFFFFFFFF
#define   DBG_TBUSFUN_PERIPHID7__PERIPHID7___S                 0
#define   DBG_TBUSFUN_PERIPHID7___M              0xFFFFFFFF   
#define   DBG_TBUSFUN_PERIPHID7___S                            0

#define DBG_TBUSFUN_CID0                          (0x00BB5FF0)
#define   DBG_TBUSFUN_CID0___RWC                    QCSR_REG_RO    
#define   DBG_TBUSFUN_CID0___POR                 0x0000000D
#define   DBG_TBUSFUN_CID0__PREAMBLE___POR       0x0D
#define   DBG_TBUSFUN_CID0__PREAMBLE___M         0x000000FF
#define   DBG_TBUSFUN_CID0__PREAMBLE___S                       0
#define   DBG_TBUSFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_TBUSFUN_CID0___M                   0x000000FF   
#define   DBG_TBUSFUN_CID0___S                                 0

#define DBG_TBUSFUN_CID1                          (0x00BB5FF4)
#define   DBG_TBUSFUN_CID1___RWC                    QCSR_REG_RO    
#define   DBG_TBUSFUN_CID1___POR                 0x00000090
#define   DBG_TBUSFUN_CID1__CLASS___POR          0x9
#define   DBG_TBUSFUN_CID1__PREAMBLE___POR       0x0
#define   DBG_TBUSFUN_CID1__CLASS___M            0x000000F0
#define   DBG_TBUSFUN_CID1__CLASS___S                          4
#define   DBG_TBUSFUN_CID1__CLASS__CLASS_0X9                 0x9
#define   DBG_TBUSFUN_CID1__PREAMBLE___M         0x0000000F
#define   DBG_TBUSFUN_CID1__PREAMBLE___S                       0
#define   DBG_TBUSFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_TBUSFUN_CID1___M                   0x000000FF   
#define   DBG_TBUSFUN_CID1___S                                 0

#define DBG_TBUSFUN_CID2                          (0x00BB5FF8)
#define   DBG_TBUSFUN_CID2___RWC                    QCSR_REG_RO    
#define   DBG_TBUSFUN_CID2___POR                 0x00000005
#define   DBG_TBUSFUN_CID2__PREAMBLE___POR       0x05
#define   DBG_TBUSFUN_CID2__PREAMBLE___M         0x000000FF
#define   DBG_TBUSFUN_CID2__PREAMBLE___S                       0
#define   DBG_TBUSFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_TBUSFUN_CID2___M                   0x000000FF   
#define   DBG_TBUSFUN_CID2___S                                 0

#define DBG_TBUSFUN_CID3                          (0x00BB5FFC)
#define   DBG_TBUSFUN_CID3___RWC                    QCSR_REG_RO    
#define   DBG_TBUSFUN_CID3___POR                 0x000000B1
#define   DBG_TBUSFUN_CID3__PREAMBLE___POR       0xB1
#define   DBG_TBUSFUN_CID3__PREAMBLE___M         0x000000FF
#define   DBG_TBUSFUN_CID3__PREAMBLE___S                       0
#define   DBG_TBUSFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_TBUSFUN_CID3___M                   0x000000FF   
#define   DBG_TBUSFUN_CID3___S                                 0

#define DBG_CTIMAC_CTICONTROL                     (0x00BB6000)
#define   DBG_CTIMAC_CTICONTROL___RWC               QCSR_REG_RW    
#define   DBG_CTIMAC_CTICONTROL___POR            0x00000000
#define   DBG_CTIMAC_CTICONTROL__GLBEN___POR     0x0
#define   DBG_CTIMAC_CTICONTROL__GLBEN___M       0x00000001
#define   DBG_CTIMAC_CTICONTROL__GLBEN___S                     0
#define   DBG_CTIMAC_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_CTIMAC_CTICONTROL__GLBEN__ENABLED              0x1
#define   DBG_CTIMAC_CTICONTROL___M              0x00000001   
#define   DBG_CTIMAC_CTICONTROL___S                            0

#define DBG_CTIMAC_CTIINTACK                      (0x00BB6010)
#define   DBG_CTIMAC_CTIINTACK___RWC                QCSR_REG_WO    
#define   DBG_CTIMAC_CTIINTACK___POR             0x00000000
#define   DBG_CTIMAC_CTIINTACK__INTACK___POR     0x000
#define   DBG_CTIMAC_CTIINTACK__INTACK___M       0x00000FFF
#define   DBG_CTIMAC_CTIINTACK__INTACK___S                     0
#define   DBG_CTIMAC_CTIINTACK___M               0x00000FFF   
#define   DBG_CTIMAC_CTIINTACK___S                             0

#define DBG_CTIMAC_CTIAPPSET                      (0x00BB6014)
#define   DBG_CTIMAC_CTIAPPSET___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIAPPSET___POR             0x00000000
#define   DBG_CTIMAC_CTIAPPSET__APPSET___POR     0x00
#define   DBG_CTIMAC_CTIAPPSET__APPSET___M       0x000000FF
#define   DBG_CTIMAC_CTIAPPSET__APPSET___S                     0
#define   DBG_CTIMAC_CTIAPPSET___M               0x000000FF   
#define   DBG_CTIMAC_CTIAPPSET___S                             0

#define DBG_CTIMAC_CTIAPPCLEAR                    (0x00BB6018)
#define   DBG_CTIMAC_CTIAPPCLEAR___RWC              QCSR_REG_WO    
#define   DBG_CTIMAC_CTIAPPCLEAR___POR           0x00000000
#define   DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___M   0x000000FF
#define   DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___S                 0
#define   DBG_CTIMAC_CTIAPPCLEAR___M             0x000000FF   
#define   DBG_CTIMAC_CTIAPPCLEAR___S                           0

#define DBG_CTIMAC_CTIAPPPULSE                    (0x00BB601C)
#define   DBG_CTIMAC_CTIAPPPULSE___RWC              QCSR_REG_WO    
#define   DBG_CTIMAC_CTIAPPPULSE___POR           0x00000000
#define   DBG_CTIMAC_CTIAPPPULSE__APPULSE___POR  0x00
#define   DBG_CTIMAC_CTIAPPPULSE__APPULSE___M    0x000000FF
#define   DBG_CTIMAC_CTIAPPPULSE__APPULSE___S                  0
#define   DBG_CTIMAC_CTIAPPPULSE___M             0x000000FF   
#define   DBG_CTIMAC_CTIAPPPULSE___S                           0

#define DBG_CTIMAC_CTIINEN0                       (0x00BB6020)
#define   DBG_CTIMAC_CTIINEN0___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN0___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN0__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN0__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN0__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN0___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN0___S                              0

#define DBG_CTIMAC_CTIINEN1                       (0x00BB6024)
#define   DBG_CTIMAC_CTIINEN1___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN1___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN1__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN1__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN1__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN1___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN1___S                              0

#define DBG_CTIMAC_CTIINEN2                       (0x00BB6028)
#define   DBG_CTIMAC_CTIINEN2___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN2___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN2__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN2__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN2__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN2___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN2___S                              0

#define DBG_CTIMAC_CTIINEN3                       (0x00BB602C)
#define   DBG_CTIMAC_CTIINEN3___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN3___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN3__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN3__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN3__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN3___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN3___S                              0

#define DBG_CTIMAC_CTIINEN4                       (0x00BB6030)
#define   DBG_CTIMAC_CTIINEN4___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN4___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN4__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN4__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN4__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN4___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN4___S                              0

#define DBG_CTIMAC_CTIINEN5                       (0x00BB6034)
#define   DBG_CTIMAC_CTIINEN5___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN5___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN5__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN5__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN5__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN5___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN5___S                              0

#define DBG_CTIMAC_CTIINEN6                       (0x00BB6038)
#define   DBG_CTIMAC_CTIINEN6___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN6___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN6__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN6__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN6__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN6___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN6___S                              0

#define DBG_CTIMAC_CTIINEN7                       (0x00BB603C)
#define   DBG_CTIMAC_CTIINEN7___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN7___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN7__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN7__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN7__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN7___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN7___S                              0

#define DBG_CTIMAC_CTIINEN8                       (0x00BB6040)
#define   DBG_CTIMAC_CTIINEN8___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN8___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN8__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN8__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN8__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN8___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN8___S                              0

#define DBG_CTIMAC_CTIINEN9                       (0x00BB6044)
#define   DBG_CTIMAC_CTIINEN9___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN9___POR              0x00000000
#define   DBG_CTIMAC_CTIINEN9__TRIGINEN___POR    0x00
#define   DBG_CTIMAC_CTIINEN9__TRIGINEN___M      0x000000FF
#define   DBG_CTIMAC_CTIINEN9__TRIGINEN___S                    0
#define   DBG_CTIMAC_CTIINEN9___M                0x000000FF   
#define   DBG_CTIMAC_CTIINEN9___S                              0

#define DBG_CTIMAC_CTIINEN10                      (0x00BB6048)
#define   DBG_CTIMAC_CTIINEN10___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN10___POR             0x00000000
#define   DBG_CTIMAC_CTIINEN10__TRIGINEN___POR   0x00
#define   DBG_CTIMAC_CTIINEN10__TRIGINEN___M     0x000000FF
#define   DBG_CTIMAC_CTIINEN10__TRIGINEN___S                   0
#define   DBG_CTIMAC_CTIINEN10___M               0x000000FF   
#define   DBG_CTIMAC_CTIINEN10___S                             0

#define DBG_CTIMAC_CTIINEN11                      (0x00BB604C)
#define   DBG_CTIMAC_CTIINEN11___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIINEN11___POR             0x00000000
#define   DBG_CTIMAC_CTIINEN11__TRIGINEN___POR   0x00
#define   DBG_CTIMAC_CTIINEN11__TRIGINEN___M     0x000000FF
#define   DBG_CTIMAC_CTIINEN11__TRIGINEN___S                   0
#define   DBG_CTIMAC_CTIINEN11___M               0x000000FF   
#define   DBG_CTIMAC_CTIINEN11___S                             0

#define DBG_CTIMAC_CTIOUTEN0                      (0x00BB60A0)
#define   DBG_CTIMAC_CTIOUTEN0___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN0___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN0___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN0___S                             0

#define DBG_CTIMAC_CTIOUTEN1                      (0x00BB60A4)
#define   DBG_CTIMAC_CTIOUTEN1___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN1___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN1___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN1___S                             0

#define DBG_CTIMAC_CTIOUTEN2                      (0x00BB60A8)
#define   DBG_CTIMAC_CTIOUTEN2___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN2___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN2___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN2___S                             0

#define DBG_CTIMAC_CTIOUTEN3                      (0x00BB60AC)
#define   DBG_CTIMAC_CTIOUTEN3___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN3___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN3___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN3___S                             0

#define DBG_CTIMAC_CTIOUTEN4                      (0x00BB60B0)
#define   DBG_CTIMAC_CTIOUTEN4___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN4___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN4___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN4___S                             0

#define DBG_CTIMAC_CTIOUTEN5                      (0x00BB60B4)
#define   DBG_CTIMAC_CTIOUTEN5___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN5___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN5___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN5___S                             0

#define DBG_CTIMAC_CTIOUTEN6                      (0x00BB60B8)
#define   DBG_CTIMAC_CTIOUTEN6___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN6___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN6___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN6___S                             0

#define DBG_CTIMAC_CTIOUTEN7                      (0x00BB60BC)
#define   DBG_CTIMAC_CTIOUTEN7___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN7___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN7___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN7___S                             0

#define DBG_CTIMAC_CTIOUTEN8                      (0x00BB60C0)
#define   DBG_CTIMAC_CTIOUTEN8___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN8___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN8___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN8___S                             0

#define DBG_CTIMAC_CTIOUTEN9                      (0x00BB60C4)
#define   DBG_CTIMAC_CTIOUTEN9___RWC                QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN9___POR             0x00000000
#define   DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___POR  0x00
#define   DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___M    0x000000FF
#define   DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___S                  0
#define   DBG_CTIMAC_CTIOUTEN9___M               0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN9___S                             0

#define DBG_CTIMAC_CTIOUTEN10                     (0x00BB60C8)
#define   DBG_CTIMAC_CTIOUTEN10___RWC               QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN10___POR            0x00000000
#define   DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___POR 0x00
#define   DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___S                 0
#define   DBG_CTIMAC_CTIOUTEN10___M              0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN10___S                            0

#define DBG_CTIMAC_CTIOUTEN11                     (0x00BB60CC)
#define   DBG_CTIMAC_CTIOUTEN11___RWC               QCSR_REG_RW    
#define   DBG_CTIMAC_CTIOUTEN11___POR            0x00000000
#define   DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___POR 0x00
#define   DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___M   0x000000FF
#define   DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___S                 0
#define   DBG_CTIMAC_CTIOUTEN11___M              0x000000FF   
#define   DBG_CTIMAC_CTIOUTEN11___S                            0

#define DBG_CTIMAC_CTITRIGINSTATUS                (0x00BB6130)
#define   DBG_CTIMAC_CTITRIGINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_CTIMAC_CTITRIGINSTATUS__TRIGINSTATUS___M 0x00000FFF
#define   DBG_CTIMAC_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_CTIMAC_CTITRIGINSTATUS___M         0x00000FFF   
#define   DBG_CTIMAC_CTITRIGINSTATUS___S                       0

#define DBG_CTIMAC_CTITRIGOUTSTATUS               (0x00BB6134)
#define   DBG_CTIMAC_CTITRIGOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_CTIMAC_CTITRIGOUTSTATUS___POR      0x00000000
#define   DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x000
#define   DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x00000FFF
#define   DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_CTIMAC_CTITRIGOUTSTATUS___M        0x00000FFF   
#define   DBG_CTIMAC_CTITRIGOUTSTATUS___S                      0

#define DBG_CTIMAC_CTICHINSTATUS                  (0x00BB6138)
#define   DBG_CTIMAC_CTICHINSTATUS___RWC            QCSR_REG_RO    
#define   DBG_CTIMAC_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_CTIMAC_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_CTIMAC_CTICHINSTATUS___M           0x000000FF   
#define   DBG_CTIMAC_CTICHINSTATUS___S                         0

#define DBG_CTIMAC_CTICHOUTSTATUS                 (0x00BB613C)
#define   DBG_CTIMAC_CTICHOUTSTATUS___RWC           QCSR_REG_RO    
#define   DBG_CTIMAC_CTICHOUTSTATUS___POR        0x00000000
#define   DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_CTIMAC_CTICHOUTSTATUS___M          0x000000FF   
#define   DBG_CTIMAC_CTICHOUTSTATUS___S                        0

#define DBG_CTIMAC_CTIGATE                        (0x00BB6140)
#define   DBG_CTIMAC_CTIGATE___RWC                  QCSR_REG_RW    
#define   DBG_CTIMAC_CTIGATE___POR               0x000000FF
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN7___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN6___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN5___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN4___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN3___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN2___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN1___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN0___POR   0x1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN7___M     0x00000080
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN7___S                   7
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN6___M     0x00000040
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN6___S                   6
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN5___M     0x00000020
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN5___S                   5
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN4___M     0x00000010
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN4___S                   4
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN3___M     0x00000008
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN3___S                   3
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN2___M     0x00000004
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN2___S                   2
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN1___M     0x00000002
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN1___S                   1
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN0___M     0x00000001
#define   DBG_CTIMAC_CTIGATE__CTIGATEEN0___S                   0
#define   DBG_CTIMAC_CTIGATE___M                 0x000000FF   
#define   DBG_CTIMAC_CTIGATE___S                               0

#define DBG_CTIMAC_ASICCTL                        (0x00BB6144)
#define   DBG_CTIMAC_ASICCTL___RWC                  QCSR_REG_RW    
#define   DBG_CTIMAC_ASICCTL___POR               0x00000000
#define   DBG_CTIMAC_ASICCTL__ASICCTL___POR      0x00000000
#define   DBG_CTIMAC_ASICCTL__ASICCTL___M        0xFFFFFFFF
#define   DBG_CTIMAC_ASICCTL__ASICCTL___S                      0
#define   DBG_CTIMAC_ASICCTL___M                 0xFFFFFFFF   
#define   DBG_CTIMAC_ASICCTL___S                               0

#define DBG_CTIMAC_ITCHINACK                      (0x00BB6EDC)
#define   DBG_CTIMAC_ITCHINACK___RWC                QCSR_REG_WO    
#define   DBG_CTIMAC_ITCHINACK___POR             0x00000000
#define   DBG_CTIMAC_ITCHINACK__CTCHINACK___POR  0x00
#define   DBG_CTIMAC_ITCHINACK__CTCHINACK___M    0x000000FF
#define   DBG_CTIMAC_ITCHINACK__CTCHINACK___S                  0
#define   DBG_CTIMAC_ITCHINACK___M               0x000000FF   
#define   DBG_CTIMAC_ITCHINACK___S                             0

#define DBG_CTIMAC_ITTRIGINACK                    (0x00BB6EE0)
#define   DBG_CTIMAC_ITTRIGINACK___RWC              QCSR_REG_WO    
#define   DBG_CTIMAC_ITTRIGINACK___POR           0x00000000
#define   DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___POR 0x000
#define   DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___M 0x00000FFF
#define   DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_CTIMAC_ITTRIGINACK___M             0x00000FFF   
#define   DBG_CTIMAC_ITTRIGINACK___S                           0

#define DBG_CTIMAC_ITCHOUT                        (0x00BB6EE4)
#define   DBG_CTIMAC_ITCHOUT___RWC                  QCSR_REG_WO    
#define   DBG_CTIMAC_ITCHOUT___POR               0x00000000
#define   DBG_CTIMAC_ITCHOUT__CTCHOUT___POR      0x00
#define   DBG_CTIMAC_ITCHOUT__CTCHOUT___M        0x000000FF
#define   DBG_CTIMAC_ITCHOUT__CTCHOUT___S                      0
#define   DBG_CTIMAC_ITCHOUT___M                 0x000000FF   
#define   DBG_CTIMAC_ITCHOUT___S                               0

#define DBG_CTIMAC_ITTRIGOUT                      (0x00BB6EE8)
#define   DBG_CTIMAC_ITTRIGOUT___RWC                QCSR_REG_WO    
#define   DBG_CTIMAC_ITTRIGOUT___POR             0x00000000
#define   DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___POR  0x000
#define   DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___M    0x00000FFF
#define   DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___S                  0
#define   DBG_CTIMAC_ITTRIGOUT___M               0x00000FFF   
#define   DBG_CTIMAC_ITTRIGOUT___S                             0

#define DBG_CTIMAC_ITCHOUTACK                     (0x00BB6EEC)
#define   DBG_CTIMAC_ITCHOUTACK___RWC               QCSR_REG_RO    
#define   DBG_CTIMAC_ITCHOUTACK___POR            0x00000000
#define   DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___M  0x000000FF
#define   DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___S                0
#define   DBG_CTIMAC_ITCHOUTACK___M              0x000000FF   
#define   DBG_CTIMAC_ITCHOUTACK___S                            0

#define DBG_CTIMAC_ITTRIGOUTACK                   (0x00BB6EF0)
#define   DBG_CTIMAC_ITTRIGOUTACK___RWC             QCSR_REG_RO    
#define   DBG_CTIMAC_ITTRIGOUTACK___POR          0x00000000
#define   DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x000
#define   DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___M 0x00000FFF
#define   DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_CTIMAC_ITTRIGOUTACK___M            0x00000FFF   
#define   DBG_CTIMAC_ITTRIGOUTACK___S                          0

#define DBG_CTIMAC_ITCHIN                         (0x00BB6EF4)
#define   DBG_CTIMAC_ITCHIN___RWC                   QCSR_REG_RO    
#define   DBG_CTIMAC_ITCHIN___POR                0x00000000
#define   DBG_CTIMAC_ITCHIN__CTCHIN___POR        0x00
#define   DBG_CTIMAC_ITCHIN__CTCHIN___M          0x000000FF
#define   DBG_CTIMAC_ITCHIN__CTCHIN___S                        0
#define   DBG_CTIMAC_ITCHIN___M                  0x000000FF   
#define   DBG_CTIMAC_ITCHIN___S                                0

#define DBG_CTIMAC_ITTRIGIN                       (0x00BB6EF8)
#define   DBG_CTIMAC_ITTRIGIN___RWC                 QCSR_REG_RO    
#define   DBG_CTIMAC_ITTRIGIN___POR              0x00000000
#define   DBG_CTIMAC_ITTRIGIN__CTTRIGIN___POR    0x000
#define   DBG_CTIMAC_ITTRIGIN__CTTRIGIN___M      0x00000FFF
#define   DBG_CTIMAC_ITTRIGIN__CTTRIGIN___S                    0
#define   DBG_CTIMAC_ITTRIGIN___M                0x00000FFF   
#define   DBG_CTIMAC_ITTRIGIN___S                              0

#define DBG_CTIMAC_ITCTRL                         (0x00BB6F00)
#define   DBG_CTIMAC_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_CTIMAC_ITCTRL___POR                0x00000000
#define   DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_CTIMAC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_CTIMAC_ITCTRL__INTEGRATION_MODE__INTG_MODE             0x1
#define   DBG_CTIMAC_ITCTRL___M                  0x00000001   
#define   DBG_CTIMAC_ITCTRL___S                                0

#define DBG_CTIMAC_CLAIMSET                       (0x00BB6FA0)
#define   DBG_CTIMAC_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CLAIMSET___POR              0x0000000F
#define   DBG_CTIMAC_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_CTIMAC_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_CTIMAC_CLAIMSET__CLAIMSET___S                    0
#define   DBG_CTIMAC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_CTIMAC_CLAIMSET___M                0x0000000F   
#define   DBG_CTIMAC_CLAIMSET___S                              0

#define DBG_CTIMAC_CLAIMCLR                       (0x00BB6FA4)
#define   DBG_CTIMAC_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_CTIMAC_CLAIMCLR___POR              0x00000000
#define   DBG_CTIMAC_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_CTIMAC_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_CTIMAC_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_CTIMAC_CLAIMCLR___M                0x0000000F   
#define   DBG_CTIMAC_CLAIMCLR___S                              0

#define DBG_CTIMAC_DEVAFF0                        (0x00BB6FA8)
#define   DBG_CTIMAC_DEVAFF0___RWC                  QCSR_REG_RO    
#define   DBG_CTIMAC_DEVAFF0___POR               0x00000000
#define   DBG_CTIMAC_DEVAFF0__VAL___POR          0x00000000
#define   DBG_CTIMAC_DEVAFF0__VAL___M            0xFFFFFFFF
#define   DBG_CTIMAC_DEVAFF0__VAL___S                          0
#define   DBG_CTIMAC_DEVAFF0___M                 0xFFFFFFFF   
#define   DBG_CTIMAC_DEVAFF0___S                               0

#define DBG_CTIMAC_DEVAFF1                        (0x00BB6FAC)
#define   DBG_CTIMAC_DEVAFF1___RWC                  QCSR_REG_RO    
#define   DBG_CTIMAC_DEVAFF1___POR               0x00000000
#define   DBG_CTIMAC_DEVAFF1__VAL___POR          0x00000000
#define   DBG_CTIMAC_DEVAFF1__VAL___M            0xFFFFFFFF
#define   DBG_CTIMAC_DEVAFF1__VAL___S                          0
#define   DBG_CTIMAC_DEVAFF1___M                 0xFFFFFFFF   
#define   DBG_CTIMAC_DEVAFF1___S                               0

#define DBG_CTIMAC_LAR                            (0x00BB6FB0)
#define   DBG_CTIMAC_LAR___RWC                      QCSR_REG_WO    
#define   DBG_CTIMAC_LAR__ACCESS_W___M           0xFFFFFFFF
#define   DBG_CTIMAC_LAR__ACCESS_W___S                         0
#define   DBG_CTIMAC_LAR__ACCESS_W__UNLOCK            0xC5ACCE55
#define   DBG_CTIMAC_LAR___M                     0xFFFFFFFF   
#define   DBG_CTIMAC_LAR___S                                   0

#define DBG_CTIMAC_LSR                            (0x00BB6FB4)
#define   DBG_CTIMAC_LSR___RWC                      QCSR_REG_RO    
#define   DBG_CTIMAC_LSR___POR                   0x00000003
#define   DBG_CTIMAC_LSR__NTT___POR              0x0
#define   DBG_CTIMAC_LSR__SLK___POR              0x1
#define   DBG_CTIMAC_LSR__SLI___POR              0x1
#define   DBG_CTIMAC_LSR__NTT___M                0x00000004
#define   DBG_CTIMAC_LSR__NTT___S                              2
#define   DBG_CTIMAC_LSR__NTT__SIZE_32BIT                    0x0
#define   DBG_CTIMAC_LSR__SLK___M                0x00000002
#define   DBG_CTIMAC_LSR__SLK___S                              1
#define   DBG_CTIMAC_LSR__SLK__ACCESS_PERMITTED              0x0
#define   DBG_CTIMAC_LSR__SLK__DEVICE_LOCKED                 0x1
#define   DBG_CTIMAC_LSR__SLI___M                0x00000001
#define   DBG_CTIMAC_LSR__SLI___S                              0
#define   DBG_CTIMAC_LSR__SLI__LOCK_NOT_PRESENT              0x0
#define   DBG_CTIMAC_LSR__SLI__LOCK_PRESENT                  0x1
#define   DBG_CTIMAC_LSR___M                     0x00000007   
#define   DBG_CTIMAC_LSR___S                                   0

#define DBG_CTIMAC_AUTHSTATUS                     (0x00BB6FB8)
#define   DBG_CTIMAC_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CTIMAC_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_CTIMAC_AUTHSTATUS__SNID___S                      6
#define   DBG_CTIMAC_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIMAC_AUTHSTATUS__SID___M         0x00000030
#define   DBG_CTIMAC_AUTHSTATUS__SID___S                       4
#define   DBG_CTIMAC_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_CTIMAC_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_CTIMAC_AUTHSTATUS__NSNID___S                     2
#define   DBG_CTIMAC_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_CTIMAC_AUTHSTATUS__NSNID__ENABLED              0x3
#define   DBG_CTIMAC_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_CTIMAC_AUTHSTATUS__NSID___S                      0
#define   DBG_CTIMAC_AUTHSTATUS__NSID__DISABLED              0x2
#define   DBG_CTIMAC_AUTHSTATUS__NSID__ENABLED               0x3
#define   DBG_CTIMAC_AUTHSTATUS___M              0x000000FF   
#define   DBG_CTIMAC_AUTHSTATUS___S                            0

#define DBG_CTIMAC_DEVARCH                        (0x00BB6FBC)
#define   DBG_CTIMAC_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CTIMAC_DEVARCH___POR               0x8EF00A14
#define   DBG_CTIMAC_DEVARCH__ARCHITECT___POR    0x477
#define   DBG_CTIMAC_DEVARCH__PRESENT___POR      0x1
#define   DBG_CTIMAC_DEVARCH__REVISION___POR     0x0
#define   DBG_CTIMAC_DEVARCH__ARCHID___POR       0x0A14
#define   DBG_CTIMAC_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CTIMAC_DEVARCH__ARCHITECT___S                   21
#define   DBG_CTIMAC_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CTIMAC_DEVARCH__PRESENT___S                     20
#define   DBG_CTIMAC_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CTIMAC_DEVARCH__REVISION___S                    16
#define   DBG_CTIMAC_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CTIMAC_DEVARCH__ARCHID___S                       0
#define   DBG_CTIMAC_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CTIMAC_DEVARCH___S                               0

#define DBG_CTIMAC_DEVID2                         (0x00BB6FC0)
#define   DBG_CTIMAC_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CTIMAC_DEVID2___POR                0x00000000
#define   DBG_CTIMAC_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CTIMAC_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CTIMAC_DEVID2__IMPLDEF___S                       0
#define   DBG_CTIMAC_DEVID2___M                  0x00000001   
#define   DBG_CTIMAC_DEVID2___S                                0

#define DBG_CTIMAC_DEVID1                         (0x00BB6FC4)
#define   DBG_CTIMAC_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CTIMAC_DEVID1___POR                0x00000000
#define   DBG_CTIMAC_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CTIMAC_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CTIMAC_DEVID1__IMPLDEF___S                       0
#define   DBG_CTIMAC_DEVID1___M                  0x00000001   
#define   DBG_CTIMAC_DEVID1___S                                0

#define DBG_CTIMAC_DEVID                          (0x00BB6FC8)
#define   DBG_CTIMAC_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_DEVID___POR                 0x00080C00
#define   DBG_CTIMAC_DEVID__NUMCH___POR          0x8
#define   DBG_CTIMAC_DEVID__NUMTRIG___POR        0xC
#define   DBG_CTIMAC_DEVID__EXTMUXNUM___POR      0x00
#define   DBG_CTIMAC_DEVID__NUMCH___M            0x003F0000
#define   DBG_CTIMAC_DEVID__NUMCH___S                         16
#define   DBG_CTIMAC_DEVID__NUMTRIG___M          0x0000FF00
#define   DBG_CTIMAC_DEVID__NUMTRIG___S                        8
#define   DBG_CTIMAC_DEVID__EXTMUXNUM___M        0x0000001F
#define   DBG_CTIMAC_DEVID__EXTMUXNUM___S                      0
#define   DBG_CTIMAC_DEVID___M                   0x003FFF1F   
#define   DBG_CTIMAC_DEVID___S                                 0

#define DBG_CTIMAC_DEVTYPE                        (0x00BB6FCC)
#define   DBG_CTIMAC_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_CTIMAC_DEVTYPE___POR               0x00000014
#define   DBG_CTIMAC_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___POR   0x4
#define   DBG_CTIMAC_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_CTIMAC_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_CTIMAC_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_CTIMAC_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_CTIMAC_DEVTYPE___M                 0x000000FF   
#define   DBG_CTIMAC_DEVTYPE___S                               0

#define DBG_CTIMAC_PIDR0                          (0x00BB6FE0)
#define   DBG_CTIMAC_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_PIDR0___POR                 0x00000006
#define   DBG_CTIMAC_PIDR0__PART_0___POR         0x06
#define   DBG_CTIMAC_PIDR0__PART_0___M           0x000000FF
#define   DBG_CTIMAC_PIDR0__PART_0___S                         0
#define   DBG_CTIMAC_PIDR0__PART_0__CTI_PART_NUMBER_BITS7TO0            0x06
#define   DBG_CTIMAC_PIDR0___M                   0x000000FF   
#define   DBG_CTIMAC_PIDR0___S                                 0

#define DBG_CTIMAC_PIDR1                          (0x00BB6FE4)
#define   DBG_CTIMAC_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_PIDR1___POR                 0x000000B9
#define   DBG_CTIMAC_PIDR1__DES_0___POR          0xB
#define   DBG_CTIMAC_PIDR1__PART_1___POR         0x9
#define   DBG_CTIMAC_PIDR1__DES_0___M            0x000000F0
#define   DBG_CTIMAC_PIDR1__DES_0___S                          4
#define   DBG_CTIMAC_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_BITS3TO0             0xB
#define   DBG_CTIMAC_PIDR1__PART_1___M           0x0000000F
#define   DBG_CTIMAC_PIDR1__PART_1___S                         0
#define   DBG_CTIMAC_PIDR1__PART_1__CTI_PART_NUMBER_BITS11TO8             0x9
#define   DBG_CTIMAC_PIDR1___M                   0x000000FF   
#define   DBG_CTIMAC_PIDR1___S                                 0

#define DBG_CTIMAC_PIDR2                          (0x00BB6FE8)
#define   DBG_CTIMAC_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_PIDR2___POR                 0x0000004B
#define   DBG_CTIMAC_PIDR2__REVISION___POR       0x4
#define   DBG_CTIMAC_PIDR2__JEDEC___POR          0x1
#define   DBG_CTIMAC_PIDR2__DES_1___POR          0x3
#define   DBG_CTIMAC_PIDR2__REVISION___M         0x000000F0
#define   DBG_CTIMAC_PIDR2__REVISION___S                       4
#define   DBG_CTIMAC_PIDR2__REVISION__R0P5                   0x4
#define   DBG_CTIMAC_PIDR2__JEDEC___M            0x00000008
#define   DBG_CTIMAC_PIDR2__JEDEC___S                          3
#define   DBG_CTIMAC_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_CTIMAC_PIDR2__DES_1___M            0x00000007
#define   DBG_CTIMAC_PIDR2__DES_1___S                          0
#define   DBG_CTIMAC_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_BITS6TO4             0x3
#define   DBG_CTIMAC_PIDR2___M                   0x000000FF   
#define   DBG_CTIMAC_PIDR2___S                                 0

#define DBG_CTIMAC_PIDR3                          (0x00BB6FEC)
#define   DBG_CTIMAC_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_PIDR3___POR                 0x00000000
#define   DBG_CTIMAC_PIDR3__REVAND___POR         0x0
#define   DBG_CTIMAC_PIDR3__CMOD___POR           0x0
#define   DBG_CTIMAC_PIDR3__REVAND___M           0x000000F0
#define   DBG_CTIMAC_PIDR3__REVAND___S                         4
#define   DBG_CTIMAC_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_CTIMAC_PIDR3__CMOD___M             0x0000000F
#define   DBG_CTIMAC_PIDR3__CMOD___S                           0
#define   DBG_CTIMAC_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_CTIMAC_PIDR3___M                   0x000000FF   
#define   DBG_CTIMAC_PIDR3___S                                 0

#define DBG_CTIMAC_PIDR4                          (0x00BB6FD0)
#define   DBG_CTIMAC_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_PIDR4___POR                 0x00000004
#define   DBG_CTIMAC_PIDR4__SIZE___POR           0x0
#define   DBG_CTIMAC_PIDR4__DES_2___POR          0x4
#define   DBG_CTIMAC_PIDR4__SIZE___M             0x000000F0
#define   DBG_CTIMAC_PIDR4__SIZE___S                           4
#define   DBG_CTIMAC_PIDR4__SIZE__SIZE_4KB                   0x0
#define   DBG_CTIMAC_PIDR4__DES_2___M            0x0000000F
#define   DBG_CTIMAC_PIDR4__DES_2___S                          0
#define   DBG_CTIMAC_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_CTIMAC_PIDR4___M                   0x000000FF   
#define   DBG_CTIMAC_PIDR4___S                                 0

#define DBG_CTIMAC_PIDR5                          (0x00BB6FD4)
#define   DBG_CTIMAC_PIDR5___RWC                    QCSR_REG_RW    
#define   DBG_CTIMAC_PIDR5__PERIPHID5___M        0xFFFFFFFF
#define   DBG_CTIMAC_PIDR5__PERIPHID5___S                      0
#define   DBG_CTIMAC_PIDR5___M                   0xFFFFFFFF   
#define   DBG_CTIMAC_PIDR5___S                                 0

#define DBG_CTIMAC_PIDR6                          (0x00BB6FD8)
#define   DBG_CTIMAC_PIDR6___RWC                    QCSR_REG_RW    
#define   DBG_CTIMAC_PIDR6__PERIPHID6___M        0xFFFFFFFF
#define   DBG_CTIMAC_PIDR6__PERIPHID6___S                      0
#define   DBG_CTIMAC_PIDR6___M                   0xFFFFFFFF   
#define   DBG_CTIMAC_PIDR6___S                                 0

#define DBG_CTIMAC_PIDR7                          (0x00BB6FDC)
#define   DBG_CTIMAC_PIDR7___RWC                    QCSR_REG_RW    
#define   DBG_CTIMAC_PIDR7__PERIPHID7___M        0xFFFFFFFF
#define   DBG_CTIMAC_PIDR7__PERIPHID7___S                      0
#define   DBG_CTIMAC_PIDR7___M                   0xFFFFFFFF   
#define   DBG_CTIMAC_PIDR7___S                                 0

#define DBG_CTIMAC_CIDR0                          (0x00BB6FF0)
#define   DBG_CTIMAC_CIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_CIDR0___POR                 0x0000000D
#define   DBG_CTIMAC_CIDR0__PRMBL_0___POR        0x0D
#define   DBG_CTIMAC_CIDR0__PRMBL_0___M          0x000000FF
#define   DBG_CTIMAC_CIDR0__PRMBL_0___S                        0
#define   DBG_CTIMAC_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_CTIMAC_CIDR0___M                   0x000000FF   
#define   DBG_CTIMAC_CIDR0___S                                 0

#define DBG_CTIMAC_CIDR1                          (0x00BB6FF4)
#define   DBG_CTIMAC_CIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_CIDR1___POR                 0x00000090
#define   DBG_CTIMAC_CIDR1__CLASS___POR          0x9
#define   DBG_CTIMAC_CIDR1__PRMBL_1___POR        0x0
#define   DBG_CTIMAC_CIDR1__CLASS___M            0x000000F0
#define   DBG_CTIMAC_CIDR1__CLASS___S                          4
#define   DBG_CTIMAC_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_CTIMAC_CIDR1__PRMBL_1___M          0x0000000F
#define   DBG_CTIMAC_CIDR1__PRMBL_1___S                        0
#define   DBG_CTIMAC_CIDR1__PRMBL_1__ID_VALUE_0              0x0
#define   DBG_CTIMAC_CIDR1___M                   0x000000FF   
#define   DBG_CTIMAC_CIDR1___S                                 0

#define DBG_CTIMAC_CIDR2                          (0x00BB6FF8)
#define   DBG_CTIMAC_CIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_CIDR2___POR                 0x00000005
#define   DBG_CTIMAC_CIDR2__PRMBL_2___POR        0x05
#define   DBG_CTIMAC_CIDR2__PRMBL_2___M          0x000000FF
#define   DBG_CTIMAC_CIDR2__PRMBL_2___S                        0
#define   DBG_CTIMAC_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_CTIMAC_CIDR2___M                   0x000000FF   
#define   DBG_CTIMAC_CIDR2___S                                 0

#define DBG_CTIMAC_CIDR3                          (0x00BB6FFC)
#define   DBG_CTIMAC_CIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTIMAC_CIDR3___POR                 0x000000B1
#define   DBG_CTIMAC_CIDR3__PRMBL_3___POR        0xB1
#define   DBG_CTIMAC_CIDR3__PRMBL_3___M          0x000000FF
#define   DBG_CTIMAC_CIDR3__PRMBL_3___S                        0
#define   DBG_CTIMAC_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_CTIMAC_CIDR3___M                   0x000000FF   
#define   DBG_CTIMAC_CIDR3___S                                 0

#define DBG_CFG                                   (0x00BB8000)
#define   DBG_CFG___RWC                             QCSR_REG_RW    
#define   DBG_CFG___POR                          0x00000000
#define   DBG_CFG__TSBIT_VAL___POR               0x00
#define   DBG_CFG__ATBID___POR                   0x00
#define   DBG_CFG__TRIG_EN___POR                 0x0
#define   DBG_CFG__TSBIT_VAL___M                 0x00003F00
#define   DBG_CFG__TSBIT_VAL___S                               8
#define   DBG_CFG__ATBID___M                     0x000000FE
#define   DBG_CFG__ATBID___S                                   1
#define   DBG_CFG__TRIG_EN___M                   0x00000001
#define   DBG_CFG__TRIG_EN___S                                 0
#define   DBG_CFG___M                            0x00003FFF   
#define   DBG_CFG___S                                          0

#define DBG_SW_INJCT_REQ                          (0x00BB8004)
#define   DBG_SW_INJCT_REQ___RWC                    QCSR_REG_WO    
#define   DBG_SW_INJCT_REQ___POR                 0x00000000
#define   DBG_SW_INJCT_REQ__REQ___POR            0x0
#define   DBG_SW_INJCT_REQ__REQ___M              0x00000001
#define   DBG_SW_INJCT_REQ__REQ___S                            0
#define   DBG_SW_INJCT_REQ__REQ__NOP                         0x0
#define   DBG_SW_INJCT_REQ__REQ__INJECT_TIMESTAMP             0x1
#define   DBG_SW_INJCT_REQ___M                   0x00000001   
#define   DBG_SW_INJCT_REQ___S                                 0

#define DBG_TPDM_DSB_CR                           (0x00BB9780)
#define   DBG_TPDM_DSB_CR___RWC                     QCSR_REG_RW    
#define   DBG_TPDM_DSB_CR___POR                  0x00000000
#define   DBG_TPDM_DSB_CR__TRIG_TYPE___POR       0x0
#define   DBG_TPDM_DSB_CR__ATBFLOWERR___POR      0x0
#define   DBG_TPDM_DSB_CR__EBITSET___POR         0x0
#define   DBG_TPDM_DSB_CR__HPSEL___POR           0x00
#define   DBG_TPDM_DSB_CR__MODE___POR            0x0
#define   DBG_TPDM_DSB_CR__E___POR               0x0
#define   DBG_TPDM_DSB_CR__TRIG_TYPE___M         0x00001000
#define   DBG_TPDM_DSB_CR__TRIG_TYPE___S                      12
#define   DBG_TPDM_DSB_CR__ATBFLOWERR___M        0x00000100
#define   DBG_TPDM_DSB_CR__ATBFLOWERR___S                      8
#define   DBG_TPDM_DSB_CR__EBITSET___M           0x00000080
#define   DBG_TPDM_DSB_CR__EBITSET___S                         7
#define   DBG_TPDM_DSB_CR__HPSEL___M             0x0000007C
#define   DBG_TPDM_DSB_CR__HPSEL___S                           2
#define   DBG_TPDM_DSB_CR__MODE___M              0x00000002
#define   DBG_TPDM_DSB_CR__MODE___S                            1
#define   DBG_TPDM_DSB_CR__E___M                 0x00000001
#define   DBG_TPDM_DSB_CR__E___S                               0
#define   DBG_TPDM_DSB_CR___M                    0x000011FF   
#define   DBG_TPDM_DSB_CR___S                                  0

#define DBG_TPDM_DSB_TIER                         (0x00BB9784)
#define   DBG_TPDM_DSB_TIER___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TIER___POR                0x00000000
#define   DBG_TPDM_DSB_TIER__PATT_TYPE___POR     0x0
#define   DBG_TPDM_DSB_TIER__XTRIG_TSENAB___POR  0x0
#define   DBG_TPDM_DSB_TIER__PATT_TSENAB___POR   0x0
#define   DBG_TPDM_DSB_TIER__PATT_TYPE___M       0x00000004
#define   DBG_TPDM_DSB_TIER__PATT_TYPE___S                     2
#define   DBG_TPDM_DSB_TIER__XTRIG_TSENAB___M    0x00000002
#define   DBG_TPDM_DSB_TIER__XTRIG_TSENAB___S                  1
#define   DBG_TPDM_DSB_TIER__PATT_TSENAB___M     0x00000001
#define   DBG_TPDM_DSB_TIER__PATT_TSENAB___S                   0
#define   DBG_TPDM_DSB_TIER___M                  0x00000007   
#define   DBG_TPDM_DSB_TIER___S                                0

#define DBG_TPDM_DSB_TPRn(n)             (0x00BB9788+0x4*(n))
#define   DBG_TPDM_DSB_TPRn_nMIN   0    
#define   DBG_TPDM_DSB_TPRn_nMAX   6    
#define   DBG_TPDM_DSB_TPRn_ELEM   7    
#define   DBG_TPDM_DSB_TPRn___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPRn___POR                0x00000000
#define   DBG_TPDM_DSB_TPRn__VAL___POR           0x00000000
#define   DBG_TPDM_DSB_TPRn__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPRn__VAL___S                           0
#define   DBG_TPDM_DSB_TPRn___M                  0xFFFFFFFF   
#define   DBG_TPDM_DSB_TPRn___S                                0
#define DBG_TPDM_DSB_TPR0                         (0x00BB9788)
#define   DBG_TPDM_DSB_TPR0___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR0__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR0__VAL___S                           0
#define DBG_TPDM_DSB_TPR1                         (0x00BB978C)
#define   DBG_TPDM_DSB_TPR1___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR1__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR1__VAL___S                           0
#define DBG_TPDM_DSB_TPR2                         (0x00BB9790)
#define   DBG_TPDM_DSB_TPR2___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR2__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR2__VAL___S                           0
#define DBG_TPDM_DSB_TPR3                         (0x00BB9794)
#define   DBG_TPDM_DSB_TPR3___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR3__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR3__VAL___S                           0
#define DBG_TPDM_DSB_TPR4                         (0x00BB9798)
#define   DBG_TPDM_DSB_TPR4___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR4__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR4__VAL___S                           0
#define DBG_TPDM_DSB_TPR5                         (0x00BB979C)
#define   DBG_TPDM_DSB_TPR5___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR5__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR5__VAL___S                           0
#define DBG_TPDM_DSB_TPR6                         (0x00BB97A0)
#define   DBG_TPDM_DSB_TPR6___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR6__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR6__VAL___S                           0

#define DBG_TPDM_DSB_TPRm(m)             (0x00BB9788+0x4*(m))
#define   DBG_TPDM_DSB_TPRm_mMIN   7    
#define   DBG_TPDM_DSB_TPRm_mMAX   7    
#define   DBG_TPDM_DSB_TPRm_ELEM   1    
#define   DBG_TPDM_DSB_TPRm___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPRm___POR                0x00000000
#define   DBG_TPDM_DSB_TPRm__VAL___POR           0x00000000
#define   DBG_TPDM_DSB_TPRm__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPRm__VAL___S                           0
#define   DBG_TPDM_DSB_TPRm___M                  0xFFFFFFFF   
#define   DBG_TPDM_DSB_TPRm___S                                0
#define DBG_TPDM_DSB_TPR7                         (0x00BB97A4)
#define   DBG_TPDM_DSB_TPR7___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPR7__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_TPR7__VAL___S                           0

#define DBG_TPDM_DSB_TPMRn(n)            (0x00BB97A8+0x4*(n))
#define   DBG_TPDM_DSB_TPMRn_nMIN  0    
#define   DBG_TPDM_DSB_TPMRn_nMAX  6    
#define   DBG_TPDM_DSB_TPMRn_ELEM  7    
#define   DBG_TPDM_DSB_TPMRn___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMRn___POR               0x00000000
#define   DBG_TPDM_DSB_TPMRn__VAL___POR          0x00000000
#define   DBG_TPDM_DSB_TPMRn__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMRn__VAL___S                          0
#define   DBG_TPDM_DSB_TPMRn___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_TPMRn___S                               0
#define DBG_TPDM_DSB_TPMR0                        (0x00BB97A8)
#define   DBG_TPDM_DSB_TPMR0___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR0__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR0__VAL___S                          0
#define DBG_TPDM_DSB_TPMR1                        (0x00BB97AC)
#define   DBG_TPDM_DSB_TPMR1___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR1__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR1__VAL___S                          0
#define DBG_TPDM_DSB_TPMR2                        (0x00BB97B0)
#define   DBG_TPDM_DSB_TPMR2___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR2__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR2__VAL___S                          0
#define DBG_TPDM_DSB_TPMR3                        (0x00BB97B4)
#define   DBG_TPDM_DSB_TPMR3___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR3__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR3__VAL___S                          0
#define DBG_TPDM_DSB_TPMR4                        (0x00BB97B8)
#define   DBG_TPDM_DSB_TPMR4___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR4__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR4__VAL___S                          0
#define DBG_TPDM_DSB_TPMR5                        (0x00BB97BC)
#define   DBG_TPDM_DSB_TPMR5___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR5__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR5__VAL___S                          0
#define DBG_TPDM_DSB_TPMR6                        (0x00BB97C0)
#define   DBG_TPDM_DSB_TPMR6___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR6__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR6__VAL___S                          0

#define DBG_TPDM_DSB_TPMRm(m)            (0x00BB97A8+0x4*(m))
#define   DBG_TPDM_DSB_TPMRm_mMIN  7    
#define   DBG_TPDM_DSB_TPMRm_mMAX  7    
#define   DBG_TPDM_DSB_TPMRm_ELEM  1    
#define   DBG_TPDM_DSB_TPMRm___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMRm___POR               0x00000000
#define   DBG_TPDM_DSB_TPMRm__VAL___POR          0x00000000
#define   DBG_TPDM_DSB_TPMRm__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMRm__VAL___S                          0
#define   DBG_TPDM_DSB_TPMRm___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_TPMRm___S                               0
#define DBG_TPDM_DSB_TPMR7                        (0x00BB97C4)
#define   DBG_TPDM_DSB_TPMR7___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_TPMR7__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_TPMR7__VAL___S                          0

#define DBG_TPDM_DSB_XPRn(n)             (0x00BB97C8+0x4*(n))
#define   DBG_TPDM_DSB_XPRn_nMIN   0    
#define   DBG_TPDM_DSB_XPRn_nMAX   6    
#define   DBG_TPDM_DSB_XPRn_ELEM   7    
#define   DBG_TPDM_DSB_XPRn___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPRn___POR                0x00000000
#define   DBG_TPDM_DSB_XPRn__VAL___POR           0x00000000
#define   DBG_TPDM_DSB_XPRn__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPRn__VAL___S                           0
#define   DBG_TPDM_DSB_XPRn___M                  0xFFFFFFFF   
#define   DBG_TPDM_DSB_XPRn___S                                0
#define DBG_TPDM_DSB_XPR0                         (0x00BB97C8)
#define   DBG_TPDM_DSB_XPR0___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR0__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR0__VAL___S                           0
#define DBG_TPDM_DSB_XPR1                         (0x00BB97CC)
#define   DBG_TPDM_DSB_XPR1___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR1__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR1__VAL___S                           0
#define DBG_TPDM_DSB_XPR2                         (0x00BB97D0)
#define   DBG_TPDM_DSB_XPR2___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR2__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR2__VAL___S                           0
#define DBG_TPDM_DSB_XPR3                         (0x00BB97D4)
#define   DBG_TPDM_DSB_XPR3___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR3__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR3__VAL___S                           0
#define DBG_TPDM_DSB_XPR4                         (0x00BB97D8)
#define   DBG_TPDM_DSB_XPR4___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR4__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR4__VAL___S                           0
#define DBG_TPDM_DSB_XPR5                         (0x00BB97DC)
#define   DBG_TPDM_DSB_XPR5___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR5__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR5__VAL___S                           0
#define DBG_TPDM_DSB_XPR6                         (0x00BB97E0)
#define   DBG_TPDM_DSB_XPR6___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR6__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR6__VAL___S                           0

#define DBG_TPDM_DSB_XPRm(m)             (0x00BB97C8+0x4*(m))
#define   DBG_TPDM_DSB_XPRm_mMIN   7    
#define   DBG_TPDM_DSB_XPRm_mMAX   7    
#define   DBG_TPDM_DSB_XPRm_ELEM   1    
#define   DBG_TPDM_DSB_XPRm___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPRm___POR                0x00000000
#define   DBG_TPDM_DSB_XPRm__VAL___POR           0x00000000
#define   DBG_TPDM_DSB_XPRm__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPRm__VAL___S                           0
#define   DBG_TPDM_DSB_XPRm___M                  0xFFFFFFFF   
#define   DBG_TPDM_DSB_XPRm___S                                0
#define DBG_TPDM_DSB_XPR7                         (0x00BB97E4)
#define   DBG_TPDM_DSB_XPR7___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPR7__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_DSB_XPR7__VAL___S                           0

#define DBG_TPDM_DSB_XPMRn(n)            (0x00BB97E8+0x4*(n))
#define   DBG_TPDM_DSB_XPMRn_nMIN  0    
#define   DBG_TPDM_DSB_XPMRn_nMAX  6    
#define   DBG_TPDM_DSB_XPMRn_ELEM  7    
#define   DBG_TPDM_DSB_XPMRn___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMRn___POR               0x00000000
#define   DBG_TPDM_DSB_XPMRn__VAL___POR          0x00000000
#define   DBG_TPDM_DSB_XPMRn__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMRn__VAL___S                          0
#define   DBG_TPDM_DSB_XPMRn___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_XPMRn___S                               0
#define DBG_TPDM_DSB_XPMR0                        (0x00BB97E8)
#define   DBG_TPDM_DSB_XPMR0___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR0__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR0__VAL___S                          0
#define DBG_TPDM_DSB_XPMR1                        (0x00BB97EC)
#define   DBG_TPDM_DSB_XPMR1___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR1__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR1__VAL___S                          0
#define DBG_TPDM_DSB_XPMR2                        (0x00BB97F0)
#define   DBG_TPDM_DSB_XPMR2___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR2__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR2__VAL___S                          0
#define DBG_TPDM_DSB_XPMR3                        (0x00BB97F4)
#define   DBG_TPDM_DSB_XPMR3___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR3__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR3__VAL___S                          0
#define DBG_TPDM_DSB_XPMR4                        (0x00BB97F8)
#define   DBG_TPDM_DSB_XPMR4___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR4__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR4__VAL___S                          0
#define DBG_TPDM_DSB_XPMR5                        (0x00BB97FC)
#define   DBG_TPDM_DSB_XPMR5___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR5__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR5__VAL___S                          0
#define DBG_TPDM_DSB_XPMR6                        (0x00BB9800)
#define   DBG_TPDM_DSB_XPMR6___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR6__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR6__VAL___S                          0

#define DBG_TPDM_DSB_XPMRm(m)            (0x00BB97E8+0x4*(m))
#define   DBG_TPDM_DSB_XPMRm_mMIN  7    
#define   DBG_TPDM_DSB_XPMRm_mMAX  7    
#define   DBG_TPDM_DSB_XPMRm_ELEM  1    
#define   DBG_TPDM_DSB_XPMRm___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMRm___POR               0x00000000
#define   DBG_TPDM_DSB_XPMRm__VAL___POR          0x00000000
#define   DBG_TPDM_DSB_XPMRm__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMRm__VAL___S                          0
#define   DBG_TPDM_DSB_XPMRm___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_XPMRm___S                               0
#define DBG_TPDM_DSB_XPMR7                        (0x00BB9804)
#define   DBG_TPDM_DSB_XPMR7___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_XPMR7__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_DSB_XPMR7__VAL___S                          0

#define DBG_TPDM_DSB_EDCRn(n)            (0x00BB9808+0x4*(n))
#define   DBG_TPDM_DSB_EDCRn_nMIN  0    
#define   DBG_TPDM_DSB_EDCRn_nMAX  14   
#define   DBG_TPDM_DSB_EDCRn_ELEM  15   
#define   DBG_TPDM_DSB_EDCRn___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCRn___POR               0x00000000
#define   DBG_TPDM_DSB_EDCRn__EDGECONTROL___POR  0x00000000
#define   DBG_TPDM_DSB_EDCRn__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCRn__EDGECONTROL___S                  0
#define   DBG_TPDM_DSB_EDCRn___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_EDCRn___S                               0
#define DBG_TPDM_DSB_EDCR0                        (0x00BB9808)
#define   DBG_TPDM_DSB_EDCR0___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR0__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR0__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR1                        (0x00BB980C)
#define   DBG_TPDM_DSB_EDCR1___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR1__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR1__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR2                        (0x00BB9810)
#define   DBG_TPDM_DSB_EDCR2___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR2__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR2__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR3                        (0x00BB9814)
#define   DBG_TPDM_DSB_EDCR3___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR3__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR3__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR4                        (0x00BB9818)
#define   DBG_TPDM_DSB_EDCR4___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR4__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR4__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR5                        (0x00BB981C)
#define   DBG_TPDM_DSB_EDCR5___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR5__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR5__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR6                        (0x00BB9820)
#define   DBG_TPDM_DSB_EDCR6___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR6__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR6__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR7                        (0x00BB9824)
#define   DBG_TPDM_DSB_EDCR7___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR7__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR7__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR8                        (0x00BB9828)
#define   DBG_TPDM_DSB_EDCR8___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR8__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR8__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR9                        (0x00BB982C)
#define   DBG_TPDM_DSB_EDCR9___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR9__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR9__EDGECONTROL___S                  0
#define DBG_TPDM_DSB_EDCR10                       (0x00BB9830)
#define   DBG_TPDM_DSB_EDCR10___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR10__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR10__EDGECONTROL___S                 0
#define DBG_TPDM_DSB_EDCR11                       (0x00BB9834)
#define   DBG_TPDM_DSB_EDCR11___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR11__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR11__EDGECONTROL___S                 0
#define DBG_TPDM_DSB_EDCR12                       (0x00BB9838)
#define   DBG_TPDM_DSB_EDCR12___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR12__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR12__EDGECONTROL___S                 0
#define DBG_TPDM_DSB_EDCR13                       (0x00BB983C)
#define   DBG_TPDM_DSB_EDCR13___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR13__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR13__EDGECONTROL___S                 0
#define DBG_TPDM_DSB_EDCR14                       (0x00BB9840)
#define   DBG_TPDM_DSB_EDCR14___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR14__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR14__EDGECONTROL___S                 0

#define DBG_TPDM_DSB_EDCRm(m)            (0x00BB9808+0x4*(m))
#define   DBG_TPDM_DSB_EDCRm_mMIN  15   
#define   DBG_TPDM_DSB_EDCRm_mMAX  15   
#define   DBG_TPDM_DSB_EDCRm_ELEM  1    
#define   DBG_TPDM_DSB_EDCRm___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCRm___POR               0x00000000
#define   DBG_TPDM_DSB_EDCRm__EDGECONTROL___POR  0x00000000
#define   DBG_TPDM_DSB_EDCRm__EDGECONTROL___M    0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCRm__EDGECONTROL___S                  0
#define   DBG_TPDM_DSB_EDCRm___M                 0xFFFFFFFF   
#define   DBG_TPDM_DSB_EDCRm___S                               0
#define DBG_TPDM_DSB_EDCR15                       (0x00BB9844)
#define   DBG_TPDM_DSB_EDCR15___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCR15__EDGECONTROL___M   0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCR15__EDGECONTROL___S                 0

#define DBG_TPDM_DSB_EDCMRn(n)           (0x00BB9848+0x4*(n))
#define   DBG_TPDM_DSB_EDCMRn_nMIN 0    
#define   DBG_TPDM_DSB_EDCMRn_nMAX 6    
#define   DBG_TPDM_DSB_EDCMRn_ELEM 7    
#define   DBG_TPDM_DSB_EDCMRn___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMRn___POR              0x00000000
#define   DBG_TPDM_DSB_EDCMRn__VAL___POR         0x00000000
#define   DBG_TPDM_DSB_EDCMRn__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMRn__VAL___S                         0
#define   DBG_TPDM_DSB_EDCMRn___M                0xFFFFFFFF   
#define   DBG_TPDM_DSB_EDCMRn___S                              0
#define DBG_TPDM_DSB_EDCMR0                       (0x00BB9848)
#define   DBG_TPDM_DSB_EDCMR0___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR0__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR0__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR1                       (0x00BB984C)
#define   DBG_TPDM_DSB_EDCMR1___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR1__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR1__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR2                       (0x00BB9850)
#define   DBG_TPDM_DSB_EDCMR2___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR2__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR2__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR3                       (0x00BB9854)
#define   DBG_TPDM_DSB_EDCMR3___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR3__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR3__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR4                       (0x00BB9858)
#define   DBG_TPDM_DSB_EDCMR4___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR4__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR4__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR5                       (0x00BB985C)
#define   DBG_TPDM_DSB_EDCMR5___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR5__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR5__VAL___S                         0
#define DBG_TPDM_DSB_EDCMR6                       (0x00BB9860)
#define   DBG_TPDM_DSB_EDCMR6___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR6__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR6__VAL___S                         0

#define DBG_TPDM_DSB_EDCMRm(m)           (0x00BB9848+0x4*(m))
#define   DBG_TPDM_DSB_EDCMRm_mMIN 7    
#define   DBG_TPDM_DSB_EDCMRm_mMAX 7    
#define   DBG_TPDM_DSB_EDCMRm_ELEM 1    
#define   DBG_TPDM_DSB_EDCMRm___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMRm___POR              0x00000000
#define   DBG_TPDM_DSB_EDCMRm__VAL___POR         0x00000000
#define   DBG_TPDM_DSB_EDCMRm__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMRm__VAL___S                         0
#define   DBG_TPDM_DSB_EDCMRm___M                0xFFFFFFFF   
#define   DBG_TPDM_DSB_EDCMRm___S                              0
#define DBG_TPDM_DSB_EDCMR7                       (0x00BB9864)
#define   DBG_TPDM_DSB_EDCMR7___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_DSB_EDCMR7__VAL___M           0xFFFFFFFF
#define   DBG_TPDM_DSB_EDCMR7__VAL___S                         0

#define DBG_TPDM_DSB_READCTL                      (0x00BB9970)
#define   DBG_TPDM_DSB_READCTL___RWC                QCSR_REG_RW    
#define   DBG_TPDM_DSB_READCTL___POR             0x00000000
#define   DBG_TPDM_DSB_READCTL__MODE___POR       0x0
#define   DBG_TPDM_DSB_READCTL__SLICESEL___POR   0x0
#define   DBG_TPDM_DSB_READCTL__MODE___M         0x00000008
#define   DBG_TPDM_DSB_READCTL__MODE___S                       3
#define   DBG_TPDM_DSB_READCTL__SLICESEL___M     0x00000007
#define   DBG_TPDM_DSB_READCTL__SLICESEL___S                   0
#define   DBG_TPDM_DSB_READCTL___M               0x0000000F   
#define   DBG_TPDM_DSB_READCTL___S                             0

#define DBG_TPDM_DSB_READVAL                      (0x00BB9974)
#define   DBG_TPDM_DSB_READVAL___RWC                QCSR_REG_RO    
#define   DBG_TPDM_DSB_READVAL___POR             0x00000000
#define   DBG_TPDM_DSB_READVAL__VALUE___POR      0x00000000
#define   DBG_TPDM_DSB_READVAL__VALUE___M        0xFFFFFFFF
#define   DBG_TPDM_DSB_READVAL__VALUE___S                      0
#define   DBG_TPDM_DSB_READVAL___M               0xFFFFFFFF   
#define   DBG_TPDM_DSB_READVAL___S                             0

#define DBG_TPDM_CMB_CR                           (0x00BB9A00)
#define   DBG_TPDM_CMB_CR___RWC                     QCSR_REG_RW    
#define   DBG_TPDM_CMB_CR___POR                  0x00000000
#define   DBG_TPDM_CMB_CR__ATBFLOWERR___POR      0x0
#define   DBG_TPDM_CMB_CR__EBITSET___POR         0x0
#define   DBG_TPDM_CMB_CR__FLOWCTRL___POR        0x0
#define   DBG_TPDM_CMB_CR__MODE___POR            0x0
#define   DBG_TPDM_CMB_CR__E___POR               0x0
#define   DBG_TPDM_CMB_CR__ATBFLOWERR___M        0x00000080
#define   DBG_TPDM_CMB_CR__ATBFLOWERR___S                      7
#define   DBG_TPDM_CMB_CR__EBITSET___M           0x00000040
#define   DBG_TPDM_CMB_CR__EBITSET___S                         6
#define   DBG_TPDM_CMB_CR__FLOWCTRL___M          0x00000004
#define   DBG_TPDM_CMB_CR__FLOWCTRL___S                        2
#define   DBG_TPDM_CMB_CR__MODE___M              0x00000002
#define   DBG_TPDM_CMB_CR__MODE___S                            1
#define   DBG_TPDM_CMB_CR__E___M                 0x00000001
#define   DBG_TPDM_CMB_CR__E___S                               0
#define   DBG_TPDM_CMB_CR___M                    0x000000C7   
#define   DBG_TPDM_CMB_CR___S                                  0

#define DBG_TPDM_CMB_TIER                         (0x00BB9A04)
#define   DBG_TPDM_CMB_TIER___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_TIER___POR                0x00000000
#define   DBG_TPDM_CMB_TIER__TS_ALL___POR        0x0
#define   DBG_TPDM_CMB_TIER__XTRIG_TSENAB___POR  0x0
#define   DBG_TPDM_CMB_TIER__PATT_TSENAB___POR   0x0
#define   DBG_TPDM_CMB_TIER__TS_ALL___M          0x00000004
#define   DBG_TPDM_CMB_TIER__TS_ALL___S                        2
#define   DBG_TPDM_CMB_TIER__XTRIG_TSENAB___M    0x00000002
#define   DBG_TPDM_CMB_TIER__XTRIG_TSENAB___S                  1
#define   DBG_TPDM_CMB_TIER__PATT_TSENAB___M     0x00000001
#define   DBG_TPDM_CMB_TIER__PATT_TSENAB___S                   0
#define   DBG_TPDM_CMB_TIER___M                  0x00000007   
#define   DBG_TPDM_CMB_TIER___S                                0

#define DBG_TPDM_CMB_TPRn(n)             (0x00BB9A08+0x4*(n))
#define   DBG_TPDM_CMB_TPRn_nMIN   0    
#define   DBG_TPDM_CMB_TPRn_nMAX   0    
#define   DBG_TPDM_CMB_TPRn_ELEM   1    
#define   DBG_TPDM_CMB_TPRn___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPRn___POR                0x00000000
#define   DBG_TPDM_CMB_TPRn__VAL___POR           0x00000000
#define   DBG_TPDM_CMB_TPRn__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_CMB_TPRn__VAL___S                           0
#define   DBG_TPDM_CMB_TPRn___M                  0xFFFFFFFF   
#define   DBG_TPDM_CMB_TPRn___S                                0
#define DBG_TPDM_CMB_TPR0                         (0x00BB9A08)
#define   DBG_TPDM_CMB_TPR0___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPR0__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_CMB_TPR0__VAL___S                           0

#define DBG_TPDM_CMB_TPRm(m)             (0x00BB9A08+0x4*(m))
#define   DBG_TPDM_CMB_TPRm_mMIN   1    
#define   DBG_TPDM_CMB_TPRm_mMAX   1    
#define   DBG_TPDM_CMB_TPRm_ELEM   1    
#define   DBG_TPDM_CMB_TPRm___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPRm___POR                0x00000000
#define   DBG_TPDM_CMB_TPRm__VAL___POR           0x00
#define   DBG_TPDM_CMB_TPRm__VAL___M             0x000000FF
#define   DBG_TPDM_CMB_TPRm__VAL___S                           0
#define   DBG_TPDM_CMB_TPRm___M                  0x000000FF   
#define   DBG_TPDM_CMB_TPRm___S                                0
#define DBG_TPDM_CMB_TPR1                         (0x00BB9A0C)
#define   DBG_TPDM_CMB_TPR1___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPR1__VAL___M             0x000000FF
#define   DBG_TPDM_CMB_TPR1__VAL___S                           0

#define DBG_TPDM_CMB_TPMRn(n)            (0x00BB9A10+0x4*(n))
#define   DBG_TPDM_CMB_TPMRn_nMIN  0    
#define   DBG_TPDM_CMB_TPMRn_nMAX  0    
#define   DBG_TPDM_CMB_TPMRn_ELEM  1    
#define   DBG_TPDM_CMB_TPMRn___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPMRn___POR               0x00000000
#define   DBG_TPDM_CMB_TPMRn__VAL___POR          0x00000000
#define   DBG_TPDM_CMB_TPMRn__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_CMB_TPMRn__VAL___S                          0
#define   DBG_TPDM_CMB_TPMRn___M                 0xFFFFFFFF   
#define   DBG_TPDM_CMB_TPMRn___S                               0
#define DBG_TPDM_CMB_TPMR0                        (0x00BB9A10)
#define   DBG_TPDM_CMB_TPMR0___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPMR0__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_CMB_TPMR0__VAL___S                          0

#define DBG_TPDM_CMB_TPMRm(m)            (0x00BB9A10+0x4*(m))
#define   DBG_TPDM_CMB_TPMRm_mMIN  1    
#define   DBG_TPDM_CMB_TPMRm_mMAX  1    
#define   DBG_TPDM_CMB_TPMRm_ELEM  1    
#define   DBG_TPDM_CMB_TPMRm___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPMRm___POR               0x00000000
#define   DBG_TPDM_CMB_TPMRm__VAL___POR          0x00
#define   DBG_TPDM_CMB_TPMRm__VAL___M            0x000000FF
#define   DBG_TPDM_CMB_TPMRm__VAL___S                          0
#define   DBG_TPDM_CMB_TPMRm___M                 0x000000FF   
#define   DBG_TPDM_CMB_TPMRm___S                               0
#define DBG_TPDM_CMB_TPMR1                        (0x00BB9A14)
#define   DBG_TPDM_CMB_TPMR1___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_TPMR1__VAL___M            0x000000FF
#define   DBG_TPDM_CMB_TPMR1__VAL___S                          0

#define DBG_TPDM_CMB_XPRn(n)             (0x00BB9A18+0x4*(n))
#define   DBG_TPDM_CMB_XPRn_nMIN   0    
#define   DBG_TPDM_CMB_XPRn_nMAX   0    
#define   DBG_TPDM_CMB_XPRn_ELEM   1    
#define   DBG_TPDM_CMB_XPRn___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPRn___POR                0x00000000
#define   DBG_TPDM_CMB_XPRn__VAL___POR           0x00000000
#define   DBG_TPDM_CMB_XPRn__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_CMB_XPRn__VAL___S                           0
#define   DBG_TPDM_CMB_XPRn___M                  0xFFFFFFFF   
#define   DBG_TPDM_CMB_XPRn___S                                0
#define DBG_TPDM_CMB_XPR0                         (0x00BB9A18)
#define   DBG_TPDM_CMB_XPR0___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPR0__VAL___M             0xFFFFFFFF
#define   DBG_TPDM_CMB_XPR0__VAL___S                           0

#define DBG_TPDM_CMB_XPRm(m)             (0x00BB9A18+0x4*(m))
#define   DBG_TPDM_CMB_XPRm_mMIN   1    
#define   DBG_TPDM_CMB_XPRm_mMAX   1    
#define   DBG_TPDM_CMB_XPRm_ELEM   1    
#define   DBG_TPDM_CMB_XPRm___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPRm___POR                0x00000000
#define   DBG_TPDM_CMB_XPRm__VAL___POR           0x00
#define   DBG_TPDM_CMB_XPRm__VAL___M             0x000000FF
#define   DBG_TPDM_CMB_XPRm__VAL___S                           0
#define   DBG_TPDM_CMB_XPRm___M                  0x000000FF   
#define   DBG_TPDM_CMB_XPRm___S                                0
#define DBG_TPDM_CMB_XPR1                         (0x00BB9A1C)
#define   DBG_TPDM_CMB_XPR1___RWC                   QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPR1__VAL___M             0x000000FF
#define   DBG_TPDM_CMB_XPR1__VAL___S                           0

#define DBG_TPDM_CMB_XPMRn(n)            (0x00BB9A20+0x4*(n))
#define   DBG_TPDM_CMB_XPMRn_nMIN  0    
#define   DBG_TPDM_CMB_XPMRn_nMAX  0    
#define   DBG_TPDM_CMB_XPMRn_ELEM  1    
#define   DBG_TPDM_CMB_XPMRn___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPMRn___POR               0x00000000
#define   DBG_TPDM_CMB_XPMRn__VAL___POR          0x00000000
#define   DBG_TPDM_CMB_XPMRn__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_CMB_XPMRn__VAL___S                          0
#define   DBG_TPDM_CMB_XPMRn___M                 0xFFFFFFFF   
#define   DBG_TPDM_CMB_XPMRn___S                               0
#define DBG_TPDM_CMB_XPMR0                        (0x00BB9A20)
#define   DBG_TPDM_CMB_XPMR0___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPMR0__VAL___M            0xFFFFFFFF
#define   DBG_TPDM_CMB_XPMR0__VAL___S                          0

#define DBG_TPDM_CMB_XPMRm(m)            (0x00BB9A20+0x4*(m))
#define   DBG_TPDM_CMB_XPMRm_mMIN  1    
#define   DBG_TPDM_CMB_XPMRm_mMAX  1    
#define   DBG_TPDM_CMB_XPMRm_ELEM  1    
#define   DBG_TPDM_CMB_XPMRm___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPMRm___POR               0x00000000
#define   DBG_TPDM_CMB_XPMRm__VAL___POR          0x00
#define   DBG_TPDM_CMB_XPMRm__VAL___M            0x000000FF
#define   DBG_TPDM_CMB_XPMRm__VAL___S                          0
#define   DBG_TPDM_CMB_XPMRm___M                 0x000000FF   
#define   DBG_TPDM_CMB_XPMRm___S                               0
#define DBG_TPDM_CMB_XPMR1                        (0x00BB9A24)
#define   DBG_TPDM_CMB_XPMR1___RWC                  QCSR_REG_RW    
#define   DBG_TPDM_CMB_XPMR1__VAL___M            0x000000FF
#define   DBG_TPDM_CMB_XPMR1__VAL___S                          0

#define DBG_TPDM_CMB_READCTL                      (0x00BB9A70)
#define   DBG_TPDM_CMB_READCTL___RWC                QCSR_REG_RW    
#define   DBG_TPDM_CMB_READCTL___POR             0x00000000
#define   DBG_TPDM_CMB_READCTL__SEL___POR        0x0
#define   DBG_TPDM_CMB_READCTL__SEL___M          0x00000001
#define   DBG_TPDM_CMB_READCTL__SEL___S                        0
#define   DBG_TPDM_CMB_READCTL___M               0x00000001   
#define   DBG_TPDM_CMB_READCTL___S                             0

#define DBG_TPDM_CMB_READVAL                      (0x00BB9A74)
#define   DBG_TPDM_CMB_READVAL___RWC                QCSR_REG_RO    
#define   DBG_TPDM_CMB_READVAL___POR             0x00000000
#define   DBG_TPDM_CMB_READVAL__VALUE___POR      0x00000000
#define   DBG_TPDM_CMB_READVAL__VALUE___M        0xFFFFFFFF
#define   DBG_TPDM_CMB_READVAL__VALUE___S                      0
#define   DBG_TPDM_CMB_READVAL___M               0xFFFFFFFF   
#define   DBG_TPDM_CMB_READVAL___S                             0

#define DBG_TPDM_ITATBCNTRL                       (0x00BB9EF0)
#define   DBG_TPDM_ITATBCNTRL___RWC                 QCSR_REG_RW    
#define   DBG_TPDM_ITATBCNTRL___POR              0x00000000
#define   DBG_TPDM_ITATBCNTRL__TSREQ___POR       0x0
#define   DBG_TPDM_ITATBCNTRL__ATVALID___POR     0x0
#define   DBG_TPDM_ITATBCNTRL__ATDATAMODE___POR  0x0
#define   DBG_TPDM_ITATBCNTRL__ATBYTES___POR     0x0
#define   DBG_TPDM_ITATBCNTRL__ATDATA___POR      0x00
#define   DBG_TPDM_ITATBCNTRL__ATID___POR        0x00
#define   DBG_TPDM_ITATBCNTRL__TSVAL___POR       0x0
#define   DBG_TPDM_ITATBCNTRL__TSREQ___M         0x80000000
#define   DBG_TPDM_ITATBCNTRL__TSREQ___S                      31
#define   DBG_TPDM_ITATBCNTRL__ATVALID___M       0x40000000
#define   DBG_TPDM_ITATBCNTRL__ATVALID___S                    30
#define   DBG_TPDM_ITATBCNTRL__ATDATAMODE___M    0x00400000
#define   DBG_TPDM_ITATBCNTRL__ATDATAMODE___S                 22
#define   DBG_TPDM_ITATBCNTRL__ATBYTES___M       0x003C0000
#define   DBG_TPDM_ITATBCNTRL__ATBYTES___S                    18
#define   DBG_TPDM_ITATBCNTRL__ATDATA___M        0x0003FC00
#define   DBG_TPDM_ITATBCNTRL__ATDATA___S                     10
#define   DBG_TPDM_ITATBCNTRL__ATID___M          0x000003F8
#define   DBG_TPDM_ITATBCNTRL__ATID___S                        3
#define   DBG_TPDM_ITATBCNTRL__TSVAL___M         0x00000007
#define   DBG_TPDM_ITATBCNTRL__TSVAL___S                       0
#define   DBG_TPDM_ITATBCNTRL___M                0xC07FFFFF   
#define   DBG_TPDM_ITATBCNTRL___S                              0

#define DBG_TPDM_ITCNTRL                          (0x00BB9F00)
#define   DBG_TPDM_ITCNTRL___RWC                    QCSR_REG_RW    
#define   DBG_TPDM_ITCNTRL___POR                 0x00000000
#define   DBG_TPDM_ITCNTRL__IME___POR            0x0
#define   DBG_TPDM_ITCNTRL__IME___M              0x00000001
#define   DBG_TPDM_ITCNTRL__IME___S                            0
#define   DBG_TPDM_ITCNTRL___M                   0x00000001   
#define   DBG_TPDM_ITCNTRL___S                                 0

#define DBG_TPDM_CLAIMSET                         (0x00BB9FA0)
#define   DBG_TPDM_CLAIMSET___RWC                   QCSR_REG_RO    
#define   DBG_TPDM_CLAIMSET___POR                0x00000000
#define   DBG_TPDM_CLAIMSET__VAL_SET___POR       0x00000000
#define   DBG_TPDM_CLAIMSET__VAL_SET___M         0xFFFFFFFF
#define   DBG_TPDM_CLAIMSET__VAL_SET___S                       0
#define   DBG_TPDM_CLAIMSET___M                  0xFFFFFFFF   
#define   DBG_TPDM_CLAIMSET___S                                0

#define DBG_TPDM_CLAIMCLR                         (0x00BB9FA4)
#define   DBG_TPDM_CLAIMCLR___RWC                   QCSR_REG_RO    
#define   DBG_TPDM_CLAIMCLR___POR                0x00000000
#define   DBG_TPDM_CLAIMCLR__VAL_CLR___POR       0x00000000
#define   DBG_TPDM_CLAIMCLR__VAL_CLR___M         0xFFFFFFFF
#define   DBG_TPDM_CLAIMCLR__VAL_CLR___S                       0
#define   DBG_TPDM_CLAIMCLR___M                  0xFFFFFFFF   
#define   DBG_TPDM_CLAIMCLR___S                                0

#define DBG_TPDM_DEVAFF0                          (0x00BB9FA8)
#define   DBG_TPDM_DEVAFF0___RWC                    QCSR_REG_RO    
#define   DBG_TPDM_DEVAFF0___POR                 0x00000000
#define   DBG_TPDM_DEVAFF0__VAL___POR            0x00000000
#define   DBG_TPDM_DEVAFF0__VAL___M              0xFFFFFFFF
#define   DBG_TPDM_DEVAFF0__VAL___S                            0
#define   DBG_TPDM_DEVAFF0___M                   0xFFFFFFFF   
#define   DBG_TPDM_DEVAFF0___S                                 0

#define DBG_TPDM_DEVAFF1                          (0x00BB9FAC)
#define   DBG_TPDM_DEVAFF1___RWC                    QCSR_REG_RO    
#define   DBG_TPDM_DEVAFF1___POR                 0x00000000
#define   DBG_TPDM_DEVAFF1__VAL___POR            0x00000000
#define   DBG_TPDM_DEVAFF1__VAL___M              0xFFFFFFFF
#define   DBG_TPDM_DEVAFF1__VAL___S                            0
#define   DBG_TPDM_DEVAFF1___M                   0xFFFFFFFF   
#define   DBG_TPDM_DEVAFF1___S                                 0

#define DBG_TPDM_LAR                              (0x00BB9FB0)
#define   DBG_TPDM_LAR___RWC                        QCSR_REG_WO    
#define   DBG_TPDM_LAR___POR                     0x00000000
#define   DBG_TPDM_LAR__KEY___POR                0x00000000
#define   DBG_TPDM_LAR__KEY___M                  0xFFFFFFFF
#define   DBG_TPDM_LAR__KEY___S                                0
#define   DBG_TPDM_LAR___M                       0xFFFFFFFF   
#define   DBG_TPDM_LAR___S                                     0

#define DBG_TPDM_LSR                              (0x00BB9FB4)
#define   DBG_TPDM_LSR___RWC                        QCSR_REG_RO    
#define   DBG_TPDM_LSR___POR                     0x00000003
#define   DBG_TPDM_LSR__NTT___POR                0x0
#define   DBG_TPDM_LSR__SLK___POR                0x1
#define   DBG_TPDM_LSR__SLI___POR                0x1
#define   DBG_TPDM_LSR__NTT___M                  0x00000004
#define   DBG_TPDM_LSR__NTT___S                                2
#define   DBG_TPDM_LSR__SLK___M                  0x00000002
#define   DBG_TPDM_LSR__SLK___S                                1
#define   DBG_TPDM_LSR__SLI___M                  0x00000001
#define   DBG_TPDM_LSR__SLI___S                                0
#define   DBG_TPDM_LSR___M                       0x00000007   
#define   DBG_TPDM_LSR___S                                     0

#define DBG_TPDM_AUTHSTATUS                       (0x00BB9FB8)
#define   DBG_TPDM_AUTHSTATUS___RWC                 QCSR_REG_RO    
#define   DBG_TPDM_AUTHSTATUS___POR              0x000000AA
#define   DBG_TPDM_AUTHSTATUS__SNID___POR        0x2
#define   DBG_TPDM_AUTHSTATUS__SID___POR         0x2
#define   DBG_TPDM_AUTHSTATUS__NSNID___POR       0x2
#define   DBG_TPDM_AUTHSTATUS__NSID___POR        0x2
#define   DBG_TPDM_AUTHSTATUS__SNID___M          0x000000C0
#define   DBG_TPDM_AUTHSTATUS__SNID___S                        6
#define   DBG_TPDM_AUTHSTATUS__SID___M           0x00000030
#define   DBG_TPDM_AUTHSTATUS__SID___S                         4
#define   DBG_TPDM_AUTHSTATUS__NSNID___M         0x0000000C
#define   DBG_TPDM_AUTHSTATUS__NSNID___S                       2
#define   DBG_TPDM_AUTHSTATUS__NSID___M          0x00000003
#define   DBG_TPDM_AUTHSTATUS__NSID___S                        0
#define   DBG_TPDM_AUTHSTATUS___M                0x000000FF   
#define   DBG_TPDM_AUTHSTATUS___S                              0

#define DBG_TPDM_DEVARCH                          (0x00BB9FBC)
#define   DBG_TPDM_DEVARCH___RWC                    QCSR_REG_RO    
#define   DBG_TPDM_DEVARCH___POR                 0x0E105CDA
#define   DBG_TPDM_DEVARCH__ARCHITECT___POR      0x070
#define   DBG_TPDM_DEVARCH__PRESENT___POR        0x1
#define   DBG_TPDM_DEVARCH__REVISION___POR       0x0
#define   DBG_TPDM_DEVARCH__ARCHID___POR         0x5CDA
#define   DBG_TPDM_DEVARCH__ARCHITECT___M        0xFFE00000
#define   DBG_TPDM_DEVARCH__ARCHITECT___S                     21
#define   DBG_TPDM_DEVARCH__PRESENT___M          0x00100000
#define   DBG_TPDM_DEVARCH__PRESENT___S                       20
#define   DBG_TPDM_DEVARCH__REVISION___M         0x000F0000
#define   DBG_TPDM_DEVARCH__REVISION___S                      16
#define   DBG_TPDM_DEVARCH__ARCHID___M           0x0000FFFF
#define   DBG_TPDM_DEVARCH__ARCHID___S                         0
#define   DBG_TPDM_DEVARCH___M                   0xFFFFFFFF   
#define   DBG_TPDM_DEVARCH___S                                 0

#define DBG_TPDM_DEVID1                           (0x00BB9FC4)
#define   DBG_TPDM_DEVID1___RWC                     QCSR_REG_RO    
#define   DBG_TPDM_DEVID1___POR                  0x00000000
#define   DBG_TPDM_DEVID1__CMB_LIVE___POR        0x0
#define   DBG_TPDM_DEVID1__DSB_LIVE___POR        0x0
#define   DBG_TPDM_DEVID1__CMB_LIVE___M          0x80000000
#define   DBG_TPDM_DEVID1__CMB_LIVE___S                       31
#define   DBG_TPDM_DEVID1__DSB_LIVE___M          0x40000000
#define   DBG_TPDM_DEVID1__DSB_LIVE___S                       30
#define   DBG_TPDM_DEVID1___M                    0xC0000000   
#define   DBG_TPDM_DEVID1___S                                 30

#define DBG_TPDM_DEVID                            (0x00BB9FC8)
#define   DBG_TPDM_DEVID___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_DEVID___POR                   0x15000008
#define   DBG_TPDM_DEVID__TC_LVL_TRIG___POR      0x2
#define   DBG_TPDM_DEVID__BC_LVL_TRIG___POR      0x2
#define   DBG_TPDM_DEVID__BC_GANG___POR          0x2
#define   DBG_TPDM_DEVID__CMB_IN___POR           0x2
#define   DBG_TPDM_DEVID__DSB_ELEM___POR         0x0
#define   DBG_TPDM_DEVID__TC_LVL_TRIG___M        0x18000000
#define   DBG_TPDM_DEVID__TC_LVL_TRIG___S                     27
#define   DBG_TPDM_DEVID__BC_LVL_TRIG___M        0x06000000
#define   DBG_TPDM_DEVID__BC_LVL_TRIG___S                     25
#define   DBG_TPDM_DEVID__BC_GANG___M            0x01800000
#define   DBG_TPDM_DEVID__BC_GANG___S                         23
#define   DBG_TPDM_DEVID__CMB_IN___M             0x0000000C
#define   DBG_TPDM_DEVID__CMB_IN___S                           2
#define   DBG_TPDM_DEVID__DSB_ELEM___M           0x00000002
#define   DBG_TPDM_DEVID__DSB_ELEM___S                         1
#define   DBG_TPDM_DEVID___M                     0x1F80000E   
#define   DBG_TPDM_DEVID___S                                   1

#define DBG_TPDM_DEVTYPE                          (0x00BB9FCC)
#define   DBG_TPDM_DEVTYPE___RWC                    QCSR_REG_RO    
#define   DBG_TPDM_DEVTYPE___POR                 0x00000003
#define   DBG_TPDM_DEVTYPE__SUB___POR            0x0
#define   DBG_TPDM_DEVTYPE__MAJOR___POR          0x3
#define   DBG_TPDM_DEVTYPE__SUB___M              0x000000F0
#define   DBG_TPDM_DEVTYPE__SUB___S                            4
#define   DBG_TPDM_DEVTYPE__MAJOR___M            0x0000000F
#define   DBG_TPDM_DEVTYPE__MAJOR___S                          0
#define   DBG_TPDM_DEVTYPE___M                   0x000000FF   
#define   DBG_TPDM_DEVTYPE___S                                 0

#define DBG_TPDM_PIDR4                            (0x00BB9FD0)
#define   DBG_TPDM_PIDR4___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR4___POR                   0x00000000
#define   DBG_TPDM_PIDR4__SIZE___POR             0x0
#define   DBG_TPDM_PIDR4__DES_2___POR            0x0
#define   DBG_TPDM_PIDR4__SIZE___M               0x000000F0
#define   DBG_TPDM_PIDR4__SIZE___S                             4
#define   DBG_TPDM_PIDR4__DES_2___M              0x0000000F
#define   DBG_TPDM_PIDR4__DES_2___S                            0
#define   DBG_TPDM_PIDR4___M                     0x000000FF   
#define   DBG_TPDM_PIDR4___S                                   0

#define DBG_TPDM_PIDR5                            (0x00BB9FD4)
#define   DBG_TPDM_PIDR5___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR5___POR                   0x00000000
#define   DBG_TPDM_PIDR5__EMPTY___POR            0x00000000
#define   DBG_TPDM_PIDR5__EMPTY___M              0xFFFFFFFF
#define   DBG_TPDM_PIDR5__EMPTY___S                            0
#define   DBG_TPDM_PIDR5___M                     0xFFFFFFFF   
#define   DBG_TPDM_PIDR5___S                                   0

#define DBG_TPDM_PIDR6                            (0x00BB9FD8)
#define   DBG_TPDM_PIDR6___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR6___POR                   0x00000000
#define   DBG_TPDM_PIDR6__EMPTY___POR            0x00000000
#define   DBG_TPDM_PIDR6__EMPTY___M              0xFFFFFFFF
#define   DBG_TPDM_PIDR6__EMPTY___S                            0
#define   DBG_TPDM_PIDR6___M                     0xFFFFFFFF   
#define   DBG_TPDM_PIDR6___S                                   0

#define DBG_TPDM_PIDR7                            (0x00BB9FDC)
#define   DBG_TPDM_PIDR7___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR7___POR                   0x00000000
#define   DBG_TPDM_PIDR7__EMPTY___POR            0x00000000
#define   DBG_TPDM_PIDR7__EMPTY___M              0xFFFFFFFF
#define   DBG_TPDM_PIDR7__EMPTY___S                            0
#define   DBG_TPDM_PIDR7___M                     0xFFFFFFFF   
#define   DBG_TPDM_PIDR7___S                                   0

#define DBG_TPDM_PIDR0                            (0x00BB9FE0)
#define   DBG_TPDM_PIDR0___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR0___POR                   0x00000026
#define   DBG_TPDM_PIDR0__PART_7___POR           0x0
#define   DBG_TPDM_PIDR0__PART_6___POR           0x0
#define   DBG_TPDM_PIDR0__PART_5___POR           0x1
#define   DBG_TPDM_PIDR0__PART_4___POR           0x0
#define   DBG_TPDM_PIDR0__PART_3___POR           0x0
#define   DBG_TPDM_PIDR0__PART_2___POR           0x1
#define   DBG_TPDM_PIDR0__PART_1___POR           0x1
#define   DBG_TPDM_PIDR0__PART_0___POR           0x0
#define   DBG_TPDM_PIDR0__PART_7___M             0x00000080
#define   DBG_TPDM_PIDR0__PART_7___S                           7
#define   DBG_TPDM_PIDR0__PART_6___M             0x00000040
#define   DBG_TPDM_PIDR0__PART_6___S                           6
#define   DBG_TPDM_PIDR0__PART_5___M             0x00000020
#define   DBG_TPDM_PIDR0__PART_5___S                           5
#define   DBG_TPDM_PIDR0__PART_4___M             0x00000010
#define   DBG_TPDM_PIDR0__PART_4___S                           4
#define   DBG_TPDM_PIDR0__PART_3___M             0x00000008
#define   DBG_TPDM_PIDR0__PART_3___S                           3
#define   DBG_TPDM_PIDR0__PART_2___M             0x00000004
#define   DBG_TPDM_PIDR0__PART_2___S                           2
#define   DBG_TPDM_PIDR0__PART_1___M             0x00000002
#define   DBG_TPDM_PIDR0__PART_1___S                           1
#define   DBG_TPDM_PIDR0__PART_0___M             0x00000001
#define   DBG_TPDM_PIDR0__PART_0___S                           0
#define   DBG_TPDM_PIDR0___M                     0x000000FF   
#define   DBG_TPDM_PIDR0___S                                   0

#define DBG_TPDM_PIDR1                            (0x00BB9FE4)
#define   DBG_TPDM_PIDR1___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR1___POR                   0x0000000E
#define   DBG_TPDM_PIDR1__DES_0___POR            0x0
#define   DBG_TPDM_PIDR1__PART_1___POR           0xE
#define   DBG_TPDM_PIDR1__DES_0___M              0x000000F0
#define   DBG_TPDM_PIDR1__DES_0___S                            4
#define   DBG_TPDM_PIDR1__PART_1___M             0x0000000F
#define   DBG_TPDM_PIDR1__PART_1___S                           0
#define   DBG_TPDM_PIDR1___M                     0x000000FF   
#define   DBG_TPDM_PIDR1___S                                   0

#define DBG_TPDM_PIDR2                            (0x00BB9FE8)
#define   DBG_TPDM_PIDR2___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR2___POR                   0x00000018
#define   DBG_TPDM_PIDR2__REVISION___POR         0x1
#define   DBG_TPDM_PIDR2__JEDEC___POR            0x1
#define   DBG_TPDM_PIDR2__DES_1___POR            0x0
#define   DBG_TPDM_PIDR2__REVISION___M           0x000000F0
#define   DBG_TPDM_PIDR2__REVISION___S                         4
#define   DBG_TPDM_PIDR2__JEDEC___M              0x00000008
#define   DBG_TPDM_PIDR2__JEDEC___S                            3
#define   DBG_TPDM_PIDR2__DES_1___M              0x00000007
#define   DBG_TPDM_PIDR2__DES_1___S                            0
#define   DBG_TPDM_PIDR2___M                     0x000000FF   
#define   DBG_TPDM_PIDR2___S                                   0

#define DBG_TPDM_PIDR3                            (0x00BB9FEC)
#define   DBG_TPDM_PIDR3___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_PIDR3___POR                   0x00000000
#define   DBG_TPDM_PIDR3__REVAND___POR           0x0
#define   DBG_TPDM_PIDR3__CMOD___POR             0x0
#define   DBG_TPDM_PIDR3__REVAND___M             0x000000F0
#define   DBG_TPDM_PIDR3__REVAND___S                           4
#define   DBG_TPDM_PIDR3__CMOD___M               0x0000000F
#define   DBG_TPDM_PIDR3__CMOD___S                             0
#define   DBG_TPDM_PIDR3___M                     0x000000FF   
#define   DBG_TPDM_PIDR3___S                                   0

#define DBG_TPDM_CIDR0                            (0x00BB9FF0)
#define   DBG_TPDM_CIDR0___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_CIDR0___POR                   0x0000000D
#define   DBG_TPDM_CIDR0__PRMBL_0___POR          0x0D
#define   DBG_TPDM_CIDR0__PRMBL_0___M            0x000000FF
#define   DBG_TPDM_CIDR0__PRMBL_0___S                          0
#define   DBG_TPDM_CIDR0___M                     0x000000FF   
#define   DBG_TPDM_CIDR0___S                                   0

#define DBG_TPDM_CIDR1                            (0x00BB9FF4)
#define   DBG_TPDM_CIDR1___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_CIDR1___POR                   0x00000090
#define   DBG_TPDM_CIDR1__CLASS___POR            0x9
#define   DBG_TPDM_CIDR1__PRMBL_1___POR          0x0
#define   DBG_TPDM_CIDR1__CLASS___M              0x000000F0
#define   DBG_TPDM_CIDR1__CLASS___S                            4
#define   DBG_TPDM_CIDR1__PRMBL_1___M            0x0000000F
#define   DBG_TPDM_CIDR1__PRMBL_1___S                          0
#define   DBG_TPDM_CIDR1___M                     0x000000FF   
#define   DBG_TPDM_CIDR1___S                                   0

#define DBG_TPDM_CIDR2                            (0x00BB9FF8)
#define   DBG_TPDM_CIDR2___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_CIDR2___POR                   0x00000005
#define   DBG_TPDM_CIDR2__PRMBL_2___POR          0x05
#define   DBG_TPDM_CIDR2__PRMBL_2___M            0x000000FF
#define   DBG_TPDM_CIDR2__PRMBL_2___S                          0
#define   DBG_TPDM_CIDR2___M                     0x000000FF   
#define   DBG_TPDM_CIDR2___S                                   0

#define DBG_TPDM_CIDR3                            (0x00BB9FFC)
#define   DBG_TPDM_CIDR3___RWC                      QCSR_REG_RO    
#define   DBG_TPDM_CIDR3___POR                   0x000000B1
#define   DBG_TPDM_CIDR3__PRMBL_3___POR          0xB1
#define   DBG_TPDM_CIDR3__PRMBL_3___M            0x000000FF
#define   DBG_TPDM_CIDR3__PRMBL_3___S                          0
#define   DBG_TPDM_CIDR3___M                     0x000000FF   
#define   DBG_TPDM_CIDR3___S                                   0

#define DBG_TPDM_GPRn(n)                 (0x00BB9000+0x4*(n))
#define   DBG_TPDM_GPRn_nMIN       0    
#define   DBG_TPDM_GPRn_nMAX       3    
#define   DBG_TPDM_GPRn_ELEM       4    
#define   DBG_TPDM_GPRn___RWC                       QCSR_REG_RW    
#define   DBG_TPDM_GPRn___POR                    0x00000000
#define   DBG_TPDM_GPRn__VAL___POR               0x00000000
#define   DBG_TPDM_GPRn__VAL___M                 0xFFFFFFFF
#define   DBG_TPDM_GPRn__VAL___S                               0
#define   DBG_TPDM_GPRn___M                      0xFFFFFFFF   
#define   DBG_TPDM_GPRn___S                                    0
#define DBG_TPDM_GPR0                             (0x00BB9000)
#define   DBG_TPDM_GPR0___RWC                       QCSR_REG_RW    
#define   DBG_TPDM_GPR0__VAL___M                 0xFFFFFFFF
#define   DBG_TPDM_GPR0__VAL___S                               0
#define DBG_TPDM_GPR1                             (0x00BB9004)
#define   DBG_TPDM_GPR1___RWC                       QCSR_REG_RW    
#define   DBG_TPDM_GPR1__VAL___M                 0xFFFFFFFF
#define   DBG_TPDM_GPR1__VAL___S                               0
#define DBG_TPDM_GPR2                             (0x00BB9008)
#define   DBG_TPDM_GPR2___RWC                       QCSR_REG_RW    
#define   DBG_TPDM_GPR2__VAL___M                 0xFFFFFFFF
#define   DBG_TPDM_GPR2__VAL___S                               0
#define DBG_TPDM_GPR3                             (0x00BB900C)
#define   DBG_TPDM_GPR3___RWC                       QCSR_REG_RW    
#define   DBG_TPDM_GPR3__VAL___M                 0xFFFFFFFF
#define   DBG_TPDM_GPR3__VAL___S                               0

#define DBG_TPDA_CR                               (0x00BBA000)
#define   DBG_TPDA_CR___RWC                         QCSR_REG_RW    
#define   DBG_TPDA_CR___POR                      0x00000000
#define   DBG_TPDA_CR__RFU___POR                 0x000
#define   DBG_TPDA_CR__AVFREQEN___POR            0x0
#define   DBG_TPDA_CR__CMBCHANMODE___POR         0x0
#define   DBG_TPDA_CR__MID___POR                 0x00
#define   DBG_TPDA_CR__ATID___POR                0x00
#define   DBG_TPDA_CR__SRIE___POR                0x0
#define   DBG_TPDA_CR__FLRIE___POR               0x0
#define   DBG_TPDA_CR__FRIE___POR                0x0
#define   DBG_TPDA_CR__FREQTS___POR              0x0
#define   DBG_TPDA_CR__FREQREQ___POR             0x0
#define   DBG_TPDA_CR__FLREQ___POR               0x0
#define   DBG_TPDA_CR__RFU___M                   0xFFC00000
#define   DBG_TPDA_CR__RFU___S                                22
#define   DBG_TPDA_CR__AVFREQEN___M              0x00200000
#define   DBG_TPDA_CR__AVFREQEN___S                           21
#define   DBG_TPDA_CR__CMBCHANMODE___M           0x00100000
#define   DBG_TPDA_CR__CMBCHANMODE___S                        20
#define   DBG_TPDA_CR__MID___M                   0x000FE000
#define   DBG_TPDA_CR__MID___S                                13
#define   DBG_TPDA_CR__ATID___M                  0x00001FC0
#define   DBG_TPDA_CR__ATID___S                                6
#define   DBG_TPDA_CR__SRIE___M                  0x00000020
#define   DBG_TPDA_CR__SRIE___S                                5
#define   DBG_TPDA_CR__FLRIE___M                 0x00000010
#define   DBG_TPDA_CR__FLRIE___S                               4
#define   DBG_TPDA_CR__FRIE___M                  0x00000008
#define   DBG_TPDA_CR__FRIE___S                                3
#define   DBG_TPDA_CR__FREQTS___M                0x00000004
#define   DBG_TPDA_CR__FREQTS___S                              2
#define   DBG_TPDA_CR__FREQREQ___M               0x00000002
#define   DBG_TPDA_CR__FREQREQ___S                             1
#define   DBG_TPDA_CR__FLREQ___M                 0x00000001
#define   DBG_TPDA_CR__FLREQ___S                               0
#define   DBG_TPDA_CR___M                        0xFFFFFFFF   
#define   DBG_TPDA_CR___S                                      0

#define DBG_TPDA_Pn_CR(n)                (0x00BBA004+0x4*(n))
#define   DBG_TPDA_Pn_CR_nMIN      0    
#define   DBG_TPDA_Pn_CR_nMAX      3    
#define   DBG_TPDA_Pn_CR_ELEM      4    
#define   DBG_TPDA_Pn_CR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_Pn_CR___POR                   0x00000000
#define   DBG_TPDA_Pn_CR__RFU___POR              0x000000
#define   DBG_TPDA_Pn_CR__IMPLDEFESIZE___POR     0x0
#define   DBG_TPDA_Pn_CR__DSBESIZE___POR         0x0
#define   DBG_TPDA_Pn_CR__CMBESIZE___POR         0x0
#define   DBG_TPDA_Pn_CR__TCESIZE___POR          0x0
#define   DBG_TPDA_Pn_CR__BCESIZE___POR          0x0
#define   DBG_TPDA_Pn_CR__HOLD___POR             0x0
#define   DBG_TPDA_Pn_CR__E___POR                0x0
#define   DBG_TPDA_Pn_CR__RFU___M                0xFFFFF800
#define   DBG_TPDA_Pn_CR__RFU___S                             11
#define   DBG_TPDA_Pn_CR__IMPLDEFESIZE___M       0x00000600
#define   DBG_TPDA_Pn_CR__IMPLDEFESIZE___S                     9
#define   DBG_TPDA_Pn_CR__DSBESIZE___M           0x00000100
#define   DBG_TPDA_Pn_CR__DSBESIZE___S                         8
#define   DBG_TPDA_Pn_CR__CMBESIZE___M           0x000000C0
#define   DBG_TPDA_Pn_CR__CMBESIZE___S                         6
#define   DBG_TPDA_Pn_CR__TCESIZE___M            0x00000020
#define   DBG_TPDA_Pn_CR__TCESIZE___S                          5
#define   DBG_TPDA_Pn_CR__BCESIZE___M            0x00000010
#define   DBG_TPDA_Pn_CR__BCESIZE___S                          4
#define   DBG_TPDA_Pn_CR__HOLD___M               0x0000000E
#define   DBG_TPDA_Pn_CR__HOLD___S                             1
#define   DBG_TPDA_Pn_CR__E___M                  0x00000001
#define   DBG_TPDA_Pn_CR__E___S                                0
#define   DBG_TPDA_Pn_CR___M                     0xFFFFFFFF   
#define   DBG_TPDA_Pn_CR___S                                   0
#define DBG_TPDA_P0_CR                            (0x00BBA004)
#define   DBG_TPDA_P0_CR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_P0_CR__RFU___M                0xFFFFF800
#define   DBG_TPDA_P0_CR__RFU___S                             11
#define   DBG_TPDA_P0_CR__IMPLDEFESIZE___M       0x00000600
#define   DBG_TPDA_P0_CR__IMPLDEFESIZE___S                     9
#define   DBG_TPDA_P0_CR__DSBESIZE___M           0x00000100
#define   DBG_TPDA_P0_CR__DSBESIZE___S                         8
#define   DBG_TPDA_P0_CR__CMBESIZE___M           0x000000C0
#define   DBG_TPDA_P0_CR__CMBESIZE___S                         6
#define   DBG_TPDA_P0_CR__TCESIZE___M            0x00000020
#define   DBG_TPDA_P0_CR__TCESIZE___S                          5
#define   DBG_TPDA_P0_CR__BCESIZE___M            0x00000010
#define   DBG_TPDA_P0_CR__BCESIZE___S                          4
#define   DBG_TPDA_P0_CR__HOLD___M               0x0000000E
#define   DBG_TPDA_P0_CR__HOLD___S                             1
#define   DBG_TPDA_P0_CR__E___M                  0x00000001
#define   DBG_TPDA_P0_CR__E___S                                0
#define DBG_TPDA_P1_CR                            (0x00BBA008)
#define   DBG_TPDA_P1_CR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_P1_CR__RFU___M                0xFFFFF800
#define   DBG_TPDA_P1_CR__RFU___S                             11
#define   DBG_TPDA_P1_CR__IMPLDEFESIZE___M       0x00000600
#define   DBG_TPDA_P1_CR__IMPLDEFESIZE___S                     9
#define   DBG_TPDA_P1_CR__DSBESIZE___M           0x00000100
#define   DBG_TPDA_P1_CR__DSBESIZE___S                         8
#define   DBG_TPDA_P1_CR__CMBESIZE___M           0x000000C0
#define   DBG_TPDA_P1_CR__CMBESIZE___S                         6
#define   DBG_TPDA_P1_CR__TCESIZE___M            0x00000020
#define   DBG_TPDA_P1_CR__TCESIZE___S                          5
#define   DBG_TPDA_P1_CR__BCESIZE___M            0x00000010
#define   DBG_TPDA_P1_CR__BCESIZE___S                          4
#define   DBG_TPDA_P1_CR__HOLD___M               0x0000000E
#define   DBG_TPDA_P1_CR__HOLD___S                             1
#define   DBG_TPDA_P1_CR__E___M                  0x00000001
#define   DBG_TPDA_P1_CR__E___S                                0
#define DBG_TPDA_P2_CR                            (0x00BBA00C)
#define   DBG_TPDA_P2_CR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_P2_CR__RFU___M                0xFFFFF800
#define   DBG_TPDA_P2_CR__RFU___S                             11
#define   DBG_TPDA_P2_CR__IMPLDEFESIZE___M       0x00000600
#define   DBG_TPDA_P2_CR__IMPLDEFESIZE___S                     9
#define   DBG_TPDA_P2_CR__DSBESIZE___M           0x00000100
#define   DBG_TPDA_P2_CR__DSBESIZE___S                         8
#define   DBG_TPDA_P2_CR__CMBESIZE___M           0x000000C0
#define   DBG_TPDA_P2_CR__CMBESIZE___S                         6
#define   DBG_TPDA_P2_CR__TCESIZE___M            0x00000020
#define   DBG_TPDA_P2_CR__TCESIZE___S                          5
#define   DBG_TPDA_P2_CR__BCESIZE___M            0x00000010
#define   DBG_TPDA_P2_CR__BCESIZE___S                          4
#define   DBG_TPDA_P2_CR__HOLD___M               0x0000000E
#define   DBG_TPDA_P2_CR__HOLD___S                             1
#define   DBG_TPDA_P2_CR__E___M                  0x00000001
#define   DBG_TPDA_P2_CR__E___S                                0
#define DBG_TPDA_P3_CR                            (0x00BBA010)
#define   DBG_TPDA_P3_CR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_P3_CR__RFU___M                0xFFFFF800
#define   DBG_TPDA_P3_CR__RFU___S                             11
#define   DBG_TPDA_P3_CR__IMPLDEFESIZE___M       0x00000600
#define   DBG_TPDA_P3_CR__IMPLDEFESIZE___S                     9
#define   DBG_TPDA_P3_CR__DSBESIZE___M           0x00000100
#define   DBG_TPDA_P3_CR__DSBESIZE___S                         8
#define   DBG_TPDA_P3_CR__CMBESIZE___M           0x000000C0
#define   DBG_TPDA_P3_CR__CMBESIZE___S                         6
#define   DBG_TPDA_P3_CR__TCESIZE___M            0x00000020
#define   DBG_TPDA_P3_CR__TCESIZE___S                          5
#define   DBG_TPDA_P3_CR__BCESIZE___M            0x00000010
#define   DBG_TPDA_P3_CR__BCESIZE___S                          4
#define   DBG_TPDA_P3_CR__HOLD___M               0x0000000E
#define   DBG_TPDA_P3_CR__HOLD___S                             1
#define   DBG_TPDA_P3_CR__E___M                  0x00000001
#define   DBG_TPDA_P3_CR__E___S                                0

#define DBG_TPDA_FPID_CR                          (0x00BBA084)
#define   DBG_TPDA_FPID_CR___RWC                    QCSR_REG_RW    
#define   DBG_TPDA_FPID_CR___POR                 0x00000000
#define   DBG_TPDA_FPID_CR__CID___POR            0x0000
#define   DBG_TPDA_FPID_CR__MID___POR            0x0000
#define   DBG_TPDA_FPID_CR__CID___M              0xFFFF0000
#define   DBG_TPDA_FPID_CR__CID___S                           16
#define   DBG_TPDA_FPID_CR__MID___M              0x0000FFFF
#define   DBG_TPDA_FPID_CR__MID___S                            0
#define   DBG_TPDA_FPID_CR___M                   0xFFFFFFFF   
#define   DBG_TPDA_FPID_CR___S                                 0

#define DBG_TPDA_FREQREQ_VAL                      (0x00BBA088)
#define   DBG_TPDA_FREQREQ_VAL___RWC                QCSR_REG_RW    
#define   DBG_TPDA_FREQREQ_VAL___POR             0x00000000
#define   DBG_TPDA_FREQREQ_VAL__VAL___POR        0x00000000
#define   DBG_TPDA_FREQREQ_VAL__VAL___M          0xFFFFFFFF
#define   DBG_TPDA_FREQREQ_VAL__VAL___S                        0
#define   DBG_TPDA_FREQREQ_VAL___M               0xFFFFFFFF   
#define   DBG_TPDA_FREQREQ_VAL___S                             0

#define DBG_TPDA_SYNCR                            (0x00BBA08C)
#define   DBG_TPDA_SYNCR___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_SYNCR___POR                   0x00000000
#define   DBG_TPDA_SYNCR__RFU___POR              0x00000
#define   DBG_TPDA_SYNCR__MODE___POR             0x0
#define   DBG_TPDA_SYNCR__COUNT___POR            0x000
#define   DBG_TPDA_SYNCR__RFU___M                0xFFFFE000
#define   DBG_TPDA_SYNCR__RFU___S                             13
#define   DBG_TPDA_SYNCR__MODE___M               0x00001000
#define   DBG_TPDA_SYNCR__MODE___S                            12
#define   DBG_TPDA_SYNCR__COUNT___M              0x00000FFF
#define   DBG_TPDA_SYNCR__COUNT___S                            0
#define   DBG_TPDA_SYNCR___M                     0xFFFFFFFF   
#define   DBG_TPDA_SYNCR___S                                   0

#define DBG_TPDA_FLUSH_CR                         (0x00BBA090)
#define   DBG_TPDA_FLUSH_CR___RWC                   QCSR_REG_RW    
#define   DBG_TPDA_FLUSH_CR___POR                0x00000000
#define   DBG_TPDA_FLUSH_CR__REQ___POR           0x00000000
#define   DBG_TPDA_FLUSH_CR__REQ___M             0xFFFFFFFF
#define   DBG_TPDA_FLUSH_CR__REQ___S                           0
#define   DBG_TPDA_FLUSH_CR___M                  0xFFFFFFFF   
#define   DBG_TPDA_FLUSH_CR___S                                0

#define DBG_TPDA_FLUSH_SR                         (0x00BBA094)
#define   DBG_TPDA_FLUSH_SR___RWC                   QCSR_REG_RO    
#define   DBG_TPDA_FLUSH_SR___POR                0x00000000
#define   DBG_TPDA_FLUSH_SR__FLUSHSTAT___POR     0x00000000
#define   DBG_TPDA_FLUSH_SR__FLUSHSTAT___M       0xFFFFFFFF
#define   DBG_TPDA_FLUSH_SR__FLUSHSTAT___S                     0
#define   DBG_TPDA_FLUSH_SR___M                  0xFFFFFFFF   
#define   DBG_TPDA_FLUSH_SR___S                                0

#define DBG_TPDA_FLUSH_ERR                        (0x00BBA098)
#define   DBG_TPDA_FLUSH_ERR___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_FLUSH_ERR___POR               0x00000000
#define   DBG_TPDA_FLUSH_ERR__SYNDROME___POR     0x00000000
#define   DBG_TPDA_FLUSH_ERR__SYNDROME___M       0xFFFFFFFF
#define   DBG_TPDA_FLUSH_ERR__SYNDROME___S                     0
#define   DBG_TPDA_FLUSH_ERR___M                 0xFFFFFFFF   
#define   DBG_TPDA_FLUSH_ERR___S                               0

#define DBG_TPDA_SPARE                            (0x00BBAEFC)
#define   DBG_TPDA_SPARE___RWC                      QCSR_REG_RW    
#define   DBG_TPDA_SPARE___POR                   0x00000000
#define   DBG_TPDA_SPARE__RFU___POR              0x00000000
#define   DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___POR 0x0
#define   DBG_TPDA_SPARE__RFU___M                0xFFFFFFFE
#define   DBG_TPDA_SPARE__RFU___S                              1
#define   DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___M  0x00000001
#define   DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___S                0
#define   DBG_TPDA_SPARE___M                     0xFFFFFFFF   
#define   DBG_TPDA_SPARE___S                                   0

#define DBG_TPDA_ITCTL                            (0x00BBAF00)
#define   DBG_TPDA_ITCTL___RWC                      QCSR_REG_RO    
#define   DBG_TPDA_ITCTL___POR                   0x00000000
#define   DBG_TPDA_ITCTL__RFU___POR              0x00000000
#define   DBG_TPDA_ITCTL__RFU___M                0xFFFFFFFF
#define   DBG_TPDA_ITCTL__RFU___S                              0
#define   DBG_TPDA_ITCTL___M                     0xFFFFFFFF   
#define   DBG_TPDA_ITCTL___S                                   0

#define DBG_TPDA_CLAIMSET                         (0x00BBAFA0)
#define   DBG_TPDA_CLAIMSET___RWC                   QCSR_REG_RO    
#define   DBG_TPDA_CLAIMSET___POR                0x00000000
#define   DBG_TPDA_CLAIMSET__RFU___POR           0x00000000
#define   DBG_TPDA_CLAIMSET__RFU___M             0xFFFFFFFF
#define   DBG_TPDA_CLAIMSET__RFU___S                           0
#define   DBG_TPDA_CLAIMSET___M                  0xFFFFFFFF   
#define   DBG_TPDA_CLAIMSET___S                                0

#define DBG_TPDA_CLAIMCLR                         (0x00BBAFA4)
#define   DBG_TPDA_CLAIMCLR___RWC                   QCSR_REG_RO    
#define   DBG_TPDA_CLAIMCLR___POR                0x00000000
#define   DBG_TPDA_CLAIMCLR__RFU___POR           0x00000000
#define   DBG_TPDA_CLAIMCLR__RFU___M             0xFFFFFFFF
#define   DBG_TPDA_CLAIMCLR__RFU___S                           0
#define   DBG_TPDA_CLAIMCLR___M                  0xFFFFFFFF   
#define   DBG_TPDA_CLAIMCLR___S                                0

#define DBG_TPDA_DEVAFF0                          (0x00BBAFA8)
#define   DBG_TPDA_DEVAFF0___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_DEVAFF0___POR                 0x00000000
#define   DBG_TPDA_DEVAFF0__AFFINITY___POR       0x00000000
#define   DBG_TPDA_DEVAFF0__AFFINITY___M         0xFFFFFFFF
#define   DBG_TPDA_DEVAFF0__AFFINITY___S                       0
#define   DBG_TPDA_DEVAFF0___M                   0xFFFFFFFF   
#define   DBG_TPDA_DEVAFF0___S                                 0

#define DBG_TPDA_DEVAFF1                          (0x00BBAFAC)
#define   DBG_TPDA_DEVAFF1___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_DEVAFF1___POR                 0x00000000
#define   DBG_TPDA_DEVAFF1__AFFINITY___POR       0x00000000
#define   DBG_TPDA_DEVAFF1__AFFINITY___M         0xFFFFFFFF
#define   DBG_TPDA_DEVAFF1__AFFINITY___S                       0
#define   DBG_TPDA_DEVAFF1___M                   0xFFFFFFFF   
#define   DBG_TPDA_DEVAFF1___S                                 0

#define DBG_TPDA_LOCKACCESS                       (0x00BBAFB0)
#define   DBG_TPDA_LOCKACCESS___RWC                 QCSR_REG_WO    
#define   DBG_TPDA_LOCKACCESS__LOCKACCESS___M    0xFFFFFFFF
#define   DBG_TPDA_LOCKACCESS__LOCKACCESS___S                  0
#define   DBG_TPDA_LOCKACCESS___M                0xFFFFFFFF   
#define   DBG_TPDA_LOCKACCESS___S                              0

#define DBG_TPDA_LOCKSTATUS                       (0x00BBAFB4)
#define   DBG_TPDA_LOCKSTATUS___RWC                 QCSR_REG_RO    
#define   DBG_TPDA_LOCKSTATUS___POR              0x00000003
#define   DBG_TPDA_LOCKSTATUS__RFU___POR         0x00000000
#define   DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___POR 0x0
#define   DBG_TPDA_LOCKSTATUS__ACCESS___POR      0x1
#define   DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___POR 0x1
#define   DBG_TPDA_LOCKSTATUS__RFU___M           0xFFFFFFF8
#define   DBG_TPDA_LOCKSTATUS__RFU___S                         3
#define   DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___M 0x00000004
#define   DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___S               2
#define   DBG_TPDA_LOCKSTATUS__ACCESS___M        0x00000002
#define   DBG_TPDA_LOCKSTATUS__ACCESS___S                      1
#define   DBG_TPDA_LOCKSTATUS__ACCESS__LOW                   0x0
#define   DBG_TPDA_LOCKSTATUS__ACCESS__HIGH                  0x1
#define   DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___M  0x00000001
#define   DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___S                0
#define   DBG_TPDA_LOCKSTATUS___M                0xFFFFFFFF   
#define   DBG_TPDA_LOCKSTATUS___S                              0

#define DBG_TPDA_AUTHSTATUS                       (0x00BBAFB8)
#define   DBG_TPDA_AUTHSTATUS___RWC                 QCSR_REG_RO    
#define   DBG_TPDA_AUTHSTATUS___POR              0x00000000
#define   DBG_TPDA_AUTHSTATUS__RFU___POR         0x00000000
#define   DBG_TPDA_AUTHSTATUS__RFU___M           0xFFFFFFFF
#define   DBG_TPDA_AUTHSTATUS__RFU___S                         0
#define   DBG_TPDA_AUTHSTATUS___M                0xFFFFFFFF   
#define   DBG_TPDA_AUTHSTATUS___S                              0

#define DBG_TPDA_DEVARCH                          (0x00BBAFBC)
#define   DBG_TPDA_DEVARCH___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_DEVARCH__ARCHITECT___M        0xFFE00000
#define   DBG_TPDA_DEVARCH__ARCHITECT___S                     21
#define   DBG_TPDA_DEVARCH__PRESENT___M          0x00100000
#define   DBG_TPDA_DEVARCH__PRESENT___S                       20
#define   DBG_TPDA_DEVARCH__REVISION___M         0x000F0000
#define   DBG_TPDA_DEVARCH__REVISION___S                      16
#define   DBG_TPDA_DEVARCH__ARCHID___M           0x0000FFFF
#define   DBG_TPDA_DEVARCH__ARCHID___S                         0
#define   DBG_TPDA_DEVARCH___M                   0xFFFFFFFF   
#define   DBG_TPDA_DEVARCH___S                                 0

#define DBG_TPDA_DEVID2                           (0x00BBAFC0)
#define   DBG_TPDA_DEVID2___RWC                     QCSR_REG_RO    
#define   DBG_TPDA_DEVID2___POR                  0x00000000
#define   DBG_TPDA_DEVID2__DEVID2___POR          0x00000000
#define   DBG_TPDA_DEVID2__DEVID2___M            0xFFFFFFFF
#define   DBG_TPDA_DEVID2__DEVID2___S                          0
#define   DBG_TPDA_DEVID2___M                    0xFFFFFFFF   
#define   DBG_TPDA_DEVID2___S                                  0

#define DBG_TPDA_DEVID1                           (0x00BBAFC4)
#define   DBG_TPDA_DEVID1___RWC                     QCSR_REG_RO    
#define   DBG_TPDA_DEVID1___POR                  0x00000000
#define   DBG_TPDA_DEVID1__DEVID1___POR          0x00000000
#define   DBG_TPDA_DEVID1__DEVID1___M            0xFFFFFFFF
#define   DBG_TPDA_DEVID1__DEVID1___S                          0
#define   DBG_TPDA_DEVID1___M                    0xFFFFFFFF   
#define   DBG_TPDA_DEVID1___S                                  0

#define DBG_TPDA_DEVID                            (0x00BBAFC8)
#define   DBG_TPDA_DEVID___RWC                      QCSR_REG_RO    
#define   DBG_TPDA_DEVID___POR                   0x00000000
#define   DBG_TPDA_DEVID__DEVID___POR            0x00000000
#define   DBG_TPDA_DEVID__DEVID___M              0xFFFFFFFF
#define   DBG_TPDA_DEVID__DEVID___S                            0
#define   DBG_TPDA_DEVID___M                     0xFFFFFFFF   
#define   DBG_TPDA_DEVID___S                                   0

#define DBG_TPDA_DEVTYPE                          (0x00BBAFCC)
#define   DBG_TPDA_DEVTYPE___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_DEVTYPE___POR                 0x00000003
#define   DBG_TPDA_DEVTYPE__RFU___POR            0x000000
#define   DBG_TPDA_DEVTYPE__SUBTYPE___POR        0x0
#define   DBG_TPDA_DEVTYPE__MAJTYPE___POR        0x3
#define   DBG_TPDA_DEVTYPE__RFU___M              0xFFFFFF00
#define   DBG_TPDA_DEVTYPE__RFU___S                            8
#define   DBG_TPDA_DEVTYPE__SUBTYPE___M          0x000000F0
#define   DBG_TPDA_DEVTYPE__SUBTYPE___S                        4
#define   DBG_TPDA_DEVTYPE__MAJTYPE___M          0x0000000F
#define   DBG_TPDA_DEVTYPE__MAJTYPE___S                        0
#define   DBG_TPDA_DEVTYPE___M                   0xFFFFFFFF   
#define   DBG_TPDA_DEVTYPE___S                                 0

#define DBG_TPDA_PERIPHID4                        (0x00BBAFD0)
#define   DBG_TPDA_PERIPHID4___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID4__RFU___M            0xFFFFFF00
#define   DBG_TPDA_PERIPHID4__RFU___S                          8
#define   DBG_TPDA_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_TPDA_PERIPHID4__FIELD_4KB_COUNT___S               4
#define   DBG_TPDA_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_TPDA_PERIPHID4__JEP106_CONTINUATION___S               0
#define   DBG_TPDA_PERIPHID4___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID4___S                               0

#define DBG_TPDA_PERIPHID5                        (0x00BBAFD4)
#define   DBG_TPDA_PERIPHID5___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID5___POR               0x00000000
#define   DBG_TPDA_PERIPHID5__RFU___POR          0x00000000
#define   DBG_TPDA_PERIPHID5__RFU___M            0xFFFFFFFF
#define   DBG_TPDA_PERIPHID5__RFU___S                          0
#define   DBG_TPDA_PERIPHID5___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID5___S                               0

#define DBG_TPDA_PERIPHID6                        (0x00BBAFD8)
#define   DBG_TPDA_PERIPHID6___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID6___POR               0x00000000
#define   DBG_TPDA_PERIPHID6__RFU___POR          0x00000000
#define   DBG_TPDA_PERIPHID6__RFU___M            0xFFFFFFFF
#define   DBG_TPDA_PERIPHID6__RFU___S                          0
#define   DBG_TPDA_PERIPHID6___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID6___S                               0

#define DBG_TPDA_PERIPHID7                        (0x00BBAFDC)
#define   DBG_TPDA_PERIPHID7___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID7___POR               0x00000000
#define   DBG_TPDA_PERIPHID7__RFU___POR          0x00000000
#define   DBG_TPDA_PERIPHID7__RFU___M            0xFFFFFFFF
#define   DBG_TPDA_PERIPHID7__RFU___S                          0
#define   DBG_TPDA_PERIPHID7___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID7___S                               0

#define DBG_TPDA_PERIPHID0                        (0x00BBAFE0)
#define   DBG_TPDA_PERIPHID0___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID0___POR               0x00000003
#define   DBG_TPDA_PERIPHID0__RFU___POR          0x000000
#define   DBG_TPDA_PERIPHID0__PARTNUM___POR      0x03
#define   DBG_TPDA_PERIPHID0__RFU___M            0xFFFFFF00
#define   DBG_TPDA_PERIPHID0__RFU___S                          8
#define   DBG_TPDA_PERIPHID0__PARTNUM___M        0x000000FF
#define   DBG_TPDA_PERIPHID0__PARTNUM___S                      0
#define   DBG_TPDA_PERIPHID0___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID0___S                               0

#define DBG_TPDA_PERIPHID1                        (0x00BBAFE4)
#define   DBG_TPDA_PERIPHID1___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID1__RFU___M            0xFFFFFF00
#define   DBG_TPDA_PERIPHID1__RFU___S                          8
#define   DBG_TPDA_PERIPHID1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_TPDA_PERIPHID1__JEP106_IDENTITY_3_0___S               4
#define   DBG_TPDA_PERIPHID1__PARTNUM___M        0x0000000F
#define   DBG_TPDA_PERIPHID1__PARTNUM___S                      0
#define   DBG_TPDA_PERIPHID1___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID1___S                               0

#define DBG_TPDA_PERIPHID2                        (0x00BBAFE8)
#define   DBG_TPDA_PERIPHID2___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID2__RFU___M            0xFFFFFF00
#define   DBG_TPDA_PERIPHID2__RFU___S                          8
#define   DBG_TPDA_PERIPHID2__MAJREV___M         0x000000F0
#define   DBG_TPDA_PERIPHID2__MAJREV___S                       4
#define   DBG_TPDA_PERIPHID2__JEDEC___M          0x00000008
#define   DBG_TPDA_PERIPHID2__JEDEC___S                        3
#define   DBG_TPDA_PERIPHID2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_TPDA_PERIPHID2__JEP106_IDENTITY_6_4___S               0
#define   DBG_TPDA_PERIPHID2___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID2___S                               0

#define DBG_TPDA_PERIPHID3                        (0x00BBAFEC)
#define   DBG_TPDA_PERIPHID3___RWC                  QCSR_REG_RO    
#define   DBG_TPDA_PERIPHID3___POR               0x00000000
#define   DBG_TPDA_PERIPHID3__RFU___POR          0x000000
#define   DBG_TPDA_PERIPHID3__REV_AND___POR      0x0
#define   DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_TPDA_PERIPHID3__RFU___M            0xFFFFFF00
#define   DBG_TPDA_PERIPHID3__RFU___S                          8
#define   DBG_TPDA_PERIPHID3__REV_AND___M        0x000000F0
#define   DBG_TPDA_PERIPHID3__REV_AND___S                      4
#define   DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___S               0
#define   DBG_TPDA_PERIPHID3___M                 0xFFFFFFFF   
#define   DBG_TPDA_PERIPHID3___S                               0

#define DBG_TPDA_COMPID0                          (0x00BBAFF0)
#define   DBG_TPDA_COMPID0___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_COMPID0___POR                 0x0000000D
#define   DBG_TPDA_COMPID0__RFU___POR            0x000000
#define   DBG_TPDA_COMPID0__PREAMBLE_7_0___POR   0x0D
#define   DBG_TPDA_COMPID0__RFU___M              0xFFFFFF00
#define   DBG_TPDA_COMPID0__RFU___S                            8
#define   DBG_TPDA_COMPID0__PREAMBLE_7_0___M     0x000000FF
#define   DBG_TPDA_COMPID0__PREAMBLE_7_0___S                   0
#define   DBG_TPDA_COMPID0___M                   0xFFFFFFFF   
#define   DBG_TPDA_COMPID0___S                                 0

#define DBG_TPDA_COMPID1                          (0x00BBAFF4)
#define   DBG_TPDA_COMPID1___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_COMPID1___POR                 0x00000090
#define   DBG_TPDA_COMPID1__RFU___POR            0x000000
#define   DBG_TPDA_COMPID1__PREAMBLE_15_12___POR 0x9
#define   DBG_TPDA_COMPID1__PREAMBLE_11_8___POR  0x0
#define   DBG_TPDA_COMPID1__RFU___M              0xFFFFFF00
#define   DBG_TPDA_COMPID1__RFU___S                            8
#define   DBG_TPDA_COMPID1__PREAMBLE_15_12___M   0x000000F0
#define   DBG_TPDA_COMPID1__PREAMBLE_15_12___S                 4
#define   DBG_TPDA_COMPID1__PREAMBLE_11_8___M    0x0000000F
#define   DBG_TPDA_COMPID1__PREAMBLE_11_8___S                  0
#define   DBG_TPDA_COMPID1___M                   0xFFFFFFFF   
#define   DBG_TPDA_COMPID1___S                                 0

#define DBG_TPDA_COMPID2                          (0x00BBAFF8)
#define   DBG_TPDA_COMPID2___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_COMPID2___POR                 0x00000005
#define   DBG_TPDA_COMPID2__RFU___POR            0x000000
#define   DBG_TPDA_COMPID2__PREAMBLE_23_16___POR 0x05
#define   DBG_TPDA_COMPID2__RFU___M              0xFFFFFF00
#define   DBG_TPDA_COMPID2__RFU___S                            8
#define   DBG_TPDA_COMPID2__PREAMBLE_23_16___M   0x000000FF
#define   DBG_TPDA_COMPID2__PREAMBLE_23_16___S                 0
#define   DBG_TPDA_COMPID2___M                   0xFFFFFFFF   
#define   DBG_TPDA_COMPID2___S                                 0

#define DBG_TPDA_COMPID3                          (0x00BBAFFC)
#define   DBG_TPDA_COMPID3___RWC                    QCSR_REG_RO    
#define   DBG_TPDA_COMPID3___POR                 0x000000B1
#define   DBG_TPDA_COMPID3__RFU___POR            0x000000
#define   DBG_TPDA_COMPID3__PREAMBLE_31_24___POR 0xB1
#define   DBG_TPDA_COMPID3__RFU___M              0xFFFFFF00
#define   DBG_TPDA_COMPID3__RFU___S                            8
#define   DBG_TPDA_COMPID3__PREAMBLE_31_24___M   0x000000FF
#define   DBG_TPDA_COMPID3__PREAMBLE_31_24___S                 0
#define   DBG_TPDA_COMPID3___M                   0xFFFFFFFF   
#define   DBG_TPDA_COMPID3___S                                 0

#define DBG_CTRL_REG                              (0x00BBB000)
#define   DBG_CTRL_REG___RWC                        QCSR_REG_RW    
#define   DBG_CTRL_REG___POR                     0x00000300
#define   DBG_CTRL_REG__HT___POR                 0x3
#define   DBG_CTRL_REG__ENS7___POR               0x0
#define   DBG_CTRL_REG__ENS6___POR               0x0
#define   DBG_CTRL_REG__ENS5___POR               0x0
#define   DBG_CTRL_REG__ENS4___POR               0x0
#define   DBG_CTRL_REG__ENS3___POR               0x0
#define   DBG_CTRL_REG__ENS2___POR               0x0
#define   DBG_CTRL_REG__ENS1___POR               0x0
#define   DBG_CTRL_REG__ENS0___POR               0x0
#define   DBG_CTRL_REG__HT___M                   0x00000F00
#define   DBG_CTRL_REG__HT___S                                 8
#define   DBG_CTRL_REG__HT__HT_0X0                           0x0
#define   DBG_CTRL_REG__HT__HT_0X1                           0x1
#define   DBG_CTRL_REG__HT__HT_0X2                           0x2
#define   DBG_CTRL_REG__HT__HT_0X3                           0x3
#define   DBG_CTRL_REG__HT__HT_0X4                           0x4
#define   DBG_CTRL_REG__HT__HT_0X5                           0x5
#define   DBG_CTRL_REG__HT__HT_0X6                           0x6
#define   DBG_CTRL_REG__HT__HT_0X7                           0x7
#define   DBG_CTRL_REG__HT__HT_0X8                           0x8
#define   DBG_CTRL_REG__HT__HT_0X9                           0x9
#define   DBG_CTRL_REG__HT__HT_0XA                           0xA
#define   DBG_CTRL_REG__HT__HT_0XB                           0xB
#define   DBG_CTRL_REG__HT__HT_0XC                           0xC
#define   DBG_CTRL_REG__HT__HT_0XD                           0xD
#define   DBG_CTRL_REG__HT__HT_0XE                           0xE
#define   DBG_CTRL_REG__ENS7___M                 0x00000080
#define   DBG_CTRL_REG__ENS7___S                               7
#define   DBG_CTRL_REG__ENS7__ENS7_0                         0x0
#define   DBG_CTRL_REG__ENS7__ENS7_1                         0x1
#define   DBG_CTRL_REG__ENS6___M                 0x00000040
#define   DBG_CTRL_REG__ENS6___S                               6
#define   DBG_CTRL_REG__ENS6__ENS6_0                         0x0
#define   DBG_CTRL_REG__ENS6__ENS6_1                         0x1
#define   DBG_CTRL_REG__ENS5___M                 0x00000020
#define   DBG_CTRL_REG__ENS5___S                               5
#define   DBG_CTRL_REG__ENS5__ENS5_0                         0x0
#define   DBG_CTRL_REG__ENS5__ENS5_1                         0x1
#define   DBG_CTRL_REG__ENS4___M                 0x00000010
#define   DBG_CTRL_REG__ENS4___S                               4
#define   DBG_CTRL_REG__ENS4__ENS4_0                         0x0
#define   DBG_CTRL_REG__ENS4__ENS4_1                         0x1
#define   DBG_CTRL_REG__ENS3___M                 0x00000008
#define   DBG_CTRL_REG__ENS3___S                               3
#define   DBG_CTRL_REG__ENS3__ENS3_0                         0x0
#define   DBG_CTRL_REG__ENS3__ENS3_1                         0x1
#define   DBG_CTRL_REG__ENS2___M                 0x00000004
#define   DBG_CTRL_REG__ENS2___S                               2
#define   DBG_CTRL_REG__ENS2__ENS2_0                         0x0
#define   DBG_CTRL_REG__ENS2__ENS2_1                         0x1
#define   DBG_CTRL_REG__ENS1___M                 0x00000002
#define   DBG_CTRL_REG__ENS1___S                               1
#define   DBG_CTRL_REG__ENS1__ENS1_0                         0x0
#define   DBG_CTRL_REG__ENS1__ENS1_1                         0x1
#define   DBG_CTRL_REG__ENS0___M                 0x00000001
#define   DBG_CTRL_REG__ENS0___S                               0
#define   DBG_CTRL_REG__ENS0__ENS0_0                         0x0
#define   DBG_CTRL_REG__ENS0__ENS0_1                         0x1
#define   DBG_CTRL_REG___M                       0x00000FFF   
#define   DBG_CTRL_REG___S                                     0

#define DBG_PRIORITY_CTRL_REG                     (0x00BBB004)
#define   DBG_PRIORITY_CTRL_REG___RWC               QCSR_REG_RW    
#define   DBG_PRIORITY_CTRL_REG___POR            0x00000000
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0___POR  0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7___M    0x00E00000
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7___S                 21
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6___M    0x001C0000
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6___S                 18
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5___M    0x00038000
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5___S                 15
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4___M    0x00007000
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4___S                 12
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3___M    0x00000E00
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3___S                  9
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2___M    0x000001C0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2___S                  6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1___M    0x00000038
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1___S                  3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0___M    0x00000007
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0___S                  0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_PRIORITY_CTRL_REG___M              0x00FFFFFF   
#define   DBG_PRIORITY_CTRL_REG___S                            0

#define DBG_ITATBDATA0                            (0x00BBBEEC)
#define   DBG_ITATBDATA0___RWC                      QCSR_REG_RW    
#define   DBG_ITATBDATA0___POR                   0x00000000
#define   DBG_ITATBDATA0__ATDATA127___POR        0x0
#define   DBG_ITATBDATA0__ATDATA119___POR        0x0
#define   DBG_ITATBDATA0__ATDATA111___POR        0x0
#define   DBG_ITATBDATA0__ATDATA103___POR        0x0
#define   DBG_ITATBDATA0__ATDATA95___POR         0x0
#define   DBG_ITATBDATA0__ATDATA87___POR         0x0
#define   DBG_ITATBDATA0__ATDATA79___POR         0x0
#define   DBG_ITATBDATA0__ATDATA71___POR         0x0
#define   DBG_ITATBDATA0__ATDATA63___POR         0x0
#define   DBG_ITATBDATA0__ATDATA55___POR         0x0
#define   DBG_ITATBDATA0__ATDATA47___POR         0x0
#define   DBG_ITATBDATA0__ATDATA39___POR         0x0
#define   DBG_ITATBDATA0__ATDATA31___POR         0x0
#define   DBG_ITATBDATA0__ATDATAM23___POR        0x0
#define   DBG_ITATBDATA0__ATDATA15___POR         0x0
#define   DBG_ITATBDATA0__ATDATA7___POR          0x0
#define   DBG_ITATBDATA0__ATDATA0___POR          0x0
#define   DBG_ITATBDATA0__ATDATA127___M          0x00010000
#define   DBG_ITATBDATA0__ATDATA127___S                       16
#define   DBG_ITATBDATA0__ATDATA127__ATDATA127_0             0x0
#define   DBG_ITATBDATA0__ATDATA127__ATDATA127_1             0x1
#define   DBG_ITATBDATA0__ATDATA119___M          0x00008000
#define   DBG_ITATBDATA0__ATDATA119___S                       15
#define   DBG_ITATBDATA0__ATDATA119__ATDATA119_0             0x0
#define   DBG_ITATBDATA0__ATDATA119__ATDATA119_1             0x1
#define   DBG_ITATBDATA0__ATDATA111___M          0x00004000
#define   DBG_ITATBDATA0__ATDATA111___S                       14
#define   DBG_ITATBDATA0__ATDATA111__ATDATA111_0             0x0
#define   DBG_ITATBDATA0__ATDATA111__ATDATA111_1             0x1
#define   DBG_ITATBDATA0__ATDATA103___M          0x00002000
#define   DBG_ITATBDATA0__ATDATA103___S                       13
#define   DBG_ITATBDATA0__ATDATA103__ATDATA103_0             0x0
#define   DBG_ITATBDATA0__ATDATA103__ATDATA103_1             0x1
#define   DBG_ITATBDATA0__ATDATA95___M           0x00001000
#define   DBG_ITATBDATA0__ATDATA95___S                        12
#define   DBG_ITATBDATA0__ATDATA95__ATDATA95_0               0x0
#define   DBG_ITATBDATA0__ATDATA95__ATDATA95_1               0x1
#define   DBG_ITATBDATA0__ATDATA87___M           0x00000800
#define   DBG_ITATBDATA0__ATDATA87___S                        11
#define   DBG_ITATBDATA0__ATDATA87__ATDATA87_0               0x0
#define   DBG_ITATBDATA0__ATDATA87__ATDATA87_1               0x1
#define   DBG_ITATBDATA0__ATDATA79___M           0x00000400
#define   DBG_ITATBDATA0__ATDATA79___S                        10
#define   DBG_ITATBDATA0__ATDATA79__ATDATA79_0               0x0
#define   DBG_ITATBDATA0__ATDATA79__ATDATA79_1               0x1
#define   DBG_ITATBDATA0__ATDATA71___M           0x00000200
#define   DBG_ITATBDATA0__ATDATA71___S                         9
#define   DBG_ITATBDATA0__ATDATA71__ATDATA71_0               0x0
#define   DBG_ITATBDATA0__ATDATA71__ATDATA71_1               0x1
#define   DBG_ITATBDATA0__ATDATA63___M           0x00000100
#define   DBG_ITATBDATA0__ATDATA63___S                         8
#define   DBG_ITATBDATA0__ATDATA63__ATDATA63_0               0x0
#define   DBG_ITATBDATA0__ATDATA63__ATDATA63_1               0x1
#define   DBG_ITATBDATA0__ATDATA55___M           0x00000080
#define   DBG_ITATBDATA0__ATDATA55___S                         7
#define   DBG_ITATBDATA0__ATDATA55__ATDATA55_0               0x0
#define   DBG_ITATBDATA0__ATDATA55__ATDATA55_1               0x1
#define   DBG_ITATBDATA0__ATDATA47___M           0x00000040
#define   DBG_ITATBDATA0__ATDATA47___S                         6
#define   DBG_ITATBDATA0__ATDATA47__ATDATA47_0               0x0
#define   DBG_ITATBDATA0__ATDATA47__ATDATA47_1               0x1
#define   DBG_ITATBDATA0__ATDATA39___M           0x00000020
#define   DBG_ITATBDATA0__ATDATA39___S                         5
#define   DBG_ITATBDATA0__ATDATA39__ATDATA39_0               0x0
#define   DBG_ITATBDATA0__ATDATA39__ATDATA39_1               0x1
#define   DBG_ITATBDATA0__ATDATA31___M           0x00000010
#define   DBG_ITATBDATA0__ATDATA31___S                         4
#define   DBG_ITATBDATA0__ATDATA31__ATDATA31_0               0x0
#define   DBG_ITATBDATA0__ATDATA31__ATDATA31_1               0x1
#define   DBG_ITATBDATA0__ATDATAM23___M          0x00000008
#define   DBG_ITATBDATA0__ATDATAM23___S                        3
#define   DBG_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_ITATBDATA0__ATDATA15___M           0x00000004
#define   DBG_ITATBDATA0__ATDATA15___S                         2
#define   DBG_ITATBDATA0__ATDATA15__ATDATA15_0               0x0
#define   DBG_ITATBDATA0__ATDATA15__ATDATA15_1               0x1
#define   DBG_ITATBDATA0__ATDATA7___M            0x00000002
#define   DBG_ITATBDATA0__ATDATA7___S                          1
#define   DBG_ITATBDATA0__ATDATA7__ATDATA7_0                 0x0
#define   DBG_ITATBDATA0__ATDATA7__ATDATA7_1                 0x1
#define   DBG_ITATBDATA0__ATDATA0___M            0x00000001
#define   DBG_ITATBDATA0__ATDATA0___S                          0
#define   DBG_ITATBDATA0__ATDATA0__ATDATA0_0                 0x0
#define   DBG_ITATBDATA0__ATDATA0__ATDATA0_1                 0x1
#define   DBG_ITATBDATA0___M                     0x0001FFFF   
#define   DBG_ITATBDATA0___S                                   0

#define DBG_ITATBCTR2                             (0x00BBBEF0)
#define   DBG_ITATBCTR2___RWC                       QCSR_REG_RW    
#define   DBG_ITATBCTR2___POR                    0x00000000
#define   DBG_ITATBCTR2__AFVALID___POR           0x0
#define   DBG_ITATBCTR2__ATREADY___POR           0x0
#define   DBG_ITATBCTR2__AFVALID___M             0x00000002
#define   DBG_ITATBCTR2__AFVALID___S                           1
#define   DBG_ITATBCTR2__AFVALID__AFVALID_0                  0x0
#define   DBG_ITATBCTR2__AFVALID__AFVALID_1                  0x1
#define   DBG_ITATBCTR2__ATREADY___M             0x00000001
#define   DBG_ITATBCTR2__ATREADY___S                           0
#define   DBG_ITATBCTR2__ATREADY__ATREADY_0                  0x0
#define   DBG_ITATBCTR2__ATREADY__ATREADY_1                  0x1
#define   DBG_ITATBCTR2___M                      0x00000003   
#define   DBG_ITATBCTR2___S                                    0

#define DBG_ITATBCTR1                             (0x00BBBEF4)
#define   DBG_ITATBCTR1___RWC                       QCSR_REG_RW    
#define   DBG_ITATBCTR1__ATID___M                0x0000007F
#define   DBG_ITATBCTR1__ATID___S                              0
#define   DBG_ITATBCTR1___M                      0x0000007F   
#define   DBG_ITATBCTR1___S                                    0

#define DBG_ITATBCTR0                             (0x00BBBEF8)
#define   DBG_ITATBCTR0___RWC                       QCSR_REG_RW    
#define   DBG_ITATBCTR0___POR                    0x00000000
#define   DBG_ITATBCTR0__ATBYTES___POR           0x0
#define   DBG_ITATBCTR0__AFREADY___POR           0x0
#define   DBG_ITATBCTR0__ATVALID___POR           0x0
#define   DBG_ITATBCTR0__ATBYTES___M             0x00000F00
#define   DBG_ITATBCTR0__ATBYTES___S                           8
#define   DBG_ITATBCTR0__ATBYTES__ATBYTES_0                  0x0
#define   DBG_ITATBCTR0__ATBYTES__ATBYTES_1                  0x1
#define   DBG_ITATBCTR0__AFREADY___M             0x00000002
#define   DBG_ITATBCTR0__AFREADY___S                           1
#define   DBG_ITATBCTR0__AFREADY__AFREADY_0                  0x0
#define   DBG_ITATBCTR0__AFREADY__AFREADY_1                  0x1
#define   DBG_ITATBCTR0__ATVALID___M             0x00000001
#define   DBG_ITATBCTR0__ATVALID___S                           0
#define   DBG_ITATBCTR0__ATVALID__ATVALID_0                  0x0
#define   DBG_ITATBCTR0__ATVALID__ATVALID_1                  0x1
#define   DBG_ITATBCTR0___M                      0x00000F03   
#define   DBG_ITATBCTR0___S                                    0

#define DBG_ITCTRL                                (0x00BBBF00)
#define   DBG_ITCTRL___RWC                          QCSR_REG_RW    
#define   DBG_ITCTRL___POR                       0x00000000
#define   DBG_ITCTRL__INTEGRATION_MODE___POR     0x0
#define   DBG_ITCTRL__INTEGRATION_MODE___M       0x00000001
#define   DBG_ITCTRL__INTEGRATION_MODE___S                     0
#define   DBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_ITCTRL___M                         0x00000001   
#define   DBG_ITCTRL___S                                       0

#define DBG_CLAIMSET                              (0x00BBBFA0)
#define   DBG_CLAIMSET___RWC                        QCSR_REG_RW    
#define   DBG_CLAIMSET___POR                     0x0000000F
#define   DBG_CLAIMSET__CLAIMSET___POR           0xF
#define   DBG_CLAIMSET__CLAIMSET___M             0x0000000F
#define   DBG_CLAIMSET__CLAIMSET___S                           0
#define   DBG_CLAIMSET__CLAIMSET__CLAIMSET_0XF               0xF
#define   DBG_CLAIMSET___M                       0x0000000F   
#define   DBG_CLAIMSET___S                                     0

#define DBG_CLAIMCLR                              (0x00BBBFA4)
#define   DBG_CLAIMCLR___RWC                        QCSR_REG_RW    
#define   DBG_CLAIMCLR___POR                     0x00000000
#define   DBG_CLAIMCLR__CLAIMCLR___POR           0x0
#define   DBG_CLAIMCLR__CLAIMCLR___M             0x0000000F
#define   DBG_CLAIMCLR__CLAIMCLR___S                           0
#define   DBG_CLAIMCLR___M                       0x0000000F   
#define   DBG_CLAIMCLR___S                                     0

#define DBG_LOCKACCESS                            (0x00BBBFB0)
#define   DBG_LOCKACCESS___RWC                      QCSR_REG_WO    
#define   DBG_LOCKACCESS__KEY___M                0xFFFFFFFF
#define   DBG_LOCKACCESS__KEY___S                              0
#define   DBG_LOCKACCESS__KEY__KEY_0XC5ACCE55         0xC5ACCE55
#define   DBG_LOCKACCESS__KEY__KEY_0XDEADBEEF         0xDEADBEEF
#define   DBG_LOCKACCESS___M                     0xFFFFFFFF   
#define   DBG_LOCKACCESS___S                                   0

#define DBG_LOCKSTATUS                            (0x00BBBFB4)
#define   DBG_LOCKSTATUS___RWC                      QCSR_REG_RO    
#define   DBG_LOCKSTATUS___POR                   0x00000003
#define   DBG_LOCKSTATUS__NTT___POR              0x0
#define   DBG_LOCKSTATUS__SLK___POR              0x1
#define   DBG_LOCKSTATUS__SLI___POR              0x1
#define   DBG_LOCKSTATUS__NTT___M                0x00000004
#define   DBG_LOCKSTATUS__NTT___S                              2
#define   DBG_LOCKSTATUS__NTT__NTT_0X0                       0x0
#define   DBG_LOCKSTATUS__SLK___M                0x00000002
#define   DBG_LOCKSTATUS__SLK___S                              1
#define   DBG_LOCKSTATUS__SLK__SLK_0X0                       0x0
#define   DBG_LOCKSTATUS__SLK__SLK_0X1                       0x1
#define   DBG_LOCKSTATUS__SLI___M                0x00000001
#define   DBG_LOCKSTATUS__SLI___S                              0
#define   DBG_LOCKSTATUS__SLI__SLI_0X0                       0x0
#define   DBG_LOCKSTATUS__SLI__SLI_0X1                       0x1
#define   DBG_LOCKSTATUS___M                     0x00000007   
#define   DBG_LOCKSTATUS___S                                   0

#define DBG_AUTHSTATUS                            (0x00BBBFB8)
#define   DBG_AUTHSTATUS___RWC                      QCSR_REG_RO    
#define   DBG_AUTHSTATUS___POR                   0x00000000
#define   DBG_AUTHSTATUS__SNID___POR             0x0
#define   DBG_AUTHSTATUS__SID___POR              0x0
#define   DBG_AUTHSTATUS__NSNID___POR            0x0
#define   DBG_AUTHSTATUS__NSID___POR             0x0
#define   DBG_AUTHSTATUS__SNID___M               0x000000C0
#define   DBG_AUTHSTATUS__SNID___S                             6
#define   DBG_AUTHSTATUS__SNID__SNID_0X0                     0x0
#define   DBG_AUTHSTATUS__SID___M                0x00000030
#define   DBG_AUTHSTATUS__SID___S                              4
#define   DBG_AUTHSTATUS__SID__SID_0X0                       0x0
#define   DBG_AUTHSTATUS__NSNID___M              0x0000000C
#define   DBG_AUTHSTATUS__NSNID___S                            2
#define   DBG_AUTHSTATUS__NSNID__NSNID_0X0                   0x0
#define   DBG_AUTHSTATUS__NSID___M               0x00000003
#define   DBG_AUTHSTATUS__NSID___S                             0
#define   DBG_AUTHSTATUS__NSID__NSID_0X0                     0x0
#define   DBG_AUTHSTATUS___M                     0x000000FF   
#define   DBG_AUTHSTATUS___S                                   0

#define DBG_DEVID                                 (0x00BBBFC8)
#define   DBG_DEVID___RWC                           QCSR_REG_RO    
#define   DBG_DEVID___POR                        0x00000038
#define   DBG_DEVID__SCHEME___POR                0x3
#define   DBG_DEVID__PORTCOUNT___POR             0x8
#define   DBG_DEVID__SCHEME___M                  0x000000F0
#define   DBG_DEVID__SCHEME___S                                4
#define   DBG_DEVID__SCHEME__SCHEME_0X3                      0x3
#define   DBG_DEVID__PORTCOUNT___M               0x0000000F
#define   DBG_DEVID__PORTCOUNT___S                             0
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X2                0x2
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X3                0x3
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X4                0x4
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X5                0x5
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X6                0x6
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X7                0x7
#define   DBG_DEVID__PORTCOUNT__PORTCOUNT_0X8                0x8
#define   DBG_DEVID___M                          0x000000FF   
#define   DBG_DEVID___S                                        0

#define DBG_DEVTYPE                               (0x00BBBFCC)
#define   DBG_DEVTYPE___RWC                         QCSR_REG_RO    
#define   DBG_DEVTYPE___POR                      0x00000012
#define   DBG_DEVTYPE__SUB_TYPE___POR            0x1
#define   DBG_DEVTYPE__MAJOR_TYPE___POR          0x2
#define   DBG_DEVTYPE__SUB_TYPE___M              0x000000F0
#define   DBG_DEVTYPE__SUB_TYPE___S                            4
#define   DBG_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1                0x1
#define   DBG_DEVTYPE__MAJOR_TYPE___M            0x0000000F
#define   DBG_DEVTYPE__MAJOR_TYPE___S                          0
#define   DBG_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_DEVTYPE___M                        0x000000FF   
#define   DBG_DEVTYPE___S                                      0

#define DBG_PIDR0                                 (0x00BBBFE0)
#define   DBG_PIDR0___RWC                           QCSR_REG_RO    
#define   DBG_PIDR0___POR                        0x00000008
#define   DBG_PIDR0__PART_NUMBER_BITS7TO0___POR  0x08
#define   DBG_PIDR0__PART_NUMBER_BITS7TO0___M    0x000000FF
#define   DBG_PIDR0__PART_NUMBER_BITS7TO0___S                  0
#define   DBG_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_PIDR0___M                          0x000000FF   
#define   DBG_PIDR0___S                                        0

#define DBG_PIDR1                                 (0x00BBBFE4)
#define   DBG_PIDR1___RWC                           QCSR_REG_RO    
#define   DBG_PIDR1___POR                        0x000000B9
#define   DBG_PIDR1__JEP106_BITS3TO0___POR       0xB
#define   DBG_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_PIDR1__JEP106_BITS3TO0___M         0x000000F0
#define   DBG_PIDR1__JEP106_BITS3TO0___S                       4
#define   DBG_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_PIDR1__PART_NUMBER_BITS11TO8___M   0x0000000F
#define   DBG_PIDR1__PART_NUMBER_BITS11TO8___S                 0
#define   DBG_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_PIDR1___M                          0x000000FF   
#define   DBG_PIDR1___S                                        0

#define DBG_PIDR2                                 (0x00BBBFE8)
#define   DBG_PIDR2___RWC                           QCSR_REG_RO    
#define   DBG_PIDR2___POR                        0x0000003B
#define   DBG_PIDR2__REVISION___POR              0x3
#define   DBG_PIDR2__JEDEC___POR                 0x1
#define   DBG_PIDR2__JEP106_BITS6TO4___POR       0x3
#define   DBG_PIDR2__REVISION___M                0x000000F0
#define   DBG_PIDR2__REVISION___S                              4
#define   DBG_PIDR2__REVISION__REVISION_0X3                  0x3
#define   DBG_PIDR2__JEDEC___M                   0x00000008
#define   DBG_PIDR2__JEDEC___S                                 3
#define   DBG_PIDR2__JEDEC__JEDEC_0X1                        0x1
#define   DBG_PIDR2__JEP106_BITS6TO4___M         0x00000007
#define   DBG_PIDR2__JEP106_BITS6TO4___S                       0
#define   DBG_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_PIDR2___M                          0x000000FF   
#define   DBG_PIDR2___S                                        0

#define DBG_PIDR3                                 (0x00BBBFEC)
#define   DBG_PIDR3___RWC                           QCSR_REG_RO    
#define   DBG_PIDR3___POR                        0x00000000
#define   DBG_PIDR3__REVAND___POR                0x0
#define   DBG_PIDR3__CUSTOMER_MODIFIED___POR     0x0
#define   DBG_PIDR3__REVAND___M                  0x000000F0
#define   DBG_PIDR3__REVAND___S                                4
#define   DBG_PIDR3__REVAND__REVAND_0X0                      0x0
#define   DBG_PIDR3__CUSTOMER_MODIFIED___M       0x0000000F
#define   DBG_PIDR3__CUSTOMER_MODIFIED___S                     0
#define   DBG_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_PIDR3___M                          0x000000FF   
#define   DBG_PIDR3___S                                        0

#define DBG_PIDR4                                 (0x00BBBFD0)
#define   DBG_PIDR4___RWC                           QCSR_REG_RO    
#define   DBG_PIDR4___POR                        0x00000004
#define   DBG_PIDR4__FOURKB_COUNT___POR          0x0
#define   DBG_PIDR4__JEP106_CONT___POR           0x4
#define   DBG_PIDR4__FOURKB_COUNT___M            0x000000F0
#define   DBG_PIDR4__FOURKB_COUNT___S                          4
#define   DBG_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_PIDR4__JEP106_CONT___M             0x0000000F
#define   DBG_PIDR4__JEP106_CONT___S                           0
#define   DBG_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_PIDR4___M                          0x000000FF   
#define   DBG_PIDR4___S                                        0

#define DBG_PERIPHID5                             (0x00BBBFD4)
#define   DBG_PERIPHID5___RWC                       QCSR_REG_RO    
#define   DBG_PERIPHID5___POR                    0x00000000
#define   DBG_PERIPHID5__PERIPHID5___POR         0x00000000
#define   DBG_PERIPHID5__PERIPHID5___M           0xFFFFFFFF
#define   DBG_PERIPHID5__PERIPHID5___S                         0
#define   DBG_PERIPHID5___M                      0xFFFFFFFF   
#define   DBG_PERIPHID5___S                                    0

#define DBG_PERIPHID6                             (0x00BBBFD8)
#define   DBG_PERIPHID6___RWC                       QCSR_REG_RO    
#define   DBG_PERIPHID6___POR                    0x00000000
#define   DBG_PERIPHID6__PERIPHID6___POR         0x00000000
#define   DBG_PERIPHID6__PERIPHID6___M           0xFFFFFFFF
#define   DBG_PERIPHID6__PERIPHID6___S                         0
#define   DBG_PERIPHID6___M                      0xFFFFFFFF   
#define   DBG_PERIPHID6___S                                    0

#define DBG_PERIPHID7                             (0x00BBBFDC)
#define   DBG_PERIPHID7___RWC                       QCSR_REG_RO    
#define   DBG_PERIPHID7___POR                    0x00000000
#define   DBG_PERIPHID7__PERIPHID7___POR         0x00000000
#define   DBG_PERIPHID7__PERIPHID7___M           0xFFFFFFFF
#define   DBG_PERIPHID7__PERIPHID7___S                         0
#define   DBG_PERIPHID7___M                      0xFFFFFFFF   
#define   DBG_PERIPHID7___S                                    0

#define DBG_CID0                                  (0x00BBBFF0)
#define   DBG_CID0___RWC                            QCSR_REG_RO    
#define   DBG_CID0___POR                         0x0000000D
#define   DBG_CID0__PREAMBLE___POR               0x0D
#define   DBG_CID0__PREAMBLE___M                 0x000000FF
#define   DBG_CID0__PREAMBLE___S                               0
#define   DBG_CID0__PREAMBLE__PREAMBLE_0X0D                 0x0D
#define   DBG_CID0___M                           0x000000FF   
#define   DBG_CID0___S                                         0

#define DBG_CID1                                  (0x00BBBFF4)
#define   DBG_CID1___RWC                            QCSR_REG_RO    
#define   DBG_CID1___POR                         0x00000090
#define   DBG_CID1__CLASS___POR                  0x9
#define   DBG_CID1__PREAMBLE___POR               0x0
#define   DBG_CID1__CLASS___M                    0x000000F0
#define   DBG_CID1__CLASS___S                                  4
#define   DBG_CID1__CLASS__CLASS_0X9                         0x9
#define   DBG_CID1__PREAMBLE___M                 0x0000000F
#define   DBG_CID1__PREAMBLE___S                               0
#define   DBG_CID1__PREAMBLE__PREAMBLE_0X0                   0x0
#define   DBG_CID1___M                           0x000000FF   
#define   DBG_CID1___S                                         0

#define DBG_CID2                                  (0x00BBBFF8)
#define   DBG_CID2___RWC                            QCSR_REG_RO    
#define   DBG_CID2___POR                         0x00000005
#define   DBG_CID2__PREAMBLE___POR               0x05
#define   DBG_CID2__PREAMBLE___M                 0x000000FF
#define   DBG_CID2__PREAMBLE___S                               0
#define   DBG_CID2__PREAMBLE__PREAMBLE_0X05                 0x05
#define   DBG_CID2___M                           0x000000FF   
#define   DBG_CID2___S                                         0

#define DBG_CID3                                  (0x00BBBFFC)
#define   DBG_CID3___RWC                            QCSR_REG_RO    
#define   DBG_CID3___POR                         0x000000B1
#define   DBG_CID3__PREAMBLE___POR               0xB1
#define   DBG_CID3__PREAMBLE___M                 0x000000FF
#define   DBG_CID3__PREAMBLE___S                               0
#define   DBG_CID3__PREAMBLE__PREAMBLE_0XB1                 0xB1
#define   DBG_CID3___M                           0x000000FF   
#define   DBG_CID3___S                                         0

#define DBG_TMC_RSZ                               (0x00BBC004)
#define   DBG_TMC_RSZ___RWC                         QCSR_REG_RO    
#define   DBG_TMC_RSZ___POR                      0x00002000
#define   DBG_TMC_RSZ__RSZ___POR                 0x00002000
#define   DBG_TMC_RSZ__RSZ___M                   0x7FFFFFFF
#define   DBG_TMC_RSZ__RSZ___S                                 0
#define   DBG_TMC_RSZ___M                        0x7FFFFFFF   
#define   DBG_TMC_RSZ___S                                      0

#define DBG_TMC_STS                               (0x00BBC00C)
#define   DBG_TMC_STS___RWC                         QCSR_REG_RO    
#define   DBG_TMC_STS___POR                      0x0000000C
#define   DBG_TMC_STS__EMPTY___POR               0x0
#define   DBG_TMC_STS__FTEMPTY___POR             0x1
#define   DBG_TMC_STS__TMCREADY___POR            0x1
#define   DBG_TMC_STS__TRIGGERED___POR           0x0
#define   DBG_TMC_STS__FULL___POR                0x0
#define   DBG_TMC_STS__EMPTY___M                 0x00000010
#define   DBG_TMC_STS__EMPTY___S                               4
#define   DBG_TMC_STS__EMPTY__LOW                            0x0
#define   DBG_TMC_STS__EMPTY__HIGH                           0x1
#define   DBG_TMC_STS__FTEMPTY___M               0x00000008
#define   DBG_TMC_STS__FTEMPTY___S                             3
#define   DBG_TMC_STS__FTEMPTY__LOW                          0x0
#define   DBG_TMC_STS__FTEMPTY__HIGH                         0x1
#define   DBG_TMC_STS__TMCREADY___M              0x00000004
#define   DBG_TMC_STS__TMCREADY___S                            2
#define   DBG_TMC_STS__TMCREADY__LOW                         0x0
#define   DBG_TMC_STS__TMCREADY__HIGH                        0x1
#define   DBG_TMC_STS__TRIGGERED___M             0x00000002
#define   DBG_TMC_STS__TRIGGERED___S                           1
#define   DBG_TMC_STS__TRIGGERED__LOW                        0x0
#define   DBG_TMC_STS__TRIGGERED__HIGH                       0x1
#define   DBG_TMC_STS__FULL___M                  0x00000001
#define   DBG_TMC_STS__FULL___S                                0
#define   DBG_TMC_STS__FULL__LOW                             0x0
#define   DBG_TMC_STS__FULL__HIGH                            0x1
#define   DBG_TMC_STS___M                        0x0000001F   
#define   DBG_TMC_STS___S                                      0

#define DBG_TMC_RRD                               (0x00BBC010)
#define   DBG_TMC_RRD___RWC                         QCSR_REG_RO    
#define   DBG_TMC_RRD__RRD___M                   0xFFFFFFFF
#define   DBG_TMC_RRD__RRD___S                                 0
#define   DBG_TMC_RRD___M                        0xFFFFFFFF   
#define   DBG_TMC_RRD___S                                      0

#define DBG_TMC_RRP                               (0x00BBC014)
#define   DBG_TMC_RRP___RWC                         QCSR_REG_RW    
#define   DBG_TMC_RRP___POR                      0x00000000
#define   DBG_TMC_RRP__RRP___POR                 0x0000
#define   DBG_TMC_RRP__RRP___M                   0x00007FFF
#define   DBG_TMC_RRP__RRP___S                                 0
#define   DBG_TMC_RRP___M                        0x00007FFF   
#define   DBG_TMC_RRP___S                                      0

#define DBG_TMC_RWP                               (0x00BBC018)
#define   DBG_TMC_RWP___RWC                         QCSR_REG_RW    
#define   DBG_TMC_RWP___POR                      0x00000000
#define   DBG_TMC_RWP__RWP___POR                 0x0000
#define   DBG_TMC_RWP__RWP___M                   0x00007FFF
#define   DBG_TMC_RWP__RWP___S                                 0
#define   DBG_TMC_RWP___M                        0x00007FFF   
#define   DBG_TMC_RWP___S                                      0

#define DBG_TMC_TRG                               (0x00BBC01C)
#define   DBG_TMC_TRG___RWC                         QCSR_REG_RW    
#define   DBG_TMC_TRG___POR                      0x00000000
#define   DBG_TMC_TRG__TRG___POR                 0x0000
#define   DBG_TMC_TRG__TRG___M                   0x00001FFF
#define   DBG_TMC_TRG__TRG___S                                 0
#define   DBG_TMC_TRG___M                        0x00001FFF   
#define   DBG_TMC_TRG___S                                      0

#define DBG_TMC_CTL                               (0x00BBC020)
#define   DBG_TMC_CTL___RWC                         QCSR_REG_RW    
#define   DBG_TMC_CTL___POR                      0x00000000
#define   DBG_TMC_CTL__TRACECAPTEN___POR         0x0
#define   DBG_TMC_CTL__TRACECAPTEN___M           0x00000001
#define   DBG_TMC_CTL__TRACECAPTEN___S                         0
#define   DBG_TMC_CTL__TRACECAPTEN__LOW                      0x0
#define   DBG_TMC_CTL__TRACECAPTEN__HIGH                     0x1
#define   DBG_TMC_CTL___M                        0x00000001   
#define   DBG_TMC_CTL___S                                      0

#define DBG_TMC_RWD                               (0x00BBC024)
#define   DBG_TMC_RWD___RWC                         QCSR_REG_WO    
#define   DBG_TMC_RWD__RWD___M                   0xFFFFFFFF
#define   DBG_TMC_RWD__RWD___S                                 0
#define   DBG_TMC_RWD___M                        0xFFFFFFFF   
#define   DBG_TMC_RWD___S                                      0

#define DBG_TMC_MODE                              (0x00BBC028)
#define   DBG_TMC_MODE___RWC                        QCSR_REG_RW    
#define   DBG_TMC_MODE___POR                     0x00000000
#define   DBG_TMC_MODE__MODE___POR               0x0
#define   DBG_TMC_MODE__MODE___M                 0x00000003
#define   DBG_TMC_MODE__MODE___S                               0
#define   DBG_TMC_MODE__MODE__CIRCULAR_BUFFER                0x0
#define   DBG_TMC_MODE__MODE__SW_FIFO                        0x1
#define   DBG_TMC_MODE__MODE__HW_FIFO                        0x2
#define   DBG_TMC_MODE__MODE__RESERVED                       0x3
#define   DBG_TMC_MODE___M                       0x00000003   
#define   DBG_TMC_MODE___S                                     0

#define DBG_TMC_LBUFLEVEL                         (0x00BBC02C)
#define   DBG_TMC_LBUFLEVEL___RWC                   QCSR_REG_RO    
#define   DBG_TMC_LBUFLEVEL___POR                0x00000000
#define   DBG_TMC_LBUFLEVEL__LBUFLEVEL___POR     0x0000
#define   DBG_TMC_LBUFLEVEL__LBUFLEVEL___M       0x00003FFF
#define   DBG_TMC_LBUFLEVEL__LBUFLEVEL___S                     0
#define   DBG_TMC_LBUFLEVEL___M                  0x00003FFF   
#define   DBG_TMC_LBUFLEVEL___S                                0

#define DBG_TMC_CBUFLEVEL                         (0x00BBC030)
#define   DBG_TMC_CBUFLEVEL___RWC                   QCSR_REG_RO    
#define   DBG_TMC_CBUFLEVEL___POR                0x00000000
#define   DBG_TMC_CBUFLEVEL__CBUFLEVEL___POR     0x0000
#define   DBG_TMC_CBUFLEVEL__CBUFLEVEL___M       0x00003FFF
#define   DBG_TMC_CBUFLEVEL__CBUFLEVEL___S                     0
#define   DBG_TMC_CBUFLEVEL___M                  0x00003FFF   
#define   DBG_TMC_CBUFLEVEL___S                                0

#define DBG_TMC_BUFWM                             (0x00BBC034)
#define   DBG_TMC_BUFWM___RWC                       QCSR_REG_RW    
#define   DBG_TMC_BUFWM___POR                    0x00000000
#define   DBG_TMC_BUFWM__BUFWM___POR             0x0000
#define   DBG_TMC_BUFWM__BUFWM___M               0x00001FFF
#define   DBG_TMC_BUFWM__BUFWM___S                             0
#define   DBG_TMC_BUFWM___M                      0x00001FFF   
#define   DBG_TMC_BUFWM___S                                    0

#define DBG_TMC_FFSR                              (0x00BBC300)
#define   DBG_TMC_FFSR___RWC                        QCSR_REG_RO    
#define   DBG_TMC_FFSR___POR                     0x00000002
#define   DBG_TMC_FFSR__FTSTOPPED___POR          0x1
#define   DBG_TMC_FFSR__FLINPROG___POR           0x0
#define   DBG_TMC_FFSR__FTSTOPPED___M            0x00000002
#define   DBG_TMC_FFSR__FTSTOPPED___S                          1
#define   DBG_TMC_FFSR__FTSTOPPED__LOW                       0x0
#define   DBG_TMC_FFSR__FTSTOPPED__HIGH                      0x1
#define   DBG_TMC_FFSR__FLINPROG___M             0x00000001
#define   DBG_TMC_FFSR__FLINPROG___S                           0
#define   DBG_TMC_FFSR__FLINPROG__LOW                        0x0
#define   DBG_TMC_FFSR__FLINPROG__HIGH                       0x1
#define   DBG_TMC_FFSR___M                       0x00000003   
#define   DBG_TMC_FFSR___S                                     0

#define DBG_TMC_FFCR                              (0x00BBC304)
#define   DBG_TMC_FFCR___RWC                        QCSR_REG_RW    
#define   DBG_TMC_FFCR___POR                     0x00000000
#define   DBG_TMC_FFCR__DRAINBUFFER___POR        0x0
#define   DBG_TMC_FFCR__STOPONTRIGEVT___POR      0x0
#define   DBG_TMC_FFCR__STOPONFL___POR           0x0
#define   DBG_TMC_FFCR__TRIGONFL___POR           0x0
#define   DBG_TMC_FFCR__TRIGONTRIGEVT___POR      0x0
#define   DBG_TMC_FFCR__TRIGONTRIGIN___POR       0x0
#define   DBG_TMC_FFCR__FLUSHMAN___POR           0x0
#define   DBG_TMC_FFCR__FONTRIGEVT___POR         0x0
#define   DBG_TMC_FFCR__FONFLIN___POR            0x0
#define   DBG_TMC_FFCR__ENTI___POR               0x0
#define   DBG_TMC_FFCR__ENFT___POR               0x0
#define   DBG_TMC_FFCR__DRAINBUFFER___M          0x00004000
#define   DBG_TMC_FFCR__DRAINBUFFER___S                       14
#define   DBG_TMC_FFCR__DRAINBUFFER__LOW                     0x0
#define   DBG_TMC_FFCR__DRAINBUFFER__HIGH                    0x1
#define   DBG_TMC_FFCR__STOPONTRIGEVT___M        0x00002000
#define   DBG_TMC_FFCR__STOPONTRIGEVT___S                     13
#define   DBG_TMC_FFCR__STOPONTRIGEVT__LOW                   0x0
#define   DBG_TMC_FFCR__STOPONTRIGEVT__HIGH                  0x1
#define   DBG_TMC_FFCR__STOPONFL___M             0x00001000
#define   DBG_TMC_FFCR__STOPONFL___S                          12
#define   DBG_TMC_FFCR__STOPONFL__LOW                        0x0
#define   DBG_TMC_FFCR__STOPONFL__HIGH                       0x1
#define   DBG_TMC_FFCR__TRIGONFL___M             0x00000400
#define   DBG_TMC_FFCR__TRIGONFL___S                          10
#define   DBG_TMC_FFCR__TRIGONFL__LOW                        0x0
#define   DBG_TMC_FFCR__TRIGONFL__HIGH                       0x1
#define   DBG_TMC_FFCR__TRIGONTRIGEVT___M        0x00000200
#define   DBG_TMC_FFCR__TRIGONTRIGEVT___S                      9
#define   DBG_TMC_FFCR__TRIGONTRIGEVT__LOW                   0x0
#define   DBG_TMC_FFCR__TRIGONTRIGEVT__HIGH                  0x1
#define   DBG_TMC_FFCR__TRIGONTRIGIN___M         0x00000100
#define   DBG_TMC_FFCR__TRIGONTRIGIN___S                       8
#define   DBG_TMC_FFCR__TRIGONTRIGIN__LOW                    0x0
#define   DBG_TMC_FFCR__TRIGONTRIGIN__HIGH                   0x1
#define   DBG_TMC_FFCR__FLUSHMAN___M             0x00000040
#define   DBG_TMC_FFCR__FLUSHMAN___S                           6
#define   DBG_TMC_FFCR__FLUSHMAN__LOW                        0x0
#define   DBG_TMC_FFCR__FLUSHMAN__HIGH                       0x1
#define   DBG_TMC_FFCR__FONTRIGEVT___M           0x00000020
#define   DBG_TMC_FFCR__FONTRIGEVT___S                         5
#define   DBG_TMC_FFCR__FONTRIGEVT__LOW                      0x0
#define   DBG_TMC_FFCR__FONTRIGEVT__HIGH                     0x1
#define   DBG_TMC_FFCR__FONFLIN___M              0x00000010
#define   DBG_TMC_FFCR__FONFLIN___S                            4
#define   DBG_TMC_FFCR__FONFLIN__LOW                         0x0
#define   DBG_TMC_FFCR__FONFLIN__HIGH                        0x1
#define   DBG_TMC_FFCR__ENTI___M                 0x00000002
#define   DBG_TMC_FFCR__ENTI___S                               1
#define   DBG_TMC_FFCR__ENTI__TRIGGER_INSERTION_DISABLED             0x0
#define   DBG_TMC_FFCR__ENTI__TRIGGER_INSERTION_ENABLED             0x1
#define   DBG_TMC_FFCR__ENFT___M                 0x00000001
#define   DBG_TMC_FFCR__ENFT___S                               0
#define   DBG_TMC_FFCR__ENFT__LOW                            0x0
#define   DBG_TMC_FFCR__ENFT__HIGH                           0x1
#define   DBG_TMC_FFCR___M                       0x00007773   
#define   DBG_TMC_FFCR___S                                     0

#define DBG_TMC_PSCR                              (0x00BBC308)
#define   DBG_TMC_PSCR___RWC                        QCSR_REG_RW    
#define   DBG_TMC_PSCR___POR                     0x00000000
#define   DBG_TMC_PSCR__PSCOUNT___POR            0x00
#define   DBG_TMC_PSCR__PSCOUNT___M              0x0000001F
#define   DBG_TMC_PSCR__PSCOUNT___S                            0
#define   DBG_TMC_PSCR___M                       0x0000001F   
#define   DBG_TMC_PSCR___S                                     0

#define DBG_TMC_ITATBMDATA0                       (0x00BBCED0)
#define   DBG_TMC_ITATBMDATA0___RWC                 QCSR_REG_WO    
#define   DBG_TMC_ITATBMDATA0___POR              0x00000000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT127___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT119___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT111___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT103___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT95___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT87___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT79___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT71___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT63___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT55___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT47___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT39___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT31___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT23___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT15___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT7___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT0___POR 0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT127___M 0x00010000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT127___S              16
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT127__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT127__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT119___M 0x00008000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT119___S              15
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT119__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT119__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT111___M 0x00004000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT111___S              14
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT111__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT111__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT103___M 0x00002000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT103___S              13
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT103__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT103__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT95___M  0x00001000
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT95___S               12
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT95__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT95__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT87___M  0x00000800
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT87___S               11
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT87__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT87__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT79___M  0x00000400
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT79___S               10
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT79__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT79__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT71___M  0x00000200
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT71___S                9
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT71__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT71__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT63___M  0x00000100
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT63___S                8
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT63__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT63__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT55___M  0x00000080
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT55___S                7
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT55__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT55__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT47___M  0x00000040
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT47___S                6
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT47__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT47__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT39___M  0x00000020
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT39___S                5
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT39__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT39__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT31___M  0x00000010
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT31___S                4
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT31__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT31__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT23___M  0x00000008
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT23___S                3
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT23__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT23__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT15___M  0x00000004
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT15___S                2
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT15__LOW             0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT15__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT7___M   0x00000002
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT7___S                 1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT7__LOW              0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT7__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT0___M   0x00000001
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT0___S                 0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT0__LOW              0x0
#define   DBG_TMC_ITATBMDATA0__ATDATAMBIT0__HIGH             0x1
#define   DBG_TMC_ITATBMDATA0___M                0x0001FFFF   
#define   DBG_TMC_ITATBMDATA0___S                              0

#define DBG_TMC_ITATBMCTR2                        (0x00BBCED4)
#define   DBG_TMC_ITATBMCTR2___RWC                  QCSR_REG_RO    
#define   DBG_TMC_ITATBMCTR2___POR               0x00000001
#define   DBG_TMC_ITATBMCTR2__SYNCREQM___POR     0x0
#define   DBG_TMC_ITATBMCTR2__AFVALIDM___POR     0x0
#define   DBG_TMC_ITATBMCTR2__ATREADYM___POR     0x1
#define   DBG_TMC_ITATBMCTR2__SYNCREQM___M       0x00000004
#define   DBG_TMC_ITATBMCTR2__SYNCREQM___S                     2
#define   DBG_TMC_ITATBMCTR2__SYNCREQM__LOW                  0x0
#define   DBG_TMC_ITATBMCTR2__SYNCREQM__HIGH                 0x1
#define   DBG_TMC_ITATBMCTR2__AFVALIDM___M       0x00000002
#define   DBG_TMC_ITATBMCTR2__AFVALIDM___S                     1
#define   DBG_TMC_ITATBMCTR2__AFVALIDM__LOW                  0x0
#define   DBG_TMC_ITATBMCTR2__AFVALIDM__HIGH                 0x1
#define   DBG_TMC_ITATBMCTR2__ATREADYM___M       0x00000001
#define   DBG_TMC_ITATBMCTR2__ATREADYM___S                     0
#define   DBG_TMC_ITATBMCTR2__ATREADYM__LOW                  0x0
#define   DBG_TMC_ITATBMCTR2__ATREADYM__HIGH                 0x1
#define   DBG_TMC_ITATBMCTR2___M                 0x00000007   
#define   DBG_TMC_ITATBMCTR2___S                               0

#define DBG_TMC_ITATBMCTR1                        (0x00BBCED8)
#define   DBG_TMC_ITATBMCTR1___RWC                  QCSR_REG_WO    
#define   DBG_TMC_ITATBMCTR1___POR               0x00000000
#define   DBG_TMC_ITATBMCTR1__ATIDM___POR        0x00
#define   DBG_TMC_ITATBMCTR1__ATIDM___M          0x0000007F
#define   DBG_TMC_ITATBMCTR1__ATIDM___S                        0
#define   DBG_TMC_ITATBMCTR1___M                 0x0000007F   
#define   DBG_TMC_ITATBMCTR1___S                               0

#define DBG_TMC_ITATBMCTR0                        (0x00BBCEDC)
#define   DBG_TMC_ITATBMCTR0___RWC                  QCSR_REG_WO    
#define   DBG_TMC_ITATBMCTR0___POR               0x00000000
#define   DBG_TMC_ITATBMCTR0__ATBYTESM___POR     0x0
#define   DBG_TMC_ITATBMCTR0__AFREADYM___POR     0x0
#define   DBG_TMC_ITATBMCTR0__ATVALIDM___POR     0x0
#define   DBG_TMC_ITATBMCTR0__ATBYTESM___M       0x00000F00
#define   DBG_TMC_ITATBMCTR0__ATBYTESM___S                     8
#define   DBG_TMC_ITATBMCTR0__AFREADYM___M       0x00000002
#define   DBG_TMC_ITATBMCTR0__AFREADYM___S                     1
#define   DBG_TMC_ITATBMCTR0__AFREADYM__LOW                  0x0
#define   DBG_TMC_ITATBMCTR0__AFREADYM__HIGH                 0x1
#define   DBG_TMC_ITATBMCTR0__ATVALIDM___M       0x00000001
#define   DBG_TMC_ITATBMCTR0__ATVALIDM___S                     0
#define   DBG_TMC_ITATBMCTR0__ATVALIDM__LOW                  0x0
#define   DBG_TMC_ITATBMCTR0__ATVALIDM__HIGH                 0x1
#define   DBG_TMC_ITATBMCTR0___M                 0x00000F03   
#define   DBG_TMC_ITATBMCTR0___S                               0

#define DBG_TMC_ITMISCOP0                         (0x00BBCEE0)
#define   DBG_TMC_ITMISCOP0___RWC                   QCSR_REG_WO    
#define   DBG_TMC_ITMISCOP0___POR                0x00000000
#define   DBG_TMC_ITMISCOP0__FULL___POR          0x0
#define   DBG_TMC_ITMISCOP0__ACQCOMP___POR       0x0
#define   DBG_TMC_ITMISCOP0__FULL___M            0x00000002
#define   DBG_TMC_ITMISCOP0__FULL___S                          1
#define   DBG_TMC_ITMISCOP0__FULL__LOW                       0x0
#define   DBG_TMC_ITMISCOP0__FULL__HIGH                      0x1
#define   DBG_TMC_ITMISCOP0__ACQCOMP___M         0x00000001
#define   DBG_TMC_ITMISCOP0__ACQCOMP___S                       0
#define   DBG_TMC_ITMISCOP0__ACQCOMP__LOW                    0x0
#define   DBG_TMC_ITMISCOP0__ACQCOMP__HIGH                   0x1
#define   DBG_TMC_ITMISCOP0___M                  0x00000003   
#define   DBG_TMC_ITMISCOP0___S                                0

#define DBG_TMC_ITTRFLIN                          (0x00BBCEE8)
#define   DBG_TMC_ITTRFLIN___RWC                    QCSR_REG_RO    
#define   DBG_TMC_ITTRFLIN___POR                 0x00000000
#define   DBG_TMC_ITTRFLIN__FLUSHIN___POR        0x0
#define   DBG_TMC_ITTRFLIN__TRIGIN___POR         0x0
#define   DBG_TMC_ITTRFLIN__FLUSHIN___M          0x00000002
#define   DBG_TMC_ITTRFLIN__FLUSHIN___S                        1
#define   DBG_TMC_ITTRFLIN__FLUSHIN__LOW                     0x0
#define   DBG_TMC_ITTRFLIN__FLUSHIN__HIGH                    0x1
#define   DBG_TMC_ITTRFLIN__TRIGIN___M           0x00000001
#define   DBG_TMC_ITTRFLIN__TRIGIN___S                         0
#define   DBG_TMC_ITTRFLIN__TRIGIN__LOW                      0x0
#define   DBG_TMC_ITTRFLIN__TRIGIN__HIGH                     0x1
#define   DBG_TMC_ITTRFLIN___M                   0x00000003   
#define   DBG_TMC_ITTRFLIN___S                                 0

#define DBG_TMC_ITATBDATA0                        (0x00BBCEEC)
#define   DBG_TMC_ITATBDATA0___RWC                  QCSR_REG_RO    
#define   DBG_TMC_ITATBDATA0___POR               0x00000000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT127___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT119___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT111___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT103___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT95___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT87___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT79___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT71___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT63___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT55___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT47___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT39___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT31___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT23___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT15___POR 0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT7___POR  0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT0___POR  0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT127___M  0x00010000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT127___S               16
#define   DBG_TMC_ITATBDATA0__ATDATASBIT127__LOW             0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT127__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT119___M  0x00008000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT119___S               15
#define   DBG_TMC_ITATBDATA0__ATDATASBIT119__LOW             0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT119__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT111___M  0x00004000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT111___S               14
#define   DBG_TMC_ITATBDATA0__ATDATASBIT111__LOW             0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT111__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT103___M  0x00002000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT103___S               13
#define   DBG_TMC_ITATBDATA0__ATDATASBIT103__LOW             0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT103__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT95___M   0x00001000
#define   DBG_TMC_ITATBDATA0__ATDATASBIT95___S                12
#define   DBG_TMC_ITATBDATA0__ATDATASBIT95__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT95__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT87___M   0x00000800
#define   DBG_TMC_ITATBDATA0__ATDATASBIT87___S                11
#define   DBG_TMC_ITATBDATA0__ATDATASBIT87__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT87__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT79___M   0x00000400
#define   DBG_TMC_ITATBDATA0__ATDATASBIT79___S                10
#define   DBG_TMC_ITATBDATA0__ATDATASBIT79__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT79__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT71___M   0x00000200
#define   DBG_TMC_ITATBDATA0__ATDATASBIT71___S                 9
#define   DBG_TMC_ITATBDATA0__ATDATASBIT71__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT71__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT63___M   0x00000100
#define   DBG_TMC_ITATBDATA0__ATDATASBIT63___S                 8
#define   DBG_TMC_ITATBDATA0__ATDATASBIT63__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT63__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT55___M   0x00000080
#define   DBG_TMC_ITATBDATA0__ATDATASBIT55___S                 7
#define   DBG_TMC_ITATBDATA0__ATDATASBIT55__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT55__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT47___M   0x00000040
#define   DBG_TMC_ITATBDATA0__ATDATASBIT47___S                 6
#define   DBG_TMC_ITATBDATA0__ATDATASBIT47__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT47__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT39___M   0x00000020
#define   DBG_TMC_ITATBDATA0__ATDATASBIT39___S                 5
#define   DBG_TMC_ITATBDATA0__ATDATASBIT39__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT39__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT31___M   0x00000010
#define   DBG_TMC_ITATBDATA0__ATDATASBIT31___S                 4
#define   DBG_TMC_ITATBDATA0__ATDATASBIT31__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT31__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT23___M   0x00000008
#define   DBG_TMC_ITATBDATA0__ATDATASBIT23___S                 3
#define   DBG_TMC_ITATBDATA0__ATDATASBIT23__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT23__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT15___M   0x00000004
#define   DBG_TMC_ITATBDATA0__ATDATASBIT15___S                 2
#define   DBG_TMC_ITATBDATA0__ATDATASBIT15__LOW              0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT15__HIGH             0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT7___M    0x00000002
#define   DBG_TMC_ITATBDATA0__ATDATASBIT7___S                  1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT7__LOW               0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT7__HIGH              0x1
#define   DBG_TMC_ITATBDATA0__ATDATASBIT0___M    0x00000001
#define   DBG_TMC_ITATBDATA0__ATDATASBIT0___S                  0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT0__LOW               0x0
#define   DBG_TMC_ITATBDATA0__ATDATASBIT0__HIGH              0x1
#define   DBG_TMC_ITATBDATA0___M                 0x0001FFFF   
#define   DBG_TMC_ITATBDATA0___S                               0

#define DBG_TMC_ITATBCTR2                         (0x00BBCEF0)
#define   DBG_TMC_ITATBCTR2___RWC                   QCSR_REG_WO    
#define   DBG_TMC_ITATBCTR2___POR                0x00000000
#define   DBG_TMC_ITATBCTR2__SYNCREQS___POR      0x0
#define   DBG_TMC_ITATBCTR2__AFVALIDS___POR      0x0
#define   DBG_TMC_ITATBCTR2__ATREADYS___POR      0x0
#define   DBG_TMC_ITATBCTR2__SYNCREQS___M        0x00000004
#define   DBG_TMC_ITATBCTR2__SYNCREQS___S                      2
#define   DBG_TMC_ITATBCTR2__SYNCREQS__LOW                   0x0
#define   DBG_TMC_ITATBCTR2__SYNCREQS__HIGH                  0x1
#define   DBG_TMC_ITATBCTR2__AFVALIDS___M        0x00000002
#define   DBG_TMC_ITATBCTR2__AFVALIDS___S                      1
#define   DBG_TMC_ITATBCTR2__AFVALIDS__LOW                   0x0
#define   DBG_TMC_ITATBCTR2__AFVALIDS__HIGH                  0x1
#define   DBG_TMC_ITATBCTR2__ATREADYS___M        0x00000001
#define   DBG_TMC_ITATBCTR2__ATREADYS___S                      0
#define   DBG_TMC_ITATBCTR2__ATREADYS__LOW                   0x0
#define   DBG_TMC_ITATBCTR2__ATREADYS__HIGH                  0x1
#define   DBG_TMC_ITATBCTR2___M                  0x00000007   
#define   DBG_TMC_ITATBCTR2___S                                0

#define DBG_TMC_ITATBCTR1                         (0x00BBCEF4)
#define   DBG_TMC_ITATBCTR1___RWC                   QCSR_REG_RO    
#define   DBG_TMC_ITATBCTR1___POR                0x00000000
#define   DBG_TMC_ITATBCTR1__ATIDS___POR         0x00
#define   DBG_TMC_ITATBCTR1__ATIDS___M           0x0000007F
#define   DBG_TMC_ITATBCTR1__ATIDS___S                         0
#define   DBG_TMC_ITATBCTR1___M                  0x0000007F   
#define   DBG_TMC_ITATBCTR1___S                                0

#define DBG_TMC_ITATBCTR0                         (0x00BBCEF8)
#define   DBG_TMC_ITATBCTR0___RWC                   QCSR_REG_RO    
#define   DBG_TMC_ITATBCTR0___POR                0x00000000
#define   DBG_TMC_ITATBCTR0__ATBYTESS___POR      0x0
#define   DBG_TMC_ITATBCTR0__AFREADYS___POR      0x0
#define   DBG_TMC_ITATBCTR0__ATVALIDS___POR      0x0
#define   DBG_TMC_ITATBCTR0__ATBYTESS___M        0x00000F00
#define   DBG_TMC_ITATBCTR0__ATBYTESS___S                      8
#define   DBG_TMC_ITATBCTR0__AFREADYS___M        0x00000002
#define   DBG_TMC_ITATBCTR0__AFREADYS___S                      1
#define   DBG_TMC_ITATBCTR0__AFREADYS__LOW                   0x0
#define   DBG_TMC_ITATBCTR0__AFREADYS__HIGH                  0x1
#define   DBG_TMC_ITATBCTR0__ATVALIDS___M        0x00000001
#define   DBG_TMC_ITATBCTR0__ATVALIDS___S                      0
#define   DBG_TMC_ITATBCTR0__ATVALIDS__LOW                   0x0
#define   DBG_TMC_ITATBCTR0__ATVALIDS__HIGH                  0x1
#define   DBG_TMC_ITATBCTR0___M                  0x00000F03   
#define   DBG_TMC_ITATBCTR0___S                                0

#define DBG_TMC_ITCTRL                            (0x00BBCF00)
#define   DBG_TMC_ITCTRL___RWC                      QCSR_REG_RW    
#define   DBG_TMC_ITCTRL___POR                   0x00000000
#define   DBG_TMC_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_TMC_ITCTRL__INTEGRATION_MODE___M   0x00000001
#define   DBG_TMC_ITCTRL__INTEGRATION_MODE___S                 0
#define   DBG_TMC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_TMC_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_TMC_ITCTRL___M                     0x00000001   
#define   DBG_TMC_ITCTRL___S                                   0

#define DBG_TMC_CLAIMSET                          (0x00BBCFA0)
#define   DBG_TMC_CLAIMSET___RWC                    QCSR_REG_RW    
#define   DBG_TMC_CLAIMSET___POR                 0x0000000F
#define   DBG_TMC_CLAIMSET__CLAIMSET___POR       0xF
#define   DBG_TMC_CLAIMSET__CLAIMSET___M         0x0000000F
#define   DBG_TMC_CLAIMSET__CLAIMSET___S                       0
#define   DBG_TMC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_TMC_CLAIMSET___M                   0x0000000F   
#define   DBG_TMC_CLAIMSET___S                                 0

#define DBG_TMC_CLAIMCLR                          (0x00BBCFA4)
#define   DBG_TMC_CLAIMCLR___RWC                    QCSR_REG_RW    
#define   DBG_TMC_CLAIMCLR___POR                 0x00000000
#define   DBG_TMC_CLAIMCLR__CLAIMCLR___POR       0x0
#define   DBG_TMC_CLAIMCLR__CLAIMCLR___M         0x0000000F
#define   DBG_TMC_CLAIMCLR__CLAIMCLR___S                       0
#define   DBG_TMC_CLAIMCLR___M                   0x0000000F   
#define   DBG_TMC_CLAIMCLR___S                                 0

#define DBG_TMC_LAR                               (0x00BBCFB0)
#define   DBG_TMC_LAR___RWC                         QCSR_REG_WO    
#define   DBG_TMC_LAR__ACCESS_W___M              0xFFFFFFFF
#define   DBG_TMC_LAR__ACCESS_W___S                            0
#define   DBG_TMC_LAR__ACCESS_W__UNLOCK               0xC5ACCE55
#define   DBG_TMC_LAR___M                        0xFFFFFFFF   
#define   DBG_TMC_LAR___S                                      0

#define DBG_TMC_LSR                               (0x00BBCFB4)
#define   DBG_TMC_LSR___RWC                         QCSR_REG_RO    
#define   DBG_TMC_LSR___POR                      0x00000003
#define   DBG_TMC_LSR__LOCKTYPE___POR            0x0
#define   DBG_TMC_LSR__LOCKGRANT___POR           0x1
#define   DBG_TMC_LSR__LOCKEXIST___POR           0x1
#define   DBG_TMC_LSR__LOCKTYPE___M              0x00000004
#define   DBG_TMC_LSR__LOCKTYPE___S                            2
#define   DBG_TMC_LSR__LOCKTYPE__ENUM_32_BIT                 0x0
#define   DBG_TMC_LSR__LOCKGRANT___M             0x00000002
#define   DBG_TMC_LSR__LOCKGRANT___S                           1
#define   DBG_TMC_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_TMC_LSR__LOCKGRANT__DEVICE_LOCKED              0x1
#define   DBG_TMC_LSR__LOCKEXIST___M             0x00000001
#define   DBG_TMC_LSR__LOCKEXIST___S                           0
#define   DBG_TMC_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_TMC_LSR__LOCKEXIST__LOCK_PRESENT               0x1
#define   DBG_TMC_LSR___M                        0x00000007   
#define   DBG_TMC_LSR___S                                      0

#define DBG_TMC_AUTHSTATUS                        (0x00BBCFB8)
#define   DBG_TMC_AUTHSTATUS___RWC                  QCSR_REG_RO    
#define   DBG_TMC_AUTHSTATUS___POR               0x00000000
#define   DBG_TMC_AUTHSTATUS__SNID___POR         0x0
#define   DBG_TMC_AUTHSTATUS__SID___POR          0x0
#define   DBG_TMC_AUTHSTATUS__NSNID___POR        0x0
#define   DBG_TMC_AUTHSTATUS__NSID___POR         0x0
#define   DBG_TMC_AUTHSTATUS__SNID___M           0x000000C0
#define   DBG_TMC_AUTHSTATUS__SNID___S                         6
#define   DBG_TMC_AUTHSTATUS__SNID__ENUM_2_B00               0x0
#define   DBG_TMC_AUTHSTATUS__SID___M            0x00000030
#define   DBG_TMC_AUTHSTATUS__SID___S                          4
#define   DBG_TMC_AUTHSTATUS__SID__ENUM_2_B00                0x0
#define   DBG_TMC_AUTHSTATUS__SID__ENUM_2_B10                0x2
#define   DBG_TMC_AUTHSTATUS__SID__ENUM_2_B11                0x3
#define   DBG_TMC_AUTHSTATUS__NSNID___M          0x0000000C
#define   DBG_TMC_AUTHSTATUS__NSNID___S                        2
#define   DBG_TMC_AUTHSTATUS__NSNID__ENUM_2_B00              0x0
#define   DBG_TMC_AUTHSTATUS__NSID___M           0x00000003
#define   DBG_TMC_AUTHSTATUS__NSID___S                         0
#define   DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B00               0x0
#define   DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B10               0x2
#define   DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B11               0x3
#define   DBG_TMC_AUTHSTATUS___M                 0x000000FF   
#define   DBG_TMC_AUTHSTATUS___S                               0

#define DBG_TMC_DEVID                             (0x00BBCFC8)
#define   DBG_TMC_DEVID___RWC                       QCSR_REG_RO    
#define   DBG_TMC_DEVID___POR                    0x00000580
#define   DBG_TMC_DEVID__MEMWIDTH___POR          0x5
#define   DBG_TMC_DEVID__CONFIGTYPE___POR        0x2
#define   DBG_TMC_DEVID__CLKSCHEME___POR         0x0
#define   DBG_TMC_DEVID__ATBINPORTCOUNT___POR    0x00
#define   DBG_TMC_DEVID__MEMWIDTH___M            0x00000700
#define   DBG_TMC_DEVID__MEMWIDTH___S                          8
#define   DBG_TMC_DEVID__MEMWIDTH__ENUM_32_BITS              0x2
#define   DBG_TMC_DEVID__MEMWIDTH__ENUM_64_BITS              0x3
#define   DBG_TMC_DEVID__MEMWIDTH__ENUM_128_BITS             0x4
#define   DBG_TMC_DEVID__MEMWIDTH__ENUM_256_BITS             0x5
#define   DBG_TMC_DEVID__CONFIGTYPE___M          0x000000C0
#define   DBG_TMC_DEVID__CONFIGTYPE___S                        6
#define   DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETB_EMBEDDED_TRACE_BUFFER             0x0
#define   DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETR_EMBEDDED_TRACE_ROUTER             0x1
#define   DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETF_EMBEDDED_TRACE_FIFO             0x2
#define   DBG_TMC_DEVID__CLKSCHEME___M           0x00000020
#define   DBG_TMC_DEVID__CLKSCHEME___S                         5
#define   DBG_TMC_DEVID__CLKSCHEME__TMC_RAM_SYNCHRONOUS_TO_CLK             0x0
#define   DBG_TMC_DEVID__ATBINPORTCOUNT___M      0x0000001F
#define   DBG_TMC_DEVID__ATBINPORTCOUNT___S                    0
#define   DBG_TMC_DEVID__ATBINPORTCOUNT__NO_MULTIPLEXING_PRESENT            0x00
#define   DBG_TMC_DEVID___M                      0x000007FF   
#define   DBG_TMC_DEVID___S                                    0

#define DBG_TMC_DEVTYPE                           (0x00BBCFCC)
#define   DBG_TMC_DEVTYPE___RWC                     QCSR_REG_RO    
#define   DBG_TMC_DEVTYPE___POR                  0x00000032
#define   DBG_TMC_DEVTYPE__SUB_TYPE___POR        0x3
#define   DBG_TMC_DEVTYPE__MAJOR_TYPE___POR      0x2
#define   DBG_TMC_DEVTYPE__SUB_TYPE___M          0x000000F0
#define   DBG_TMC_DEVTYPE__SUB_TYPE___S                        4
#define   DBG_TMC_DEVTYPE__SUB_TYPE__BUFFER                  0x2
#define   DBG_TMC_DEVTYPE__SUB_TYPE__FIFO                    0x3
#define   DBG_TMC_DEVTYPE__MAJOR_TYPE___M        0x0000000F
#define   DBG_TMC_DEVTYPE__MAJOR_TYPE___S                      0
#define   DBG_TMC_DEVTYPE__MAJOR_TYPE__TRACE_SINK             0x1
#define   DBG_TMC_DEVTYPE__MAJOR_TYPE__TRACE_LINK             0x2
#define   DBG_TMC_DEVTYPE___M                    0x000000FF   
#define   DBG_TMC_DEVTYPE___S                                  0

#define DBG_TMC_PERIPHID0                         (0x00BBCFE0)
#define   DBG_TMC_PERIPHID0___RWC                   QCSR_REG_RO    
#define   DBG_TMC_PERIPHID0___POR                0x00000061
#define   DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___POR 0x61
#define   DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0__CORESIGHT_TMC_PART_NUMBER_7_0            0x61
#define   DBG_TMC_PERIPHID0___M                  0x000000FF   
#define   DBG_TMC_PERIPHID0___S                                0

#define DBG_TMC_PERIPHID1                         (0x00BBCFE4)
#define   DBG_TMC_PERIPHID1___RWC                   QCSR_REG_RO    
#define   DBG_TMC_PERIPHID1___POR                0x000000B9
#define   DBG_TMC_PERIPHID1__JEP106_BITS3TO0___POR 0xB
#define   DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_TMC_PERIPHID1__JEP106_BITS3TO0___M 0x000000F0
#define   DBG_TMC_PERIPHID1__JEP106_BITS3TO0___S               4
#define   DBG_TMC_PERIPHID1__JEP106_BITS3TO0__ARM_JEP106_IDENTITY_CODE_7_0             0xB
#define   DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8__CORESIGHT_TMC_PART_NUMBER_11_8             0x9
#define   DBG_TMC_PERIPHID1___M                  0x000000FF   
#define   DBG_TMC_PERIPHID1___S                                0

#define DBG_TMC_PERIPHID2                         (0x00BBCFE8)
#define   DBG_TMC_PERIPHID2___RWC                   QCSR_REG_RO    
#define   DBG_TMC_PERIPHID2___POR                0x0000001B
#define   DBG_TMC_PERIPHID2__REVISION___POR      0x1
#define   DBG_TMC_PERIPHID2__JEDEC___POR         0x1
#define   DBG_TMC_PERIPHID2__JEP106_BITS6TO4___POR 0x3
#define   DBG_TMC_PERIPHID2__REVISION___M        0x000000F0
#define   DBG_TMC_PERIPHID2__REVISION___S                      4
#define   DBG_TMC_PERIPHID2__REVISION__R0P1                  0x1
#define   DBG_TMC_PERIPHID2__JEDEC___M           0x00000008
#define   DBG_TMC_PERIPHID2__JEDEC___S                         3
#define   DBG_TMC_PERIPHID2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_TMC_PERIPHID2__JEP106_BITS6TO4___M 0x00000007
#define   DBG_TMC_PERIPHID2__JEP106_BITS6TO4___S               0
#define   DBG_TMC_PERIPHID2__JEP106_BITS6TO4__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_TMC_PERIPHID2___M                  0x000000FF   
#define   DBG_TMC_PERIPHID2___S                                0

#define DBG_TMC_PERIPHID3                         (0x00BBCFEC)
#define   DBG_TMC_PERIPHID3___RWC                   QCSR_REG_RO    
#define   DBG_TMC_PERIPHID3___POR                0x00000000
#define   DBG_TMC_PERIPHID3__REVAND___POR        0x0
#define   DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_TMC_PERIPHID3__REVAND___M          0x000000F0
#define   DBG_TMC_PERIPHID3__REVAND___S                        4
#define   DBG_TMC_PERIPHID3__REVAND__NO_MODS                 0x0
#define   DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___S               0
#define   DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED__NO_MODS             0x0
#define   DBG_TMC_PERIPHID3___M                  0x000000FF   
#define   DBG_TMC_PERIPHID3___S                                0

#define DBG_TMC_PERIPHID4                         (0x00BBCFD0)
#define   DBG_TMC_PERIPHID4___RWC                   QCSR_REG_RO    
#define   DBG_TMC_PERIPHID4___POR                0x00000004
#define   DBG_TMC_PERIPHID4__FOURKB_COUNT___POR  0x0
#define   DBG_TMC_PERIPHID4__JEP106_CONT___POR   0x4
#define   DBG_TMC_PERIPHID4__FOURKB_COUNT___M    0x000000F0
#define   DBG_TMC_PERIPHID4__FOURKB_COUNT___S                  4
#define   DBG_TMC_PERIPHID4__FOURKB_COUNT__ENUM_4KB             0x0
#define   DBG_TMC_PERIPHID4__JEP106_CONT___M     0x0000000F
#define   DBG_TMC_PERIPHID4__JEP106_CONT___S                   0
#define   DBG_TMC_PERIPHID4__JEP106_CONT__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_TMC_PERIPHID4___M                  0x000000FF   
#define   DBG_TMC_PERIPHID4___S                                0

#define DBG_TMC_PERIPHID5                         (0x00BBCFD4)
#define   DBG_TMC_PERIPHID5___RWC                   QCSR_REG_RW    
#define   DBG_TMC_PERIPHID5__PERIPHID5___M       0xFFFFFFFF
#define   DBG_TMC_PERIPHID5__PERIPHID5___S                     0
#define   DBG_TMC_PERIPHID5___M                  0xFFFFFFFF   
#define   DBG_TMC_PERIPHID5___S                                0

#define DBG_TMC_PERIPHID6                         (0x00BBCFD8)
#define   DBG_TMC_PERIPHID6___RWC                   QCSR_REG_RW    
#define   DBG_TMC_PERIPHID6__PERIPHID6___M       0xFFFFFFFF
#define   DBG_TMC_PERIPHID6__PERIPHID6___S                     0
#define   DBG_TMC_PERIPHID6___M                  0xFFFFFFFF   
#define   DBG_TMC_PERIPHID6___S                                0

#define DBG_TMC_PERIPHID7                         (0x00BBCFDC)
#define   DBG_TMC_PERIPHID7___RWC                   QCSR_REG_RW    
#define   DBG_TMC_PERIPHID7__PERIPHID7___M       0xFFFFFFFF
#define   DBG_TMC_PERIPHID7__PERIPHID7___S                     0
#define   DBG_TMC_PERIPHID7___M                  0xFFFFFFFF   
#define   DBG_TMC_PERIPHID7___S                                0

#define DBG_TMC_COMPID0                           (0x00BBCFF0)
#define   DBG_TMC_COMPID0___RWC                     QCSR_REG_RO    
#define   DBG_TMC_COMPID0___POR                  0x0000000D
#define   DBG_TMC_COMPID0__PREAMBLE___POR        0x0D
#define   DBG_TMC_COMPID0__PREAMBLE___M          0x000000FF
#define   DBG_TMC_COMPID0__PREAMBLE___S                        0
#define   DBG_TMC_COMPID0__PREAMBLE__ENUM_0D                0x0D
#define   DBG_TMC_COMPID0___M                    0x000000FF   
#define   DBG_TMC_COMPID0___S                                  0

#define DBG_TMC_COMPID1                           (0x00BBCFF4)
#define   DBG_TMC_COMPID1___RWC                     QCSR_REG_RO    
#define   DBG_TMC_COMPID1___POR                  0x00000090
#define   DBG_TMC_COMPID1__CLASS___POR           0x9
#define   DBG_TMC_COMPID1__PREAMBLE___POR        0x0
#define   DBG_TMC_COMPID1__CLASS___M             0x000000F0
#define   DBG_TMC_COMPID1__CLASS___S                           4
#define   DBG_TMC_COMPID1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_TMC_COMPID1__PREAMBLE___M          0x0000000F
#define   DBG_TMC_COMPID1__PREAMBLE___S                        0
#define   DBG_TMC_COMPID1__PREAMBLE__ENUM_0                  0x0
#define   DBG_TMC_COMPID1___M                    0x000000FF   
#define   DBG_TMC_COMPID1___S                                  0

#define DBG_TMC_COMPID2                           (0x00BBCFF8)
#define   DBG_TMC_COMPID2___RWC                     QCSR_REG_RO    
#define   DBG_TMC_COMPID2___POR                  0x00000005
#define   DBG_TMC_COMPID2__PREAMBLE___POR        0x05
#define   DBG_TMC_COMPID2__PREAMBLE___M          0x000000FF
#define   DBG_TMC_COMPID2__PREAMBLE___S                        0
#define   DBG_TMC_COMPID2__PREAMBLE__ENUM_05                0x05
#define   DBG_TMC_COMPID2___M                    0x000000FF   
#define   DBG_TMC_COMPID2___S                                  0

#define DBG_TMC_COMPID3                           (0x00BBCFFC)
#define   DBG_TMC_COMPID3___RWC                     QCSR_REG_RO    
#define   DBG_TMC_COMPID3___POR                  0x000000B1
#define   DBG_TMC_COMPID3__PREAMBLE___POR        0xB1
#define   DBG_TMC_COMPID3__PREAMBLE___M          0x000000FF
#define   DBG_TMC_COMPID3__PREAMBLE___S                        0
#define   DBG_TMC_COMPID3__PREAMBLE__B1                     0xB1
#define   DBG_TMC_COMPID3___M                    0x000000FF   
#define   DBG_TMC_COMPID3___S                                  0

#define DBG_OUTFUN_CTRL_REG                       (0x00BBE000)
#define   DBG_OUTFUN_CTRL_REG___RWC                 QCSR_REG_RW    
#define   DBG_OUTFUN_CTRL_REG___POR              0x00000300
#define   DBG_OUTFUN_CTRL_REG__HT___POR          0x3
#define   DBG_OUTFUN_CTRL_REG__ENS1___POR        0x0
#define   DBG_OUTFUN_CTRL_REG__ENS0___POR        0x0
#define   DBG_OUTFUN_CTRL_REG__HT___M            0x00000F00
#define   DBG_OUTFUN_CTRL_REG__HT___S                          8
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X0                    0x0
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X1                    0x1
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X2                    0x2
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X3                    0x3
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X4                    0x4
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X5                    0x5
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X6                    0x6
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X7                    0x7
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X8                    0x8
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0X9                    0x9
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0XA                    0xA
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0XB                    0xB
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0XC                    0xC
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0XD                    0xD
#define   DBG_OUTFUN_CTRL_REG__HT__HT_0XE                    0xE
#define   DBG_OUTFUN_CTRL_REG__ENS1___M          0x00000002
#define   DBG_OUTFUN_CTRL_REG__ENS1___S                        1
#define   DBG_OUTFUN_CTRL_REG__ENS1__ENS1_0                  0x0
#define   DBG_OUTFUN_CTRL_REG__ENS1__ENS1_1                  0x1
#define   DBG_OUTFUN_CTRL_REG__ENS0___M          0x00000001
#define   DBG_OUTFUN_CTRL_REG__ENS0___S                        0
#define   DBG_OUTFUN_CTRL_REG__ENS0__ENS0_0                  0x0
#define   DBG_OUTFUN_CTRL_REG__ENS0__ENS0_1                  0x1
#define   DBG_OUTFUN_CTRL_REG___M                0x00000F03   
#define   DBG_OUTFUN_CTRL_REG___S                              0

#define DBG_OUTFUN_PRIORITY_CTRL_REG              (0x00BBE004)
#define   DBG_OUTFUN_PRIORITY_CTRL_REG___RWC        QCSR_REG_RW    
#define   DBG_OUTFUN_PRIORITY_CTRL_REG___POR     0x00000000
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_OUTFUN_PRIORITY_CTRL_REG___M       0x0000003F   
#define   DBG_OUTFUN_PRIORITY_CTRL_REG___S                     0

#define DBG_OUTFUN_ITATBDATA0                     (0x00BBEEEC)
#define   DBG_OUTFUN_ITATBDATA0___RWC               QCSR_REG_RW    
#define   DBG_OUTFUN_ITATBDATA0___POR            0x00000000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA127___POR 0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA119___POR 0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA111___POR 0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA103___POR 0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA95___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA87___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA79___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA71___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA63___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA55___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA47___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA39___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA31___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA15___POR  0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA7___POR   0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA0___POR   0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA127___M   0x00010000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA127___S                16
#define   DBG_OUTFUN_ITATBDATA0__ATDATA127__ATDATA127_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA127__ATDATA127_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA119___M   0x00008000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA119___S                15
#define   DBG_OUTFUN_ITATBDATA0__ATDATA119__ATDATA119_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA119__ATDATA119_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA111___M   0x00004000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA111___S                14
#define   DBG_OUTFUN_ITATBDATA0__ATDATA111__ATDATA111_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA111__ATDATA111_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA103___M   0x00002000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA103___S                13
#define   DBG_OUTFUN_ITATBDATA0__ATDATA103__ATDATA103_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA103__ATDATA103_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA95___M    0x00001000
#define   DBG_OUTFUN_ITATBDATA0__ATDATA95___S                 12
#define   DBG_OUTFUN_ITATBDATA0__ATDATA95__ATDATA95_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA95__ATDATA95_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA87___M    0x00000800
#define   DBG_OUTFUN_ITATBDATA0__ATDATA87___S                 11
#define   DBG_OUTFUN_ITATBDATA0__ATDATA87__ATDATA87_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA87__ATDATA87_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA79___M    0x00000400
#define   DBG_OUTFUN_ITATBDATA0__ATDATA79___S                 10
#define   DBG_OUTFUN_ITATBDATA0__ATDATA79__ATDATA79_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA79__ATDATA79_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA71___M    0x00000200
#define   DBG_OUTFUN_ITATBDATA0__ATDATA71___S                  9
#define   DBG_OUTFUN_ITATBDATA0__ATDATA71__ATDATA71_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA71__ATDATA71_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA63___M    0x00000100
#define   DBG_OUTFUN_ITATBDATA0__ATDATA63___S                  8
#define   DBG_OUTFUN_ITATBDATA0__ATDATA63__ATDATA63_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA63__ATDATA63_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA55___M    0x00000080
#define   DBG_OUTFUN_ITATBDATA0__ATDATA55___S                  7
#define   DBG_OUTFUN_ITATBDATA0__ATDATA55__ATDATA55_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA55__ATDATA55_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA47___M    0x00000040
#define   DBG_OUTFUN_ITATBDATA0__ATDATA47___S                  6
#define   DBG_OUTFUN_ITATBDATA0__ATDATA47__ATDATA47_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA47__ATDATA47_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA39___M    0x00000020
#define   DBG_OUTFUN_ITATBDATA0__ATDATA39___S                  5
#define   DBG_OUTFUN_ITATBDATA0__ATDATA39__ATDATA39_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA39__ATDATA39_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA31___M    0x00000010
#define   DBG_OUTFUN_ITATBDATA0__ATDATA31___S                  4
#define   DBG_OUTFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATAM23___M   0x00000008
#define   DBG_OUTFUN_ITATBDATA0__ATDATAM23___S                 3
#define   DBG_OUTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA15___M    0x00000004
#define   DBG_OUTFUN_ITATBDATA0__ATDATA15___S                  2
#define   DBG_OUTFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA7___M     0x00000002
#define   DBG_OUTFUN_ITATBDATA0__ATDATA7___S                   1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_OUTFUN_ITATBDATA0__ATDATA0___M     0x00000001
#define   DBG_OUTFUN_ITATBDATA0__ATDATA0___S                   0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_OUTFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_OUTFUN_ITATBDATA0___M              0x0001FFFF   
#define   DBG_OUTFUN_ITATBDATA0___S                            0

#define DBG_OUTFUN_ITATBCTR2                      (0x00BBEEF0)
#define   DBG_OUTFUN_ITATBCTR2___RWC                QCSR_REG_RW    
#define   DBG_OUTFUN_ITATBCTR2___POR             0x00000000
#define   DBG_OUTFUN_ITATBCTR2__AFVALID___POR    0x0
#define   DBG_OUTFUN_ITATBCTR2__ATREADY___POR    0x0
#define   DBG_OUTFUN_ITATBCTR2__AFVALID___M      0x00000002
#define   DBG_OUTFUN_ITATBCTR2__AFVALID___S                    1
#define   DBG_OUTFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_OUTFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_OUTFUN_ITATBCTR2__ATREADY___M      0x00000001
#define   DBG_OUTFUN_ITATBCTR2__ATREADY___S                    0
#define   DBG_OUTFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_OUTFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_OUTFUN_ITATBCTR2___M               0x00000003   
#define   DBG_OUTFUN_ITATBCTR2___S                             0

#define DBG_OUTFUN_ITATBCTR1                      (0x00BBEEF4)
#define   DBG_OUTFUN_ITATBCTR1___RWC                QCSR_REG_RW    
#define   DBG_OUTFUN_ITATBCTR1__ATID___M         0x0000007F
#define   DBG_OUTFUN_ITATBCTR1__ATID___S                       0
#define   DBG_OUTFUN_ITATBCTR1___M               0x0000007F   
#define   DBG_OUTFUN_ITATBCTR1___S                             0

#define DBG_OUTFUN_ITATBCTR0                      (0x00BBEEF8)
#define   DBG_OUTFUN_ITATBCTR0___RWC                QCSR_REG_RW    
#define   DBG_OUTFUN_ITATBCTR0___POR             0x00000000
#define   DBG_OUTFUN_ITATBCTR0__ATBYTES___POR    0x0
#define   DBG_OUTFUN_ITATBCTR0__AFREADY___POR    0x0
#define   DBG_OUTFUN_ITATBCTR0__ATVALID___POR    0x0
#define   DBG_OUTFUN_ITATBCTR0__ATBYTES___M      0x00000F00
#define   DBG_OUTFUN_ITATBCTR0__ATBYTES___S                    8
#define   DBG_OUTFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_OUTFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_OUTFUN_ITATBCTR0__AFREADY___M      0x00000002
#define   DBG_OUTFUN_ITATBCTR0__AFREADY___S                    1
#define   DBG_OUTFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_OUTFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_OUTFUN_ITATBCTR0__ATVALID___M      0x00000001
#define   DBG_OUTFUN_ITATBCTR0__ATVALID___S                    0
#define   DBG_OUTFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_OUTFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_OUTFUN_ITATBCTR0___M               0x00000F03   
#define   DBG_OUTFUN_ITATBCTR0___S                             0

#define DBG_OUTFUN_ITCTRL                         (0x00BBEF00)
#define   DBG_OUTFUN_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_OUTFUN_ITCTRL___POR                0x00000000
#define   DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_OUTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_OUTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_OUTFUN_ITCTRL___M                  0x00000001   
#define   DBG_OUTFUN_ITCTRL___S                                0

#define DBG_OUTFUN_CLAIMSET                       (0x00BBEFA0)
#define   DBG_OUTFUN_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_OUTFUN_CLAIMSET___POR              0x0000000F
#define   DBG_OUTFUN_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_OUTFUN_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_OUTFUN_CLAIMSET__CLAIMSET___S                    0
#define   DBG_OUTFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_OUTFUN_CLAIMSET___M                0x0000000F   
#define   DBG_OUTFUN_CLAIMSET___S                              0

#define DBG_OUTFUN_CLAIMCLR                       (0x00BBEFA4)
#define   DBG_OUTFUN_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_OUTFUN_CLAIMCLR___POR              0x00000000
#define   DBG_OUTFUN_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_OUTFUN_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_OUTFUN_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_OUTFUN_CLAIMCLR___M                0x0000000F   
#define   DBG_OUTFUN_CLAIMCLR___S                              0

#define DBG_OUTFUN_LOCKACCESS                     (0x00BBEFB0)
#define   DBG_OUTFUN_LOCKACCESS___RWC               QCSR_REG_WO    
#define   DBG_OUTFUN_LOCKACCESS__KEY___M         0xFFFFFFFF
#define   DBG_OUTFUN_LOCKACCESS__KEY___S                       0
#define   DBG_OUTFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_OUTFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_OUTFUN_LOCKACCESS___M              0xFFFFFFFF   
#define   DBG_OUTFUN_LOCKACCESS___S                            0

#define DBG_OUTFUN_LOCKSTATUS                     (0x00BBEFB4)
#define   DBG_OUTFUN_LOCKSTATUS___RWC               QCSR_REG_RO    
#define   DBG_OUTFUN_LOCKSTATUS___POR            0x00000003
#define   DBG_OUTFUN_LOCKSTATUS__NTT___POR       0x0
#define   DBG_OUTFUN_LOCKSTATUS__SLK___POR       0x1
#define   DBG_OUTFUN_LOCKSTATUS__SLI___POR       0x1
#define   DBG_OUTFUN_LOCKSTATUS__NTT___M         0x00000004
#define   DBG_OUTFUN_LOCKSTATUS__NTT___S                       2
#define   DBG_OUTFUN_LOCKSTATUS__NTT__NTT_0X0                0x0
#define   DBG_OUTFUN_LOCKSTATUS__SLK___M         0x00000002
#define   DBG_OUTFUN_LOCKSTATUS__SLK___S                       1
#define   DBG_OUTFUN_LOCKSTATUS__SLK__SLK_0X0                0x0
#define   DBG_OUTFUN_LOCKSTATUS__SLK__SLK_0X1                0x1
#define   DBG_OUTFUN_LOCKSTATUS__SLI___M         0x00000001
#define   DBG_OUTFUN_LOCKSTATUS__SLI___S                       0
#define   DBG_OUTFUN_LOCKSTATUS__SLI__SLI_0X0                0x0
#define   DBG_OUTFUN_LOCKSTATUS__SLI__SLI_0X1                0x1
#define   DBG_OUTFUN_LOCKSTATUS___M              0x00000007   
#define   DBG_OUTFUN_LOCKSTATUS___S                            0

#define DBG_OUTFUN_AUTHSTATUS                     (0x00BBEFB8)
#define   DBG_OUTFUN_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_OUTFUN_AUTHSTATUS___POR            0x00000000
#define   DBG_OUTFUN_AUTHSTATUS__SNID___POR      0x0
#define   DBG_OUTFUN_AUTHSTATUS__SID___POR       0x0
#define   DBG_OUTFUN_AUTHSTATUS__NSNID___POR     0x0
#define   DBG_OUTFUN_AUTHSTATUS__NSID___POR      0x0
#define   DBG_OUTFUN_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_OUTFUN_AUTHSTATUS__SNID___S                      6
#define   DBG_OUTFUN_AUTHSTATUS__SNID__SNID_0X0              0x0
#define   DBG_OUTFUN_AUTHSTATUS__SID___M         0x00000030
#define   DBG_OUTFUN_AUTHSTATUS__SID___S                       4
#define   DBG_OUTFUN_AUTHSTATUS__SID__SID_0X0                0x0
#define   DBG_OUTFUN_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_OUTFUN_AUTHSTATUS__NSNID___S                     2
#define   DBG_OUTFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_OUTFUN_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_OUTFUN_AUTHSTATUS__NSID___S                      0
#define   DBG_OUTFUN_AUTHSTATUS__NSID__NSID_0X0              0x0
#define   DBG_OUTFUN_AUTHSTATUS___M              0x000000FF   
#define   DBG_OUTFUN_AUTHSTATUS___S                            0

#define DBG_OUTFUN_DEVID                          (0x00BBEFC8)
#define   DBG_OUTFUN_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_DEVID___POR                 0x00000032
#define   DBG_OUTFUN_DEVID__SCHEME___POR         0x3
#define   DBG_OUTFUN_DEVID__PORTCOUNT___POR      0x2
#define   DBG_OUTFUN_DEVID__SCHEME___M           0x000000F0
#define   DBG_OUTFUN_DEVID__SCHEME___S                         4
#define   DBG_OUTFUN_DEVID__SCHEME__SCHEME_0X3               0x3
#define   DBG_OUTFUN_DEVID__PORTCOUNT___M        0x0000000F
#define   DBG_OUTFUN_DEVID__PORTCOUNT___S                      0
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_OUTFUN_DEVID___M                   0x000000FF   
#define   DBG_OUTFUN_DEVID___S                                 0

#define DBG_OUTFUN_DEVTYPE                        (0x00BBEFCC)
#define   DBG_OUTFUN_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_OUTFUN_DEVTYPE___POR               0x00000012
#define   DBG_OUTFUN_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___POR   0x2
#define   DBG_OUTFUN_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_OUTFUN_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_OUTFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_OUTFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_OUTFUN_DEVTYPE___M                 0x000000FF   
#define   DBG_OUTFUN_DEVTYPE___S                               0

#define DBG_OUTFUN_PIDR0                          (0x00BBEFE0)
#define   DBG_OUTFUN_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_PIDR0___POR                 0x00000008
#define   DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_OUTFUN_PIDR0___M                   0x000000FF   
#define   DBG_OUTFUN_PIDR0___S                                 0

#define DBG_OUTFUN_PIDR1                          (0x00BBEFE4)
#define   DBG_OUTFUN_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_PIDR1___POR                 0x000000B9
#define   DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___M  0x000000F0
#define   DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___S                4
#define   DBG_OUTFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_OUTFUN_PIDR1___M                   0x000000FF   
#define   DBG_OUTFUN_PIDR1___S                                 0

#define DBG_OUTFUN_PIDR2                          (0x00BBEFE8)
#define   DBG_OUTFUN_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_PIDR2___POR                 0x0000003B
#define   DBG_OUTFUN_PIDR2__REVISION___POR       0x3
#define   DBG_OUTFUN_PIDR2__JEDEC___POR          0x1
#define   DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_OUTFUN_PIDR2__REVISION___M         0x000000F0
#define   DBG_OUTFUN_PIDR2__REVISION___S                       4
#define   DBG_OUTFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_OUTFUN_PIDR2__JEDEC___M            0x00000008
#define   DBG_OUTFUN_PIDR2__JEDEC___S                          3
#define   DBG_OUTFUN_PIDR2__JEDEC__JEDEC_0X1                 0x1
#define   DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___M  0x00000007
#define   DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___S                0
#define   DBG_OUTFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_OUTFUN_PIDR2___M                   0x000000FF   
#define   DBG_OUTFUN_PIDR2___S                                 0

#define DBG_OUTFUN_PIDR3                          (0x00BBEFEC)
#define   DBG_OUTFUN_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_PIDR3___POR                 0x00000000
#define   DBG_OUTFUN_PIDR3__REVAND___POR         0x0
#define   DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_OUTFUN_PIDR3__REVAND___M           0x000000F0
#define   DBG_OUTFUN_PIDR3__REVAND___S                         4
#define   DBG_OUTFUN_PIDR3__REVAND__REVAND_0X0               0x0
#define   DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_OUTFUN_PIDR3___M                   0x000000FF   
#define   DBG_OUTFUN_PIDR3___S                                 0

#define DBG_OUTFUN_PIDR4                          (0x00BBEFD0)
#define   DBG_OUTFUN_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_OUTFUN_PIDR4___POR                 0x00000004
#define   DBG_OUTFUN_PIDR4__FOURKB_COUNT___POR   0x0
#define   DBG_OUTFUN_PIDR4__JEP106_CONT___POR    0x4
#define   DBG_OUTFUN_PIDR4__FOURKB_COUNT___M     0x000000F0
#define   DBG_OUTFUN_PIDR4__FOURKB_COUNT___S                   4
#define   DBG_OUTFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_OUTFUN_PIDR4__JEP106_CONT___M      0x0000000F
#define   DBG_OUTFUN_PIDR4__JEP106_CONT___S                    0
#define   DBG_OUTFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_OUTFUN_PIDR4___M                   0x000000FF   
#define   DBG_OUTFUN_PIDR4___S                                 0

#define DBG_OUTFUN_PERIPHID5                      (0x00BBEFD4)
#define   DBG_OUTFUN_PERIPHID5___RWC                QCSR_REG_RO    
#define   DBG_OUTFUN_PERIPHID5___POR             0x00000000
#define   DBG_OUTFUN_PERIPHID5__PERIPHID5___POR  0x00000000
#define   DBG_OUTFUN_PERIPHID5__PERIPHID5___M    0xFFFFFFFF
#define   DBG_OUTFUN_PERIPHID5__PERIPHID5___S                  0
#define   DBG_OUTFUN_PERIPHID5___M               0xFFFFFFFF   
#define   DBG_OUTFUN_PERIPHID5___S                             0

#define DBG_OUTFUN_PERIPHID6                      (0x00BBEFD8)
#define   DBG_OUTFUN_PERIPHID6___RWC                QCSR_REG_RO    
#define   DBG_OUTFUN_PERIPHID6___POR             0x00000000
#define   DBG_OUTFUN_PERIPHID6__PERIPHID6___POR  0x00000000
#define   DBG_OUTFUN_PERIPHID6__PERIPHID6___M    0xFFFFFFFF
#define   DBG_OUTFUN_PERIPHID6__PERIPHID6___S                  0
#define   DBG_OUTFUN_PERIPHID6___M               0xFFFFFFFF   
#define   DBG_OUTFUN_PERIPHID6___S                             0

#define DBG_OUTFUN_PERIPHID7                      (0x00BBEFDC)
#define   DBG_OUTFUN_PERIPHID7___RWC                QCSR_REG_RO    
#define   DBG_OUTFUN_PERIPHID7___POR             0x00000000
#define   DBG_OUTFUN_PERIPHID7__PERIPHID7___POR  0x00000000
#define   DBG_OUTFUN_PERIPHID7__PERIPHID7___M    0xFFFFFFFF
#define   DBG_OUTFUN_PERIPHID7__PERIPHID7___S                  0
#define   DBG_OUTFUN_PERIPHID7___M               0xFFFFFFFF   
#define   DBG_OUTFUN_PERIPHID7___S                             0

#define DBG_OUTFUN_CID0                           (0x00BBEFF0)
#define   DBG_OUTFUN_CID0___RWC                     QCSR_REG_RO    
#define   DBG_OUTFUN_CID0___POR                  0x0000000D
#define   DBG_OUTFUN_CID0__PREAMBLE___POR        0x0D
#define   DBG_OUTFUN_CID0__PREAMBLE___M          0x000000FF
#define   DBG_OUTFUN_CID0__PREAMBLE___S                        0
#define   DBG_OUTFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_OUTFUN_CID0___M                    0x000000FF   
#define   DBG_OUTFUN_CID0___S                                  0

#define DBG_OUTFUN_CID1                           (0x00BBEFF4)
#define   DBG_OUTFUN_CID1___RWC                     QCSR_REG_RO    
#define   DBG_OUTFUN_CID1___POR                  0x00000090
#define   DBG_OUTFUN_CID1__CLASS___POR           0x9
#define   DBG_OUTFUN_CID1__PREAMBLE___POR        0x0
#define   DBG_OUTFUN_CID1__CLASS___M             0x000000F0
#define   DBG_OUTFUN_CID1__CLASS___S                           4
#define   DBG_OUTFUN_CID1__CLASS__CLASS_0X9                  0x9
#define   DBG_OUTFUN_CID1__PREAMBLE___M          0x0000000F
#define   DBG_OUTFUN_CID1__PREAMBLE___S                        0
#define   DBG_OUTFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_OUTFUN_CID1___M                    0x000000FF   
#define   DBG_OUTFUN_CID1___S                                  0

#define DBG_OUTFUN_CID2                           (0x00BBEFF8)
#define   DBG_OUTFUN_CID2___RWC                     QCSR_REG_RO    
#define   DBG_OUTFUN_CID2___POR                  0x00000005
#define   DBG_OUTFUN_CID2__PREAMBLE___POR        0x05
#define   DBG_OUTFUN_CID2__PREAMBLE___M          0x000000FF
#define   DBG_OUTFUN_CID2__PREAMBLE___S                        0
#define   DBG_OUTFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_OUTFUN_CID2___M                    0x000000FF   
#define   DBG_OUTFUN_CID2___S                                  0

#define DBG_OUTFUN_CID3                           (0x00BBEFFC)
#define   DBG_OUTFUN_CID3___RWC                     QCSR_REG_RO    
#define   DBG_OUTFUN_CID3___POR                  0x000000B1
#define   DBG_OUTFUN_CID3__PREAMBLE___POR        0xB1
#define   DBG_OUTFUN_CID3__PREAMBLE___M          0x000000FF
#define   DBG_OUTFUN_CID3__PREAMBLE___S                        0
#define   DBG_OUTFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_OUTFUN_CID3___M                    0x000000FF   
#define   DBG_OUTFUN_CID3___S                                  0

#define DBG_PHYFUN_CTRL_REG                       (0x00BBF000)
#define   DBG_PHYFUN_CTRL_REG___RWC                 QCSR_REG_RW    
#define   DBG_PHYFUN_CTRL_REG___POR              0x00000300
#define   DBG_PHYFUN_CTRL_REG__HT___POR          0x3
#define   DBG_PHYFUN_CTRL_REG__ENS1___POR        0x0
#define   DBG_PHYFUN_CTRL_REG__ENS0___POR        0x0
#define   DBG_PHYFUN_CTRL_REG__HT___M            0x00000F00
#define   DBG_PHYFUN_CTRL_REG__HT___S                          8
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X0                    0x0
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X1                    0x1
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X2                    0x2
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X3                    0x3
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X4                    0x4
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X5                    0x5
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X6                    0x6
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X7                    0x7
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X8                    0x8
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0X9                    0x9
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0XA                    0xA
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0XB                    0xB
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0XC                    0xC
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0XD                    0xD
#define   DBG_PHYFUN_CTRL_REG__HT__HT_0XE                    0xE
#define   DBG_PHYFUN_CTRL_REG__ENS1___M          0x00000002
#define   DBG_PHYFUN_CTRL_REG__ENS1___S                        1
#define   DBG_PHYFUN_CTRL_REG__ENS1__ENS1_0                  0x0
#define   DBG_PHYFUN_CTRL_REG__ENS1__ENS1_1                  0x1
#define   DBG_PHYFUN_CTRL_REG__ENS0___M          0x00000001
#define   DBG_PHYFUN_CTRL_REG__ENS0___S                        0
#define   DBG_PHYFUN_CTRL_REG__ENS0__ENS0_0                  0x0
#define   DBG_PHYFUN_CTRL_REG__ENS0__ENS0_1                  0x1
#define   DBG_PHYFUN_CTRL_REG___M                0x00000F03   
#define   DBG_PHYFUN_CTRL_REG___S                              0

#define DBG_PHYFUN_PRIORITY_CTRL_REG              (0x00BBF004)
#define   DBG_PHYFUN_PRIORITY_CTRL_REG___RWC        QCSR_REG_RW    
#define   DBG_PHYFUN_PRIORITY_CTRL_REG___POR     0x00000000
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_PHYFUN_PRIORITY_CTRL_REG___M       0x0000003F   
#define   DBG_PHYFUN_PRIORITY_CTRL_REG___S                     0

#define DBG_PHYFUN_ITATBDATA0                     (0x00BBFEEC)
#define   DBG_PHYFUN_ITATBDATA0___RWC               QCSR_REG_RW    
#define   DBG_PHYFUN_ITATBDATA0___POR            0x00000000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA127___POR 0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA119___POR 0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA111___POR 0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA103___POR 0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA95___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA87___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA79___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA71___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA63___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA55___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA47___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA39___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA31___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA15___POR  0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA7___POR   0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA0___POR   0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA127___M   0x00010000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA127___S                16
#define   DBG_PHYFUN_ITATBDATA0__ATDATA127__ATDATA127_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA127__ATDATA127_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA119___M   0x00008000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA119___S                15
#define   DBG_PHYFUN_ITATBDATA0__ATDATA119__ATDATA119_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA119__ATDATA119_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA111___M   0x00004000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA111___S                14
#define   DBG_PHYFUN_ITATBDATA0__ATDATA111__ATDATA111_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA111__ATDATA111_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA103___M   0x00002000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA103___S                13
#define   DBG_PHYFUN_ITATBDATA0__ATDATA103__ATDATA103_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA103__ATDATA103_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA95___M    0x00001000
#define   DBG_PHYFUN_ITATBDATA0__ATDATA95___S                 12
#define   DBG_PHYFUN_ITATBDATA0__ATDATA95__ATDATA95_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA95__ATDATA95_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA87___M    0x00000800
#define   DBG_PHYFUN_ITATBDATA0__ATDATA87___S                 11
#define   DBG_PHYFUN_ITATBDATA0__ATDATA87__ATDATA87_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA87__ATDATA87_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA79___M    0x00000400
#define   DBG_PHYFUN_ITATBDATA0__ATDATA79___S                 10
#define   DBG_PHYFUN_ITATBDATA0__ATDATA79__ATDATA79_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA79__ATDATA79_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA71___M    0x00000200
#define   DBG_PHYFUN_ITATBDATA0__ATDATA71___S                  9
#define   DBG_PHYFUN_ITATBDATA0__ATDATA71__ATDATA71_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA71__ATDATA71_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA63___M    0x00000100
#define   DBG_PHYFUN_ITATBDATA0__ATDATA63___S                  8
#define   DBG_PHYFUN_ITATBDATA0__ATDATA63__ATDATA63_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA63__ATDATA63_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA55___M    0x00000080
#define   DBG_PHYFUN_ITATBDATA0__ATDATA55___S                  7
#define   DBG_PHYFUN_ITATBDATA0__ATDATA55__ATDATA55_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA55__ATDATA55_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA47___M    0x00000040
#define   DBG_PHYFUN_ITATBDATA0__ATDATA47___S                  6
#define   DBG_PHYFUN_ITATBDATA0__ATDATA47__ATDATA47_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA47__ATDATA47_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA39___M    0x00000020
#define   DBG_PHYFUN_ITATBDATA0__ATDATA39___S                  5
#define   DBG_PHYFUN_ITATBDATA0__ATDATA39__ATDATA39_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA39__ATDATA39_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA31___M    0x00000010
#define   DBG_PHYFUN_ITATBDATA0__ATDATA31___S                  4
#define   DBG_PHYFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATAM23___M   0x00000008
#define   DBG_PHYFUN_ITATBDATA0__ATDATAM23___S                 3
#define   DBG_PHYFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA15___M    0x00000004
#define   DBG_PHYFUN_ITATBDATA0__ATDATA15___S                  2
#define   DBG_PHYFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA7___M     0x00000002
#define   DBG_PHYFUN_ITATBDATA0__ATDATA7___S                   1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_PHYFUN_ITATBDATA0__ATDATA0___M     0x00000001
#define   DBG_PHYFUN_ITATBDATA0__ATDATA0___S                   0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_PHYFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_PHYFUN_ITATBDATA0___M              0x0001FFFF   
#define   DBG_PHYFUN_ITATBDATA0___S                            0

#define DBG_PHYFUN_ITATBCTR2                      (0x00BBFEF0)
#define   DBG_PHYFUN_ITATBCTR2___RWC                QCSR_REG_RW    
#define   DBG_PHYFUN_ITATBCTR2___POR             0x00000000
#define   DBG_PHYFUN_ITATBCTR2__AFVALID___POR    0x0
#define   DBG_PHYFUN_ITATBCTR2__ATREADY___POR    0x0
#define   DBG_PHYFUN_ITATBCTR2__AFVALID___M      0x00000002
#define   DBG_PHYFUN_ITATBCTR2__AFVALID___S                    1
#define   DBG_PHYFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_PHYFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_PHYFUN_ITATBCTR2__ATREADY___M      0x00000001
#define   DBG_PHYFUN_ITATBCTR2__ATREADY___S                    0
#define   DBG_PHYFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_PHYFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_PHYFUN_ITATBCTR2___M               0x00000003   
#define   DBG_PHYFUN_ITATBCTR2___S                             0

#define DBG_PHYFUN_ITATBCTR1                      (0x00BBFEF4)
#define   DBG_PHYFUN_ITATBCTR1___RWC                QCSR_REG_RW    
#define   DBG_PHYFUN_ITATBCTR1__ATID___M         0x0000007F
#define   DBG_PHYFUN_ITATBCTR1__ATID___S                       0
#define   DBG_PHYFUN_ITATBCTR1___M               0x0000007F   
#define   DBG_PHYFUN_ITATBCTR1___S                             0

#define DBG_PHYFUN_ITATBCTR0                      (0x00BBFEF8)
#define   DBG_PHYFUN_ITATBCTR0___RWC                QCSR_REG_RW    
#define   DBG_PHYFUN_ITATBCTR0___POR             0x00000000
#define   DBG_PHYFUN_ITATBCTR0__ATBYTES___POR    0x0
#define   DBG_PHYFUN_ITATBCTR0__AFREADY___POR    0x0
#define   DBG_PHYFUN_ITATBCTR0__ATVALID___POR    0x0
#define   DBG_PHYFUN_ITATBCTR0__ATBYTES___M      0x00000F00
#define   DBG_PHYFUN_ITATBCTR0__ATBYTES___S                    8
#define   DBG_PHYFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_PHYFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_PHYFUN_ITATBCTR0__AFREADY___M      0x00000002
#define   DBG_PHYFUN_ITATBCTR0__AFREADY___S                    1
#define   DBG_PHYFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_PHYFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_PHYFUN_ITATBCTR0__ATVALID___M      0x00000001
#define   DBG_PHYFUN_ITATBCTR0__ATVALID___S                    0
#define   DBG_PHYFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_PHYFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_PHYFUN_ITATBCTR0___M               0x00000F03   
#define   DBG_PHYFUN_ITATBCTR0___S                             0

#define DBG_PHYFUN_ITCTRL                         (0x00BBFF00)
#define   DBG_PHYFUN_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_PHYFUN_ITCTRL___POR                0x00000000
#define   DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_PHYFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_PHYFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_PHYFUN_ITCTRL___M                  0x00000001   
#define   DBG_PHYFUN_ITCTRL___S                                0

#define DBG_PHYFUN_CLAIMSET                       (0x00BBFFA0)
#define   DBG_PHYFUN_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_PHYFUN_CLAIMSET___POR              0x0000000F
#define   DBG_PHYFUN_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_PHYFUN_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_PHYFUN_CLAIMSET__CLAIMSET___S                    0
#define   DBG_PHYFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_PHYFUN_CLAIMSET___M                0x0000000F   
#define   DBG_PHYFUN_CLAIMSET___S                              0

#define DBG_PHYFUN_CLAIMCLR                       (0x00BBFFA4)
#define   DBG_PHYFUN_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_PHYFUN_CLAIMCLR___POR              0x00000000
#define   DBG_PHYFUN_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_PHYFUN_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_PHYFUN_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_PHYFUN_CLAIMCLR___M                0x0000000F   
#define   DBG_PHYFUN_CLAIMCLR___S                              0

#define DBG_PHYFUN_LOCKACCESS                     (0x00BBFFB0)
#define   DBG_PHYFUN_LOCKACCESS___RWC               QCSR_REG_WO    
#define   DBG_PHYFUN_LOCKACCESS__KEY___M         0xFFFFFFFF
#define   DBG_PHYFUN_LOCKACCESS__KEY___S                       0
#define   DBG_PHYFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_PHYFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_PHYFUN_LOCKACCESS___M              0xFFFFFFFF   
#define   DBG_PHYFUN_LOCKACCESS___S                            0

#define DBG_PHYFUN_LOCKSTATUS                     (0x00BBFFB4)
#define   DBG_PHYFUN_LOCKSTATUS___RWC               QCSR_REG_RO    
#define   DBG_PHYFUN_LOCKSTATUS___POR            0x00000003
#define   DBG_PHYFUN_LOCKSTATUS__NTT___POR       0x0
#define   DBG_PHYFUN_LOCKSTATUS__SLK___POR       0x1
#define   DBG_PHYFUN_LOCKSTATUS__SLI___POR       0x1
#define   DBG_PHYFUN_LOCKSTATUS__NTT___M         0x00000004
#define   DBG_PHYFUN_LOCKSTATUS__NTT___S                       2
#define   DBG_PHYFUN_LOCKSTATUS__NTT__NTT_0X0                0x0
#define   DBG_PHYFUN_LOCKSTATUS__SLK___M         0x00000002
#define   DBG_PHYFUN_LOCKSTATUS__SLK___S                       1
#define   DBG_PHYFUN_LOCKSTATUS__SLK__SLK_0X0                0x0
#define   DBG_PHYFUN_LOCKSTATUS__SLK__SLK_0X1                0x1
#define   DBG_PHYFUN_LOCKSTATUS__SLI___M         0x00000001
#define   DBG_PHYFUN_LOCKSTATUS__SLI___S                       0
#define   DBG_PHYFUN_LOCKSTATUS__SLI__SLI_0X0                0x0
#define   DBG_PHYFUN_LOCKSTATUS__SLI__SLI_0X1                0x1
#define   DBG_PHYFUN_LOCKSTATUS___M              0x00000007   
#define   DBG_PHYFUN_LOCKSTATUS___S                            0

#define DBG_PHYFUN_AUTHSTATUS                     (0x00BBFFB8)
#define   DBG_PHYFUN_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_PHYFUN_AUTHSTATUS___POR            0x00000000
#define   DBG_PHYFUN_AUTHSTATUS__SNID___POR      0x0
#define   DBG_PHYFUN_AUTHSTATUS__SID___POR       0x0
#define   DBG_PHYFUN_AUTHSTATUS__NSNID___POR     0x0
#define   DBG_PHYFUN_AUTHSTATUS__NSID___POR      0x0
#define   DBG_PHYFUN_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_PHYFUN_AUTHSTATUS__SNID___S                      6
#define   DBG_PHYFUN_AUTHSTATUS__SNID__SNID_0X0              0x0
#define   DBG_PHYFUN_AUTHSTATUS__SID___M         0x00000030
#define   DBG_PHYFUN_AUTHSTATUS__SID___S                       4
#define   DBG_PHYFUN_AUTHSTATUS__SID__SID_0X0                0x0
#define   DBG_PHYFUN_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_PHYFUN_AUTHSTATUS__NSNID___S                     2
#define   DBG_PHYFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_PHYFUN_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_PHYFUN_AUTHSTATUS__NSID___S                      0
#define   DBG_PHYFUN_AUTHSTATUS__NSID__NSID_0X0              0x0
#define   DBG_PHYFUN_AUTHSTATUS___M              0x000000FF   
#define   DBG_PHYFUN_AUTHSTATUS___S                            0

#define DBG_PHYFUN_DEVID                          (0x00BBFFC8)
#define   DBG_PHYFUN_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_DEVID___POR                 0x00000032
#define   DBG_PHYFUN_DEVID__SCHEME___POR         0x3
#define   DBG_PHYFUN_DEVID__PORTCOUNT___POR      0x2
#define   DBG_PHYFUN_DEVID__SCHEME___M           0x000000F0
#define   DBG_PHYFUN_DEVID__SCHEME___S                         4
#define   DBG_PHYFUN_DEVID__SCHEME__SCHEME_0X3               0x3
#define   DBG_PHYFUN_DEVID__PORTCOUNT___M        0x0000000F
#define   DBG_PHYFUN_DEVID__PORTCOUNT___S                      0
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_PHYFUN_DEVID___M                   0x000000FF   
#define   DBG_PHYFUN_DEVID___S                                 0

#define DBG_PHYFUN_DEVTYPE                        (0x00BBFFCC)
#define   DBG_PHYFUN_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_PHYFUN_DEVTYPE___POR               0x00000012
#define   DBG_PHYFUN_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___POR   0x2
#define   DBG_PHYFUN_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_PHYFUN_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_PHYFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_PHYFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_PHYFUN_DEVTYPE___M                 0x000000FF   
#define   DBG_PHYFUN_DEVTYPE___S                               0

#define DBG_PHYFUN_PIDR0                          (0x00BBFFE0)
#define   DBG_PHYFUN_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_PIDR0___POR                 0x00000008
#define   DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_PHYFUN_PIDR0___M                   0x000000FF   
#define   DBG_PHYFUN_PIDR0___S                                 0

#define DBG_PHYFUN_PIDR1                          (0x00BBFFE4)
#define   DBG_PHYFUN_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_PIDR1___POR                 0x000000B9
#define   DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___M  0x000000F0
#define   DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___S                4
#define   DBG_PHYFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_PHYFUN_PIDR1___M                   0x000000FF   
#define   DBG_PHYFUN_PIDR1___S                                 0

#define DBG_PHYFUN_PIDR2                          (0x00BBFFE8)
#define   DBG_PHYFUN_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_PIDR2___POR                 0x0000003B
#define   DBG_PHYFUN_PIDR2__REVISION___POR       0x3
#define   DBG_PHYFUN_PIDR2__JEDEC___POR          0x1
#define   DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_PHYFUN_PIDR2__REVISION___M         0x000000F0
#define   DBG_PHYFUN_PIDR2__REVISION___S                       4
#define   DBG_PHYFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_PHYFUN_PIDR2__JEDEC___M            0x00000008
#define   DBG_PHYFUN_PIDR2__JEDEC___S                          3
#define   DBG_PHYFUN_PIDR2__JEDEC__JEDEC_0X1                 0x1
#define   DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___M  0x00000007
#define   DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___S                0
#define   DBG_PHYFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_PHYFUN_PIDR2___M                   0x000000FF   
#define   DBG_PHYFUN_PIDR2___S                                 0

#define DBG_PHYFUN_PIDR3                          (0x00BBFFEC)
#define   DBG_PHYFUN_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_PIDR3___POR                 0x00000000
#define   DBG_PHYFUN_PIDR3__REVAND___POR         0x0
#define   DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYFUN_PIDR3__REVAND___M           0x000000F0
#define   DBG_PHYFUN_PIDR3__REVAND___S                         4
#define   DBG_PHYFUN_PIDR3__REVAND__REVAND_0X0               0x0
#define   DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_PHYFUN_PIDR3___M                   0x000000FF   
#define   DBG_PHYFUN_PIDR3___S                                 0

#define DBG_PHYFUN_PIDR4                          (0x00BBFFD0)
#define   DBG_PHYFUN_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_PHYFUN_PIDR4___POR                 0x00000004
#define   DBG_PHYFUN_PIDR4__FOURKB_COUNT___POR   0x0
#define   DBG_PHYFUN_PIDR4__JEP106_CONT___POR    0x4
#define   DBG_PHYFUN_PIDR4__FOURKB_COUNT___M     0x000000F0
#define   DBG_PHYFUN_PIDR4__FOURKB_COUNT___S                   4
#define   DBG_PHYFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_PHYFUN_PIDR4__JEP106_CONT___M      0x0000000F
#define   DBG_PHYFUN_PIDR4__JEP106_CONT___S                    0
#define   DBG_PHYFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_PHYFUN_PIDR4___M                   0x000000FF   
#define   DBG_PHYFUN_PIDR4___S                                 0

#define DBG_PHYFUN_PERIPHID5                      (0x00BBFFD4)
#define   DBG_PHYFUN_PERIPHID5___RWC                QCSR_REG_RO    
#define   DBG_PHYFUN_PERIPHID5___POR             0x00000000
#define   DBG_PHYFUN_PERIPHID5__PERIPHID5___POR  0x00000000
#define   DBG_PHYFUN_PERIPHID5__PERIPHID5___M    0xFFFFFFFF
#define   DBG_PHYFUN_PERIPHID5__PERIPHID5___S                  0
#define   DBG_PHYFUN_PERIPHID5___M               0xFFFFFFFF   
#define   DBG_PHYFUN_PERIPHID5___S                             0

#define DBG_PHYFUN_PERIPHID6                      (0x00BBFFD8)
#define   DBG_PHYFUN_PERIPHID6___RWC                QCSR_REG_RO    
#define   DBG_PHYFUN_PERIPHID6___POR             0x00000000
#define   DBG_PHYFUN_PERIPHID6__PERIPHID6___POR  0x00000000
#define   DBG_PHYFUN_PERIPHID6__PERIPHID6___M    0xFFFFFFFF
#define   DBG_PHYFUN_PERIPHID6__PERIPHID6___S                  0
#define   DBG_PHYFUN_PERIPHID6___M               0xFFFFFFFF   
#define   DBG_PHYFUN_PERIPHID6___S                             0

#define DBG_PHYFUN_PERIPHID7                      (0x00BBFFDC)
#define   DBG_PHYFUN_PERIPHID7___RWC                QCSR_REG_RO    
#define   DBG_PHYFUN_PERIPHID7___POR             0x00000000
#define   DBG_PHYFUN_PERIPHID7__PERIPHID7___POR  0x00000000
#define   DBG_PHYFUN_PERIPHID7__PERIPHID7___M    0xFFFFFFFF
#define   DBG_PHYFUN_PERIPHID7__PERIPHID7___S                  0
#define   DBG_PHYFUN_PERIPHID7___M               0xFFFFFFFF   
#define   DBG_PHYFUN_PERIPHID7___S                             0

#define DBG_PHYFUN_CID0                           (0x00BBFFF0)
#define   DBG_PHYFUN_CID0___RWC                     QCSR_REG_RO    
#define   DBG_PHYFUN_CID0___POR                  0x0000000D
#define   DBG_PHYFUN_CID0__PREAMBLE___POR        0x0D
#define   DBG_PHYFUN_CID0__PREAMBLE___M          0x000000FF
#define   DBG_PHYFUN_CID0__PREAMBLE___S                        0
#define   DBG_PHYFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_PHYFUN_CID0___M                    0x000000FF   
#define   DBG_PHYFUN_CID0___S                                  0

#define DBG_PHYFUN_CID1                           (0x00BBFFF4)
#define   DBG_PHYFUN_CID1___RWC                     QCSR_REG_RO    
#define   DBG_PHYFUN_CID1___POR                  0x00000090
#define   DBG_PHYFUN_CID1__CLASS___POR           0x9
#define   DBG_PHYFUN_CID1__PREAMBLE___POR        0x0
#define   DBG_PHYFUN_CID1__CLASS___M             0x000000F0
#define   DBG_PHYFUN_CID1__CLASS___S                           4
#define   DBG_PHYFUN_CID1__CLASS__CLASS_0X9                  0x9
#define   DBG_PHYFUN_CID1__PREAMBLE___M          0x0000000F
#define   DBG_PHYFUN_CID1__PREAMBLE___S                        0
#define   DBG_PHYFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_PHYFUN_CID1___M                    0x000000FF   
#define   DBG_PHYFUN_CID1___S                                  0

#define DBG_PHYFUN_CID2                           (0x00BBFFF8)
#define   DBG_PHYFUN_CID2___RWC                     QCSR_REG_RO    
#define   DBG_PHYFUN_CID2___POR                  0x00000005
#define   DBG_PHYFUN_CID2__PREAMBLE___POR        0x05
#define   DBG_PHYFUN_CID2__PREAMBLE___M          0x000000FF
#define   DBG_PHYFUN_CID2__PREAMBLE___S                        0
#define   DBG_PHYFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_PHYFUN_CID2___M                    0x000000FF   
#define   DBG_PHYFUN_CID2___S                                  0

#define DBG_PHYFUN_CID3                           (0x00BBFFFC)
#define   DBG_PHYFUN_CID3___RWC                     QCSR_REG_RO    
#define   DBG_PHYFUN_CID3___POR                  0x000000B1
#define   DBG_PHYFUN_CID3__PREAMBLE___POR        0xB1
#define   DBG_PHYFUN_CID3__PREAMBLE___M          0x000000FF
#define   DBG_PHYFUN_CID3__PREAMBLE___S                        0
#define   DBG_PHYFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_PHYFUN_CID3___M                    0x000000FF   
#define   DBG_PHYFUN_CID3___S                                  0

#define DBG_OUTDMUX_ATID_EN0                      (0x00BC0000)
#define   DBG_OUTDMUX_ATID_EN0___RWC                QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_EN0___POR             0xFFFFFFFF
#define   DBG_OUTDMUX_ATID_EN0__ATID31_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID30_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID29_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID28_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID27_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID26_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID25_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID24_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID23_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID22_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID21_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID20_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID19_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID18_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID17_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID16_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID15_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID14_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID13_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID12_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID11_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID10_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID9_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID8_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID7_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID6_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID5_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID4_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID3_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID2_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID1_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID0_EN___POR   0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID31_EN___M    0x80000000
#define   DBG_OUTDMUX_ATID_EN0__ATID31_EN___S                 31
#define   DBG_OUTDMUX_ATID_EN0__ATID31_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID31_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID30_EN___M    0x40000000
#define   DBG_OUTDMUX_ATID_EN0__ATID30_EN___S                 30
#define   DBG_OUTDMUX_ATID_EN0__ATID30_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID30_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID29_EN___M    0x20000000
#define   DBG_OUTDMUX_ATID_EN0__ATID29_EN___S                 29
#define   DBG_OUTDMUX_ATID_EN0__ATID29_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID29_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID28_EN___M    0x10000000
#define   DBG_OUTDMUX_ATID_EN0__ATID28_EN___S                 28
#define   DBG_OUTDMUX_ATID_EN0__ATID28_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID28_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID27_EN___M    0x08000000
#define   DBG_OUTDMUX_ATID_EN0__ATID27_EN___S                 27
#define   DBG_OUTDMUX_ATID_EN0__ATID27_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID27_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID26_EN___M    0x04000000
#define   DBG_OUTDMUX_ATID_EN0__ATID26_EN___S                 26
#define   DBG_OUTDMUX_ATID_EN0__ATID26_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID26_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID25_EN___M    0x02000000
#define   DBG_OUTDMUX_ATID_EN0__ATID25_EN___S                 25
#define   DBG_OUTDMUX_ATID_EN0__ATID25_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID25_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID24_EN___M    0x01000000
#define   DBG_OUTDMUX_ATID_EN0__ATID24_EN___S                 24
#define   DBG_OUTDMUX_ATID_EN0__ATID24_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID24_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID23_EN___M    0x00800000
#define   DBG_OUTDMUX_ATID_EN0__ATID23_EN___S                 23
#define   DBG_OUTDMUX_ATID_EN0__ATID23_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID23_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID22_EN___M    0x00400000
#define   DBG_OUTDMUX_ATID_EN0__ATID22_EN___S                 22
#define   DBG_OUTDMUX_ATID_EN0__ATID22_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID22_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID21_EN___M    0x00200000
#define   DBG_OUTDMUX_ATID_EN0__ATID21_EN___S                 21
#define   DBG_OUTDMUX_ATID_EN0__ATID21_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID21_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID20_EN___M    0x00100000
#define   DBG_OUTDMUX_ATID_EN0__ATID20_EN___S                 20
#define   DBG_OUTDMUX_ATID_EN0__ATID20_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID20_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID19_EN___M    0x00080000
#define   DBG_OUTDMUX_ATID_EN0__ATID19_EN___S                 19
#define   DBG_OUTDMUX_ATID_EN0__ATID19_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID19_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID18_EN___M    0x00040000
#define   DBG_OUTDMUX_ATID_EN0__ATID18_EN___S                 18
#define   DBG_OUTDMUX_ATID_EN0__ATID18_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID18_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID17_EN___M    0x00020000
#define   DBG_OUTDMUX_ATID_EN0__ATID17_EN___S                 17
#define   DBG_OUTDMUX_ATID_EN0__ATID17_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID17_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID16_EN___M    0x00010000
#define   DBG_OUTDMUX_ATID_EN0__ATID16_EN___S                 16
#define   DBG_OUTDMUX_ATID_EN0__ATID16_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID16_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID15_EN___M    0x00008000
#define   DBG_OUTDMUX_ATID_EN0__ATID15_EN___S                 15
#define   DBG_OUTDMUX_ATID_EN0__ATID15_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID15_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID14_EN___M    0x00004000
#define   DBG_OUTDMUX_ATID_EN0__ATID14_EN___S                 14
#define   DBG_OUTDMUX_ATID_EN0__ATID14_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID14_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID13_EN___M    0x00002000
#define   DBG_OUTDMUX_ATID_EN0__ATID13_EN___S                 13
#define   DBG_OUTDMUX_ATID_EN0__ATID13_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID13_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID12_EN___M    0x00001000
#define   DBG_OUTDMUX_ATID_EN0__ATID12_EN___S                 12
#define   DBG_OUTDMUX_ATID_EN0__ATID12_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID12_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID11_EN___M    0x00000800
#define   DBG_OUTDMUX_ATID_EN0__ATID11_EN___S                 11
#define   DBG_OUTDMUX_ATID_EN0__ATID11_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID11_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID10_EN___M    0x00000400
#define   DBG_OUTDMUX_ATID_EN0__ATID10_EN___S                 10
#define   DBG_OUTDMUX_ATID_EN0__ATID10_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID10_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID9_EN___M     0x00000200
#define   DBG_OUTDMUX_ATID_EN0__ATID9_EN___S                   9
#define   DBG_OUTDMUX_ATID_EN0__ATID9_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID9_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID8_EN___M     0x00000100
#define   DBG_OUTDMUX_ATID_EN0__ATID8_EN___S                   8
#define   DBG_OUTDMUX_ATID_EN0__ATID8_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID8_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID7_EN___M     0x00000080
#define   DBG_OUTDMUX_ATID_EN0__ATID7_EN___S                   7
#define   DBG_OUTDMUX_ATID_EN0__ATID7_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID7_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID6_EN___M     0x00000040
#define   DBG_OUTDMUX_ATID_EN0__ATID6_EN___S                   6
#define   DBG_OUTDMUX_ATID_EN0__ATID6_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID6_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID5_EN___M     0x00000020
#define   DBG_OUTDMUX_ATID_EN0__ATID5_EN___S                   5
#define   DBG_OUTDMUX_ATID_EN0__ATID5_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID5_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID4_EN___M     0x00000010
#define   DBG_OUTDMUX_ATID_EN0__ATID4_EN___S                   4
#define   DBG_OUTDMUX_ATID_EN0__ATID4_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID4_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID3_EN___M     0x00000008
#define   DBG_OUTDMUX_ATID_EN0__ATID3_EN___S                   3
#define   DBG_OUTDMUX_ATID_EN0__ATID3_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID3_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID2_EN___M     0x00000004
#define   DBG_OUTDMUX_ATID_EN0__ATID2_EN___S                   2
#define   DBG_OUTDMUX_ATID_EN0__ATID2_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID2_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID1_EN___M     0x00000002
#define   DBG_OUTDMUX_ATID_EN0__ATID1_EN___S                   1
#define   DBG_OUTDMUX_ATID_EN0__ATID1_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID1_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0__ATID0_EN___M     0x00000001
#define   DBG_OUTDMUX_ATID_EN0__ATID0_EN___S                   0
#define   DBG_OUTDMUX_ATID_EN0__ATID0_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN0__ATID0_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN0___M               0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_EN0___S                             0

#define DBG_OUTDMUX_ATID_EN1                      (0x00BC0004)
#define   DBG_OUTDMUX_ATID_EN1___RWC                QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_EN1___POR             0xFFFFFFFF
#define   DBG_OUTDMUX_ATID_EN1__ATID63_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID62_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID61_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID60_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID59_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID58_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID57_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID56_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID55_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID54_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID53_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID52_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID51_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID50_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID49_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID48_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID47_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID46_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID45_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID44_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID43_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID42_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID41_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID40_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID39_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID38_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID37_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID36_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID35_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID34_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID33_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID32_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID63_EN___M    0x80000000
#define   DBG_OUTDMUX_ATID_EN1__ATID63_EN___S                 31
#define   DBG_OUTDMUX_ATID_EN1__ATID63_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID63_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID62_EN___M    0x40000000
#define   DBG_OUTDMUX_ATID_EN1__ATID62_EN___S                 30
#define   DBG_OUTDMUX_ATID_EN1__ATID62_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID62_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID61_EN___M    0x20000000
#define   DBG_OUTDMUX_ATID_EN1__ATID61_EN___S                 29
#define   DBG_OUTDMUX_ATID_EN1__ATID61_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID61_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID60_EN___M    0x10000000
#define   DBG_OUTDMUX_ATID_EN1__ATID60_EN___S                 28
#define   DBG_OUTDMUX_ATID_EN1__ATID60_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID60_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID59_EN___M    0x08000000
#define   DBG_OUTDMUX_ATID_EN1__ATID59_EN___S                 27
#define   DBG_OUTDMUX_ATID_EN1__ATID59_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID59_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID58_EN___M    0x04000000
#define   DBG_OUTDMUX_ATID_EN1__ATID58_EN___S                 26
#define   DBG_OUTDMUX_ATID_EN1__ATID58_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID58_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID57_EN___M    0x02000000
#define   DBG_OUTDMUX_ATID_EN1__ATID57_EN___S                 25
#define   DBG_OUTDMUX_ATID_EN1__ATID57_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID57_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID56_EN___M    0x01000000
#define   DBG_OUTDMUX_ATID_EN1__ATID56_EN___S                 24
#define   DBG_OUTDMUX_ATID_EN1__ATID56_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID56_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID55_EN___M    0x00800000
#define   DBG_OUTDMUX_ATID_EN1__ATID55_EN___S                 23
#define   DBG_OUTDMUX_ATID_EN1__ATID55_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID55_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID54_EN___M    0x00400000
#define   DBG_OUTDMUX_ATID_EN1__ATID54_EN___S                 22
#define   DBG_OUTDMUX_ATID_EN1__ATID54_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID54_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID53_EN___M    0x00200000
#define   DBG_OUTDMUX_ATID_EN1__ATID53_EN___S                 21
#define   DBG_OUTDMUX_ATID_EN1__ATID53_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID53_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID52_EN___M    0x00100000
#define   DBG_OUTDMUX_ATID_EN1__ATID52_EN___S                 20
#define   DBG_OUTDMUX_ATID_EN1__ATID52_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID52_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID51_EN___M    0x00080000
#define   DBG_OUTDMUX_ATID_EN1__ATID51_EN___S                 19
#define   DBG_OUTDMUX_ATID_EN1__ATID51_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID51_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID50_EN___M    0x00040000
#define   DBG_OUTDMUX_ATID_EN1__ATID50_EN___S                 18
#define   DBG_OUTDMUX_ATID_EN1__ATID50_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID50_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID49_EN___M    0x00020000
#define   DBG_OUTDMUX_ATID_EN1__ATID49_EN___S                 17
#define   DBG_OUTDMUX_ATID_EN1__ATID49_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID49_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID48_EN___M    0x00010000
#define   DBG_OUTDMUX_ATID_EN1__ATID48_EN___S                 16
#define   DBG_OUTDMUX_ATID_EN1__ATID48_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID48_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID47_EN___M    0x00008000
#define   DBG_OUTDMUX_ATID_EN1__ATID47_EN___S                 15
#define   DBG_OUTDMUX_ATID_EN1__ATID47_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID47_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID46_EN___M    0x00004000
#define   DBG_OUTDMUX_ATID_EN1__ATID46_EN___S                 14
#define   DBG_OUTDMUX_ATID_EN1__ATID46_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID46_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID45_EN___M    0x00002000
#define   DBG_OUTDMUX_ATID_EN1__ATID45_EN___S                 13
#define   DBG_OUTDMUX_ATID_EN1__ATID45_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID45_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID44_EN___M    0x00001000
#define   DBG_OUTDMUX_ATID_EN1__ATID44_EN___S                 12
#define   DBG_OUTDMUX_ATID_EN1__ATID44_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID44_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID43_EN___M    0x00000800
#define   DBG_OUTDMUX_ATID_EN1__ATID43_EN___S                 11
#define   DBG_OUTDMUX_ATID_EN1__ATID43_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID43_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID42_EN___M    0x00000400
#define   DBG_OUTDMUX_ATID_EN1__ATID42_EN___S                 10
#define   DBG_OUTDMUX_ATID_EN1__ATID42_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID42_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID41_EN___M    0x00000200
#define   DBG_OUTDMUX_ATID_EN1__ATID41_EN___S                  9
#define   DBG_OUTDMUX_ATID_EN1__ATID41_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID41_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID40_EN___M    0x00000100
#define   DBG_OUTDMUX_ATID_EN1__ATID40_EN___S                  8
#define   DBG_OUTDMUX_ATID_EN1__ATID40_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID40_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID39_EN___M    0x00000080
#define   DBG_OUTDMUX_ATID_EN1__ATID39_EN___S                  7
#define   DBG_OUTDMUX_ATID_EN1__ATID39_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID39_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID38_EN___M    0x00000040
#define   DBG_OUTDMUX_ATID_EN1__ATID38_EN___S                  6
#define   DBG_OUTDMUX_ATID_EN1__ATID38_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID38_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID37_EN___M    0x00000020
#define   DBG_OUTDMUX_ATID_EN1__ATID37_EN___S                  5
#define   DBG_OUTDMUX_ATID_EN1__ATID37_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID37_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID36_EN___M    0x00000010
#define   DBG_OUTDMUX_ATID_EN1__ATID36_EN___S                  4
#define   DBG_OUTDMUX_ATID_EN1__ATID36_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID36_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID35_EN___M    0x00000008
#define   DBG_OUTDMUX_ATID_EN1__ATID35_EN___S                  3
#define   DBG_OUTDMUX_ATID_EN1__ATID35_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID35_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID34_EN___M    0x00000004
#define   DBG_OUTDMUX_ATID_EN1__ATID34_EN___S                  2
#define   DBG_OUTDMUX_ATID_EN1__ATID34_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID34_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID33_EN___M    0x00000002
#define   DBG_OUTDMUX_ATID_EN1__ATID33_EN___S                  1
#define   DBG_OUTDMUX_ATID_EN1__ATID33_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID33_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1__ATID32_EN___M    0x00000001
#define   DBG_OUTDMUX_ATID_EN1__ATID32_EN___S                  0
#define   DBG_OUTDMUX_ATID_EN1__ATID32_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN1__ATID32_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN1___M               0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_EN1___S                             0

#define DBG_OUTDMUX_ATID_EN2                      (0x00BC0008)
#define   DBG_OUTDMUX_ATID_EN2___RWC                QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_EN2___POR             0xFFFFFFFF
#define   DBG_OUTDMUX_ATID_EN2__ATID95_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID94_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID93_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID92_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID91_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID90_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID89_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID88_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID87_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID86_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID85_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID84_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID83_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID82_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID81_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID80_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID79_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID78_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID77_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID76_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID75_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID74_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID73_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID72_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID71_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID70_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID69_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID68_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID67_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID66_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID65_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID64_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID95_EN___M    0x80000000
#define   DBG_OUTDMUX_ATID_EN2__ATID95_EN___S                 31
#define   DBG_OUTDMUX_ATID_EN2__ATID95_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID95_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID94_EN___M    0x40000000
#define   DBG_OUTDMUX_ATID_EN2__ATID94_EN___S                 30
#define   DBG_OUTDMUX_ATID_EN2__ATID94_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID94_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID93_EN___M    0x20000000
#define   DBG_OUTDMUX_ATID_EN2__ATID93_EN___S                 29
#define   DBG_OUTDMUX_ATID_EN2__ATID93_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID93_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID92_EN___M    0x10000000
#define   DBG_OUTDMUX_ATID_EN2__ATID92_EN___S                 28
#define   DBG_OUTDMUX_ATID_EN2__ATID92_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID92_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID91_EN___M    0x08000000
#define   DBG_OUTDMUX_ATID_EN2__ATID91_EN___S                 27
#define   DBG_OUTDMUX_ATID_EN2__ATID91_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID91_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID90_EN___M    0x04000000
#define   DBG_OUTDMUX_ATID_EN2__ATID90_EN___S                 26
#define   DBG_OUTDMUX_ATID_EN2__ATID90_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID90_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID89_EN___M    0x02000000
#define   DBG_OUTDMUX_ATID_EN2__ATID89_EN___S                 25
#define   DBG_OUTDMUX_ATID_EN2__ATID89_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID89_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID88_EN___M    0x01000000
#define   DBG_OUTDMUX_ATID_EN2__ATID88_EN___S                 24
#define   DBG_OUTDMUX_ATID_EN2__ATID88_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID88_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID87_EN___M    0x00800000
#define   DBG_OUTDMUX_ATID_EN2__ATID87_EN___S                 23
#define   DBG_OUTDMUX_ATID_EN2__ATID87_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID87_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID86_EN___M    0x00400000
#define   DBG_OUTDMUX_ATID_EN2__ATID86_EN___S                 22
#define   DBG_OUTDMUX_ATID_EN2__ATID86_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID86_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID85_EN___M    0x00200000
#define   DBG_OUTDMUX_ATID_EN2__ATID85_EN___S                 21
#define   DBG_OUTDMUX_ATID_EN2__ATID85_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID85_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID84_EN___M    0x00100000
#define   DBG_OUTDMUX_ATID_EN2__ATID84_EN___S                 20
#define   DBG_OUTDMUX_ATID_EN2__ATID84_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID84_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID83_EN___M    0x00080000
#define   DBG_OUTDMUX_ATID_EN2__ATID83_EN___S                 19
#define   DBG_OUTDMUX_ATID_EN2__ATID83_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID83_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID82_EN___M    0x00040000
#define   DBG_OUTDMUX_ATID_EN2__ATID82_EN___S                 18
#define   DBG_OUTDMUX_ATID_EN2__ATID82_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID82_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID81_EN___M    0x00020000
#define   DBG_OUTDMUX_ATID_EN2__ATID81_EN___S                 17
#define   DBG_OUTDMUX_ATID_EN2__ATID81_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID81_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID80_EN___M    0x00010000
#define   DBG_OUTDMUX_ATID_EN2__ATID80_EN___S                 16
#define   DBG_OUTDMUX_ATID_EN2__ATID80_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID80_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID79_EN___M    0x00008000
#define   DBG_OUTDMUX_ATID_EN2__ATID79_EN___S                 15
#define   DBG_OUTDMUX_ATID_EN2__ATID79_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID79_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID78_EN___M    0x00004000
#define   DBG_OUTDMUX_ATID_EN2__ATID78_EN___S                 14
#define   DBG_OUTDMUX_ATID_EN2__ATID78_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID78_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID77_EN___M    0x00002000
#define   DBG_OUTDMUX_ATID_EN2__ATID77_EN___S                 13
#define   DBG_OUTDMUX_ATID_EN2__ATID77_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID77_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID76_EN___M    0x00001000
#define   DBG_OUTDMUX_ATID_EN2__ATID76_EN___S                 12
#define   DBG_OUTDMUX_ATID_EN2__ATID76_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID76_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID75_EN___M    0x00000800
#define   DBG_OUTDMUX_ATID_EN2__ATID75_EN___S                 11
#define   DBG_OUTDMUX_ATID_EN2__ATID75_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID75_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID74_EN___M    0x00000400
#define   DBG_OUTDMUX_ATID_EN2__ATID74_EN___S                 10
#define   DBG_OUTDMUX_ATID_EN2__ATID74_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID74_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID73_EN___M    0x00000200
#define   DBG_OUTDMUX_ATID_EN2__ATID73_EN___S                  9
#define   DBG_OUTDMUX_ATID_EN2__ATID73_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID73_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID72_EN___M    0x00000100
#define   DBG_OUTDMUX_ATID_EN2__ATID72_EN___S                  8
#define   DBG_OUTDMUX_ATID_EN2__ATID72_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID72_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID71_EN___M    0x00000080
#define   DBG_OUTDMUX_ATID_EN2__ATID71_EN___S                  7
#define   DBG_OUTDMUX_ATID_EN2__ATID71_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID71_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID70_EN___M    0x00000040
#define   DBG_OUTDMUX_ATID_EN2__ATID70_EN___S                  6
#define   DBG_OUTDMUX_ATID_EN2__ATID70_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID70_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID69_EN___M    0x00000020
#define   DBG_OUTDMUX_ATID_EN2__ATID69_EN___S                  5
#define   DBG_OUTDMUX_ATID_EN2__ATID69_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID69_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID68_EN___M    0x00000010
#define   DBG_OUTDMUX_ATID_EN2__ATID68_EN___S                  4
#define   DBG_OUTDMUX_ATID_EN2__ATID68_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID68_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID67_EN___M    0x00000008
#define   DBG_OUTDMUX_ATID_EN2__ATID67_EN___S                  3
#define   DBG_OUTDMUX_ATID_EN2__ATID67_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID67_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID66_EN___M    0x00000004
#define   DBG_OUTDMUX_ATID_EN2__ATID66_EN___S                  2
#define   DBG_OUTDMUX_ATID_EN2__ATID66_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID66_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID65_EN___M    0x00000002
#define   DBG_OUTDMUX_ATID_EN2__ATID65_EN___S                  1
#define   DBG_OUTDMUX_ATID_EN2__ATID65_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID65_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2__ATID64_EN___M    0x00000001
#define   DBG_OUTDMUX_ATID_EN2__ATID64_EN___S                  0
#define   DBG_OUTDMUX_ATID_EN2__ATID64_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN2__ATID64_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN2___M               0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_EN2___S                             0

#define DBG_OUTDMUX_ATID_EN3                      (0x00BC000C)
#define   DBG_OUTDMUX_ATID_EN3___RWC                QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_EN3___POR             0xFFFFFFFF
#define   DBG_OUTDMUX_ATID_EN3__ATID127_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID126_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID125_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID124_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID123_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID122_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID121_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID120_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID119_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID118_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID117_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID116_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID115_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID114_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID113_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID112_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID111_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID110_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID109_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID108_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID107_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID106_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID105_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID104_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID103_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID102_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID101_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID100_EN___POR 0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID99_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID98_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID97_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID96_EN___POR  0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID127_EN___M   0x80000000
#define   DBG_OUTDMUX_ATID_EN3__ATID127_EN___S                31
#define   DBG_OUTDMUX_ATID_EN3__ATID127_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID127_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID126_EN___M   0x40000000
#define   DBG_OUTDMUX_ATID_EN3__ATID126_EN___S                30
#define   DBG_OUTDMUX_ATID_EN3__ATID126_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID126_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID125_EN___M   0x20000000
#define   DBG_OUTDMUX_ATID_EN3__ATID125_EN___S                29
#define   DBG_OUTDMUX_ATID_EN3__ATID125_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID125_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID124_EN___M   0x10000000
#define   DBG_OUTDMUX_ATID_EN3__ATID124_EN___S                28
#define   DBG_OUTDMUX_ATID_EN3__ATID124_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID124_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID123_EN___M   0x08000000
#define   DBG_OUTDMUX_ATID_EN3__ATID123_EN___S                27
#define   DBG_OUTDMUX_ATID_EN3__ATID123_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID123_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID122_EN___M   0x04000000
#define   DBG_OUTDMUX_ATID_EN3__ATID122_EN___S                26
#define   DBG_OUTDMUX_ATID_EN3__ATID122_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID122_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID121_EN___M   0x02000000
#define   DBG_OUTDMUX_ATID_EN3__ATID121_EN___S                25
#define   DBG_OUTDMUX_ATID_EN3__ATID121_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID121_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID120_EN___M   0x01000000
#define   DBG_OUTDMUX_ATID_EN3__ATID120_EN___S                24
#define   DBG_OUTDMUX_ATID_EN3__ATID120_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID120_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID119_EN___M   0x00800000
#define   DBG_OUTDMUX_ATID_EN3__ATID119_EN___S                23
#define   DBG_OUTDMUX_ATID_EN3__ATID119_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID119_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID118_EN___M   0x00400000
#define   DBG_OUTDMUX_ATID_EN3__ATID118_EN___S                22
#define   DBG_OUTDMUX_ATID_EN3__ATID118_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID118_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID117_EN___M   0x00200000
#define   DBG_OUTDMUX_ATID_EN3__ATID117_EN___S                21
#define   DBG_OUTDMUX_ATID_EN3__ATID117_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID117_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID116_EN___M   0x00100000
#define   DBG_OUTDMUX_ATID_EN3__ATID116_EN___S                20
#define   DBG_OUTDMUX_ATID_EN3__ATID116_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID116_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID115_EN___M   0x00080000
#define   DBG_OUTDMUX_ATID_EN3__ATID115_EN___S                19
#define   DBG_OUTDMUX_ATID_EN3__ATID115_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID115_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID114_EN___M   0x00040000
#define   DBG_OUTDMUX_ATID_EN3__ATID114_EN___S                18
#define   DBG_OUTDMUX_ATID_EN3__ATID114_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID114_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID113_EN___M   0x00020000
#define   DBG_OUTDMUX_ATID_EN3__ATID113_EN___S                17
#define   DBG_OUTDMUX_ATID_EN3__ATID113_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID113_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID112_EN___M   0x00010000
#define   DBG_OUTDMUX_ATID_EN3__ATID112_EN___S                16
#define   DBG_OUTDMUX_ATID_EN3__ATID112_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID112_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID111_EN___M   0x00008000
#define   DBG_OUTDMUX_ATID_EN3__ATID111_EN___S                15
#define   DBG_OUTDMUX_ATID_EN3__ATID111_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID111_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID110_EN___M   0x00004000
#define   DBG_OUTDMUX_ATID_EN3__ATID110_EN___S                14
#define   DBG_OUTDMUX_ATID_EN3__ATID110_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID110_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID109_EN___M   0x00002000
#define   DBG_OUTDMUX_ATID_EN3__ATID109_EN___S                13
#define   DBG_OUTDMUX_ATID_EN3__ATID109_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID109_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID108_EN___M   0x00001000
#define   DBG_OUTDMUX_ATID_EN3__ATID108_EN___S                12
#define   DBG_OUTDMUX_ATID_EN3__ATID108_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID108_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID107_EN___M   0x00000800
#define   DBG_OUTDMUX_ATID_EN3__ATID107_EN___S                11
#define   DBG_OUTDMUX_ATID_EN3__ATID107_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID107_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID106_EN___M   0x00000400
#define   DBG_OUTDMUX_ATID_EN3__ATID106_EN___S                10
#define   DBG_OUTDMUX_ATID_EN3__ATID106_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID106_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID105_EN___M   0x00000200
#define   DBG_OUTDMUX_ATID_EN3__ATID105_EN___S                 9
#define   DBG_OUTDMUX_ATID_EN3__ATID105_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID105_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID104_EN___M   0x00000100
#define   DBG_OUTDMUX_ATID_EN3__ATID104_EN___S                 8
#define   DBG_OUTDMUX_ATID_EN3__ATID104_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID104_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID103_EN___M   0x00000080
#define   DBG_OUTDMUX_ATID_EN3__ATID103_EN___S                 7
#define   DBG_OUTDMUX_ATID_EN3__ATID103_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID103_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID102_EN___M   0x00000040
#define   DBG_OUTDMUX_ATID_EN3__ATID102_EN___S                 6
#define   DBG_OUTDMUX_ATID_EN3__ATID102_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID102_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID101_EN___M   0x00000020
#define   DBG_OUTDMUX_ATID_EN3__ATID101_EN___S                 5
#define   DBG_OUTDMUX_ATID_EN3__ATID101_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID101_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID100_EN___M   0x00000010
#define   DBG_OUTDMUX_ATID_EN3__ATID100_EN___S                 4
#define   DBG_OUTDMUX_ATID_EN3__ATID100_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID100_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID99_EN___M    0x00000008
#define   DBG_OUTDMUX_ATID_EN3__ATID99_EN___S                  3
#define   DBG_OUTDMUX_ATID_EN3__ATID99_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID99_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID98_EN___M    0x00000004
#define   DBG_OUTDMUX_ATID_EN3__ATID98_EN___S                  2
#define   DBG_OUTDMUX_ATID_EN3__ATID98_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID98_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID97_EN___M    0x00000002
#define   DBG_OUTDMUX_ATID_EN3__ATID97_EN___S                  1
#define   DBG_OUTDMUX_ATID_EN3__ATID97_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID97_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3__ATID96_EN___M    0x00000001
#define   DBG_OUTDMUX_ATID_EN3__ATID96_EN___S                  0
#define   DBG_OUTDMUX_ATID_EN3__ATID96_EN__DISABLE             0x0
#define   DBG_OUTDMUX_ATID_EN3__ATID96_EN__ENABLE             0x1
#define   DBG_OUTDMUX_ATID_EN3___M               0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_EN3___S                             0

#define DBG_OUTDMUX_ATID_SEL0                     (0x00BC0010)
#define   DBG_OUTDMUX_ATID_SEL0___RWC               QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_SEL0___POR            0x00000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___M  0x80000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___S               31
#define   DBG_OUTDMUX_ATID_SEL0__ATID31_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID31_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___M  0x40000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___S               30
#define   DBG_OUTDMUX_ATID_SEL0__ATID30_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID30_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___M  0x20000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___S               29
#define   DBG_OUTDMUX_ATID_SEL0__ATID29_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID29_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___M  0x10000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___S               28
#define   DBG_OUTDMUX_ATID_SEL0__ATID28_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID28_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___M  0x08000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___S               27
#define   DBG_OUTDMUX_ATID_SEL0__ATID27_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID27_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___M  0x04000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___S               26
#define   DBG_OUTDMUX_ATID_SEL0__ATID26_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID26_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___M  0x02000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___S               25
#define   DBG_OUTDMUX_ATID_SEL0__ATID25_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID25_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___M  0x01000000
#define   DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___S               24
#define   DBG_OUTDMUX_ATID_SEL0__ATID24_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID24_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___M  0x00800000
#define   DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___S               23
#define   DBG_OUTDMUX_ATID_SEL0__ATID23_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID23_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___M  0x00400000
#define   DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___S               22
#define   DBG_OUTDMUX_ATID_SEL0__ATID22_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID22_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___M  0x00200000
#define   DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___S               21
#define   DBG_OUTDMUX_ATID_SEL0__ATID21_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID21_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___M  0x00100000
#define   DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___S               20
#define   DBG_OUTDMUX_ATID_SEL0__ATID20_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID20_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___M  0x00080000
#define   DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___S               19
#define   DBG_OUTDMUX_ATID_SEL0__ATID19_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID19_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___M  0x00040000
#define   DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___S               18
#define   DBG_OUTDMUX_ATID_SEL0__ATID18_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID18_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___M  0x00020000
#define   DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___S               17
#define   DBG_OUTDMUX_ATID_SEL0__ATID17_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID17_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___M  0x00010000
#define   DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___S               16
#define   DBG_OUTDMUX_ATID_SEL0__ATID16_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID16_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___M  0x00008000
#define   DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___S               15
#define   DBG_OUTDMUX_ATID_SEL0__ATID15_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID15_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___M  0x00004000
#define   DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___S               14
#define   DBG_OUTDMUX_ATID_SEL0__ATID14_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID14_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___M  0x00002000
#define   DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___S               13
#define   DBG_OUTDMUX_ATID_SEL0__ATID13_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID13_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___M  0x00001000
#define   DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___S               12
#define   DBG_OUTDMUX_ATID_SEL0__ATID12_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID12_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___M  0x00000800
#define   DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___S               11
#define   DBG_OUTDMUX_ATID_SEL0__ATID11_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID11_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___M  0x00000400
#define   DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___S               10
#define   DBG_OUTDMUX_ATID_SEL0__ATID10_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID10_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___M   0x00000200
#define   DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___S                 9
#define   DBG_OUTDMUX_ATID_SEL0__ATID9_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID9_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___M   0x00000100
#define   DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___S                 8
#define   DBG_OUTDMUX_ATID_SEL0__ATID8_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID8_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___M   0x00000080
#define   DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___S                 7
#define   DBG_OUTDMUX_ATID_SEL0__ATID7_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID7_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___M   0x00000040
#define   DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___S                 6
#define   DBG_OUTDMUX_ATID_SEL0__ATID6_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID6_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___M   0x00000020
#define   DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___S                 5
#define   DBG_OUTDMUX_ATID_SEL0__ATID5_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID5_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___M   0x00000010
#define   DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___S                 4
#define   DBG_OUTDMUX_ATID_SEL0__ATID4_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID4_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___M   0x00000008
#define   DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___S                 3
#define   DBG_OUTDMUX_ATID_SEL0__ATID3_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID3_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___M   0x00000004
#define   DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___S                 2
#define   DBG_OUTDMUX_ATID_SEL0__ATID2_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID2_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___M   0x00000002
#define   DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___S                 1
#define   DBG_OUTDMUX_ATID_SEL0__ATID1_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID1_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___M   0x00000001
#define   DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___S                 0
#define   DBG_OUTDMUX_ATID_SEL0__ATID0_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL0__ATID0_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL0___M              0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_SEL0___S                            0

#define DBG_OUTDMUX_ATID_SEL1                     (0x00BC0014)
#define   DBG_OUTDMUX_ATID_SEL1___RWC               QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_SEL1___POR            0x00000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___M  0x80000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___S               31
#define   DBG_OUTDMUX_ATID_SEL1__ATID63_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID63_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___M  0x40000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___S               30
#define   DBG_OUTDMUX_ATID_SEL1__ATID62_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID62_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___M  0x20000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___S               29
#define   DBG_OUTDMUX_ATID_SEL1__ATID61_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID61_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___M  0x10000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___S               28
#define   DBG_OUTDMUX_ATID_SEL1__ATID60_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID60_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___M  0x08000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___S               27
#define   DBG_OUTDMUX_ATID_SEL1__ATID59_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID59_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___M  0x04000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___S               26
#define   DBG_OUTDMUX_ATID_SEL1__ATID58_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID58_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___M  0x02000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___S               25
#define   DBG_OUTDMUX_ATID_SEL1__ATID57_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID57_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___M  0x01000000
#define   DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___S               24
#define   DBG_OUTDMUX_ATID_SEL1__ATID56_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID56_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___M  0x00800000
#define   DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___S               23
#define   DBG_OUTDMUX_ATID_SEL1__ATID55_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID55_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___M  0x00400000
#define   DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___S               22
#define   DBG_OUTDMUX_ATID_SEL1__ATID54_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID54_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___M  0x00200000
#define   DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___S               21
#define   DBG_OUTDMUX_ATID_SEL1__ATID53_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID53_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___M  0x00100000
#define   DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___S               20
#define   DBG_OUTDMUX_ATID_SEL1__ATID52_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID52_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___M  0x00080000
#define   DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___S               19
#define   DBG_OUTDMUX_ATID_SEL1__ATID51_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID51_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___M  0x00040000
#define   DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___S               18
#define   DBG_OUTDMUX_ATID_SEL1__ATID50_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID50_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___M  0x00020000
#define   DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___S               17
#define   DBG_OUTDMUX_ATID_SEL1__ATID49_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID49_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___M  0x00010000
#define   DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___S               16
#define   DBG_OUTDMUX_ATID_SEL1__ATID48_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID48_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___M  0x00008000
#define   DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___S               15
#define   DBG_OUTDMUX_ATID_SEL1__ATID47_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID47_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___M  0x00004000
#define   DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___S               14
#define   DBG_OUTDMUX_ATID_SEL1__ATID46_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID46_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___M  0x00002000
#define   DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___S               13
#define   DBG_OUTDMUX_ATID_SEL1__ATID45_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID45_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___M  0x00001000
#define   DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___S               12
#define   DBG_OUTDMUX_ATID_SEL1__ATID44_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID44_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___M  0x00000800
#define   DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___S               11
#define   DBG_OUTDMUX_ATID_SEL1__ATID43_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID43_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___M  0x00000400
#define   DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___S               10
#define   DBG_OUTDMUX_ATID_SEL1__ATID42_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID42_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___M  0x00000200
#define   DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___S                9
#define   DBG_OUTDMUX_ATID_SEL1__ATID41_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID41_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___M  0x00000100
#define   DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___S                8
#define   DBG_OUTDMUX_ATID_SEL1__ATID40_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID40_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___M  0x00000080
#define   DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___S                7
#define   DBG_OUTDMUX_ATID_SEL1__ATID39_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID39_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___M  0x00000040
#define   DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___S                6
#define   DBG_OUTDMUX_ATID_SEL1__ATID38_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID38_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___M  0x00000020
#define   DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___S                5
#define   DBG_OUTDMUX_ATID_SEL1__ATID37_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID37_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___M  0x00000010
#define   DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___S                4
#define   DBG_OUTDMUX_ATID_SEL1__ATID36_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID36_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___M  0x00000008
#define   DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___S                3
#define   DBG_OUTDMUX_ATID_SEL1__ATID35_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID35_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___M  0x00000004
#define   DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___S                2
#define   DBG_OUTDMUX_ATID_SEL1__ATID34_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID34_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___M  0x00000002
#define   DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___S                1
#define   DBG_OUTDMUX_ATID_SEL1__ATID33_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID33_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___M  0x00000001
#define   DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___S                0
#define   DBG_OUTDMUX_ATID_SEL1__ATID32_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL1__ATID32_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL1___M              0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_SEL1___S                            0

#define DBG_OUTDMUX_ATID_SEL2                     (0x00BC0018)
#define   DBG_OUTDMUX_ATID_SEL2___RWC               QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_SEL2___POR            0x00000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___M  0x80000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___S               31
#define   DBG_OUTDMUX_ATID_SEL2__ATID95_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID95_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___M  0x40000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___S               30
#define   DBG_OUTDMUX_ATID_SEL2__ATID94_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID94_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___M  0x20000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___S               29
#define   DBG_OUTDMUX_ATID_SEL2__ATID93_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID93_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___M  0x10000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___S               28
#define   DBG_OUTDMUX_ATID_SEL2__ATID92_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID92_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___M  0x08000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___S               27
#define   DBG_OUTDMUX_ATID_SEL2__ATID91_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID91_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___M  0x04000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___S               26
#define   DBG_OUTDMUX_ATID_SEL2__ATID90_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID90_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___M  0x02000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___S               25
#define   DBG_OUTDMUX_ATID_SEL2__ATID89_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID89_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___M  0x01000000
#define   DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___S               24
#define   DBG_OUTDMUX_ATID_SEL2__ATID88_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID88_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___M  0x00800000
#define   DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___S               23
#define   DBG_OUTDMUX_ATID_SEL2__ATID87_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID87_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___M  0x00400000
#define   DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___S               22
#define   DBG_OUTDMUX_ATID_SEL2__ATID86_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID86_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___M  0x00200000
#define   DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___S               21
#define   DBG_OUTDMUX_ATID_SEL2__ATID85_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID85_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___M  0x00100000
#define   DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___S               20
#define   DBG_OUTDMUX_ATID_SEL2__ATID84_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID84_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___M  0x00080000
#define   DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___S               19
#define   DBG_OUTDMUX_ATID_SEL2__ATID83_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID83_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___M  0x00040000
#define   DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___S               18
#define   DBG_OUTDMUX_ATID_SEL2__ATID82_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID82_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___M  0x00020000
#define   DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___S               17
#define   DBG_OUTDMUX_ATID_SEL2__ATID81_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID81_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___M  0x00010000
#define   DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___S               16
#define   DBG_OUTDMUX_ATID_SEL2__ATID80_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID80_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___M  0x00008000
#define   DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___S               15
#define   DBG_OUTDMUX_ATID_SEL2__ATID79_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID79_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___M  0x00004000
#define   DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___S               14
#define   DBG_OUTDMUX_ATID_SEL2__ATID78_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID78_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___M  0x00002000
#define   DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___S               13
#define   DBG_OUTDMUX_ATID_SEL2__ATID77_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID77_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___M  0x00001000
#define   DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___S               12
#define   DBG_OUTDMUX_ATID_SEL2__ATID76_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID76_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___M  0x00000800
#define   DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___S               11
#define   DBG_OUTDMUX_ATID_SEL2__ATID75_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID75_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___M  0x00000400
#define   DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___S               10
#define   DBG_OUTDMUX_ATID_SEL2__ATID74_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID74_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___M  0x00000200
#define   DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___S                9
#define   DBG_OUTDMUX_ATID_SEL2__ATID73_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID73_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___M  0x00000100
#define   DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___S                8
#define   DBG_OUTDMUX_ATID_SEL2__ATID72_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID72_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___M  0x00000080
#define   DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___S                7
#define   DBG_OUTDMUX_ATID_SEL2__ATID71_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID71_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___M  0x00000040
#define   DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___S                6
#define   DBG_OUTDMUX_ATID_SEL2__ATID70_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID70_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___M  0x00000020
#define   DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___S                5
#define   DBG_OUTDMUX_ATID_SEL2__ATID69_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID69_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___M  0x00000010
#define   DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___S                4
#define   DBG_OUTDMUX_ATID_SEL2__ATID68_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID68_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___M  0x00000008
#define   DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___S                3
#define   DBG_OUTDMUX_ATID_SEL2__ATID67_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID67_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___M  0x00000004
#define   DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___S                2
#define   DBG_OUTDMUX_ATID_SEL2__ATID66_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID66_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___M  0x00000002
#define   DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___S                1
#define   DBG_OUTDMUX_ATID_SEL2__ATID65_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID65_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___M  0x00000001
#define   DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___S                0
#define   DBG_OUTDMUX_ATID_SEL2__ATID64_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL2__ATID64_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL2___M              0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_SEL2___S                            0

#define DBG_OUTDMUX_ATID_SEL3                     (0x00BC001C)
#define   DBG_OUTDMUX_ATID_SEL3___RWC               QCSR_REG_RW    
#define   DBG_OUTDMUX_ATID_SEL3___POR            0x00000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___POR 0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___M 0x80000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___S              31
#define   DBG_OUTDMUX_ATID_SEL3__ATID127_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID127_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___M 0x40000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___S              30
#define   DBG_OUTDMUX_ATID_SEL3__ATID126_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID126_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___M 0x20000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___S              29
#define   DBG_OUTDMUX_ATID_SEL3__ATID125_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID125_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___M 0x10000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___S              28
#define   DBG_OUTDMUX_ATID_SEL3__ATID124_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID124_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___M 0x08000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___S              27
#define   DBG_OUTDMUX_ATID_SEL3__ATID123_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID123_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___M 0x04000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___S              26
#define   DBG_OUTDMUX_ATID_SEL3__ATID122_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID122_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___M 0x02000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___S              25
#define   DBG_OUTDMUX_ATID_SEL3__ATID121_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID121_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___M 0x01000000
#define   DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___S              24
#define   DBG_OUTDMUX_ATID_SEL3__ATID120_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID120_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___M 0x00800000
#define   DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___S              23
#define   DBG_OUTDMUX_ATID_SEL3__ATID119_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID119_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___M 0x00400000
#define   DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___S              22
#define   DBG_OUTDMUX_ATID_SEL3__ATID118_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID118_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___M 0x00200000
#define   DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___S              21
#define   DBG_OUTDMUX_ATID_SEL3__ATID117_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID117_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___M 0x00100000
#define   DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___S              20
#define   DBG_OUTDMUX_ATID_SEL3__ATID116_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID116_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___M 0x00080000
#define   DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___S              19
#define   DBG_OUTDMUX_ATID_SEL3__ATID115_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID115_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___M 0x00040000
#define   DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___S              18
#define   DBG_OUTDMUX_ATID_SEL3__ATID114_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID114_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___M 0x00020000
#define   DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___S              17
#define   DBG_OUTDMUX_ATID_SEL3__ATID113_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID113_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___M 0x00010000
#define   DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___S              16
#define   DBG_OUTDMUX_ATID_SEL3__ATID112_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID112_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___M 0x00008000
#define   DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___S              15
#define   DBG_OUTDMUX_ATID_SEL3__ATID111_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID111_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___M 0x00004000
#define   DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___S              14
#define   DBG_OUTDMUX_ATID_SEL3__ATID110_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID110_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___M 0x00002000
#define   DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___S              13
#define   DBG_OUTDMUX_ATID_SEL3__ATID109_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID109_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___M 0x00001000
#define   DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___S              12
#define   DBG_OUTDMUX_ATID_SEL3__ATID108_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID108_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___M 0x00000800
#define   DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___S              11
#define   DBG_OUTDMUX_ATID_SEL3__ATID107_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID107_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___M 0x00000400
#define   DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___S              10
#define   DBG_OUTDMUX_ATID_SEL3__ATID106_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID106_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___M 0x00000200
#define   DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___S               9
#define   DBG_OUTDMUX_ATID_SEL3__ATID105_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID105_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___M 0x00000100
#define   DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___S               8
#define   DBG_OUTDMUX_ATID_SEL3__ATID104_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID104_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___M 0x00000080
#define   DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___S               7
#define   DBG_OUTDMUX_ATID_SEL3__ATID103_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID103_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___M 0x00000040
#define   DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___S               6
#define   DBG_OUTDMUX_ATID_SEL3__ATID102_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID102_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___M 0x00000020
#define   DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___S               5
#define   DBG_OUTDMUX_ATID_SEL3__ATID101_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID101_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___M 0x00000010
#define   DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___S               4
#define   DBG_OUTDMUX_ATID_SEL3__ATID100_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID100_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___M  0x00000008
#define   DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___S                3
#define   DBG_OUTDMUX_ATID_SEL3__ATID99_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID99_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___M  0x00000004
#define   DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___S                2
#define   DBG_OUTDMUX_ATID_SEL3__ATID98_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID98_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___M  0x00000002
#define   DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___S                1
#define   DBG_OUTDMUX_ATID_SEL3__ATID97_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID97_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___M  0x00000001
#define   DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___S                0
#define   DBG_OUTDMUX_ATID_SEL3__ATID96_SEL__SEL_PORT0             0x0
#define   DBG_OUTDMUX_ATID_SEL3__ATID96_SEL__SEL_PORT1             0x1
#define   DBG_OUTDMUX_ATID_SEL3___M              0xFFFFFFFF   
#define   DBG_OUTDMUX_ATID_SEL3___S                            0

#define DBG_CNTRn_CFG(n)                 (0x00BC1000+0x40*(n))
#define   DBG_CNTRn_CFG_nMIN       0    
#define   DBG_CNTRn_CFG_nMAX       3    
#define   DBG_CNTRn_CFG_ELEM       4    
#define   DBG_CNTRn_CFG___RWC                       QCSR_REG_RW    
#define   DBG_CNTRn_CFG___POR                    0x00000000
#define   DBG_CNTRn_CFG__CNT_TYPE___POR          0x0
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL___POR     0x00
#define   DBG_CNTRn_CFG__ENABLE___POR            0x0
#define   DBG_CNTRn_CFG__CNT_TYPE___M            0x00000040
#define   DBG_CNTRn_CFG__CNT_TYPE___S                          6
#define   DBG_CNTRn_CFG__CNT_TYPE__BYTES                     0x0
#define   DBG_CNTRn_CFG__CNT_TYPE__WAIT_CYCLES               0x1
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL___M       0x0000003E
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL___S                     1
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_BDG2TGUFILT            0x00
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_CMB_BDG2FUN            0x01
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_BDG2FUN            0x02
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__UMACDBG_BDG2FUN            0x03
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_BDG2TGUFILT            0x04
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_DMUX2CMB            0x05
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_BDG2FUN            0x06
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_BDG2TGUFILT            0x07
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_DMUX2CMB            0x08
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_BDG2FUN            0x09
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__CPHY_BDG2FUN            0x0A
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACEVENT_CMB            0x0B
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__DATDUMPR_CMB            0x0C
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__APBMON_CMB            0x0D
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__SWGEN_CMB            0x0E
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__UPSZ2TPDA            0x0F
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_CMB            0x10
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_TPDM2TPDA            0x11
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTBUS_CMB            0x12
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MISC_TPDM2TPDA            0x13
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__TPDA_BDG2FUN            0x14
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__TSTMP_INJCTR            0x15
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACEVENT_ATB            0x16
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_ATB            0x17
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTBUS_ATB            0x18
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__FUN_MST             0x19
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_SLV             0x1A
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_MST             0x1B
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_BYPASS            0x1C
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__FIFO2ABDGS            0x1D
#define   DBG_CNTRn_CFG__ATB_PROBE_SEL__MISC_FUN2TPDM            0x1E
#define   DBG_CNTRn_CFG__ENABLE___M              0x00000001
#define   DBG_CNTRn_CFG__ENABLE___S                            0
#define   DBG_CNTRn_CFG___M                      0x0000007F   
#define   DBG_CNTRn_CFG___S                                    0
#define DBG_CNTR0_CFG                             (0x00BC1000)
#define   DBG_CNTR0_CFG___RWC                       QCSR_REG_RW    
#define   DBG_CNTR0_CFG__CNT_TYPE___M            0x00000040
#define   DBG_CNTR0_CFG__CNT_TYPE___S                          6
#define   DBG_CNTR0_CFG__ATB_PROBE_SEL___M       0x0000003E
#define   DBG_CNTR0_CFG__ATB_PROBE_SEL___S                     1
#define   DBG_CNTR0_CFG__ENABLE___M              0x00000001
#define   DBG_CNTR0_CFG__ENABLE___S                            0
#define DBG_CNTR1_CFG                             (0x00BC1040)
#define   DBG_CNTR1_CFG___RWC                       QCSR_REG_RW    
#define   DBG_CNTR1_CFG__CNT_TYPE___M            0x00000040
#define   DBG_CNTR1_CFG__CNT_TYPE___S                          6
#define   DBG_CNTR1_CFG__ATB_PROBE_SEL___M       0x0000003E
#define   DBG_CNTR1_CFG__ATB_PROBE_SEL___S                     1
#define   DBG_CNTR1_CFG__ENABLE___M              0x00000001
#define   DBG_CNTR1_CFG__ENABLE___S                            0
#define DBG_CNTR2_CFG                             (0x00BC1080)
#define   DBG_CNTR2_CFG___RWC                       QCSR_REG_RW    
#define   DBG_CNTR2_CFG__CNT_TYPE___M            0x00000040
#define   DBG_CNTR2_CFG__CNT_TYPE___S                          6
#define   DBG_CNTR2_CFG__ATB_PROBE_SEL___M       0x0000003E
#define   DBG_CNTR2_CFG__ATB_PROBE_SEL___S                     1
#define   DBG_CNTR2_CFG__ENABLE___M              0x00000001
#define   DBG_CNTR2_CFG__ENABLE___S                            0
#define DBG_CNTR3_CFG                             (0x00BC10C0)
#define   DBG_CNTR3_CFG___RWC                       QCSR_REG_RW    
#define   DBG_CNTR3_CFG__CNT_TYPE___M            0x00000040
#define   DBG_CNTR3_CFG__CNT_TYPE___S                          6
#define   DBG_CNTR3_CFG__ATB_PROBE_SEL___M       0x0000003E
#define   DBG_CNTR3_CFG__ATB_PROBE_SEL___S                     1
#define   DBG_CNTR3_CFG__ENABLE___M              0x00000001
#define   DBG_CNTR3_CFG__ENABLE___S                            0

#define DBG_CNTRn_ATID_EN0(n)            (0x00BC1004+0x40*(n))
#define   DBG_CNTRn_ATID_EN0_nMIN  0    
#define   DBG_CNTRn_ATID_EN0_nMAX  3    
#define   DBG_CNTRn_ATID_EN0_ELEM  4    
#define   DBG_CNTRn_ATID_EN0___RWC                  QCSR_REG_RW    
#define   DBG_CNTRn_ATID_EN0___POR               0xFFFFFFFF
#define   DBG_CNTRn_ATID_EN0__ATID31_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID30_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID29_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID28_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID27_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID26_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID25_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID24_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID23_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID22_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID21_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID20_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID19_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID18_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID17_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID16_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID15_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID14_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID13_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID12_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID11_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID10_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN0__ATID9_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID8_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID7_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID6_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID5_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID4_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID3_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID2_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID1_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID0_EN___POR     0x1
#define   DBG_CNTRn_ATID_EN0__ATID31_EN___M      0x80000000
#define   DBG_CNTRn_ATID_EN0__ATID31_EN___S                   31
#define   DBG_CNTRn_ATID_EN0__ATID31_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID31_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID30_EN___M      0x40000000
#define   DBG_CNTRn_ATID_EN0__ATID30_EN___S                   30
#define   DBG_CNTRn_ATID_EN0__ATID30_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID30_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID29_EN___M      0x20000000
#define   DBG_CNTRn_ATID_EN0__ATID29_EN___S                   29
#define   DBG_CNTRn_ATID_EN0__ATID29_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID29_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID28_EN___M      0x10000000
#define   DBG_CNTRn_ATID_EN0__ATID28_EN___S                   28
#define   DBG_CNTRn_ATID_EN0__ATID28_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID28_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID27_EN___M      0x08000000
#define   DBG_CNTRn_ATID_EN0__ATID27_EN___S                   27
#define   DBG_CNTRn_ATID_EN0__ATID27_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID27_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID26_EN___M      0x04000000
#define   DBG_CNTRn_ATID_EN0__ATID26_EN___S                   26
#define   DBG_CNTRn_ATID_EN0__ATID26_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID26_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID25_EN___M      0x02000000
#define   DBG_CNTRn_ATID_EN0__ATID25_EN___S                   25
#define   DBG_CNTRn_ATID_EN0__ATID25_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID25_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID24_EN___M      0x01000000
#define   DBG_CNTRn_ATID_EN0__ATID24_EN___S                   24
#define   DBG_CNTRn_ATID_EN0__ATID24_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID24_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID23_EN___M      0x00800000
#define   DBG_CNTRn_ATID_EN0__ATID23_EN___S                   23
#define   DBG_CNTRn_ATID_EN0__ATID23_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID23_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID22_EN___M      0x00400000
#define   DBG_CNTRn_ATID_EN0__ATID22_EN___S                   22
#define   DBG_CNTRn_ATID_EN0__ATID22_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID22_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID21_EN___M      0x00200000
#define   DBG_CNTRn_ATID_EN0__ATID21_EN___S                   21
#define   DBG_CNTRn_ATID_EN0__ATID21_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID21_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID20_EN___M      0x00100000
#define   DBG_CNTRn_ATID_EN0__ATID20_EN___S                   20
#define   DBG_CNTRn_ATID_EN0__ATID20_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID20_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID19_EN___M      0x00080000
#define   DBG_CNTRn_ATID_EN0__ATID19_EN___S                   19
#define   DBG_CNTRn_ATID_EN0__ATID19_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID19_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID18_EN___M      0x00040000
#define   DBG_CNTRn_ATID_EN0__ATID18_EN___S                   18
#define   DBG_CNTRn_ATID_EN0__ATID18_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID18_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID17_EN___M      0x00020000
#define   DBG_CNTRn_ATID_EN0__ATID17_EN___S                   17
#define   DBG_CNTRn_ATID_EN0__ATID17_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID17_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID16_EN___M      0x00010000
#define   DBG_CNTRn_ATID_EN0__ATID16_EN___S                   16
#define   DBG_CNTRn_ATID_EN0__ATID16_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID16_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID15_EN___M      0x00008000
#define   DBG_CNTRn_ATID_EN0__ATID15_EN___S                   15
#define   DBG_CNTRn_ATID_EN0__ATID15_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID15_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID14_EN___M      0x00004000
#define   DBG_CNTRn_ATID_EN0__ATID14_EN___S                   14
#define   DBG_CNTRn_ATID_EN0__ATID14_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID14_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID13_EN___M      0x00002000
#define   DBG_CNTRn_ATID_EN0__ATID13_EN___S                   13
#define   DBG_CNTRn_ATID_EN0__ATID13_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID13_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID12_EN___M      0x00001000
#define   DBG_CNTRn_ATID_EN0__ATID12_EN___S                   12
#define   DBG_CNTRn_ATID_EN0__ATID12_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID12_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID11_EN___M      0x00000800
#define   DBG_CNTRn_ATID_EN0__ATID11_EN___S                   11
#define   DBG_CNTRn_ATID_EN0__ATID11_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID11_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID10_EN___M      0x00000400
#define   DBG_CNTRn_ATID_EN0__ATID10_EN___S                   10
#define   DBG_CNTRn_ATID_EN0__ATID10_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN0__ATID10_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN0__ATID9_EN___M       0x00000200
#define   DBG_CNTRn_ATID_EN0__ATID9_EN___S                     9
#define   DBG_CNTRn_ATID_EN0__ATID9_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID9_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID8_EN___M       0x00000100
#define   DBG_CNTRn_ATID_EN0__ATID8_EN___S                     8
#define   DBG_CNTRn_ATID_EN0__ATID8_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID8_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID7_EN___M       0x00000080
#define   DBG_CNTRn_ATID_EN0__ATID7_EN___S                     7
#define   DBG_CNTRn_ATID_EN0__ATID7_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID7_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID6_EN___M       0x00000040
#define   DBG_CNTRn_ATID_EN0__ATID6_EN___S                     6
#define   DBG_CNTRn_ATID_EN0__ATID6_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID6_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID5_EN___M       0x00000020
#define   DBG_CNTRn_ATID_EN0__ATID5_EN___S                     5
#define   DBG_CNTRn_ATID_EN0__ATID5_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID5_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID4_EN___M       0x00000010
#define   DBG_CNTRn_ATID_EN0__ATID4_EN___S                     4
#define   DBG_CNTRn_ATID_EN0__ATID4_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID4_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID3_EN___M       0x00000008
#define   DBG_CNTRn_ATID_EN0__ATID3_EN___S                     3
#define   DBG_CNTRn_ATID_EN0__ATID3_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID3_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID2_EN___M       0x00000004
#define   DBG_CNTRn_ATID_EN0__ATID2_EN___S                     2
#define   DBG_CNTRn_ATID_EN0__ATID2_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID2_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID1_EN___M       0x00000002
#define   DBG_CNTRn_ATID_EN0__ATID1_EN___S                     1
#define   DBG_CNTRn_ATID_EN0__ATID1_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID1_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0__ATID0_EN___M       0x00000001
#define   DBG_CNTRn_ATID_EN0__ATID0_EN___S                     0
#define   DBG_CNTRn_ATID_EN0__ATID0_EN__DISABLE              0x0
#define   DBG_CNTRn_ATID_EN0__ATID0_EN__ENABLE               0x1
#define   DBG_CNTRn_ATID_EN0___M                 0xFFFFFFFF   
#define   DBG_CNTRn_ATID_EN0___S                               0
#define DBG_CNTR0_ATID_EN0                        (0x00BC1004)
#define   DBG_CNTR0_ATID_EN0___RWC                  QCSR_REG_RW    
#define   DBG_CNTR0_ATID_EN0__ATID31_EN___M      0x80000000
#define   DBG_CNTR0_ATID_EN0__ATID31_EN___S                   31
#define   DBG_CNTR0_ATID_EN0__ATID30_EN___M      0x40000000
#define   DBG_CNTR0_ATID_EN0__ATID30_EN___S                   30
#define   DBG_CNTR0_ATID_EN0__ATID29_EN___M      0x20000000
#define   DBG_CNTR0_ATID_EN0__ATID29_EN___S                   29
#define   DBG_CNTR0_ATID_EN0__ATID28_EN___M      0x10000000
#define   DBG_CNTR0_ATID_EN0__ATID28_EN___S                   28
#define   DBG_CNTR0_ATID_EN0__ATID27_EN___M      0x08000000
#define   DBG_CNTR0_ATID_EN0__ATID27_EN___S                   27
#define   DBG_CNTR0_ATID_EN0__ATID26_EN___M      0x04000000
#define   DBG_CNTR0_ATID_EN0__ATID26_EN___S                   26
#define   DBG_CNTR0_ATID_EN0__ATID25_EN___M      0x02000000
#define   DBG_CNTR0_ATID_EN0__ATID25_EN___S                   25
#define   DBG_CNTR0_ATID_EN0__ATID24_EN___M      0x01000000
#define   DBG_CNTR0_ATID_EN0__ATID24_EN___S                   24
#define   DBG_CNTR0_ATID_EN0__ATID23_EN___M      0x00800000
#define   DBG_CNTR0_ATID_EN0__ATID23_EN___S                   23
#define   DBG_CNTR0_ATID_EN0__ATID22_EN___M      0x00400000
#define   DBG_CNTR0_ATID_EN0__ATID22_EN___S                   22
#define   DBG_CNTR0_ATID_EN0__ATID21_EN___M      0x00200000
#define   DBG_CNTR0_ATID_EN0__ATID21_EN___S                   21
#define   DBG_CNTR0_ATID_EN0__ATID20_EN___M      0x00100000
#define   DBG_CNTR0_ATID_EN0__ATID20_EN___S                   20
#define   DBG_CNTR0_ATID_EN0__ATID19_EN___M      0x00080000
#define   DBG_CNTR0_ATID_EN0__ATID19_EN___S                   19
#define   DBG_CNTR0_ATID_EN0__ATID18_EN___M      0x00040000
#define   DBG_CNTR0_ATID_EN0__ATID18_EN___S                   18
#define   DBG_CNTR0_ATID_EN0__ATID17_EN___M      0x00020000
#define   DBG_CNTR0_ATID_EN0__ATID17_EN___S                   17
#define   DBG_CNTR0_ATID_EN0__ATID16_EN___M      0x00010000
#define   DBG_CNTR0_ATID_EN0__ATID16_EN___S                   16
#define   DBG_CNTR0_ATID_EN0__ATID15_EN___M      0x00008000
#define   DBG_CNTR0_ATID_EN0__ATID15_EN___S                   15
#define   DBG_CNTR0_ATID_EN0__ATID14_EN___M      0x00004000
#define   DBG_CNTR0_ATID_EN0__ATID14_EN___S                   14
#define   DBG_CNTR0_ATID_EN0__ATID13_EN___M      0x00002000
#define   DBG_CNTR0_ATID_EN0__ATID13_EN___S                   13
#define   DBG_CNTR0_ATID_EN0__ATID12_EN___M      0x00001000
#define   DBG_CNTR0_ATID_EN0__ATID12_EN___S                   12
#define   DBG_CNTR0_ATID_EN0__ATID11_EN___M      0x00000800
#define   DBG_CNTR0_ATID_EN0__ATID11_EN___S                   11
#define   DBG_CNTR0_ATID_EN0__ATID10_EN___M      0x00000400
#define   DBG_CNTR0_ATID_EN0__ATID10_EN___S                   10
#define   DBG_CNTR0_ATID_EN0__ATID9_EN___M       0x00000200
#define   DBG_CNTR0_ATID_EN0__ATID9_EN___S                     9
#define   DBG_CNTR0_ATID_EN0__ATID8_EN___M       0x00000100
#define   DBG_CNTR0_ATID_EN0__ATID8_EN___S                     8
#define   DBG_CNTR0_ATID_EN0__ATID7_EN___M       0x00000080
#define   DBG_CNTR0_ATID_EN0__ATID7_EN___S                     7
#define   DBG_CNTR0_ATID_EN0__ATID6_EN___M       0x00000040
#define   DBG_CNTR0_ATID_EN0__ATID6_EN___S                     6
#define   DBG_CNTR0_ATID_EN0__ATID5_EN___M       0x00000020
#define   DBG_CNTR0_ATID_EN0__ATID5_EN___S                     5
#define   DBG_CNTR0_ATID_EN0__ATID4_EN___M       0x00000010
#define   DBG_CNTR0_ATID_EN0__ATID4_EN___S                     4
#define   DBG_CNTR0_ATID_EN0__ATID3_EN___M       0x00000008
#define   DBG_CNTR0_ATID_EN0__ATID3_EN___S                     3
#define   DBG_CNTR0_ATID_EN0__ATID2_EN___M       0x00000004
#define   DBG_CNTR0_ATID_EN0__ATID2_EN___S                     2
#define   DBG_CNTR0_ATID_EN0__ATID1_EN___M       0x00000002
#define   DBG_CNTR0_ATID_EN0__ATID1_EN___S                     1
#define   DBG_CNTR0_ATID_EN0__ATID0_EN___M       0x00000001
#define   DBG_CNTR0_ATID_EN0__ATID0_EN___S                     0
#define DBG_CNTR1_ATID_EN0                        (0x00BC1044)
#define   DBG_CNTR1_ATID_EN0___RWC                  QCSR_REG_RW    
#define   DBG_CNTR1_ATID_EN0__ATID31_EN___M      0x80000000
#define   DBG_CNTR1_ATID_EN0__ATID31_EN___S                   31
#define   DBG_CNTR1_ATID_EN0__ATID30_EN___M      0x40000000
#define   DBG_CNTR1_ATID_EN0__ATID30_EN___S                   30
#define   DBG_CNTR1_ATID_EN0__ATID29_EN___M      0x20000000
#define   DBG_CNTR1_ATID_EN0__ATID29_EN___S                   29
#define   DBG_CNTR1_ATID_EN0__ATID28_EN___M      0x10000000
#define   DBG_CNTR1_ATID_EN0__ATID28_EN___S                   28
#define   DBG_CNTR1_ATID_EN0__ATID27_EN___M      0x08000000
#define   DBG_CNTR1_ATID_EN0__ATID27_EN___S                   27
#define   DBG_CNTR1_ATID_EN0__ATID26_EN___M      0x04000000
#define   DBG_CNTR1_ATID_EN0__ATID26_EN___S                   26
#define   DBG_CNTR1_ATID_EN0__ATID25_EN___M      0x02000000
#define   DBG_CNTR1_ATID_EN0__ATID25_EN___S                   25
#define   DBG_CNTR1_ATID_EN0__ATID24_EN___M      0x01000000
#define   DBG_CNTR1_ATID_EN0__ATID24_EN___S                   24
#define   DBG_CNTR1_ATID_EN0__ATID23_EN___M      0x00800000
#define   DBG_CNTR1_ATID_EN0__ATID23_EN___S                   23
#define   DBG_CNTR1_ATID_EN0__ATID22_EN___M      0x00400000
#define   DBG_CNTR1_ATID_EN0__ATID22_EN___S                   22
#define   DBG_CNTR1_ATID_EN0__ATID21_EN___M      0x00200000
#define   DBG_CNTR1_ATID_EN0__ATID21_EN___S                   21
#define   DBG_CNTR1_ATID_EN0__ATID20_EN___M      0x00100000
#define   DBG_CNTR1_ATID_EN0__ATID20_EN___S                   20
#define   DBG_CNTR1_ATID_EN0__ATID19_EN___M      0x00080000
#define   DBG_CNTR1_ATID_EN0__ATID19_EN___S                   19
#define   DBG_CNTR1_ATID_EN0__ATID18_EN___M      0x00040000
#define   DBG_CNTR1_ATID_EN0__ATID18_EN___S                   18
#define   DBG_CNTR1_ATID_EN0__ATID17_EN___M      0x00020000
#define   DBG_CNTR1_ATID_EN0__ATID17_EN___S                   17
#define   DBG_CNTR1_ATID_EN0__ATID16_EN___M      0x00010000
#define   DBG_CNTR1_ATID_EN0__ATID16_EN___S                   16
#define   DBG_CNTR1_ATID_EN0__ATID15_EN___M      0x00008000
#define   DBG_CNTR1_ATID_EN0__ATID15_EN___S                   15
#define   DBG_CNTR1_ATID_EN0__ATID14_EN___M      0x00004000
#define   DBG_CNTR1_ATID_EN0__ATID14_EN___S                   14
#define   DBG_CNTR1_ATID_EN0__ATID13_EN___M      0x00002000
#define   DBG_CNTR1_ATID_EN0__ATID13_EN___S                   13
#define   DBG_CNTR1_ATID_EN0__ATID12_EN___M      0x00001000
#define   DBG_CNTR1_ATID_EN0__ATID12_EN___S                   12
#define   DBG_CNTR1_ATID_EN0__ATID11_EN___M      0x00000800
#define   DBG_CNTR1_ATID_EN0__ATID11_EN___S                   11
#define   DBG_CNTR1_ATID_EN0__ATID10_EN___M      0x00000400
#define   DBG_CNTR1_ATID_EN0__ATID10_EN___S                   10
#define   DBG_CNTR1_ATID_EN0__ATID9_EN___M       0x00000200
#define   DBG_CNTR1_ATID_EN0__ATID9_EN___S                     9
#define   DBG_CNTR1_ATID_EN0__ATID8_EN___M       0x00000100
#define   DBG_CNTR1_ATID_EN0__ATID8_EN___S                     8
#define   DBG_CNTR1_ATID_EN0__ATID7_EN___M       0x00000080
#define   DBG_CNTR1_ATID_EN0__ATID7_EN___S                     7
#define   DBG_CNTR1_ATID_EN0__ATID6_EN___M       0x00000040
#define   DBG_CNTR1_ATID_EN0__ATID6_EN___S                     6
#define   DBG_CNTR1_ATID_EN0__ATID5_EN___M       0x00000020
#define   DBG_CNTR1_ATID_EN0__ATID5_EN___S                     5
#define   DBG_CNTR1_ATID_EN0__ATID4_EN___M       0x00000010
#define   DBG_CNTR1_ATID_EN0__ATID4_EN___S                     4
#define   DBG_CNTR1_ATID_EN0__ATID3_EN___M       0x00000008
#define   DBG_CNTR1_ATID_EN0__ATID3_EN___S                     3
#define   DBG_CNTR1_ATID_EN0__ATID2_EN___M       0x00000004
#define   DBG_CNTR1_ATID_EN0__ATID2_EN___S                     2
#define   DBG_CNTR1_ATID_EN0__ATID1_EN___M       0x00000002
#define   DBG_CNTR1_ATID_EN0__ATID1_EN___S                     1
#define   DBG_CNTR1_ATID_EN0__ATID0_EN___M       0x00000001
#define   DBG_CNTR1_ATID_EN0__ATID0_EN___S                     0
#define DBG_CNTR2_ATID_EN0                        (0x00BC1084)
#define   DBG_CNTR2_ATID_EN0___RWC                  QCSR_REG_RW    
#define   DBG_CNTR2_ATID_EN0__ATID31_EN___M      0x80000000
#define   DBG_CNTR2_ATID_EN0__ATID31_EN___S                   31
#define   DBG_CNTR2_ATID_EN0__ATID30_EN___M      0x40000000
#define   DBG_CNTR2_ATID_EN0__ATID30_EN___S                   30
#define   DBG_CNTR2_ATID_EN0__ATID29_EN___M      0x20000000
#define   DBG_CNTR2_ATID_EN0__ATID29_EN___S                   29
#define   DBG_CNTR2_ATID_EN0__ATID28_EN___M      0x10000000
#define   DBG_CNTR2_ATID_EN0__ATID28_EN___S                   28
#define   DBG_CNTR2_ATID_EN0__ATID27_EN___M      0x08000000
#define   DBG_CNTR2_ATID_EN0__ATID27_EN___S                   27
#define   DBG_CNTR2_ATID_EN0__ATID26_EN___M      0x04000000
#define   DBG_CNTR2_ATID_EN0__ATID26_EN___S                   26
#define   DBG_CNTR2_ATID_EN0__ATID25_EN___M      0x02000000
#define   DBG_CNTR2_ATID_EN0__ATID25_EN___S                   25
#define   DBG_CNTR2_ATID_EN0__ATID24_EN___M      0x01000000
#define   DBG_CNTR2_ATID_EN0__ATID24_EN___S                   24
#define   DBG_CNTR2_ATID_EN0__ATID23_EN___M      0x00800000
#define   DBG_CNTR2_ATID_EN0__ATID23_EN___S                   23
#define   DBG_CNTR2_ATID_EN0__ATID22_EN___M      0x00400000
#define   DBG_CNTR2_ATID_EN0__ATID22_EN___S                   22
#define   DBG_CNTR2_ATID_EN0__ATID21_EN___M      0x00200000
#define   DBG_CNTR2_ATID_EN0__ATID21_EN___S                   21
#define   DBG_CNTR2_ATID_EN0__ATID20_EN___M      0x00100000
#define   DBG_CNTR2_ATID_EN0__ATID20_EN___S                   20
#define   DBG_CNTR2_ATID_EN0__ATID19_EN___M      0x00080000
#define   DBG_CNTR2_ATID_EN0__ATID19_EN___S                   19
#define   DBG_CNTR2_ATID_EN0__ATID18_EN___M      0x00040000
#define   DBG_CNTR2_ATID_EN0__ATID18_EN___S                   18
#define   DBG_CNTR2_ATID_EN0__ATID17_EN___M      0x00020000
#define   DBG_CNTR2_ATID_EN0__ATID17_EN___S                   17
#define   DBG_CNTR2_ATID_EN0__ATID16_EN___M      0x00010000
#define   DBG_CNTR2_ATID_EN0__ATID16_EN___S                   16
#define   DBG_CNTR2_ATID_EN0__ATID15_EN___M      0x00008000
#define   DBG_CNTR2_ATID_EN0__ATID15_EN___S                   15
#define   DBG_CNTR2_ATID_EN0__ATID14_EN___M      0x00004000
#define   DBG_CNTR2_ATID_EN0__ATID14_EN___S                   14
#define   DBG_CNTR2_ATID_EN0__ATID13_EN___M      0x00002000
#define   DBG_CNTR2_ATID_EN0__ATID13_EN___S                   13
#define   DBG_CNTR2_ATID_EN0__ATID12_EN___M      0x00001000
#define   DBG_CNTR2_ATID_EN0__ATID12_EN___S                   12
#define   DBG_CNTR2_ATID_EN0__ATID11_EN___M      0x00000800
#define   DBG_CNTR2_ATID_EN0__ATID11_EN___S                   11
#define   DBG_CNTR2_ATID_EN0__ATID10_EN___M      0x00000400
#define   DBG_CNTR2_ATID_EN0__ATID10_EN___S                   10
#define   DBG_CNTR2_ATID_EN0__ATID9_EN___M       0x00000200
#define   DBG_CNTR2_ATID_EN0__ATID9_EN___S                     9
#define   DBG_CNTR2_ATID_EN0__ATID8_EN___M       0x00000100
#define   DBG_CNTR2_ATID_EN0__ATID8_EN___S                     8
#define   DBG_CNTR2_ATID_EN0__ATID7_EN___M       0x00000080
#define   DBG_CNTR2_ATID_EN0__ATID7_EN___S                     7
#define   DBG_CNTR2_ATID_EN0__ATID6_EN___M       0x00000040
#define   DBG_CNTR2_ATID_EN0__ATID6_EN___S                     6
#define   DBG_CNTR2_ATID_EN0__ATID5_EN___M       0x00000020
#define   DBG_CNTR2_ATID_EN0__ATID5_EN___S                     5
#define   DBG_CNTR2_ATID_EN0__ATID4_EN___M       0x00000010
#define   DBG_CNTR2_ATID_EN0__ATID4_EN___S                     4
#define   DBG_CNTR2_ATID_EN0__ATID3_EN___M       0x00000008
#define   DBG_CNTR2_ATID_EN0__ATID3_EN___S                     3
#define   DBG_CNTR2_ATID_EN0__ATID2_EN___M       0x00000004
#define   DBG_CNTR2_ATID_EN0__ATID2_EN___S                     2
#define   DBG_CNTR2_ATID_EN0__ATID1_EN___M       0x00000002
#define   DBG_CNTR2_ATID_EN0__ATID1_EN___S                     1
#define   DBG_CNTR2_ATID_EN0__ATID0_EN___M       0x00000001
#define   DBG_CNTR2_ATID_EN0__ATID0_EN___S                     0
#define DBG_CNTR3_ATID_EN0                        (0x00BC10C4)
#define   DBG_CNTR3_ATID_EN0___RWC                  QCSR_REG_RW    
#define   DBG_CNTR3_ATID_EN0__ATID31_EN___M      0x80000000
#define   DBG_CNTR3_ATID_EN0__ATID31_EN___S                   31
#define   DBG_CNTR3_ATID_EN0__ATID30_EN___M      0x40000000
#define   DBG_CNTR3_ATID_EN0__ATID30_EN___S                   30
#define   DBG_CNTR3_ATID_EN0__ATID29_EN___M      0x20000000
#define   DBG_CNTR3_ATID_EN0__ATID29_EN___S                   29
#define   DBG_CNTR3_ATID_EN0__ATID28_EN___M      0x10000000
#define   DBG_CNTR3_ATID_EN0__ATID28_EN___S                   28
#define   DBG_CNTR3_ATID_EN0__ATID27_EN___M      0x08000000
#define   DBG_CNTR3_ATID_EN0__ATID27_EN___S                   27
#define   DBG_CNTR3_ATID_EN0__ATID26_EN___M      0x04000000
#define   DBG_CNTR3_ATID_EN0__ATID26_EN___S                   26
#define   DBG_CNTR3_ATID_EN0__ATID25_EN___M      0x02000000
#define   DBG_CNTR3_ATID_EN0__ATID25_EN___S                   25
#define   DBG_CNTR3_ATID_EN0__ATID24_EN___M      0x01000000
#define   DBG_CNTR3_ATID_EN0__ATID24_EN___S                   24
#define   DBG_CNTR3_ATID_EN0__ATID23_EN___M      0x00800000
#define   DBG_CNTR3_ATID_EN0__ATID23_EN___S                   23
#define   DBG_CNTR3_ATID_EN0__ATID22_EN___M      0x00400000
#define   DBG_CNTR3_ATID_EN0__ATID22_EN___S                   22
#define   DBG_CNTR3_ATID_EN0__ATID21_EN___M      0x00200000
#define   DBG_CNTR3_ATID_EN0__ATID21_EN___S                   21
#define   DBG_CNTR3_ATID_EN0__ATID20_EN___M      0x00100000
#define   DBG_CNTR3_ATID_EN0__ATID20_EN___S                   20
#define   DBG_CNTR3_ATID_EN0__ATID19_EN___M      0x00080000
#define   DBG_CNTR3_ATID_EN0__ATID19_EN___S                   19
#define   DBG_CNTR3_ATID_EN0__ATID18_EN___M      0x00040000
#define   DBG_CNTR3_ATID_EN0__ATID18_EN___S                   18
#define   DBG_CNTR3_ATID_EN0__ATID17_EN___M      0x00020000
#define   DBG_CNTR3_ATID_EN0__ATID17_EN___S                   17
#define   DBG_CNTR3_ATID_EN0__ATID16_EN___M      0x00010000
#define   DBG_CNTR3_ATID_EN0__ATID16_EN___S                   16
#define   DBG_CNTR3_ATID_EN0__ATID15_EN___M      0x00008000
#define   DBG_CNTR3_ATID_EN0__ATID15_EN___S                   15
#define   DBG_CNTR3_ATID_EN0__ATID14_EN___M      0x00004000
#define   DBG_CNTR3_ATID_EN0__ATID14_EN___S                   14
#define   DBG_CNTR3_ATID_EN0__ATID13_EN___M      0x00002000
#define   DBG_CNTR3_ATID_EN0__ATID13_EN___S                   13
#define   DBG_CNTR3_ATID_EN0__ATID12_EN___M      0x00001000
#define   DBG_CNTR3_ATID_EN0__ATID12_EN___S                   12
#define   DBG_CNTR3_ATID_EN0__ATID11_EN___M      0x00000800
#define   DBG_CNTR3_ATID_EN0__ATID11_EN___S                   11
#define   DBG_CNTR3_ATID_EN0__ATID10_EN___M      0x00000400
#define   DBG_CNTR3_ATID_EN0__ATID10_EN___S                   10
#define   DBG_CNTR3_ATID_EN0__ATID9_EN___M       0x00000200
#define   DBG_CNTR3_ATID_EN0__ATID9_EN___S                     9
#define   DBG_CNTR3_ATID_EN0__ATID8_EN___M       0x00000100
#define   DBG_CNTR3_ATID_EN0__ATID8_EN___S                     8
#define   DBG_CNTR3_ATID_EN0__ATID7_EN___M       0x00000080
#define   DBG_CNTR3_ATID_EN0__ATID7_EN___S                     7
#define   DBG_CNTR3_ATID_EN0__ATID6_EN___M       0x00000040
#define   DBG_CNTR3_ATID_EN0__ATID6_EN___S                     6
#define   DBG_CNTR3_ATID_EN0__ATID5_EN___M       0x00000020
#define   DBG_CNTR3_ATID_EN0__ATID5_EN___S                     5
#define   DBG_CNTR3_ATID_EN0__ATID4_EN___M       0x00000010
#define   DBG_CNTR3_ATID_EN0__ATID4_EN___S                     4
#define   DBG_CNTR3_ATID_EN0__ATID3_EN___M       0x00000008
#define   DBG_CNTR3_ATID_EN0__ATID3_EN___S                     3
#define   DBG_CNTR3_ATID_EN0__ATID2_EN___M       0x00000004
#define   DBG_CNTR3_ATID_EN0__ATID2_EN___S                     2
#define   DBG_CNTR3_ATID_EN0__ATID1_EN___M       0x00000002
#define   DBG_CNTR3_ATID_EN0__ATID1_EN___S                     1
#define   DBG_CNTR3_ATID_EN0__ATID0_EN___M       0x00000001
#define   DBG_CNTR3_ATID_EN0__ATID0_EN___S                     0

#define DBG_CNTRn_ATID_EN1(n)            (0x00BC1008+0x40*(n))
#define   DBG_CNTRn_ATID_EN1_nMIN  0    
#define   DBG_CNTRn_ATID_EN1_nMAX  3    
#define   DBG_CNTRn_ATID_EN1_ELEM  4    
#define   DBG_CNTRn_ATID_EN1___RWC                  QCSR_REG_RW    
#define   DBG_CNTRn_ATID_EN1___POR               0xFFFFFFFF
#define   DBG_CNTRn_ATID_EN1__ATID63_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID62_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID61_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID60_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID59_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID58_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID57_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID56_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID55_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID54_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID53_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID52_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID51_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID50_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID49_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID48_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID47_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID46_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID45_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID44_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID43_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID42_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID41_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID40_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID39_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID38_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID37_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID36_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID35_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID34_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID33_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID32_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN1__ATID63_EN___M      0x80000000
#define   DBG_CNTRn_ATID_EN1__ATID63_EN___S                   31
#define   DBG_CNTRn_ATID_EN1__ATID63_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID63_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID62_EN___M      0x40000000
#define   DBG_CNTRn_ATID_EN1__ATID62_EN___S                   30
#define   DBG_CNTRn_ATID_EN1__ATID62_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID62_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID61_EN___M      0x20000000
#define   DBG_CNTRn_ATID_EN1__ATID61_EN___S                   29
#define   DBG_CNTRn_ATID_EN1__ATID61_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID61_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID60_EN___M      0x10000000
#define   DBG_CNTRn_ATID_EN1__ATID60_EN___S                   28
#define   DBG_CNTRn_ATID_EN1__ATID60_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID60_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID59_EN___M      0x08000000
#define   DBG_CNTRn_ATID_EN1__ATID59_EN___S                   27
#define   DBG_CNTRn_ATID_EN1__ATID59_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID59_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID58_EN___M      0x04000000
#define   DBG_CNTRn_ATID_EN1__ATID58_EN___S                   26
#define   DBG_CNTRn_ATID_EN1__ATID58_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID58_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID57_EN___M      0x02000000
#define   DBG_CNTRn_ATID_EN1__ATID57_EN___S                   25
#define   DBG_CNTRn_ATID_EN1__ATID57_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID57_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID56_EN___M      0x01000000
#define   DBG_CNTRn_ATID_EN1__ATID56_EN___S                   24
#define   DBG_CNTRn_ATID_EN1__ATID56_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID56_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID55_EN___M      0x00800000
#define   DBG_CNTRn_ATID_EN1__ATID55_EN___S                   23
#define   DBG_CNTRn_ATID_EN1__ATID55_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID55_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID54_EN___M      0x00400000
#define   DBG_CNTRn_ATID_EN1__ATID54_EN___S                   22
#define   DBG_CNTRn_ATID_EN1__ATID54_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID54_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID53_EN___M      0x00200000
#define   DBG_CNTRn_ATID_EN1__ATID53_EN___S                   21
#define   DBG_CNTRn_ATID_EN1__ATID53_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID53_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID52_EN___M      0x00100000
#define   DBG_CNTRn_ATID_EN1__ATID52_EN___S                   20
#define   DBG_CNTRn_ATID_EN1__ATID52_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID52_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID51_EN___M      0x00080000
#define   DBG_CNTRn_ATID_EN1__ATID51_EN___S                   19
#define   DBG_CNTRn_ATID_EN1__ATID51_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID51_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID50_EN___M      0x00040000
#define   DBG_CNTRn_ATID_EN1__ATID50_EN___S                   18
#define   DBG_CNTRn_ATID_EN1__ATID50_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID50_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID49_EN___M      0x00020000
#define   DBG_CNTRn_ATID_EN1__ATID49_EN___S                   17
#define   DBG_CNTRn_ATID_EN1__ATID49_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID49_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID48_EN___M      0x00010000
#define   DBG_CNTRn_ATID_EN1__ATID48_EN___S                   16
#define   DBG_CNTRn_ATID_EN1__ATID48_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID48_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID47_EN___M      0x00008000
#define   DBG_CNTRn_ATID_EN1__ATID47_EN___S                   15
#define   DBG_CNTRn_ATID_EN1__ATID47_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID47_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID46_EN___M      0x00004000
#define   DBG_CNTRn_ATID_EN1__ATID46_EN___S                   14
#define   DBG_CNTRn_ATID_EN1__ATID46_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID46_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID45_EN___M      0x00002000
#define   DBG_CNTRn_ATID_EN1__ATID45_EN___S                   13
#define   DBG_CNTRn_ATID_EN1__ATID45_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID45_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID44_EN___M      0x00001000
#define   DBG_CNTRn_ATID_EN1__ATID44_EN___S                   12
#define   DBG_CNTRn_ATID_EN1__ATID44_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID44_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID43_EN___M      0x00000800
#define   DBG_CNTRn_ATID_EN1__ATID43_EN___S                   11
#define   DBG_CNTRn_ATID_EN1__ATID43_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID43_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID42_EN___M      0x00000400
#define   DBG_CNTRn_ATID_EN1__ATID42_EN___S                   10
#define   DBG_CNTRn_ATID_EN1__ATID42_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID42_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID41_EN___M      0x00000200
#define   DBG_CNTRn_ATID_EN1__ATID41_EN___S                    9
#define   DBG_CNTRn_ATID_EN1__ATID41_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID41_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID40_EN___M      0x00000100
#define   DBG_CNTRn_ATID_EN1__ATID40_EN___S                    8
#define   DBG_CNTRn_ATID_EN1__ATID40_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID40_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID39_EN___M      0x00000080
#define   DBG_CNTRn_ATID_EN1__ATID39_EN___S                    7
#define   DBG_CNTRn_ATID_EN1__ATID39_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID39_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID38_EN___M      0x00000040
#define   DBG_CNTRn_ATID_EN1__ATID38_EN___S                    6
#define   DBG_CNTRn_ATID_EN1__ATID38_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID38_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID37_EN___M      0x00000020
#define   DBG_CNTRn_ATID_EN1__ATID37_EN___S                    5
#define   DBG_CNTRn_ATID_EN1__ATID37_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID37_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID36_EN___M      0x00000010
#define   DBG_CNTRn_ATID_EN1__ATID36_EN___S                    4
#define   DBG_CNTRn_ATID_EN1__ATID36_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID36_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID35_EN___M      0x00000008
#define   DBG_CNTRn_ATID_EN1__ATID35_EN___S                    3
#define   DBG_CNTRn_ATID_EN1__ATID35_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID35_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID34_EN___M      0x00000004
#define   DBG_CNTRn_ATID_EN1__ATID34_EN___S                    2
#define   DBG_CNTRn_ATID_EN1__ATID34_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID34_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID33_EN___M      0x00000002
#define   DBG_CNTRn_ATID_EN1__ATID33_EN___S                    1
#define   DBG_CNTRn_ATID_EN1__ATID33_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID33_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1__ATID32_EN___M      0x00000001
#define   DBG_CNTRn_ATID_EN1__ATID32_EN___S                    0
#define   DBG_CNTRn_ATID_EN1__ATID32_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN1__ATID32_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN1___M                 0xFFFFFFFF   
#define   DBG_CNTRn_ATID_EN1___S                               0
#define DBG_CNTR0_ATID_EN1                        (0x00BC1008)
#define   DBG_CNTR0_ATID_EN1___RWC                  QCSR_REG_RW    
#define   DBG_CNTR0_ATID_EN1__ATID63_EN___M      0x80000000
#define   DBG_CNTR0_ATID_EN1__ATID63_EN___S                   31
#define   DBG_CNTR0_ATID_EN1__ATID62_EN___M      0x40000000
#define   DBG_CNTR0_ATID_EN1__ATID62_EN___S                   30
#define   DBG_CNTR0_ATID_EN1__ATID61_EN___M      0x20000000
#define   DBG_CNTR0_ATID_EN1__ATID61_EN___S                   29
#define   DBG_CNTR0_ATID_EN1__ATID60_EN___M      0x10000000
#define   DBG_CNTR0_ATID_EN1__ATID60_EN___S                   28
#define   DBG_CNTR0_ATID_EN1__ATID59_EN___M      0x08000000
#define   DBG_CNTR0_ATID_EN1__ATID59_EN___S                   27
#define   DBG_CNTR0_ATID_EN1__ATID58_EN___M      0x04000000
#define   DBG_CNTR0_ATID_EN1__ATID58_EN___S                   26
#define   DBG_CNTR0_ATID_EN1__ATID57_EN___M      0x02000000
#define   DBG_CNTR0_ATID_EN1__ATID57_EN___S                   25
#define   DBG_CNTR0_ATID_EN1__ATID56_EN___M      0x01000000
#define   DBG_CNTR0_ATID_EN1__ATID56_EN___S                   24
#define   DBG_CNTR0_ATID_EN1__ATID55_EN___M      0x00800000
#define   DBG_CNTR0_ATID_EN1__ATID55_EN___S                   23
#define   DBG_CNTR0_ATID_EN1__ATID54_EN___M      0x00400000
#define   DBG_CNTR0_ATID_EN1__ATID54_EN___S                   22
#define   DBG_CNTR0_ATID_EN1__ATID53_EN___M      0x00200000
#define   DBG_CNTR0_ATID_EN1__ATID53_EN___S                   21
#define   DBG_CNTR0_ATID_EN1__ATID52_EN___M      0x00100000
#define   DBG_CNTR0_ATID_EN1__ATID52_EN___S                   20
#define   DBG_CNTR0_ATID_EN1__ATID51_EN___M      0x00080000
#define   DBG_CNTR0_ATID_EN1__ATID51_EN___S                   19
#define   DBG_CNTR0_ATID_EN1__ATID50_EN___M      0x00040000
#define   DBG_CNTR0_ATID_EN1__ATID50_EN___S                   18
#define   DBG_CNTR0_ATID_EN1__ATID49_EN___M      0x00020000
#define   DBG_CNTR0_ATID_EN1__ATID49_EN___S                   17
#define   DBG_CNTR0_ATID_EN1__ATID48_EN___M      0x00010000
#define   DBG_CNTR0_ATID_EN1__ATID48_EN___S                   16
#define   DBG_CNTR0_ATID_EN1__ATID47_EN___M      0x00008000
#define   DBG_CNTR0_ATID_EN1__ATID47_EN___S                   15
#define   DBG_CNTR0_ATID_EN1__ATID46_EN___M      0x00004000
#define   DBG_CNTR0_ATID_EN1__ATID46_EN___S                   14
#define   DBG_CNTR0_ATID_EN1__ATID45_EN___M      0x00002000
#define   DBG_CNTR0_ATID_EN1__ATID45_EN___S                   13
#define   DBG_CNTR0_ATID_EN1__ATID44_EN___M      0x00001000
#define   DBG_CNTR0_ATID_EN1__ATID44_EN___S                   12
#define   DBG_CNTR0_ATID_EN1__ATID43_EN___M      0x00000800
#define   DBG_CNTR0_ATID_EN1__ATID43_EN___S                   11
#define   DBG_CNTR0_ATID_EN1__ATID42_EN___M      0x00000400
#define   DBG_CNTR0_ATID_EN1__ATID42_EN___S                   10
#define   DBG_CNTR0_ATID_EN1__ATID41_EN___M      0x00000200
#define   DBG_CNTR0_ATID_EN1__ATID41_EN___S                    9
#define   DBG_CNTR0_ATID_EN1__ATID40_EN___M      0x00000100
#define   DBG_CNTR0_ATID_EN1__ATID40_EN___S                    8
#define   DBG_CNTR0_ATID_EN1__ATID39_EN___M      0x00000080
#define   DBG_CNTR0_ATID_EN1__ATID39_EN___S                    7
#define   DBG_CNTR0_ATID_EN1__ATID38_EN___M      0x00000040
#define   DBG_CNTR0_ATID_EN1__ATID38_EN___S                    6
#define   DBG_CNTR0_ATID_EN1__ATID37_EN___M      0x00000020
#define   DBG_CNTR0_ATID_EN1__ATID37_EN___S                    5
#define   DBG_CNTR0_ATID_EN1__ATID36_EN___M      0x00000010
#define   DBG_CNTR0_ATID_EN1__ATID36_EN___S                    4
#define   DBG_CNTR0_ATID_EN1__ATID35_EN___M      0x00000008
#define   DBG_CNTR0_ATID_EN1__ATID35_EN___S                    3
#define   DBG_CNTR0_ATID_EN1__ATID34_EN___M      0x00000004
#define   DBG_CNTR0_ATID_EN1__ATID34_EN___S                    2
#define   DBG_CNTR0_ATID_EN1__ATID33_EN___M      0x00000002
#define   DBG_CNTR0_ATID_EN1__ATID33_EN___S                    1
#define   DBG_CNTR0_ATID_EN1__ATID32_EN___M      0x00000001
#define   DBG_CNTR0_ATID_EN1__ATID32_EN___S                    0
#define DBG_CNTR1_ATID_EN1                        (0x00BC1048)
#define   DBG_CNTR1_ATID_EN1___RWC                  QCSR_REG_RW    
#define   DBG_CNTR1_ATID_EN1__ATID63_EN___M      0x80000000
#define   DBG_CNTR1_ATID_EN1__ATID63_EN___S                   31
#define   DBG_CNTR1_ATID_EN1__ATID62_EN___M      0x40000000
#define   DBG_CNTR1_ATID_EN1__ATID62_EN___S                   30
#define   DBG_CNTR1_ATID_EN1__ATID61_EN___M      0x20000000
#define   DBG_CNTR1_ATID_EN1__ATID61_EN___S                   29
#define   DBG_CNTR1_ATID_EN1__ATID60_EN___M      0x10000000
#define   DBG_CNTR1_ATID_EN1__ATID60_EN___S                   28
#define   DBG_CNTR1_ATID_EN1__ATID59_EN___M      0x08000000
#define   DBG_CNTR1_ATID_EN1__ATID59_EN___S                   27
#define   DBG_CNTR1_ATID_EN1__ATID58_EN___M      0x04000000
#define   DBG_CNTR1_ATID_EN1__ATID58_EN___S                   26
#define   DBG_CNTR1_ATID_EN1__ATID57_EN___M      0x02000000
#define   DBG_CNTR1_ATID_EN1__ATID57_EN___S                   25
#define   DBG_CNTR1_ATID_EN1__ATID56_EN___M      0x01000000
#define   DBG_CNTR1_ATID_EN1__ATID56_EN___S                   24
#define   DBG_CNTR1_ATID_EN1__ATID55_EN___M      0x00800000
#define   DBG_CNTR1_ATID_EN1__ATID55_EN___S                   23
#define   DBG_CNTR1_ATID_EN1__ATID54_EN___M      0x00400000
#define   DBG_CNTR1_ATID_EN1__ATID54_EN___S                   22
#define   DBG_CNTR1_ATID_EN1__ATID53_EN___M      0x00200000
#define   DBG_CNTR1_ATID_EN1__ATID53_EN___S                   21
#define   DBG_CNTR1_ATID_EN1__ATID52_EN___M      0x00100000
#define   DBG_CNTR1_ATID_EN1__ATID52_EN___S                   20
#define   DBG_CNTR1_ATID_EN1__ATID51_EN___M      0x00080000
#define   DBG_CNTR1_ATID_EN1__ATID51_EN___S                   19
#define   DBG_CNTR1_ATID_EN1__ATID50_EN___M      0x00040000
#define   DBG_CNTR1_ATID_EN1__ATID50_EN___S                   18
#define   DBG_CNTR1_ATID_EN1__ATID49_EN___M      0x00020000
#define   DBG_CNTR1_ATID_EN1__ATID49_EN___S                   17
#define   DBG_CNTR1_ATID_EN1__ATID48_EN___M      0x00010000
#define   DBG_CNTR1_ATID_EN1__ATID48_EN___S                   16
#define   DBG_CNTR1_ATID_EN1__ATID47_EN___M      0x00008000
#define   DBG_CNTR1_ATID_EN1__ATID47_EN___S                   15
#define   DBG_CNTR1_ATID_EN1__ATID46_EN___M      0x00004000
#define   DBG_CNTR1_ATID_EN1__ATID46_EN___S                   14
#define   DBG_CNTR1_ATID_EN1__ATID45_EN___M      0x00002000
#define   DBG_CNTR1_ATID_EN1__ATID45_EN___S                   13
#define   DBG_CNTR1_ATID_EN1__ATID44_EN___M      0x00001000
#define   DBG_CNTR1_ATID_EN1__ATID44_EN___S                   12
#define   DBG_CNTR1_ATID_EN1__ATID43_EN___M      0x00000800
#define   DBG_CNTR1_ATID_EN1__ATID43_EN___S                   11
#define   DBG_CNTR1_ATID_EN1__ATID42_EN___M      0x00000400
#define   DBG_CNTR1_ATID_EN1__ATID42_EN___S                   10
#define   DBG_CNTR1_ATID_EN1__ATID41_EN___M      0x00000200
#define   DBG_CNTR1_ATID_EN1__ATID41_EN___S                    9
#define   DBG_CNTR1_ATID_EN1__ATID40_EN___M      0x00000100
#define   DBG_CNTR1_ATID_EN1__ATID40_EN___S                    8
#define   DBG_CNTR1_ATID_EN1__ATID39_EN___M      0x00000080
#define   DBG_CNTR1_ATID_EN1__ATID39_EN___S                    7
#define   DBG_CNTR1_ATID_EN1__ATID38_EN___M      0x00000040
#define   DBG_CNTR1_ATID_EN1__ATID38_EN___S                    6
#define   DBG_CNTR1_ATID_EN1__ATID37_EN___M      0x00000020
#define   DBG_CNTR1_ATID_EN1__ATID37_EN___S                    5
#define   DBG_CNTR1_ATID_EN1__ATID36_EN___M      0x00000010
#define   DBG_CNTR1_ATID_EN1__ATID36_EN___S                    4
#define   DBG_CNTR1_ATID_EN1__ATID35_EN___M      0x00000008
#define   DBG_CNTR1_ATID_EN1__ATID35_EN___S                    3
#define   DBG_CNTR1_ATID_EN1__ATID34_EN___M      0x00000004
#define   DBG_CNTR1_ATID_EN1__ATID34_EN___S                    2
#define   DBG_CNTR1_ATID_EN1__ATID33_EN___M      0x00000002
#define   DBG_CNTR1_ATID_EN1__ATID33_EN___S                    1
#define   DBG_CNTR1_ATID_EN1__ATID32_EN___M      0x00000001
#define   DBG_CNTR1_ATID_EN1__ATID32_EN___S                    0
#define DBG_CNTR2_ATID_EN1                        (0x00BC1088)
#define   DBG_CNTR2_ATID_EN1___RWC                  QCSR_REG_RW    
#define   DBG_CNTR2_ATID_EN1__ATID63_EN___M      0x80000000
#define   DBG_CNTR2_ATID_EN1__ATID63_EN___S                   31
#define   DBG_CNTR2_ATID_EN1__ATID62_EN___M      0x40000000
#define   DBG_CNTR2_ATID_EN1__ATID62_EN___S                   30
#define   DBG_CNTR2_ATID_EN1__ATID61_EN___M      0x20000000
#define   DBG_CNTR2_ATID_EN1__ATID61_EN___S                   29
#define   DBG_CNTR2_ATID_EN1__ATID60_EN___M      0x10000000
#define   DBG_CNTR2_ATID_EN1__ATID60_EN___S                   28
#define   DBG_CNTR2_ATID_EN1__ATID59_EN___M      0x08000000
#define   DBG_CNTR2_ATID_EN1__ATID59_EN___S                   27
#define   DBG_CNTR2_ATID_EN1__ATID58_EN___M      0x04000000
#define   DBG_CNTR2_ATID_EN1__ATID58_EN___S                   26
#define   DBG_CNTR2_ATID_EN1__ATID57_EN___M      0x02000000
#define   DBG_CNTR2_ATID_EN1__ATID57_EN___S                   25
#define   DBG_CNTR2_ATID_EN1__ATID56_EN___M      0x01000000
#define   DBG_CNTR2_ATID_EN1__ATID56_EN___S                   24
#define   DBG_CNTR2_ATID_EN1__ATID55_EN___M      0x00800000
#define   DBG_CNTR2_ATID_EN1__ATID55_EN___S                   23
#define   DBG_CNTR2_ATID_EN1__ATID54_EN___M      0x00400000
#define   DBG_CNTR2_ATID_EN1__ATID54_EN___S                   22
#define   DBG_CNTR2_ATID_EN1__ATID53_EN___M      0x00200000
#define   DBG_CNTR2_ATID_EN1__ATID53_EN___S                   21
#define   DBG_CNTR2_ATID_EN1__ATID52_EN___M      0x00100000
#define   DBG_CNTR2_ATID_EN1__ATID52_EN___S                   20
#define   DBG_CNTR2_ATID_EN1__ATID51_EN___M      0x00080000
#define   DBG_CNTR2_ATID_EN1__ATID51_EN___S                   19
#define   DBG_CNTR2_ATID_EN1__ATID50_EN___M      0x00040000
#define   DBG_CNTR2_ATID_EN1__ATID50_EN___S                   18
#define   DBG_CNTR2_ATID_EN1__ATID49_EN___M      0x00020000
#define   DBG_CNTR2_ATID_EN1__ATID49_EN___S                   17
#define   DBG_CNTR2_ATID_EN1__ATID48_EN___M      0x00010000
#define   DBG_CNTR2_ATID_EN1__ATID48_EN___S                   16
#define   DBG_CNTR2_ATID_EN1__ATID47_EN___M      0x00008000
#define   DBG_CNTR2_ATID_EN1__ATID47_EN___S                   15
#define   DBG_CNTR2_ATID_EN1__ATID46_EN___M      0x00004000
#define   DBG_CNTR2_ATID_EN1__ATID46_EN___S                   14
#define   DBG_CNTR2_ATID_EN1__ATID45_EN___M      0x00002000
#define   DBG_CNTR2_ATID_EN1__ATID45_EN___S                   13
#define   DBG_CNTR2_ATID_EN1__ATID44_EN___M      0x00001000
#define   DBG_CNTR2_ATID_EN1__ATID44_EN___S                   12
#define   DBG_CNTR2_ATID_EN1__ATID43_EN___M      0x00000800
#define   DBG_CNTR2_ATID_EN1__ATID43_EN___S                   11
#define   DBG_CNTR2_ATID_EN1__ATID42_EN___M      0x00000400
#define   DBG_CNTR2_ATID_EN1__ATID42_EN___S                   10
#define   DBG_CNTR2_ATID_EN1__ATID41_EN___M      0x00000200
#define   DBG_CNTR2_ATID_EN1__ATID41_EN___S                    9
#define   DBG_CNTR2_ATID_EN1__ATID40_EN___M      0x00000100
#define   DBG_CNTR2_ATID_EN1__ATID40_EN___S                    8
#define   DBG_CNTR2_ATID_EN1__ATID39_EN___M      0x00000080
#define   DBG_CNTR2_ATID_EN1__ATID39_EN___S                    7
#define   DBG_CNTR2_ATID_EN1__ATID38_EN___M      0x00000040
#define   DBG_CNTR2_ATID_EN1__ATID38_EN___S                    6
#define   DBG_CNTR2_ATID_EN1__ATID37_EN___M      0x00000020
#define   DBG_CNTR2_ATID_EN1__ATID37_EN___S                    5
#define   DBG_CNTR2_ATID_EN1__ATID36_EN___M      0x00000010
#define   DBG_CNTR2_ATID_EN1__ATID36_EN___S                    4
#define   DBG_CNTR2_ATID_EN1__ATID35_EN___M      0x00000008
#define   DBG_CNTR2_ATID_EN1__ATID35_EN___S                    3
#define   DBG_CNTR2_ATID_EN1__ATID34_EN___M      0x00000004
#define   DBG_CNTR2_ATID_EN1__ATID34_EN___S                    2
#define   DBG_CNTR2_ATID_EN1__ATID33_EN___M      0x00000002
#define   DBG_CNTR2_ATID_EN1__ATID33_EN___S                    1
#define   DBG_CNTR2_ATID_EN1__ATID32_EN___M      0x00000001
#define   DBG_CNTR2_ATID_EN1__ATID32_EN___S                    0
#define DBG_CNTR3_ATID_EN1                        (0x00BC10C8)
#define   DBG_CNTR3_ATID_EN1___RWC                  QCSR_REG_RW    
#define   DBG_CNTR3_ATID_EN1__ATID63_EN___M      0x80000000
#define   DBG_CNTR3_ATID_EN1__ATID63_EN___S                   31
#define   DBG_CNTR3_ATID_EN1__ATID62_EN___M      0x40000000
#define   DBG_CNTR3_ATID_EN1__ATID62_EN___S                   30
#define   DBG_CNTR3_ATID_EN1__ATID61_EN___M      0x20000000
#define   DBG_CNTR3_ATID_EN1__ATID61_EN___S                   29
#define   DBG_CNTR3_ATID_EN1__ATID60_EN___M      0x10000000
#define   DBG_CNTR3_ATID_EN1__ATID60_EN___S                   28
#define   DBG_CNTR3_ATID_EN1__ATID59_EN___M      0x08000000
#define   DBG_CNTR3_ATID_EN1__ATID59_EN___S                   27
#define   DBG_CNTR3_ATID_EN1__ATID58_EN___M      0x04000000
#define   DBG_CNTR3_ATID_EN1__ATID58_EN___S                   26
#define   DBG_CNTR3_ATID_EN1__ATID57_EN___M      0x02000000
#define   DBG_CNTR3_ATID_EN1__ATID57_EN___S                   25
#define   DBG_CNTR3_ATID_EN1__ATID56_EN___M      0x01000000
#define   DBG_CNTR3_ATID_EN1__ATID56_EN___S                   24
#define   DBG_CNTR3_ATID_EN1__ATID55_EN___M      0x00800000
#define   DBG_CNTR3_ATID_EN1__ATID55_EN___S                   23
#define   DBG_CNTR3_ATID_EN1__ATID54_EN___M      0x00400000
#define   DBG_CNTR3_ATID_EN1__ATID54_EN___S                   22
#define   DBG_CNTR3_ATID_EN1__ATID53_EN___M      0x00200000
#define   DBG_CNTR3_ATID_EN1__ATID53_EN___S                   21
#define   DBG_CNTR3_ATID_EN1__ATID52_EN___M      0x00100000
#define   DBG_CNTR3_ATID_EN1__ATID52_EN___S                   20
#define   DBG_CNTR3_ATID_EN1__ATID51_EN___M      0x00080000
#define   DBG_CNTR3_ATID_EN1__ATID51_EN___S                   19
#define   DBG_CNTR3_ATID_EN1__ATID50_EN___M      0x00040000
#define   DBG_CNTR3_ATID_EN1__ATID50_EN___S                   18
#define   DBG_CNTR3_ATID_EN1__ATID49_EN___M      0x00020000
#define   DBG_CNTR3_ATID_EN1__ATID49_EN___S                   17
#define   DBG_CNTR3_ATID_EN1__ATID48_EN___M      0x00010000
#define   DBG_CNTR3_ATID_EN1__ATID48_EN___S                   16
#define   DBG_CNTR3_ATID_EN1__ATID47_EN___M      0x00008000
#define   DBG_CNTR3_ATID_EN1__ATID47_EN___S                   15
#define   DBG_CNTR3_ATID_EN1__ATID46_EN___M      0x00004000
#define   DBG_CNTR3_ATID_EN1__ATID46_EN___S                   14
#define   DBG_CNTR3_ATID_EN1__ATID45_EN___M      0x00002000
#define   DBG_CNTR3_ATID_EN1__ATID45_EN___S                   13
#define   DBG_CNTR3_ATID_EN1__ATID44_EN___M      0x00001000
#define   DBG_CNTR3_ATID_EN1__ATID44_EN___S                   12
#define   DBG_CNTR3_ATID_EN1__ATID43_EN___M      0x00000800
#define   DBG_CNTR3_ATID_EN1__ATID43_EN___S                   11
#define   DBG_CNTR3_ATID_EN1__ATID42_EN___M      0x00000400
#define   DBG_CNTR3_ATID_EN1__ATID42_EN___S                   10
#define   DBG_CNTR3_ATID_EN1__ATID41_EN___M      0x00000200
#define   DBG_CNTR3_ATID_EN1__ATID41_EN___S                    9
#define   DBG_CNTR3_ATID_EN1__ATID40_EN___M      0x00000100
#define   DBG_CNTR3_ATID_EN1__ATID40_EN___S                    8
#define   DBG_CNTR3_ATID_EN1__ATID39_EN___M      0x00000080
#define   DBG_CNTR3_ATID_EN1__ATID39_EN___S                    7
#define   DBG_CNTR3_ATID_EN1__ATID38_EN___M      0x00000040
#define   DBG_CNTR3_ATID_EN1__ATID38_EN___S                    6
#define   DBG_CNTR3_ATID_EN1__ATID37_EN___M      0x00000020
#define   DBG_CNTR3_ATID_EN1__ATID37_EN___S                    5
#define   DBG_CNTR3_ATID_EN1__ATID36_EN___M      0x00000010
#define   DBG_CNTR3_ATID_EN1__ATID36_EN___S                    4
#define   DBG_CNTR3_ATID_EN1__ATID35_EN___M      0x00000008
#define   DBG_CNTR3_ATID_EN1__ATID35_EN___S                    3
#define   DBG_CNTR3_ATID_EN1__ATID34_EN___M      0x00000004
#define   DBG_CNTR3_ATID_EN1__ATID34_EN___S                    2
#define   DBG_CNTR3_ATID_EN1__ATID33_EN___M      0x00000002
#define   DBG_CNTR3_ATID_EN1__ATID33_EN___S                    1
#define   DBG_CNTR3_ATID_EN1__ATID32_EN___M      0x00000001
#define   DBG_CNTR3_ATID_EN1__ATID32_EN___S                    0

#define DBG_CNTRn_ATID_EN2(n)            (0x00BC100C+0x40*(n))
#define   DBG_CNTRn_ATID_EN2_nMIN  0    
#define   DBG_CNTRn_ATID_EN2_nMAX  3    
#define   DBG_CNTRn_ATID_EN2_ELEM  4    
#define   DBG_CNTRn_ATID_EN2___RWC                  QCSR_REG_RW    
#define   DBG_CNTRn_ATID_EN2___POR               0xFFFFFFFF
#define   DBG_CNTRn_ATID_EN2__ATID95_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID94_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID93_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID92_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID91_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID90_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID89_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID88_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID87_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID86_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID85_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID84_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID83_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID82_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID81_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID80_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID79_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID78_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID77_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID76_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID75_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID74_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID73_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID72_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID71_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID70_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID69_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID68_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID67_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID66_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID65_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID64_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN2__ATID95_EN___M      0x80000000
#define   DBG_CNTRn_ATID_EN2__ATID95_EN___S                   31
#define   DBG_CNTRn_ATID_EN2__ATID95_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID95_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID94_EN___M      0x40000000
#define   DBG_CNTRn_ATID_EN2__ATID94_EN___S                   30
#define   DBG_CNTRn_ATID_EN2__ATID94_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID94_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID93_EN___M      0x20000000
#define   DBG_CNTRn_ATID_EN2__ATID93_EN___S                   29
#define   DBG_CNTRn_ATID_EN2__ATID93_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID93_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID92_EN___M      0x10000000
#define   DBG_CNTRn_ATID_EN2__ATID92_EN___S                   28
#define   DBG_CNTRn_ATID_EN2__ATID92_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID92_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID91_EN___M      0x08000000
#define   DBG_CNTRn_ATID_EN2__ATID91_EN___S                   27
#define   DBG_CNTRn_ATID_EN2__ATID91_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID91_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID90_EN___M      0x04000000
#define   DBG_CNTRn_ATID_EN2__ATID90_EN___S                   26
#define   DBG_CNTRn_ATID_EN2__ATID90_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID90_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID89_EN___M      0x02000000
#define   DBG_CNTRn_ATID_EN2__ATID89_EN___S                   25
#define   DBG_CNTRn_ATID_EN2__ATID89_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID89_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID88_EN___M      0x01000000
#define   DBG_CNTRn_ATID_EN2__ATID88_EN___S                   24
#define   DBG_CNTRn_ATID_EN2__ATID88_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID88_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID87_EN___M      0x00800000
#define   DBG_CNTRn_ATID_EN2__ATID87_EN___S                   23
#define   DBG_CNTRn_ATID_EN2__ATID87_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID87_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID86_EN___M      0x00400000
#define   DBG_CNTRn_ATID_EN2__ATID86_EN___S                   22
#define   DBG_CNTRn_ATID_EN2__ATID86_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID86_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID85_EN___M      0x00200000
#define   DBG_CNTRn_ATID_EN2__ATID85_EN___S                   21
#define   DBG_CNTRn_ATID_EN2__ATID85_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID85_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID84_EN___M      0x00100000
#define   DBG_CNTRn_ATID_EN2__ATID84_EN___S                   20
#define   DBG_CNTRn_ATID_EN2__ATID84_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID84_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID83_EN___M      0x00080000
#define   DBG_CNTRn_ATID_EN2__ATID83_EN___S                   19
#define   DBG_CNTRn_ATID_EN2__ATID83_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID83_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID82_EN___M      0x00040000
#define   DBG_CNTRn_ATID_EN2__ATID82_EN___S                   18
#define   DBG_CNTRn_ATID_EN2__ATID82_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID82_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID81_EN___M      0x00020000
#define   DBG_CNTRn_ATID_EN2__ATID81_EN___S                   17
#define   DBG_CNTRn_ATID_EN2__ATID81_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID81_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID80_EN___M      0x00010000
#define   DBG_CNTRn_ATID_EN2__ATID80_EN___S                   16
#define   DBG_CNTRn_ATID_EN2__ATID80_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID80_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID79_EN___M      0x00008000
#define   DBG_CNTRn_ATID_EN2__ATID79_EN___S                   15
#define   DBG_CNTRn_ATID_EN2__ATID79_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID79_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID78_EN___M      0x00004000
#define   DBG_CNTRn_ATID_EN2__ATID78_EN___S                   14
#define   DBG_CNTRn_ATID_EN2__ATID78_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID78_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID77_EN___M      0x00002000
#define   DBG_CNTRn_ATID_EN2__ATID77_EN___S                   13
#define   DBG_CNTRn_ATID_EN2__ATID77_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID77_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID76_EN___M      0x00001000
#define   DBG_CNTRn_ATID_EN2__ATID76_EN___S                   12
#define   DBG_CNTRn_ATID_EN2__ATID76_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID76_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID75_EN___M      0x00000800
#define   DBG_CNTRn_ATID_EN2__ATID75_EN___S                   11
#define   DBG_CNTRn_ATID_EN2__ATID75_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID75_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID74_EN___M      0x00000400
#define   DBG_CNTRn_ATID_EN2__ATID74_EN___S                   10
#define   DBG_CNTRn_ATID_EN2__ATID74_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID74_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID73_EN___M      0x00000200
#define   DBG_CNTRn_ATID_EN2__ATID73_EN___S                    9
#define   DBG_CNTRn_ATID_EN2__ATID73_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID73_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID72_EN___M      0x00000100
#define   DBG_CNTRn_ATID_EN2__ATID72_EN___S                    8
#define   DBG_CNTRn_ATID_EN2__ATID72_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID72_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID71_EN___M      0x00000080
#define   DBG_CNTRn_ATID_EN2__ATID71_EN___S                    7
#define   DBG_CNTRn_ATID_EN2__ATID71_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID71_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID70_EN___M      0x00000040
#define   DBG_CNTRn_ATID_EN2__ATID70_EN___S                    6
#define   DBG_CNTRn_ATID_EN2__ATID70_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID70_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID69_EN___M      0x00000020
#define   DBG_CNTRn_ATID_EN2__ATID69_EN___S                    5
#define   DBG_CNTRn_ATID_EN2__ATID69_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID69_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID68_EN___M      0x00000010
#define   DBG_CNTRn_ATID_EN2__ATID68_EN___S                    4
#define   DBG_CNTRn_ATID_EN2__ATID68_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID68_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID67_EN___M      0x00000008
#define   DBG_CNTRn_ATID_EN2__ATID67_EN___S                    3
#define   DBG_CNTRn_ATID_EN2__ATID67_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID67_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID66_EN___M      0x00000004
#define   DBG_CNTRn_ATID_EN2__ATID66_EN___S                    2
#define   DBG_CNTRn_ATID_EN2__ATID66_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID66_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID65_EN___M      0x00000002
#define   DBG_CNTRn_ATID_EN2__ATID65_EN___S                    1
#define   DBG_CNTRn_ATID_EN2__ATID65_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID65_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2__ATID64_EN___M      0x00000001
#define   DBG_CNTRn_ATID_EN2__ATID64_EN___S                    0
#define   DBG_CNTRn_ATID_EN2__ATID64_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN2__ATID64_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN2___M                 0xFFFFFFFF   
#define   DBG_CNTRn_ATID_EN2___S                               0
#define DBG_CNTR0_ATID_EN2                        (0x00BC100C)
#define   DBG_CNTR0_ATID_EN2___RWC                  QCSR_REG_RW    
#define   DBG_CNTR0_ATID_EN2__ATID95_EN___M      0x80000000
#define   DBG_CNTR0_ATID_EN2__ATID95_EN___S                   31
#define   DBG_CNTR0_ATID_EN2__ATID94_EN___M      0x40000000
#define   DBG_CNTR0_ATID_EN2__ATID94_EN___S                   30
#define   DBG_CNTR0_ATID_EN2__ATID93_EN___M      0x20000000
#define   DBG_CNTR0_ATID_EN2__ATID93_EN___S                   29
#define   DBG_CNTR0_ATID_EN2__ATID92_EN___M      0x10000000
#define   DBG_CNTR0_ATID_EN2__ATID92_EN___S                   28
#define   DBG_CNTR0_ATID_EN2__ATID91_EN___M      0x08000000
#define   DBG_CNTR0_ATID_EN2__ATID91_EN___S                   27
#define   DBG_CNTR0_ATID_EN2__ATID90_EN___M      0x04000000
#define   DBG_CNTR0_ATID_EN2__ATID90_EN___S                   26
#define   DBG_CNTR0_ATID_EN2__ATID89_EN___M      0x02000000
#define   DBG_CNTR0_ATID_EN2__ATID89_EN___S                   25
#define   DBG_CNTR0_ATID_EN2__ATID88_EN___M      0x01000000
#define   DBG_CNTR0_ATID_EN2__ATID88_EN___S                   24
#define   DBG_CNTR0_ATID_EN2__ATID87_EN___M      0x00800000
#define   DBG_CNTR0_ATID_EN2__ATID87_EN___S                   23
#define   DBG_CNTR0_ATID_EN2__ATID86_EN___M      0x00400000
#define   DBG_CNTR0_ATID_EN2__ATID86_EN___S                   22
#define   DBG_CNTR0_ATID_EN2__ATID85_EN___M      0x00200000
#define   DBG_CNTR0_ATID_EN2__ATID85_EN___S                   21
#define   DBG_CNTR0_ATID_EN2__ATID84_EN___M      0x00100000
#define   DBG_CNTR0_ATID_EN2__ATID84_EN___S                   20
#define   DBG_CNTR0_ATID_EN2__ATID83_EN___M      0x00080000
#define   DBG_CNTR0_ATID_EN2__ATID83_EN___S                   19
#define   DBG_CNTR0_ATID_EN2__ATID82_EN___M      0x00040000
#define   DBG_CNTR0_ATID_EN2__ATID82_EN___S                   18
#define   DBG_CNTR0_ATID_EN2__ATID81_EN___M      0x00020000
#define   DBG_CNTR0_ATID_EN2__ATID81_EN___S                   17
#define   DBG_CNTR0_ATID_EN2__ATID80_EN___M      0x00010000
#define   DBG_CNTR0_ATID_EN2__ATID80_EN___S                   16
#define   DBG_CNTR0_ATID_EN2__ATID79_EN___M      0x00008000
#define   DBG_CNTR0_ATID_EN2__ATID79_EN___S                   15
#define   DBG_CNTR0_ATID_EN2__ATID78_EN___M      0x00004000
#define   DBG_CNTR0_ATID_EN2__ATID78_EN___S                   14
#define   DBG_CNTR0_ATID_EN2__ATID77_EN___M      0x00002000
#define   DBG_CNTR0_ATID_EN2__ATID77_EN___S                   13
#define   DBG_CNTR0_ATID_EN2__ATID76_EN___M      0x00001000
#define   DBG_CNTR0_ATID_EN2__ATID76_EN___S                   12
#define   DBG_CNTR0_ATID_EN2__ATID75_EN___M      0x00000800
#define   DBG_CNTR0_ATID_EN2__ATID75_EN___S                   11
#define   DBG_CNTR0_ATID_EN2__ATID74_EN___M      0x00000400
#define   DBG_CNTR0_ATID_EN2__ATID74_EN___S                   10
#define   DBG_CNTR0_ATID_EN2__ATID73_EN___M      0x00000200
#define   DBG_CNTR0_ATID_EN2__ATID73_EN___S                    9
#define   DBG_CNTR0_ATID_EN2__ATID72_EN___M      0x00000100
#define   DBG_CNTR0_ATID_EN2__ATID72_EN___S                    8
#define   DBG_CNTR0_ATID_EN2__ATID71_EN___M      0x00000080
#define   DBG_CNTR0_ATID_EN2__ATID71_EN___S                    7
#define   DBG_CNTR0_ATID_EN2__ATID70_EN___M      0x00000040
#define   DBG_CNTR0_ATID_EN2__ATID70_EN___S                    6
#define   DBG_CNTR0_ATID_EN2__ATID69_EN___M      0x00000020
#define   DBG_CNTR0_ATID_EN2__ATID69_EN___S                    5
#define   DBG_CNTR0_ATID_EN2__ATID68_EN___M      0x00000010
#define   DBG_CNTR0_ATID_EN2__ATID68_EN___S                    4
#define   DBG_CNTR0_ATID_EN2__ATID67_EN___M      0x00000008
#define   DBG_CNTR0_ATID_EN2__ATID67_EN___S                    3
#define   DBG_CNTR0_ATID_EN2__ATID66_EN___M      0x00000004
#define   DBG_CNTR0_ATID_EN2__ATID66_EN___S                    2
#define   DBG_CNTR0_ATID_EN2__ATID65_EN___M      0x00000002
#define   DBG_CNTR0_ATID_EN2__ATID65_EN___S                    1
#define   DBG_CNTR0_ATID_EN2__ATID64_EN___M      0x00000001
#define   DBG_CNTR0_ATID_EN2__ATID64_EN___S                    0
#define DBG_CNTR1_ATID_EN2                        (0x00BC104C)
#define   DBG_CNTR1_ATID_EN2___RWC                  QCSR_REG_RW    
#define   DBG_CNTR1_ATID_EN2__ATID95_EN___M      0x80000000
#define   DBG_CNTR1_ATID_EN2__ATID95_EN___S                   31
#define   DBG_CNTR1_ATID_EN2__ATID94_EN___M      0x40000000
#define   DBG_CNTR1_ATID_EN2__ATID94_EN___S                   30
#define   DBG_CNTR1_ATID_EN2__ATID93_EN___M      0x20000000
#define   DBG_CNTR1_ATID_EN2__ATID93_EN___S                   29
#define   DBG_CNTR1_ATID_EN2__ATID92_EN___M      0x10000000
#define   DBG_CNTR1_ATID_EN2__ATID92_EN___S                   28
#define   DBG_CNTR1_ATID_EN2__ATID91_EN___M      0x08000000
#define   DBG_CNTR1_ATID_EN2__ATID91_EN___S                   27
#define   DBG_CNTR1_ATID_EN2__ATID90_EN___M      0x04000000
#define   DBG_CNTR1_ATID_EN2__ATID90_EN___S                   26
#define   DBG_CNTR1_ATID_EN2__ATID89_EN___M      0x02000000
#define   DBG_CNTR1_ATID_EN2__ATID89_EN___S                   25
#define   DBG_CNTR1_ATID_EN2__ATID88_EN___M      0x01000000
#define   DBG_CNTR1_ATID_EN2__ATID88_EN___S                   24
#define   DBG_CNTR1_ATID_EN2__ATID87_EN___M      0x00800000
#define   DBG_CNTR1_ATID_EN2__ATID87_EN___S                   23
#define   DBG_CNTR1_ATID_EN2__ATID86_EN___M      0x00400000
#define   DBG_CNTR1_ATID_EN2__ATID86_EN___S                   22
#define   DBG_CNTR1_ATID_EN2__ATID85_EN___M      0x00200000
#define   DBG_CNTR1_ATID_EN2__ATID85_EN___S                   21
#define   DBG_CNTR1_ATID_EN2__ATID84_EN___M      0x00100000
#define   DBG_CNTR1_ATID_EN2__ATID84_EN___S                   20
#define   DBG_CNTR1_ATID_EN2__ATID83_EN___M      0x00080000
#define   DBG_CNTR1_ATID_EN2__ATID83_EN___S                   19
#define   DBG_CNTR1_ATID_EN2__ATID82_EN___M      0x00040000
#define   DBG_CNTR1_ATID_EN2__ATID82_EN___S                   18
#define   DBG_CNTR1_ATID_EN2__ATID81_EN___M      0x00020000
#define   DBG_CNTR1_ATID_EN2__ATID81_EN___S                   17
#define   DBG_CNTR1_ATID_EN2__ATID80_EN___M      0x00010000
#define   DBG_CNTR1_ATID_EN2__ATID80_EN___S                   16
#define   DBG_CNTR1_ATID_EN2__ATID79_EN___M      0x00008000
#define   DBG_CNTR1_ATID_EN2__ATID79_EN___S                   15
#define   DBG_CNTR1_ATID_EN2__ATID78_EN___M      0x00004000
#define   DBG_CNTR1_ATID_EN2__ATID78_EN___S                   14
#define   DBG_CNTR1_ATID_EN2__ATID77_EN___M      0x00002000
#define   DBG_CNTR1_ATID_EN2__ATID77_EN___S                   13
#define   DBG_CNTR1_ATID_EN2__ATID76_EN___M      0x00001000
#define   DBG_CNTR1_ATID_EN2__ATID76_EN___S                   12
#define   DBG_CNTR1_ATID_EN2__ATID75_EN___M      0x00000800
#define   DBG_CNTR1_ATID_EN2__ATID75_EN___S                   11
#define   DBG_CNTR1_ATID_EN2__ATID74_EN___M      0x00000400
#define   DBG_CNTR1_ATID_EN2__ATID74_EN___S                   10
#define   DBG_CNTR1_ATID_EN2__ATID73_EN___M      0x00000200
#define   DBG_CNTR1_ATID_EN2__ATID73_EN___S                    9
#define   DBG_CNTR1_ATID_EN2__ATID72_EN___M      0x00000100
#define   DBG_CNTR1_ATID_EN2__ATID72_EN___S                    8
#define   DBG_CNTR1_ATID_EN2__ATID71_EN___M      0x00000080
#define   DBG_CNTR1_ATID_EN2__ATID71_EN___S                    7
#define   DBG_CNTR1_ATID_EN2__ATID70_EN___M      0x00000040
#define   DBG_CNTR1_ATID_EN2__ATID70_EN___S                    6
#define   DBG_CNTR1_ATID_EN2__ATID69_EN___M      0x00000020
#define   DBG_CNTR1_ATID_EN2__ATID69_EN___S                    5
#define   DBG_CNTR1_ATID_EN2__ATID68_EN___M      0x00000010
#define   DBG_CNTR1_ATID_EN2__ATID68_EN___S                    4
#define   DBG_CNTR1_ATID_EN2__ATID67_EN___M      0x00000008
#define   DBG_CNTR1_ATID_EN2__ATID67_EN___S                    3
#define   DBG_CNTR1_ATID_EN2__ATID66_EN___M      0x00000004
#define   DBG_CNTR1_ATID_EN2__ATID66_EN___S                    2
#define   DBG_CNTR1_ATID_EN2__ATID65_EN___M      0x00000002
#define   DBG_CNTR1_ATID_EN2__ATID65_EN___S                    1
#define   DBG_CNTR1_ATID_EN2__ATID64_EN___M      0x00000001
#define   DBG_CNTR1_ATID_EN2__ATID64_EN___S                    0
#define DBG_CNTR2_ATID_EN2                        (0x00BC108C)
#define   DBG_CNTR2_ATID_EN2___RWC                  QCSR_REG_RW    
#define   DBG_CNTR2_ATID_EN2__ATID95_EN___M      0x80000000
#define   DBG_CNTR2_ATID_EN2__ATID95_EN___S                   31
#define   DBG_CNTR2_ATID_EN2__ATID94_EN___M      0x40000000
#define   DBG_CNTR2_ATID_EN2__ATID94_EN___S                   30
#define   DBG_CNTR2_ATID_EN2__ATID93_EN___M      0x20000000
#define   DBG_CNTR2_ATID_EN2__ATID93_EN___S                   29
#define   DBG_CNTR2_ATID_EN2__ATID92_EN___M      0x10000000
#define   DBG_CNTR2_ATID_EN2__ATID92_EN___S                   28
#define   DBG_CNTR2_ATID_EN2__ATID91_EN___M      0x08000000
#define   DBG_CNTR2_ATID_EN2__ATID91_EN___S                   27
#define   DBG_CNTR2_ATID_EN2__ATID90_EN___M      0x04000000
#define   DBG_CNTR2_ATID_EN2__ATID90_EN___S                   26
#define   DBG_CNTR2_ATID_EN2__ATID89_EN___M      0x02000000
#define   DBG_CNTR2_ATID_EN2__ATID89_EN___S                   25
#define   DBG_CNTR2_ATID_EN2__ATID88_EN___M      0x01000000
#define   DBG_CNTR2_ATID_EN2__ATID88_EN___S                   24
#define   DBG_CNTR2_ATID_EN2__ATID87_EN___M      0x00800000
#define   DBG_CNTR2_ATID_EN2__ATID87_EN___S                   23
#define   DBG_CNTR2_ATID_EN2__ATID86_EN___M      0x00400000
#define   DBG_CNTR2_ATID_EN2__ATID86_EN___S                   22
#define   DBG_CNTR2_ATID_EN2__ATID85_EN___M      0x00200000
#define   DBG_CNTR2_ATID_EN2__ATID85_EN___S                   21
#define   DBG_CNTR2_ATID_EN2__ATID84_EN___M      0x00100000
#define   DBG_CNTR2_ATID_EN2__ATID84_EN___S                   20
#define   DBG_CNTR2_ATID_EN2__ATID83_EN___M      0x00080000
#define   DBG_CNTR2_ATID_EN2__ATID83_EN___S                   19
#define   DBG_CNTR2_ATID_EN2__ATID82_EN___M      0x00040000
#define   DBG_CNTR2_ATID_EN2__ATID82_EN___S                   18
#define   DBG_CNTR2_ATID_EN2__ATID81_EN___M      0x00020000
#define   DBG_CNTR2_ATID_EN2__ATID81_EN___S                   17
#define   DBG_CNTR2_ATID_EN2__ATID80_EN___M      0x00010000
#define   DBG_CNTR2_ATID_EN2__ATID80_EN___S                   16
#define   DBG_CNTR2_ATID_EN2__ATID79_EN___M      0x00008000
#define   DBG_CNTR2_ATID_EN2__ATID79_EN___S                   15
#define   DBG_CNTR2_ATID_EN2__ATID78_EN___M      0x00004000
#define   DBG_CNTR2_ATID_EN2__ATID78_EN___S                   14
#define   DBG_CNTR2_ATID_EN2__ATID77_EN___M      0x00002000
#define   DBG_CNTR2_ATID_EN2__ATID77_EN___S                   13
#define   DBG_CNTR2_ATID_EN2__ATID76_EN___M      0x00001000
#define   DBG_CNTR2_ATID_EN2__ATID76_EN___S                   12
#define   DBG_CNTR2_ATID_EN2__ATID75_EN___M      0x00000800
#define   DBG_CNTR2_ATID_EN2__ATID75_EN___S                   11
#define   DBG_CNTR2_ATID_EN2__ATID74_EN___M      0x00000400
#define   DBG_CNTR2_ATID_EN2__ATID74_EN___S                   10
#define   DBG_CNTR2_ATID_EN2__ATID73_EN___M      0x00000200
#define   DBG_CNTR2_ATID_EN2__ATID73_EN___S                    9
#define   DBG_CNTR2_ATID_EN2__ATID72_EN___M      0x00000100
#define   DBG_CNTR2_ATID_EN2__ATID72_EN___S                    8
#define   DBG_CNTR2_ATID_EN2__ATID71_EN___M      0x00000080
#define   DBG_CNTR2_ATID_EN2__ATID71_EN___S                    7
#define   DBG_CNTR2_ATID_EN2__ATID70_EN___M      0x00000040
#define   DBG_CNTR2_ATID_EN2__ATID70_EN___S                    6
#define   DBG_CNTR2_ATID_EN2__ATID69_EN___M      0x00000020
#define   DBG_CNTR2_ATID_EN2__ATID69_EN___S                    5
#define   DBG_CNTR2_ATID_EN2__ATID68_EN___M      0x00000010
#define   DBG_CNTR2_ATID_EN2__ATID68_EN___S                    4
#define   DBG_CNTR2_ATID_EN2__ATID67_EN___M      0x00000008
#define   DBG_CNTR2_ATID_EN2__ATID67_EN___S                    3
#define   DBG_CNTR2_ATID_EN2__ATID66_EN___M      0x00000004
#define   DBG_CNTR2_ATID_EN2__ATID66_EN___S                    2
#define   DBG_CNTR2_ATID_EN2__ATID65_EN___M      0x00000002
#define   DBG_CNTR2_ATID_EN2__ATID65_EN___S                    1
#define   DBG_CNTR2_ATID_EN2__ATID64_EN___M      0x00000001
#define   DBG_CNTR2_ATID_EN2__ATID64_EN___S                    0
#define DBG_CNTR3_ATID_EN2                        (0x00BC10CC)
#define   DBG_CNTR3_ATID_EN2___RWC                  QCSR_REG_RW    
#define   DBG_CNTR3_ATID_EN2__ATID95_EN___M      0x80000000
#define   DBG_CNTR3_ATID_EN2__ATID95_EN___S                   31
#define   DBG_CNTR3_ATID_EN2__ATID94_EN___M      0x40000000
#define   DBG_CNTR3_ATID_EN2__ATID94_EN___S                   30
#define   DBG_CNTR3_ATID_EN2__ATID93_EN___M      0x20000000
#define   DBG_CNTR3_ATID_EN2__ATID93_EN___S                   29
#define   DBG_CNTR3_ATID_EN2__ATID92_EN___M      0x10000000
#define   DBG_CNTR3_ATID_EN2__ATID92_EN___S                   28
#define   DBG_CNTR3_ATID_EN2__ATID91_EN___M      0x08000000
#define   DBG_CNTR3_ATID_EN2__ATID91_EN___S                   27
#define   DBG_CNTR3_ATID_EN2__ATID90_EN___M      0x04000000
#define   DBG_CNTR3_ATID_EN2__ATID90_EN___S                   26
#define   DBG_CNTR3_ATID_EN2__ATID89_EN___M      0x02000000
#define   DBG_CNTR3_ATID_EN2__ATID89_EN___S                   25
#define   DBG_CNTR3_ATID_EN2__ATID88_EN___M      0x01000000
#define   DBG_CNTR3_ATID_EN2__ATID88_EN___S                   24
#define   DBG_CNTR3_ATID_EN2__ATID87_EN___M      0x00800000
#define   DBG_CNTR3_ATID_EN2__ATID87_EN___S                   23
#define   DBG_CNTR3_ATID_EN2__ATID86_EN___M      0x00400000
#define   DBG_CNTR3_ATID_EN2__ATID86_EN___S                   22
#define   DBG_CNTR3_ATID_EN2__ATID85_EN___M      0x00200000
#define   DBG_CNTR3_ATID_EN2__ATID85_EN___S                   21
#define   DBG_CNTR3_ATID_EN2__ATID84_EN___M      0x00100000
#define   DBG_CNTR3_ATID_EN2__ATID84_EN___S                   20
#define   DBG_CNTR3_ATID_EN2__ATID83_EN___M      0x00080000
#define   DBG_CNTR3_ATID_EN2__ATID83_EN___S                   19
#define   DBG_CNTR3_ATID_EN2__ATID82_EN___M      0x00040000
#define   DBG_CNTR3_ATID_EN2__ATID82_EN___S                   18
#define   DBG_CNTR3_ATID_EN2__ATID81_EN___M      0x00020000
#define   DBG_CNTR3_ATID_EN2__ATID81_EN___S                   17
#define   DBG_CNTR3_ATID_EN2__ATID80_EN___M      0x00010000
#define   DBG_CNTR3_ATID_EN2__ATID80_EN___S                   16
#define   DBG_CNTR3_ATID_EN2__ATID79_EN___M      0x00008000
#define   DBG_CNTR3_ATID_EN2__ATID79_EN___S                   15
#define   DBG_CNTR3_ATID_EN2__ATID78_EN___M      0x00004000
#define   DBG_CNTR3_ATID_EN2__ATID78_EN___S                   14
#define   DBG_CNTR3_ATID_EN2__ATID77_EN___M      0x00002000
#define   DBG_CNTR3_ATID_EN2__ATID77_EN___S                   13
#define   DBG_CNTR3_ATID_EN2__ATID76_EN___M      0x00001000
#define   DBG_CNTR3_ATID_EN2__ATID76_EN___S                   12
#define   DBG_CNTR3_ATID_EN2__ATID75_EN___M      0x00000800
#define   DBG_CNTR3_ATID_EN2__ATID75_EN___S                   11
#define   DBG_CNTR3_ATID_EN2__ATID74_EN___M      0x00000400
#define   DBG_CNTR3_ATID_EN2__ATID74_EN___S                   10
#define   DBG_CNTR3_ATID_EN2__ATID73_EN___M      0x00000200
#define   DBG_CNTR3_ATID_EN2__ATID73_EN___S                    9
#define   DBG_CNTR3_ATID_EN2__ATID72_EN___M      0x00000100
#define   DBG_CNTR3_ATID_EN2__ATID72_EN___S                    8
#define   DBG_CNTR3_ATID_EN2__ATID71_EN___M      0x00000080
#define   DBG_CNTR3_ATID_EN2__ATID71_EN___S                    7
#define   DBG_CNTR3_ATID_EN2__ATID70_EN___M      0x00000040
#define   DBG_CNTR3_ATID_EN2__ATID70_EN___S                    6
#define   DBG_CNTR3_ATID_EN2__ATID69_EN___M      0x00000020
#define   DBG_CNTR3_ATID_EN2__ATID69_EN___S                    5
#define   DBG_CNTR3_ATID_EN2__ATID68_EN___M      0x00000010
#define   DBG_CNTR3_ATID_EN2__ATID68_EN___S                    4
#define   DBG_CNTR3_ATID_EN2__ATID67_EN___M      0x00000008
#define   DBG_CNTR3_ATID_EN2__ATID67_EN___S                    3
#define   DBG_CNTR3_ATID_EN2__ATID66_EN___M      0x00000004
#define   DBG_CNTR3_ATID_EN2__ATID66_EN___S                    2
#define   DBG_CNTR3_ATID_EN2__ATID65_EN___M      0x00000002
#define   DBG_CNTR3_ATID_EN2__ATID65_EN___S                    1
#define   DBG_CNTR3_ATID_EN2__ATID64_EN___M      0x00000001
#define   DBG_CNTR3_ATID_EN2__ATID64_EN___S                    0

#define DBG_CNTRn_ATID_EN3(n)            (0x00BC1010+0x40*(n))
#define   DBG_CNTRn_ATID_EN3_nMIN  0    
#define   DBG_CNTRn_ATID_EN3_nMAX  3    
#define   DBG_CNTRn_ATID_EN3_ELEM  4    
#define   DBG_CNTRn_ATID_EN3___RWC                  QCSR_REG_RW    
#define   DBG_CNTRn_ATID_EN3___POR               0xFFFFFFFF
#define   DBG_CNTRn_ATID_EN3__ATID127_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID126_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID125_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID124_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID123_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID122_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID121_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID120_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID119_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID118_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID117_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID116_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID115_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID114_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID113_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID112_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID111_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID110_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID109_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID108_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID107_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID106_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID105_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID104_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID103_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID102_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID101_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID100_EN___POR   0x1
#define   DBG_CNTRn_ATID_EN3__ATID99_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN3__ATID98_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN3__ATID97_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN3__ATID96_EN___POR    0x1
#define   DBG_CNTRn_ATID_EN3__ATID127_EN___M     0x80000000
#define   DBG_CNTRn_ATID_EN3__ATID127_EN___S                  31
#define   DBG_CNTRn_ATID_EN3__ATID127_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID127_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID126_EN___M     0x40000000
#define   DBG_CNTRn_ATID_EN3__ATID126_EN___S                  30
#define   DBG_CNTRn_ATID_EN3__ATID126_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID126_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID125_EN___M     0x20000000
#define   DBG_CNTRn_ATID_EN3__ATID125_EN___S                  29
#define   DBG_CNTRn_ATID_EN3__ATID125_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID125_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID124_EN___M     0x10000000
#define   DBG_CNTRn_ATID_EN3__ATID124_EN___S                  28
#define   DBG_CNTRn_ATID_EN3__ATID124_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID124_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID123_EN___M     0x08000000
#define   DBG_CNTRn_ATID_EN3__ATID123_EN___S                  27
#define   DBG_CNTRn_ATID_EN3__ATID123_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID123_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID122_EN___M     0x04000000
#define   DBG_CNTRn_ATID_EN3__ATID122_EN___S                  26
#define   DBG_CNTRn_ATID_EN3__ATID122_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID122_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID121_EN___M     0x02000000
#define   DBG_CNTRn_ATID_EN3__ATID121_EN___S                  25
#define   DBG_CNTRn_ATID_EN3__ATID121_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID121_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID120_EN___M     0x01000000
#define   DBG_CNTRn_ATID_EN3__ATID120_EN___S                  24
#define   DBG_CNTRn_ATID_EN3__ATID120_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID120_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID119_EN___M     0x00800000
#define   DBG_CNTRn_ATID_EN3__ATID119_EN___S                  23
#define   DBG_CNTRn_ATID_EN3__ATID119_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID119_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID118_EN___M     0x00400000
#define   DBG_CNTRn_ATID_EN3__ATID118_EN___S                  22
#define   DBG_CNTRn_ATID_EN3__ATID118_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID118_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID117_EN___M     0x00200000
#define   DBG_CNTRn_ATID_EN3__ATID117_EN___S                  21
#define   DBG_CNTRn_ATID_EN3__ATID117_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID117_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID116_EN___M     0x00100000
#define   DBG_CNTRn_ATID_EN3__ATID116_EN___S                  20
#define   DBG_CNTRn_ATID_EN3__ATID116_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID116_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID115_EN___M     0x00080000
#define   DBG_CNTRn_ATID_EN3__ATID115_EN___S                  19
#define   DBG_CNTRn_ATID_EN3__ATID115_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID115_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID114_EN___M     0x00040000
#define   DBG_CNTRn_ATID_EN3__ATID114_EN___S                  18
#define   DBG_CNTRn_ATID_EN3__ATID114_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID114_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID113_EN___M     0x00020000
#define   DBG_CNTRn_ATID_EN3__ATID113_EN___S                  17
#define   DBG_CNTRn_ATID_EN3__ATID113_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID113_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID112_EN___M     0x00010000
#define   DBG_CNTRn_ATID_EN3__ATID112_EN___S                  16
#define   DBG_CNTRn_ATID_EN3__ATID112_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID112_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID111_EN___M     0x00008000
#define   DBG_CNTRn_ATID_EN3__ATID111_EN___S                  15
#define   DBG_CNTRn_ATID_EN3__ATID111_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID111_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID110_EN___M     0x00004000
#define   DBG_CNTRn_ATID_EN3__ATID110_EN___S                  14
#define   DBG_CNTRn_ATID_EN3__ATID110_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID110_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID109_EN___M     0x00002000
#define   DBG_CNTRn_ATID_EN3__ATID109_EN___S                  13
#define   DBG_CNTRn_ATID_EN3__ATID109_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID109_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID108_EN___M     0x00001000
#define   DBG_CNTRn_ATID_EN3__ATID108_EN___S                  12
#define   DBG_CNTRn_ATID_EN3__ATID108_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID108_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID107_EN___M     0x00000800
#define   DBG_CNTRn_ATID_EN3__ATID107_EN___S                  11
#define   DBG_CNTRn_ATID_EN3__ATID107_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID107_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID106_EN___M     0x00000400
#define   DBG_CNTRn_ATID_EN3__ATID106_EN___S                  10
#define   DBG_CNTRn_ATID_EN3__ATID106_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID106_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID105_EN___M     0x00000200
#define   DBG_CNTRn_ATID_EN3__ATID105_EN___S                   9
#define   DBG_CNTRn_ATID_EN3__ATID105_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID105_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID104_EN___M     0x00000100
#define   DBG_CNTRn_ATID_EN3__ATID104_EN___S                   8
#define   DBG_CNTRn_ATID_EN3__ATID104_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID104_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID103_EN___M     0x00000080
#define   DBG_CNTRn_ATID_EN3__ATID103_EN___S                   7
#define   DBG_CNTRn_ATID_EN3__ATID103_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID103_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID102_EN___M     0x00000040
#define   DBG_CNTRn_ATID_EN3__ATID102_EN___S                   6
#define   DBG_CNTRn_ATID_EN3__ATID102_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID102_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID101_EN___M     0x00000020
#define   DBG_CNTRn_ATID_EN3__ATID101_EN___S                   5
#define   DBG_CNTRn_ATID_EN3__ATID101_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID101_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID100_EN___M     0x00000010
#define   DBG_CNTRn_ATID_EN3__ATID100_EN___S                   4
#define   DBG_CNTRn_ATID_EN3__ATID100_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID100_EN__ENABLE             0x1
#define   DBG_CNTRn_ATID_EN3__ATID99_EN___M      0x00000008
#define   DBG_CNTRn_ATID_EN3__ATID99_EN___S                    3
#define   DBG_CNTRn_ATID_EN3__ATID99_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID99_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN3__ATID98_EN___M      0x00000004
#define   DBG_CNTRn_ATID_EN3__ATID98_EN___S                    2
#define   DBG_CNTRn_ATID_EN3__ATID98_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID98_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN3__ATID97_EN___M      0x00000002
#define   DBG_CNTRn_ATID_EN3__ATID97_EN___S                    1
#define   DBG_CNTRn_ATID_EN3__ATID97_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID97_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN3__ATID96_EN___M      0x00000001
#define   DBG_CNTRn_ATID_EN3__ATID96_EN___S                    0
#define   DBG_CNTRn_ATID_EN3__ATID96_EN__DISABLE             0x0
#define   DBG_CNTRn_ATID_EN3__ATID96_EN__ENABLE              0x1
#define   DBG_CNTRn_ATID_EN3___M                 0xFFFFFFFF   
#define   DBG_CNTRn_ATID_EN3___S                               0
#define DBG_CNTR0_ATID_EN3                        (0x00BC1010)
#define   DBG_CNTR0_ATID_EN3___RWC                  QCSR_REG_RW    
#define   DBG_CNTR0_ATID_EN3__ATID127_EN___M     0x80000000
#define   DBG_CNTR0_ATID_EN3__ATID127_EN___S                  31
#define   DBG_CNTR0_ATID_EN3__ATID126_EN___M     0x40000000
#define   DBG_CNTR0_ATID_EN3__ATID126_EN___S                  30
#define   DBG_CNTR0_ATID_EN3__ATID125_EN___M     0x20000000
#define   DBG_CNTR0_ATID_EN3__ATID125_EN___S                  29
#define   DBG_CNTR0_ATID_EN3__ATID124_EN___M     0x10000000
#define   DBG_CNTR0_ATID_EN3__ATID124_EN___S                  28
#define   DBG_CNTR0_ATID_EN3__ATID123_EN___M     0x08000000
#define   DBG_CNTR0_ATID_EN3__ATID123_EN___S                  27
#define   DBG_CNTR0_ATID_EN3__ATID122_EN___M     0x04000000
#define   DBG_CNTR0_ATID_EN3__ATID122_EN___S                  26
#define   DBG_CNTR0_ATID_EN3__ATID121_EN___M     0x02000000
#define   DBG_CNTR0_ATID_EN3__ATID121_EN___S                  25
#define   DBG_CNTR0_ATID_EN3__ATID120_EN___M     0x01000000
#define   DBG_CNTR0_ATID_EN3__ATID120_EN___S                  24
#define   DBG_CNTR0_ATID_EN3__ATID119_EN___M     0x00800000
#define   DBG_CNTR0_ATID_EN3__ATID119_EN___S                  23
#define   DBG_CNTR0_ATID_EN3__ATID118_EN___M     0x00400000
#define   DBG_CNTR0_ATID_EN3__ATID118_EN___S                  22
#define   DBG_CNTR0_ATID_EN3__ATID117_EN___M     0x00200000
#define   DBG_CNTR0_ATID_EN3__ATID117_EN___S                  21
#define   DBG_CNTR0_ATID_EN3__ATID116_EN___M     0x00100000
#define   DBG_CNTR0_ATID_EN3__ATID116_EN___S                  20
#define   DBG_CNTR0_ATID_EN3__ATID115_EN___M     0x00080000
#define   DBG_CNTR0_ATID_EN3__ATID115_EN___S                  19
#define   DBG_CNTR0_ATID_EN3__ATID114_EN___M     0x00040000
#define   DBG_CNTR0_ATID_EN3__ATID114_EN___S                  18
#define   DBG_CNTR0_ATID_EN3__ATID113_EN___M     0x00020000
#define   DBG_CNTR0_ATID_EN3__ATID113_EN___S                  17
#define   DBG_CNTR0_ATID_EN3__ATID112_EN___M     0x00010000
#define   DBG_CNTR0_ATID_EN3__ATID112_EN___S                  16
#define   DBG_CNTR0_ATID_EN3__ATID111_EN___M     0x00008000
#define   DBG_CNTR0_ATID_EN3__ATID111_EN___S                  15
#define   DBG_CNTR0_ATID_EN3__ATID110_EN___M     0x00004000
#define   DBG_CNTR0_ATID_EN3__ATID110_EN___S                  14
#define   DBG_CNTR0_ATID_EN3__ATID109_EN___M     0x00002000
#define   DBG_CNTR0_ATID_EN3__ATID109_EN___S                  13
#define   DBG_CNTR0_ATID_EN3__ATID108_EN___M     0x00001000
#define   DBG_CNTR0_ATID_EN3__ATID108_EN___S                  12
#define   DBG_CNTR0_ATID_EN3__ATID107_EN___M     0x00000800
#define   DBG_CNTR0_ATID_EN3__ATID107_EN___S                  11
#define   DBG_CNTR0_ATID_EN3__ATID106_EN___M     0x00000400
#define   DBG_CNTR0_ATID_EN3__ATID106_EN___S                  10
#define   DBG_CNTR0_ATID_EN3__ATID105_EN___M     0x00000200
#define   DBG_CNTR0_ATID_EN3__ATID105_EN___S                   9
#define   DBG_CNTR0_ATID_EN3__ATID104_EN___M     0x00000100
#define   DBG_CNTR0_ATID_EN3__ATID104_EN___S                   8
#define   DBG_CNTR0_ATID_EN3__ATID103_EN___M     0x00000080
#define   DBG_CNTR0_ATID_EN3__ATID103_EN___S                   7
#define   DBG_CNTR0_ATID_EN3__ATID102_EN___M     0x00000040
#define   DBG_CNTR0_ATID_EN3__ATID102_EN___S                   6
#define   DBG_CNTR0_ATID_EN3__ATID101_EN___M     0x00000020
#define   DBG_CNTR0_ATID_EN3__ATID101_EN___S                   5
#define   DBG_CNTR0_ATID_EN3__ATID100_EN___M     0x00000010
#define   DBG_CNTR0_ATID_EN3__ATID100_EN___S                   4
#define   DBG_CNTR0_ATID_EN3__ATID99_EN___M      0x00000008
#define   DBG_CNTR0_ATID_EN3__ATID99_EN___S                    3
#define   DBG_CNTR0_ATID_EN3__ATID98_EN___M      0x00000004
#define   DBG_CNTR0_ATID_EN3__ATID98_EN___S                    2
#define   DBG_CNTR0_ATID_EN3__ATID97_EN___M      0x00000002
#define   DBG_CNTR0_ATID_EN3__ATID97_EN___S                    1
#define   DBG_CNTR0_ATID_EN3__ATID96_EN___M      0x00000001
#define   DBG_CNTR0_ATID_EN3__ATID96_EN___S                    0
#define DBG_CNTR1_ATID_EN3                        (0x00BC1050)
#define   DBG_CNTR1_ATID_EN3___RWC                  QCSR_REG_RW    
#define   DBG_CNTR1_ATID_EN3__ATID127_EN___M     0x80000000
#define   DBG_CNTR1_ATID_EN3__ATID127_EN___S                  31
#define   DBG_CNTR1_ATID_EN3__ATID126_EN___M     0x40000000
#define   DBG_CNTR1_ATID_EN3__ATID126_EN___S                  30
#define   DBG_CNTR1_ATID_EN3__ATID125_EN___M     0x20000000
#define   DBG_CNTR1_ATID_EN3__ATID125_EN___S                  29
#define   DBG_CNTR1_ATID_EN3__ATID124_EN___M     0x10000000
#define   DBG_CNTR1_ATID_EN3__ATID124_EN___S                  28
#define   DBG_CNTR1_ATID_EN3__ATID123_EN___M     0x08000000
#define   DBG_CNTR1_ATID_EN3__ATID123_EN___S                  27
#define   DBG_CNTR1_ATID_EN3__ATID122_EN___M     0x04000000
#define   DBG_CNTR1_ATID_EN3__ATID122_EN___S                  26
#define   DBG_CNTR1_ATID_EN3__ATID121_EN___M     0x02000000
#define   DBG_CNTR1_ATID_EN3__ATID121_EN___S                  25
#define   DBG_CNTR1_ATID_EN3__ATID120_EN___M     0x01000000
#define   DBG_CNTR1_ATID_EN3__ATID120_EN___S                  24
#define   DBG_CNTR1_ATID_EN3__ATID119_EN___M     0x00800000
#define   DBG_CNTR1_ATID_EN3__ATID119_EN___S                  23
#define   DBG_CNTR1_ATID_EN3__ATID118_EN___M     0x00400000
#define   DBG_CNTR1_ATID_EN3__ATID118_EN___S                  22
#define   DBG_CNTR1_ATID_EN3__ATID117_EN___M     0x00200000
#define   DBG_CNTR1_ATID_EN3__ATID117_EN___S                  21
#define   DBG_CNTR1_ATID_EN3__ATID116_EN___M     0x00100000
#define   DBG_CNTR1_ATID_EN3__ATID116_EN___S                  20
#define   DBG_CNTR1_ATID_EN3__ATID115_EN___M     0x00080000
#define   DBG_CNTR1_ATID_EN3__ATID115_EN___S                  19
#define   DBG_CNTR1_ATID_EN3__ATID114_EN___M     0x00040000
#define   DBG_CNTR1_ATID_EN3__ATID114_EN___S                  18
#define   DBG_CNTR1_ATID_EN3__ATID113_EN___M     0x00020000
#define   DBG_CNTR1_ATID_EN3__ATID113_EN___S                  17
#define   DBG_CNTR1_ATID_EN3__ATID112_EN___M     0x00010000
#define   DBG_CNTR1_ATID_EN3__ATID112_EN___S                  16
#define   DBG_CNTR1_ATID_EN3__ATID111_EN___M     0x00008000
#define   DBG_CNTR1_ATID_EN3__ATID111_EN___S                  15
#define   DBG_CNTR1_ATID_EN3__ATID110_EN___M     0x00004000
#define   DBG_CNTR1_ATID_EN3__ATID110_EN___S                  14
#define   DBG_CNTR1_ATID_EN3__ATID109_EN___M     0x00002000
#define   DBG_CNTR1_ATID_EN3__ATID109_EN___S                  13
#define   DBG_CNTR1_ATID_EN3__ATID108_EN___M     0x00001000
#define   DBG_CNTR1_ATID_EN3__ATID108_EN___S                  12
#define   DBG_CNTR1_ATID_EN3__ATID107_EN___M     0x00000800
#define   DBG_CNTR1_ATID_EN3__ATID107_EN___S                  11
#define   DBG_CNTR1_ATID_EN3__ATID106_EN___M     0x00000400
#define   DBG_CNTR1_ATID_EN3__ATID106_EN___S                  10
#define   DBG_CNTR1_ATID_EN3__ATID105_EN___M     0x00000200
#define   DBG_CNTR1_ATID_EN3__ATID105_EN___S                   9
#define   DBG_CNTR1_ATID_EN3__ATID104_EN___M     0x00000100
#define   DBG_CNTR1_ATID_EN3__ATID104_EN___S                   8
#define   DBG_CNTR1_ATID_EN3__ATID103_EN___M     0x00000080
#define   DBG_CNTR1_ATID_EN3__ATID103_EN___S                   7
#define   DBG_CNTR1_ATID_EN3__ATID102_EN___M     0x00000040
#define   DBG_CNTR1_ATID_EN3__ATID102_EN___S                   6
#define   DBG_CNTR1_ATID_EN3__ATID101_EN___M     0x00000020
#define   DBG_CNTR1_ATID_EN3__ATID101_EN___S                   5
#define   DBG_CNTR1_ATID_EN3__ATID100_EN___M     0x00000010
#define   DBG_CNTR1_ATID_EN3__ATID100_EN___S                   4
#define   DBG_CNTR1_ATID_EN3__ATID99_EN___M      0x00000008
#define   DBG_CNTR1_ATID_EN3__ATID99_EN___S                    3
#define   DBG_CNTR1_ATID_EN3__ATID98_EN___M      0x00000004
#define   DBG_CNTR1_ATID_EN3__ATID98_EN___S                    2
#define   DBG_CNTR1_ATID_EN3__ATID97_EN___M      0x00000002
#define   DBG_CNTR1_ATID_EN3__ATID97_EN___S                    1
#define   DBG_CNTR1_ATID_EN3__ATID96_EN___M      0x00000001
#define   DBG_CNTR1_ATID_EN3__ATID96_EN___S                    0
#define DBG_CNTR2_ATID_EN3                        (0x00BC1090)
#define   DBG_CNTR2_ATID_EN3___RWC                  QCSR_REG_RW    
#define   DBG_CNTR2_ATID_EN3__ATID127_EN___M     0x80000000
#define   DBG_CNTR2_ATID_EN3__ATID127_EN___S                  31
#define   DBG_CNTR2_ATID_EN3__ATID126_EN___M     0x40000000
#define   DBG_CNTR2_ATID_EN3__ATID126_EN___S                  30
#define   DBG_CNTR2_ATID_EN3__ATID125_EN___M     0x20000000
#define   DBG_CNTR2_ATID_EN3__ATID125_EN___S                  29
#define   DBG_CNTR2_ATID_EN3__ATID124_EN___M     0x10000000
#define   DBG_CNTR2_ATID_EN3__ATID124_EN___S                  28
#define   DBG_CNTR2_ATID_EN3__ATID123_EN___M     0x08000000
#define   DBG_CNTR2_ATID_EN3__ATID123_EN___S                  27
#define   DBG_CNTR2_ATID_EN3__ATID122_EN___M     0x04000000
#define   DBG_CNTR2_ATID_EN3__ATID122_EN___S                  26
#define   DBG_CNTR2_ATID_EN3__ATID121_EN___M     0x02000000
#define   DBG_CNTR2_ATID_EN3__ATID121_EN___S                  25
#define   DBG_CNTR2_ATID_EN3__ATID120_EN___M     0x01000000
#define   DBG_CNTR2_ATID_EN3__ATID120_EN___S                  24
#define   DBG_CNTR2_ATID_EN3__ATID119_EN___M     0x00800000
#define   DBG_CNTR2_ATID_EN3__ATID119_EN___S                  23
#define   DBG_CNTR2_ATID_EN3__ATID118_EN___M     0x00400000
#define   DBG_CNTR2_ATID_EN3__ATID118_EN___S                  22
#define   DBG_CNTR2_ATID_EN3__ATID117_EN___M     0x00200000
#define   DBG_CNTR2_ATID_EN3__ATID117_EN___S                  21
#define   DBG_CNTR2_ATID_EN3__ATID116_EN___M     0x00100000
#define   DBG_CNTR2_ATID_EN3__ATID116_EN___S                  20
#define   DBG_CNTR2_ATID_EN3__ATID115_EN___M     0x00080000
#define   DBG_CNTR2_ATID_EN3__ATID115_EN___S                  19
#define   DBG_CNTR2_ATID_EN3__ATID114_EN___M     0x00040000
#define   DBG_CNTR2_ATID_EN3__ATID114_EN___S                  18
#define   DBG_CNTR2_ATID_EN3__ATID113_EN___M     0x00020000
#define   DBG_CNTR2_ATID_EN3__ATID113_EN___S                  17
#define   DBG_CNTR2_ATID_EN3__ATID112_EN___M     0x00010000
#define   DBG_CNTR2_ATID_EN3__ATID112_EN___S                  16
#define   DBG_CNTR2_ATID_EN3__ATID111_EN___M     0x00008000
#define   DBG_CNTR2_ATID_EN3__ATID111_EN___S                  15
#define   DBG_CNTR2_ATID_EN3__ATID110_EN___M     0x00004000
#define   DBG_CNTR2_ATID_EN3__ATID110_EN___S                  14
#define   DBG_CNTR2_ATID_EN3__ATID109_EN___M     0x00002000
#define   DBG_CNTR2_ATID_EN3__ATID109_EN___S                  13
#define   DBG_CNTR2_ATID_EN3__ATID108_EN___M     0x00001000
#define   DBG_CNTR2_ATID_EN3__ATID108_EN___S                  12
#define   DBG_CNTR2_ATID_EN3__ATID107_EN___M     0x00000800
#define   DBG_CNTR2_ATID_EN3__ATID107_EN___S                  11
#define   DBG_CNTR2_ATID_EN3__ATID106_EN___M     0x00000400
#define   DBG_CNTR2_ATID_EN3__ATID106_EN___S                  10
#define   DBG_CNTR2_ATID_EN3__ATID105_EN___M     0x00000200
#define   DBG_CNTR2_ATID_EN3__ATID105_EN___S                   9
#define   DBG_CNTR2_ATID_EN3__ATID104_EN___M     0x00000100
#define   DBG_CNTR2_ATID_EN3__ATID104_EN___S                   8
#define   DBG_CNTR2_ATID_EN3__ATID103_EN___M     0x00000080
#define   DBG_CNTR2_ATID_EN3__ATID103_EN___S                   7
#define   DBG_CNTR2_ATID_EN3__ATID102_EN___M     0x00000040
#define   DBG_CNTR2_ATID_EN3__ATID102_EN___S                   6
#define   DBG_CNTR2_ATID_EN3__ATID101_EN___M     0x00000020
#define   DBG_CNTR2_ATID_EN3__ATID101_EN___S                   5
#define   DBG_CNTR2_ATID_EN3__ATID100_EN___M     0x00000010
#define   DBG_CNTR2_ATID_EN3__ATID100_EN___S                   4
#define   DBG_CNTR2_ATID_EN3__ATID99_EN___M      0x00000008
#define   DBG_CNTR2_ATID_EN3__ATID99_EN___S                    3
#define   DBG_CNTR2_ATID_EN3__ATID98_EN___M      0x00000004
#define   DBG_CNTR2_ATID_EN3__ATID98_EN___S                    2
#define   DBG_CNTR2_ATID_EN3__ATID97_EN___M      0x00000002
#define   DBG_CNTR2_ATID_EN3__ATID97_EN___S                    1
#define   DBG_CNTR2_ATID_EN3__ATID96_EN___M      0x00000001
#define   DBG_CNTR2_ATID_EN3__ATID96_EN___S                    0
#define DBG_CNTR3_ATID_EN3                        (0x00BC10D0)
#define   DBG_CNTR3_ATID_EN3___RWC                  QCSR_REG_RW    
#define   DBG_CNTR3_ATID_EN3__ATID127_EN___M     0x80000000
#define   DBG_CNTR3_ATID_EN3__ATID127_EN___S                  31
#define   DBG_CNTR3_ATID_EN3__ATID126_EN___M     0x40000000
#define   DBG_CNTR3_ATID_EN3__ATID126_EN___S                  30
#define   DBG_CNTR3_ATID_EN3__ATID125_EN___M     0x20000000
#define   DBG_CNTR3_ATID_EN3__ATID125_EN___S                  29
#define   DBG_CNTR3_ATID_EN3__ATID124_EN___M     0x10000000
#define   DBG_CNTR3_ATID_EN3__ATID124_EN___S                  28
#define   DBG_CNTR3_ATID_EN3__ATID123_EN___M     0x08000000
#define   DBG_CNTR3_ATID_EN3__ATID123_EN___S                  27
#define   DBG_CNTR3_ATID_EN3__ATID122_EN___M     0x04000000
#define   DBG_CNTR3_ATID_EN3__ATID122_EN___S                  26
#define   DBG_CNTR3_ATID_EN3__ATID121_EN___M     0x02000000
#define   DBG_CNTR3_ATID_EN3__ATID121_EN___S                  25
#define   DBG_CNTR3_ATID_EN3__ATID120_EN___M     0x01000000
#define   DBG_CNTR3_ATID_EN3__ATID120_EN___S                  24
#define   DBG_CNTR3_ATID_EN3__ATID119_EN___M     0x00800000
#define   DBG_CNTR3_ATID_EN3__ATID119_EN___S                  23
#define   DBG_CNTR3_ATID_EN3__ATID118_EN___M     0x00400000
#define   DBG_CNTR3_ATID_EN3__ATID118_EN___S                  22
#define   DBG_CNTR3_ATID_EN3__ATID117_EN___M     0x00200000
#define   DBG_CNTR3_ATID_EN3__ATID117_EN___S                  21
#define   DBG_CNTR3_ATID_EN3__ATID116_EN___M     0x00100000
#define   DBG_CNTR3_ATID_EN3__ATID116_EN___S                  20
#define   DBG_CNTR3_ATID_EN3__ATID115_EN___M     0x00080000
#define   DBG_CNTR3_ATID_EN3__ATID115_EN___S                  19
#define   DBG_CNTR3_ATID_EN3__ATID114_EN___M     0x00040000
#define   DBG_CNTR3_ATID_EN3__ATID114_EN___S                  18
#define   DBG_CNTR3_ATID_EN3__ATID113_EN___M     0x00020000
#define   DBG_CNTR3_ATID_EN3__ATID113_EN___S                  17
#define   DBG_CNTR3_ATID_EN3__ATID112_EN___M     0x00010000
#define   DBG_CNTR3_ATID_EN3__ATID112_EN___S                  16
#define   DBG_CNTR3_ATID_EN3__ATID111_EN___M     0x00008000
#define   DBG_CNTR3_ATID_EN3__ATID111_EN___S                  15
#define   DBG_CNTR3_ATID_EN3__ATID110_EN___M     0x00004000
#define   DBG_CNTR3_ATID_EN3__ATID110_EN___S                  14
#define   DBG_CNTR3_ATID_EN3__ATID109_EN___M     0x00002000
#define   DBG_CNTR3_ATID_EN3__ATID109_EN___S                  13
#define   DBG_CNTR3_ATID_EN3__ATID108_EN___M     0x00001000
#define   DBG_CNTR3_ATID_EN3__ATID108_EN___S                  12
#define   DBG_CNTR3_ATID_EN3__ATID107_EN___M     0x00000800
#define   DBG_CNTR3_ATID_EN3__ATID107_EN___S                  11
#define   DBG_CNTR3_ATID_EN3__ATID106_EN___M     0x00000400
#define   DBG_CNTR3_ATID_EN3__ATID106_EN___S                  10
#define   DBG_CNTR3_ATID_EN3__ATID105_EN___M     0x00000200
#define   DBG_CNTR3_ATID_EN3__ATID105_EN___S                   9
#define   DBG_CNTR3_ATID_EN3__ATID104_EN___M     0x00000100
#define   DBG_CNTR3_ATID_EN3__ATID104_EN___S                   8
#define   DBG_CNTR3_ATID_EN3__ATID103_EN___M     0x00000080
#define   DBG_CNTR3_ATID_EN3__ATID103_EN___S                   7
#define   DBG_CNTR3_ATID_EN3__ATID102_EN___M     0x00000040
#define   DBG_CNTR3_ATID_EN3__ATID102_EN___S                   6
#define   DBG_CNTR3_ATID_EN3__ATID101_EN___M     0x00000020
#define   DBG_CNTR3_ATID_EN3__ATID101_EN___S                   5
#define   DBG_CNTR3_ATID_EN3__ATID100_EN___M     0x00000010
#define   DBG_CNTR3_ATID_EN3__ATID100_EN___S                   4
#define   DBG_CNTR3_ATID_EN3__ATID99_EN___M      0x00000008
#define   DBG_CNTR3_ATID_EN3__ATID99_EN___S                    3
#define   DBG_CNTR3_ATID_EN3__ATID98_EN___M      0x00000004
#define   DBG_CNTR3_ATID_EN3__ATID98_EN___S                    2
#define   DBG_CNTR3_ATID_EN3__ATID97_EN___M      0x00000002
#define   DBG_CNTR3_ATID_EN3__ATID97_EN___S                    1
#define   DBG_CNTR3_ATID_EN3__ATID96_EN___M      0x00000001
#define   DBG_CNTR3_ATID_EN3__ATID96_EN___S                    0

#define DBG_CNTRn_MATCH_CNT(n)           (0x00BC1014+0x40*(n))
#define   DBG_CNTRn_MATCH_CNT_nMIN 0    
#define   DBG_CNTRn_MATCH_CNT_nMAX 3    
#define   DBG_CNTRn_MATCH_CNT_ELEM 4    
#define   DBG_CNTRn_MATCH_CNT___RWC                 QCSR_REG_RW    
#define   DBG_CNTRn_MATCH_CNT___POR              0x00000000
#define   DBG_CNTRn_MATCH_CNT__VALUE___POR       0x00000000
#define   DBG_CNTRn_MATCH_CNT__VALUE___M         0xFFFFFFFF
#define   DBG_CNTRn_MATCH_CNT__VALUE___S                       0
#define   DBG_CNTRn_MATCH_CNT___M                0xFFFFFFFF   
#define   DBG_CNTRn_MATCH_CNT___S                              0
#define DBG_CNTR0_MATCH_CNT                       (0x00BC1014)
#define   DBG_CNTR0_MATCH_CNT___RWC                 QCSR_REG_RW    
#define   DBG_CNTR0_MATCH_CNT__VALUE___M         0xFFFFFFFF
#define   DBG_CNTR0_MATCH_CNT__VALUE___S                       0
#define DBG_CNTR1_MATCH_CNT                       (0x00BC1054)
#define   DBG_CNTR1_MATCH_CNT___RWC                 QCSR_REG_RW    
#define   DBG_CNTR1_MATCH_CNT__VALUE___M         0xFFFFFFFF
#define   DBG_CNTR1_MATCH_CNT__VALUE___S                       0
#define DBG_CNTR2_MATCH_CNT                       (0x00BC1094)
#define   DBG_CNTR2_MATCH_CNT___RWC                 QCSR_REG_RW    
#define   DBG_CNTR2_MATCH_CNT__VALUE___M         0xFFFFFFFF
#define   DBG_CNTR2_MATCH_CNT__VALUE___S                       0
#define DBG_CNTR3_MATCH_CNT                       (0x00BC10D4)
#define   DBG_CNTR3_MATCH_CNT___RWC                 QCSR_REG_RW    
#define   DBG_CNTR3_MATCH_CNT__VALUE___M         0xFFFFFFFF
#define   DBG_CNTR3_MATCH_CNT__VALUE___S                       0

#define DBG_CNTRn_CNT(n)                 (0x00BC101C+0x40*(n))
#define   DBG_CNTRn_CNT_nMIN       0    
#define   DBG_CNTRn_CNT_nMAX       3    
#define   DBG_CNTRn_CNT_ELEM       4    
#define   DBG_CNTRn_CNT___RWC                       QCSR_REG_RW    
#define   DBG_CNTRn_CNT___POR                    0x00000000
#define   DBG_CNTRn_CNT__VALUE___POR             0x00000000
#define   DBG_CNTRn_CNT__VALUE___M               0xFFFFFFFF
#define   DBG_CNTRn_CNT__VALUE___S                             0
#define   DBG_CNTRn_CNT___M                      0xFFFFFFFF   
#define   DBG_CNTRn_CNT___S                                    0
#define DBG_CNTR0_CNT                             (0x00BC101C)
#define   DBG_CNTR0_CNT___RWC                       QCSR_REG_RW    
#define   DBG_CNTR0_CNT__VALUE___M               0xFFFFFFFF
#define   DBG_CNTR0_CNT__VALUE___S                             0
#define DBG_CNTR1_CNT                             (0x00BC105C)
#define   DBG_CNTR1_CNT___RWC                       QCSR_REG_RW    
#define   DBG_CNTR1_CNT__VALUE___M               0xFFFFFFFF
#define   DBG_CNTR1_CNT__VALUE___S                             0
#define DBG_CNTR2_CNT                             (0x00BC109C)
#define   DBG_CNTR2_CNT___RWC                       QCSR_REG_RW    
#define   DBG_CNTR2_CNT__VALUE___M               0xFFFFFFFF
#define   DBG_CNTR2_CNT__VALUE___S                             0
#define DBG_CNTR3_CNT                             (0x00BC10DC)
#define   DBG_CNTR3_CNT___RWC                       QCSR_REG_RW    
#define   DBG_CNTR3_CNT__VALUE___M               0xFFFFFFFF
#define   DBG_CNTR3_CNT__VALUE___S                             0

#define DBG_CNTRn_START_TSTMP_L(n)       (0x00BC1024+0x40*(n))
#define   DBG_CNTRn_START_TSTMP_L_nMIN 0    
#define   DBG_CNTRn_START_TSTMP_L_nMAX 3    
#define   DBG_CNTRn_START_TSTMP_L_ELEM 4    
#define   DBG_CNTRn_START_TSTMP_L___RWC             QCSR_REG_RO    
#define   DBG_CNTRn_START_TSTMP_L___POR          0x00000000
#define   DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___POR 0x00000000
#define   DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___S               0
#define   DBG_CNTRn_START_TSTMP_L___M            0xFFFFFFFF   
#define   DBG_CNTRn_START_TSTMP_L___S                          0
#define DBG_CNTR0_START_TSTMP_L                   (0x00BC1024)
#define   DBG_CNTR0_START_TSTMP_L___RWC             QCSR_REG_RO    
#define   DBG_CNTR0_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR0_START_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR1_START_TSTMP_L                   (0x00BC1064)
#define   DBG_CNTR1_START_TSTMP_L___RWC             QCSR_REG_RO    
#define   DBG_CNTR1_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR1_START_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR2_START_TSTMP_L                   (0x00BC10A4)
#define   DBG_CNTR2_START_TSTMP_L___RWC             QCSR_REG_RO    
#define   DBG_CNTR2_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR2_START_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR3_START_TSTMP_L                   (0x00BC10E4)
#define   DBG_CNTR3_START_TSTMP_L___RWC             QCSR_REG_RO    
#define   DBG_CNTR3_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR3_START_TSTMP_L__TSTMP_31_0___S               0

#define DBG_CNTRn_START_TSTMP_H(n)       (0x00BC1028+0x40*(n))
#define   DBG_CNTRn_START_TSTMP_H_nMIN 0    
#define   DBG_CNTRn_START_TSTMP_H_nMAX 3    
#define   DBG_CNTRn_START_TSTMP_H_ELEM 4    
#define   DBG_CNTRn_START_TSTMP_H___RWC             QCSR_REG_RO    
#define   DBG_CNTRn_START_TSTMP_H___POR          0x00000000
#define   DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___POR 0x00000000
#define   DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___S               0
#define   DBG_CNTRn_START_TSTMP_H___M            0xFFFFFFFF   
#define   DBG_CNTRn_START_TSTMP_H___S                          0
#define DBG_CNTR0_START_TSTMP_H                   (0x00BC1028)
#define   DBG_CNTR0_START_TSTMP_H___RWC             QCSR_REG_RO    
#define   DBG_CNTR0_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR0_START_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR1_START_TSTMP_H                   (0x00BC1068)
#define   DBG_CNTR1_START_TSTMP_H___RWC             QCSR_REG_RO    
#define   DBG_CNTR1_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR1_START_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR2_START_TSTMP_H                   (0x00BC10A8)
#define   DBG_CNTR2_START_TSTMP_H___RWC             QCSR_REG_RO    
#define   DBG_CNTR2_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR2_START_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR3_START_TSTMP_H                   (0x00BC10E8)
#define   DBG_CNTR3_START_TSTMP_H___RWC             QCSR_REG_RO    
#define   DBG_CNTR3_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR3_START_TSTMP_H__TSTMP_63_32___S               0

#define DBG_CNTRn_STOP_TSTMP_L(n)        (0x00BC102C+0x40*(n))
#define   DBG_CNTRn_STOP_TSTMP_L_nMIN 0    
#define   DBG_CNTRn_STOP_TSTMP_L_nMAX 3    
#define   DBG_CNTRn_STOP_TSTMP_L_ELEM 4    
#define   DBG_CNTRn_STOP_TSTMP_L___RWC              QCSR_REG_RO    
#define   DBG_CNTRn_STOP_TSTMP_L___POR           0x00000000
#define   DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___POR 0x00000000
#define   DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___S               0
#define   DBG_CNTRn_STOP_TSTMP_L___M             0xFFFFFFFF   
#define   DBG_CNTRn_STOP_TSTMP_L___S                           0
#define DBG_CNTR0_STOP_TSTMP_L                    (0x00BC102C)
#define   DBG_CNTR0_STOP_TSTMP_L___RWC              QCSR_REG_RO    
#define   DBG_CNTR0_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR0_STOP_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR1_STOP_TSTMP_L                    (0x00BC106C)
#define   DBG_CNTR1_STOP_TSTMP_L___RWC              QCSR_REG_RO    
#define   DBG_CNTR1_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR1_STOP_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR2_STOP_TSTMP_L                    (0x00BC10AC)
#define   DBG_CNTR2_STOP_TSTMP_L___RWC              QCSR_REG_RO    
#define   DBG_CNTR2_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR2_STOP_TSTMP_L__TSTMP_31_0___S               0
#define DBG_CNTR3_STOP_TSTMP_L                    (0x00BC10EC)
#define   DBG_CNTR3_STOP_TSTMP_L___RWC              QCSR_REG_RO    
#define   DBG_CNTR3_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF
#define   DBG_CNTR3_STOP_TSTMP_L__TSTMP_31_0___S               0

#define DBG_CNTRn_STOP_TSTMP_H(n)        (0x00BC1030+0x40*(n))
#define   DBG_CNTRn_STOP_TSTMP_H_nMIN 0    
#define   DBG_CNTRn_STOP_TSTMP_H_nMAX 3    
#define   DBG_CNTRn_STOP_TSTMP_H_ELEM 4    
#define   DBG_CNTRn_STOP_TSTMP_H___RWC              QCSR_REG_RO    
#define   DBG_CNTRn_STOP_TSTMP_H___POR           0x00000000
#define   DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___POR 0x00000000
#define   DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___S               0
#define   DBG_CNTRn_STOP_TSTMP_H___M             0xFFFFFFFF   
#define   DBG_CNTRn_STOP_TSTMP_H___S                           0
#define DBG_CNTR0_STOP_TSTMP_H                    (0x00BC1030)
#define   DBG_CNTR0_STOP_TSTMP_H___RWC              QCSR_REG_RO    
#define   DBG_CNTR0_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR0_STOP_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR1_STOP_TSTMP_H                    (0x00BC1070)
#define   DBG_CNTR1_STOP_TSTMP_H___RWC              QCSR_REG_RO    
#define   DBG_CNTR1_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR1_STOP_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR2_STOP_TSTMP_H                    (0x00BC10B0)
#define   DBG_CNTR2_STOP_TSTMP_H___RWC              QCSR_REG_RO    
#define   DBG_CNTR2_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR2_STOP_TSTMP_H__TSTMP_63_32___S               0
#define DBG_CNTR3_STOP_TSTMP_H                    (0x00BC10F0)
#define   DBG_CNTR3_STOP_TSTMP_H___RWC              QCSR_REG_RO    
#define   DBG_CNTR3_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF
#define   DBG_CNTR3_STOP_TSTMP_H__TSTMP_63_32___S               0

#define DBG_TLV_TPDM_CMB_CR                       (0x00BC2A00)
#define   DBG_TLV_TPDM_CMB_CR___RWC                 QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_CR___POR              0x00000000
#define   DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___POR  0x0
#define   DBG_TLV_TPDM_CMB_CR__EBITSET___POR     0x0
#define   DBG_TLV_TPDM_CMB_CR__FLOWCTRL___POR    0x0
#define   DBG_TLV_TPDM_CMB_CR__MODE___POR        0x0
#define   DBG_TLV_TPDM_CMB_CR__E___POR           0x0
#define   DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___M    0x00000080
#define   DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___S                  7
#define   DBG_TLV_TPDM_CMB_CR__EBITSET___M       0x00000040
#define   DBG_TLV_TPDM_CMB_CR__EBITSET___S                     6
#define   DBG_TLV_TPDM_CMB_CR__FLOWCTRL___M      0x00000004
#define   DBG_TLV_TPDM_CMB_CR__FLOWCTRL___S                    2
#define   DBG_TLV_TPDM_CMB_CR__MODE___M          0x00000002
#define   DBG_TLV_TPDM_CMB_CR__MODE___S                        1
#define   DBG_TLV_TPDM_CMB_CR__E___M             0x00000001
#define   DBG_TLV_TPDM_CMB_CR__E___S                           0
#define   DBG_TLV_TPDM_CMB_CR___M                0x000000C7   
#define   DBG_TLV_TPDM_CMB_CR___S                              0

#define DBG_TLV_TPDM_CMB_TIER                     (0x00BC2A04)
#define   DBG_TLV_TPDM_CMB_TIER___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TIER___POR            0x00000000
#define   DBG_TLV_TPDM_CMB_TIER__TS_ALL___POR    0x0
#define   DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___POR 0x0
#define   DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___POR 0x0
#define   DBG_TLV_TPDM_CMB_TIER__TS_ALL___M      0x00000004
#define   DBG_TLV_TPDM_CMB_TIER__TS_ALL___S                    2
#define   DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___M 0x00000002
#define   DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___S               1
#define   DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___M 0x00000001
#define   DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___S               0
#define   DBG_TLV_TPDM_CMB_TIER___M              0x00000007   
#define   DBG_TLV_TPDM_CMB_TIER___S                            0

#define DBG_TLV_TPDM_CMB_TPRn(n)         (0x00BC2A08+0x4*(n))
#define   DBG_TLV_TPDM_CMB_TPRn_nMIN 0    
#define   DBG_TLV_TPDM_CMB_TPRn_nMAX 0    
#define   DBG_TLV_TPDM_CMB_TPRn_ELEM 1    
#define   DBG_TLV_TPDM_CMB_TPRn___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPRn___POR            0x00000000
#define   DBG_TLV_TPDM_CMB_TPRn__VAL___POR       0x00000000
#define   DBG_TLV_TPDM_CMB_TPRn__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPRn__VAL___S                       0
#define   DBG_TLV_TPDM_CMB_TPRn___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_TPRn___S                            0
#define DBG_TLV_TPDM_CMB_TPR0                     (0x00BC2A08)
#define   DBG_TLV_TPDM_CMB_TPR0___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPR0__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPR0__VAL___S                       0

#define DBG_TLV_TPDM_CMB_TPRm(m)         (0x00BC2A08+0x4*(m))
#define   DBG_TLV_TPDM_CMB_TPRm_mMIN 1    
#define   DBG_TLV_TPDM_CMB_TPRm_mMAX 1    
#define   DBG_TLV_TPDM_CMB_TPRm_ELEM 1    
#define   DBG_TLV_TPDM_CMB_TPRm___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPRm___POR            0x00000000
#define   DBG_TLV_TPDM_CMB_TPRm__VAL___POR       0x00000000
#define   DBG_TLV_TPDM_CMB_TPRm__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPRm__VAL___S                       0
#define   DBG_TLV_TPDM_CMB_TPRm___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_TPRm___S                            0
#define DBG_TLV_TPDM_CMB_TPR1                     (0x00BC2A0C)
#define   DBG_TLV_TPDM_CMB_TPR1___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPR1__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPR1__VAL___S                       0

#define DBG_TLV_TPDM_CMB_TPMRn(n)        (0x00BC2A10+0x4*(n))
#define   DBG_TLV_TPDM_CMB_TPMRn_nMIN 0    
#define   DBG_TLV_TPDM_CMB_TPMRn_nMAX 0    
#define   DBG_TLV_TPDM_CMB_TPMRn_ELEM 1    
#define   DBG_TLV_TPDM_CMB_TPMRn___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPMRn___POR           0x00000000
#define   DBG_TLV_TPDM_CMB_TPMRn__VAL___POR      0x00000000
#define   DBG_TLV_TPDM_CMB_TPMRn__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPMRn__VAL___S                      0
#define   DBG_TLV_TPDM_CMB_TPMRn___M             0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_TPMRn___S                           0
#define DBG_TLV_TPDM_CMB_TPMR0                    (0x00BC2A10)
#define   DBG_TLV_TPDM_CMB_TPMR0___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPMR0__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPMR0__VAL___S                      0

#define DBG_TLV_TPDM_CMB_TPMRm(m)        (0x00BC2A10+0x4*(m))
#define   DBG_TLV_TPDM_CMB_TPMRm_mMIN 1    
#define   DBG_TLV_TPDM_CMB_TPMRm_mMAX 1    
#define   DBG_TLV_TPDM_CMB_TPMRm_ELEM 1    
#define   DBG_TLV_TPDM_CMB_TPMRm___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPMRm___POR           0x00000000
#define   DBG_TLV_TPDM_CMB_TPMRm__VAL___POR      0x00000000
#define   DBG_TLV_TPDM_CMB_TPMRm__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPMRm__VAL___S                      0
#define   DBG_TLV_TPDM_CMB_TPMRm___M             0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_TPMRm___S                           0
#define DBG_TLV_TPDM_CMB_TPMR1                    (0x00BC2A14)
#define   DBG_TLV_TPDM_CMB_TPMR1___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_TPMR1__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_TPMR1__VAL___S                      0

#define DBG_TLV_TPDM_CMB_XPRn(n)         (0x00BC2A18+0x4*(n))
#define   DBG_TLV_TPDM_CMB_XPRn_nMIN 0    
#define   DBG_TLV_TPDM_CMB_XPRn_nMAX 0    
#define   DBG_TLV_TPDM_CMB_XPRn_ELEM 1    
#define   DBG_TLV_TPDM_CMB_XPRn___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPRn___POR            0x00000000
#define   DBG_TLV_TPDM_CMB_XPRn__VAL___POR       0x00000000
#define   DBG_TLV_TPDM_CMB_XPRn__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPRn__VAL___S                       0
#define   DBG_TLV_TPDM_CMB_XPRn___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_XPRn___S                            0
#define DBG_TLV_TPDM_CMB_XPR0                     (0x00BC2A18)
#define   DBG_TLV_TPDM_CMB_XPR0___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPR0__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPR0__VAL___S                       0

#define DBG_TLV_TPDM_CMB_XPRm(m)         (0x00BC2A18+0x4*(m))
#define   DBG_TLV_TPDM_CMB_XPRm_mMIN 1    
#define   DBG_TLV_TPDM_CMB_XPRm_mMAX 1    
#define   DBG_TLV_TPDM_CMB_XPRm_ELEM 1    
#define   DBG_TLV_TPDM_CMB_XPRm___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPRm___POR            0x00000000
#define   DBG_TLV_TPDM_CMB_XPRm__VAL___POR       0x00000000
#define   DBG_TLV_TPDM_CMB_XPRm__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPRm__VAL___S                       0
#define   DBG_TLV_TPDM_CMB_XPRm___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_XPRm___S                            0
#define DBG_TLV_TPDM_CMB_XPR1                     (0x00BC2A1C)
#define   DBG_TLV_TPDM_CMB_XPR1___RWC               QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPR1__VAL___M         0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPR1__VAL___S                       0

#define DBG_TLV_TPDM_CMB_XPMRn(n)        (0x00BC2A20+0x4*(n))
#define   DBG_TLV_TPDM_CMB_XPMRn_nMIN 0    
#define   DBG_TLV_TPDM_CMB_XPMRn_nMAX 0    
#define   DBG_TLV_TPDM_CMB_XPMRn_ELEM 1    
#define   DBG_TLV_TPDM_CMB_XPMRn___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPMRn___POR           0x00000000
#define   DBG_TLV_TPDM_CMB_XPMRn__VAL___POR      0x00000000
#define   DBG_TLV_TPDM_CMB_XPMRn__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPMRn__VAL___S                      0
#define   DBG_TLV_TPDM_CMB_XPMRn___M             0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_XPMRn___S                           0
#define DBG_TLV_TPDM_CMB_XPMR0                    (0x00BC2A20)
#define   DBG_TLV_TPDM_CMB_XPMR0___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPMR0__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPMR0__VAL___S                      0

#define DBG_TLV_TPDM_CMB_XPMRm(m)        (0x00BC2A20+0x4*(m))
#define   DBG_TLV_TPDM_CMB_XPMRm_mMIN 1    
#define   DBG_TLV_TPDM_CMB_XPMRm_mMAX 1    
#define   DBG_TLV_TPDM_CMB_XPMRm_ELEM 1    
#define   DBG_TLV_TPDM_CMB_XPMRm___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPMRm___POR           0x00000000
#define   DBG_TLV_TPDM_CMB_XPMRm__VAL___POR      0x00000000
#define   DBG_TLV_TPDM_CMB_XPMRm__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPMRm__VAL___S                      0
#define   DBG_TLV_TPDM_CMB_XPMRm___M             0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_XPMRm___S                           0
#define DBG_TLV_TPDM_CMB_XPMR1                    (0x00BC2A24)
#define   DBG_TLV_TPDM_CMB_XPMR1___RWC              QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_XPMR1__VAL___M        0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_XPMR1__VAL___S                      0

#define DBG_TLV_TPDM_CMB_READCTL                  (0x00BC2A70)
#define   DBG_TLV_TPDM_CMB_READCTL___RWC            QCSR_REG_RW    
#define   DBG_TLV_TPDM_CMB_READCTL___POR         0x00000000
#define   DBG_TLV_TPDM_CMB_READCTL__SEL___POR    0x0
#define   DBG_TLV_TPDM_CMB_READCTL__SEL___M      0x00000001
#define   DBG_TLV_TPDM_CMB_READCTL__SEL___S                    0
#define   DBG_TLV_TPDM_CMB_READCTL___M           0x00000001   
#define   DBG_TLV_TPDM_CMB_READCTL___S                         0

#define DBG_TLV_TPDM_CMB_READVAL                  (0x00BC2A74)
#define   DBG_TLV_TPDM_CMB_READVAL___RWC            QCSR_REG_RO    
#define   DBG_TLV_TPDM_CMB_READVAL___POR         0x00000000
#define   DBG_TLV_TPDM_CMB_READVAL__VALUE___POR  0x00000000
#define   DBG_TLV_TPDM_CMB_READVAL__VALUE___M    0xFFFFFFFF
#define   DBG_TLV_TPDM_CMB_READVAL__VALUE___S                  0
#define   DBG_TLV_TPDM_CMB_READVAL___M           0xFFFFFFFF   
#define   DBG_TLV_TPDM_CMB_READVAL___S                         0

#define DBG_TLV_TPDM_ITATBCNTRL                   (0x00BC2EF0)
#define   DBG_TLV_TPDM_ITATBCNTRL___RWC             QCSR_REG_RW    
#define   DBG_TLV_TPDM_ITATBCNTRL___POR          0x00000000
#define   DBG_TLV_TPDM_ITATBCNTRL__TSREQ___POR   0x0
#define   DBG_TLV_TPDM_ITATBCNTRL__ATVALID___POR 0x0
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___POR 0x0
#define   DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___POR 0x0
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATA___POR  0x00
#define   DBG_TLV_TPDM_ITATBCNTRL__ATID___POR    0x00
#define   DBG_TLV_TPDM_ITATBCNTRL__TSVAL___POR   0x0
#define   DBG_TLV_TPDM_ITATBCNTRL__TSREQ___M     0x80000000
#define   DBG_TLV_TPDM_ITATBCNTRL__TSREQ___S                  31
#define   DBG_TLV_TPDM_ITATBCNTRL__ATVALID___M   0x40000000
#define   DBG_TLV_TPDM_ITATBCNTRL__ATVALID___S                30
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___M 0x00400000
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___S              22
#define   DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___M   0x003C0000
#define   DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___S                18
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATA___M    0x0003FC00
#define   DBG_TLV_TPDM_ITATBCNTRL__ATDATA___S                 10
#define   DBG_TLV_TPDM_ITATBCNTRL__ATID___M      0x000003F8
#define   DBG_TLV_TPDM_ITATBCNTRL__ATID___S                    3
#define   DBG_TLV_TPDM_ITATBCNTRL__TSVAL___M     0x00000007
#define   DBG_TLV_TPDM_ITATBCNTRL__TSVAL___S                   0
#define   DBG_TLV_TPDM_ITATBCNTRL___M            0xC07FFFFF   
#define   DBG_TLV_TPDM_ITATBCNTRL___S                          0

#define DBG_TLV_TPDM_ITCNTRL                      (0x00BC2F00)
#define   DBG_TLV_TPDM_ITCNTRL___RWC                QCSR_REG_RW    
#define   DBG_TLV_TPDM_ITCNTRL___POR             0x00000000
#define   DBG_TLV_TPDM_ITCNTRL__IME___POR        0x0
#define   DBG_TLV_TPDM_ITCNTRL__IME___M          0x00000001
#define   DBG_TLV_TPDM_ITCNTRL__IME___S                        0
#define   DBG_TLV_TPDM_ITCNTRL___M               0x00000001   
#define   DBG_TLV_TPDM_ITCNTRL___S                             0

#define DBG_TLV_TPDM_CLAIMSET                     (0x00BC2FA0)
#define   DBG_TLV_TPDM_CLAIMSET___RWC               QCSR_REG_RO    
#define   DBG_TLV_TPDM_CLAIMSET___POR            0x00000000
#define   DBG_TLV_TPDM_CLAIMSET__VAL_SET___POR   0x00000000
#define   DBG_TLV_TPDM_CLAIMSET__VAL_SET___M     0xFFFFFFFF
#define   DBG_TLV_TPDM_CLAIMSET__VAL_SET___S                   0
#define   DBG_TLV_TPDM_CLAIMSET___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CLAIMSET___S                            0

#define DBG_TLV_TPDM_CLAIMCLR                     (0x00BC2FA4)
#define   DBG_TLV_TPDM_CLAIMCLR___RWC               QCSR_REG_RO    
#define   DBG_TLV_TPDM_CLAIMCLR___POR            0x00000000
#define   DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___POR   0x00000000
#define   DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___M     0xFFFFFFFF
#define   DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___S                   0
#define   DBG_TLV_TPDM_CLAIMCLR___M              0xFFFFFFFF   
#define   DBG_TLV_TPDM_CLAIMCLR___S                            0

#define DBG_TLV_TPDM_DEVAFF0                      (0x00BC2FA8)
#define   DBG_TLV_TPDM_DEVAFF0___RWC                QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVAFF0___POR             0x00000000
#define   DBG_TLV_TPDM_DEVAFF0__VAL___POR        0x00000000
#define   DBG_TLV_TPDM_DEVAFF0__VAL___M          0xFFFFFFFF
#define   DBG_TLV_TPDM_DEVAFF0__VAL___S                        0
#define   DBG_TLV_TPDM_DEVAFF0___M               0xFFFFFFFF   
#define   DBG_TLV_TPDM_DEVAFF0___S                             0

#define DBG_TLV_TPDM_DEVAFF1                      (0x00BC2FAC)
#define   DBG_TLV_TPDM_DEVAFF1___RWC                QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVAFF1___POR             0x00000000
#define   DBG_TLV_TPDM_DEVAFF1__VAL___POR        0x00000000
#define   DBG_TLV_TPDM_DEVAFF1__VAL___M          0xFFFFFFFF
#define   DBG_TLV_TPDM_DEVAFF1__VAL___S                        0
#define   DBG_TLV_TPDM_DEVAFF1___M               0xFFFFFFFF   
#define   DBG_TLV_TPDM_DEVAFF1___S                             0

#define DBG_TLV_TPDM_LAR                          (0x00BC2FB0)
#define   DBG_TLV_TPDM_LAR___RWC                    QCSR_REG_WO    
#define   DBG_TLV_TPDM_LAR___POR                 0x00000000
#define   DBG_TLV_TPDM_LAR__KEY___POR            0x00000000
#define   DBG_TLV_TPDM_LAR__KEY___M              0xFFFFFFFF
#define   DBG_TLV_TPDM_LAR__KEY___S                            0
#define   DBG_TLV_TPDM_LAR___M                   0xFFFFFFFF   
#define   DBG_TLV_TPDM_LAR___S                                 0

#define DBG_TLV_TPDM_LSR                          (0x00BC2FB4)
#define   DBG_TLV_TPDM_LSR___RWC                    QCSR_REG_RO    
#define   DBG_TLV_TPDM_LSR___POR                 0x00000003
#define   DBG_TLV_TPDM_LSR__NTT___POR            0x0
#define   DBG_TLV_TPDM_LSR__SLK___POR            0x1
#define   DBG_TLV_TPDM_LSR__SLI___POR            0x1
#define   DBG_TLV_TPDM_LSR__NTT___M              0x00000004
#define   DBG_TLV_TPDM_LSR__NTT___S                            2
#define   DBG_TLV_TPDM_LSR__SLK___M              0x00000002
#define   DBG_TLV_TPDM_LSR__SLK___S                            1
#define   DBG_TLV_TPDM_LSR__SLI___M              0x00000001
#define   DBG_TLV_TPDM_LSR__SLI___S                            0
#define   DBG_TLV_TPDM_LSR___M                   0x00000007   
#define   DBG_TLV_TPDM_LSR___S                                 0

#define DBG_TLV_TPDM_AUTHSTATUS                   (0x00BC2FB8)
#define   DBG_TLV_TPDM_AUTHSTATUS___RWC             QCSR_REG_RO    
#define   DBG_TLV_TPDM_AUTHSTATUS___POR          0x000000AA
#define   DBG_TLV_TPDM_AUTHSTATUS__SNID___POR    0x2
#define   DBG_TLV_TPDM_AUTHSTATUS__SID___POR     0x2
#define   DBG_TLV_TPDM_AUTHSTATUS__NSNID___POR   0x2
#define   DBG_TLV_TPDM_AUTHSTATUS__NSID___POR    0x2
#define   DBG_TLV_TPDM_AUTHSTATUS__SNID___M      0x000000C0
#define   DBG_TLV_TPDM_AUTHSTATUS__SNID___S                    6
#define   DBG_TLV_TPDM_AUTHSTATUS__SID___M       0x00000030
#define   DBG_TLV_TPDM_AUTHSTATUS__SID___S                     4
#define   DBG_TLV_TPDM_AUTHSTATUS__NSNID___M     0x0000000C
#define   DBG_TLV_TPDM_AUTHSTATUS__NSNID___S                   2
#define   DBG_TLV_TPDM_AUTHSTATUS__NSID___M      0x00000003
#define   DBG_TLV_TPDM_AUTHSTATUS__NSID___S                    0
#define   DBG_TLV_TPDM_AUTHSTATUS___M            0x000000FF   
#define   DBG_TLV_TPDM_AUTHSTATUS___S                          0

#define DBG_TLV_TPDM_DEVARCH                      (0x00BC2FBC)
#define   DBG_TLV_TPDM_DEVARCH___RWC                QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVARCH___POR             0x0E105CDA
#define   DBG_TLV_TPDM_DEVARCH__ARCHITECT___POR  0x070
#define   DBG_TLV_TPDM_DEVARCH__PRESENT___POR    0x1
#define   DBG_TLV_TPDM_DEVARCH__REVISION___POR   0x0
#define   DBG_TLV_TPDM_DEVARCH__ARCHID___POR     0x5CDA
#define   DBG_TLV_TPDM_DEVARCH__ARCHITECT___M    0xFFE00000
#define   DBG_TLV_TPDM_DEVARCH__ARCHITECT___S                 21
#define   DBG_TLV_TPDM_DEVARCH__PRESENT___M      0x00100000
#define   DBG_TLV_TPDM_DEVARCH__PRESENT___S                   20
#define   DBG_TLV_TPDM_DEVARCH__REVISION___M     0x000F0000
#define   DBG_TLV_TPDM_DEVARCH__REVISION___S                  16
#define   DBG_TLV_TPDM_DEVARCH__ARCHID___M       0x0000FFFF
#define   DBG_TLV_TPDM_DEVARCH__ARCHID___S                     0
#define   DBG_TLV_TPDM_DEVARCH___M               0xFFFFFFFF   
#define   DBG_TLV_TPDM_DEVARCH___S                             0

#define DBG_TLV_TPDM_DEVID1                       (0x00BC2FC4)
#define   DBG_TLV_TPDM_DEVID1___RWC                 QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVID1___POR              0x40000000
#define   DBG_TLV_TPDM_DEVID1__CMB_LIVE___POR    0x0
#define   DBG_TLV_TPDM_DEVID1__DSB_LIVE___POR    0x1
#define   DBG_TLV_TPDM_DEVID1__CMB_LIVE___M      0x80000000
#define   DBG_TLV_TPDM_DEVID1__CMB_LIVE___S                   31
#define   DBG_TLV_TPDM_DEVID1__DSB_LIVE___M      0x40000000
#define   DBG_TLV_TPDM_DEVID1__DSB_LIVE___S                   30
#define   DBG_TLV_TPDM_DEVID1___M                0xC0000000   
#define   DBG_TLV_TPDM_DEVID1___S                             30

#define DBG_TLV_TPDM_DEVID                        (0x00BC2FC8)
#define   DBG_TLV_TPDM_DEVID___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVID___POR               0x15000008
#define   DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___POR  0x2
#define   DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___POR  0x2
#define   DBG_TLV_TPDM_DEVID__BC_GANG___POR      0x2
#define   DBG_TLV_TPDM_DEVID__CMB_IN___POR       0x2
#define   DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___M    0x18000000
#define   DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___S                 27
#define   DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___M    0x06000000
#define   DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___S                 25
#define   DBG_TLV_TPDM_DEVID__BC_GANG___M        0x01800000
#define   DBG_TLV_TPDM_DEVID__BC_GANG___S                     23
#define   DBG_TLV_TPDM_DEVID__CMB_IN___M         0x0000000C
#define   DBG_TLV_TPDM_DEVID__CMB_IN___S                       2
#define   DBG_TLV_TPDM_DEVID___M                 0x1F80000C   
#define   DBG_TLV_TPDM_DEVID___S                               2

#define DBG_TLV_TPDM_DEVTYPE                      (0x00BC2FCC)
#define   DBG_TLV_TPDM_DEVTYPE___RWC                QCSR_REG_RO    
#define   DBG_TLV_TPDM_DEVTYPE___POR             0x00000003
#define   DBG_TLV_TPDM_DEVTYPE__SUB___POR        0x0
#define   DBG_TLV_TPDM_DEVTYPE__MAJOR___POR      0x3
#define   DBG_TLV_TPDM_DEVTYPE__SUB___M          0x000000F0
#define   DBG_TLV_TPDM_DEVTYPE__SUB___S                        4
#define   DBG_TLV_TPDM_DEVTYPE__MAJOR___M        0x0000000F
#define   DBG_TLV_TPDM_DEVTYPE__MAJOR___S                      0
#define   DBG_TLV_TPDM_DEVTYPE___M               0x000000FF   
#define   DBG_TLV_TPDM_DEVTYPE___S                             0

#define DBG_TLV_TPDM_PIDR4                        (0x00BC2FD0)
#define   DBG_TLV_TPDM_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR4___POR               0x00000000
#define   DBG_TLV_TPDM_PIDR4__SIZE___POR         0x0
#define   DBG_TLV_TPDM_PIDR4__DES_2___POR        0x0
#define   DBG_TLV_TPDM_PIDR4__SIZE___M           0x000000F0
#define   DBG_TLV_TPDM_PIDR4__SIZE___S                         4
#define   DBG_TLV_TPDM_PIDR4__DES_2___M          0x0000000F
#define   DBG_TLV_TPDM_PIDR4__DES_2___S                        0
#define   DBG_TLV_TPDM_PIDR4___M                 0x000000FF   
#define   DBG_TLV_TPDM_PIDR4___S                               0

#define DBG_TLV_TPDM_PIDR5                        (0x00BC2FD4)
#define   DBG_TLV_TPDM_PIDR5___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR5___POR               0x00000000
#define   DBG_TLV_TPDM_PIDR5__EMPTY___POR        0x00000000
#define   DBG_TLV_TPDM_PIDR5__EMPTY___M          0xFFFFFFFF
#define   DBG_TLV_TPDM_PIDR5__EMPTY___S                        0
#define   DBG_TLV_TPDM_PIDR5___M                 0xFFFFFFFF   
#define   DBG_TLV_TPDM_PIDR5___S                               0

#define DBG_TLV_TPDM_PIDR6                        (0x00BC2FD8)
#define   DBG_TLV_TPDM_PIDR6___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR6___POR               0x00000000
#define   DBG_TLV_TPDM_PIDR6__EMPTY___POR        0x00000000
#define   DBG_TLV_TPDM_PIDR6__EMPTY___M          0xFFFFFFFF
#define   DBG_TLV_TPDM_PIDR6__EMPTY___S                        0
#define   DBG_TLV_TPDM_PIDR6___M                 0xFFFFFFFF   
#define   DBG_TLV_TPDM_PIDR6___S                               0

#define DBG_TLV_TPDM_PIDR7                        (0x00BC2FDC)
#define   DBG_TLV_TPDM_PIDR7___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR7___POR               0x00000000
#define   DBG_TLV_TPDM_PIDR7__EMPTY___POR        0x00000000
#define   DBG_TLV_TPDM_PIDR7__EMPTY___M          0xFFFFFFFF
#define   DBG_TLV_TPDM_PIDR7__EMPTY___S                        0
#define   DBG_TLV_TPDM_PIDR7___M                 0xFFFFFFFF   
#define   DBG_TLV_TPDM_PIDR7___S                               0

#define DBG_TLV_TPDM_PIDR0                        (0x00BC2FE0)
#define   DBG_TLV_TPDM_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR0___POR               0x00000024
#define   DBG_TLV_TPDM_PIDR0__PART_7___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_6___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_5___POR       0x1
#define   DBG_TLV_TPDM_PIDR0__PART_4___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_3___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_2___POR       0x1
#define   DBG_TLV_TPDM_PIDR0__PART_1___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_0___POR       0x0
#define   DBG_TLV_TPDM_PIDR0__PART_7___M         0x00000080
#define   DBG_TLV_TPDM_PIDR0__PART_7___S                       7
#define   DBG_TLV_TPDM_PIDR0__PART_6___M         0x00000040
#define   DBG_TLV_TPDM_PIDR0__PART_6___S                       6
#define   DBG_TLV_TPDM_PIDR0__PART_5___M         0x00000020
#define   DBG_TLV_TPDM_PIDR0__PART_5___S                       5
#define   DBG_TLV_TPDM_PIDR0__PART_4___M         0x00000010
#define   DBG_TLV_TPDM_PIDR0__PART_4___S                       4
#define   DBG_TLV_TPDM_PIDR0__PART_3___M         0x00000008
#define   DBG_TLV_TPDM_PIDR0__PART_3___S                       3
#define   DBG_TLV_TPDM_PIDR0__PART_2___M         0x00000004
#define   DBG_TLV_TPDM_PIDR0__PART_2___S                       2
#define   DBG_TLV_TPDM_PIDR0__PART_1___M         0x00000002
#define   DBG_TLV_TPDM_PIDR0__PART_1___S                       1
#define   DBG_TLV_TPDM_PIDR0__PART_0___M         0x00000001
#define   DBG_TLV_TPDM_PIDR0__PART_0___S                       0
#define   DBG_TLV_TPDM_PIDR0___M                 0x000000FF   
#define   DBG_TLV_TPDM_PIDR0___S                               0

#define DBG_TLV_TPDM_PIDR1                        (0x00BC2FE4)
#define   DBG_TLV_TPDM_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR1___POR               0x0000000E
#define   DBG_TLV_TPDM_PIDR1__DES_0___POR        0x0
#define   DBG_TLV_TPDM_PIDR1__PART_1___POR       0xE
#define   DBG_TLV_TPDM_PIDR1__DES_0___M          0x000000F0
#define   DBG_TLV_TPDM_PIDR1__DES_0___S                        4
#define   DBG_TLV_TPDM_PIDR1__PART_1___M         0x0000000F
#define   DBG_TLV_TPDM_PIDR1__PART_1___S                       0
#define   DBG_TLV_TPDM_PIDR1___M                 0x000000FF   
#define   DBG_TLV_TPDM_PIDR1___S                               0

#define DBG_TLV_TPDM_PIDR2                        (0x00BC2FE8)
#define   DBG_TLV_TPDM_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR2___POR               0x00000018
#define   DBG_TLV_TPDM_PIDR2__REVISION___POR     0x1
#define   DBG_TLV_TPDM_PIDR2__JEDEC___POR        0x1
#define   DBG_TLV_TPDM_PIDR2__DES_1___POR        0x0
#define   DBG_TLV_TPDM_PIDR2__REVISION___M       0x000000F0
#define   DBG_TLV_TPDM_PIDR2__REVISION___S                     4
#define   DBG_TLV_TPDM_PIDR2__JEDEC___M          0x00000008
#define   DBG_TLV_TPDM_PIDR2__JEDEC___S                        3
#define   DBG_TLV_TPDM_PIDR2__DES_1___M          0x00000007
#define   DBG_TLV_TPDM_PIDR2__DES_1___S                        0
#define   DBG_TLV_TPDM_PIDR2___M                 0x000000FF   
#define   DBG_TLV_TPDM_PIDR2___S                               0

#define DBG_TLV_TPDM_PIDR3                        (0x00BC2FEC)
#define   DBG_TLV_TPDM_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_PIDR3___POR               0x00000000
#define   DBG_TLV_TPDM_PIDR3__REVAND___POR       0x0
#define   DBG_TLV_TPDM_PIDR3__CMOD___POR         0x0
#define   DBG_TLV_TPDM_PIDR3__REVAND___M         0x000000F0
#define   DBG_TLV_TPDM_PIDR3__REVAND___S                       4
#define   DBG_TLV_TPDM_PIDR3__CMOD___M           0x0000000F
#define   DBG_TLV_TPDM_PIDR3__CMOD___S                         0
#define   DBG_TLV_TPDM_PIDR3___M                 0x000000FF   
#define   DBG_TLV_TPDM_PIDR3___S                               0

#define DBG_TLV_TPDM_CIDR0                        (0x00BC2FF0)
#define   DBG_TLV_TPDM_CIDR0___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_CIDR0___POR               0x0000000D
#define   DBG_TLV_TPDM_CIDR0__PRMBL_0___POR      0x0D
#define   DBG_TLV_TPDM_CIDR0__PRMBL_0___M        0x000000FF
#define   DBG_TLV_TPDM_CIDR0__PRMBL_0___S                      0
#define   DBG_TLV_TPDM_CIDR0___M                 0x000000FF   
#define   DBG_TLV_TPDM_CIDR0___S                               0

#define DBG_TLV_TPDM_CIDR1                        (0x00BC2FF4)
#define   DBG_TLV_TPDM_CIDR1___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_CIDR1___POR               0x00000090
#define   DBG_TLV_TPDM_CIDR1__CLASS___POR        0x9
#define   DBG_TLV_TPDM_CIDR1__PRMBL_1___POR      0x0
#define   DBG_TLV_TPDM_CIDR1__CLASS___M          0x000000F0
#define   DBG_TLV_TPDM_CIDR1__CLASS___S                        4
#define   DBG_TLV_TPDM_CIDR1__PRMBL_1___M        0x0000000F
#define   DBG_TLV_TPDM_CIDR1__PRMBL_1___S                      0
#define   DBG_TLV_TPDM_CIDR1___M                 0x000000FF   
#define   DBG_TLV_TPDM_CIDR1___S                               0

#define DBG_TLV_TPDM_CIDR2                        (0x00BC2FF8)
#define   DBG_TLV_TPDM_CIDR2___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_CIDR2___POR               0x00000005
#define   DBG_TLV_TPDM_CIDR2__PRMBL_2___POR      0x05
#define   DBG_TLV_TPDM_CIDR2__PRMBL_2___M        0x000000FF
#define   DBG_TLV_TPDM_CIDR2__PRMBL_2___S                      0
#define   DBG_TLV_TPDM_CIDR2___M                 0x000000FF   
#define   DBG_TLV_TPDM_CIDR2___S                               0

#define DBG_TLV_TPDM_CIDR3                        (0x00BC2FFC)
#define   DBG_TLV_TPDM_CIDR3___RWC                  QCSR_REG_RO    
#define   DBG_TLV_TPDM_CIDR3___POR               0x000000B1
#define   DBG_TLV_TPDM_CIDR3__PRMBL_3___POR      0xB1
#define   DBG_TLV_TPDM_CIDR3__PRMBL_3___M        0x000000FF
#define   DBG_TLV_TPDM_CIDR3__PRMBL_3___S                      0
#define   DBG_TLV_TPDM_CIDR3___M                 0x000000FF   
#define   DBG_TLV_TPDM_CIDR3___S                               0

#define DBG_TLV_TPDM_GPRn(n)             (0x00BC2000+0x4*(n))
#define   DBG_TLV_TPDM_GPRn_nMIN   0    
#define   DBG_TLV_TPDM_GPRn_nMAX   2    
#define   DBG_TLV_TPDM_GPRn_ELEM   3    
#define   DBG_TLV_TPDM_GPRn___RWC                   QCSR_REG_RW    
#define   DBG_TLV_TPDM_GPRn___POR                0x00000000
#define   DBG_TLV_TPDM_GPRn__VAL___POR           0x00000000
#define   DBG_TLV_TPDM_GPRn__VAL___M             0xFFFFFFFF
#define   DBG_TLV_TPDM_GPRn__VAL___S                           0
#define   DBG_TLV_TPDM_GPRn___M                  0xFFFFFFFF   
#define   DBG_TLV_TPDM_GPRn___S                                0
#define DBG_TLV_TPDM_GPR0                         (0x00BC2000)
#define   DBG_TLV_TPDM_GPR0___RWC                   QCSR_REG_RW    
#define   DBG_TLV_TPDM_GPR0__VAL___M             0xFFFFFFFF
#define   DBG_TLV_TPDM_GPR0__VAL___S                           0
#define DBG_TLV_TPDM_GPR1                         (0x00BC2004)
#define   DBG_TLV_TPDM_GPR1___RWC                   QCSR_REG_RW    
#define   DBG_TLV_TPDM_GPR1__VAL___M             0xFFFFFFFF
#define   DBG_TLV_TPDM_GPR1__VAL___S                           0
#define DBG_TLV_TPDM_GPR2                         (0x00BC2008)
#define   DBG_TLV_TPDM_GPR2___RWC                   QCSR_REG_RW    
#define   DBG_TLV_TPDM_GPR2__VAL___M             0xFFFFFFFF
#define   DBG_TLV_TPDM_GPR2__VAL___S                           0

#define DBG_MISC_TPDM_CMB_CR                      (0x00BC3A00)
#define   DBG_MISC_TPDM_CMB_CR___RWC                QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_CR___POR             0x00000000
#define   DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___POR 0x0
#define   DBG_MISC_TPDM_CMB_CR__EBITSET___POR    0x0
#define   DBG_MISC_TPDM_CMB_CR__FLOWCTRL___POR   0x0
#define   DBG_MISC_TPDM_CMB_CR__MODE___POR       0x0
#define   DBG_MISC_TPDM_CMB_CR__E___POR          0x0
#define   DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___M   0x00000080
#define   DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___S                 7
#define   DBG_MISC_TPDM_CMB_CR__EBITSET___M      0x00000040
#define   DBG_MISC_TPDM_CMB_CR__EBITSET___S                    6
#define   DBG_MISC_TPDM_CMB_CR__FLOWCTRL___M     0x00000004
#define   DBG_MISC_TPDM_CMB_CR__FLOWCTRL___S                   2
#define   DBG_MISC_TPDM_CMB_CR__MODE___M         0x00000002
#define   DBG_MISC_TPDM_CMB_CR__MODE___S                       1
#define   DBG_MISC_TPDM_CMB_CR__E___M            0x00000001
#define   DBG_MISC_TPDM_CMB_CR__E___S                          0
#define   DBG_MISC_TPDM_CMB_CR___M               0x000000C7   
#define   DBG_MISC_TPDM_CMB_CR___S                             0

#define DBG_MISC_TPDM_CMB_TIER                    (0x00BC3A04)
#define   DBG_MISC_TPDM_CMB_TIER___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TIER___POR           0x00000000
#define   DBG_MISC_TPDM_CMB_TIER__TS_ALL___POR   0x0
#define   DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___POR 0x0
#define   DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___POR 0x0
#define   DBG_MISC_TPDM_CMB_TIER__TS_ALL___M     0x00000004
#define   DBG_MISC_TPDM_CMB_TIER__TS_ALL___S                   2
#define   DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___M 0x00000002
#define   DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___S               1
#define   DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___M 0x00000001
#define   DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___S               0
#define   DBG_MISC_TPDM_CMB_TIER___M             0x00000007   
#define   DBG_MISC_TPDM_CMB_TIER___S                           0

#define DBG_MISC_TPDM_CMB_TPRn(n)        (0x00BC3A08+0x4*(n))
#define   DBG_MISC_TPDM_CMB_TPRn_nMIN 0    
#define   DBG_MISC_TPDM_CMB_TPRn_nMAX 0    
#define   DBG_MISC_TPDM_CMB_TPRn_ELEM 1    
#define   DBG_MISC_TPDM_CMB_TPRn___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPRn___POR           0x00000000
#define   DBG_MISC_TPDM_CMB_TPRn__VAL___POR      0x00000000
#define   DBG_MISC_TPDM_CMB_TPRn__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPRn__VAL___S                      0
#define   DBG_MISC_TPDM_CMB_TPRn___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_TPRn___S                           0
#define DBG_MISC_TPDM_CMB_TPR0                    (0x00BC3A08)
#define   DBG_MISC_TPDM_CMB_TPR0___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPR0__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPR0__VAL___S                      0

#define DBG_MISC_TPDM_CMB_TPRm(m)        (0x00BC3A08+0x4*(m))
#define   DBG_MISC_TPDM_CMB_TPRm_mMIN 1    
#define   DBG_MISC_TPDM_CMB_TPRm_mMAX 1    
#define   DBG_MISC_TPDM_CMB_TPRm_ELEM 1    
#define   DBG_MISC_TPDM_CMB_TPRm___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPRm___POR           0x00000000
#define   DBG_MISC_TPDM_CMB_TPRm__VAL___POR      0x00000000
#define   DBG_MISC_TPDM_CMB_TPRm__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPRm__VAL___S                      0
#define   DBG_MISC_TPDM_CMB_TPRm___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_TPRm___S                           0
#define DBG_MISC_TPDM_CMB_TPR1                    (0x00BC3A0C)
#define   DBG_MISC_TPDM_CMB_TPR1___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPR1__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPR1__VAL___S                      0

#define DBG_MISC_TPDM_CMB_TPMRn(n)       (0x00BC3A10+0x4*(n))
#define   DBG_MISC_TPDM_CMB_TPMRn_nMIN 0    
#define   DBG_MISC_TPDM_CMB_TPMRn_nMAX 0    
#define   DBG_MISC_TPDM_CMB_TPMRn_ELEM 1    
#define   DBG_MISC_TPDM_CMB_TPMRn___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPMRn___POR          0x00000000
#define   DBG_MISC_TPDM_CMB_TPMRn__VAL___POR     0x00000000
#define   DBG_MISC_TPDM_CMB_TPMRn__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPMRn__VAL___S                     0
#define   DBG_MISC_TPDM_CMB_TPMRn___M            0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_TPMRn___S                          0
#define DBG_MISC_TPDM_CMB_TPMR0                   (0x00BC3A10)
#define   DBG_MISC_TPDM_CMB_TPMR0___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPMR0__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPMR0__VAL___S                     0

#define DBG_MISC_TPDM_CMB_TPMRm(m)       (0x00BC3A10+0x4*(m))
#define   DBG_MISC_TPDM_CMB_TPMRm_mMIN 1    
#define   DBG_MISC_TPDM_CMB_TPMRm_mMAX 1    
#define   DBG_MISC_TPDM_CMB_TPMRm_ELEM 1    
#define   DBG_MISC_TPDM_CMB_TPMRm___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPMRm___POR          0x00000000
#define   DBG_MISC_TPDM_CMB_TPMRm__VAL___POR     0x00000000
#define   DBG_MISC_TPDM_CMB_TPMRm__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPMRm__VAL___S                     0
#define   DBG_MISC_TPDM_CMB_TPMRm___M            0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_TPMRm___S                          0
#define DBG_MISC_TPDM_CMB_TPMR1                   (0x00BC3A14)
#define   DBG_MISC_TPDM_CMB_TPMR1___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_TPMR1__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_TPMR1__VAL___S                     0

#define DBG_MISC_TPDM_CMB_XPRn(n)        (0x00BC3A18+0x4*(n))
#define   DBG_MISC_TPDM_CMB_XPRn_nMIN 0    
#define   DBG_MISC_TPDM_CMB_XPRn_nMAX 0    
#define   DBG_MISC_TPDM_CMB_XPRn_ELEM 1    
#define   DBG_MISC_TPDM_CMB_XPRn___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPRn___POR           0x00000000
#define   DBG_MISC_TPDM_CMB_XPRn__VAL___POR      0x00000000
#define   DBG_MISC_TPDM_CMB_XPRn__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPRn__VAL___S                      0
#define   DBG_MISC_TPDM_CMB_XPRn___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_XPRn___S                           0
#define DBG_MISC_TPDM_CMB_XPR0                    (0x00BC3A18)
#define   DBG_MISC_TPDM_CMB_XPR0___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPR0__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPR0__VAL___S                      0

#define DBG_MISC_TPDM_CMB_XPRm(m)        (0x00BC3A18+0x4*(m))
#define   DBG_MISC_TPDM_CMB_XPRm_mMIN 1    
#define   DBG_MISC_TPDM_CMB_XPRm_mMAX 1    
#define   DBG_MISC_TPDM_CMB_XPRm_ELEM 1    
#define   DBG_MISC_TPDM_CMB_XPRm___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPRm___POR           0x00000000
#define   DBG_MISC_TPDM_CMB_XPRm__VAL___POR      0x00000000
#define   DBG_MISC_TPDM_CMB_XPRm__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPRm__VAL___S                      0
#define   DBG_MISC_TPDM_CMB_XPRm___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_XPRm___S                           0
#define DBG_MISC_TPDM_CMB_XPR1                    (0x00BC3A1C)
#define   DBG_MISC_TPDM_CMB_XPR1___RWC              QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPR1__VAL___M        0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPR1__VAL___S                      0

#define DBG_MISC_TPDM_CMB_XPMRn(n)       (0x00BC3A20+0x4*(n))
#define   DBG_MISC_TPDM_CMB_XPMRn_nMIN 0    
#define   DBG_MISC_TPDM_CMB_XPMRn_nMAX 0    
#define   DBG_MISC_TPDM_CMB_XPMRn_ELEM 1    
#define   DBG_MISC_TPDM_CMB_XPMRn___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPMRn___POR          0x00000000
#define   DBG_MISC_TPDM_CMB_XPMRn__VAL___POR     0x00000000
#define   DBG_MISC_TPDM_CMB_XPMRn__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPMRn__VAL___S                     0
#define   DBG_MISC_TPDM_CMB_XPMRn___M            0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_XPMRn___S                          0
#define DBG_MISC_TPDM_CMB_XPMR0                   (0x00BC3A20)
#define   DBG_MISC_TPDM_CMB_XPMR0___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPMR0__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPMR0__VAL___S                     0

#define DBG_MISC_TPDM_CMB_XPMRm(m)       (0x00BC3A20+0x4*(m))
#define   DBG_MISC_TPDM_CMB_XPMRm_mMIN 1    
#define   DBG_MISC_TPDM_CMB_XPMRm_mMAX 1    
#define   DBG_MISC_TPDM_CMB_XPMRm_ELEM 1    
#define   DBG_MISC_TPDM_CMB_XPMRm___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPMRm___POR          0x00000000
#define   DBG_MISC_TPDM_CMB_XPMRm__VAL___POR     0x00000000
#define   DBG_MISC_TPDM_CMB_XPMRm__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPMRm__VAL___S                     0
#define   DBG_MISC_TPDM_CMB_XPMRm___M            0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_XPMRm___S                          0
#define DBG_MISC_TPDM_CMB_XPMR1                   (0x00BC3A24)
#define   DBG_MISC_TPDM_CMB_XPMR1___RWC             QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_XPMR1__VAL___M       0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_XPMR1__VAL___S                     0

#define DBG_MISC_TPDM_CMB_READCTL                 (0x00BC3A70)
#define   DBG_MISC_TPDM_CMB_READCTL___RWC           QCSR_REG_RW    
#define   DBG_MISC_TPDM_CMB_READCTL___POR        0x00000000
#define   DBG_MISC_TPDM_CMB_READCTL__SEL___POR   0x0
#define   DBG_MISC_TPDM_CMB_READCTL__SEL___M     0x00000001
#define   DBG_MISC_TPDM_CMB_READCTL__SEL___S                   0
#define   DBG_MISC_TPDM_CMB_READCTL___M          0x00000001   
#define   DBG_MISC_TPDM_CMB_READCTL___S                        0

#define DBG_MISC_TPDM_CMB_READVAL                 (0x00BC3A74)
#define   DBG_MISC_TPDM_CMB_READVAL___RWC           QCSR_REG_RO    
#define   DBG_MISC_TPDM_CMB_READVAL___POR        0x00000000
#define   DBG_MISC_TPDM_CMB_READVAL__VALUE___POR 0x00000000
#define   DBG_MISC_TPDM_CMB_READVAL__VALUE___M   0xFFFFFFFF
#define   DBG_MISC_TPDM_CMB_READVAL__VALUE___S                 0
#define   DBG_MISC_TPDM_CMB_READVAL___M          0xFFFFFFFF   
#define   DBG_MISC_TPDM_CMB_READVAL___S                        0

#define DBG_MISC_TPDM_ITATBCNTRL                  (0x00BC3EF0)
#define   DBG_MISC_TPDM_ITATBCNTRL___RWC            QCSR_REG_RW    
#define   DBG_MISC_TPDM_ITATBCNTRL___POR         0x00000000
#define   DBG_MISC_TPDM_ITATBCNTRL__TSREQ___POR  0x0
#define   DBG_MISC_TPDM_ITATBCNTRL__ATVALID___POR 0x0
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___POR 0x0
#define   DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___POR 0x0
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATA___POR 0x00
#define   DBG_MISC_TPDM_ITATBCNTRL__ATID___POR   0x00
#define   DBG_MISC_TPDM_ITATBCNTRL__TSVAL___POR  0x0
#define   DBG_MISC_TPDM_ITATBCNTRL__TSREQ___M    0x80000000
#define   DBG_MISC_TPDM_ITATBCNTRL__TSREQ___S                 31
#define   DBG_MISC_TPDM_ITATBCNTRL__ATVALID___M  0x40000000
#define   DBG_MISC_TPDM_ITATBCNTRL__ATVALID___S               30
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___M 0x00400000
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___S              22
#define   DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___M  0x003C0000
#define   DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___S               18
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATA___M   0x0003FC00
#define   DBG_MISC_TPDM_ITATBCNTRL__ATDATA___S                10
#define   DBG_MISC_TPDM_ITATBCNTRL__ATID___M     0x000003F8
#define   DBG_MISC_TPDM_ITATBCNTRL__ATID___S                   3
#define   DBG_MISC_TPDM_ITATBCNTRL__TSVAL___M    0x00000007
#define   DBG_MISC_TPDM_ITATBCNTRL__TSVAL___S                  0
#define   DBG_MISC_TPDM_ITATBCNTRL___M           0xC07FFFFF   
#define   DBG_MISC_TPDM_ITATBCNTRL___S                         0

#define DBG_MISC_TPDM_ITCNTRL                     (0x00BC3F00)
#define   DBG_MISC_TPDM_ITCNTRL___RWC               QCSR_REG_RW    
#define   DBG_MISC_TPDM_ITCNTRL___POR            0x00000000
#define   DBG_MISC_TPDM_ITCNTRL__IME___POR       0x0
#define   DBG_MISC_TPDM_ITCNTRL__IME___M         0x00000001
#define   DBG_MISC_TPDM_ITCNTRL__IME___S                       0
#define   DBG_MISC_TPDM_ITCNTRL___M              0x00000001   
#define   DBG_MISC_TPDM_ITCNTRL___S                            0

#define DBG_MISC_TPDM_CLAIMSET                    (0x00BC3FA0)
#define   DBG_MISC_TPDM_CLAIMSET___RWC              QCSR_REG_RO    
#define   DBG_MISC_TPDM_CLAIMSET___POR           0x00000000
#define   DBG_MISC_TPDM_CLAIMSET__VAL_SET___POR  0x00000000
#define   DBG_MISC_TPDM_CLAIMSET__VAL_SET___M    0xFFFFFFFF
#define   DBG_MISC_TPDM_CLAIMSET__VAL_SET___S                  0
#define   DBG_MISC_TPDM_CLAIMSET___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CLAIMSET___S                           0

#define DBG_MISC_TPDM_CLAIMCLR                    (0x00BC3FA4)
#define   DBG_MISC_TPDM_CLAIMCLR___RWC              QCSR_REG_RO    
#define   DBG_MISC_TPDM_CLAIMCLR___POR           0x00000000
#define   DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___POR  0x00000000
#define   DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___M    0xFFFFFFFF
#define   DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___S                  0
#define   DBG_MISC_TPDM_CLAIMCLR___M             0xFFFFFFFF   
#define   DBG_MISC_TPDM_CLAIMCLR___S                           0

#define DBG_MISC_TPDM_DEVAFF0                     (0x00BC3FA8)
#define   DBG_MISC_TPDM_DEVAFF0___RWC               QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVAFF0___POR            0x00000000
#define   DBG_MISC_TPDM_DEVAFF0__VAL___POR       0x00000000
#define   DBG_MISC_TPDM_DEVAFF0__VAL___M         0xFFFFFFFF
#define   DBG_MISC_TPDM_DEVAFF0__VAL___S                       0
#define   DBG_MISC_TPDM_DEVAFF0___M              0xFFFFFFFF   
#define   DBG_MISC_TPDM_DEVAFF0___S                            0

#define DBG_MISC_TPDM_DEVAFF1                     (0x00BC3FAC)
#define   DBG_MISC_TPDM_DEVAFF1___RWC               QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVAFF1___POR            0x00000000
#define   DBG_MISC_TPDM_DEVAFF1__VAL___POR       0x00000000
#define   DBG_MISC_TPDM_DEVAFF1__VAL___M         0xFFFFFFFF
#define   DBG_MISC_TPDM_DEVAFF1__VAL___S                       0
#define   DBG_MISC_TPDM_DEVAFF1___M              0xFFFFFFFF   
#define   DBG_MISC_TPDM_DEVAFF1___S                            0

#define DBG_MISC_TPDM_LAR                         (0x00BC3FB0)
#define   DBG_MISC_TPDM_LAR___RWC                   QCSR_REG_WO    
#define   DBG_MISC_TPDM_LAR___POR                0x00000000
#define   DBG_MISC_TPDM_LAR__KEY___POR           0x00000000
#define   DBG_MISC_TPDM_LAR__KEY___M             0xFFFFFFFF
#define   DBG_MISC_TPDM_LAR__KEY___S                           0
#define   DBG_MISC_TPDM_LAR___M                  0xFFFFFFFF   
#define   DBG_MISC_TPDM_LAR___S                                0

#define DBG_MISC_TPDM_LSR                         (0x00BC3FB4)
#define   DBG_MISC_TPDM_LSR___RWC                   QCSR_REG_RO    
#define   DBG_MISC_TPDM_LSR___POR                0x00000003
#define   DBG_MISC_TPDM_LSR__NTT___POR           0x0
#define   DBG_MISC_TPDM_LSR__SLK___POR           0x1
#define   DBG_MISC_TPDM_LSR__SLI___POR           0x1
#define   DBG_MISC_TPDM_LSR__NTT___M             0x00000004
#define   DBG_MISC_TPDM_LSR__NTT___S                           2
#define   DBG_MISC_TPDM_LSR__SLK___M             0x00000002
#define   DBG_MISC_TPDM_LSR__SLK___S                           1
#define   DBG_MISC_TPDM_LSR__SLI___M             0x00000001
#define   DBG_MISC_TPDM_LSR__SLI___S                           0
#define   DBG_MISC_TPDM_LSR___M                  0x00000007   
#define   DBG_MISC_TPDM_LSR___S                                0

#define DBG_MISC_TPDM_AUTHSTATUS                  (0x00BC3FB8)
#define   DBG_MISC_TPDM_AUTHSTATUS___RWC            QCSR_REG_RO    
#define   DBG_MISC_TPDM_AUTHSTATUS___POR         0x000000AA
#define   DBG_MISC_TPDM_AUTHSTATUS__SNID___POR   0x2
#define   DBG_MISC_TPDM_AUTHSTATUS__SID___POR    0x2
#define   DBG_MISC_TPDM_AUTHSTATUS__NSNID___POR  0x2
#define   DBG_MISC_TPDM_AUTHSTATUS__NSID___POR   0x2
#define   DBG_MISC_TPDM_AUTHSTATUS__SNID___M     0x000000C0
#define   DBG_MISC_TPDM_AUTHSTATUS__SNID___S                   6
#define   DBG_MISC_TPDM_AUTHSTATUS__SID___M      0x00000030
#define   DBG_MISC_TPDM_AUTHSTATUS__SID___S                    4
#define   DBG_MISC_TPDM_AUTHSTATUS__NSNID___M    0x0000000C
#define   DBG_MISC_TPDM_AUTHSTATUS__NSNID___S                  2
#define   DBG_MISC_TPDM_AUTHSTATUS__NSID___M     0x00000003
#define   DBG_MISC_TPDM_AUTHSTATUS__NSID___S                   0
#define   DBG_MISC_TPDM_AUTHSTATUS___M           0x000000FF   
#define   DBG_MISC_TPDM_AUTHSTATUS___S                         0

#define DBG_MISC_TPDM_DEVARCH                     (0x00BC3FBC)
#define   DBG_MISC_TPDM_DEVARCH___RWC               QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVARCH___POR            0x0E105CDA
#define   DBG_MISC_TPDM_DEVARCH__ARCHITECT___POR 0x070
#define   DBG_MISC_TPDM_DEVARCH__PRESENT___POR   0x1
#define   DBG_MISC_TPDM_DEVARCH__REVISION___POR  0x0
#define   DBG_MISC_TPDM_DEVARCH__ARCHID___POR    0x5CDA
#define   DBG_MISC_TPDM_DEVARCH__ARCHITECT___M   0xFFE00000
#define   DBG_MISC_TPDM_DEVARCH__ARCHITECT___S                21
#define   DBG_MISC_TPDM_DEVARCH__PRESENT___M     0x00100000
#define   DBG_MISC_TPDM_DEVARCH__PRESENT___S                  20
#define   DBG_MISC_TPDM_DEVARCH__REVISION___M    0x000F0000
#define   DBG_MISC_TPDM_DEVARCH__REVISION___S                 16
#define   DBG_MISC_TPDM_DEVARCH__ARCHID___M      0x0000FFFF
#define   DBG_MISC_TPDM_DEVARCH__ARCHID___S                    0
#define   DBG_MISC_TPDM_DEVARCH___M              0xFFFFFFFF   
#define   DBG_MISC_TPDM_DEVARCH___S                            0

#define DBG_MISC_TPDM_DEVID1                      (0x00BC3FC4)
#define   DBG_MISC_TPDM_DEVID1___RWC                QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVID1___POR             0x40000000
#define   DBG_MISC_TPDM_DEVID1__CMB_LIVE___POR   0x0
#define   DBG_MISC_TPDM_DEVID1__DSB_LIVE___POR   0x1
#define   DBG_MISC_TPDM_DEVID1__CMB_LIVE___M     0x80000000
#define   DBG_MISC_TPDM_DEVID1__CMB_LIVE___S                  31
#define   DBG_MISC_TPDM_DEVID1__DSB_LIVE___M     0x40000000
#define   DBG_MISC_TPDM_DEVID1__DSB_LIVE___S                  30
#define   DBG_MISC_TPDM_DEVID1___M               0xC0000000   
#define   DBG_MISC_TPDM_DEVID1___S                            30

#define DBG_MISC_TPDM_DEVID                       (0x00BC3FC8)
#define   DBG_MISC_TPDM_DEVID___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVID___POR              0x15000008
#define   DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___POR 0x2
#define   DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___POR 0x2
#define   DBG_MISC_TPDM_DEVID__BC_GANG___POR     0x2
#define   DBG_MISC_TPDM_DEVID__CMB_IN___POR      0x2
#define   DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___M   0x18000000
#define   DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___S                27
#define   DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___M   0x06000000
#define   DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___S                25
#define   DBG_MISC_TPDM_DEVID__BC_GANG___M       0x01800000
#define   DBG_MISC_TPDM_DEVID__BC_GANG___S                    23
#define   DBG_MISC_TPDM_DEVID__CMB_IN___M        0x0000000C
#define   DBG_MISC_TPDM_DEVID__CMB_IN___S                      2
#define   DBG_MISC_TPDM_DEVID___M                0x1F80000C   
#define   DBG_MISC_TPDM_DEVID___S                              2

#define DBG_MISC_TPDM_DEVTYPE                     (0x00BC3FCC)
#define   DBG_MISC_TPDM_DEVTYPE___RWC               QCSR_REG_RO    
#define   DBG_MISC_TPDM_DEVTYPE___POR            0x00000003
#define   DBG_MISC_TPDM_DEVTYPE__SUB___POR       0x0
#define   DBG_MISC_TPDM_DEVTYPE__MAJOR___POR     0x3
#define   DBG_MISC_TPDM_DEVTYPE__SUB___M         0x000000F0
#define   DBG_MISC_TPDM_DEVTYPE__SUB___S                       4
#define   DBG_MISC_TPDM_DEVTYPE__MAJOR___M       0x0000000F
#define   DBG_MISC_TPDM_DEVTYPE__MAJOR___S                     0
#define   DBG_MISC_TPDM_DEVTYPE___M              0x000000FF   
#define   DBG_MISC_TPDM_DEVTYPE___S                            0

#define DBG_MISC_TPDM_PIDR4                       (0x00BC3FD0)
#define   DBG_MISC_TPDM_PIDR4___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR4___POR              0x00000000
#define   DBG_MISC_TPDM_PIDR4__SIZE___POR        0x0
#define   DBG_MISC_TPDM_PIDR4__DES_2___POR       0x0
#define   DBG_MISC_TPDM_PIDR4__SIZE___M          0x000000F0
#define   DBG_MISC_TPDM_PIDR4__SIZE___S                        4
#define   DBG_MISC_TPDM_PIDR4__DES_2___M         0x0000000F
#define   DBG_MISC_TPDM_PIDR4__DES_2___S                       0
#define   DBG_MISC_TPDM_PIDR4___M                0x000000FF   
#define   DBG_MISC_TPDM_PIDR4___S                              0

#define DBG_MISC_TPDM_PIDR5                       (0x00BC3FD4)
#define   DBG_MISC_TPDM_PIDR5___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR5___POR              0x00000000
#define   DBG_MISC_TPDM_PIDR5__EMPTY___POR       0x00000000
#define   DBG_MISC_TPDM_PIDR5__EMPTY___M         0xFFFFFFFF
#define   DBG_MISC_TPDM_PIDR5__EMPTY___S                       0
#define   DBG_MISC_TPDM_PIDR5___M                0xFFFFFFFF   
#define   DBG_MISC_TPDM_PIDR5___S                              0

#define DBG_MISC_TPDM_PIDR6                       (0x00BC3FD8)
#define   DBG_MISC_TPDM_PIDR6___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR6___POR              0x00000000
#define   DBG_MISC_TPDM_PIDR6__EMPTY___POR       0x00000000
#define   DBG_MISC_TPDM_PIDR6__EMPTY___M         0xFFFFFFFF
#define   DBG_MISC_TPDM_PIDR6__EMPTY___S                       0
#define   DBG_MISC_TPDM_PIDR6___M                0xFFFFFFFF   
#define   DBG_MISC_TPDM_PIDR6___S                              0

#define DBG_MISC_TPDM_PIDR7                       (0x00BC3FDC)
#define   DBG_MISC_TPDM_PIDR7___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR7___POR              0x00000000
#define   DBG_MISC_TPDM_PIDR7__EMPTY___POR       0x00000000
#define   DBG_MISC_TPDM_PIDR7__EMPTY___M         0xFFFFFFFF
#define   DBG_MISC_TPDM_PIDR7__EMPTY___S                       0
#define   DBG_MISC_TPDM_PIDR7___M                0xFFFFFFFF   
#define   DBG_MISC_TPDM_PIDR7___S                              0

#define DBG_MISC_TPDM_PIDR0                       (0x00BC3FE0)
#define   DBG_MISC_TPDM_PIDR0___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR0___POR              0x00000024
#define   DBG_MISC_TPDM_PIDR0__PART_7___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_6___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_5___POR      0x1
#define   DBG_MISC_TPDM_PIDR0__PART_4___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_3___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_2___POR      0x1
#define   DBG_MISC_TPDM_PIDR0__PART_1___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_0___POR      0x0
#define   DBG_MISC_TPDM_PIDR0__PART_7___M        0x00000080
#define   DBG_MISC_TPDM_PIDR0__PART_7___S                      7
#define   DBG_MISC_TPDM_PIDR0__PART_6___M        0x00000040
#define   DBG_MISC_TPDM_PIDR0__PART_6___S                      6
#define   DBG_MISC_TPDM_PIDR0__PART_5___M        0x00000020
#define   DBG_MISC_TPDM_PIDR0__PART_5___S                      5
#define   DBG_MISC_TPDM_PIDR0__PART_4___M        0x00000010
#define   DBG_MISC_TPDM_PIDR0__PART_4___S                      4
#define   DBG_MISC_TPDM_PIDR0__PART_3___M        0x00000008
#define   DBG_MISC_TPDM_PIDR0__PART_3___S                      3
#define   DBG_MISC_TPDM_PIDR0__PART_2___M        0x00000004
#define   DBG_MISC_TPDM_PIDR0__PART_2___S                      2
#define   DBG_MISC_TPDM_PIDR0__PART_1___M        0x00000002
#define   DBG_MISC_TPDM_PIDR0__PART_1___S                      1
#define   DBG_MISC_TPDM_PIDR0__PART_0___M        0x00000001
#define   DBG_MISC_TPDM_PIDR0__PART_0___S                      0
#define   DBG_MISC_TPDM_PIDR0___M                0x000000FF   
#define   DBG_MISC_TPDM_PIDR0___S                              0

#define DBG_MISC_TPDM_PIDR1                       (0x00BC3FE4)
#define   DBG_MISC_TPDM_PIDR1___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR1___POR              0x0000000E
#define   DBG_MISC_TPDM_PIDR1__DES_0___POR       0x0
#define   DBG_MISC_TPDM_PIDR1__PART_1___POR      0xE
#define   DBG_MISC_TPDM_PIDR1__DES_0___M         0x000000F0
#define   DBG_MISC_TPDM_PIDR1__DES_0___S                       4
#define   DBG_MISC_TPDM_PIDR1__PART_1___M        0x0000000F
#define   DBG_MISC_TPDM_PIDR1__PART_1___S                      0
#define   DBG_MISC_TPDM_PIDR1___M                0x000000FF   
#define   DBG_MISC_TPDM_PIDR1___S                              0

#define DBG_MISC_TPDM_PIDR2                       (0x00BC3FE8)
#define   DBG_MISC_TPDM_PIDR2___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR2___POR              0x00000018
#define   DBG_MISC_TPDM_PIDR2__REVISION___POR    0x1
#define   DBG_MISC_TPDM_PIDR2__JEDEC___POR       0x1
#define   DBG_MISC_TPDM_PIDR2__DES_1___POR       0x0
#define   DBG_MISC_TPDM_PIDR2__REVISION___M      0x000000F0
#define   DBG_MISC_TPDM_PIDR2__REVISION___S                    4
#define   DBG_MISC_TPDM_PIDR2__JEDEC___M         0x00000008
#define   DBG_MISC_TPDM_PIDR2__JEDEC___S                       3
#define   DBG_MISC_TPDM_PIDR2__DES_1___M         0x00000007
#define   DBG_MISC_TPDM_PIDR2__DES_1___S                       0
#define   DBG_MISC_TPDM_PIDR2___M                0x000000FF   
#define   DBG_MISC_TPDM_PIDR2___S                              0

#define DBG_MISC_TPDM_PIDR3                       (0x00BC3FEC)
#define   DBG_MISC_TPDM_PIDR3___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_PIDR3___POR              0x00000000
#define   DBG_MISC_TPDM_PIDR3__REVAND___POR      0x0
#define   DBG_MISC_TPDM_PIDR3__CMOD___POR        0x0
#define   DBG_MISC_TPDM_PIDR3__REVAND___M        0x000000F0
#define   DBG_MISC_TPDM_PIDR3__REVAND___S                      4
#define   DBG_MISC_TPDM_PIDR3__CMOD___M          0x0000000F
#define   DBG_MISC_TPDM_PIDR3__CMOD___S                        0
#define   DBG_MISC_TPDM_PIDR3___M                0x000000FF   
#define   DBG_MISC_TPDM_PIDR3___S                              0

#define DBG_MISC_TPDM_CIDR0                       (0x00BC3FF0)
#define   DBG_MISC_TPDM_CIDR0___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_CIDR0___POR              0x0000000D
#define   DBG_MISC_TPDM_CIDR0__PRMBL_0___POR     0x0D
#define   DBG_MISC_TPDM_CIDR0__PRMBL_0___M       0x000000FF
#define   DBG_MISC_TPDM_CIDR0__PRMBL_0___S                     0
#define   DBG_MISC_TPDM_CIDR0___M                0x000000FF   
#define   DBG_MISC_TPDM_CIDR0___S                              0

#define DBG_MISC_TPDM_CIDR1                       (0x00BC3FF4)
#define   DBG_MISC_TPDM_CIDR1___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_CIDR1___POR              0x00000090
#define   DBG_MISC_TPDM_CIDR1__CLASS___POR       0x9
#define   DBG_MISC_TPDM_CIDR1__PRMBL_1___POR     0x0
#define   DBG_MISC_TPDM_CIDR1__CLASS___M         0x000000F0
#define   DBG_MISC_TPDM_CIDR1__CLASS___S                       4
#define   DBG_MISC_TPDM_CIDR1__PRMBL_1___M       0x0000000F
#define   DBG_MISC_TPDM_CIDR1__PRMBL_1___S                     0
#define   DBG_MISC_TPDM_CIDR1___M                0x000000FF   
#define   DBG_MISC_TPDM_CIDR1___S                              0

#define DBG_MISC_TPDM_CIDR2                       (0x00BC3FF8)
#define   DBG_MISC_TPDM_CIDR2___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_CIDR2___POR              0x00000005
#define   DBG_MISC_TPDM_CIDR2__PRMBL_2___POR     0x05
#define   DBG_MISC_TPDM_CIDR2__PRMBL_2___M       0x000000FF
#define   DBG_MISC_TPDM_CIDR2__PRMBL_2___S                     0
#define   DBG_MISC_TPDM_CIDR2___M                0x000000FF   
#define   DBG_MISC_TPDM_CIDR2___S                              0

#define DBG_MISC_TPDM_CIDR3                       (0x00BC3FFC)
#define   DBG_MISC_TPDM_CIDR3___RWC                 QCSR_REG_RO    
#define   DBG_MISC_TPDM_CIDR3___POR              0x000000B1
#define   DBG_MISC_TPDM_CIDR3__PRMBL_3___POR     0xB1
#define   DBG_MISC_TPDM_CIDR3__PRMBL_3___M       0x000000FF
#define   DBG_MISC_TPDM_CIDR3__PRMBL_3___S                     0
#define   DBG_MISC_TPDM_CIDR3___M                0x000000FF   
#define   DBG_MISC_TPDM_CIDR3___S                              0

#define DBG_MISC_TPDM_GPRn(n)            (0x00BC3000+0x4*(n))
#define   DBG_MISC_TPDM_GPRn_nMIN  0    
#define   DBG_MISC_TPDM_GPRn_nMAX  2    
#define   DBG_MISC_TPDM_GPRn_ELEM  3    
#define   DBG_MISC_TPDM_GPRn___RWC                  QCSR_REG_RW    
#define   DBG_MISC_TPDM_GPRn___POR               0x00000000
#define   DBG_MISC_TPDM_GPRn__VAL___POR          0x00000000
#define   DBG_MISC_TPDM_GPRn__VAL___M            0xFFFFFFFF
#define   DBG_MISC_TPDM_GPRn__VAL___S                          0
#define   DBG_MISC_TPDM_GPRn___M                 0xFFFFFFFF   
#define   DBG_MISC_TPDM_GPRn___S                               0
#define DBG_MISC_TPDM_GPR0                        (0x00BC3000)
#define   DBG_MISC_TPDM_GPR0___RWC                  QCSR_REG_RW    
#define   DBG_MISC_TPDM_GPR0__VAL___M            0xFFFFFFFF
#define   DBG_MISC_TPDM_GPR0__VAL___S                          0
#define DBG_MISC_TPDM_GPR1                        (0x00BC3004)
#define   DBG_MISC_TPDM_GPR1___RWC                  QCSR_REG_RW    
#define   DBG_MISC_TPDM_GPR1__VAL___M            0xFFFFFFFF
#define   DBG_MISC_TPDM_GPR1__VAL___S                          0
#define DBG_MISC_TPDM_GPR2                        (0x00BC3008)
#define   DBG_MISC_TPDM_GPR2___RWC                  QCSR_REG_RW    
#define   DBG_MISC_TPDM_GPR2__VAL___M            0xFFFFFFFF
#define   DBG_MISC_TPDM_GPR2__VAL___S                          0

#define DBG_TGU_CONTROL                           (0x00BC4000)
#define   DBG_TGU_CONTROL___RWC                     QCSR_REG_RW    
#define   DBG_TGU_CONTROL___POR                  0x00000000
#define   DBG_TGU_CONTROL__FSM_ENABLE___POR      0x0
#define   DBG_TGU_CONTROL__FSM_ENABLE___M        0x00000001
#define   DBG_TGU_CONTROL__FSM_ENABLE___S                      0
#define   DBG_TGU_CONTROL___M                    0x00000001   
#define   DBG_TGU_CONTROL___S                                  0

#define DBG_TIMER0_STATUS                         (0x00BC4004)
#define   DBG_TIMER0_STATUS___RWC                   QCSR_REG_RO    
#define   DBG_TIMER0_STATUS___POR                0x00000000
#define   DBG_TIMER0_STATUS__COUNT___POR         0x0000
#define   DBG_TIMER0_STATUS__COUNT___M           0x0000FFFF
#define   DBG_TIMER0_STATUS__COUNT___S                         0
#define   DBG_TIMER0_STATUS___M                  0x0000FFFF   
#define   DBG_TIMER0_STATUS___S                                0

#define DBG_COUNTER0_STATUS                       (0x00BC400C)
#define   DBG_COUNTER0_STATUS___RWC                 QCSR_REG_RO    
#define   DBG_COUNTER0_STATUS___POR              0x00000000
#define   DBG_COUNTER0_STATUS__COUNT___POR       0x0000
#define   DBG_COUNTER0_STATUS__COUNT___M         0x0000FFFF
#define   DBG_COUNTER0_STATUS__COUNT___S                       0
#define   DBG_COUNTER0_STATUS___M                0x0000FFFF   
#define   DBG_COUNTER0_STATUS___S                              0

#define DBG_TGU_STATUS                            (0x00BC4014)
#define   DBG_TGU_STATUS___RWC                      QCSR_REG_RO    
#define   DBG_TGU_STATUS___POR                   0x00000000
#define   DBG_TGU_STATUS__TRIGGERS___POR         0x0
#define   DBG_TGU_STATUS__CURRENT_STEP___POR     0x0
#define   DBG_TGU_STATUS__FSM_STATE___POR        0x0
#define   DBG_TGU_STATUS__TRIGGERS___M           0x00000F00
#define   DBG_TGU_STATUS__TRIGGERS___S                         8
#define   DBG_TGU_STATUS__CURRENT_STEP___M       0x0000001C
#define   DBG_TGU_STATUS__CURRENT_STEP___S                     2
#define   DBG_TGU_STATUS__FSM_STATE___M          0x00000003
#define   DBG_TGU_STATUS__FSM_STATE___S                        0
#define   DBG_TGU_STATUS___M                     0x00000F1F   
#define   DBG_TGU_STATUS___S                                   0

#define DBG_TIMER0_COMPARE_STEPn(n)      (0x00BC4040+0x1D8*(n))
#define   DBG_TIMER0_COMPARE_STEPn_nMIN 0    
#define   DBG_TIMER0_COMPARE_STEPn_nMAX 7    
#define   DBG_TIMER0_COMPARE_STEPn_ELEM 8    
#define   DBG_TIMER0_COMPARE_STEPn___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEPn___POR         0x00000000
#define   DBG_TIMER0_COMPARE_STEPn__COUNT___POR  0x0000
#define   DBG_TIMER0_COMPARE_STEPn__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEPn__COUNT___S                  0
#define   DBG_TIMER0_COMPARE_STEPn___M           0x0000FFFF   
#define   DBG_TIMER0_COMPARE_STEPn___S                         0
#define DBG_TIMER0_COMPARE_STEP0                  (0x00BC4040)
#define   DBG_TIMER0_COMPARE_STEP0___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP0__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP0__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP1                  (0x00BC4218)
#define   DBG_TIMER0_COMPARE_STEP1___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP1__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP1__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP2                  (0x00BC43F0)
#define   DBG_TIMER0_COMPARE_STEP2___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP2__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP2__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP3                  (0x00BC45C8)
#define   DBG_TIMER0_COMPARE_STEP3___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP3__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP3__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP4                  (0x00BC47A0)
#define   DBG_TIMER0_COMPARE_STEP4___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP4__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP4__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP5                  (0x00BC4978)
#define   DBG_TIMER0_COMPARE_STEP5___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP5__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP5__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP6                  (0x00BC4B50)
#define   DBG_TIMER0_COMPARE_STEP6___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP6__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP6__COUNT___S                  0
#define DBG_TIMER0_COMPARE_STEP7                  (0x00BC4D28)
#define   DBG_TIMER0_COMPARE_STEP7___RWC            QCSR_REG_RW    
#define   DBG_TIMER0_COMPARE_STEP7__COUNT___M    0x0000FFFF
#define   DBG_TIMER0_COMPARE_STEP7__COUNT___S                  0

#define DBG_COUNTER0_COMPARE_STEPn(n)    (0x00BC4048+0x1D8*(n))
#define   DBG_COUNTER0_COMPARE_STEPn_nMIN 0    
#define   DBG_COUNTER0_COMPARE_STEPn_nMAX 7    
#define   DBG_COUNTER0_COMPARE_STEPn_ELEM 8    
#define   DBG_COUNTER0_COMPARE_STEPn___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEPn___POR       0x00000000
#define   DBG_COUNTER0_COMPARE_STEPn__COUNT___POR 0x0000
#define   DBG_COUNTER0_COMPARE_STEPn__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEPn__COUNT___S                0
#define   DBG_COUNTER0_COMPARE_STEPn___M         0x0000FFFF   
#define   DBG_COUNTER0_COMPARE_STEPn___S                       0
#define DBG_COUNTER0_COMPARE_STEP0                (0x00BC4048)
#define   DBG_COUNTER0_COMPARE_STEP0___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP0__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP0__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP1                (0x00BC4220)
#define   DBG_COUNTER0_COMPARE_STEP1___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP1__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP1__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP2                (0x00BC43F8)
#define   DBG_COUNTER0_COMPARE_STEP2___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP2__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP2__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP3                (0x00BC45D0)
#define   DBG_COUNTER0_COMPARE_STEP3___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP3__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP3__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP4                (0x00BC47A8)
#define   DBG_COUNTER0_COMPARE_STEP4___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP4__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP4__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP5                (0x00BC4980)
#define   DBG_COUNTER0_COMPARE_STEP5___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP5__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP5__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP6                (0x00BC4B58)
#define   DBG_COUNTER0_COMPARE_STEP6___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP6__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP6__COUNT___S                0
#define DBG_COUNTER0_COMPARE_STEP7                (0x00BC4D30)
#define   DBG_COUNTER0_COMPARE_STEP7___RWC          QCSR_REG_RW    
#define   DBG_COUNTER0_COMPARE_STEP7__COUNT___M  0x0000FFFF
#define   DBG_COUNTER0_COMPARE_STEP7__COUNT___S                0

#define DBG_CONDITION_DECODEm_STEPn(m,n) (0x00BC4050+0x4*(m)+0x1D8*(n))
#define   DBG_CONDITION_DECODEm_STEPn_mMIN 0    
#define   DBG_CONDITION_DECODEm_STEPn_mMAX 3    
#define   DBG_CONDITION_DECODEm_STEPn_nMIN 0    
#define   DBG_CONDITION_DECODEm_STEPn_nMAX 7    
#define   DBG_CONDITION_DECODEm_STEPn_ELEM 32   
#define   DBG_CONDITION_DECODEm_STEPn___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODEm_STEPn___POR      0x00000000
#define   DBG_CONDITION_DECODEm_STEPn__NOT___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___POR 0x0
#define   DBG_CONDITION_DECODEm_STEPn__NOT___M   0x01000000
#define   DBG_CONDITION_DECODEm_STEPn__NOT___S                24
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___S               0
#define   DBG_CONDITION_DECODEm_STEPn___M        0x0133FFFF   
#define   DBG_CONDITION_DECODEm_STEPn___S                      0
#define DBG_CONDITION_DECODE0_STEP0               (0x00BC4050)
#define   DBG_CONDITION_DECODE0_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP0__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP0__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP0__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP0__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP0__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP0__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP0__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP0__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP0__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP0__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP1               (0x00BC4228)
#define   DBG_CONDITION_DECODE0_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP1__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP1__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP1__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP1__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP1__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP1__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP1__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP1__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP1__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP1__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP2               (0x00BC4400)
#define   DBG_CONDITION_DECODE0_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP2__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP2__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP2__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP2__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP2__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP2__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP2__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP2__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP2__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP2__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP3               (0x00BC45D8)
#define   DBG_CONDITION_DECODE0_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP3__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP3__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP3__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP3__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP3__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP3__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP3__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP3__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP3__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP3__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP4               (0x00BC47B0)
#define   DBG_CONDITION_DECODE0_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP4__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP4__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP4__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP4__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP4__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP4__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP4__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP4__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP4__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP4__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP5               (0x00BC4988)
#define   DBG_CONDITION_DECODE0_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP5__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP5__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP5__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP5__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP5__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP5__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP5__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP5__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP5__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP5__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP6               (0x00BC4B60)
#define   DBG_CONDITION_DECODE0_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP6__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP6__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP6__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP6__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP6__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP6__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP6__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP6__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP6__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP6__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE0_STEP7               (0x00BC4D38)
#define   DBG_CONDITION_DECODE0_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE0_STEP7__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE0_STEP7__NOT___S                24
#define   DBG_CONDITION_DECODE0_STEP7__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE0_STEP7__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE0_STEP7__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE0_STEP7__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE0_STEP7__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE0_STEP7__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE0_STEP7__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE0_STEP7__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP0               (0x00BC4054)
#define   DBG_CONDITION_DECODE1_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP0__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP0__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP0__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP0__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP0__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP0__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP0__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP0__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP0__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP0__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP1               (0x00BC422C)
#define   DBG_CONDITION_DECODE1_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP1__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP1__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP1__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP1__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP1__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP1__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP1__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP1__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP1__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP1__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP2               (0x00BC4404)
#define   DBG_CONDITION_DECODE1_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP2__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP2__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP2__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP2__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP2__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP2__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP2__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP2__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP2__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP2__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP3               (0x00BC45DC)
#define   DBG_CONDITION_DECODE1_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP3__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP3__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP3__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP3__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP3__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP3__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP3__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP3__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP3__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP3__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP4               (0x00BC47B4)
#define   DBG_CONDITION_DECODE1_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP4__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP4__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP4__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP4__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP4__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP4__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP4__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP4__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP4__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP4__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP5               (0x00BC498C)
#define   DBG_CONDITION_DECODE1_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP5__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP5__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP5__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP5__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP5__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP5__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP5__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP5__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP5__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP5__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP6               (0x00BC4B64)
#define   DBG_CONDITION_DECODE1_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP6__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP6__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP6__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP6__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP6__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP6__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP6__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP6__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP6__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP6__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE1_STEP7               (0x00BC4D3C)
#define   DBG_CONDITION_DECODE1_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE1_STEP7__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE1_STEP7__NOT___S                24
#define   DBG_CONDITION_DECODE1_STEP7__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE1_STEP7__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE1_STEP7__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE1_STEP7__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE1_STEP7__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE1_STEP7__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE1_STEP7__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE1_STEP7__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP0               (0x00BC4058)
#define   DBG_CONDITION_DECODE2_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP0__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP0__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP0__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP0__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP0__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP0__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP0__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP0__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP0__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP0__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP1               (0x00BC4230)
#define   DBG_CONDITION_DECODE2_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP1__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP1__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP1__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP1__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP1__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP1__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP1__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP1__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP1__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP1__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP2               (0x00BC4408)
#define   DBG_CONDITION_DECODE2_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP2__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP2__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP2__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP2__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP2__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP2__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP2__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP2__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP2__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP2__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP3               (0x00BC45E0)
#define   DBG_CONDITION_DECODE2_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP3__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP3__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP3__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP3__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP3__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP3__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP3__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP3__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP3__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP3__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP4               (0x00BC47B8)
#define   DBG_CONDITION_DECODE2_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP4__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP4__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP4__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP4__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP4__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP4__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP4__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP4__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP4__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP4__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP5               (0x00BC4990)
#define   DBG_CONDITION_DECODE2_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP5__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP5__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP5__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP5__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP5__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP5__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP5__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP5__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP5__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP5__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP6               (0x00BC4B68)
#define   DBG_CONDITION_DECODE2_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP6__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP6__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP6__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP6__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP6__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP6__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP6__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP6__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP6__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP6__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE2_STEP7               (0x00BC4D40)
#define   DBG_CONDITION_DECODE2_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE2_STEP7__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE2_STEP7__NOT___S                24
#define   DBG_CONDITION_DECODE2_STEP7__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE2_STEP7__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE2_STEP7__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE2_STEP7__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE2_STEP7__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE2_STEP7__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE2_STEP7__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE2_STEP7__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP0               (0x00BC405C)
#define   DBG_CONDITION_DECODE3_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP0__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP0__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP0__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP0__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP0__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP0__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP0__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP0__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP0__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP0__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP1               (0x00BC4234)
#define   DBG_CONDITION_DECODE3_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP1__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP1__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP1__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP1__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP1__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP1__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP1__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP1__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP1__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP1__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP2               (0x00BC440C)
#define   DBG_CONDITION_DECODE3_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP2__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP2__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP2__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP2__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP2__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP2__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP2__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP2__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP2__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP2__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP3               (0x00BC45E4)
#define   DBG_CONDITION_DECODE3_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP3__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP3__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP3__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP3__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP3__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP3__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP3__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP3__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP3__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP3__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP4               (0x00BC47BC)
#define   DBG_CONDITION_DECODE3_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP4__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP4__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP4__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP4__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP4__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP4__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP4__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP4__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP4__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP4__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP5               (0x00BC4994)
#define   DBG_CONDITION_DECODE3_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP5__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP5__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP5__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP5__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP5__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP5__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP5__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP5__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP5__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP5__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP6               (0x00BC4B6C)
#define   DBG_CONDITION_DECODE3_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP6__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP6__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP6__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP6__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP6__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP6__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP6__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP6__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP6__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP6__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_HIGH___S               0
#define DBG_CONDITION_DECODE3_STEP7               (0x00BC4D44)
#define   DBG_CONDITION_DECODE3_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_DECODE3_STEP7__NOT___M   0x01000000
#define   DBG_CONDITION_DECODE3_STEP7__NOT___S                24
#define   DBG_CONDITION_DECODE3_STEP7__BC0_COMP_ACTIVE___M 0x00200000
#define   DBG_CONDITION_DECODE3_STEP7__BC0_COMP_ACTIVE___S              21
#define   DBG_CONDITION_DECODE3_STEP7__BC0_COMP_HIGH___M 0x00100000
#define   DBG_CONDITION_DECODE3_STEP7__BC0_COMP_HIGH___S              20
#define   DBG_CONDITION_DECODE3_STEP7__TC0_COMP_ACTIVE___M 0x00020000
#define   DBG_CONDITION_DECODE3_STEP7__TC0_COMP_ACTIVE___S              17
#define   DBG_CONDITION_DECODE3_STEP7__TC0_COMP_HIGH___M 0x00010000
#define   DBG_CONDITION_DECODE3_STEP7__TC0_COMP_HIGH___S              16
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_ACTIVE___S              15
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_HIGH___M 0x00004000
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_HIGH___S              14
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_ACTIVE___S              13
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_HIGH___M 0x00001000
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_HIGH___S              12
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_ACTIVE___S              11
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_HIGH___M 0x00000400
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_HIGH___S              10
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_ACTIVE___S               9
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_HIGH___M 0x00000100
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_HIGH___S               8
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_ACTIVE___S               7
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_HIGH___M 0x00000040
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_HIGH___S               6
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_ACTIVE___S               5
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_HIGH___M 0x00000010
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_HIGH___S               4
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_ACTIVE___S               3
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_HIGH___M 0x00000004
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_HIGH___S               2
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_ACTIVE___S               1
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_HIGH___M 0x00000001
#define   DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_HIGH___S               0

#define DBG_CONDITION_SELECTm_STEPn(m,n) (0x00BC4060+0x4*(m)+0x1D8*(n))
#define   DBG_CONDITION_SELECTm_STEPn_mMIN 0    
#define   DBG_CONDITION_SELECTm_STEPn_mMAX 3    
#define   DBG_CONDITION_SELECTm_STEPn_nMIN 0    
#define   DBG_CONDITION_SELECTm_STEPn_nMAX 7    
#define   DBG_CONDITION_SELECTm_STEPn_ELEM 32   
#define   DBG_CONDITION_SELECTm_STEPn___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECTm_STEPn___POR      0x00000000
#define   DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__TRIGGER___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__BC0_INC___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__BC0_DEC___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__DONE___POR 0x0
#define   DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECTm_STEPn__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECTm_STEPn__TRIGGER___S              13
#define   DBG_CONDITION_SELECTm_STEPn__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECTm_STEPn__BC0_INC___S               9
#define   DBG_CONDITION_SELECTm_STEPn__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECTm_STEPn__BC0_DEC___S               8
#define   DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECTm_STEPn__DONE___M  0x00000001
#define   DBG_CONDITION_SELECTm_STEPn__DONE___S                0
#define   DBG_CONDITION_SELECTm_STEPn___M        0x000FE38F   
#define   DBG_CONDITION_SELECTm_STEPn___S                      0
#define DBG_CONDITION_SELECT0_STEP0               (0x00BC4060)
#define   DBG_CONDITION_SELECT0_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP0__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP0__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP0__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP0__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP0__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP0__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP0__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP0__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP0__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP0__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP0__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP0__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP0__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP0__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP0__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP0__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP0__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP0__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP1               (0x00BC4238)
#define   DBG_CONDITION_SELECT0_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP1__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP1__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP1__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP1__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP1__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP1__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP1__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP1__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP1__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP1__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP1__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP1__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP1__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP1__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP1__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP1__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP1__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP1__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP2               (0x00BC4410)
#define   DBG_CONDITION_SELECT0_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP2__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP2__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP2__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP2__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP2__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP2__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP2__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP2__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP2__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP2__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP2__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP2__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP2__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP2__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP2__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP2__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP2__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP2__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP3               (0x00BC45E8)
#define   DBG_CONDITION_SELECT0_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP3__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP3__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP3__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP3__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP3__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP3__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP3__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP3__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP3__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP3__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP3__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP3__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP3__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP3__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP3__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP3__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP3__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP3__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP4               (0x00BC47C0)
#define   DBG_CONDITION_SELECT0_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP4__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP4__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP4__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP4__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP4__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP4__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP4__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP4__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP4__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP4__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP4__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP4__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP4__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP4__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP4__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP4__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP4__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP4__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP5               (0x00BC4998)
#define   DBG_CONDITION_SELECT0_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP5__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP5__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP5__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP5__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP5__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP5__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP5__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP5__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP5__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP5__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP5__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP5__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP5__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP5__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP5__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP5__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP5__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP5__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP6               (0x00BC4B70)
#define   DBG_CONDITION_SELECT0_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP6__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP6__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP6__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP6__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP6__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP6__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP6__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP6__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP6__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP6__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP6__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP6__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP6__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP6__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP6__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP6__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP6__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP6__DONE___S                0
#define DBG_CONDITION_SELECT0_STEP7               (0x00BC4D48)
#define   DBG_CONDITION_SELECT0_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT0_STEP7__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT0_STEP7__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT0_STEP7__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT0_STEP7__TRIGGER___S              13
#define   DBG_CONDITION_SELECT0_STEP7__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT0_STEP7__BC0_INC___S               9
#define   DBG_CONDITION_SELECT0_STEP7__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT0_STEP7__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT0_STEP7__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT0_STEP7__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT0_STEP7__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT0_STEP7__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT0_STEP7__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT0_STEP7__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT0_STEP7__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT0_STEP7__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT0_STEP7__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT0_STEP7__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP0               (0x00BC4064)
#define   DBG_CONDITION_SELECT1_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP0__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP0__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP0__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP0__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP0__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP0__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP0__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP0__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP0__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP0__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP0__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP0__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP0__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP0__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP0__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP0__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP0__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP0__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP1               (0x00BC423C)
#define   DBG_CONDITION_SELECT1_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP1__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP1__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP1__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP1__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP1__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP1__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP1__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP1__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP1__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP1__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP1__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP1__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP1__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP1__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP1__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP1__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP1__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP1__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP2               (0x00BC4414)
#define   DBG_CONDITION_SELECT1_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP2__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP2__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP2__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP2__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP2__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP2__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP2__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP2__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP2__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP2__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP2__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP2__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP2__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP2__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP2__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP2__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP2__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP2__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP3               (0x00BC45EC)
#define   DBG_CONDITION_SELECT1_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP3__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP3__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP3__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP3__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP3__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP3__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP3__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP3__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP3__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP3__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP3__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP3__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP3__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP3__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP3__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP3__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP3__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP3__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP4               (0x00BC47C4)
#define   DBG_CONDITION_SELECT1_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP4__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP4__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP4__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP4__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP4__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP4__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP4__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP4__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP4__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP4__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP4__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP4__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP4__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP4__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP4__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP4__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP4__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP4__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP5               (0x00BC499C)
#define   DBG_CONDITION_SELECT1_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP5__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP5__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP5__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP5__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP5__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP5__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP5__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP5__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP5__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP5__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP5__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP5__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP5__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP5__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP5__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP5__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP5__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP5__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP6               (0x00BC4B74)
#define   DBG_CONDITION_SELECT1_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP6__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP6__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP6__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP6__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP6__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP6__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP6__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP6__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP6__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP6__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP6__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP6__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP6__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP6__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP6__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP6__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP6__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP6__DONE___S                0
#define DBG_CONDITION_SELECT1_STEP7               (0x00BC4D4C)
#define   DBG_CONDITION_SELECT1_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT1_STEP7__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT1_STEP7__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT1_STEP7__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT1_STEP7__TRIGGER___S              13
#define   DBG_CONDITION_SELECT1_STEP7__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT1_STEP7__BC0_INC___S               9
#define   DBG_CONDITION_SELECT1_STEP7__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT1_STEP7__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT1_STEP7__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT1_STEP7__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT1_STEP7__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT1_STEP7__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT1_STEP7__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT1_STEP7__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT1_STEP7__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT1_STEP7__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT1_STEP7__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT1_STEP7__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP0               (0x00BC4068)
#define   DBG_CONDITION_SELECT2_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP0__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP0__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP0__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP0__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP0__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP0__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP0__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP0__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP0__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP0__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP0__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP0__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP0__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP0__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP0__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP0__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP0__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP0__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP1               (0x00BC4240)
#define   DBG_CONDITION_SELECT2_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP1__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP1__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP1__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP1__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP1__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP1__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP1__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP1__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP1__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP1__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP1__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP1__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP1__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP1__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP1__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP1__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP1__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP1__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP2               (0x00BC4418)
#define   DBG_CONDITION_SELECT2_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP2__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP2__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP2__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP2__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP2__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP2__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP2__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP2__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP2__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP2__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP2__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP2__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP2__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP2__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP2__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP2__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP2__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP2__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP3               (0x00BC45F0)
#define   DBG_CONDITION_SELECT2_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP3__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP3__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP3__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP3__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP3__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP3__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP3__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP3__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP3__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP3__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP3__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP3__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP3__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP3__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP3__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP3__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP3__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP3__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP4               (0x00BC47C8)
#define   DBG_CONDITION_SELECT2_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP4__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP4__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP4__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP4__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP4__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP4__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP4__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP4__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP4__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP4__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP4__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP4__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP4__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP4__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP4__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP4__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP4__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP4__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP5               (0x00BC49A0)
#define   DBG_CONDITION_SELECT2_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP5__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP5__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP5__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP5__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP5__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP5__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP5__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP5__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP5__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP5__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP5__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP5__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP5__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP5__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP5__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP5__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP5__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP5__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP6               (0x00BC4B78)
#define   DBG_CONDITION_SELECT2_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP6__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP6__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP6__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP6__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP6__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP6__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP6__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP6__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP6__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP6__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP6__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP6__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP6__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP6__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP6__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP6__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP6__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP6__DONE___S                0
#define DBG_CONDITION_SELECT2_STEP7               (0x00BC4D50)
#define   DBG_CONDITION_SELECT2_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT2_STEP7__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT2_STEP7__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT2_STEP7__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT2_STEP7__TRIGGER___S              13
#define   DBG_CONDITION_SELECT2_STEP7__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT2_STEP7__BC0_INC___S               9
#define   DBG_CONDITION_SELECT2_STEP7__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT2_STEP7__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT2_STEP7__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT2_STEP7__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT2_STEP7__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT2_STEP7__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT2_STEP7__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT2_STEP7__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT2_STEP7__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT2_STEP7__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT2_STEP7__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT2_STEP7__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP0               (0x00BC406C)
#define   DBG_CONDITION_SELECT3_STEP0___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP0__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP0__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP0__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP0__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP0__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP0__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP0__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP0__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP0__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP0__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP0__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP0__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP0__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP0__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP0__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP0__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP0__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP0__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP1               (0x00BC4244)
#define   DBG_CONDITION_SELECT3_STEP1___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP1__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP1__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP1__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP1__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP1__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP1__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP1__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP1__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP1__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP1__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP1__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP1__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP1__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP1__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP1__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP1__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP1__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP1__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP2               (0x00BC441C)
#define   DBG_CONDITION_SELECT3_STEP2___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP2__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP2__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP2__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP2__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP2__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP2__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP2__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP2__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP2__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP2__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP2__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP2__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP2__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP2__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP2__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP2__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP2__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP2__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP3               (0x00BC45F4)
#define   DBG_CONDITION_SELECT3_STEP3___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP3__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP3__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP3__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP3__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP3__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP3__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP3__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP3__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP3__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP3__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP3__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP3__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP3__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP3__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP3__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP3__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP3__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP3__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP4               (0x00BC47CC)
#define   DBG_CONDITION_SELECT3_STEP4___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP4__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP4__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP4__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP4__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP4__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP4__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP4__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP4__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP4__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP4__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP4__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP4__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP4__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP4__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP4__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP4__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP4__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP4__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP5               (0x00BC49A4)
#define   DBG_CONDITION_SELECT3_STEP5___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP5__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP5__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP5__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP5__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP5__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP5__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP5__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP5__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP5__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP5__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP5__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP5__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP5__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP5__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP5__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP5__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP5__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP5__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP6               (0x00BC4B7C)
#define   DBG_CONDITION_SELECT3_STEP6___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP6__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP6__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP6__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP6__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP6__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP6__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP6__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP6__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP6__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP6__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP6__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP6__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP6__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP6__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP6__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP6__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP6__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP6__DONE___S                0
#define DBG_CONDITION_SELECT3_STEP7               (0x00BC4D54)
#define   DBG_CONDITION_SELECT3_STEP7___RWC         QCSR_REG_RW    
#define   DBG_CONDITION_SELECT3_STEP7__NEXT_STEP___M 0x000E0000
#define   DBG_CONDITION_SELECT3_STEP7__NEXT_STEP___S              17
#define   DBG_CONDITION_SELECT3_STEP7__TRIGGER___M 0x0001E000
#define   DBG_CONDITION_SELECT3_STEP7__TRIGGER___S              13
#define   DBG_CONDITION_SELECT3_STEP7__BC0_INC___M 0x00000200
#define   DBG_CONDITION_SELECT3_STEP7__BC0_INC___S               9
#define   DBG_CONDITION_SELECT3_STEP7__BC0_DEC___M 0x00000100
#define   DBG_CONDITION_SELECT3_STEP7__BC0_DEC___S               8
#define   DBG_CONDITION_SELECT3_STEP7__BC0_CLEAR___M 0x00000080
#define   DBG_CONDITION_SELECT3_STEP7__BC0_CLEAR___S               7
#define   DBG_CONDITION_SELECT3_STEP7__TC0_ENABLE___M 0x00000008
#define   DBG_CONDITION_SELECT3_STEP7__TC0_ENABLE___S               3
#define   DBG_CONDITION_SELECT3_STEP7__TC0_PAUSE___M 0x00000004
#define   DBG_CONDITION_SELECT3_STEP7__TC0_PAUSE___S               2
#define   DBG_CONDITION_SELECT3_STEP7__TC0_CLEAR___M 0x00000002
#define   DBG_CONDITION_SELECT3_STEP7__TC0_CLEAR___S               1
#define   DBG_CONDITION_SELECT3_STEP7__DONE___M  0x00000001
#define   DBG_CONDITION_SELECT3_STEP7__DONE___S                0

#define DBG_DEFAULT_CONDITION_STEPn(n)   (0x00BC4070+0x1D8*(n))
#define   DBG_DEFAULT_CONDITION_STEPn_nMIN 0    
#define   DBG_DEFAULT_CONDITION_STEPn_nMAX 7    
#define   DBG_DEFAULT_CONDITION_STEPn_ELEM 8    
#define   DBG_DEFAULT_CONDITION_STEPn___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEPn___POR      0x00000000
#define   DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__TRIGGER___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_INC___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__DONE___POR 0x0
#define   DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEPn__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEPn__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEPn__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEPn__DONE___S                0
#define   DBG_DEFAULT_CONDITION_STEPn___M        0x000FE38F   
#define   DBG_DEFAULT_CONDITION_STEPn___S                      0
#define DBG_DEFAULT_CONDITION_STEP0               (0x00BC4070)
#define   DBG_DEFAULT_CONDITION_STEP0___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP0__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP0__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP0__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP0__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP0__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP0__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP0__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP0__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP1               (0x00BC4248)
#define   DBG_DEFAULT_CONDITION_STEP1___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP1__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP1__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP1__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP1__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP1__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP1__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP1__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP1__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP2               (0x00BC4420)
#define   DBG_DEFAULT_CONDITION_STEP2___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP2__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP2__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP2__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP2__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP2__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP2__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP2__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP2__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP3               (0x00BC45F8)
#define   DBG_DEFAULT_CONDITION_STEP3___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP3__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP3__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP3__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP3__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP3__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP3__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP3__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP3__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP4               (0x00BC47D0)
#define   DBG_DEFAULT_CONDITION_STEP4___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP4__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP4__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP4__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP4__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP4__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP4__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP4__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP4__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP5               (0x00BC49A8)
#define   DBG_DEFAULT_CONDITION_STEP5___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP5__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP5__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP5__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP5__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP5__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP5__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP5__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP5__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP6               (0x00BC4B80)
#define   DBG_DEFAULT_CONDITION_STEP6___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP6__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP6__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP6__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP6__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP6__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP6__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP6__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP6__DONE___S                0
#define DBG_DEFAULT_CONDITION_STEP7               (0x00BC4D58)
#define   DBG_DEFAULT_CONDITION_STEP7___RWC         QCSR_REG_RW    
#define   DBG_DEFAULT_CONDITION_STEP7__NEXT_STEP___M 0x000E0000
#define   DBG_DEFAULT_CONDITION_STEP7__NEXT_STEP___S              17
#define   DBG_DEFAULT_CONDITION_STEP7__TRIGGER___M 0x0001E000
#define   DBG_DEFAULT_CONDITION_STEP7__TRIGGER___S              13
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_INC___M 0x00000200
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_INC___S               9
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_DEC___M 0x00000100
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_DEC___S               8
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_CLEAR___M 0x00000080
#define   DBG_DEFAULT_CONDITION_STEP7__BC0_CLEAR___S               7
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_ENABLE___M 0x00000008
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_ENABLE___S               3
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_PAUSE___M 0x00000004
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_PAUSE___S               2
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_CLEAR___M 0x00000002
#define   DBG_DEFAULT_CONDITION_STEP7__TC0_CLEAR___S               1
#define   DBG_DEFAULT_CONDITION_STEP7__DONE___M  0x00000001
#define   DBG_DEFAULT_CONDITION_STEP7__DONE___S                0

#define DBG_GROUP0_REGm_STEPn(m,n)       (0x00BC4074+0x4*(m)+0x1D8*(n))
#define   DBG_GROUP0_REGm_STEPn_mMIN 0    
#define   DBG_GROUP0_REGm_STEPn_mMAX 5    
#define   DBG_GROUP0_REGm_STEPn_nMIN 0    
#define   DBG_GROUP0_REGm_STEPn_nMAX 7    
#define   DBG_GROUP0_REGm_STEPn_ELEM 48   
#define   DBG_GROUP0_REGm_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGm_STEPn___POR            0x00000000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP0_REGm_STEPn___M              0x77777777   
#define   DBG_GROUP0_REGm_STEPn___S                            0
#define DBG_GROUP0_REG0_STEP0                     (0x00BC4074)
#define   DBG_GROUP0_REG0_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP1                     (0x00BC424C)
#define   DBG_GROUP0_REG0_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP2                     (0x00BC4424)
#define   DBG_GROUP0_REG0_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP3                     (0x00BC45FC)
#define   DBG_GROUP0_REG0_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP4                     (0x00BC47D4)
#define   DBG_GROUP0_REG0_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP5                     (0x00BC49AC)
#define   DBG_GROUP0_REG0_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP6                     (0x00BC4B84)
#define   DBG_GROUP0_REG0_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG0_STEP7                     (0x00BC4D5C)
#define   DBG_GROUP0_REG0_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG0_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP0                     (0x00BC4078)
#define   DBG_GROUP0_REG1_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP1                     (0x00BC4250)
#define   DBG_GROUP0_REG1_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP2                     (0x00BC4428)
#define   DBG_GROUP0_REG1_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP3                     (0x00BC4600)
#define   DBG_GROUP0_REG1_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP4                     (0x00BC47D8)
#define   DBG_GROUP0_REG1_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP5                     (0x00BC49B0)
#define   DBG_GROUP0_REG1_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP6                     (0x00BC4B88)
#define   DBG_GROUP0_REG1_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG1_STEP7                     (0x00BC4D60)
#define   DBG_GROUP0_REG1_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG1_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP0                     (0x00BC407C)
#define   DBG_GROUP0_REG2_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP1                     (0x00BC4254)
#define   DBG_GROUP0_REG2_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP2                     (0x00BC442C)
#define   DBG_GROUP0_REG2_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP3                     (0x00BC4604)
#define   DBG_GROUP0_REG2_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP4                     (0x00BC47DC)
#define   DBG_GROUP0_REG2_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP5                     (0x00BC49B4)
#define   DBG_GROUP0_REG2_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP6                     (0x00BC4B8C)
#define   DBG_GROUP0_REG2_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG2_STEP7                     (0x00BC4D64)
#define   DBG_GROUP0_REG2_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG2_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP0                     (0x00BC4080)
#define   DBG_GROUP0_REG3_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP1                     (0x00BC4258)
#define   DBG_GROUP0_REG3_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP2                     (0x00BC4430)
#define   DBG_GROUP0_REG3_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP3                     (0x00BC4608)
#define   DBG_GROUP0_REG3_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP4                     (0x00BC47E0)
#define   DBG_GROUP0_REG3_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP5                     (0x00BC49B8)
#define   DBG_GROUP0_REG3_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP6                     (0x00BC4B90)
#define   DBG_GROUP0_REG3_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG3_STEP7                     (0x00BC4D68)
#define   DBG_GROUP0_REG3_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG3_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP0                     (0x00BC4084)
#define   DBG_GROUP0_REG4_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP1                     (0x00BC425C)
#define   DBG_GROUP0_REG4_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP2                     (0x00BC4434)
#define   DBG_GROUP0_REG4_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP3                     (0x00BC460C)
#define   DBG_GROUP0_REG4_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP4                     (0x00BC47E4)
#define   DBG_GROUP0_REG4_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP5                     (0x00BC49BC)
#define   DBG_GROUP0_REG4_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP6                     (0x00BC4B94)
#define   DBG_GROUP0_REG4_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG4_STEP7                     (0x00BC4D6C)
#define   DBG_GROUP0_REG4_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG4_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP0                     (0x00BC4088)
#define   DBG_GROUP0_REG5_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP1                     (0x00BC4260)
#define   DBG_GROUP0_REG5_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP2                     (0x00BC4438)
#define   DBG_GROUP0_REG5_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP3                     (0x00BC4610)
#define   DBG_GROUP0_REG5_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP4                     (0x00BC47E8)
#define   DBG_GROUP0_REG5_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP5                     (0x00BC49C0)
#define   DBG_GROUP0_REG5_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP6                     (0x00BC4B98)
#define   DBG_GROUP0_REG5_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REG5_STEP7                     (0x00BC4D70)
#define   DBG_GROUP0_REG5_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REG5_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP0_REGN_STEPn(n)         (0x00BC408C+0x1D8*(n))
#define   DBG_GROUP0_REGN_STEPn_nMIN 0    
#define   DBG_GROUP0_REGN_STEPn_nMAX 7    
#define   DBG_GROUP0_REGN_STEPn_ELEM 8    
#define   DBG_GROUP0_REGN_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEPn___POR            0x00000000
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP0_REGN_STEPn___M              0x00000077   
#define   DBG_GROUP0_REGN_STEPn___S                            0
#define DBG_GROUP0_REGN_STEP0                     (0x00BC408C)
#define   DBG_GROUP0_REGN_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP1                     (0x00BC4264)
#define   DBG_GROUP0_REGN_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP2                     (0x00BC443C)
#define   DBG_GROUP0_REGN_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP3                     (0x00BC4614)
#define   DBG_GROUP0_REGN_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP4                     (0x00BC47EC)
#define   DBG_GROUP0_REGN_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP5                     (0x00BC49C4)
#define   DBG_GROUP0_REGN_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP6                     (0x00BC4B9C)
#define   DBG_GROUP0_REGN_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP0_REGN_STEP7                     (0x00BC4D74)
#define   DBG_GROUP0_REGN_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP0_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP0_REGN_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP0_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP0_REGN_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP1_REGm_STEPn(m,n)       (0x00BC40D4+0x4*(m)+0x1D8*(n))
#define   DBG_GROUP1_REGm_STEPn_mMIN 0    
#define   DBG_GROUP1_REGm_STEPn_mMAX 5    
#define   DBG_GROUP1_REGm_STEPn_nMIN 0    
#define   DBG_GROUP1_REGm_STEPn_nMAX 7    
#define   DBG_GROUP1_REGm_STEPn_ELEM 48   
#define   DBG_GROUP1_REGm_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGm_STEPn___POR            0x00000000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP1_REGm_STEPn___M              0x77777777   
#define   DBG_GROUP1_REGm_STEPn___S                            0
#define DBG_GROUP1_REG0_STEP0                     (0x00BC40D4)
#define   DBG_GROUP1_REG0_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP1                     (0x00BC42AC)
#define   DBG_GROUP1_REG0_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP2                     (0x00BC4484)
#define   DBG_GROUP1_REG0_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP3                     (0x00BC465C)
#define   DBG_GROUP1_REG0_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP4                     (0x00BC4834)
#define   DBG_GROUP1_REG0_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP5                     (0x00BC4A0C)
#define   DBG_GROUP1_REG0_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP6                     (0x00BC4BE4)
#define   DBG_GROUP1_REG0_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG0_STEP7                     (0x00BC4DBC)
#define   DBG_GROUP1_REG0_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG0_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP0                     (0x00BC40D8)
#define   DBG_GROUP1_REG1_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP1                     (0x00BC42B0)
#define   DBG_GROUP1_REG1_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP2                     (0x00BC4488)
#define   DBG_GROUP1_REG1_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP3                     (0x00BC4660)
#define   DBG_GROUP1_REG1_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP4                     (0x00BC4838)
#define   DBG_GROUP1_REG1_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP5                     (0x00BC4A10)
#define   DBG_GROUP1_REG1_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP6                     (0x00BC4BE8)
#define   DBG_GROUP1_REG1_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG1_STEP7                     (0x00BC4DC0)
#define   DBG_GROUP1_REG1_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG1_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP0                     (0x00BC40DC)
#define   DBG_GROUP1_REG2_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP1                     (0x00BC42B4)
#define   DBG_GROUP1_REG2_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP2                     (0x00BC448C)
#define   DBG_GROUP1_REG2_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP3                     (0x00BC4664)
#define   DBG_GROUP1_REG2_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP4                     (0x00BC483C)
#define   DBG_GROUP1_REG2_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP5                     (0x00BC4A14)
#define   DBG_GROUP1_REG2_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP6                     (0x00BC4BEC)
#define   DBG_GROUP1_REG2_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG2_STEP7                     (0x00BC4DC4)
#define   DBG_GROUP1_REG2_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG2_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP0                     (0x00BC40E0)
#define   DBG_GROUP1_REG3_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP1                     (0x00BC42B8)
#define   DBG_GROUP1_REG3_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP2                     (0x00BC4490)
#define   DBG_GROUP1_REG3_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP3                     (0x00BC4668)
#define   DBG_GROUP1_REG3_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP4                     (0x00BC4840)
#define   DBG_GROUP1_REG3_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP5                     (0x00BC4A18)
#define   DBG_GROUP1_REG3_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP6                     (0x00BC4BF0)
#define   DBG_GROUP1_REG3_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG3_STEP7                     (0x00BC4DC8)
#define   DBG_GROUP1_REG3_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG3_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP0                     (0x00BC40E4)
#define   DBG_GROUP1_REG4_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP1                     (0x00BC42BC)
#define   DBG_GROUP1_REG4_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP2                     (0x00BC4494)
#define   DBG_GROUP1_REG4_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP3                     (0x00BC466C)
#define   DBG_GROUP1_REG4_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP4                     (0x00BC4844)
#define   DBG_GROUP1_REG4_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP5                     (0x00BC4A1C)
#define   DBG_GROUP1_REG4_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP6                     (0x00BC4BF4)
#define   DBG_GROUP1_REG4_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG4_STEP7                     (0x00BC4DCC)
#define   DBG_GROUP1_REG4_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG4_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP0                     (0x00BC40E8)
#define   DBG_GROUP1_REG5_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP1                     (0x00BC42C0)
#define   DBG_GROUP1_REG5_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP2                     (0x00BC4498)
#define   DBG_GROUP1_REG5_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP3                     (0x00BC4670)
#define   DBG_GROUP1_REG5_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP4                     (0x00BC4848)
#define   DBG_GROUP1_REG5_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP5                     (0x00BC4A20)
#define   DBG_GROUP1_REG5_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP6                     (0x00BC4BF8)
#define   DBG_GROUP1_REG5_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REG5_STEP7                     (0x00BC4DD0)
#define   DBG_GROUP1_REG5_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REG5_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP1_REGN_STEPn(n)         (0x00BC40EC+0x1D8*(n))
#define   DBG_GROUP1_REGN_STEPn_nMIN 0    
#define   DBG_GROUP1_REGN_STEPn_nMAX 7    
#define   DBG_GROUP1_REGN_STEPn_ELEM 8    
#define   DBG_GROUP1_REGN_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEPn___POR            0x00000000
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP1_REGN_STEPn___M              0x00000077   
#define   DBG_GROUP1_REGN_STEPn___S                            0
#define DBG_GROUP1_REGN_STEP0                     (0x00BC40EC)
#define   DBG_GROUP1_REGN_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP1                     (0x00BC42C4)
#define   DBG_GROUP1_REGN_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP2                     (0x00BC449C)
#define   DBG_GROUP1_REGN_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP3                     (0x00BC4674)
#define   DBG_GROUP1_REGN_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP4                     (0x00BC484C)
#define   DBG_GROUP1_REGN_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP5                     (0x00BC4A24)
#define   DBG_GROUP1_REGN_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP6                     (0x00BC4BFC)
#define   DBG_GROUP1_REGN_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP1_REGN_STEP7                     (0x00BC4DD4)
#define   DBG_GROUP1_REGN_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP1_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP1_REGN_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP1_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP1_REGN_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP2_REGm_STEPn(m,n)       (0x00BC4134+0x4*(m)+0x1D8*(n))
#define   DBG_GROUP2_REGm_STEPn_mMIN 0    
#define   DBG_GROUP2_REGm_STEPn_mMAX 5    
#define   DBG_GROUP2_REGm_STEPn_nMIN 0    
#define   DBG_GROUP2_REGm_STEPn_nMAX 7    
#define   DBG_GROUP2_REGm_STEPn_ELEM 48   
#define   DBG_GROUP2_REGm_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGm_STEPn___POR            0x00000000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP2_REGm_STEPn___M              0x77777777   
#define   DBG_GROUP2_REGm_STEPn___S                            0
#define DBG_GROUP2_REG0_STEP0                     (0x00BC4134)
#define   DBG_GROUP2_REG0_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP1                     (0x00BC430C)
#define   DBG_GROUP2_REG0_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP2                     (0x00BC44E4)
#define   DBG_GROUP2_REG0_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP3                     (0x00BC46BC)
#define   DBG_GROUP2_REG0_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP4                     (0x00BC4894)
#define   DBG_GROUP2_REG0_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP5                     (0x00BC4A6C)
#define   DBG_GROUP2_REG0_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP6                     (0x00BC4C44)
#define   DBG_GROUP2_REG0_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG0_STEP7                     (0x00BC4E1C)
#define   DBG_GROUP2_REG0_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG0_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP0                     (0x00BC4138)
#define   DBG_GROUP2_REG1_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP1                     (0x00BC4310)
#define   DBG_GROUP2_REG1_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP2                     (0x00BC44E8)
#define   DBG_GROUP2_REG1_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP3                     (0x00BC46C0)
#define   DBG_GROUP2_REG1_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP4                     (0x00BC4898)
#define   DBG_GROUP2_REG1_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP5                     (0x00BC4A70)
#define   DBG_GROUP2_REG1_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP6                     (0x00BC4C48)
#define   DBG_GROUP2_REG1_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG1_STEP7                     (0x00BC4E20)
#define   DBG_GROUP2_REG1_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG1_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP0                     (0x00BC413C)
#define   DBG_GROUP2_REG2_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP1                     (0x00BC4314)
#define   DBG_GROUP2_REG2_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP2                     (0x00BC44EC)
#define   DBG_GROUP2_REG2_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP3                     (0x00BC46C4)
#define   DBG_GROUP2_REG2_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP4                     (0x00BC489C)
#define   DBG_GROUP2_REG2_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP5                     (0x00BC4A74)
#define   DBG_GROUP2_REG2_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP6                     (0x00BC4C4C)
#define   DBG_GROUP2_REG2_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG2_STEP7                     (0x00BC4E24)
#define   DBG_GROUP2_REG2_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG2_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP0                     (0x00BC4140)
#define   DBG_GROUP2_REG3_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP1                     (0x00BC4318)
#define   DBG_GROUP2_REG3_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP2                     (0x00BC44F0)
#define   DBG_GROUP2_REG3_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP3                     (0x00BC46C8)
#define   DBG_GROUP2_REG3_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP4                     (0x00BC48A0)
#define   DBG_GROUP2_REG3_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP5                     (0x00BC4A78)
#define   DBG_GROUP2_REG3_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP6                     (0x00BC4C50)
#define   DBG_GROUP2_REG3_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG3_STEP7                     (0x00BC4E28)
#define   DBG_GROUP2_REG3_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG3_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP0                     (0x00BC4144)
#define   DBG_GROUP2_REG4_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP1                     (0x00BC431C)
#define   DBG_GROUP2_REG4_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP2                     (0x00BC44F4)
#define   DBG_GROUP2_REG4_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP3                     (0x00BC46CC)
#define   DBG_GROUP2_REG4_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP4                     (0x00BC48A4)
#define   DBG_GROUP2_REG4_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP5                     (0x00BC4A7C)
#define   DBG_GROUP2_REG4_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP6                     (0x00BC4C54)
#define   DBG_GROUP2_REG4_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG4_STEP7                     (0x00BC4E2C)
#define   DBG_GROUP2_REG4_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG4_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP0                     (0x00BC4148)
#define   DBG_GROUP2_REG5_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP1                     (0x00BC4320)
#define   DBG_GROUP2_REG5_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP2                     (0x00BC44F8)
#define   DBG_GROUP2_REG5_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP3                     (0x00BC46D0)
#define   DBG_GROUP2_REG5_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP4                     (0x00BC48A8)
#define   DBG_GROUP2_REG5_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP5                     (0x00BC4A80)
#define   DBG_GROUP2_REG5_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP6                     (0x00BC4C58)
#define   DBG_GROUP2_REG5_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REG5_STEP7                     (0x00BC4E30)
#define   DBG_GROUP2_REG5_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REG5_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP2_REGN_STEPn(n)         (0x00BC414C+0x1D8*(n))
#define   DBG_GROUP2_REGN_STEPn_nMIN 0    
#define   DBG_GROUP2_REGN_STEPn_nMAX 7    
#define   DBG_GROUP2_REGN_STEPn_ELEM 8    
#define   DBG_GROUP2_REGN_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEPn___POR            0x00000000
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP2_REGN_STEPn___M              0x00000077   
#define   DBG_GROUP2_REGN_STEPn___S                            0
#define DBG_GROUP2_REGN_STEP0                     (0x00BC414C)
#define   DBG_GROUP2_REGN_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP1                     (0x00BC4324)
#define   DBG_GROUP2_REGN_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP2                     (0x00BC44FC)
#define   DBG_GROUP2_REGN_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP3                     (0x00BC46D4)
#define   DBG_GROUP2_REGN_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP4                     (0x00BC48AC)
#define   DBG_GROUP2_REGN_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP5                     (0x00BC4A84)
#define   DBG_GROUP2_REGN_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP6                     (0x00BC4C5C)
#define   DBG_GROUP2_REGN_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP2_REGN_STEP7                     (0x00BC4E34)
#define   DBG_GROUP2_REGN_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP2_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP2_REGN_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP2_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP2_REGN_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP3_REGm_STEPn(m,n)       (0x00BC4194+0x4*(m)+0x1D8*(n))
#define   DBG_GROUP3_REGm_STEPn_mMIN 0    
#define   DBG_GROUP3_REGm_STEPn_mMAX 5    
#define   DBG_GROUP3_REGm_STEPn_nMIN 0    
#define   DBG_GROUP3_REGm_STEPn_nMAX 7    
#define   DBG_GROUP3_REGm_STEPn_ELEM 48   
#define   DBG_GROUP3_REGm_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGm_STEPn___POR            0x00000000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP3_REGm_STEPn___M              0x77777777   
#define   DBG_GROUP3_REGm_STEPn___S                            0
#define DBG_GROUP3_REG0_STEP0                     (0x00BC4194)
#define   DBG_GROUP3_REG0_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP1                     (0x00BC436C)
#define   DBG_GROUP3_REG0_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP2                     (0x00BC4544)
#define   DBG_GROUP3_REG0_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP3                     (0x00BC471C)
#define   DBG_GROUP3_REG0_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP4                     (0x00BC48F4)
#define   DBG_GROUP3_REG0_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP5                     (0x00BC4ACC)
#define   DBG_GROUP3_REG0_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP6                     (0x00BC4CA4)
#define   DBG_GROUP3_REG0_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG0_STEP7                     (0x00BC4E7C)
#define   DBG_GROUP3_REG0_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG0_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP0                     (0x00BC4198)
#define   DBG_GROUP3_REG1_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP1                     (0x00BC4370)
#define   DBG_GROUP3_REG1_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP2                     (0x00BC4548)
#define   DBG_GROUP3_REG1_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP3                     (0x00BC4720)
#define   DBG_GROUP3_REG1_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP4                     (0x00BC48F8)
#define   DBG_GROUP3_REG1_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP5                     (0x00BC4AD0)
#define   DBG_GROUP3_REG1_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP6                     (0x00BC4CA8)
#define   DBG_GROUP3_REG1_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG1_STEP7                     (0x00BC4E80)
#define   DBG_GROUP3_REG1_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG1_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP0                     (0x00BC419C)
#define   DBG_GROUP3_REG2_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP1                     (0x00BC4374)
#define   DBG_GROUP3_REG2_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP2                     (0x00BC454C)
#define   DBG_GROUP3_REG2_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP3                     (0x00BC4724)
#define   DBG_GROUP3_REG2_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP4                     (0x00BC48FC)
#define   DBG_GROUP3_REG2_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP5                     (0x00BC4AD4)
#define   DBG_GROUP3_REG2_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP6                     (0x00BC4CAC)
#define   DBG_GROUP3_REG2_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG2_STEP7                     (0x00BC4E84)
#define   DBG_GROUP3_REG2_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG2_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP0                     (0x00BC41A0)
#define   DBG_GROUP3_REG3_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP1                     (0x00BC4378)
#define   DBG_GROUP3_REG3_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP2                     (0x00BC4550)
#define   DBG_GROUP3_REG3_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP3                     (0x00BC4728)
#define   DBG_GROUP3_REG3_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP4                     (0x00BC4900)
#define   DBG_GROUP3_REG3_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP5                     (0x00BC4AD8)
#define   DBG_GROUP3_REG3_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP6                     (0x00BC4CB0)
#define   DBG_GROUP3_REG3_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG3_STEP7                     (0x00BC4E88)
#define   DBG_GROUP3_REG3_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG3_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP0                     (0x00BC41A4)
#define   DBG_GROUP3_REG4_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP1                     (0x00BC437C)
#define   DBG_GROUP3_REG4_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP2                     (0x00BC4554)
#define   DBG_GROUP3_REG4_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP3                     (0x00BC472C)
#define   DBG_GROUP3_REG4_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP4                     (0x00BC4904)
#define   DBG_GROUP3_REG4_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP5                     (0x00BC4ADC)
#define   DBG_GROUP3_REG4_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP6                     (0x00BC4CB4)
#define   DBG_GROUP3_REG4_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG4_STEP7                     (0x00BC4E8C)
#define   DBG_GROUP3_REG4_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG4_STEP7__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP0                     (0x00BC41A8)
#define   DBG_GROUP3_REG5_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP1                     (0x00BC4380)
#define   DBG_GROUP3_REG5_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP2                     (0x00BC4558)
#define   DBG_GROUP3_REG5_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP3                     (0x00BC4730)
#define   DBG_GROUP3_REG5_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP4                     (0x00BC4908)
#define   DBG_GROUP3_REG5_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP5                     (0x00BC4AE0)
#define   DBG_GROUP3_REG5_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP6                     (0x00BC4CB8)
#define   DBG_GROUP3_REG5_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REG5_STEP7                     (0x00BC4E90)
#define   DBG_GROUP3_REG5_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT7_TYPE3___S              28
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT6_TYPE3___S              24
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT5_TYPE3___S              20
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT4_TYPE3___S              16
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT3_TYPE3___S              12
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT2_TYPE3___S               8
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REG5_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_GROUP3_REGN_STEPn(n)         (0x00BC41AC+0x1D8*(n))
#define   DBG_GROUP3_REGN_STEPn_nMIN 0    
#define   DBG_GROUP3_REGN_STEPn_nMAX 7    
#define   DBG_GROUP3_REGN_STEPn_ELEM 8    
#define   DBG_GROUP3_REGN_STEPn___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEPn___POR            0x00000000
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___S               0
#define   DBG_GROUP3_REGN_STEPn___M              0x00000077   
#define   DBG_GROUP3_REGN_STEPn___S                            0
#define DBG_GROUP3_REGN_STEP0                     (0x00BC41AC)
#define   DBG_GROUP3_REGN_STEP0___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP0__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP0__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP1                     (0x00BC4384)
#define   DBG_GROUP3_REGN_STEP1___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP1__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP1__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP2                     (0x00BC455C)
#define   DBG_GROUP3_REGN_STEP2___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP2__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP2__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP3                     (0x00BC4734)
#define   DBG_GROUP3_REGN_STEP3___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP3__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP3__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP4                     (0x00BC490C)
#define   DBG_GROUP3_REGN_STEP4___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP4__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP4__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP5                     (0x00BC4AE4)
#define   DBG_GROUP3_REGN_STEP5___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP5__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP5__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP6                     (0x00BC4CBC)
#define   DBG_GROUP3_REGN_STEP6___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP6__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP6__SEL_BIT0_TYPE3___S               0
#define DBG_GROUP3_REGN_STEP7                     (0x00BC4E94)
#define   DBG_GROUP3_REGN_STEP7___RWC               QCSR_REG_RW    
#define   DBG_GROUP3_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070
#define   DBG_GROUP3_REGN_STEP7__SEL_BIT1_TYPE3___S               4
#define   DBG_GROUP3_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007
#define   DBG_GROUP3_REGN_STEP7__SEL_BIT0_TYPE3___S               0

#define DBG_TGU_ITATBCNTRL                        (0x00BC4EF0)
#define   DBG_TGU_ITATBCNTRL___RWC                  QCSR_REG_RW    
#define   DBG_TGU_ITATBCNTRL___POR               0x00000000
#define   DBG_TGU_ITATBCNTRL__TSREQ___POR        0x0
#define   DBG_TGU_ITATBCNTRL__ATVALID___POR      0x0
#define   DBG_TGU_ITATBCNTRL__ATDATAMODE___POR   0x0
#define   DBG_TGU_ITATBCNTRL__ATBYTES___POR      0x0
#define   DBG_TGU_ITATBCNTRL__ATDATA___POR       0x00
#define   DBG_TGU_ITATBCNTRL__ATID___POR         0x00
#define   DBG_TGU_ITATBCNTRL__TSVAL___POR        0x0
#define   DBG_TGU_ITATBCNTRL__TSREQ___M          0x80000000
#define   DBG_TGU_ITATBCNTRL__TSREQ___S                       31
#define   DBG_TGU_ITATBCNTRL__ATVALID___M        0x40000000
#define   DBG_TGU_ITATBCNTRL__ATVALID___S                     30
#define   DBG_TGU_ITATBCNTRL__ATDATAMODE___M     0x00400000
#define   DBG_TGU_ITATBCNTRL__ATDATAMODE___S                  22
#define   DBG_TGU_ITATBCNTRL__ATBYTES___M        0x003C0000
#define   DBG_TGU_ITATBCNTRL__ATBYTES___S                     18
#define   DBG_TGU_ITATBCNTRL__ATDATA___M         0x0003FC00
#define   DBG_TGU_ITATBCNTRL__ATDATA___S                      10
#define   DBG_TGU_ITATBCNTRL__ATID___M           0x000003F8
#define   DBG_TGU_ITATBCNTRL__ATID___S                         3
#define   DBG_TGU_ITATBCNTRL__TSVAL___M          0x00000007
#define   DBG_TGU_ITATBCNTRL__TSVAL___S                        0
#define   DBG_TGU_ITATBCNTRL___M                 0xC07FFFFF   
#define   DBG_TGU_ITATBCNTRL___S                               0

#define DBG_TGU_ITCNTRL                           (0x00BC4F00)
#define   DBG_TGU_ITCNTRL___RWC                     QCSR_REG_RW    
#define   DBG_TGU_ITCNTRL___POR                  0x00000000
#define   DBG_TGU_ITCNTRL__IME___POR             0x0
#define   DBG_TGU_ITCNTRL__IME___M               0x00000001
#define   DBG_TGU_ITCNTRL__IME___S                             0
#define   DBG_TGU_ITCNTRL___M                    0x00000001   
#define   DBG_TGU_ITCNTRL___S                                  0

#define DBG_TGU_CLAIMSET                          (0x00BC4FA0)
#define   DBG_TGU_CLAIMSET___RWC                    QCSR_REG_RO    
#define   DBG_TGU_CLAIMSET___POR                 0x00000000
#define   DBG_TGU_CLAIMSET__VAL_SET___POR        0x00000000
#define   DBG_TGU_CLAIMSET__VAL_SET___M          0xFFFFFFFF
#define   DBG_TGU_CLAIMSET__VAL_SET___S                        0
#define   DBG_TGU_CLAIMSET___M                   0xFFFFFFFF   
#define   DBG_TGU_CLAIMSET___S                                 0

#define DBG_TGU_CLAIMCLR                          (0x00BC4FA4)
#define   DBG_TGU_CLAIMCLR___RWC                    QCSR_REG_RO    
#define   DBG_TGU_CLAIMCLR___POR                 0x00000000
#define   DBG_TGU_CLAIMCLR__VAL_CLR___POR        0x00000000
#define   DBG_TGU_CLAIMCLR__VAL_CLR___M          0xFFFFFFFF
#define   DBG_TGU_CLAIMCLR__VAL_CLR___S                        0
#define   DBG_TGU_CLAIMCLR___M                   0xFFFFFFFF   
#define   DBG_TGU_CLAIMCLR___S                                 0

#define DBG_TGU_DEVAFF0                           (0x00BC4FA8)
#define   DBG_TGU_DEVAFF0___RWC                     QCSR_REG_RO    
#define   DBG_TGU_DEVAFF0___POR                  0x00000000
#define   DBG_TGU_DEVAFF0__VAL___POR             0x00000000
#define   DBG_TGU_DEVAFF0__VAL___M               0xFFFFFFFF
#define   DBG_TGU_DEVAFF0__VAL___S                             0
#define   DBG_TGU_DEVAFF0___M                    0xFFFFFFFF   
#define   DBG_TGU_DEVAFF0___S                                  0

#define DBG_TGU_DEVAFF1                           (0x00BC4FAC)
#define   DBG_TGU_DEVAFF1___RWC                     QCSR_REG_RO    
#define   DBG_TGU_DEVAFF1___POR                  0x00000000
#define   DBG_TGU_DEVAFF1__VAL___POR             0x00000000
#define   DBG_TGU_DEVAFF1__VAL___M               0xFFFFFFFF
#define   DBG_TGU_DEVAFF1__VAL___S                             0
#define   DBG_TGU_DEVAFF1___M                    0xFFFFFFFF   
#define   DBG_TGU_DEVAFF1___S                                  0

#define DBG_TGU_LAR                               (0x00BC4FB0)
#define   DBG_TGU_LAR___RWC                         QCSR_REG_RW    
#define   DBG_TGU_LAR___POR                      0x00000000
#define   DBG_TGU_LAR__KEY___POR                 0x00000000
#define   DBG_TGU_LAR__KEY___M                   0xFFFFFFFF
#define   DBG_TGU_LAR__KEY___S                                 0
#define   DBG_TGU_LAR___M                        0xFFFFFFFF   
#define   DBG_TGU_LAR___S                                      0

#define DBG_TGU_LSR                               (0x00BC4FB4)
#define   DBG_TGU_LSR___RWC                         QCSR_REG_RO    
#define   DBG_TGU_LSR___POR                      0x00000003
#define   DBG_TGU_LSR__NTT___POR                 0x0
#define   DBG_TGU_LSR__SLK___POR                 0x1
#define   DBG_TGU_LSR__SLI___POR                 0x1
#define   DBG_TGU_LSR__NTT___M                   0x00000004
#define   DBG_TGU_LSR__NTT___S                                 2
#define   DBG_TGU_LSR__SLK___M                   0x00000002
#define   DBG_TGU_LSR__SLK___S                                 1
#define   DBG_TGU_LSR__SLI___M                   0x00000001
#define   DBG_TGU_LSR__SLI___S                                 0
#define   DBG_TGU_LSR___M                        0x00000007   
#define   DBG_TGU_LSR___S                                      0

#define DBG_TGU_AUTHSTATUS                        (0x00BC4FB8)
#define   DBG_TGU_AUTHSTATUS___RWC                  QCSR_REG_RO    
#define   DBG_TGU_AUTHSTATUS___POR               0x000000AA
#define   DBG_TGU_AUTHSTATUS__SNID___POR         0x2
#define   DBG_TGU_AUTHSTATUS__SID___POR          0x2
#define   DBG_TGU_AUTHSTATUS__NSNID___POR        0x2
#define   DBG_TGU_AUTHSTATUS__NSID___POR         0x2
#define   DBG_TGU_AUTHSTATUS__SNID___M           0x000000C0
#define   DBG_TGU_AUTHSTATUS__SNID___S                         6
#define   DBG_TGU_AUTHSTATUS__SID___M            0x00000030
#define   DBG_TGU_AUTHSTATUS__SID___S                          4
#define   DBG_TGU_AUTHSTATUS__NSNID___M          0x0000000C
#define   DBG_TGU_AUTHSTATUS__NSNID___S                        2
#define   DBG_TGU_AUTHSTATUS__NSID___M           0x00000003
#define   DBG_TGU_AUTHSTATUS__NSID___S                         0
#define   DBG_TGU_AUTHSTATUS___M                 0x000000FF   
#define   DBG_TGU_AUTHSTATUS___S                               0

#define DBG_TGU_DEVARCH                           (0x00BC4FBC)
#define   DBG_TGU_DEVARCH___RWC                     QCSR_REG_RO    
#define   DBG_TGU_DEVARCH___POR                  0x0E105CDA
#define   DBG_TGU_DEVARCH__ARCHITECT___POR       0x070
#define   DBG_TGU_DEVARCH__PRESENT___POR         0x1
#define   DBG_TGU_DEVARCH__REVISION___POR        0x0
#define   DBG_TGU_DEVARCH__ARCHID___POR          0x5CDA
#define   DBG_TGU_DEVARCH__ARCHITECT___M         0xFFE00000
#define   DBG_TGU_DEVARCH__ARCHITECT___S                      21
#define   DBG_TGU_DEVARCH__PRESENT___M           0x00100000
#define   DBG_TGU_DEVARCH__PRESENT___S                        20
#define   DBG_TGU_DEVARCH__REVISION___M          0x000F0000
#define   DBG_TGU_DEVARCH__REVISION___S                       16
#define   DBG_TGU_DEVARCH__ARCHID___M            0x0000FFFF
#define   DBG_TGU_DEVARCH__ARCHID___S                          0
#define   DBG_TGU_DEVARCH___M                    0xFFFFFFFF   
#define   DBG_TGU_DEVARCH___S                                  0

#define DBG_TGU_DEVID2                            (0x00BC4FC0)
#define   DBG_TGU_DEVID2___RWC                      QCSR_REG_RO    
#define   DBG_TGU_DEVID2___POR                   0xFF400400
#define   DBG_TGU_DEVID2__GROUP0_TYPE___POR      0x3
#define   DBG_TGU_DEVID2__GROUP1_TYPE___POR      0x3
#define   DBG_TGU_DEVID2__GROUP2_TYPE___POR      0x3
#define   DBG_TGU_DEVID2__GROUP3_TYPE___POR      0x3
#define   DBG_TGU_DEVID2__WIDTH_TC0___POR        0x10
#define   DBG_TGU_DEVID2__WIDTH_TC1___POR        0x0
#define   DBG_TGU_DEVID2__WIDTH_BC0___POR        0x10
#define   DBG_TGU_DEVID2__WIDTH_BC1___POR        0x0
#define   DBG_TGU_DEVID2__GROUP0_TYPE___M        0xC0000000
#define   DBG_TGU_DEVID2__GROUP0_TYPE___S                     30
#define   DBG_TGU_DEVID2__GROUP1_TYPE___M        0x30000000
#define   DBG_TGU_DEVID2__GROUP1_TYPE___S                     28
#define   DBG_TGU_DEVID2__GROUP2_TYPE___M        0x0C000000
#define   DBG_TGU_DEVID2__GROUP2_TYPE___S                     26
#define   DBG_TGU_DEVID2__GROUP3_TYPE___M        0x03000000
#define   DBG_TGU_DEVID2__GROUP3_TYPE___S                     24
#define   DBG_TGU_DEVID2__WIDTH_TC0___M          0x00FC0000
#define   DBG_TGU_DEVID2__WIDTH_TC0___S                       18
#define   DBG_TGU_DEVID2__WIDTH_TC1___M          0x0003E000
#define   DBG_TGU_DEVID2__WIDTH_TC1___S                       13
#define   DBG_TGU_DEVID2__WIDTH_BC0___M          0x00000FC0
#define   DBG_TGU_DEVID2__WIDTH_BC0___S                        6
#define   DBG_TGU_DEVID2__WIDTH_BC1___M          0x0000003F
#define   DBG_TGU_DEVID2__WIDTH_BC1___S                        0
#define   DBG_TGU_DEVID2___M                     0xFFFFEFFF   
#define   DBG_TGU_DEVID2___S                                   0

#define DBG_TGU_DEVID1                            (0x00BC4FC4)
#define   DBG_TGU_DEVID1___RWC                      QCSR_REG_RO    
#define   DBG_TGU_DEVID1___POR                   0x00000000
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP3___POR   0x0
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP2___POR   0x0
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP1___POR   0x0
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP0___POR   0x0
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP3___M     0xFF000000
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP3___S                  24
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP2___M     0x00FF0000
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP2___S                  16
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP1___M     0x0000FF00
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP1___S                   8
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP0___M     0x000000FF
#define   DBG_TGU_DEVID1__SSC_LSB_GROUP0___S                   0
#define   DBG_TGU_DEVID1___M                     0xFFFFFFFF   
#define   DBG_TGU_DEVID1___S                                   0

#define DBG_TGU_DEVID                             (0x00BC4FC8)
#define   DBG_TGU_DEVID___RWC                       QCSR_REG_RO    
#define   DBG_TGU_DEVID___POR                    0x0020CA44
#define   DBG_TGU_DEVID__REGISTER_INPUTS_VAL___POR 0x0
#define   DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___POR 0x0
#define   DBG_TGU_DEVID__AXI_WR_CH_VAL___POR     0x0
#define   DBG_TGU_DEVID__ASYNC_APB_VAL___POR     0x1
#define   DBG_TGU_DEVID__TC_CDC_VAL___POR        0x0
#define   DBG_TGU_DEVID__TR_PRESENT_VAL___POR    0x0
#define   DBG_TGU_DEVID__FIRST_TOKEN_VAL___POR   0x0
#define   DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___POR 0x32
#define   DBG_TGU_DEVID__NUM_TRIGGERS_VAL___POR  0x4
#define   DBG_TGU_DEVID__NUM_STEPS_VAL___POR     0x8
#define   DBG_TGU_DEVID__NUM_CONDS_VAL___POR     0x4
#define   DBG_TGU_DEVID__REGISTER_INPUTS_VAL___M 0x01000000
#define   DBG_TGU_DEVID__REGISTER_INPUTS_VAL___S              24
#define   DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___M 0x00800000
#define   DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___S              23
#define   DBG_TGU_DEVID__AXI_WR_CH_VAL___M       0x00400000
#define   DBG_TGU_DEVID__AXI_WR_CH_VAL___S                    22
#define   DBG_TGU_DEVID__ASYNC_APB_VAL___M       0x00200000
#define   DBG_TGU_DEVID__ASYNC_APB_VAL___S                    21
#define   DBG_TGU_DEVID__TC_CDC_VAL___M          0x00100000
#define   DBG_TGU_DEVID__TC_CDC_VAL___S                       20
#define   DBG_TGU_DEVID__TR_PRESENT_VAL___M      0x00080000
#define   DBG_TGU_DEVID__TR_PRESENT_VAL___S                   19
#define   DBG_TGU_DEVID__FIRST_TOKEN_VAL___M     0x00040000
#define   DBG_TGU_DEVID__FIRST_TOKEN_VAL___S                  18
#define   DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___M 0x0003FC00
#define   DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___S              10
#define   DBG_TGU_DEVID__NUM_TRIGGERS_VAL___M    0x00000380
#define   DBG_TGU_DEVID__NUM_TRIGGERS_VAL___S                  7
#define   DBG_TGU_DEVID__NUM_STEPS_VAL___M       0x00000078
#define   DBG_TGU_DEVID__NUM_STEPS_VAL___S                     3
#define   DBG_TGU_DEVID__NUM_CONDS_VAL___M       0x00000007
#define   DBG_TGU_DEVID__NUM_CONDS_VAL___S                     0
#define   DBG_TGU_DEVID___M                      0x01FFFFFF   
#define   DBG_TGU_DEVID___S                                    0

#define DBG_TGU_PIDR4                             (0x00BC4FD0)
#define   DBG_TGU_PIDR4___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR4___POR                    0x00000000
#define   DBG_TGU_PIDR4__SIZE___POR              0x0
#define   DBG_TGU_PIDR4__DES_2___POR             0x0
#define   DBG_TGU_PIDR4__SIZE___M                0x000000F0
#define   DBG_TGU_PIDR4__SIZE___S                              4
#define   DBG_TGU_PIDR4__DES_2___M               0x0000000F
#define   DBG_TGU_PIDR4__DES_2___S                             0
#define   DBG_TGU_PIDR4___M                      0x000000FF   
#define   DBG_TGU_PIDR4___S                                    0

#define DBG_TGU_PIDR5                             (0x00BC4FD4)
#define   DBG_TGU_PIDR5___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR5___POR                    0x00000000
#define   DBG_TGU_PIDR5__EMPTY___POR             0x00000000
#define   DBG_TGU_PIDR5__EMPTY___M               0xFFFFFFFF
#define   DBG_TGU_PIDR5__EMPTY___S                             0
#define   DBG_TGU_PIDR5___M                      0xFFFFFFFF   
#define   DBG_TGU_PIDR5___S                                    0

#define DBG_TGU_PIDR6                             (0x00BC4FD8)
#define   DBG_TGU_PIDR6___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR6___POR                    0x00000000
#define   DBG_TGU_PIDR6__EMPTY___POR             0x00000000
#define   DBG_TGU_PIDR6__EMPTY___M               0xFFFFFFFF
#define   DBG_TGU_PIDR6__EMPTY___S                             0
#define   DBG_TGU_PIDR6___M                      0xFFFFFFFF   
#define   DBG_TGU_PIDR6___S                                    0

#define DBG_TGU_PIDR7                             (0x00BC4FDC)
#define   DBG_TGU_PIDR7___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR7___POR                    0x00000000
#define   DBG_TGU_PIDR7__EMPTY___POR             0x00000000
#define   DBG_TGU_PIDR7__EMPTY___M               0xFFFFFFFF
#define   DBG_TGU_PIDR7__EMPTY___S                             0
#define   DBG_TGU_PIDR7___M                      0xFFFFFFFF   
#define   DBG_TGU_PIDR7___S                                    0

#define DBG_TGU_PIDR0                             (0x00BC4FE0)
#define   DBG_TGU_PIDR0___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR0___POR                    0x00000000
#define   DBG_TGU_PIDR0__PART_0___POR            0x00000
#define   DBG_TGU_PIDR0__PART_0___M              0x0007FFFF
#define   DBG_TGU_PIDR0__PART_0___S                            0
#define   DBG_TGU_PIDR0___M                      0x0007FFFF   
#define   DBG_TGU_PIDR0___S                                    0

#define DBG_TGU_PIDR1                             (0x00BC4FE4)
#define   DBG_TGU_PIDR1___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR1___POR                    0x0000000E
#define   DBG_TGU_PIDR1__DES_0___POR             0x0
#define   DBG_TGU_PIDR1__PART_1___POR            0xE
#define   DBG_TGU_PIDR1__DES_0___M               0x000000F0
#define   DBG_TGU_PIDR1__DES_0___S                             4
#define   DBG_TGU_PIDR1__PART_1___M              0x0000000F
#define   DBG_TGU_PIDR1__PART_1___S                            0
#define   DBG_TGU_PIDR1___M                      0x000000FF   
#define   DBG_TGU_PIDR1___S                                    0

#define DBG_TGU_PIDR2                             (0x00BC4FE8)
#define   DBG_TGU_PIDR2___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR2___POR                    0x00000008
#define   DBG_TGU_PIDR2__REVISION___POR          0x0
#define   DBG_TGU_PIDR2__JEDEC___POR             0x1
#define   DBG_TGU_PIDR2__DES_1___POR             0x0
#define   DBG_TGU_PIDR2__REVISION___M            0x000000F0
#define   DBG_TGU_PIDR2__REVISION___S                          4
#define   DBG_TGU_PIDR2__JEDEC___M               0x00000008
#define   DBG_TGU_PIDR2__JEDEC___S                             3
#define   DBG_TGU_PIDR2__DES_1___M               0x00000007
#define   DBG_TGU_PIDR2__DES_1___S                             0
#define   DBG_TGU_PIDR2___M                      0x000000FF   
#define   DBG_TGU_PIDR2___S                                    0

#define DBG_TGU_PIDR3                             (0x00BC4FEC)
#define   DBG_TGU_PIDR3___RWC                       QCSR_REG_RO    
#define   DBG_TGU_PIDR3___POR                    0x00000000
#define   DBG_TGU_PIDR3__REVAND___POR            0x0
#define   DBG_TGU_PIDR3__CMOD___POR              0x0
#define   DBG_TGU_PIDR3__REVAND___M              0x000000F0
#define   DBG_TGU_PIDR3__REVAND___S                            4
#define   DBG_TGU_PIDR3__CMOD___M                0x0000000F
#define   DBG_TGU_PIDR3__CMOD___S                              0
#define   DBG_TGU_PIDR3___M                      0x000000FF   
#define   DBG_TGU_PIDR3___S                                    0

#define DBG_TGU_CIDR0                             (0x00BC4FF0)
#define   DBG_TGU_CIDR0___RWC                       QCSR_REG_RO    
#define   DBG_TGU_CIDR0___POR                    0x0000000D
#define   DBG_TGU_CIDR0__PRMBL_0___POR           0x0D
#define   DBG_TGU_CIDR0__PRMBL_0___M             0x000000FF
#define   DBG_TGU_CIDR0__PRMBL_0___S                           0
#define   DBG_TGU_CIDR0___M                      0x000000FF   
#define   DBG_TGU_CIDR0___S                                    0

#define DBG_TGU_CIDR1                             (0x00BC4FF4)
#define   DBG_TGU_CIDR1___RWC                       QCSR_REG_RO    
#define   DBG_TGU_CIDR1___POR                    0x00000090
#define   DBG_TGU_CIDR1__CLASS___POR             0x9
#define   DBG_TGU_CIDR1__PRMBL_1___POR           0x0
#define   DBG_TGU_CIDR1__CLASS___M               0x000000F0
#define   DBG_TGU_CIDR1__CLASS___S                             4
#define   DBG_TGU_CIDR1__PRMBL_1___M             0x0000000F
#define   DBG_TGU_CIDR1__PRMBL_1___S                           0
#define   DBG_TGU_CIDR1___M                      0x000000FF   
#define   DBG_TGU_CIDR1___S                                    0

#define DBG_TGU_CIDR2                             (0x00BC4FF8)
#define   DBG_TGU_CIDR2___RWC                       QCSR_REG_RO    
#define   DBG_TGU_CIDR2___POR                    0x00000005
#define   DBG_TGU_CIDR2__PRMBL_2___POR           0x05
#define   DBG_TGU_CIDR2__PRMBL_2___M             0x000000FF
#define   DBG_TGU_CIDR2__PRMBL_2___S                           0
#define   DBG_TGU_CIDR2___M                      0x000000FF   
#define   DBG_TGU_CIDR2___S                                    0

#define DBG_TGU_CIDR3                             (0x00BC4FFC)
#define   DBG_TGU_CIDR3___RWC                       QCSR_REG_RO    
#define   DBG_TGU_CIDR3___POR                    0x000000B1
#define   DBG_TGU_CIDR3__PRMBL_3___POR           0xB1
#define   DBG_TGU_CIDR3__PRMBL_3___M             0x000000FF
#define   DBG_TGU_CIDR3__PRMBL_3___S                           0
#define   DBG_TGU_CIDR3___M                      0x000000FF   
#define   DBG_TGU_CIDR3___S                                    0

#define DBG_CTITGU_CTICONTROL                     (0x00BC5000)
#define   DBG_CTITGU_CTICONTROL___RWC               QCSR_REG_RW    
#define   DBG_CTITGU_CTICONTROL___POR            0x00000000
#define   DBG_CTITGU_CTICONTROL__GLBEN___POR     0x0
#define   DBG_CTITGU_CTICONTROL__GLBEN___M       0x00000001
#define   DBG_CTITGU_CTICONTROL__GLBEN___S                     0
#define   DBG_CTITGU_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_CTITGU_CTICONTROL__GLBEN__ENABLED              0x1
#define   DBG_CTITGU_CTICONTROL___M              0x00000001   
#define   DBG_CTITGU_CTICONTROL___S                            0

#define DBG_CTITGU_CTIINTACK                      (0x00BC5010)
#define   DBG_CTITGU_CTIINTACK___RWC                QCSR_REG_WO    
#define   DBG_CTITGU_CTIINTACK___POR             0x00000000
#define   DBG_CTITGU_CTIINTACK__INTACK___POR     0x0
#define   DBG_CTITGU_CTIINTACK__INTACK___M       0x0000000F
#define   DBG_CTITGU_CTIINTACK__INTACK___S                     0
#define   DBG_CTITGU_CTIINTACK___M               0x0000000F   
#define   DBG_CTITGU_CTIINTACK___S                             0

#define DBG_CTITGU_CTIAPPSET                      (0x00BC5014)
#define   DBG_CTITGU_CTIAPPSET___RWC                QCSR_REG_RW    
#define   DBG_CTITGU_CTIAPPSET___POR             0x00000000
#define   DBG_CTITGU_CTIAPPSET__APPSET___POR     0x00
#define   DBG_CTITGU_CTIAPPSET__APPSET___M       0x000000FF
#define   DBG_CTITGU_CTIAPPSET__APPSET___S                     0
#define   DBG_CTITGU_CTIAPPSET___M               0x000000FF   
#define   DBG_CTITGU_CTIAPPSET___S                             0

#define DBG_CTITGU_CTIAPPCLEAR                    (0x00BC5018)
#define   DBG_CTITGU_CTIAPPCLEAR___RWC              QCSR_REG_WO    
#define   DBG_CTITGU_CTIAPPCLEAR___POR           0x00000000
#define   DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___M   0x000000FF
#define   DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___S                 0
#define   DBG_CTITGU_CTIAPPCLEAR___M             0x000000FF   
#define   DBG_CTITGU_CTIAPPCLEAR___S                           0

#define DBG_CTITGU_CTIAPPPULSE                    (0x00BC501C)
#define   DBG_CTITGU_CTIAPPPULSE___RWC              QCSR_REG_WO    
#define   DBG_CTITGU_CTIAPPPULSE___POR           0x00000000
#define   DBG_CTITGU_CTIAPPPULSE__APPULSE___POR  0x00
#define   DBG_CTITGU_CTIAPPPULSE__APPULSE___M    0x000000FF
#define   DBG_CTITGU_CTIAPPPULSE__APPULSE___S                  0
#define   DBG_CTITGU_CTIAPPPULSE___M             0x000000FF   
#define   DBG_CTITGU_CTIAPPPULSE___S                           0

#define DBG_CTITGU_CTIINEN0                       (0x00BC5020)
#define   DBG_CTITGU_CTIINEN0___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CTIINEN0___POR              0x00000000
#define   DBG_CTITGU_CTIINEN0__TRIGINEN___POR    0x00
#define   DBG_CTITGU_CTIINEN0__TRIGINEN___M      0x000000FF
#define   DBG_CTITGU_CTIINEN0__TRIGINEN___S                    0
#define   DBG_CTITGU_CTIINEN0___M                0x000000FF   
#define   DBG_CTITGU_CTIINEN0___S                              0

#define DBG_CTITGU_CTIINEN1                       (0x00BC5024)
#define   DBG_CTITGU_CTIINEN1___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CTIINEN1___POR              0x00000000
#define   DBG_CTITGU_CTIINEN1__TRIGINEN___POR    0x00
#define   DBG_CTITGU_CTIINEN1__TRIGINEN___M      0x000000FF
#define   DBG_CTITGU_CTIINEN1__TRIGINEN___S                    0
#define   DBG_CTITGU_CTIINEN1___M                0x000000FF   
#define   DBG_CTITGU_CTIINEN1___S                              0

#define DBG_CTITGU_CTIINEN2                       (0x00BC5028)
#define   DBG_CTITGU_CTIINEN2___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CTIINEN2___POR              0x00000000
#define   DBG_CTITGU_CTIINEN2__TRIGINEN___POR    0x00
#define   DBG_CTITGU_CTIINEN2__TRIGINEN___M      0x000000FF
#define   DBG_CTITGU_CTIINEN2__TRIGINEN___S                    0
#define   DBG_CTITGU_CTIINEN2___M                0x000000FF   
#define   DBG_CTITGU_CTIINEN2___S                              0

#define DBG_CTITGU_CTIINEN3                       (0x00BC502C)
#define   DBG_CTITGU_CTIINEN3___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CTIINEN3___POR              0x00000000
#define   DBG_CTITGU_CTIINEN3__TRIGINEN___POR    0x00
#define   DBG_CTITGU_CTIINEN3__TRIGINEN___M      0x000000FF
#define   DBG_CTITGU_CTIINEN3__TRIGINEN___S                    0
#define   DBG_CTITGU_CTIINEN3___M                0x000000FF   
#define   DBG_CTITGU_CTIINEN3___S                              0

#define DBG_CTITGU_CTIOUTEN0                      (0x00BC50A0)
#define   DBG_CTITGU_CTIOUTEN0___RWC                QCSR_REG_RW    
#define   DBG_CTITGU_CTIOUTEN0___POR             0x00000000
#define   DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___POR  0x00
#define   DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___M    0x000000FF
#define   DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___S                  0
#define   DBG_CTITGU_CTIOUTEN0___M               0x000000FF   
#define   DBG_CTITGU_CTIOUTEN0___S                             0

#define DBG_CTITGU_CTIOUTEN1                      (0x00BC50A4)
#define   DBG_CTITGU_CTIOUTEN1___RWC                QCSR_REG_RW    
#define   DBG_CTITGU_CTIOUTEN1___POR             0x00000000
#define   DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___POR  0x00
#define   DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___M    0x000000FF
#define   DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___S                  0
#define   DBG_CTITGU_CTIOUTEN1___M               0x000000FF   
#define   DBG_CTITGU_CTIOUTEN1___S                             0

#define DBG_CTITGU_CTIOUTEN2                      (0x00BC50A8)
#define   DBG_CTITGU_CTIOUTEN2___RWC                QCSR_REG_RW    
#define   DBG_CTITGU_CTIOUTEN2___POR             0x00000000
#define   DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___POR  0x00
#define   DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___M    0x000000FF
#define   DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___S                  0
#define   DBG_CTITGU_CTIOUTEN2___M               0x000000FF   
#define   DBG_CTITGU_CTIOUTEN2___S                             0

#define DBG_CTITGU_CTIOUTEN3                      (0x00BC50AC)
#define   DBG_CTITGU_CTIOUTEN3___RWC                QCSR_REG_RW    
#define   DBG_CTITGU_CTIOUTEN3___POR             0x00000000
#define   DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___POR  0x00
#define   DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___M    0x000000FF
#define   DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___S                  0
#define   DBG_CTITGU_CTIOUTEN3___M               0x000000FF   
#define   DBG_CTITGU_CTIOUTEN3___S                             0

#define DBG_CTITGU_CTITRIGINSTATUS                (0x00BC5130)
#define   DBG_CTITGU_CTITRIGINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_CTITGU_CTITRIGINSTATUS__TRIGINSTATUS___M 0x0000000F
#define   DBG_CTITGU_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_CTITGU_CTITRIGINSTATUS___M         0x0000000F   
#define   DBG_CTITGU_CTITRIGINSTATUS___S                       0

#define DBG_CTITGU_CTITRIGOUTSTATUS               (0x00BC5134)
#define   DBG_CTITGU_CTITRIGOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_CTITGU_CTITRIGOUTSTATUS___POR      0x00000000
#define   DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x0
#define   DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x0000000F
#define   DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_CTITGU_CTITRIGOUTSTATUS___M        0x0000000F   
#define   DBG_CTITGU_CTITRIGOUTSTATUS___S                      0

#define DBG_CTITGU_CTICHINSTATUS                  (0x00BC5138)
#define   DBG_CTITGU_CTICHINSTATUS___RWC            QCSR_REG_RO    
#define   DBG_CTITGU_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_CTITGU_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_CTITGU_CTICHINSTATUS___M           0x000000FF   
#define   DBG_CTITGU_CTICHINSTATUS___S                         0

#define DBG_CTITGU_CTICHOUTSTATUS                 (0x00BC513C)
#define   DBG_CTITGU_CTICHOUTSTATUS___RWC           QCSR_REG_RO    
#define   DBG_CTITGU_CTICHOUTSTATUS___POR        0x00000000
#define   DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_CTITGU_CTICHOUTSTATUS___M          0x000000FF   
#define   DBG_CTITGU_CTICHOUTSTATUS___S                        0

#define DBG_CTITGU_CTIGATE                        (0x00BC5140)
#define   DBG_CTITGU_CTIGATE___RWC                  QCSR_REG_RW    
#define   DBG_CTITGU_CTIGATE___POR               0x000000FF
#define   DBG_CTITGU_CTIGATE__CTIGATEEN7___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN6___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN5___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN4___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN3___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN2___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN1___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN0___POR   0x1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN7___M     0x00000080
#define   DBG_CTITGU_CTIGATE__CTIGATEEN7___S                   7
#define   DBG_CTITGU_CTIGATE__CTIGATEEN6___M     0x00000040
#define   DBG_CTITGU_CTIGATE__CTIGATEEN6___S                   6
#define   DBG_CTITGU_CTIGATE__CTIGATEEN5___M     0x00000020
#define   DBG_CTITGU_CTIGATE__CTIGATEEN5___S                   5
#define   DBG_CTITGU_CTIGATE__CTIGATEEN4___M     0x00000010
#define   DBG_CTITGU_CTIGATE__CTIGATEEN4___S                   4
#define   DBG_CTITGU_CTIGATE__CTIGATEEN3___M     0x00000008
#define   DBG_CTITGU_CTIGATE__CTIGATEEN3___S                   3
#define   DBG_CTITGU_CTIGATE__CTIGATEEN2___M     0x00000004
#define   DBG_CTITGU_CTIGATE__CTIGATEEN2___S                   2
#define   DBG_CTITGU_CTIGATE__CTIGATEEN1___M     0x00000002
#define   DBG_CTITGU_CTIGATE__CTIGATEEN1___S                   1
#define   DBG_CTITGU_CTIGATE__CTIGATEEN0___M     0x00000001
#define   DBG_CTITGU_CTIGATE__CTIGATEEN0___S                   0
#define   DBG_CTITGU_CTIGATE___M                 0x000000FF   
#define   DBG_CTITGU_CTIGATE___S                               0

#define DBG_CTITGU_ASICCTL                        (0x00BC5144)
#define   DBG_CTITGU_ASICCTL___RWC                  QCSR_REG_RW    
#define   DBG_CTITGU_ASICCTL___POR               0x00000000
#define   DBG_CTITGU_ASICCTL__ASICCTL___POR      0x00000000
#define   DBG_CTITGU_ASICCTL__ASICCTL___M        0xFFFFFFFF
#define   DBG_CTITGU_ASICCTL__ASICCTL___S                      0
#define   DBG_CTITGU_ASICCTL___M                 0xFFFFFFFF   
#define   DBG_CTITGU_ASICCTL___S                               0

#define DBG_CTITGU_ITCHINACK                      (0x00BC5EDC)
#define   DBG_CTITGU_ITCHINACK___RWC                QCSR_REG_WO    
#define   DBG_CTITGU_ITCHINACK___POR             0x00000000
#define   DBG_CTITGU_ITCHINACK__CTCHINACK___POR  0x00
#define   DBG_CTITGU_ITCHINACK__CTCHINACK___M    0x000000FF
#define   DBG_CTITGU_ITCHINACK__CTCHINACK___S                  0
#define   DBG_CTITGU_ITCHINACK___M               0x000000FF   
#define   DBG_CTITGU_ITCHINACK___S                             0

#define DBG_CTITGU_ITTRIGINACK                    (0x00BC5EE0)
#define   DBG_CTITGU_ITTRIGINACK___RWC              QCSR_REG_WO    
#define   DBG_CTITGU_ITTRIGINACK___POR           0x00000000
#define   DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___POR 0x0
#define   DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___M 0x0000000F
#define   DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_CTITGU_ITTRIGINACK___M             0x0000000F   
#define   DBG_CTITGU_ITTRIGINACK___S                           0

#define DBG_CTITGU_ITCHOUT                        (0x00BC5EE4)
#define   DBG_CTITGU_ITCHOUT___RWC                  QCSR_REG_WO    
#define   DBG_CTITGU_ITCHOUT___POR               0x00000000
#define   DBG_CTITGU_ITCHOUT__CTCHOUT___POR      0x00
#define   DBG_CTITGU_ITCHOUT__CTCHOUT___M        0x000000FF
#define   DBG_CTITGU_ITCHOUT__CTCHOUT___S                      0
#define   DBG_CTITGU_ITCHOUT___M                 0x000000FF   
#define   DBG_CTITGU_ITCHOUT___S                               0

#define DBG_CTITGU_ITTRIGOUT                      (0x00BC5EE8)
#define   DBG_CTITGU_ITTRIGOUT___RWC                QCSR_REG_WO    
#define   DBG_CTITGU_ITTRIGOUT___POR             0x00000000
#define   DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___POR  0x0
#define   DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___M    0x0000000F
#define   DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___S                  0
#define   DBG_CTITGU_ITTRIGOUT___M               0x0000000F   
#define   DBG_CTITGU_ITTRIGOUT___S                             0

#define DBG_CTITGU_ITCHOUTACK                     (0x00BC5EEC)
#define   DBG_CTITGU_ITCHOUTACK___RWC               QCSR_REG_RO    
#define   DBG_CTITGU_ITCHOUTACK___POR            0x00000000
#define   DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___M  0x000000FF
#define   DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___S                0
#define   DBG_CTITGU_ITCHOUTACK___M              0x000000FF   
#define   DBG_CTITGU_ITCHOUTACK___S                            0

#define DBG_CTITGU_ITTRIGOUTACK                   (0x00BC5EF0)
#define   DBG_CTITGU_ITTRIGOUTACK___RWC             QCSR_REG_RO    
#define   DBG_CTITGU_ITTRIGOUTACK___POR          0x00000000
#define   DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x0
#define   DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___M 0x0000000F
#define   DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_CTITGU_ITTRIGOUTACK___M            0x0000000F   
#define   DBG_CTITGU_ITTRIGOUTACK___S                          0

#define DBG_CTITGU_ITCHIN                         (0x00BC5EF4)
#define   DBG_CTITGU_ITCHIN___RWC                   QCSR_REG_RO    
#define   DBG_CTITGU_ITCHIN___POR                0x00000000
#define   DBG_CTITGU_ITCHIN__CTCHIN___POR        0x00
#define   DBG_CTITGU_ITCHIN__CTCHIN___M          0x000000FF
#define   DBG_CTITGU_ITCHIN__CTCHIN___S                        0
#define   DBG_CTITGU_ITCHIN___M                  0x000000FF   
#define   DBG_CTITGU_ITCHIN___S                                0

#define DBG_CTITGU_ITTRIGIN                       (0x00BC5EF8)
#define   DBG_CTITGU_ITTRIGIN___RWC                 QCSR_REG_RO    
#define   DBG_CTITGU_ITTRIGIN___POR              0x00000000
#define   DBG_CTITGU_ITTRIGIN__CTTRIGIN___POR    0x0
#define   DBG_CTITGU_ITTRIGIN__CTTRIGIN___M      0x0000000F
#define   DBG_CTITGU_ITTRIGIN__CTTRIGIN___S                    0
#define   DBG_CTITGU_ITTRIGIN___M                0x0000000F   
#define   DBG_CTITGU_ITTRIGIN___S                              0

#define DBG_CTITGU_ITCTRL                         (0x00BC5F00)
#define   DBG_CTITGU_ITCTRL___RWC                   QCSR_REG_RW    
#define   DBG_CTITGU_ITCTRL___POR                0x00000000
#define   DBG_CTITGU_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_CTITGU_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_CTITGU_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_CTITGU_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_CTITGU_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_CTITGU_ITCTRL___M                  0x00000001   
#define   DBG_CTITGU_ITCTRL___S                                0

#define DBG_CTITGU_CLAIMSET                       (0x00BC5FA0)
#define   DBG_CTITGU_CLAIMSET___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CLAIMSET___POR              0x0000000F
#define   DBG_CTITGU_CLAIMSET__CLAIMSET___POR    0xF
#define   DBG_CTITGU_CLAIMSET__CLAIMSET___M      0x0000000F
#define   DBG_CTITGU_CLAIMSET__CLAIMSET___S                    0
#define   DBG_CTITGU_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_CTITGU_CLAIMSET___M                0x0000000F   
#define   DBG_CTITGU_CLAIMSET___S                              0

#define DBG_CTITGU_CLAIMCLR                       (0x00BC5FA4)
#define   DBG_CTITGU_CLAIMCLR___RWC                 QCSR_REG_RW    
#define   DBG_CTITGU_CLAIMCLR___POR              0x00000000
#define   DBG_CTITGU_CLAIMCLR__CLAIMCLR___POR    0x0
#define   DBG_CTITGU_CLAIMCLR__CLAIMCLR___M      0x0000000F
#define   DBG_CTITGU_CLAIMCLR__CLAIMCLR___S                    0
#define   DBG_CTITGU_CLAIMCLR___M                0x0000000F   
#define   DBG_CTITGU_CLAIMCLR___S                              0

#define DBG_CTITGU_DEVAFF0                        (0x00BC5FA8)
#define   DBG_CTITGU_DEVAFF0___RWC                  QCSR_REG_RO    
#define   DBG_CTITGU_DEVAFF0___POR               0x00000000
#define   DBG_CTITGU_DEVAFF0__VAL___POR          0x00000000
#define   DBG_CTITGU_DEVAFF0__VAL___M            0xFFFFFFFF
#define   DBG_CTITGU_DEVAFF0__VAL___S                          0
#define   DBG_CTITGU_DEVAFF0___M                 0xFFFFFFFF   
#define   DBG_CTITGU_DEVAFF0___S                               0

#define DBG_CTITGU_DEVAFF1                        (0x00BC5FAC)
#define   DBG_CTITGU_DEVAFF1___RWC                  QCSR_REG_RO    
#define   DBG_CTITGU_DEVAFF1___POR               0x00000000
#define   DBG_CTITGU_DEVAFF1__VAL___POR          0x00000000
#define   DBG_CTITGU_DEVAFF1__VAL___M            0xFFFFFFFF
#define   DBG_CTITGU_DEVAFF1__VAL___S                          0
#define   DBG_CTITGU_DEVAFF1___M                 0xFFFFFFFF   
#define   DBG_CTITGU_DEVAFF1___S                               0

#define DBG_CTITGU_LAR                            (0x00BC5FB0)
#define   DBG_CTITGU_LAR___RWC                      QCSR_REG_WO    
#define   DBG_CTITGU_LAR__ACCESS_W___M           0xFFFFFFFF
#define   DBG_CTITGU_LAR__ACCESS_W___S                         0
#define   DBG_CTITGU_LAR__ACCESS_W__UNLOCK            0xC5ACCE55
#define   DBG_CTITGU_LAR___M                     0xFFFFFFFF   
#define   DBG_CTITGU_LAR___S                                   0

#define DBG_CTITGU_LSR                            (0x00BC5FB4)
#define   DBG_CTITGU_LSR___RWC                      QCSR_REG_RO    
#define   DBG_CTITGU_LSR___POR                   0x00000003
#define   DBG_CTITGU_LSR__LOCKTYPE___POR         0x0
#define   DBG_CTITGU_LSR__LOCKGRANT___POR        0x1
#define   DBG_CTITGU_LSR__LOCKEXIST___POR        0x1
#define   DBG_CTITGU_LSR__LOCKTYPE___M           0x00000004
#define   DBG_CTITGU_LSR__LOCKTYPE___S                         2
#define   DBG_CTITGU_LSR__LOCKTYPE__SIZE_32BIT               0x0
#define   DBG_CTITGU_LSR__LOCKGRANT___M          0x00000002
#define   DBG_CTITGU_LSR__LOCKGRANT___S                        1
#define   DBG_CTITGU_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_CTITGU_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_CTITGU_LSR__LOCKEXIST___M          0x00000001
#define   DBG_CTITGU_LSR__LOCKEXIST___S                        0
#define   DBG_CTITGU_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_CTITGU_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_CTITGU_LSR___M                     0x00000007   
#define   DBG_CTITGU_LSR___S                                   0

#define DBG_CTITGU_AUTHSTATUS                     (0x00BC5FB8)
#define   DBG_CTITGU_AUTHSTATUS___RWC               QCSR_REG_RO    
#define   DBG_CTITGU_AUTHSTATUS__SNID___M        0x000000C0
#define   DBG_CTITGU_AUTHSTATUS__SNID___S                      6
#define   DBG_CTITGU_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_CTITGU_AUTHSTATUS__SID___M         0x00000030
#define   DBG_CTITGU_AUTHSTATUS__SID___S                       4
#define   DBG_CTITGU_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_CTITGU_AUTHSTATUS__NSNID___M       0x0000000C
#define   DBG_CTITGU_AUTHSTATUS__NSNID___S                     2
#define   DBG_CTITGU_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_CTITGU_AUTHSTATUS__NSNID__ENABLED              0x3
#define   DBG_CTITGU_AUTHSTATUS__NSID___M        0x00000003
#define   DBG_CTITGU_AUTHSTATUS__NSID___S                      0
#define   DBG_CTITGU_AUTHSTATUS__NSID__DISABLED              0x2
#define   DBG_CTITGU_AUTHSTATUS__NSID__ENABLED               0x3
#define   DBG_CTITGU_AUTHSTATUS___M              0x000000FF   
#define   DBG_CTITGU_AUTHSTATUS___S                            0

#define DBG_CTITGU_DEVARCH                        (0x00BC5FBC)
#define   DBG_CTITGU_DEVARCH___RWC                  QCSR_REG_RO    
#define   DBG_CTITGU_DEVARCH___POR               0x8EF00A14
#define   DBG_CTITGU_DEVARCH__ARCHITECT___POR    0x477
#define   DBG_CTITGU_DEVARCH__PRESENT___POR      0x1
#define   DBG_CTITGU_DEVARCH__REVISION___POR     0x0
#define   DBG_CTITGU_DEVARCH__ARCHID___POR       0x0A14
#define   DBG_CTITGU_DEVARCH__ARCHITECT___M      0xFFE00000
#define   DBG_CTITGU_DEVARCH__ARCHITECT___S                   21
#define   DBG_CTITGU_DEVARCH__PRESENT___M        0x00100000
#define   DBG_CTITGU_DEVARCH__PRESENT___S                     20
#define   DBG_CTITGU_DEVARCH__REVISION___M       0x000F0000
#define   DBG_CTITGU_DEVARCH__REVISION___S                    16
#define   DBG_CTITGU_DEVARCH__ARCHID___M         0x0000FFFF
#define   DBG_CTITGU_DEVARCH__ARCHID___S                       0
#define   DBG_CTITGU_DEVARCH___M                 0xFFFFFFFF   
#define   DBG_CTITGU_DEVARCH___S                               0

#define DBG_CTITGU_DEVID2                         (0x00BC5FC0)
#define   DBG_CTITGU_DEVID2___RWC                   QCSR_REG_RO    
#define   DBG_CTITGU_DEVID2___POR                0x00000000
#define   DBG_CTITGU_DEVID2__IMPLDEF___POR       0x0
#define   DBG_CTITGU_DEVID2__IMPLDEF___M         0x00000001
#define   DBG_CTITGU_DEVID2__IMPLDEF___S                       0
#define   DBG_CTITGU_DEVID2___M                  0x00000001   
#define   DBG_CTITGU_DEVID2___S                                0

#define DBG_CTITGU_DEVID1                         (0x00BC5FC4)
#define   DBG_CTITGU_DEVID1___RWC                   QCSR_REG_RO    
#define   DBG_CTITGU_DEVID1___POR                0x00000000
#define   DBG_CTITGU_DEVID1__IMPLDEF___POR       0x0
#define   DBG_CTITGU_DEVID1__IMPLDEF___M         0x00000001
#define   DBG_CTITGU_DEVID1__IMPLDEF___S                       0
#define   DBG_CTITGU_DEVID1___M                  0x00000001   
#define   DBG_CTITGU_DEVID1___S                                0

#define DBG_CTITGU_DEVID                          (0x00BC5FC8)
#define   DBG_CTITGU_DEVID___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_DEVID___POR                 0x00080400
#define   DBG_CTITGU_DEVID__NUMCH___POR          0x8
#define   DBG_CTITGU_DEVID__NUMTRIG___POR        0x4
#define   DBG_CTITGU_DEVID__EXTMUXNUM___POR      0x00
#define   DBG_CTITGU_DEVID__NUMCH___M            0x003F0000
#define   DBG_CTITGU_DEVID__NUMCH___S                         16
#define   DBG_CTITGU_DEVID__NUMTRIG___M          0x0000FF00
#define   DBG_CTITGU_DEVID__NUMTRIG___S                        8
#define   DBG_CTITGU_DEVID__EXTMUXNUM___M        0x0000001F
#define   DBG_CTITGU_DEVID__EXTMUXNUM___S                      0
#define   DBG_CTITGU_DEVID___M                   0x003FFF1F   
#define   DBG_CTITGU_DEVID___S                                 0

#define DBG_CTITGU_DEVTYPE                        (0x00BC5FCC)
#define   DBG_CTITGU_DEVTYPE___RWC                  QCSR_REG_RO    
#define   DBG_CTITGU_DEVTYPE___POR               0x00000014
#define   DBG_CTITGU_DEVTYPE__SUB_TYPE___POR     0x1
#define   DBG_CTITGU_DEVTYPE__MAJOR_TYPE___POR   0x4
#define   DBG_CTITGU_DEVTYPE__SUB_TYPE___M       0x000000F0
#define   DBG_CTITGU_DEVTYPE__SUB_TYPE___S                     4
#define   DBG_CTITGU_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_CTITGU_DEVTYPE__MAJOR_TYPE___M     0x0000000F
#define   DBG_CTITGU_DEVTYPE__MAJOR_TYPE___S                   0
#define   DBG_CTITGU_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_CTITGU_DEVTYPE___M                 0x000000FF   
#define   DBG_CTITGU_DEVTYPE___S                               0

#define DBG_CTITGU_PIDR0                          (0x00BC5FE0)
#define   DBG_CTITGU_PIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_PIDR0___POR                 0x00000006
#define   DBG_CTITGU_PIDR0__PART_0___POR         0x06
#define   DBG_CTITGU_PIDR0__PART_0___M           0x000000FF
#define   DBG_CTITGU_PIDR0__PART_0___S                         0
#define   DBG_CTITGU_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_CTITGU_PIDR0___M                   0x000000FF   
#define   DBG_CTITGU_PIDR0___S                                 0

#define DBG_CTITGU_PIDR1                          (0x00BC5FE4)
#define   DBG_CTITGU_PIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_PIDR1___POR                 0x000000B9
#define   DBG_CTITGU_PIDR1__DES_0___POR          0xB
#define   DBG_CTITGU_PIDR1__PART_1___POR         0x9
#define   DBG_CTITGU_PIDR1__DES_0___M            0x000000F0
#define   DBG_CTITGU_PIDR1__DES_0___S                          4
#define   DBG_CTITGU_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_CTITGU_PIDR1__PART_1___M           0x0000000F
#define   DBG_CTITGU_PIDR1__PART_1___S                         0
#define   DBG_CTITGU_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_CTITGU_PIDR1___M                   0x000000FF   
#define   DBG_CTITGU_PIDR1___S                                 0

#define DBG_CTITGU_PIDR2                          (0x00BC5FE8)
#define   DBG_CTITGU_PIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_PIDR2___POR                 0x0000004B
#define   DBG_CTITGU_PIDR2__REVISION___POR       0x4
#define   DBG_CTITGU_PIDR2__JEDEC___POR          0x1
#define   DBG_CTITGU_PIDR2__DES_1___POR          0x3
#define   DBG_CTITGU_PIDR2__REVISION___M         0x000000F0
#define   DBG_CTITGU_PIDR2__REVISION___S                       4
#define   DBG_CTITGU_PIDR2__REVISION__R0P4                   0x4
#define   DBG_CTITGU_PIDR2__REVISION__R0P5                   0x5
#define   DBG_CTITGU_PIDR2__JEDEC___M            0x00000008
#define   DBG_CTITGU_PIDR2__JEDEC___S                          3
#define   DBG_CTITGU_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_CTITGU_PIDR2__DES_1___M            0x00000007
#define   DBG_CTITGU_PIDR2__DES_1___S                          0
#define   DBG_CTITGU_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_CTITGU_PIDR2___M                   0x000000FF   
#define   DBG_CTITGU_PIDR2___S                                 0

#define DBG_CTITGU_PIDR3                          (0x00BC5FEC)
#define   DBG_CTITGU_PIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_PIDR3___POR                 0x00000000
#define   DBG_CTITGU_PIDR3__REVAND___POR         0x0
#define   DBG_CTITGU_PIDR3__CMOD___POR           0x0
#define   DBG_CTITGU_PIDR3__REVAND___M           0x000000F0
#define   DBG_CTITGU_PIDR3__REVAND___S                         4
#define   DBG_CTITGU_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_CTITGU_PIDR3__CMOD___M             0x0000000F
#define   DBG_CTITGU_PIDR3__CMOD___S                           0
#define   DBG_CTITGU_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_CTITGU_PIDR3___M                   0x000000FF   
#define   DBG_CTITGU_PIDR3___S                                 0

#define DBG_CTITGU_PIDR4                          (0x00BC5FD0)
#define   DBG_CTITGU_PIDR4___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_PIDR4___POR                 0x00000004
#define   DBG_CTITGU_PIDR4__SIZE___POR           0x0
#define   DBG_CTITGU_PIDR4__DES_2___POR          0x4
#define   DBG_CTITGU_PIDR4__SIZE___M             0x000000F0
#define   DBG_CTITGU_PIDR4__SIZE___S                           4
#define   DBG_CTITGU_PIDR4__SIZE__SIZE_4KB                   0x0
#define   DBG_CTITGU_PIDR4__DES_2___M            0x0000000F
#define   DBG_CTITGU_PIDR4__DES_2___S                          0
#define   DBG_CTITGU_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_CTITGU_PIDR4___M                   0x000000FF   
#define   DBG_CTITGU_PIDR4___S                                 0

#define DBG_CTITGU_PIDR5                          (0x00BC5FD4)
#define   DBG_CTITGU_PIDR5___RWC                    QCSR_REG_RW    
#define   DBG_CTITGU_PIDR5__PERIPHID5___M        0xFFFFFFFF
#define   DBG_CTITGU_PIDR5__PERIPHID5___S                      0
#define   DBG_CTITGU_PIDR5___M                   0xFFFFFFFF   
#define   DBG_CTITGU_PIDR5___S                                 0

#define DBG_CTITGU_PIDR6                          (0x00BC5FD8)
#define   DBG_CTITGU_PIDR6___RWC                    QCSR_REG_RW    
#define   DBG_CTITGU_PIDR6__PERIPHID6___M        0xFFFFFFFF
#define   DBG_CTITGU_PIDR6__PERIPHID6___S                      0
#define   DBG_CTITGU_PIDR6___M                   0xFFFFFFFF   
#define   DBG_CTITGU_PIDR6___S                                 0

#define DBG_CTITGU_PIDR7                          (0x00BC5FDC)
#define   DBG_CTITGU_PIDR7___RWC                    QCSR_REG_RW    
#define   DBG_CTITGU_PIDR7__PERIPHID7___M        0xFFFFFFFF
#define   DBG_CTITGU_PIDR7__PERIPHID7___S                      0
#define   DBG_CTITGU_PIDR7___M                   0xFFFFFFFF   
#define   DBG_CTITGU_PIDR7___S                                 0

#define DBG_CTITGU_CIDR0                          (0x00BC5FF0)
#define   DBG_CTITGU_CIDR0___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_CIDR0___POR                 0x0000000D
#define   DBG_CTITGU_CIDR0__PRMBL_0___POR        0x0D
#define   DBG_CTITGU_CIDR0__PRMBL_0___M          0x000000FF
#define   DBG_CTITGU_CIDR0__PRMBL_0___S                        0
#define   DBG_CTITGU_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_CTITGU_CIDR0___M                   0x000000FF   
#define   DBG_CTITGU_CIDR0___S                                 0

#define DBG_CTITGU_CIDR1                          (0x00BC5FF4)
#define   DBG_CTITGU_CIDR1___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_CIDR1___POR                 0x00000090
#define   DBG_CTITGU_CIDR1__CLASS___POR          0x9
#define   DBG_CTITGU_CIDR1__PRMBL_1___POR        0x0
#define   DBG_CTITGU_CIDR1__CLASS___M            0x000000F0
#define   DBG_CTITGU_CIDR1__CLASS___S                          4
#define   DBG_CTITGU_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_CTITGU_CIDR1__PRMBL_1___M          0x0000000F
#define   DBG_CTITGU_CIDR1__PRMBL_1___S                        0
#define   DBG_CTITGU_CIDR1__PRMBL_1__ID_VALUE_0              0x0
#define   DBG_CTITGU_CIDR1___M                   0x000000FF   
#define   DBG_CTITGU_CIDR1___S                                 0

#define DBG_CTITGU_CIDR2                          (0x00BC5FF8)
#define   DBG_CTITGU_CIDR2___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_CIDR2___POR                 0x00000005
#define   DBG_CTITGU_CIDR2__PRMBL_2___POR        0x05
#define   DBG_CTITGU_CIDR2__PRMBL_2___M          0x000000FF
#define   DBG_CTITGU_CIDR2__PRMBL_2___S                        0
#define   DBG_CTITGU_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_CTITGU_CIDR2___M                   0x000000FF   
#define   DBG_CTITGU_CIDR2___S                                 0

#define DBG_CTITGU_CIDR3                          (0x00BC5FFC)
#define   DBG_CTITGU_CIDR3___RWC                    QCSR_REG_RO    
#define   DBG_CTITGU_CIDR3___POR                 0x000000B1
#define   DBG_CTITGU_CIDR3__PRMBL_3___POR        0xB1
#define   DBG_CTITGU_CIDR3__PRMBL_3___M          0x000000FF
#define   DBG_CTITGU_CIDR3__PRMBL_3___S                        0
#define   DBG_CTITGU_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_CTITGU_CIDR3___M                   0x000000FF   
#define   DBG_CTITGU_CIDR3___S                                 0

#define DBG_PHYADMUX_ATID_EN0                     (0x00BC6000)
#define   DBG_PHYADMUX_ATID_EN0___RWC               QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_EN0___POR            0xFFFFFFFF
#define   DBG_PHYADMUX_ATID_EN0__ATID31_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID30_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID29_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID28_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID27_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID26_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID25_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID24_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID23_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID22_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID21_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID20_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID19_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID18_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID17_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID16_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID15_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID14_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID13_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID12_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID11_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID10_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID9_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID8_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID7_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID6_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID5_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID4_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID3_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID2_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID1_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID0_EN___POR  0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID31_EN___M   0x80000000
#define   DBG_PHYADMUX_ATID_EN0__ATID31_EN___S                31
#define   DBG_PHYADMUX_ATID_EN0__ATID31_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID31_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID30_EN___M   0x40000000
#define   DBG_PHYADMUX_ATID_EN0__ATID30_EN___S                30
#define   DBG_PHYADMUX_ATID_EN0__ATID30_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID30_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID29_EN___M   0x20000000
#define   DBG_PHYADMUX_ATID_EN0__ATID29_EN___S                29
#define   DBG_PHYADMUX_ATID_EN0__ATID29_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID29_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID28_EN___M   0x10000000
#define   DBG_PHYADMUX_ATID_EN0__ATID28_EN___S                28
#define   DBG_PHYADMUX_ATID_EN0__ATID28_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID28_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID27_EN___M   0x08000000
#define   DBG_PHYADMUX_ATID_EN0__ATID27_EN___S                27
#define   DBG_PHYADMUX_ATID_EN0__ATID27_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID27_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID26_EN___M   0x04000000
#define   DBG_PHYADMUX_ATID_EN0__ATID26_EN___S                26
#define   DBG_PHYADMUX_ATID_EN0__ATID26_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID26_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID25_EN___M   0x02000000
#define   DBG_PHYADMUX_ATID_EN0__ATID25_EN___S                25
#define   DBG_PHYADMUX_ATID_EN0__ATID25_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID25_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID24_EN___M   0x01000000
#define   DBG_PHYADMUX_ATID_EN0__ATID24_EN___S                24
#define   DBG_PHYADMUX_ATID_EN0__ATID24_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID24_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID23_EN___M   0x00800000
#define   DBG_PHYADMUX_ATID_EN0__ATID23_EN___S                23
#define   DBG_PHYADMUX_ATID_EN0__ATID23_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID23_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID22_EN___M   0x00400000
#define   DBG_PHYADMUX_ATID_EN0__ATID22_EN___S                22
#define   DBG_PHYADMUX_ATID_EN0__ATID22_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID22_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID21_EN___M   0x00200000
#define   DBG_PHYADMUX_ATID_EN0__ATID21_EN___S                21
#define   DBG_PHYADMUX_ATID_EN0__ATID21_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID21_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID20_EN___M   0x00100000
#define   DBG_PHYADMUX_ATID_EN0__ATID20_EN___S                20
#define   DBG_PHYADMUX_ATID_EN0__ATID20_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID20_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID19_EN___M   0x00080000
#define   DBG_PHYADMUX_ATID_EN0__ATID19_EN___S                19
#define   DBG_PHYADMUX_ATID_EN0__ATID19_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID19_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID18_EN___M   0x00040000
#define   DBG_PHYADMUX_ATID_EN0__ATID18_EN___S                18
#define   DBG_PHYADMUX_ATID_EN0__ATID18_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID18_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID17_EN___M   0x00020000
#define   DBG_PHYADMUX_ATID_EN0__ATID17_EN___S                17
#define   DBG_PHYADMUX_ATID_EN0__ATID17_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID17_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID16_EN___M   0x00010000
#define   DBG_PHYADMUX_ATID_EN0__ATID16_EN___S                16
#define   DBG_PHYADMUX_ATID_EN0__ATID16_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID16_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID15_EN___M   0x00008000
#define   DBG_PHYADMUX_ATID_EN0__ATID15_EN___S                15
#define   DBG_PHYADMUX_ATID_EN0__ATID15_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID15_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID14_EN___M   0x00004000
#define   DBG_PHYADMUX_ATID_EN0__ATID14_EN___S                14
#define   DBG_PHYADMUX_ATID_EN0__ATID14_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID14_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID13_EN___M   0x00002000
#define   DBG_PHYADMUX_ATID_EN0__ATID13_EN___S                13
#define   DBG_PHYADMUX_ATID_EN0__ATID13_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID13_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID12_EN___M   0x00001000
#define   DBG_PHYADMUX_ATID_EN0__ATID12_EN___S                12
#define   DBG_PHYADMUX_ATID_EN0__ATID12_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID12_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID11_EN___M   0x00000800
#define   DBG_PHYADMUX_ATID_EN0__ATID11_EN___S                11
#define   DBG_PHYADMUX_ATID_EN0__ATID11_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID11_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID10_EN___M   0x00000400
#define   DBG_PHYADMUX_ATID_EN0__ATID10_EN___S                10
#define   DBG_PHYADMUX_ATID_EN0__ATID10_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID10_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID9_EN___M    0x00000200
#define   DBG_PHYADMUX_ATID_EN0__ATID9_EN___S                  9
#define   DBG_PHYADMUX_ATID_EN0__ATID9_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID9_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID8_EN___M    0x00000100
#define   DBG_PHYADMUX_ATID_EN0__ATID8_EN___S                  8
#define   DBG_PHYADMUX_ATID_EN0__ATID8_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID8_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID7_EN___M    0x00000080
#define   DBG_PHYADMUX_ATID_EN0__ATID7_EN___S                  7
#define   DBG_PHYADMUX_ATID_EN0__ATID7_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID7_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID6_EN___M    0x00000040
#define   DBG_PHYADMUX_ATID_EN0__ATID6_EN___S                  6
#define   DBG_PHYADMUX_ATID_EN0__ATID6_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID6_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID5_EN___M    0x00000020
#define   DBG_PHYADMUX_ATID_EN0__ATID5_EN___S                  5
#define   DBG_PHYADMUX_ATID_EN0__ATID5_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID5_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID4_EN___M    0x00000010
#define   DBG_PHYADMUX_ATID_EN0__ATID4_EN___S                  4
#define   DBG_PHYADMUX_ATID_EN0__ATID4_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID4_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID3_EN___M    0x00000008
#define   DBG_PHYADMUX_ATID_EN0__ATID3_EN___S                  3
#define   DBG_PHYADMUX_ATID_EN0__ATID3_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID3_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID2_EN___M    0x00000004
#define   DBG_PHYADMUX_ATID_EN0__ATID2_EN___S                  2
#define   DBG_PHYADMUX_ATID_EN0__ATID2_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID2_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID1_EN___M    0x00000002
#define   DBG_PHYADMUX_ATID_EN0__ATID1_EN___S                  1
#define   DBG_PHYADMUX_ATID_EN0__ATID1_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID1_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0__ATID0_EN___M    0x00000001
#define   DBG_PHYADMUX_ATID_EN0__ATID0_EN___S                  0
#define   DBG_PHYADMUX_ATID_EN0__ATID0_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN0__ATID0_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN0___M              0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_EN0___S                            0

#define DBG_PHYADMUX_ATID_EN1                     (0x00BC6004)
#define   DBG_PHYADMUX_ATID_EN1___RWC               QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_EN1___POR            0xFFFFFFFF
#define   DBG_PHYADMUX_ATID_EN1__ATID63_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID62_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID61_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID60_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID59_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID58_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID57_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID56_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID55_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID54_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID53_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID52_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID51_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID50_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID49_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID48_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID47_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID46_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID45_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID44_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID43_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID42_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID41_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID40_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID39_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID38_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID37_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID36_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID35_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID34_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID33_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID32_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID63_EN___M   0x80000000
#define   DBG_PHYADMUX_ATID_EN1__ATID63_EN___S                31
#define   DBG_PHYADMUX_ATID_EN1__ATID63_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID63_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID62_EN___M   0x40000000
#define   DBG_PHYADMUX_ATID_EN1__ATID62_EN___S                30
#define   DBG_PHYADMUX_ATID_EN1__ATID62_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID62_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID61_EN___M   0x20000000
#define   DBG_PHYADMUX_ATID_EN1__ATID61_EN___S                29
#define   DBG_PHYADMUX_ATID_EN1__ATID61_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID61_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID60_EN___M   0x10000000
#define   DBG_PHYADMUX_ATID_EN1__ATID60_EN___S                28
#define   DBG_PHYADMUX_ATID_EN1__ATID60_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID60_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID59_EN___M   0x08000000
#define   DBG_PHYADMUX_ATID_EN1__ATID59_EN___S                27
#define   DBG_PHYADMUX_ATID_EN1__ATID59_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID59_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID58_EN___M   0x04000000
#define   DBG_PHYADMUX_ATID_EN1__ATID58_EN___S                26
#define   DBG_PHYADMUX_ATID_EN1__ATID58_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID58_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID57_EN___M   0x02000000
#define   DBG_PHYADMUX_ATID_EN1__ATID57_EN___S                25
#define   DBG_PHYADMUX_ATID_EN1__ATID57_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID57_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID56_EN___M   0x01000000
#define   DBG_PHYADMUX_ATID_EN1__ATID56_EN___S                24
#define   DBG_PHYADMUX_ATID_EN1__ATID56_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID56_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID55_EN___M   0x00800000
#define   DBG_PHYADMUX_ATID_EN1__ATID55_EN___S                23
#define   DBG_PHYADMUX_ATID_EN1__ATID55_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID55_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID54_EN___M   0x00400000
#define   DBG_PHYADMUX_ATID_EN1__ATID54_EN___S                22
#define   DBG_PHYADMUX_ATID_EN1__ATID54_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID54_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID53_EN___M   0x00200000
#define   DBG_PHYADMUX_ATID_EN1__ATID53_EN___S                21
#define   DBG_PHYADMUX_ATID_EN1__ATID53_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID53_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID52_EN___M   0x00100000
#define   DBG_PHYADMUX_ATID_EN1__ATID52_EN___S                20
#define   DBG_PHYADMUX_ATID_EN1__ATID52_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID52_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID51_EN___M   0x00080000
#define   DBG_PHYADMUX_ATID_EN1__ATID51_EN___S                19
#define   DBG_PHYADMUX_ATID_EN1__ATID51_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID51_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID50_EN___M   0x00040000
#define   DBG_PHYADMUX_ATID_EN1__ATID50_EN___S                18
#define   DBG_PHYADMUX_ATID_EN1__ATID50_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID50_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID49_EN___M   0x00020000
#define   DBG_PHYADMUX_ATID_EN1__ATID49_EN___S                17
#define   DBG_PHYADMUX_ATID_EN1__ATID49_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID49_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID48_EN___M   0x00010000
#define   DBG_PHYADMUX_ATID_EN1__ATID48_EN___S                16
#define   DBG_PHYADMUX_ATID_EN1__ATID48_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID48_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID47_EN___M   0x00008000
#define   DBG_PHYADMUX_ATID_EN1__ATID47_EN___S                15
#define   DBG_PHYADMUX_ATID_EN1__ATID47_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID47_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID46_EN___M   0x00004000
#define   DBG_PHYADMUX_ATID_EN1__ATID46_EN___S                14
#define   DBG_PHYADMUX_ATID_EN1__ATID46_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID46_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID45_EN___M   0x00002000
#define   DBG_PHYADMUX_ATID_EN1__ATID45_EN___S                13
#define   DBG_PHYADMUX_ATID_EN1__ATID45_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID45_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID44_EN___M   0x00001000
#define   DBG_PHYADMUX_ATID_EN1__ATID44_EN___S                12
#define   DBG_PHYADMUX_ATID_EN1__ATID44_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID44_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID43_EN___M   0x00000800
#define   DBG_PHYADMUX_ATID_EN1__ATID43_EN___S                11
#define   DBG_PHYADMUX_ATID_EN1__ATID43_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID43_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID42_EN___M   0x00000400
#define   DBG_PHYADMUX_ATID_EN1__ATID42_EN___S                10
#define   DBG_PHYADMUX_ATID_EN1__ATID42_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID42_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID41_EN___M   0x00000200
#define   DBG_PHYADMUX_ATID_EN1__ATID41_EN___S                 9
#define   DBG_PHYADMUX_ATID_EN1__ATID41_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID41_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID40_EN___M   0x00000100
#define   DBG_PHYADMUX_ATID_EN1__ATID40_EN___S                 8
#define   DBG_PHYADMUX_ATID_EN1__ATID40_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID40_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID39_EN___M   0x00000080
#define   DBG_PHYADMUX_ATID_EN1__ATID39_EN___S                 7
#define   DBG_PHYADMUX_ATID_EN1__ATID39_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID39_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID38_EN___M   0x00000040
#define   DBG_PHYADMUX_ATID_EN1__ATID38_EN___S                 6
#define   DBG_PHYADMUX_ATID_EN1__ATID38_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID38_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID37_EN___M   0x00000020
#define   DBG_PHYADMUX_ATID_EN1__ATID37_EN___S                 5
#define   DBG_PHYADMUX_ATID_EN1__ATID37_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID37_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID36_EN___M   0x00000010
#define   DBG_PHYADMUX_ATID_EN1__ATID36_EN___S                 4
#define   DBG_PHYADMUX_ATID_EN1__ATID36_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID36_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID35_EN___M   0x00000008
#define   DBG_PHYADMUX_ATID_EN1__ATID35_EN___S                 3
#define   DBG_PHYADMUX_ATID_EN1__ATID35_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID35_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID34_EN___M   0x00000004
#define   DBG_PHYADMUX_ATID_EN1__ATID34_EN___S                 2
#define   DBG_PHYADMUX_ATID_EN1__ATID34_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID34_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID33_EN___M   0x00000002
#define   DBG_PHYADMUX_ATID_EN1__ATID33_EN___S                 1
#define   DBG_PHYADMUX_ATID_EN1__ATID33_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID33_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1__ATID32_EN___M   0x00000001
#define   DBG_PHYADMUX_ATID_EN1__ATID32_EN___S                 0
#define   DBG_PHYADMUX_ATID_EN1__ATID32_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN1__ATID32_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN1___M              0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_EN1___S                            0

#define DBG_PHYADMUX_ATID_EN2                     (0x00BC6008)
#define   DBG_PHYADMUX_ATID_EN2___RWC               QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_EN2___POR            0xFFFFFFFF
#define   DBG_PHYADMUX_ATID_EN2__ATID95_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID94_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID93_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID92_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID91_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID90_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID89_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID88_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID87_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID86_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID85_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID84_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID83_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID82_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID81_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID80_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID79_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID78_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID77_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID76_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID75_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID74_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID73_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID72_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID71_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID70_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID69_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID68_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID67_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID66_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID65_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID64_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID95_EN___M   0x80000000
#define   DBG_PHYADMUX_ATID_EN2__ATID95_EN___S                31
#define   DBG_PHYADMUX_ATID_EN2__ATID95_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID95_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID94_EN___M   0x40000000
#define   DBG_PHYADMUX_ATID_EN2__ATID94_EN___S                30
#define   DBG_PHYADMUX_ATID_EN2__ATID94_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID94_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID93_EN___M   0x20000000
#define   DBG_PHYADMUX_ATID_EN2__ATID93_EN___S                29
#define   DBG_PHYADMUX_ATID_EN2__ATID93_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID93_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID92_EN___M   0x10000000
#define   DBG_PHYADMUX_ATID_EN2__ATID92_EN___S                28
#define   DBG_PHYADMUX_ATID_EN2__ATID92_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID92_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID91_EN___M   0x08000000
#define   DBG_PHYADMUX_ATID_EN2__ATID91_EN___S                27
#define   DBG_PHYADMUX_ATID_EN2__ATID91_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID91_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID90_EN___M   0x04000000
#define   DBG_PHYADMUX_ATID_EN2__ATID90_EN___S                26
#define   DBG_PHYADMUX_ATID_EN2__ATID90_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID90_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID89_EN___M   0x02000000
#define   DBG_PHYADMUX_ATID_EN2__ATID89_EN___S                25
#define   DBG_PHYADMUX_ATID_EN2__ATID89_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID89_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID88_EN___M   0x01000000
#define   DBG_PHYADMUX_ATID_EN2__ATID88_EN___S                24
#define   DBG_PHYADMUX_ATID_EN2__ATID88_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID88_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID87_EN___M   0x00800000
#define   DBG_PHYADMUX_ATID_EN2__ATID87_EN___S                23
#define   DBG_PHYADMUX_ATID_EN2__ATID87_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID87_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID86_EN___M   0x00400000
#define   DBG_PHYADMUX_ATID_EN2__ATID86_EN___S                22
#define   DBG_PHYADMUX_ATID_EN2__ATID86_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID86_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID85_EN___M   0x00200000
#define   DBG_PHYADMUX_ATID_EN2__ATID85_EN___S                21
#define   DBG_PHYADMUX_ATID_EN2__ATID85_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID85_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID84_EN___M   0x00100000
#define   DBG_PHYADMUX_ATID_EN2__ATID84_EN___S                20
#define   DBG_PHYADMUX_ATID_EN2__ATID84_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID84_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID83_EN___M   0x00080000
#define   DBG_PHYADMUX_ATID_EN2__ATID83_EN___S                19
#define   DBG_PHYADMUX_ATID_EN2__ATID83_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID83_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID82_EN___M   0x00040000
#define   DBG_PHYADMUX_ATID_EN2__ATID82_EN___S                18
#define   DBG_PHYADMUX_ATID_EN2__ATID82_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID82_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID81_EN___M   0x00020000
#define   DBG_PHYADMUX_ATID_EN2__ATID81_EN___S                17
#define   DBG_PHYADMUX_ATID_EN2__ATID81_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID81_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID80_EN___M   0x00010000
#define   DBG_PHYADMUX_ATID_EN2__ATID80_EN___S                16
#define   DBG_PHYADMUX_ATID_EN2__ATID80_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID80_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID79_EN___M   0x00008000
#define   DBG_PHYADMUX_ATID_EN2__ATID79_EN___S                15
#define   DBG_PHYADMUX_ATID_EN2__ATID79_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID79_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID78_EN___M   0x00004000
#define   DBG_PHYADMUX_ATID_EN2__ATID78_EN___S                14
#define   DBG_PHYADMUX_ATID_EN2__ATID78_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID78_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID77_EN___M   0x00002000
#define   DBG_PHYADMUX_ATID_EN2__ATID77_EN___S                13
#define   DBG_PHYADMUX_ATID_EN2__ATID77_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID77_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID76_EN___M   0x00001000
#define   DBG_PHYADMUX_ATID_EN2__ATID76_EN___S                12
#define   DBG_PHYADMUX_ATID_EN2__ATID76_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID76_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID75_EN___M   0x00000800
#define   DBG_PHYADMUX_ATID_EN2__ATID75_EN___S                11
#define   DBG_PHYADMUX_ATID_EN2__ATID75_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID75_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID74_EN___M   0x00000400
#define   DBG_PHYADMUX_ATID_EN2__ATID74_EN___S                10
#define   DBG_PHYADMUX_ATID_EN2__ATID74_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID74_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID73_EN___M   0x00000200
#define   DBG_PHYADMUX_ATID_EN2__ATID73_EN___S                 9
#define   DBG_PHYADMUX_ATID_EN2__ATID73_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID73_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID72_EN___M   0x00000100
#define   DBG_PHYADMUX_ATID_EN2__ATID72_EN___S                 8
#define   DBG_PHYADMUX_ATID_EN2__ATID72_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID72_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID71_EN___M   0x00000080
#define   DBG_PHYADMUX_ATID_EN2__ATID71_EN___S                 7
#define   DBG_PHYADMUX_ATID_EN2__ATID71_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID71_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID70_EN___M   0x00000040
#define   DBG_PHYADMUX_ATID_EN2__ATID70_EN___S                 6
#define   DBG_PHYADMUX_ATID_EN2__ATID70_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID70_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID69_EN___M   0x00000020
#define   DBG_PHYADMUX_ATID_EN2__ATID69_EN___S                 5
#define   DBG_PHYADMUX_ATID_EN2__ATID69_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID69_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID68_EN___M   0x00000010
#define   DBG_PHYADMUX_ATID_EN2__ATID68_EN___S                 4
#define   DBG_PHYADMUX_ATID_EN2__ATID68_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID68_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID67_EN___M   0x00000008
#define   DBG_PHYADMUX_ATID_EN2__ATID67_EN___S                 3
#define   DBG_PHYADMUX_ATID_EN2__ATID67_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID67_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID66_EN___M   0x00000004
#define   DBG_PHYADMUX_ATID_EN2__ATID66_EN___S                 2
#define   DBG_PHYADMUX_ATID_EN2__ATID66_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID66_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID65_EN___M   0x00000002
#define   DBG_PHYADMUX_ATID_EN2__ATID65_EN___S                 1
#define   DBG_PHYADMUX_ATID_EN2__ATID65_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID65_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2__ATID64_EN___M   0x00000001
#define   DBG_PHYADMUX_ATID_EN2__ATID64_EN___S                 0
#define   DBG_PHYADMUX_ATID_EN2__ATID64_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN2__ATID64_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN2___M              0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_EN2___S                            0

#define DBG_PHYADMUX_ATID_EN3                     (0x00BC600C)
#define   DBG_PHYADMUX_ATID_EN3___RWC               QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_EN3___POR            0xFFFFFFFF
#define   DBG_PHYADMUX_ATID_EN3__ATID127_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID126_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID125_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID124_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID123_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID122_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID121_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID120_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID119_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID118_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID117_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID116_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID115_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID114_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID113_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID112_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID111_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID110_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID109_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID108_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID107_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID106_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID105_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID104_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID103_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID102_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID101_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID100_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID99_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID98_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID97_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID96_EN___POR 0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID127_EN___M  0x80000000
#define   DBG_PHYADMUX_ATID_EN3__ATID127_EN___S               31
#define   DBG_PHYADMUX_ATID_EN3__ATID127_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID127_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID126_EN___M  0x40000000
#define   DBG_PHYADMUX_ATID_EN3__ATID126_EN___S               30
#define   DBG_PHYADMUX_ATID_EN3__ATID126_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID126_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID125_EN___M  0x20000000
#define   DBG_PHYADMUX_ATID_EN3__ATID125_EN___S               29
#define   DBG_PHYADMUX_ATID_EN3__ATID125_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID125_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID124_EN___M  0x10000000
#define   DBG_PHYADMUX_ATID_EN3__ATID124_EN___S               28
#define   DBG_PHYADMUX_ATID_EN3__ATID124_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID124_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID123_EN___M  0x08000000
#define   DBG_PHYADMUX_ATID_EN3__ATID123_EN___S               27
#define   DBG_PHYADMUX_ATID_EN3__ATID123_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID123_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID122_EN___M  0x04000000
#define   DBG_PHYADMUX_ATID_EN3__ATID122_EN___S               26
#define   DBG_PHYADMUX_ATID_EN3__ATID122_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID122_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID121_EN___M  0x02000000
#define   DBG_PHYADMUX_ATID_EN3__ATID121_EN___S               25
#define   DBG_PHYADMUX_ATID_EN3__ATID121_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID121_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID120_EN___M  0x01000000
#define   DBG_PHYADMUX_ATID_EN3__ATID120_EN___S               24
#define   DBG_PHYADMUX_ATID_EN3__ATID120_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID120_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID119_EN___M  0x00800000
#define   DBG_PHYADMUX_ATID_EN3__ATID119_EN___S               23
#define   DBG_PHYADMUX_ATID_EN3__ATID119_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID119_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID118_EN___M  0x00400000
#define   DBG_PHYADMUX_ATID_EN3__ATID118_EN___S               22
#define   DBG_PHYADMUX_ATID_EN3__ATID118_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID118_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID117_EN___M  0x00200000
#define   DBG_PHYADMUX_ATID_EN3__ATID117_EN___S               21
#define   DBG_PHYADMUX_ATID_EN3__ATID117_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID117_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID116_EN___M  0x00100000
#define   DBG_PHYADMUX_ATID_EN3__ATID116_EN___S               20
#define   DBG_PHYADMUX_ATID_EN3__ATID116_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID116_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID115_EN___M  0x00080000
#define   DBG_PHYADMUX_ATID_EN3__ATID115_EN___S               19
#define   DBG_PHYADMUX_ATID_EN3__ATID115_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID115_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID114_EN___M  0x00040000
#define   DBG_PHYADMUX_ATID_EN3__ATID114_EN___S               18
#define   DBG_PHYADMUX_ATID_EN3__ATID114_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID114_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID113_EN___M  0x00020000
#define   DBG_PHYADMUX_ATID_EN3__ATID113_EN___S               17
#define   DBG_PHYADMUX_ATID_EN3__ATID113_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID113_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID112_EN___M  0x00010000
#define   DBG_PHYADMUX_ATID_EN3__ATID112_EN___S               16
#define   DBG_PHYADMUX_ATID_EN3__ATID112_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID112_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID111_EN___M  0x00008000
#define   DBG_PHYADMUX_ATID_EN3__ATID111_EN___S               15
#define   DBG_PHYADMUX_ATID_EN3__ATID111_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID111_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID110_EN___M  0x00004000
#define   DBG_PHYADMUX_ATID_EN3__ATID110_EN___S               14
#define   DBG_PHYADMUX_ATID_EN3__ATID110_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID110_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID109_EN___M  0x00002000
#define   DBG_PHYADMUX_ATID_EN3__ATID109_EN___S               13
#define   DBG_PHYADMUX_ATID_EN3__ATID109_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID109_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID108_EN___M  0x00001000
#define   DBG_PHYADMUX_ATID_EN3__ATID108_EN___S               12
#define   DBG_PHYADMUX_ATID_EN3__ATID108_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID108_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID107_EN___M  0x00000800
#define   DBG_PHYADMUX_ATID_EN3__ATID107_EN___S               11
#define   DBG_PHYADMUX_ATID_EN3__ATID107_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID107_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID106_EN___M  0x00000400
#define   DBG_PHYADMUX_ATID_EN3__ATID106_EN___S               10
#define   DBG_PHYADMUX_ATID_EN3__ATID106_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID106_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID105_EN___M  0x00000200
#define   DBG_PHYADMUX_ATID_EN3__ATID105_EN___S                9
#define   DBG_PHYADMUX_ATID_EN3__ATID105_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID105_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID104_EN___M  0x00000100
#define   DBG_PHYADMUX_ATID_EN3__ATID104_EN___S                8
#define   DBG_PHYADMUX_ATID_EN3__ATID104_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID104_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID103_EN___M  0x00000080
#define   DBG_PHYADMUX_ATID_EN3__ATID103_EN___S                7
#define   DBG_PHYADMUX_ATID_EN3__ATID103_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID103_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID102_EN___M  0x00000040
#define   DBG_PHYADMUX_ATID_EN3__ATID102_EN___S                6
#define   DBG_PHYADMUX_ATID_EN3__ATID102_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID102_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID101_EN___M  0x00000020
#define   DBG_PHYADMUX_ATID_EN3__ATID101_EN___S                5
#define   DBG_PHYADMUX_ATID_EN3__ATID101_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID101_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID100_EN___M  0x00000010
#define   DBG_PHYADMUX_ATID_EN3__ATID100_EN___S                4
#define   DBG_PHYADMUX_ATID_EN3__ATID100_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID100_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID99_EN___M   0x00000008
#define   DBG_PHYADMUX_ATID_EN3__ATID99_EN___S                 3
#define   DBG_PHYADMUX_ATID_EN3__ATID99_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID99_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID98_EN___M   0x00000004
#define   DBG_PHYADMUX_ATID_EN3__ATID98_EN___S                 2
#define   DBG_PHYADMUX_ATID_EN3__ATID98_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID98_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID97_EN___M   0x00000002
#define   DBG_PHYADMUX_ATID_EN3__ATID97_EN___S                 1
#define   DBG_PHYADMUX_ATID_EN3__ATID97_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID97_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3__ATID96_EN___M   0x00000001
#define   DBG_PHYADMUX_ATID_EN3__ATID96_EN___S                 0
#define   DBG_PHYADMUX_ATID_EN3__ATID96_EN__DISABLE             0x0
#define   DBG_PHYADMUX_ATID_EN3__ATID96_EN__ENABLE             0x1
#define   DBG_PHYADMUX_ATID_EN3___M              0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_EN3___S                            0

#define DBG_PHYADMUX_ATID_SEL0                    (0x00BC6010)
#define   DBG_PHYADMUX_ATID_SEL0___RWC              QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_SEL0___POR           0x00000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___M 0x80000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___S              31
#define   DBG_PHYADMUX_ATID_SEL0__ATID31_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID31_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___M 0x40000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___S              30
#define   DBG_PHYADMUX_ATID_SEL0__ATID30_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID30_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___M 0x20000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___S              29
#define   DBG_PHYADMUX_ATID_SEL0__ATID29_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID29_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___M 0x10000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___S              28
#define   DBG_PHYADMUX_ATID_SEL0__ATID28_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID28_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___M 0x08000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___S              27
#define   DBG_PHYADMUX_ATID_SEL0__ATID27_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID27_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___M 0x04000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___S              26
#define   DBG_PHYADMUX_ATID_SEL0__ATID26_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID26_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___M 0x02000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___S              25
#define   DBG_PHYADMUX_ATID_SEL0__ATID25_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID25_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___M 0x01000000
#define   DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___S              24
#define   DBG_PHYADMUX_ATID_SEL0__ATID24_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID24_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___M 0x00800000
#define   DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___S              23
#define   DBG_PHYADMUX_ATID_SEL0__ATID23_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID23_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___M 0x00400000
#define   DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___S              22
#define   DBG_PHYADMUX_ATID_SEL0__ATID22_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID22_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___M 0x00200000
#define   DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___S              21
#define   DBG_PHYADMUX_ATID_SEL0__ATID21_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID21_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___M 0x00100000
#define   DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___S              20
#define   DBG_PHYADMUX_ATID_SEL0__ATID20_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID20_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___M 0x00080000
#define   DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___S              19
#define   DBG_PHYADMUX_ATID_SEL0__ATID19_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID19_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___M 0x00040000
#define   DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___S              18
#define   DBG_PHYADMUX_ATID_SEL0__ATID18_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID18_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___M 0x00020000
#define   DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___S              17
#define   DBG_PHYADMUX_ATID_SEL0__ATID17_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID17_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___M 0x00010000
#define   DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___S              16
#define   DBG_PHYADMUX_ATID_SEL0__ATID16_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID16_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___M 0x00008000
#define   DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___S              15
#define   DBG_PHYADMUX_ATID_SEL0__ATID15_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID15_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___M 0x00004000
#define   DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___S              14
#define   DBG_PHYADMUX_ATID_SEL0__ATID14_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID14_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___M 0x00002000
#define   DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___S              13
#define   DBG_PHYADMUX_ATID_SEL0__ATID13_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID13_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___M 0x00001000
#define   DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___S              12
#define   DBG_PHYADMUX_ATID_SEL0__ATID12_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID12_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___M 0x00000800
#define   DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___S              11
#define   DBG_PHYADMUX_ATID_SEL0__ATID11_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID11_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___M 0x00000400
#define   DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___S              10
#define   DBG_PHYADMUX_ATID_SEL0__ATID10_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID10_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___M  0x00000200
#define   DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___S                9
#define   DBG_PHYADMUX_ATID_SEL0__ATID9_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID9_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___M  0x00000100
#define   DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___S                8
#define   DBG_PHYADMUX_ATID_SEL0__ATID8_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID8_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___M  0x00000080
#define   DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___S                7
#define   DBG_PHYADMUX_ATID_SEL0__ATID7_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID7_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___M  0x00000040
#define   DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___S                6
#define   DBG_PHYADMUX_ATID_SEL0__ATID6_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID6_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___M  0x00000020
#define   DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___S                5
#define   DBG_PHYADMUX_ATID_SEL0__ATID5_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID5_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___M  0x00000010
#define   DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___S                4
#define   DBG_PHYADMUX_ATID_SEL0__ATID4_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID4_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___M  0x00000008
#define   DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___S                3
#define   DBG_PHYADMUX_ATID_SEL0__ATID3_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID3_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___M  0x00000004
#define   DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___S                2
#define   DBG_PHYADMUX_ATID_SEL0__ATID2_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID2_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___M  0x00000002
#define   DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___S                1
#define   DBG_PHYADMUX_ATID_SEL0__ATID1_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID1_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___M  0x00000001
#define   DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___S                0
#define   DBG_PHYADMUX_ATID_SEL0__ATID0_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL0__ATID0_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL0___M             0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_SEL0___S                           0

#define DBG_PHYADMUX_ATID_SEL1                    (0x00BC6014)
#define   DBG_PHYADMUX_ATID_SEL1___RWC              QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_SEL1___POR           0x00000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___M 0x80000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___S              31
#define   DBG_PHYADMUX_ATID_SEL1__ATID63_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID63_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___M 0x40000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___S              30
#define   DBG_PHYADMUX_ATID_SEL1__ATID62_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID62_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___M 0x20000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___S              29
#define   DBG_PHYADMUX_ATID_SEL1__ATID61_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID61_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___M 0x10000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___S              28
#define   DBG_PHYADMUX_ATID_SEL1__ATID60_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID60_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___M 0x08000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___S              27
#define   DBG_PHYADMUX_ATID_SEL1__ATID59_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID59_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___M 0x04000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___S              26
#define   DBG_PHYADMUX_ATID_SEL1__ATID58_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID58_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___M 0x02000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___S              25
#define   DBG_PHYADMUX_ATID_SEL1__ATID57_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID57_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___M 0x01000000
#define   DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___S              24
#define   DBG_PHYADMUX_ATID_SEL1__ATID56_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID56_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___M 0x00800000
#define   DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___S              23
#define   DBG_PHYADMUX_ATID_SEL1__ATID55_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID55_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___M 0x00400000
#define   DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___S              22
#define   DBG_PHYADMUX_ATID_SEL1__ATID54_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID54_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___M 0x00200000
#define   DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___S              21
#define   DBG_PHYADMUX_ATID_SEL1__ATID53_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID53_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___M 0x00100000
#define   DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___S              20
#define   DBG_PHYADMUX_ATID_SEL1__ATID52_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID52_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___M 0x00080000
#define   DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___S              19
#define   DBG_PHYADMUX_ATID_SEL1__ATID51_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID51_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___M 0x00040000
#define   DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___S              18
#define   DBG_PHYADMUX_ATID_SEL1__ATID50_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID50_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___M 0x00020000
#define   DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___S              17
#define   DBG_PHYADMUX_ATID_SEL1__ATID49_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID49_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___M 0x00010000
#define   DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___S              16
#define   DBG_PHYADMUX_ATID_SEL1__ATID48_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID48_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___M 0x00008000
#define   DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___S              15
#define   DBG_PHYADMUX_ATID_SEL1__ATID47_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID47_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___M 0x00004000
#define   DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___S              14
#define   DBG_PHYADMUX_ATID_SEL1__ATID46_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID46_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___M 0x00002000
#define   DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___S              13
#define   DBG_PHYADMUX_ATID_SEL1__ATID45_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID45_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___M 0x00001000
#define   DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___S              12
#define   DBG_PHYADMUX_ATID_SEL1__ATID44_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID44_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___M 0x00000800
#define   DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___S              11
#define   DBG_PHYADMUX_ATID_SEL1__ATID43_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID43_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___M 0x00000400
#define   DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___S              10
#define   DBG_PHYADMUX_ATID_SEL1__ATID42_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID42_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___M 0x00000200
#define   DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___S               9
#define   DBG_PHYADMUX_ATID_SEL1__ATID41_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID41_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___M 0x00000100
#define   DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___S               8
#define   DBG_PHYADMUX_ATID_SEL1__ATID40_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID40_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___M 0x00000080
#define   DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___S               7
#define   DBG_PHYADMUX_ATID_SEL1__ATID39_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID39_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___M 0x00000040
#define   DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___S               6
#define   DBG_PHYADMUX_ATID_SEL1__ATID38_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID38_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___M 0x00000020
#define   DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___S               5
#define   DBG_PHYADMUX_ATID_SEL1__ATID37_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID37_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___M 0x00000010
#define   DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___S               4
#define   DBG_PHYADMUX_ATID_SEL1__ATID36_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID36_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___M 0x00000008
#define   DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___S               3
#define   DBG_PHYADMUX_ATID_SEL1__ATID35_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID35_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___M 0x00000004
#define   DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___S               2
#define   DBG_PHYADMUX_ATID_SEL1__ATID34_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID34_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___M 0x00000002
#define   DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___S               1
#define   DBG_PHYADMUX_ATID_SEL1__ATID33_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID33_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___M 0x00000001
#define   DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___S               0
#define   DBG_PHYADMUX_ATID_SEL1__ATID32_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL1__ATID32_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL1___M             0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_SEL1___S                           0

#define DBG_PHYADMUX_ATID_SEL2                    (0x00BC6018)
#define   DBG_PHYADMUX_ATID_SEL2___RWC              QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_SEL2___POR           0x00000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___M 0x80000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___S              31
#define   DBG_PHYADMUX_ATID_SEL2__ATID95_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID95_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___M 0x40000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___S              30
#define   DBG_PHYADMUX_ATID_SEL2__ATID94_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID94_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___M 0x20000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___S              29
#define   DBG_PHYADMUX_ATID_SEL2__ATID93_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID93_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___M 0x10000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___S              28
#define   DBG_PHYADMUX_ATID_SEL2__ATID92_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID92_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___M 0x08000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___S              27
#define   DBG_PHYADMUX_ATID_SEL2__ATID91_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID91_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___M 0x04000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___S              26
#define   DBG_PHYADMUX_ATID_SEL2__ATID90_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID90_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___M 0x02000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___S              25
#define   DBG_PHYADMUX_ATID_SEL2__ATID89_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID89_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___M 0x01000000
#define   DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___S              24
#define   DBG_PHYADMUX_ATID_SEL2__ATID88_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID88_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___M 0x00800000
#define   DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___S              23
#define   DBG_PHYADMUX_ATID_SEL2__ATID87_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID87_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___M 0x00400000
#define   DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___S              22
#define   DBG_PHYADMUX_ATID_SEL2__ATID86_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID86_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___M 0x00200000
#define   DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___S              21
#define   DBG_PHYADMUX_ATID_SEL2__ATID85_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID85_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___M 0x00100000
#define   DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___S              20
#define   DBG_PHYADMUX_ATID_SEL2__ATID84_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID84_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___M 0x00080000
#define   DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___S              19
#define   DBG_PHYADMUX_ATID_SEL2__ATID83_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID83_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___M 0x00040000
#define   DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___S              18
#define   DBG_PHYADMUX_ATID_SEL2__ATID82_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID82_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___M 0x00020000
#define   DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___S              17
#define   DBG_PHYADMUX_ATID_SEL2__ATID81_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID81_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___M 0x00010000
#define   DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___S              16
#define   DBG_PHYADMUX_ATID_SEL2__ATID80_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID80_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___M 0x00008000
#define   DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___S              15
#define   DBG_PHYADMUX_ATID_SEL2__ATID79_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID79_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___M 0x00004000
#define   DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___S              14
#define   DBG_PHYADMUX_ATID_SEL2__ATID78_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID78_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___M 0x00002000
#define   DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___S              13
#define   DBG_PHYADMUX_ATID_SEL2__ATID77_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID77_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___M 0x00001000
#define   DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___S              12
#define   DBG_PHYADMUX_ATID_SEL2__ATID76_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID76_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___M 0x00000800
#define   DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___S              11
#define   DBG_PHYADMUX_ATID_SEL2__ATID75_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID75_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___M 0x00000400
#define   DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___S              10
#define   DBG_PHYADMUX_ATID_SEL2__ATID74_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID74_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___M 0x00000200
#define   DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___S               9
#define   DBG_PHYADMUX_ATID_SEL2__ATID73_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID73_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___M 0x00000100
#define   DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___S               8
#define   DBG_PHYADMUX_ATID_SEL2__ATID72_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID72_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___M 0x00000080
#define   DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___S               7
#define   DBG_PHYADMUX_ATID_SEL2__ATID71_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID71_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___M 0x00000040
#define   DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___S               6
#define   DBG_PHYADMUX_ATID_SEL2__ATID70_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID70_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___M 0x00000020
#define   DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___S               5
#define   DBG_PHYADMUX_ATID_SEL2__ATID69_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID69_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___M 0x00000010
#define   DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___S               4
#define   DBG_PHYADMUX_ATID_SEL2__ATID68_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID68_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___M 0x00000008
#define   DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___S               3
#define   DBG_PHYADMUX_ATID_SEL2__ATID67_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID67_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___M 0x00000004
#define   DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___S               2
#define   DBG_PHYADMUX_ATID_SEL2__ATID66_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID66_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___M 0x00000002
#define   DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___S               1
#define   DBG_PHYADMUX_ATID_SEL2__ATID65_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID65_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___M 0x00000001
#define   DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___S               0
#define   DBG_PHYADMUX_ATID_SEL2__ATID64_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL2__ATID64_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL2___M             0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_SEL2___S                           0

#define DBG_PHYADMUX_ATID_SEL3                    (0x00BC601C)
#define   DBG_PHYADMUX_ATID_SEL3___RWC              QCSR_REG_RW    
#define   DBG_PHYADMUX_ATID_SEL3___POR           0x00000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___POR 0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___M 0x80000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___S              31
#define   DBG_PHYADMUX_ATID_SEL3__ATID127_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID127_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___M 0x40000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___S              30
#define   DBG_PHYADMUX_ATID_SEL3__ATID126_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID126_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___M 0x20000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___S              29
#define   DBG_PHYADMUX_ATID_SEL3__ATID125_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID125_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___M 0x10000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___S              28
#define   DBG_PHYADMUX_ATID_SEL3__ATID124_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID124_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___M 0x08000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___S              27
#define   DBG_PHYADMUX_ATID_SEL3__ATID123_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID123_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___M 0x04000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___S              26
#define   DBG_PHYADMUX_ATID_SEL3__ATID122_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID122_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___M 0x02000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___S              25
#define   DBG_PHYADMUX_ATID_SEL3__ATID121_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID121_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___M 0x01000000
#define   DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___S              24
#define   DBG_PHYADMUX_ATID_SEL3__ATID120_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID120_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___M 0x00800000
#define   DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___S              23
#define   DBG_PHYADMUX_ATID_SEL3__ATID119_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID119_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___M 0x00400000
#define   DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___S              22
#define   DBG_PHYADMUX_ATID_SEL3__ATID118_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID118_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___M 0x00200000
#define   DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___S              21
#define   DBG_PHYADMUX_ATID_SEL3__ATID117_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID117_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___M 0x00100000
#define   DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___S              20
#define   DBG_PHYADMUX_ATID_SEL3__ATID116_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID116_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___M 0x00080000
#define   DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___S              19
#define   DBG_PHYADMUX_ATID_SEL3__ATID115_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID115_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___M 0x00040000
#define   DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___S              18
#define   DBG_PHYADMUX_ATID_SEL3__ATID114_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID114_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___M 0x00020000
#define   DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___S              17
#define   DBG_PHYADMUX_ATID_SEL3__ATID113_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID113_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___M 0x00010000
#define   DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___S              16
#define   DBG_PHYADMUX_ATID_SEL3__ATID112_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID112_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___M 0x00008000
#define   DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___S              15
#define   DBG_PHYADMUX_ATID_SEL3__ATID111_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID111_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___M 0x00004000
#define   DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___S              14
#define   DBG_PHYADMUX_ATID_SEL3__ATID110_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID110_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___M 0x00002000
#define   DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___S              13
#define   DBG_PHYADMUX_ATID_SEL3__ATID109_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID109_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___M 0x00001000
#define   DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___S              12
#define   DBG_PHYADMUX_ATID_SEL3__ATID108_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID108_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___M 0x00000800
#define   DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___S              11
#define   DBG_PHYADMUX_ATID_SEL3__ATID107_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID107_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___M 0x00000400
#define   DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___S              10
#define   DBG_PHYADMUX_ATID_SEL3__ATID106_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID106_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___M 0x00000200
#define   DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___S               9
#define   DBG_PHYADMUX_ATID_SEL3__ATID105_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID105_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___M 0x00000100
#define   DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___S               8
#define   DBG_PHYADMUX_ATID_SEL3__ATID104_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID104_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___M 0x00000080
#define   DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___S               7
#define   DBG_PHYADMUX_ATID_SEL3__ATID103_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID103_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___M 0x00000040
#define   DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___S               6
#define   DBG_PHYADMUX_ATID_SEL3__ATID102_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID102_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___M 0x00000020
#define   DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___S               5
#define   DBG_PHYADMUX_ATID_SEL3__ATID101_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID101_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___M 0x00000010
#define   DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___S               4
#define   DBG_PHYADMUX_ATID_SEL3__ATID100_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID100_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___M 0x00000008
#define   DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___S               3
#define   DBG_PHYADMUX_ATID_SEL3__ATID99_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID99_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___M 0x00000004
#define   DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___S               2
#define   DBG_PHYADMUX_ATID_SEL3__ATID98_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID98_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___M 0x00000002
#define   DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___S               1
#define   DBG_PHYADMUX_ATID_SEL3__ATID97_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID97_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___M 0x00000001
#define   DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___S               0
#define   DBG_PHYADMUX_ATID_SEL3__ATID96_SEL__SEL_PORT0             0x0
#define   DBG_PHYADMUX_ATID_SEL3__ATID96_SEL__SEL_PORT1             0x1
#define   DBG_PHYADMUX_ATID_SEL3___M             0xFFFFFFFF   
#define   DBG_PHYADMUX_ATID_SEL3___S                           0

#define DBG_MISCFUN_CTRL_REG                      (0x00BC8000)
#define   DBG_MISCFUN_CTRL_REG___RWC                QCSR_REG_RW    
#define   DBG_MISCFUN_CTRL_REG___POR             0x00000300
#define   DBG_MISCFUN_CTRL_REG__HT___POR         0x3
#define   DBG_MISCFUN_CTRL_REG__ENS7___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS6___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS5___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS4___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS3___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS2___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS1___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__ENS0___POR       0x0
#define   DBG_MISCFUN_CTRL_REG__HT___M           0x00000F00
#define   DBG_MISCFUN_CTRL_REG__HT___S                         8
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X0                   0x0
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X1                   0x1
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X2                   0x2
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X3                   0x3
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X4                   0x4
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X5                   0x5
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X6                   0x6
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X7                   0x7
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X8                   0x8
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0X9                   0x9
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0XA                   0xA
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0XB                   0xB
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0XC                   0xC
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0XD                   0xD
#define   DBG_MISCFUN_CTRL_REG__HT__HT_0XE                   0xE
#define   DBG_MISCFUN_CTRL_REG__ENS7___M         0x00000080
#define   DBG_MISCFUN_CTRL_REG__ENS7___S                       7
#define   DBG_MISCFUN_CTRL_REG__ENS7__ENS7_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS7__ENS7_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS6___M         0x00000040
#define   DBG_MISCFUN_CTRL_REG__ENS6___S                       6
#define   DBG_MISCFUN_CTRL_REG__ENS6__ENS6_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS6__ENS6_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS5___M         0x00000020
#define   DBG_MISCFUN_CTRL_REG__ENS5___S                       5
#define   DBG_MISCFUN_CTRL_REG__ENS5__ENS5_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS5__ENS5_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS4___M         0x00000010
#define   DBG_MISCFUN_CTRL_REG__ENS4___S                       4
#define   DBG_MISCFUN_CTRL_REG__ENS4__ENS4_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS4__ENS4_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS3___M         0x00000008
#define   DBG_MISCFUN_CTRL_REG__ENS3___S                       3
#define   DBG_MISCFUN_CTRL_REG__ENS3__ENS3_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS3__ENS3_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS2___M         0x00000004
#define   DBG_MISCFUN_CTRL_REG__ENS2___S                       2
#define   DBG_MISCFUN_CTRL_REG__ENS2__ENS2_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS2__ENS2_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS1___M         0x00000002
#define   DBG_MISCFUN_CTRL_REG__ENS1___S                       1
#define   DBG_MISCFUN_CTRL_REG__ENS1__ENS1_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS1__ENS1_1                 0x1
#define   DBG_MISCFUN_CTRL_REG__ENS0___M         0x00000001
#define   DBG_MISCFUN_CTRL_REG__ENS0___S                       0
#define   DBG_MISCFUN_CTRL_REG__ENS0__ENS0_0                 0x0
#define   DBG_MISCFUN_CTRL_REG__ENS0__ENS0_1                 0x1
#define   DBG_MISCFUN_CTRL_REG___M               0x00000FFF   
#define   DBG_MISCFUN_CTRL_REG___S                             0

#define DBG_MISCFUN_PRIORITY_CTRL_REG             (0x00BC8004)
#define   DBG_MISCFUN_PRIORITY_CTRL_REG___RWC       QCSR_REG_RW    
#define   DBG_MISCFUN_PRIORITY_CTRL_REG___POR    0x00000000
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___S              21
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___S              18
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___S              15
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___S              12
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___S               9
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___S               6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_MISCFUN_PRIORITY_CTRL_REG___M      0x00FFFFFF   
#define   DBG_MISCFUN_PRIORITY_CTRL_REG___S                    0

#define DBG_MISCFUN_ITATBDATA0                    (0x00BC8EEC)
#define   DBG_MISCFUN_ITATBDATA0___RWC              QCSR_REG_RW    
#define   DBG_MISCFUN_ITATBDATA0___POR           0x00000000
#define   DBG_MISCFUN_ITATBDATA0__ATDATA63___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA55___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA47___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA39___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA31___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA15___POR 0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA7___POR  0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA0___POR  0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA63___M   0x00000100
#define   DBG_MISCFUN_ITATBDATA0__ATDATA63___S                 8
#define   DBG_MISCFUN_ITATBDATA0__ATDATA63__ATDATA63_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA63__ATDATA63_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA55___M   0x00000080
#define   DBG_MISCFUN_ITATBDATA0__ATDATA55___S                 7
#define   DBG_MISCFUN_ITATBDATA0__ATDATA55__ATDATA55_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA55__ATDATA55_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA47___M   0x00000040
#define   DBG_MISCFUN_ITATBDATA0__ATDATA47___S                 6
#define   DBG_MISCFUN_ITATBDATA0__ATDATA47__ATDATA47_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA47__ATDATA47_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA39___M   0x00000020
#define   DBG_MISCFUN_ITATBDATA0__ATDATA39___S                 5
#define   DBG_MISCFUN_ITATBDATA0__ATDATA39__ATDATA39_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA39__ATDATA39_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA31___M   0x00000010
#define   DBG_MISCFUN_ITATBDATA0__ATDATA31___S                 4
#define   DBG_MISCFUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATAM23___M  0x00000008
#define   DBG_MISCFUN_ITATBDATA0__ATDATAM23___S                3
#define   DBG_MISCFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA15___M   0x00000004
#define   DBG_MISCFUN_ITATBDATA0__ATDATA15___S                 2
#define   DBG_MISCFUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA7___M    0x00000002
#define   DBG_MISCFUN_ITATBDATA0__ATDATA7___S                  1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_MISCFUN_ITATBDATA0__ATDATA0___M    0x00000001
#define   DBG_MISCFUN_ITATBDATA0__ATDATA0___S                  0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_MISCFUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_MISCFUN_ITATBDATA0___M             0x000001FF   
#define   DBG_MISCFUN_ITATBDATA0___S                           0

#define DBG_MISCFUN_ITATBCTR2                     (0x00BC8EF0)
#define   DBG_MISCFUN_ITATBCTR2___RWC               QCSR_REG_RW    
#define   DBG_MISCFUN_ITATBCTR2___POR            0x00000000
#define   DBG_MISCFUN_ITATBCTR2__AFVALID___POR   0x0
#define   DBG_MISCFUN_ITATBCTR2__ATREADY___POR   0x0
#define   DBG_MISCFUN_ITATBCTR2__AFVALID___M     0x00000002
#define   DBG_MISCFUN_ITATBCTR2__AFVALID___S                   1
#define   DBG_MISCFUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_MISCFUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_MISCFUN_ITATBCTR2__ATREADY___M     0x00000001
#define   DBG_MISCFUN_ITATBCTR2__ATREADY___S                   0
#define   DBG_MISCFUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_MISCFUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_MISCFUN_ITATBCTR2___M              0x00000003   
#define   DBG_MISCFUN_ITATBCTR2___S                            0

#define DBG_MISCFUN_ITATBCTR1                     (0x00BC8EF4)
#define   DBG_MISCFUN_ITATBCTR1___RWC               QCSR_REG_RW    
#define   DBG_MISCFUN_ITATBCTR1__ATID___M        0x0000007F
#define   DBG_MISCFUN_ITATBCTR1__ATID___S                      0
#define   DBG_MISCFUN_ITATBCTR1___M              0x0000007F   
#define   DBG_MISCFUN_ITATBCTR1___S                            0

#define DBG_MISCFUN_ITATBCTR0                     (0x00BC8EF8)
#define   DBG_MISCFUN_ITATBCTR0___RWC               QCSR_REG_RW    
#define   DBG_MISCFUN_ITATBCTR0___POR            0x00000000
#define   DBG_MISCFUN_ITATBCTR0__ATBYTES___POR   0x0
#define   DBG_MISCFUN_ITATBCTR0__AFREADY___POR   0x0
#define   DBG_MISCFUN_ITATBCTR0__ATVALID___POR   0x0
#define   DBG_MISCFUN_ITATBCTR0__ATBYTES___M     0x00000700
#define   DBG_MISCFUN_ITATBCTR0__ATBYTES___S                   8
#define   DBG_MISCFUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_MISCFUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_MISCFUN_ITATBCTR0__AFREADY___M     0x00000002
#define   DBG_MISCFUN_ITATBCTR0__AFREADY___S                   1
#define   DBG_MISCFUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_MISCFUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_MISCFUN_ITATBCTR0__ATVALID___M     0x00000001
#define   DBG_MISCFUN_ITATBCTR0__ATVALID___S                   0
#define   DBG_MISCFUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_MISCFUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_MISCFUN_ITATBCTR0___M              0x00000703   
#define   DBG_MISCFUN_ITATBCTR0___S                            0

#define DBG_MISCFUN_ITCTRL                        (0x00BC8F00)
#define   DBG_MISCFUN_ITCTRL___RWC                  QCSR_REG_RW    
#define   DBG_MISCFUN_ITCTRL___POR               0x00000000
#define   DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_MISCFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_MISCFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_MISCFUN_ITCTRL___M                 0x00000001   
#define   DBG_MISCFUN_ITCTRL___S                               0

#define DBG_MISCFUN_CLAIMSET                      (0x00BC8FA0)
#define   DBG_MISCFUN_CLAIMSET___RWC                QCSR_REG_RW    
#define   DBG_MISCFUN_CLAIMSET___POR             0x0000000F
#define   DBG_MISCFUN_CLAIMSET__CLAIMSET___POR   0xF
#define   DBG_MISCFUN_CLAIMSET__CLAIMSET___M     0x0000000F
#define   DBG_MISCFUN_CLAIMSET__CLAIMSET___S                   0
#define   DBG_MISCFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_MISCFUN_CLAIMSET___M               0x0000000F   
#define   DBG_MISCFUN_CLAIMSET___S                             0

#define DBG_MISCFUN_CLAIMCLR                      (0x00BC8FA4)
#define   DBG_MISCFUN_CLAIMCLR___RWC                QCSR_REG_RW    
#define   DBG_MISCFUN_CLAIMCLR___POR             0x00000000
#define   DBG_MISCFUN_CLAIMCLR__CLAIMCLR___POR   0x0
#define   DBG_MISCFUN_CLAIMCLR__CLAIMCLR___M     0x0000000F
#define   DBG_MISCFUN_CLAIMCLR__CLAIMCLR___S                   0
#define   DBG_MISCFUN_CLAIMCLR___M               0x0000000F   
#define   DBG_MISCFUN_CLAIMCLR___S                             0

#define DBG_MISCFUN_LOCKACCESS                    (0x00BC8FB0)
#define   DBG_MISCFUN_LOCKACCESS___RWC              QCSR_REG_WO    
#define   DBG_MISCFUN_LOCKACCESS__KEY___M        0xFFFFFFFF
#define   DBG_MISCFUN_LOCKACCESS__KEY___S                      0
#define   DBG_MISCFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_MISCFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_MISCFUN_LOCKACCESS___M             0xFFFFFFFF   
#define   DBG_MISCFUN_LOCKACCESS___S                           0

#define DBG_MISCFUN_LOCKSTATUS                    (0x00BC8FB4)
#define   DBG_MISCFUN_LOCKSTATUS___RWC              QCSR_REG_RO    
#define   DBG_MISCFUN_LOCKSTATUS___POR           0x00000003
#define   DBG_MISCFUN_LOCKSTATUS__NTT___POR      0x0
#define   DBG_MISCFUN_LOCKSTATUS__SLK___POR      0x1
#define   DBG_MISCFUN_LOCKSTATUS__SLI___POR      0x1
#define   DBG_MISCFUN_LOCKSTATUS__NTT___M        0x00000004
#define   DBG_MISCFUN_LOCKSTATUS__NTT___S                      2
#define   DBG_MISCFUN_LOCKSTATUS__NTT__NTT_0X0               0x0
#define   DBG_MISCFUN_LOCKSTATUS__SLK___M        0x00000002
#define   DBG_MISCFUN_LOCKSTATUS__SLK___S                      1
#define   DBG_MISCFUN_LOCKSTATUS__SLK__SLK_0X0               0x0
#define   DBG_MISCFUN_LOCKSTATUS__SLK__SLK_0X1               0x1
#define   DBG_MISCFUN_LOCKSTATUS__SLI___M        0x00000001
#define   DBG_MISCFUN_LOCKSTATUS__SLI___S                      0
#define   DBG_MISCFUN_LOCKSTATUS__SLI__SLI_0X0               0x0
#define   DBG_MISCFUN_LOCKSTATUS__SLI__SLI_0X1               0x1
#define   DBG_MISCFUN_LOCKSTATUS___M             0x00000007   
#define   DBG_MISCFUN_LOCKSTATUS___S                           0

#define DBG_MISCFUN_AUTHSTATUS                    (0x00BC8FB8)
#define   DBG_MISCFUN_AUTHSTATUS___RWC              QCSR_REG_RO    
#define   DBG_MISCFUN_AUTHSTATUS___POR           0x00000000
#define   DBG_MISCFUN_AUTHSTATUS__SNID___POR     0x0
#define   DBG_MISCFUN_AUTHSTATUS__SID___POR      0x0
#define   DBG_MISCFUN_AUTHSTATUS__NSNID___POR    0x0
#define   DBG_MISCFUN_AUTHSTATUS__NSID___POR     0x0
#define   DBG_MISCFUN_AUTHSTATUS__SNID___M       0x000000C0
#define   DBG_MISCFUN_AUTHSTATUS__SNID___S                     6
#define   DBG_MISCFUN_AUTHSTATUS__SNID__SNID_0X0             0x0
#define   DBG_MISCFUN_AUTHSTATUS__SID___M        0x00000030
#define   DBG_MISCFUN_AUTHSTATUS__SID___S                      4
#define   DBG_MISCFUN_AUTHSTATUS__SID__SID_0X0               0x0
#define   DBG_MISCFUN_AUTHSTATUS__NSNID___M      0x0000000C
#define   DBG_MISCFUN_AUTHSTATUS__NSNID___S                    2
#define   DBG_MISCFUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_MISCFUN_AUTHSTATUS__NSID___M       0x00000003
#define   DBG_MISCFUN_AUTHSTATUS__NSID___S                     0
#define   DBG_MISCFUN_AUTHSTATUS__NSID__NSID_0X0             0x0
#define   DBG_MISCFUN_AUTHSTATUS___M             0x000000FF   
#define   DBG_MISCFUN_AUTHSTATUS___S                           0

#define DBG_MISCFUN_DEVID                         (0x00BC8FC8)
#define   DBG_MISCFUN_DEVID___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_DEVID___POR                0x00000038
#define   DBG_MISCFUN_DEVID__SCHEME___POR        0x3
#define   DBG_MISCFUN_DEVID__PORTCOUNT___POR     0x8
#define   DBG_MISCFUN_DEVID__SCHEME___M          0x000000F0
#define   DBG_MISCFUN_DEVID__SCHEME___S                        4
#define   DBG_MISCFUN_DEVID__SCHEME__SCHEME_0X3              0x3
#define   DBG_MISCFUN_DEVID__PORTCOUNT___M       0x0000000F
#define   DBG_MISCFUN_DEVID__PORTCOUNT___S                     0
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_MISCFUN_DEVID___M                  0x000000FF   
#define   DBG_MISCFUN_DEVID___S                                0

#define DBG_MISCFUN_DEVTYPE                       (0x00BC8FCC)
#define   DBG_MISCFUN_DEVTYPE___RWC                 QCSR_REG_RO    
#define   DBG_MISCFUN_DEVTYPE___POR              0x00000012
#define   DBG_MISCFUN_DEVTYPE__SUB_TYPE___POR    0x1
#define   DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___POR  0x2
#define   DBG_MISCFUN_DEVTYPE__SUB_TYPE___M      0x000000F0
#define   DBG_MISCFUN_DEVTYPE__SUB_TYPE___S                    4
#define   DBG_MISCFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___M    0x0000000F
#define   DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___S                  0
#define   DBG_MISCFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_MISCFUN_DEVTYPE___M                0x000000FF   
#define   DBG_MISCFUN_DEVTYPE___S                              0

#define DBG_MISCFUN_PIDR0                         (0x00BC8FE0)
#define   DBG_MISCFUN_PIDR0___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_PIDR0___POR                0x00000008
#define   DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_MISCFUN_PIDR0___M                  0x000000FF   
#define   DBG_MISCFUN_PIDR0___S                                0

#define DBG_MISCFUN_PIDR1                         (0x00BC8FE4)
#define   DBG_MISCFUN_PIDR1___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_PIDR1___POR                0x000000B9
#define   DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0
#define   DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___S               4
#define   DBG_MISCFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_MISCFUN_PIDR1___M                  0x000000FF   
#define   DBG_MISCFUN_PIDR1___S                                0

#define DBG_MISCFUN_PIDR2                         (0x00BC8FE8)
#define   DBG_MISCFUN_PIDR2___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_PIDR2___POR                0x0000003B
#define   DBG_MISCFUN_PIDR2__REVISION___POR      0x3
#define   DBG_MISCFUN_PIDR2__JEDEC___POR         0x1
#define   DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_MISCFUN_PIDR2__REVISION___M        0x000000F0
#define   DBG_MISCFUN_PIDR2__REVISION___S                      4
#define   DBG_MISCFUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_MISCFUN_PIDR2__JEDEC___M           0x00000008
#define   DBG_MISCFUN_PIDR2__JEDEC___S                         3
#define   DBG_MISCFUN_PIDR2__JEDEC__JEDEC_0X1                0x1
#define   DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007
#define   DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___S               0
#define   DBG_MISCFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_MISCFUN_PIDR2___M                  0x000000FF   
#define   DBG_MISCFUN_PIDR2___S                                0

#define DBG_MISCFUN_PIDR3                         (0x00BC8FEC)
#define   DBG_MISCFUN_PIDR3___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_PIDR3___POR                0x00000000
#define   DBG_MISCFUN_PIDR3__REVAND___POR        0x0
#define   DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_MISCFUN_PIDR3__REVAND___M          0x000000F0
#define   DBG_MISCFUN_PIDR3__REVAND___S                        4
#define   DBG_MISCFUN_PIDR3__REVAND__REVAND_0X0              0x0
#define   DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_MISCFUN_PIDR3___M                  0x000000FF   
#define   DBG_MISCFUN_PIDR3___S                                0

#define DBG_MISCFUN_PIDR4                         (0x00BC8FD0)
#define   DBG_MISCFUN_PIDR4___RWC                   QCSR_REG_RO    
#define   DBG_MISCFUN_PIDR4___POR                0x00000004
#define   DBG_MISCFUN_PIDR4__FOURKB_COUNT___POR  0x0
#define   DBG_MISCFUN_PIDR4__JEP106_CONT___POR   0x4
#define   DBG_MISCFUN_PIDR4__FOURKB_COUNT___M    0x000000F0
#define   DBG_MISCFUN_PIDR4__FOURKB_COUNT___S                  4
#define   DBG_MISCFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_MISCFUN_PIDR4__JEP106_CONT___M     0x0000000F
#define   DBG_MISCFUN_PIDR4__JEP106_CONT___S                   0
#define   DBG_MISCFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_MISCFUN_PIDR4___M                  0x000000FF   
#define   DBG_MISCFUN_PIDR4___S                                0

#define DBG_MISCFUN_PERIPHID5                     (0x00BC8FD4)
#define   DBG_MISCFUN_PERIPHID5___RWC               QCSR_REG_RO    
#define   DBG_MISCFUN_PERIPHID5___POR            0x00000000
#define   DBG_MISCFUN_PERIPHID5__PERIPHID5___POR 0x00000000
#define   DBG_MISCFUN_PERIPHID5__PERIPHID5___M   0xFFFFFFFF
#define   DBG_MISCFUN_PERIPHID5__PERIPHID5___S                 0
#define   DBG_MISCFUN_PERIPHID5___M              0xFFFFFFFF   
#define   DBG_MISCFUN_PERIPHID5___S                            0

#define DBG_MISCFUN_PERIPHID6                     (0x00BC8FD8)
#define   DBG_MISCFUN_PERIPHID6___RWC               QCSR_REG_RO    
#define   DBG_MISCFUN_PERIPHID6___POR            0x00000000
#define   DBG_MISCFUN_PERIPHID6__PERIPHID6___POR 0x00000000
#define   DBG_MISCFUN_PERIPHID6__PERIPHID6___M   0xFFFFFFFF
#define   DBG_MISCFUN_PERIPHID6__PERIPHID6___S                 0
#define   DBG_MISCFUN_PERIPHID6___M              0xFFFFFFFF   
#define   DBG_MISCFUN_PERIPHID6___S                            0

#define DBG_MISCFUN_PERIPHID7                     (0x00BC8FDC)
#define   DBG_MISCFUN_PERIPHID7___RWC               QCSR_REG_RO    
#define   DBG_MISCFUN_PERIPHID7___POR            0x00000000
#define   DBG_MISCFUN_PERIPHID7__PERIPHID7___POR 0x00000000
#define   DBG_MISCFUN_PERIPHID7__PERIPHID7___M   0xFFFFFFFF
#define   DBG_MISCFUN_PERIPHID7__PERIPHID7___S                 0
#define   DBG_MISCFUN_PERIPHID7___M              0xFFFFFFFF   
#define   DBG_MISCFUN_PERIPHID7___S                            0

#define DBG_MISCFUN_CID0                          (0x00BC8FF0)
#define   DBG_MISCFUN_CID0___RWC                    QCSR_REG_RO    
#define   DBG_MISCFUN_CID0___POR                 0x0000000D
#define   DBG_MISCFUN_CID0__PREAMBLE___POR       0x0D
#define   DBG_MISCFUN_CID0__PREAMBLE___M         0x000000FF
#define   DBG_MISCFUN_CID0__PREAMBLE___S                       0
#define   DBG_MISCFUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_MISCFUN_CID0___M                   0x000000FF   
#define   DBG_MISCFUN_CID0___S                                 0

#define DBG_MISCFUN_CID1                          (0x00BC8FF4)
#define   DBG_MISCFUN_CID1___RWC                    QCSR_REG_RO    
#define   DBG_MISCFUN_CID1___POR                 0x00000090
#define   DBG_MISCFUN_CID1__CLASS___POR          0x9
#define   DBG_MISCFUN_CID1__PREAMBLE___POR       0x0
#define   DBG_MISCFUN_CID1__CLASS___M            0x000000F0
#define   DBG_MISCFUN_CID1__CLASS___S                          4
#define   DBG_MISCFUN_CID1__CLASS__CLASS_0X9                 0x9
#define   DBG_MISCFUN_CID1__PREAMBLE___M         0x0000000F
#define   DBG_MISCFUN_CID1__PREAMBLE___S                       0
#define   DBG_MISCFUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_MISCFUN_CID1___M                   0x000000FF   
#define   DBG_MISCFUN_CID1___S                                 0

#define DBG_MISCFUN_CID2                          (0x00BC8FF8)
#define   DBG_MISCFUN_CID2___RWC                    QCSR_REG_RO    
#define   DBG_MISCFUN_CID2___POR                 0x00000005
#define   DBG_MISCFUN_CID2__PREAMBLE___POR       0x05
#define   DBG_MISCFUN_CID2__PREAMBLE___M         0x000000FF
#define   DBG_MISCFUN_CID2__PREAMBLE___S                       0
#define   DBG_MISCFUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_MISCFUN_CID2___M                   0x000000FF   
#define   DBG_MISCFUN_CID2___S                                 0

#define DBG_MISCFUN_CID3                          (0x00BC8FFC)
#define   DBG_MISCFUN_CID3___RWC                    QCSR_REG_RO    
#define   DBG_MISCFUN_CID3___POR                 0x000000B1
#define   DBG_MISCFUN_CID3__PREAMBLE___POR       0xB1
#define   DBG_MISCFUN_CID3__PREAMBLE___M         0x000000FF
#define   DBG_MISCFUN_CID3__PREAMBLE___S                       0
#define   DBG_MISCFUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_MISCFUN_CID3___M                   0x000000FF   
#define   DBG_MISCFUN_CID3___S                                 0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW (0x00BD0000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___POR 0x0001E93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH (0x00BD0004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW (0x00BD0008)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___POR 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___M 0x00000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW (0x00BD0010)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW (0x00BD0018)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW (0x00BD0020)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH (0x00BD0024)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW (0x00BD0028)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH (0x00BD002C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW (0x00BD0030)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH (0x00BD0034)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW (0x00BD0038)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH (0x00BD003C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW (0x00BD0080)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___POR 0x0001E93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH (0x00BD0084)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW (0x00BD0088)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___POR 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___M 0x00000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW (0x00BD0090)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW (0x00BD0098)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW (0x00BD00A0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH (0x00BD00A4)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW (0x00BD00A8)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH (0x00BD00AC)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW (0x00BD00B0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH (0x00BD00B4)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW (0x00BD00B8)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH (0x00BD00BC)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW (0x00BD0100)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___POR 0x0001E93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH (0x00BD0104)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW (0x00BD0108)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___POR 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___M 0x00000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW (0x00BD0110)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW (0x00BD0118)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW (0x00BD0120)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH (0x00BD0124)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW (0x00BD0128)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH (0x00BD012C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW (0x00BD0130)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH (0x00BD0134)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW (0x00BD0138)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH (0x00BD013C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW (0x00BD0200)
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___POR 0x000EEC22
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___POR 0xEC22
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH (0x00BD0204)
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW (0x00BD0240)
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___M 0x00002000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___S              13
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___M 0x00FDFD6F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW (0x00BD0248)
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___M 0x00002000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___S              13
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___M 0x00FDFD6F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW (0x00BD0400)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___POR 0x000E8DBE
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___POR 0x8DBE
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH (0x00BD0404)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW (0x00BD0480)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW (0x00BD0488)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW (0x00BD0490)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW (0x00BD0500)
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___M 0x00000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW (0x00BD0600)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___POR 0x0008317D
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___POR 0x317D
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH (0x00BD0604)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW (0x00BD0608)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___M 0x00003F37   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW (0x00BD0610)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW (0x00BD0618)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW (0x00BD0620)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW (0x00BD0640)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___M 0x00003303   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW (0x00BD0648)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___POR 0x00800400
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x400
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW (0x00BD0650)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___M 0x00003303   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW (0x00BD0658)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___POR 0x00800400
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x400
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW (0x00BD0700)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH (0x00BD0704)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW (0x00BD0708)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW (0x00BD0710)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW (0x00BD0718)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW (0x00BD0720)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW (0x00BD0780)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH (0x00BD0784)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW (0x00BD0788)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW (0x00BD0790)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW (0x00BD0798)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW (0x00BD07A0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW (0x00BD0800)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___POR 0x00087F1D
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___POR 0x7F1D
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH (0x00BD0804)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW (0x00BD0808)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW (0x00BD0810)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW (0x00BD0818)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW (0x00BD0820)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___M 0x1F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___M 0x001F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___M 0x00001F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___M 0x1F1F1F1F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW (0x00BD0880)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH (0x00BD0884)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW (0x00BD0888)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW (0x00BD0890)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW (0x00BD0898)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW (0x00BD08A0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW (0x00BD0900)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___POR 0x00081500
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___POR 0x1500
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH (0x00BD0904)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW (0x00BD0908)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___M 0x00003F37   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW (0x00BD0910)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000007F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___M 0x0FFF007F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW (0x00BD0918)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW (0x00BD0920)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___M 0x3F000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___M 0x003F0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___M 0x00003F00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___M 0x0000003F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___M 0x3F3F3F3F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW (0x00BD0940)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___M 0x00003303   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW (0x00BD0948)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___POR 0x00800199
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x199
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW (0x00BD0950)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___M 0x00003303   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW (0x00BD0958)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___POR 0x00800199
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x199
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW     (0x00BD1000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___POR 0x000CE93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___POR 0x0C
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH    (0x00BD1004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW    (0x00BD1008)
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW    (0x00BD1010)
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___M 0x0000007F
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___M 0x0000007F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW (0x00BD1018)
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW (0x00BD1400)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___POR 0x0003DBB2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xDBB2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH (0x00BD1404)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW (0x00BD1408)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW (0x00BD1410)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW (0x00BD1418)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW (0x00BD1420)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW (0x00BD1428)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH (0x00BD142C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW (0x00BD1440)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW (0x00BD1448)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW (0x00BD1450)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW (0x00BD1458)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW (0x00BD1460)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW (0x00BD1468)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW (0x00BD1470)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW (0x00BD1478)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW (0x00BD1480)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BD1520)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BD1524)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BD1528)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BD152C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW (0x00BD1538)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW (0x00BD1600)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___POR 0x0003CB09
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xCB09
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH (0x00BD1604)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW (0x00BD1608)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW (0x00BD1610)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW (0x00BD1618)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW (0x00BD1620)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___POR 0x00F00000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW (0x00BD1628)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH (0x00BD162C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW (0x00BD1640)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW (0x00BD1648)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW (0x00BD1650)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW (0x00BD1658)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW (0x00BD1660)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW (0x00BD1668)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW (0x00BD1670)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW (0x00BD1678)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW (0x00BD1680)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BD1720)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BD1724)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BD1728)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BD172C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW (0x00BD1738)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW (0x00BD2000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___POR 0x00122752
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___POR 0x12
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___POR 0x2752
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH (0x00BD2004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW (0x00BD2008)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___M 0x0000002F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW (0x00BD2010)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___M 0x80000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW (0x00BD2018)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___M 0x80000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW (0x00BD2020)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___M 0x80000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW (0x00BD2028)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___M 0x00000003
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___M 0x80000003   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW (0x00BD2120)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___S               6

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH (0x00BD2124)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW (0x00BD2128)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___S               6

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH (0x00BD212C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW (0x00BD2138)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW (0x00BD2220)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___S               6

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH (0x00BD2224)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW (0x00BD2228)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___S               6

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH (0x00BD222C)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW (0x00BD2238)
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW      (0x00BD3000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___POR 0x00023E6C
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___POR 0x02
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___POR 0x3E6C
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH     (0x00BD3004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW   (0x00BD3008)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___M 0x00000007   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW    (0x00BD3010)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW (0x00BD3018)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___M 0x0000001F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW   (0x00BD3020)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW  (0x00BD3028)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW  (0x00BD3030)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW (0x00BD3038)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW  (0x00BD3040)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___RWC QCSR_REG_WO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW   (0x00BD3048)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___M 0x00000001   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW (0x00BD3100)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW (0x00BD3140)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW (0x00BD3180)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW (0x00BD31C0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW (0x00BD3200)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW (0x00BD3240)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW (0x00BD3280)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW (0x00BD32C0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW (0x00BD3300)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW (0x00BD3340)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW (0x00BD3380)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW (0x00BD33C0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW (0x00BD3400)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW (0x00BD3440)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW (0x00BD3480)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___POR 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___POR 0x1F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___M 0x0000001F
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___M 0x0000071F   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW (0x00BD34C0)
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___M 0x0000FFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW (0x00BD4000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH (0x00BD4004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW (0x00BD4100)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW (0x00BD4200)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH (0x00BD4204)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW (0x00BD4300)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW (0x00BD4400)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH (0x00BD4404)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW (0x00BD4500)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW (0x00BD4600)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH (0x00BD4604)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW (0x00BD4700)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW (0x00BD4A00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH (0x00BD4A04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW (0x00BD4B00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW (0x00BD4C00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH (0x00BD4C04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW (0x00BD4D00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW (0x00BD5000)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH (0x00BD5004)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW (0x00BD5100)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW (0x00BD5400)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___POR 0x000E533C
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___POR 0x533C
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH (0x00BD5404)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW (0x00BD5500)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___M 0x00002000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___S              13
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___M 0x00003FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW (0x00BD5600)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___POR 0x000E4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH (0x00BD5604)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW (0x00BD5700)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH (0x00BD5704)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW (0x00BD5800)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___POR 0x000E4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH (0x00BD5804)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW (0x00BD5900)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH (0x00BD5904)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW (0x00BD5A00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___POR 0x000E4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH (0x00BD5A04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW (0x00BD5B00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH (0x00BD5B04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW (0x00BD5C00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___POR 0x000E4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH (0x00BD5C04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW (0x00BD5D00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH (0x00BD5D04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW (0x00BD5E00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___POR 0x000E4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH (0x00BD5E04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW (0x00BD5F00)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH (0x00BD5F04)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW (0x00BD6200)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___POR 0x000EF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH (0x00BD6204)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___S               0

#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW (0x00BD6300)
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW        (0x00BE0000)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___RWC  QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___POR 0x00021F1B
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___POR 0x02
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___POR 0x1F1B
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH       (0x00BE0004)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW     (0x00BE0008)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S               2
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___S               1
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___M 0x00000007   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW      (0x00BE0010)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW  (0x00BE0018)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW     (0x00BE0020)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW    (0x00BE0028)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW    (0x00BE0030)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW (0x00BE0038)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW    (0x00BE0040)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW     (0x00BE0048)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW (0x00BE0100)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW (0x00BE0140)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW (0x00BE0180)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW (0x00BE01C0)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW (0x00BE0200)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW (0x00BE0240)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW (0x00BE0280)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW (0x00BE02C0)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW (0x00BE0300)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW (0x00BE0340)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW (0x00BE0380)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW (0x00BE03C0)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW (0x00BE0400)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW (0x00BE0440)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW (0x00BE0480)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___POR 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___POR 0x7F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___S               9
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___S               8
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___M 0x0000077F   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW (0x00BE04C0)
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___S               0
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___M 0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW     (0x00BE1000)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___POR 0x001237AA
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___POR 0x12
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___POR 0x37AA
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH    (0x00BE1004)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW  (0x00BE1008)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___M 0x0000002F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW (0x00BE1010)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW (0x00BE1018)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW (0x00BE1020)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW   (0x00BE1028)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW  (0x00BE1030)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___M 0x00000007
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___M 0x00000007   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW (0x00BE1120)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH (0x00BE1124)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW (0x00BE1128)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH (0x00BE112C)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW (0x00BE1138)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW (0x00BE1140)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___M 0x0000000F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW (0x00BE1178)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW (0x00BE1180)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW (0x00BE1190)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___M 0x00000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW (0x00BE1220)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH (0x00BE1224)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW (0x00BE1228)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH (0x00BE122C)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW (0x00BE1238)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW (0x00BE1240)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___M 0x0000000F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW (0x00BE1278)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW (0x00BE1280)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW (0x00BE1290)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___M 0x00000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW    (0x00BE1400)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___POR 0x0012C2E1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___POR 0x12
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___POR 0xC2E1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH   (0x00BE1404)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW (0x00BE1408)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___M 0x0000002F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW (0x00BE1410)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW (0x00BE1418)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW (0x00BE1420)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW  (0x00BE1428)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___M 0x80000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___S              31
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___M 0x80000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW (0x00BE1430)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___M 0x00000007
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___M 0x00000007   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW (0x00BE1520)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH (0x00BE1524)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW (0x00BE1528)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH (0x00BE152C)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW (0x00BE1538)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW (0x00BE1540)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___M 0x0000000F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW (0x00BE1578)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW (0x00BE1580)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW (0x00BE1590)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___M 0x00000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW (0x00BE1620)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH (0x00BE1624)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW (0x00BE1628)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___S               6

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH (0x00BE162C)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW (0x00BE1638)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW (0x00BE1640)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___S               3
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___S               2
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___S               1
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___M 0x0000000F   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW (0x00BE1678)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW (0x00BE1680)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___S               0

#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW (0x00BE1690)
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S               0
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___M 0x00000003   
#define   DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW (0x00BE1800)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___POR 0x000341AC
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x41AC
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH (0x00BE1804)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW (0x00BE1808)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW (0x00BE1810)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW (0x00BE1818)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW (0x00BE1820)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___POR 0x01400000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW (0x00BE1828)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH (0x00BE182C)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW (0x00BE1840)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW (0x00BE1848)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW (0x00BE1850)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW (0x00BE1858)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW (0x00BE1860)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW (0x00BE1868)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW (0x00BE1870)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW (0x00BE1878)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW (0x00BE1880)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE1920)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___S              10
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE1928)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___S              10
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW (0x00BE1938)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW (0x00BE1968)
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___S               4
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___S               3
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___S               2
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___S               1
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___S               0
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW (0x00BE2000)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___POR 0x00039006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH (0x00BE2004)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW (0x00BE2008)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW (0x00BE2010)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW (0x00BE2018)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW (0x00BE2020)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___POR 0x01400000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW (0x00BE2028)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH (0x00BE202C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW (0x00BE2040)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW (0x00BE2048)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW (0x00BE2050)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW (0x00BE2058)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW (0x00BE2060)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW (0x00BE2068)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW (0x00BE2070)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW (0x00BE2078)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW (0x00BE2080)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2120)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2124)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2128)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE212C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2138)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW (0x00BE2200)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___POR 0x00039006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH (0x00BE2204)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW (0x00BE2208)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW (0x00BE2210)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW (0x00BE2218)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW (0x00BE2220)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___POR 0x01400000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW (0x00BE2228)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH (0x00BE222C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW (0x00BE2240)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW (0x00BE2248)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW (0x00BE2250)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW (0x00BE2258)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW (0x00BE2260)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW (0x00BE2268)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW (0x00BE2270)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW (0x00BE2278)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW (0x00BE2280)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2320)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2324)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2328)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE232C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2338)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW (0x00BE2400)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___POR 0x00039006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH (0x00BE2404)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW (0x00BE2408)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW (0x00BE2410)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW (0x00BE2418)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW (0x00BE2420)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___POR 0x01400000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW (0x00BE2428)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH (0x00BE242C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW (0x00BE2440)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW (0x00BE2448)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW (0x00BE2450)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW (0x00BE2458)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW (0x00BE2460)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW (0x00BE2468)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW (0x00BE2470)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW (0x00BE2478)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW (0x00BE2480)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2520)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2524)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2528)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE252C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2538)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW (0x00BE2600)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___POR 0x00039006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH (0x00BE2604)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW (0x00BE2608)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW (0x00BE2610)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW (0x00BE2618)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW (0x00BE2620)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___POR 0x01400000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW (0x00BE2628)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH (0x00BE262C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___S               8

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW (0x00BE2640)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW (0x00BE2648)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW (0x00BE2650)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW (0x00BE2658)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW (0x00BE2660)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW (0x00BE2668)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW (0x00BE2670)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW (0x00BE2678)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW (0x00BE2680)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2720)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2724)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2728)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE272C)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2738)
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW            (0x00BE2800)
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW___RWC      QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW___POR   0x000CE93B
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___POR 0x0C
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW___M     0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_STP_SWID_LOW___S                   0

#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH           (0x00BE2804)
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___RWC     QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___POR  0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___M    0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___S                  0

#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW           (0x00BE2808)
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___RWC     QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___POR  0x00000000
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___S               0
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___M    0x00000001   
#define   DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___S                  0

#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW           (0x00BE2810)
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___RWC     QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___POR  0x00000000
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___POR 0x00
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___M 0x0000007F
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___S               0
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___M    0x0000007F   
#define   DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___S                  0

#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW   (0x00BE2818)
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S               0
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF   
#define   DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___S               0

#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW            (0x00BE2900)
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___RWC      QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___POR   0x0001E93B
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___S              16
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___M     0x00FFFFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___S                   0

#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH           (0x00BE2904)
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___RWC     QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___POR  0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___M    0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___S                  0

#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW         (0x00BE2908)
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___RWC   QCSR_REG_RW    
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___S               1
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___M  0x00000003   
#define   DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___S                0

#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW          (0x00BE2910)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___RWC    QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___M   0x00000001   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___S                 0

#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW          (0x00BE2918)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___RWC    QCSR_REG_WO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___M   0x00000001   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___S                 0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW         (0x00BE2920)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___RWC   QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___S               4
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___M  0x0F3F7777   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___S                0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH        (0x00BE2924)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___RWC  QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW         (0x00BE2928)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___RWC   QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___M  0x0000FFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___S                0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH        (0x00BE292C)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___RWC  QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW         (0x00BE2930)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___RWC   QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___M  0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___S                0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH        (0x00BE2934)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___RWC  QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___S               0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW         (0x00BE2938)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___RWC   QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___M  0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___S                0

#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH        (0x00BE293C)
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___RWC  QCSR_REG_RO    
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___S               0

#define DBG_PHYA_FUN_CTRL_REG                     (0x00BE4000)
#define   DBG_PHYA_FUN_CTRL_REG___RWC               QCSR_REG_RW    
#define   DBG_PHYA_FUN_CTRL_REG___POR            0x00000300
#define   DBG_PHYA_FUN_CTRL_REG__HT___POR        0x3
#define   DBG_PHYA_FUN_CTRL_REG__ENS7___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS6___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS5___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS4___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS3___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS2___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS1___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS0___POR      0x0
#define   DBG_PHYA_FUN_CTRL_REG__HT___M          0x00000F00
#define   DBG_PHYA_FUN_CTRL_REG__HT___S                        8
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X0                  0x0
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X1                  0x1
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X2                  0x2
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X3                  0x3
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X4                  0x4
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X5                  0x5
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X6                  0x6
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X7                  0x7
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X8                  0x8
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0X9                  0x9
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0XA                  0xA
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0XB                  0xB
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0XC                  0xC
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0XD                  0xD
#define   DBG_PHYA_FUN_CTRL_REG__HT__HT_0XE                  0xE
#define   DBG_PHYA_FUN_CTRL_REG__ENS7___M        0x00000080
#define   DBG_PHYA_FUN_CTRL_REG__ENS7___S                      7
#define   DBG_PHYA_FUN_CTRL_REG__ENS7__ENS7_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS7__ENS7_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS6___M        0x00000040
#define   DBG_PHYA_FUN_CTRL_REG__ENS6___S                      6
#define   DBG_PHYA_FUN_CTRL_REG__ENS6__ENS6_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS6__ENS6_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS5___M        0x00000020
#define   DBG_PHYA_FUN_CTRL_REG__ENS5___S                      5
#define   DBG_PHYA_FUN_CTRL_REG__ENS5__ENS5_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS5__ENS5_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS4___M        0x00000010
#define   DBG_PHYA_FUN_CTRL_REG__ENS4___S                      4
#define   DBG_PHYA_FUN_CTRL_REG__ENS4__ENS4_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS4__ENS4_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS3___M        0x00000008
#define   DBG_PHYA_FUN_CTRL_REG__ENS3___S                      3
#define   DBG_PHYA_FUN_CTRL_REG__ENS3__ENS3_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS3__ENS3_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS2___M        0x00000004
#define   DBG_PHYA_FUN_CTRL_REG__ENS2___S                      2
#define   DBG_PHYA_FUN_CTRL_REG__ENS2__ENS2_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS2__ENS2_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS1___M        0x00000002
#define   DBG_PHYA_FUN_CTRL_REG__ENS1___S                      1
#define   DBG_PHYA_FUN_CTRL_REG__ENS1__ENS1_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS1__ENS1_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG__ENS0___M        0x00000001
#define   DBG_PHYA_FUN_CTRL_REG__ENS0___S                      0
#define   DBG_PHYA_FUN_CTRL_REG__ENS0__ENS0_0                0x0
#define   DBG_PHYA_FUN_CTRL_REG__ENS0__ENS0_1                0x1
#define   DBG_PHYA_FUN_CTRL_REG___M              0x00000FFF   
#define   DBG_PHYA_FUN_CTRL_REG___S                            0

#define DBG_PHYA_FUN_PRIORITY_CTRL_REG            (0x00BE4004)
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG___RWC      QCSR_REG_RW    
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG___POR   0x00000000
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___S              21
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___S              18
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___S              15
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___S              12
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___S               9
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___S               6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___S               3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___S               0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0             0x0
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1             0x1
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2             0x2
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3             0x3
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4             0x4
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5             0x5
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6             0x6
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7             0x7
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG___M     0x00FFFFFF   
#define   DBG_PHYA_FUN_PRIORITY_CTRL_REG___S                   0

#define DBG_PHYA_FUN_ITATBDATA0                   (0x00BE4EEC)
#define   DBG_PHYA_FUN_ITATBDATA0___RWC             QCSR_REG_RW    
#define   DBG_PHYA_FUN_ITATBDATA0___POR          0x00000000
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA63___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA55___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA47___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA39___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA31___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA15___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA7___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA0___POR 0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA63___M  0x00000100
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA63___S                8
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA63__ATDATA63_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA63__ATDATA63_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA55___M  0x00000080
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA55___S                7
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA55__ATDATA55_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA55__ATDATA55_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA47___M  0x00000040
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA47___S                6
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA47__ATDATA47_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA47__ATDATA47_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA39___M  0x00000020
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA39___S                5
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA39__ATDATA39_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA39__ATDATA39_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA31___M  0x00000010
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA31___S                4
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA31__ATDATA31_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA31__ATDATA31_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___M 0x00000008
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___S               3
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATAM23__ATDATAM23_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATAM23__ATDATAM23_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA15___M  0x00000004
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA15___S                2
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA15__ATDATA15_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA15__ATDATA15_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA7___M   0x00000002
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA7___S                 1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA7__ATDATA7_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA7__ATDATA7_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA0___M   0x00000001
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA0___S                 0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA0__ATDATA0_0             0x0
#define   DBG_PHYA_FUN_ITATBDATA0__ATDATA0__ATDATA0_1             0x1
#define   DBG_PHYA_FUN_ITATBDATA0___M            0x000001FF   
#define   DBG_PHYA_FUN_ITATBDATA0___S                          0

#define DBG_PHYA_FUN_ITATBCTR2                    (0x00BE4EF0)
#define   DBG_PHYA_FUN_ITATBCTR2___RWC              QCSR_REG_RW    
#define   DBG_PHYA_FUN_ITATBCTR2___POR           0x00000000
#define   DBG_PHYA_FUN_ITATBCTR2__AFVALID___POR  0x0
#define   DBG_PHYA_FUN_ITATBCTR2__ATREADY___POR  0x0
#define   DBG_PHYA_FUN_ITATBCTR2__AFVALID___M    0x00000002
#define   DBG_PHYA_FUN_ITATBCTR2__AFVALID___S                  1
#define   DBG_PHYA_FUN_ITATBCTR2__AFVALID__AFVALID_0             0x0
#define   DBG_PHYA_FUN_ITATBCTR2__AFVALID__AFVALID_1             0x1
#define   DBG_PHYA_FUN_ITATBCTR2__ATREADY___M    0x00000001
#define   DBG_PHYA_FUN_ITATBCTR2__ATREADY___S                  0
#define   DBG_PHYA_FUN_ITATBCTR2__ATREADY__ATREADY_0             0x0
#define   DBG_PHYA_FUN_ITATBCTR2__ATREADY__ATREADY_1             0x1
#define   DBG_PHYA_FUN_ITATBCTR2___M             0x00000003   
#define   DBG_PHYA_FUN_ITATBCTR2___S                           0

#define DBG_PHYA_FUN_ITATBCTR1                    (0x00BE4EF4)
#define   DBG_PHYA_FUN_ITATBCTR1___RWC              QCSR_REG_RW    
#define   DBG_PHYA_FUN_ITATBCTR1__ATID___M       0x0000007F
#define   DBG_PHYA_FUN_ITATBCTR1__ATID___S                     0
#define   DBG_PHYA_FUN_ITATBCTR1___M             0x0000007F   
#define   DBG_PHYA_FUN_ITATBCTR1___S                           0

#define DBG_PHYA_FUN_ITATBCTR0                    (0x00BE4EF8)
#define   DBG_PHYA_FUN_ITATBCTR0___RWC              QCSR_REG_RW    
#define   DBG_PHYA_FUN_ITATBCTR0___POR           0x00000000
#define   DBG_PHYA_FUN_ITATBCTR0__ATBYTES___POR  0x0
#define   DBG_PHYA_FUN_ITATBCTR0__AFREADY___POR  0x0
#define   DBG_PHYA_FUN_ITATBCTR0__ATVALID___POR  0x0
#define   DBG_PHYA_FUN_ITATBCTR0__ATBYTES___M    0x00000700
#define   DBG_PHYA_FUN_ITATBCTR0__ATBYTES___S                  8
#define   DBG_PHYA_FUN_ITATBCTR0__ATBYTES__ATBYTES_0             0x0
#define   DBG_PHYA_FUN_ITATBCTR0__ATBYTES__ATBYTES_1             0x1
#define   DBG_PHYA_FUN_ITATBCTR0__AFREADY___M    0x00000002
#define   DBG_PHYA_FUN_ITATBCTR0__AFREADY___S                  1
#define   DBG_PHYA_FUN_ITATBCTR0__AFREADY__AFREADY_0             0x0
#define   DBG_PHYA_FUN_ITATBCTR0__AFREADY__AFREADY_1             0x1
#define   DBG_PHYA_FUN_ITATBCTR0__ATVALID___M    0x00000001
#define   DBG_PHYA_FUN_ITATBCTR0__ATVALID___S                  0
#define   DBG_PHYA_FUN_ITATBCTR0__ATVALID__ATVALID_0             0x0
#define   DBG_PHYA_FUN_ITATBCTR0__ATVALID__ATVALID_1             0x1
#define   DBG_PHYA_FUN_ITATBCTR0___M             0x00000703   
#define   DBG_PHYA_FUN_ITATBCTR0___S                           0

#define DBG_PHYA_FUN_ITCTRL                       (0x00BE4F00)
#define   DBG_PHYA_FUN_ITCTRL___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_FUN_ITCTRL___POR              0x00000000
#define   DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0             0x0
#define   DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1             0x1
#define   DBG_PHYA_FUN_ITCTRL___M                0x00000001   
#define   DBG_PHYA_FUN_ITCTRL___S                              0

#define DBG_PHYA_FUN_CLAIMSET                     (0x00BE4FA0)
#define   DBG_PHYA_FUN_CLAIMSET___RWC               QCSR_REG_RW    
#define   DBG_PHYA_FUN_CLAIMSET___POR            0x0000000F
#define   DBG_PHYA_FUN_CLAIMSET__CLAIMSET___POR  0xF
#define   DBG_PHYA_FUN_CLAIMSET__CLAIMSET___M    0x0000000F
#define   DBG_PHYA_FUN_CLAIMSET__CLAIMSET___S                  0
#define   DBG_PHYA_FUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF             0xF
#define   DBG_PHYA_FUN_CLAIMSET___M              0x0000000F   
#define   DBG_PHYA_FUN_CLAIMSET___S                            0

#define DBG_PHYA_FUN_CLAIMCLR                     (0x00BE4FA4)
#define   DBG_PHYA_FUN_CLAIMCLR___RWC               QCSR_REG_RW    
#define   DBG_PHYA_FUN_CLAIMCLR___POR            0x00000000
#define   DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___POR  0x0
#define   DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___M    0x0000000F
#define   DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___S                  0
#define   DBG_PHYA_FUN_CLAIMCLR___M              0x0000000F   
#define   DBG_PHYA_FUN_CLAIMCLR___S                            0

#define DBG_PHYA_FUN_LOCKACCESS                   (0x00BE4FB0)
#define   DBG_PHYA_FUN_LOCKACCESS___RWC             QCSR_REG_WO    
#define   DBG_PHYA_FUN_LOCKACCESS__KEY___M       0xFFFFFFFF
#define   DBG_PHYA_FUN_LOCKACCESS__KEY___S                     0
#define   DBG_PHYA_FUN_LOCKACCESS__KEY__KEY_0XC5ACCE55      0xC5ACCE55
#define   DBG_PHYA_FUN_LOCKACCESS__KEY__KEY_0XDEADBEEF      0xDEADBEEF
#define   DBG_PHYA_FUN_LOCKACCESS___M            0xFFFFFFFF   
#define   DBG_PHYA_FUN_LOCKACCESS___S                          0

#define DBG_PHYA_FUN_LOCKSTATUS                   (0x00BE4FB4)
#define   DBG_PHYA_FUN_LOCKSTATUS___RWC             QCSR_REG_RO    
#define   DBG_PHYA_FUN_LOCKSTATUS___POR          0x00000003
#define   DBG_PHYA_FUN_LOCKSTATUS__NTT___POR     0x0
#define   DBG_PHYA_FUN_LOCKSTATUS__SLK___POR     0x1
#define   DBG_PHYA_FUN_LOCKSTATUS__SLI___POR     0x1
#define   DBG_PHYA_FUN_LOCKSTATUS__NTT___M       0x00000004
#define   DBG_PHYA_FUN_LOCKSTATUS__NTT___S                     2
#define   DBG_PHYA_FUN_LOCKSTATUS__NTT__NTT_0X0              0x0
#define   DBG_PHYA_FUN_LOCKSTATUS__SLK___M       0x00000002
#define   DBG_PHYA_FUN_LOCKSTATUS__SLK___S                     1
#define   DBG_PHYA_FUN_LOCKSTATUS__SLK__SLK_0X0              0x0
#define   DBG_PHYA_FUN_LOCKSTATUS__SLK__SLK_0X1              0x1
#define   DBG_PHYA_FUN_LOCKSTATUS__SLI___M       0x00000001
#define   DBG_PHYA_FUN_LOCKSTATUS__SLI___S                     0
#define   DBG_PHYA_FUN_LOCKSTATUS__SLI__SLI_0X0              0x0
#define   DBG_PHYA_FUN_LOCKSTATUS__SLI__SLI_0X1              0x1
#define   DBG_PHYA_FUN_LOCKSTATUS___M            0x00000007   
#define   DBG_PHYA_FUN_LOCKSTATUS___S                          0

#define DBG_PHYA_FUN_AUTHSTATUS                   (0x00BE4FB8)
#define   DBG_PHYA_FUN_AUTHSTATUS___RWC             QCSR_REG_RO    
#define   DBG_PHYA_FUN_AUTHSTATUS___POR          0x00000000
#define   DBG_PHYA_FUN_AUTHSTATUS__SNID___POR    0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__SID___POR     0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__NSNID___POR   0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__NSID___POR    0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__SNID___M      0x000000C0
#define   DBG_PHYA_FUN_AUTHSTATUS__SNID___S                    6
#define   DBG_PHYA_FUN_AUTHSTATUS__SNID__SNID_0X0             0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__SID___M       0x00000030
#define   DBG_PHYA_FUN_AUTHSTATUS__SID___S                     4
#define   DBG_PHYA_FUN_AUTHSTATUS__SID__SID_0X0              0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__NSNID___M     0x0000000C
#define   DBG_PHYA_FUN_AUTHSTATUS__NSNID___S                   2
#define   DBG_PHYA_FUN_AUTHSTATUS__NSNID__NSNID_0X0             0x0
#define   DBG_PHYA_FUN_AUTHSTATUS__NSID___M      0x00000003
#define   DBG_PHYA_FUN_AUTHSTATUS__NSID___S                    0
#define   DBG_PHYA_FUN_AUTHSTATUS__NSID__NSID_0X0             0x0
#define   DBG_PHYA_FUN_AUTHSTATUS___M            0x000000FF   
#define   DBG_PHYA_FUN_AUTHSTATUS___S                          0

#define DBG_PHYA_FUN_DEVID                        (0x00BE4FC8)
#define   DBG_PHYA_FUN_DEVID___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_DEVID___POR               0x00000038
#define   DBG_PHYA_FUN_DEVID__SCHEME___POR       0x3
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT___POR    0x8
#define   DBG_PHYA_FUN_DEVID__SCHEME___M         0x000000F0
#define   DBG_PHYA_FUN_DEVID__SCHEME___S                       4
#define   DBG_PHYA_FUN_DEVID__SCHEME__SCHEME_0X3             0x3
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT___M      0x0000000F
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT___S                    0
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X2             0x2
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X3             0x3
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X4             0x4
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X5             0x5
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X6             0x6
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X7             0x7
#define   DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X8             0x8
#define   DBG_PHYA_FUN_DEVID___M                 0x000000FF   
#define   DBG_PHYA_FUN_DEVID___S                               0

#define DBG_PHYA_FUN_DEVTYPE                      (0x00BE4FCC)
#define   DBG_PHYA_FUN_DEVTYPE___RWC                QCSR_REG_RO    
#define   DBG_PHYA_FUN_DEVTYPE___POR             0x00000012
#define   DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___POR   0x1
#define   DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___POR 0x2
#define   DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___M     0x000000F0
#define   DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___S                   4
#define   DBG_PHYA_FUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1             0x1
#define   DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___M   0x0000000F
#define   DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___S                 0
#define   DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2             0x2
#define   DBG_PHYA_FUN_DEVTYPE___M               0x000000FF   
#define   DBG_PHYA_FUN_DEVTYPE___S                             0

#define DBG_PHYA_FUN_PIDR0                        (0x00BE4FE0)
#define   DBG_PHYA_FUN_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_PIDR0___POR               0x00000008
#define   DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08
#define   DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF
#define   DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___S               0
#define   DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08            0x08
#define   DBG_PHYA_FUN_PIDR0___M                 0x000000FF   
#define   DBG_PHYA_FUN_PIDR0___S                               0

#define DBG_PHYA_FUN_PIDR1                        (0x00BE4FE4)
#define   DBG_PHYA_FUN_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_PIDR1___POR               0x000000B9
#define   DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___POR 0xB
#define   DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9
#define   DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0
#define   DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___S               4
#define   DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB             0xB
#define   DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F
#define   DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___S               0
#define   DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9             0x9
#define   DBG_PHYA_FUN_PIDR1___M                 0x000000FF   
#define   DBG_PHYA_FUN_PIDR1___S                               0

#define DBG_PHYA_FUN_PIDR2                        (0x00BE4FE8)
#define   DBG_PHYA_FUN_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_PIDR2___POR               0x0000003B
#define   DBG_PHYA_FUN_PIDR2__REVISION___POR     0x3
#define   DBG_PHYA_FUN_PIDR2__JEDEC___POR        0x1
#define   DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___POR 0x3
#define   DBG_PHYA_FUN_PIDR2__REVISION___M       0x000000F0
#define   DBG_PHYA_FUN_PIDR2__REVISION___S                     4
#define   DBG_PHYA_FUN_PIDR2__REVISION__REVISION_0X3             0x3
#define   DBG_PHYA_FUN_PIDR2__JEDEC___M          0x00000008
#define   DBG_PHYA_FUN_PIDR2__JEDEC___S                        3
#define   DBG_PHYA_FUN_PIDR2__JEDEC__JEDEC_0X1               0x1
#define   DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___M 0x00000007
#define   DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___S               0
#define   DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3             0x3
#define   DBG_PHYA_FUN_PIDR2___M                 0x000000FF   
#define   DBG_PHYA_FUN_PIDR2___S                               0

#define DBG_PHYA_FUN_PIDR3                        (0x00BE4FEC)
#define   DBG_PHYA_FUN_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_PIDR3___POR               0x00000000
#define   DBG_PHYA_FUN_PIDR3__REVAND___POR       0x0
#define   DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_FUN_PIDR3__REVAND___M         0x000000F0
#define   DBG_PHYA_FUN_PIDR3__REVAND___S                       4
#define   DBG_PHYA_FUN_PIDR3__REVAND__REVAND_0X0             0x0
#define   DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0             0x0
#define   DBG_PHYA_FUN_PIDR3___M                 0x000000FF   
#define   DBG_PHYA_FUN_PIDR3___S                               0

#define DBG_PHYA_FUN_PIDR4                        (0x00BE4FD0)
#define   DBG_PHYA_FUN_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_FUN_PIDR4___POR               0x00000004
#define   DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___POR 0x0
#define   DBG_PHYA_FUN_PIDR4__JEP106_CONT___POR  0x4
#define   DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___M   0x000000F0
#define   DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___S                 4
#define   DBG_PHYA_FUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0             0x0
#define   DBG_PHYA_FUN_PIDR4__JEP106_CONT___M    0x0000000F
#define   DBG_PHYA_FUN_PIDR4__JEP106_CONT___S                  0
#define   DBG_PHYA_FUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4             0x4
#define   DBG_PHYA_FUN_PIDR4___M                 0x000000FF   
#define   DBG_PHYA_FUN_PIDR4___S                               0

#define DBG_PHYA_FUN_PERIPHID5                    (0x00BE4FD4)
#define   DBG_PHYA_FUN_PERIPHID5___RWC              QCSR_REG_RO    
#define   DBG_PHYA_FUN_PERIPHID5___POR           0x00000000
#define   DBG_PHYA_FUN_PERIPHID5__PERIPHID5___POR 0x00000000
#define   DBG_PHYA_FUN_PERIPHID5__PERIPHID5___M  0xFFFFFFFF
#define   DBG_PHYA_FUN_PERIPHID5__PERIPHID5___S                0
#define   DBG_PHYA_FUN_PERIPHID5___M             0xFFFFFFFF   
#define   DBG_PHYA_FUN_PERIPHID5___S                           0

#define DBG_PHYA_FUN_PERIPHID6                    (0x00BE4FD8)
#define   DBG_PHYA_FUN_PERIPHID6___RWC              QCSR_REG_RO    
#define   DBG_PHYA_FUN_PERIPHID6___POR           0x00000000
#define   DBG_PHYA_FUN_PERIPHID6__PERIPHID6___POR 0x00000000
#define   DBG_PHYA_FUN_PERIPHID6__PERIPHID6___M  0xFFFFFFFF
#define   DBG_PHYA_FUN_PERIPHID6__PERIPHID6___S                0
#define   DBG_PHYA_FUN_PERIPHID6___M             0xFFFFFFFF   
#define   DBG_PHYA_FUN_PERIPHID6___S                           0

#define DBG_PHYA_FUN_PERIPHID7                    (0x00BE4FDC)
#define   DBG_PHYA_FUN_PERIPHID7___RWC              QCSR_REG_RO    
#define   DBG_PHYA_FUN_PERIPHID7___POR           0x00000000
#define   DBG_PHYA_FUN_PERIPHID7__PERIPHID7___POR 0x00000000
#define   DBG_PHYA_FUN_PERIPHID7__PERIPHID7___M  0xFFFFFFFF
#define   DBG_PHYA_FUN_PERIPHID7__PERIPHID7___S                0
#define   DBG_PHYA_FUN_PERIPHID7___M             0xFFFFFFFF   
#define   DBG_PHYA_FUN_PERIPHID7___S                           0

#define DBG_PHYA_FUN_CID0                         (0x00BE4FF0)
#define   DBG_PHYA_FUN_CID0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FUN_CID0___POR                0x0000000D
#define   DBG_PHYA_FUN_CID0__PREAMBLE___POR      0x0D
#define   DBG_PHYA_FUN_CID0__PREAMBLE___M        0x000000FF
#define   DBG_PHYA_FUN_CID0__PREAMBLE___S                      0
#define   DBG_PHYA_FUN_CID0__PREAMBLE__PREAMBLE_0X0D            0x0D
#define   DBG_PHYA_FUN_CID0___M                  0x000000FF   
#define   DBG_PHYA_FUN_CID0___S                                0

#define DBG_PHYA_FUN_CID1                         (0x00BE4FF4)
#define   DBG_PHYA_FUN_CID1___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FUN_CID1___POR                0x00000090
#define   DBG_PHYA_FUN_CID1__CLASS___POR         0x9
#define   DBG_PHYA_FUN_CID1__PREAMBLE___POR      0x0
#define   DBG_PHYA_FUN_CID1__CLASS___M           0x000000F0
#define   DBG_PHYA_FUN_CID1__CLASS___S                         4
#define   DBG_PHYA_FUN_CID1__CLASS__CLASS_0X9                0x9
#define   DBG_PHYA_FUN_CID1__PREAMBLE___M        0x0000000F
#define   DBG_PHYA_FUN_CID1__PREAMBLE___S                      0
#define   DBG_PHYA_FUN_CID1__PREAMBLE__PREAMBLE_0X0             0x0
#define   DBG_PHYA_FUN_CID1___M                  0x000000FF   
#define   DBG_PHYA_FUN_CID1___S                                0

#define DBG_PHYA_FUN_CID2                         (0x00BE4FF8)
#define   DBG_PHYA_FUN_CID2___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FUN_CID2___POR                0x00000005
#define   DBG_PHYA_FUN_CID2__PREAMBLE___POR      0x05
#define   DBG_PHYA_FUN_CID2__PREAMBLE___M        0x000000FF
#define   DBG_PHYA_FUN_CID2__PREAMBLE___S                      0
#define   DBG_PHYA_FUN_CID2__PREAMBLE__PREAMBLE_0X05            0x05
#define   DBG_PHYA_FUN_CID2___M                  0x000000FF   
#define   DBG_PHYA_FUN_CID2___S                                0

#define DBG_PHYA_FUN_CID3                         (0x00BE4FFC)
#define   DBG_PHYA_FUN_CID3___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FUN_CID3___POR                0x000000B1
#define   DBG_PHYA_FUN_CID3__PREAMBLE___POR      0xB1
#define   DBG_PHYA_FUN_CID3__PREAMBLE___M        0x000000FF
#define   DBG_PHYA_FUN_CID3__PREAMBLE___S                      0
#define   DBG_PHYA_FUN_CID3__PREAMBLE__PREAMBLE_0XB1            0xB1
#define   DBG_PHYA_FUN_CID3___M                  0x000000FF   
#define   DBG_PHYA_FUN_CID3___S                                0

#define DBG_PHYA_CTI_CTICONTROL                   (0x00BE5000)
#define   DBG_PHYA_CTI_CTICONTROL___RWC             QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTICONTROL___POR          0x00000000
#define   DBG_PHYA_CTI_CTICONTROL__GLBEN___POR   0x0
#define   DBG_PHYA_CTI_CTICONTROL__GLBEN___M     0x00000001
#define   DBG_PHYA_CTI_CTICONTROL__GLBEN___S                   0
#define   DBG_PHYA_CTI_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_PHYA_CTI_CTICONTROL__GLBEN__ENABLED             0x1
#define   DBG_PHYA_CTI_CTICONTROL___M            0x00000001   
#define   DBG_PHYA_CTI_CTICONTROL___S                          0

#define DBG_PHYA_CTI_CTIINTACK                    (0x00BE5010)
#define   DBG_PHYA_CTI_CTIINTACK___RWC              QCSR_REG_WO    
#define   DBG_PHYA_CTI_CTIINTACK___POR           0x00000000
#define   DBG_PHYA_CTI_CTIINTACK__INTACK___POR   0x000
#define   DBG_PHYA_CTI_CTIINTACK__INTACK___M     0x000003FF
#define   DBG_PHYA_CTI_CTIINTACK__INTACK___S                   0
#define   DBG_PHYA_CTI_CTIINTACK___M             0x000003FF   
#define   DBG_PHYA_CTI_CTIINTACK___S                           0

#define DBG_PHYA_CTI_CTIAPPSET                    (0x00BE5014)
#define   DBG_PHYA_CTI_CTIAPPSET___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIAPPSET___POR           0x00000000
#define   DBG_PHYA_CTI_CTIAPPSET__APPSET___POR   0x00
#define   DBG_PHYA_CTI_CTIAPPSET__APPSET___M     0x000000FF
#define   DBG_PHYA_CTI_CTIAPPSET__APPSET___S                   0
#define   DBG_PHYA_CTI_CTIAPPSET___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIAPPSET___S                           0

#define DBG_PHYA_CTI_CTIAPPCLEAR                  (0x00BE5018)
#define   DBG_PHYA_CTI_CTIAPPCLEAR___RWC            QCSR_REG_WO    
#define   DBG_PHYA_CTI_CTIAPPCLEAR___POR         0x00000000
#define   DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___M 0x000000FF
#define   DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___S               0
#define   DBG_PHYA_CTI_CTIAPPCLEAR___M           0x000000FF   
#define   DBG_PHYA_CTI_CTIAPPCLEAR___S                         0

#define DBG_PHYA_CTI_CTIAPPPULSE                  (0x00BE501C)
#define   DBG_PHYA_CTI_CTIAPPPULSE___RWC            QCSR_REG_WO    
#define   DBG_PHYA_CTI_CTIAPPPULSE___POR         0x00000000
#define   DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___POR 0x00
#define   DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___M  0x000000FF
#define   DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___S                0
#define   DBG_PHYA_CTI_CTIAPPPULSE___M           0x000000FF   
#define   DBG_PHYA_CTI_CTIAPPPULSE___S                         0

#define DBG_PHYA_CTI_CTIINEN0                     (0x00BE5020)
#define   DBG_PHYA_CTI_CTIINEN0___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN0___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN0__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN0__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN0__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN0___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN0___S                            0

#define DBG_PHYA_CTI_CTIINEN1                     (0x00BE5024)
#define   DBG_PHYA_CTI_CTIINEN1___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN1___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN1__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN1__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN1__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN1___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN1___S                            0

#define DBG_PHYA_CTI_CTIINEN2                     (0x00BE5028)
#define   DBG_PHYA_CTI_CTIINEN2___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN2___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN2__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN2__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN2__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN2___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN2___S                            0

#define DBG_PHYA_CTI_CTIINEN3                     (0x00BE502C)
#define   DBG_PHYA_CTI_CTIINEN3___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN3___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN3__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN3__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN3__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN3___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN3___S                            0

#define DBG_PHYA_CTI_CTIINEN4                     (0x00BE5030)
#define   DBG_PHYA_CTI_CTIINEN4___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN4___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN4__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN4__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN4__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN4___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN4___S                            0

#define DBG_PHYA_CTI_CTIINEN5                     (0x00BE5034)
#define   DBG_PHYA_CTI_CTIINEN5___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN5___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN5__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN5__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN5__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN5___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN5___S                            0

#define DBG_PHYA_CTI_CTIINEN6                     (0x00BE5038)
#define   DBG_PHYA_CTI_CTIINEN6___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN6___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN6__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN6__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN6__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN6___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN6___S                            0

#define DBG_PHYA_CTI_CTIINEN7                     (0x00BE503C)
#define   DBG_PHYA_CTI_CTIINEN7___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN7___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN7__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN7__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN7__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN7___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN7___S                            0

#define DBG_PHYA_CTI_CTIINEN8                     (0x00BE5040)
#define   DBG_PHYA_CTI_CTIINEN8___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN8___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN8__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN8__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN8__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN8___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN8___S                            0

#define DBG_PHYA_CTI_CTIINEN9                     (0x00BE5044)
#define   DBG_PHYA_CTI_CTIINEN9___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIINEN9___POR            0x00000000
#define   DBG_PHYA_CTI_CTIINEN9__TRIGINEN___POR  0x00
#define   DBG_PHYA_CTI_CTIINEN9__TRIGINEN___M    0x000000FF
#define   DBG_PHYA_CTI_CTIINEN9__TRIGINEN___S                  0
#define   DBG_PHYA_CTI_CTIINEN9___M              0x000000FF   
#define   DBG_PHYA_CTI_CTIINEN9___S                            0

#define DBG_PHYA_CTI_CTIOUTEN0                    (0x00BE50A0)
#define   DBG_PHYA_CTI_CTIOUTEN0___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN0___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN0___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN0___S                           0

#define DBG_PHYA_CTI_CTIOUTEN1                    (0x00BE50A4)
#define   DBG_PHYA_CTI_CTIOUTEN1___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN1___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN1___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN1___S                           0

#define DBG_PHYA_CTI_CTIOUTEN2                    (0x00BE50A8)
#define   DBG_PHYA_CTI_CTIOUTEN2___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN2___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN2___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN2___S                           0

#define DBG_PHYA_CTI_CTIOUTEN3                    (0x00BE50AC)
#define   DBG_PHYA_CTI_CTIOUTEN3___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN3___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN3___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN3___S                           0

#define DBG_PHYA_CTI_CTIOUTEN4                    (0x00BE50B0)
#define   DBG_PHYA_CTI_CTIOUTEN4___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN4___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN4___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN4___S                           0

#define DBG_PHYA_CTI_CTIOUTEN5                    (0x00BE50B4)
#define   DBG_PHYA_CTI_CTIOUTEN5___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN5___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN5___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN5___S                           0

#define DBG_PHYA_CTI_CTIOUTEN6                    (0x00BE50B8)
#define   DBG_PHYA_CTI_CTIOUTEN6___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN6___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN6___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN6___S                           0

#define DBG_PHYA_CTI_CTIOUTEN7                    (0x00BE50BC)
#define   DBG_PHYA_CTI_CTIOUTEN7___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN7___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN7___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN7___S                           0

#define DBG_PHYA_CTI_CTIOUTEN8                    (0x00BE50C0)
#define   DBG_PHYA_CTI_CTIOUTEN8___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN8___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN8___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN8___S                           0

#define DBG_PHYA_CTI_CTIOUTEN9                    (0x00BE50C4)
#define   DBG_PHYA_CTI_CTIOUTEN9___RWC              QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIOUTEN9___POR           0x00000000
#define   DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___M  0x000000FF
#define   DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___S                0
#define   DBG_PHYA_CTI_CTIOUTEN9___M             0x000000FF   
#define   DBG_PHYA_CTI_CTIOUTEN9___S                           0

#define DBG_PHYA_CTI_CTITRIGINSTATUS              (0x00BE5130)
#define   DBG_PHYA_CTI_CTITRIGINSTATUS___RWC        QCSR_REG_RO    
#define   DBG_PHYA_CTI_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000003FF
#define   DBG_PHYA_CTI_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_PHYA_CTI_CTITRIGINSTATUS___M       0x000003FF   
#define   DBG_PHYA_CTI_CTITRIGINSTATUS___S                     0

#define DBG_PHYA_CTI_CTITRIGOUTSTATUS             (0x00BE5134)
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS___RWC       QCSR_REG_RO    
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS___POR    0x00000000
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x000
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000003FF
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS___M      0x000003FF   
#define   DBG_PHYA_CTI_CTITRIGOUTSTATUS___S                    0

#define DBG_PHYA_CTI_CTICHINSTATUS                (0x00BE5138)
#define   DBG_PHYA_CTI_CTICHINSTATUS___RWC          QCSR_REG_RO    
#define   DBG_PHYA_CTI_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_PHYA_CTI_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_PHYA_CTI_CTICHINSTATUS___M         0x000000FF   
#define   DBG_PHYA_CTI_CTICHINSTATUS___S                       0

#define DBG_PHYA_CTI_CTICHOUTSTATUS               (0x00BE513C)
#define   DBG_PHYA_CTI_CTICHOUTSTATUS___RWC         QCSR_REG_RO    
#define   DBG_PHYA_CTI_CTICHOUTSTATUS___POR      0x00000000
#define   DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_PHYA_CTI_CTICHOUTSTATUS___M        0x000000FF   
#define   DBG_PHYA_CTI_CTICHOUTSTATUS___S                      0

#define DBG_PHYA_CTI_CTIGATE                      (0x00BE5140)
#define   DBG_PHYA_CTI_CTIGATE___RWC                QCSR_REG_RW    
#define   DBG_PHYA_CTI_CTIGATE___POR             0x000000FF
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___POR 0x1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___M   0x00000080
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___S                 7
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___M   0x00000040
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___S                 6
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___M   0x00000020
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___S                 5
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___M   0x00000010
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___S                 4
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___M   0x00000008
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___S                 3
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___M   0x00000004
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___S                 2
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___M   0x00000002
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___S                 1
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___M   0x00000001
#define   DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___S                 0
#define   DBG_PHYA_CTI_CTIGATE___M               0x000000FF   
#define   DBG_PHYA_CTI_CTIGATE___S                             0

#define DBG_PHYA_CTI_ASICCTL                      (0x00BE5144)
#define   DBG_PHYA_CTI_ASICCTL___RWC                QCSR_REG_RW    
#define   DBG_PHYA_CTI_ASICCTL___POR             0x00000000
#define   DBG_PHYA_CTI_ASICCTL__ASICCTL___POR    0x00000000
#define   DBG_PHYA_CTI_ASICCTL__ASICCTL___M      0xFFFFFFFF
#define   DBG_PHYA_CTI_ASICCTL__ASICCTL___S                    0
#define   DBG_PHYA_CTI_ASICCTL___M               0xFFFFFFFF   
#define   DBG_PHYA_CTI_ASICCTL___S                             0

#define DBG_PHYA_CTI_ITCHINACK                    (0x00BE5EDC)
#define   DBG_PHYA_CTI_ITCHINACK___RWC              QCSR_REG_WO    
#define   DBG_PHYA_CTI_ITCHINACK___POR           0x00000000
#define   DBG_PHYA_CTI_ITCHINACK__CTCHINACK___POR 0x00
#define   DBG_PHYA_CTI_ITCHINACK__CTCHINACK___M  0x000000FF
#define   DBG_PHYA_CTI_ITCHINACK__CTCHINACK___S                0
#define   DBG_PHYA_CTI_ITCHINACK___M             0x000000FF   
#define   DBG_PHYA_CTI_ITCHINACK___S                           0

#define DBG_PHYA_CTI_ITTRIGINACK                  (0x00BE5EE0)
#define   DBG_PHYA_CTI_ITTRIGINACK___RWC            QCSR_REG_WO    
#define   DBG_PHYA_CTI_ITTRIGINACK___POR         0x00000000
#define   DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___POR 0x000
#define   DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___M 0x000003FF
#define   DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_PHYA_CTI_ITTRIGINACK___M           0x000003FF   
#define   DBG_PHYA_CTI_ITTRIGINACK___S                         0

#define DBG_PHYA_CTI_ITCHOUT                      (0x00BE5EE4)
#define   DBG_PHYA_CTI_ITCHOUT___RWC                QCSR_REG_WO    
#define   DBG_PHYA_CTI_ITCHOUT___POR             0x00000000
#define   DBG_PHYA_CTI_ITCHOUT__CTCHOUT___POR    0x00
#define   DBG_PHYA_CTI_ITCHOUT__CTCHOUT___M      0x000000FF
#define   DBG_PHYA_CTI_ITCHOUT__CTCHOUT___S                    0
#define   DBG_PHYA_CTI_ITCHOUT___M               0x000000FF   
#define   DBG_PHYA_CTI_ITCHOUT___S                             0

#define DBG_PHYA_CTI_ITTRIGOUT                    (0x00BE5EE8)
#define   DBG_PHYA_CTI_ITTRIGOUT___RWC              QCSR_REG_WO    
#define   DBG_PHYA_CTI_ITTRIGOUT___POR           0x00000000
#define   DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___POR 0x000
#define   DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___M  0x000003FF
#define   DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___S                0
#define   DBG_PHYA_CTI_ITTRIGOUT___M             0x000003FF   
#define   DBG_PHYA_CTI_ITTRIGOUT___S                           0

#define DBG_PHYA_CTI_ITCHOUTACK                   (0x00BE5EEC)
#define   DBG_PHYA_CTI_ITCHOUTACK___RWC             QCSR_REG_RO    
#define   DBG_PHYA_CTI_ITCHOUTACK___POR          0x00000000
#define   DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___M 0x000000FF
#define   DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___S               0
#define   DBG_PHYA_CTI_ITCHOUTACK___M            0x000000FF   
#define   DBG_PHYA_CTI_ITCHOUTACK___S                          0

#define DBG_PHYA_CTI_ITTRIGOUTACK                 (0x00BE5EF0)
#define   DBG_PHYA_CTI_ITTRIGOUTACK___RWC           QCSR_REG_RO    
#define   DBG_PHYA_CTI_ITTRIGOUTACK___POR        0x00000000
#define   DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x000
#define   DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000003FF
#define   DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_PHYA_CTI_ITTRIGOUTACK___M          0x000003FF   
#define   DBG_PHYA_CTI_ITTRIGOUTACK___S                        0

#define DBG_PHYA_CTI_ITCHIN                       (0x00BE5EF4)
#define   DBG_PHYA_CTI_ITCHIN___RWC                 QCSR_REG_RO    
#define   DBG_PHYA_CTI_ITCHIN___POR              0x00000000
#define   DBG_PHYA_CTI_ITCHIN__CTCHIN___POR      0x00
#define   DBG_PHYA_CTI_ITCHIN__CTCHIN___M        0x000000FF
#define   DBG_PHYA_CTI_ITCHIN__CTCHIN___S                      0
#define   DBG_PHYA_CTI_ITCHIN___M                0x000000FF   
#define   DBG_PHYA_CTI_ITCHIN___S                              0

#define DBG_PHYA_CTI_ITTRIGIN                     (0x00BE5EF8)
#define   DBG_PHYA_CTI_ITTRIGIN___RWC               QCSR_REG_RO    
#define   DBG_PHYA_CTI_ITTRIGIN___POR            0x00000000
#define   DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___POR  0x000
#define   DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___M    0x000003FF
#define   DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___S                  0
#define   DBG_PHYA_CTI_ITTRIGIN___M              0x000003FF   
#define   DBG_PHYA_CTI_ITTRIGIN___S                            0

#define DBG_PHYA_CTI_ITCTRL                       (0x00BE5F00)
#define   DBG_PHYA_CTI_ITCTRL___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_CTI_ITCTRL___POR              0x00000000
#define   DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_PHYA_CTI_ITCTRL___M                0x00000001   
#define   DBG_PHYA_CTI_ITCTRL___S                              0

#define DBG_PHYA_CTI_CLAIMSET                     (0x00BE5FA0)
#define   DBG_PHYA_CTI_CLAIMSET___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CLAIMSET___POR            0x0000000F
#define   DBG_PHYA_CTI_CLAIMSET__CLAIMSET___POR  0xF
#define   DBG_PHYA_CTI_CLAIMSET__CLAIMSET___M    0x0000000F
#define   DBG_PHYA_CTI_CLAIMSET__CLAIMSET___S                  0
#define   DBG_PHYA_CTI_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_PHYA_CTI_CLAIMSET___M              0x0000000F   
#define   DBG_PHYA_CTI_CLAIMSET___S                            0

#define DBG_PHYA_CTI_CLAIMCLR                     (0x00BE5FA4)
#define   DBG_PHYA_CTI_CLAIMCLR___RWC               QCSR_REG_RW    
#define   DBG_PHYA_CTI_CLAIMCLR___POR            0x00000000
#define   DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___POR  0x0
#define   DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___M    0x0000000F
#define   DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___S                  0
#define   DBG_PHYA_CTI_CLAIMCLR___M              0x0000000F   
#define   DBG_PHYA_CTI_CLAIMCLR___S                            0

#define DBG_PHYA_CTI_DEVAFF0                      (0x00BE5FA8)
#define   DBG_PHYA_CTI_DEVAFF0___RWC                QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVAFF0___POR             0x00000000
#define   DBG_PHYA_CTI_DEVAFF0__VAL___POR        0x00000000
#define   DBG_PHYA_CTI_DEVAFF0__VAL___M          0xFFFFFFFF
#define   DBG_PHYA_CTI_DEVAFF0__VAL___S                        0
#define   DBG_PHYA_CTI_DEVAFF0___M               0xFFFFFFFF   
#define   DBG_PHYA_CTI_DEVAFF0___S                             0

#define DBG_PHYA_CTI_DEVAFF1                      (0x00BE5FAC)
#define   DBG_PHYA_CTI_DEVAFF1___RWC                QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVAFF1___POR             0x00000000
#define   DBG_PHYA_CTI_DEVAFF1__VAL___POR        0x00000000
#define   DBG_PHYA_CTI_DEVAFF1__VAL___M          0xFFFFFFFF
#define   DBG_PHYA_CTI_DEVAFF1__VAL___S                        0
#define   DBG_PHYA_CTI_DEVAFF1___M               0xFFFFFFFF   
#define   DBG_PHYA_CTI_DEVAFF1___S                             0

#define DBG_PHYA_CTI_LAR                          (0x00BE5FB0)
#define   DBG_PHYA_CTI_LAR___RWC                    QCSR_REG_WO    
#define   DBG_PHYA_CTI_LAR__ACCESS_W___M         0xFFFFFFFF
#define   DBG_PHYA_CTI_LAR__ACCESS_W___S                       0
#define   DBG_PHYA_CTI_LAR__ACCESS_W__UNLOCK          0xC5ACCE55
#define   DBG_PHYA_CTI_LAR___M                   0xFFFFFFFF   
#define   DBG_PHYA_CTI_LAR___S                                 0

#define DBG_PHYA_CTI_LSR                          (0x00BE5FB4)
#define   DBG_PHYA_CTI_LSR___RWC                    QCSR_REG_RO    
#define   DBG_PHYA_CTI_LSR___POR                 0x00000003
#define   DBG_PHYA_CTI_LSR__LOCKTYPE___POR       0x0
#define   DBG_PHYA_CTI_LSR__LOCKGRANT___POR      0x1
#define   DBG_PHYA_CTI_LSR__LOCKEXIST___POR      0x1
#define   DBG_PHYA_CTI_LSR__LOCKTYPE___M         0x00000004
#define   DBG_PHYA_CTI_LSR__LOCKTYPE___S                       2
#define   DBG_PHYA_CTI_LSR__LOCKTYPE__SIZE_32BIT             0x0
#define   DBG_PHYA_CTI_LSR__LOCKGRANT___M        0x00000002
#define   DBG_PHYA_CTI_LSR__LOCKGRANT___S                      1
#define   DBG_PHYA_CTI_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_PHYA_CTI_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_PHYA_CTI_LSR__LOCKEXIST___M        0x00000001
#define   DBG_PHYA_CTI_LSR__LOCKEXIST___S                      0
#define   DBG_PHYA_CTI_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_PHYA_CTI_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_PHYA_CTI_LSR___M                   0x00000007   
#define   DBG_PHYA_CTI_LSR___S                                 0

#define DBG_PHYA_CTI_AUTHSTATUS                   (0x00BE5FB8)
#define   DBG_PHYA_CTI_AUTHSTATUS___RWC             QCSR_REG_RO    
#define   DBG_PHYA_CTI_AUTHSTATUS__SNID___M      0x000000C0
#define   DBG_PHYA_CTI_AUTHSTATUS__SNID___S                    6
#define   DBG_PHYA_CTI_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_PHYA_CTI_AUTHSTATUS__SID___M       0x00000030
#define   DBG_PHYA_CTI_AUTHSTATUS__SID___S                     4
#define   DBG_PHYA_CTI_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_PHYA_CTI_AUTHSTATUS__NSNID___M     0x0000000C
#define   DBG_PHYA_CTI_AUTHSTATUS__NSNID___S                   2
#define   DBG_PHYA_CTI_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_PHYA_CTI_AUTHSTATUS__NSNID__ENABLED             0x3
#define   DBG_PHYA_CTI_AUTHSTATUS__NSID___M      0x00000003
#define   DBG_PHYA_CTI_AUTHSTATUS__NSID___S                    0
#define   DBG_PHYA_CTI_AUTHSTATUS__NSID__DISABLED             0x2
#define   DBG_PHYA_CTI_AUTHSTATUS__NSID__ENABLED             0x3
#define   DBG_PHYA_CTI_AUTHSTATUS___M            0x000000FF   
#define   DBG_PHYA_CTI_AUTHSTATUS___S                          0

#define DBG_PHYA_CTI_DEVARCH                      (0x00BE5FBC)
#define   DBG_PHYA_CTI_DEVARCH___RWC                QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVARCH___POR             0x8EF00A14
#define   DBG_PHYA_CTI_DEVARCH__ARCHITECT___POR  0x477
#define   DBG_PHYA_CTI_DEVARCH__PRESENT___POR    0x1
#define   DBG_PHYA_CTI_DEVARCH__REVISION___POR   0x0
#define   DBG_PHYA_CTI_DEVARCH__ARCHID___POR     0x0A14
#define   DBG_PHYA_CTI_DEVARCH__ARCHITECT___M    0xFFE00000
#define   DBG_PHYA_CTI_DEVARCH__ARCHITECT___S                 21
#define   DBG_PHYA_CTI_DEVARCH__PRESENT___M      0x00100000
#define   DBG_PHYA_CTI_DEVARCH__PRESENT___S                   20
#define   DBG_PHYA_CTI_DEVARCH__REVISION___M     0x000F0000
#define   DBG_PHYA_CTI_DEVARCH__REVISION___S                  16
#define   DBG_PHYA_CTI_DEVARCH__ARCHID___M       0x0000FFFF
#define   DBG_PHYA_CTI_DEVARCH__ARCHID___S                     0
#define   DBG_PHYA_CTI_DEVARCH___M               0xFFFFFFFF   
#define   DBG_PHYA_CTI_DEVARCH___S                             0

#define DBG_PHYA_CTI_DEVID2                       (0x00BE5FC0)
#define   DBG_PHYA_CTI_DEVID2___RWC                 QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVID2___POR              0x00000000
#define   DBG_PHYA_CTI_DEVID2__IMPLDEF___POR     0x0
#define   DBG_PHYA_CTI_DEVID2__IMPLDEF___M       0x00000001
#define   DBG_PHYA_CTI_DEVID2__IMPLDEF___S                     0
#define   DBG_PHYA_CTI_DEVID2___M                0x00000001   
#define   DBG_PHYA_CTI_DEVID2___S                              0

#define DBG_PHYA_CTI_DEVID1                       (0x00BE5FC4)
#define   DBG_PHYA_CTI_DEVID1___RWC                 QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVID1___POR              0x00000000
#define   DBG_PHYA_CTI_DEVID1__IMPLDEF___POR     0x0
#define   DBG_PHYA_CTI_DEVID1__IMPLDEF___M       0x00000001
#define   DBG_PHYA_CTI_DEVID1__IMPLDEF___S                     0
#define   DBG_PHYA_CTI_DEVID1___M                0x00000001   
#define   DBG_PHYA_CTI_DEVID1___S                              0

#define DBG_PHYA_CTI_DEVID                        (0x00BE5FC8)
#define   DBG_PHYA_CTI_DEVID___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVID___POR               0x00080A00
#define   DBG_PHYA_CTI_DEVID__NUMCH___POR        0x8
#define   DBG_PHYA_CTI_DEVID__NUMTRIG___POR      0xA
#define   DBG_PHYA_CTI_DEVID__EXTMUXNUM___POR    0x00
#define   DBG_PHYA_CTI_DEVID__NUMCH___M          0x003F0000
#define   DBG_PHYA_CTI_DEVID__NUMCH___S                       16
#define   DBG_PHYA_CTI_DEVID__NUMTRIG___M        0x0000FF00
#define   DBG_PHYA_CTI_DEVID__NUMTRIG___S                      8
#define   DBG_PHYA_CTI_DEVID__EXTMUXNUM___M      0x0000001F
#define   DBG_PHYA_CTI_DEVID__EXTMUXNUM___S                    0
#define   DBG_PHYA_CTI_DEVID___M                 0x003FFF1F   
#define   DBG_PHYA_CTI_DEVID___S                               0

#define DBG_PHYA_CTI_DEVTYPE                      (0x00BE5FCC)
#define   DBG_PHYA_CTI_DEVTYPE___RWC                QCSR_REG_RO    
#define   DBG_PHYA_CTI_DEVTYPE___POR             0x00000014
#define   DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___POR   0x1
#define   DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___POR 0x4
#define   DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___M     0x000000F0
#define   DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___S                   4
#define   DBG_PHYA_CTI_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___M   0x0000000F
#define   DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___S                 0
#define   DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_PHYA_CTI_DEVTYPE___M               0x000000FF   
#define   DBG_PHYA_CTI_DEVTYPE___S                             0

#define DBG_PHYA_CTI_PIDR0                        (0x00BE5FE0)
#define   DBG_PHYA_CTI_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_PIDR0___POR               0x00000006
#define   DBG_PHYA_CTI_PIDR0__PART_0___POR       0x06
#define   DBG_PHYA_CTI_PIDR0__PART_0___M         0x000000FF
#define   DBG_PHYA_CTI_PIDR0__PART_0___S                       0
#define   DBG_PHYA_CTI_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_PHYA_CTI_PIDR0___M                 0x000000FF   
#define   DBG_PHYA_CTI_PIDR0___S                               0

#define DBG_PHYA_CTI_PIDR1                        (0x00BE5FE4)
#define   DBG_PHYA_CTI_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_PIDR1___POR               0x000000B9
#define   DBG_PHYA_CTI_PIDR1__DES_0___POR        0xB
#define   DBG_PHYA_CTI_PIDR1__PART_1___POR       0x9
#define   DBG_PHYA_CTI_PIDR1__DES_0___M          0x000000F0
#define   DBG_PHYA_CTI_PIDR1__DES_0___S                        4
#define   DBG_PHYA_CTI_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_PHYA_CTI_PIDR1__PART_1___M         0x0000000F
#define   DBG_PHYA_CTI_PIDR1__PART_1___S                       0
#define   DBG_PHYA_CTI_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_PHYA_CTI_PIDR1___M                 0x000000FF   
#define   DBG_PHYA_CTI_PIDR1___S                               0

#define DBG_PHYA_CTI_PIDR2                        (0x00BE5FE8)
#define   DBG_PHYA_CTI_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_PIDR2___POR               0x0000004B
#define   DBG_PHYA_CTI_PIDR2__REVISION___POR     0x4
#define   DBG_PHYA_CTI_PIDR2__JEDEC___POR        0x1
#define   DBG_PHYA_CTI_PIDR2__DES_1___POR        0x3
#define   DBG_PHYA_CTI_PIDR2__REVISION___M       0x000000F0
#define   DBG_PHYA_CTI_PIDR2__REVISION___S                     4
#define   DBG_PHYA_CTI_PIDR2__REVISION__R0P4                 0x4
#define   DBG_PHYA_CTI_PIDR2__REVISION__R0P5                 0x5
#define   DBG_PHYA_CTI_PIDR2__JEDEC___M          0x00000008
#define   DBG_PHYA_CTI_PIDR2__JEDEC___S                        3
#define   DBG_PHYA_CTI_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_PHYA_CTI_PIDR2__DES_1___M          0x00000007
#define   DBG_PHYA_CTI_PIDR2__DES_1___S                        0
#define   DBG_PHYA_CTI_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_PHYA_CTI_PIDR2___M                 0x000000FF   
#define   DBG_PHYA_CTI_PIDR2___S                               0

#define DBG_PHYA_CTI_PIDR3                        (0x00BE5FEC)
#define   DBG_PHYA_CTI_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_PIDR3___POR               0x00000000
#define   DBG_PHYA_CTI_PIDR3__REVAND___POR       0x0
#define   DBG_PHYA_CTI_PIDR3__CMOD___POR         0x0
#define   DBG_PHYA_CTI_PIDR3__REVAND___M         0x000000F0
#define   DBG_PHYA_CTI_PIDR3__REVAND___S                       4
#define   DBG_PHYA_CTI_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_PHYA_CTI_PIDR3__CMOD___M           0x0000000F
#define   DBG_PHYA_CTI_PIDR3__CMOD___S                         0
#define   DBG_PHYA_CTI_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_PHYA_CTI_PIDR3___M                 0x000000FF   
#define   DBG_PHYA_CTI_PIDR3___S                               0

#define DBG_PHYA_CTI_PIDR4                        (0x00BE5FD0)
#define   DBG_PHYA_CTI_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_PIDR4___POR               0x00000004
#define   DBG_PHYA_CTI_PIDR4__SIZE___POR         0x0
#define   DBG_PHYA_CTI_PIDR4__DES_2___POR        0x4
#define   DBG_PHYA_CTI_PIDR4__SIZE___M           0x000000F0
#define   DBG_PHYA_CTI_PIDR4__SIZE___S                         4
#define   DBG_PHYA_CTI_PIDR4__SIZE__SIZE_4KB                 0x0
#define   DBG_PHYA_CTI_PIDR4__DES_2___M          0x0000000F
#define   DBG_PHYA_CTI_PIDR4__DES_2___S                        0
#define   DBG_PHYA_CTI_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_PHYA_CTI_PIDR4___M                 0x000000FF   
#define   DBG_PHYA_CTI_PIDR4___S                               0

#define DBG_PHYA_CTI_PIDR5                        (0x00BE5FD4)
#define   DBG_PHYA_CTI_PIDR5___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_CTI_PIDR5__PERIPHID5___M      0xFFFFFFFF
#define   DBG_PHYA_CTI_PIDR5__PERIPHID5___S                    0
#define   DBG_PHYA_CTI_PIDR5___M                 0xFFFFFFFF   
#define   DBG_PHYA_CTI_PIDR5___S                               0

#define DBG_PHYA_CTI_PIDR6                        (0x00BE5FD8)
#define   DBG_PHYA_CTI_PIDR6___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_CTI_PIDR6__PERIPHID6___M      0xFFFFFFFF
#define   DBG_PHYA_CTI_PIDR6__PERIPHID6___S                    0
#define   DBG_PHYA_CTI_PIDR6___M                 0xFFFFFFFF   
#define   DBG_PHYA_CTI_PIDR6___S                               0

#define DBG_PHYA_CTI_PIDR7                        (0x00BE5FDC)
#define   DBG_PHYA_CTI_PIDR7___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_CTI_PIDR7__PERIPHID7___M      0xFFFFFFFF
#define   DBG_PHYA_CTI_PIDR7__PERIPHID7___S                    0
#define   DBG_PHYA_CTI_PIDR7___M                 0xFFFFFFFF   
#define   DBG_PHYA_CTI_PIDR7___S                               0

#define DBG_PHYA_CTI_CIDR0                        (0x00BE5FF0)
#define   DBG_PHYA_CTI_CIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_CIDR0___POR               0x0000000D
#define   DBG_PHYA_CTI_CIDR0__PRMBL_0___POR      0x0D
#define   DBG_PHYA_CTI_CIDR0__PRMBL_0___M        0x000000FF
#define   DBG_PHYA_CTI_CIDR0__PRMBL_0___S                      0
#define   DBG_PHYA_CTI_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_PHYA_CTI_CIDR0___M                 0x000000FF   
#define   DBG_PHYA_CTI_CIDR0___S                               0

#define DBG_PHYA_CTI_CIDR1                        (0x00BE5FF4)
#define   DBG_PHYA_CTI_CIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_CIDR1___POR               0x00000090
#define   DBG_PHYA_CTI_CIDR1__CLASS___POR        0x9
#define   DBG_PHYA_CTI_CIDR1__PRMBL_1___POR      0x0
#define   DBG_PHYA_CTI_CIDR1__CLASS___M          0x000000F0
#define   DBG_PHYA_CTI_CIDR1__CLASS___S                        4
#define   DBG_PHYA_CTI_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_PHYA_CTI_CIDR1__PRMBL_1___M        0x0000000F
#define   DBG_PHYA_CTI_CIDR1__PRMBL_1___S                      0
#define   DBG_PHYA_CTI_CIDR1__PRMBL_1__ID_VALUE_0             0x0
#define   DBG_PHYA_CTI_CIDR1___M                 0x000000FF   
#define   DBG_PHYA_CTI_CIDR1___S                               0

#define DBG_PHYA_CTI_CIDR2                        (0x00BE5FF8)
#define   DBG_PHYA_CTI_CIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_CIDR2___POR               0x00000005
#define   DBG_PHYA_CTI_CIDR2__PRMBL_2___POR      0x05
#define   DBG_PHYA_CTI_CIDR2__PRMBL_2___M        0x000000FF
#define   DBG_PHYA_CTI_CIDR2__PRMBL_2___S                      0
#define   DBG_PHYA_CTI_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_PHYA_CTI_CIDR2___M                 0x000000FF   
#define   DBG_PHYA_CTI_CIDR2___S                               0

#define DBG_PHYA_CTI_CIDR3                        (0x00BE5FFC)
#define   DBG_PHYA_CTI_CIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_CTI_CIDR3___POR               0x000000B1
#define   DBG_PHYA_CTI_CIDR3__PRMBL_3___POR      0xB1
#define   DBG_PHYA_CTI_CIDR3__PRMBL_3___M        0x000000FF
#define   DBG_PHYA_CTI_CIDR3__PRMBL_3___S                      0
#define   DBG_PHYA_CTI_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_PHYA_CTI_CIDR3___M                 0x000000FF   
#define   DBG_PHYA_CTI_CIDR3___S                               0

#define DBG_PHYA_TRC_CFG                          (0x00BE6000)
#define   DBG_PHYA_TRC_CFG___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_TRC_CFG___POR                 0x00006E03
#define   DBG_PHYA_TRC_CFG__ATID___POR           0x6E
#define   DBG_PHYA_TRC_CFG__TSTMPEN___POR        0x1
#define   DBG_PHYA_TRC_CFG__ENABLE___POR         0x1
#define   DBG_PHYA_TRC_CFG__ATID___M             0x00007F00
#define   DBG_PHYA_TRC_CFG__ATID___S                           8
#define   DBG_PHYA_TRC_CFG__TSTMPEN___M          0x00000002
#define   DBG_PHYA_TRC_CFG__TSTMPEN___S                        1
#define   DBG_PHYA_TRC_CFG__ENABLE___M           0x00000001
#define   DBG_PHYA_TRC_CFG__ENABLE___S                         0
#define   DBG_PHYA_TRC_CFG___M                   0x00007F03   
#define   DBG_PHYA_TRC_CFG___S                                 0

#define DBG_PHYA_ITM_WR_STIMn(n)         (0x00BE8000+0x4*(n))
#define   DBG_PHYA_ITM_WR_STIMn_nMIN 0    
#define   DBG_PHYA_ITM_WR_STIMn_nMAX 31   
#define   DBG_PHYA_ITM_WR_STIMn_ELEM 32   
#define   DBG_PHYA_ITM_WR_STIMn___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIMn___POR            0x00000000
#define   DBG_PHYA_ITM_WR_STIMn__STIMULUS___POR  0x00000000
#define   DBG_PHYA_ITM_WR_STIMn__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIMn__STIMULUS___S                  0
#define   DBG_PHYA_ITM_WR_STIMn___M              0xFFFFFFFF   
#define   DBG_PHYA_ITM_WR_STIMn___S                            0
#define DBG_PHYA_ITM_WR_STIM0                     (0x00BE8000)
#define   DBG_PHYA_ITM_WR_STIM0___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM0__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM0__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM1                     (0x00BE8004)
#define   DBG_PHYA_ITM_WR_STIM1___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM1__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM1__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM2                     (0x00BE8008)
#define   DBG_PHYA_ITM_WR_STIM2___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM2__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM2__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM3                     (0x00BE800C)
#define   DBG_PHYA_ITM_WR_STIM3___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM3__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM3__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM4                     (0x00BE8010)
#define   DBG_PHYA_ITM_WR_STIM4___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM4__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM4__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM5                     (0x00BE8014)
#define   DBG_PHYA_ITM_WR_STIM5___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM5__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM5__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM6                     (0x00BE8018)
#define   DBG_PHYA_ITM_WR_STIM6___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM6__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM6__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM7                     (0x00BE801C)
#define   DBG_PHYA_ITM_WR_STIM7___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM7__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM7__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM8                     (0x00BE8020)
#define   DBG_PHYA_ITM_WR_STIM8___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM8__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM8__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM9                     (0x00BE8024)
#define   DBG_PHYA_ITM_WR_STIM9___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM9__STIMULUS___M    0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM9__STIMULUS___S                  0
#define DBG_PHYA_ITM_WR_STIM10                    (0x00BE8028)
#define   DBG_PHYA_ITM_WR_STIM10___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM10__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM10__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM11                    (0x00BE802C)
#define   DBG_PHYA_ITM_WR_STIM11___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM11__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM11__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM12                    (0x00BE8030)
#define   DBG_PHYA_ITM_WR_STIM12___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM12__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM12__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM13                    (0x00BE8034)
#define   DBG_PHYA_ITM_WR_STIM13___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM13__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM13__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM14                    (0x00BE8038)
#define   DBG_PHYA_ITM_WR_STIM14___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM14__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM14__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM15                    (0x00BE803C)
#define   DBG_PHYA_ITM_WR_STIM15___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM15__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM15__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM16                    (0x00BE8040)
#define   DBG_PHYA_ITM_WR_STIM16___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM16__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM16__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM17                    (0x00BE8044)
#define   DBG_PHYA_ITM_WR_STIM17___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM17__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM17__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM18                    (0x00BE8048)
#define   DBG_PHYA_ITM_WR_STIM18___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM18__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM18__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM19                    (0x00BE804C)
#define   DBG_PHYA_ITM_WR_STIM19___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM19__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM19__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM20                    (0x00BE8050)
#define   DBG_PHYA_ITM_WR_STIM20___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM20__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM20__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM21                    (0x00BE8054)
#define   DBG_PHYA_ITM_WR_STIM21___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM21__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM21__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM22                    (0x00BE8058)
#define   DBG_PHYA_ITM_WR_STIM22___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM22__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM22__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM23                    (0x00BE805C)
#define   DBG_PHYA_ITM_WR_STIM23___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM23__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM23__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM24                    (0x00BE8060)
#define   DBG_PHYA_ITM_WR_STIM24___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM24__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM24__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM25                    (0x00BE8064)
#define   DBG_PHYA_ITM_WR_STIM25___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM25__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM25__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM26                    (0x00BE8068)
#define   DBG_PHYA_ITM_WR_STIM26___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM26__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM26__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM27                    (0x00BE806C)
#define   DBG_PHYA_ITM_WR_STIM27___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM27__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM27__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM28                    (0x00BE8070)
#define   DBG_PHYA_ITM_WR_STIM28___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM28__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM28__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM29                    (0x00BE8074)
#define   DBG_PHYA_ITM_WR_STIM29___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM29__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM29__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM30                    (0x00BE8078)
#define   DBG_PHYA_ITM_WR_STIM30___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM30__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM30__STIMULUS___S                 0
#define DBG_PHYA_ITM_WR_STIM31                    (0x00BE807C)
#define   DBG_PHYA_ITM_WR_STIM31___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ITM_WR_STIM31__STIMULUS___M   0xFFFFFFFF
#define   DBG_PHYA_ITM_WR_STIM31__STIMULUS___S                 0

#define DBG_PHYA_ITM_RD_STIMn(n)         (0x00BE8000+0x4*(n))
#define   DBG_PHYA_ITM_RD_STIMn_nMIN 0    
#define   DBG_PHYA_ITM_RD_STIMn_nMAX 31   
#define   DBG_PHYA_ITM_RD_STIMn_ELEM 32   
#define   DBG_PHYA_ITM_RD_STIMn___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIMn___POR            0x00000001
#define   DBG_PHYA_ITM_RD_STIMn__FIFOREADY___POR 0x1
#define   DBG_PHYA_ITM_RD_STIMn__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIMn__FIFOREADY___S                 0
#define   DBG_PHYA_ITM_RD_STIMn__FIFOREADY__FULL             0x0
#define   DBG_PHYA_ITM_RD_STIMn__FIFOREADY__READY             0x1
#define   DBG_PHYA_ITM_RD_STIMn___M              0x00000001   
#define   DBG_PHYA_ITM_RD_STIMn___S                            0
#define DBG_PHYA_ITM_RD_STIM0                     (0x00BE8000)
#define   DBG_PHYA_ITM_RD_STIM0___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM0__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM0__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM1                     (0x00BE8004)
#define   DBG_PHYA_ITM_RD_STIM1___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM1__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM1__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM2                     (0x00BE8008)
#define   DBG_PHYA_ITM_RD_STIM2___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM2__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM2__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM3                     (0x00BE800C)
#define   DBG_PHYA_ITM_RD_STIM3___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM3__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM3__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM4                     (0x00BE8010)
#define   DBG_PHYA_ITM_RD_STIM4___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM4__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM4__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM5                     (0x00BE8014)
#define   DBG_PHYA_ITM_RD_STIM5___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM5__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM5__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM6                     (0x00BE8018)
#define   DBG_PHYA_ITM_RD_STIM6___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM6__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM6__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM7                     (0x00BE801C)
#define   DBG_PHYA_ITM_RD_STIM7___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM7__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM7__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM8                     (0x00BE8020)
#define   DBG_PHYA_ITM_RD_STIM8___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM8__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM8__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM9                     (0x00BE8024)
#define   DBG_PHYA_ITM_RD_STIM9___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM9__FIFOREADY___M   0x00000001
#define   DBG_PHYA_ITM_RD_STIM9__FIFOREADY___S                 0
#define DBG_PHYA_ITM_RD_STIM10                    (0x00BE8028)
#define   DBG_PHYA_ITM_RD_STIM10___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM10__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM10__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM11                    (0x00BE802C)
#define   DBG_PHYA_ITM_RD_STIM11___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM11__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM11__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM12                    (0x00BE8030)
#define   DBG_PHYA_ITM_RD_STIM12___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM12__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM12__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM13                    (0x00BE8034)
#define   DBG_PHYA_ITM_RD_STIM13___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM13__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM13__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM14                    (0x00BE8038)
#define   DBG_PHYA_ITM_RD_STIM14___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM14__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM14__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM15                    (0x00BE803C)
#define   DBG_PHYA_ITM_RD_STIM15___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM15__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM15__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM16                    (0x00BE8040)
#define   DBG_PHYA_ITM_RD_STIM16___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM16__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM16__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM17                    (0x00BE8044)
#define   DBG_PHYA_ITM_RD_STIM17___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM17__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM17__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM18                    (0x00BE8048)
#define   DBG_PHYA_ITM_RD_STIM18___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM18__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM18__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM19                    (0x00BE804C)
#define   DBG_PHYA_ITM_RD_STIM19___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM19__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM19__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM20                    (0x00BE8050)
#define   DBG_PHYA_ITM_RD_STIM20___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM20__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM20__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM21                    (0x00BE8054)
#define   DBG_PHYA_ITM_RD_STIM21___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM21__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM21__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM22                    (0x00BE8058)
#define   DBG_PHYA_ITM_RD_STIM22___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM22__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM22__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM23                    (0x00BE805C)
#define   DBG_PHYA_ITM_RD_STIM23___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM23__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM23__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM24                    (0x00BE8060)
#define   DBG_PHYA_ITM_RD_STIM24___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM24__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM24__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM25                    (0x00BE8064)
#define   DBG_PHYA_ITM_RD_STIM25___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM25__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM25__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM26                    (0x00BE8068)
#define   DBG_PHYA_ITM_RD_STIM26___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM26__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM26__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM27                    (0x00BE806C)
#define   DBG_PHYA_ITM_RD_STIM27___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM27__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM27__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM28                    (0x00BE8070)
#define   DBG_PHYA_ITM_RD_STIM28___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM28__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM28__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM29                    (0x00BE8074)
#define   DBG_PHYA_ITM_RD_STIM29___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM29__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM29__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM30                    (0x00BE8078)
#define   DBG_PHYA_ITM_RD_STIM30___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM30__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM30__FIFOREADY___S                0
#define DBG_PHYA_ITM_RD_STIM31                    (0x00BE807C)
#define   DBG_PHYA_ITM_RD_STIM31___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_RD_STIM31__FIFOREADY___M  0x00000001
#define   DBG_PHYA_ITM_RD_STIM31__FIFOREADY___S                0

#define DBG_PHYA_ITM_TER                          (0x00BE8E00)
#define   DBG_PHYA_ITM_TER___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_ITM_TER___POR                 0x00000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN31___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN30___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN29___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN28___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN27___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN26___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN25___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN24___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN23___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN22___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN21___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN20___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN19___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN18___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN17___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN16___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN15___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN14___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN13___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN12___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN11___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN10___POR  0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN9___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN8___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN7___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN6___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN5___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN4___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN3___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN2___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN1___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN0___POR   0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN31___M    0x80000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN31___S                 31
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN31__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN31__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN30___M    0x40000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN30___S                 30
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN30__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN30__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN29___M    0x20000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN29___S                 29
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN29__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN29__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN28___M    0x10000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN28___S                 28
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN28__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN28__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN27___M    0x08000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN27___S                 27
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN27__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN27__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN26___M    0x04000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN26___S                 26
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN26__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN26__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN25___M    0x02000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN25___S                 25
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN25__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN25__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN24___M    0x01000000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN24___S                 24
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN24__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN24__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN23___M    0x00800000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN23___S                 23
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN23__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN23__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN22___M    0x00400000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN22___S                 22
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN22__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN22__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN21___M    0x00200000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN21___S                 21
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN21__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN21__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN20___M    0x00100000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN20___S                 20
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN20__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN20__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN19___M    0x00080000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN19___S                 19
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN19__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN19__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN18___M    0x00040000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN18___S                 18
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN18__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN18__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN17___M    0x00020000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN17___S                 17
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN17__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN17__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN16___M    0x00010000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN16___S                 16
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN16__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN16__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN15___M    0x00008000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN15___S                 15
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN15__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN15__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN14___M    0x00004000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN14___S                 14
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN14__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN14__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN13___M    0x00002000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN13___S                 13
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN13__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN13__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN12___M    0x00001000
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN12___S                 12
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN12__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN12__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN11___M    0x00000800
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN11___S                 11
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN11__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN11__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN10___M    0x00000400
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN10___S                 10
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN10__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN10__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN9___M     0x00000200
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN9___S                   9
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN9__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN9__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN8___M     0x00000100
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN8___S                   8
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN8__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN8__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN7___M     0x00000080
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN7___S                   7
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN7__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN7__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN6___M     0x00000040
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN6___S                   6
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN6__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN6__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN5___M     0x00000020
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN5___S                   5
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN5__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN5__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN4___M     0x00000010
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN4___S                   4
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN4__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN4__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN3___M     0x00000008
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN3___S                   3
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN3__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN3__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN2___M     0x00000004
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN2___S                   2
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN2__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN2__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN1___M     0x00000002
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN1___S                   1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN1__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN1__ENABLE             0x1
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN0___M     0x00000001
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN0___S                   0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN0__DISABLE             0x0
#define   DBG_PHYA_ITM_TER__ITM_STIM_EN0__ENABLE             0x1
#define   DBG_PHYA_ITM_TER___M                   0xFFFFFFFF   
#define   DBG_PHYA_ITM_TER___S                                 0

#define DBG_PHYA_ITM_TPR                          (0x00BE8E40)
#define   DBG_PHYA_ITM_TPR___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_ITM_TPR___POR                 0x00000000
#define   DBG_PHYA_ITM_TPR__PRIVMASK3___POR      0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK2___POR      0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK1___POR      0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK0___POR      0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK3___M        0x00000008
#define   DBG_PHYA_ITM_TPR__PRIVMASK3___S                      3
#define   DBG_PHYA_ITM_TPR__PRIVMASK3__UNPRIVOK              0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK3__PRIVONLY              0x1
#define   DBG_PHYA_ITM_TPR__PRIVMASK2___M        0x00000004
#define   DBG_PHYA_ITM_TPR__PRIVMASK2___S                      2
#define   DBG_PHYA_ITM_TPR__PRIVMASK2__UNPRIVOK              0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK2__PRIVONLY              0x1
#define   DBG_PHYA_ITM_TPR__PRIVMASK1___M        0x00000002
#define   DBG_PHYA_ITM_TPR__PRIVMASK1___S                      1
#define   DBG_PHYA_ITM_TPR__PRIVMASK1__UNPRIVOK              0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK1__PRIVONLY              0x1
#define   DBG_PHYA_ITM_TPR__PRIVMASK0___M        0x00000001
#define   DBG_PHYA_ITM_TPR__PRIVMASK0___S                      0
#define   DBG_PHYA_ITM_TPR__PRIVMASK0__UNPRIVOK              0x0
#define   DBG_PHYA_ITM_TPR__PRIVMASK0__PRIVONLY              0x1
#define   DBG_PHYA_ITM_TPR___M                   0x0000000F   
#define   DBG_PHYA_ITM_TPR___S                                 0

#define DBG_PHYA_ITM_TCR                          (0x00BE8E80)
#define   DBG_PHYA_ITM_TCR___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_ITM_TCR___POR                 0x00000000
#define   DBG_PHYA_ITM_TCR__BUSY___POR           0x0
#define   DBG_PHYA_ITM_TCR__TRACEBUSID___POR     0x00
#define   DBG_PHYA_ITM_TCR__GTSFREQ___POR        0x0
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE___POR    0x0
#define   DBG_PHYA_ITM_TCR__SWOENA___POR         0x0
#define   DBG_PHYA_ITM_TCR__DWTTXEN___POR        0x0
#define   DBG_PHYA_ITM_TCR__SYNCENA___POR        0x0
#define   DBG_PHYA_ITM_TCR__LTSENA___POR         0x0
#define   DBG_PHYA_ITM_TCR__ITMENA___POR         0x0
#define   DBG_PHYA_ITM_TCR__BUSY___M             0x00800000
#define   DBG_PHYA_ITM_TCR__BUSY___S                          23
#define   DBG_PHYA_ITM_TCR__BUSY__IDLE                       0x0
#define   DBG_PHYA_ITM_TCR__BUSY__BUSY                       0x1
#define   DBG_PHYA_ITM_TCR__TRACEBUSID___M       0x007F0000
#define   DBG_PHYA_ITM_TCR__TRACEBUSID___S                    16
#define   DBG_PHYA_ITM_TCR__GTSFREQ___M          0x00000C00
#define   DBG_PHYA_ITM_TCR__GTSFREQ___S                       10
#define   DBG_PHYA_ITM_TCR__GTSFREQ__TSDISABLED              0x0
#define   DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERY128CYC             0x1
#define   DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERY8KCYC             0x2
#define   DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERYPKT              0x3
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE___M      0x00000300
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE___S                    8
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE__NOPRESCALE             0x0
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY4              0x1
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY16             0x2
#define   DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY64             0x3
#define   DBG_PHYA_ITM_TCR__SWOENA___M           0x00000010
#define   DBG_PHYA_ITM_TCR__SWOENA___S                         4
#define   DBG_PHYA_ITM_TCR__DWTTXEN___M          0x00000008
#define   DBG_PHYA_ITM_TCR__DWTTXEN___S                        3
#define   DBG_PHYA_ITM_TCR__DWTTXEN__DWTDISABLED             0x0
#define   DBG_PHYA_ITM_TCR__DWTTXEN__DWTENABLED              0x1
#define   DBG_PHYA_ITM_TCR__SYNCENA___M          0x00000004
#define   DBG_PHYA_ITM_TCR__SYNCENA___S                        2
#define   DBG_PHYA_ITM_TCR__SYNCENA__SYNCPKTDISABLED             0x0
#define   DBG_PHYA_ITM_TCR__SYNCENA__SYNCPKTENABLED             0x1
#define   DBG_PHYA_ITM_TCR__LTSENA___M           0x00000002
#define   DBG_PHYA_ITM_TCR__LTSENA___S                         1
#define   DBG_PHYA_ITM_TCR__LTSENA__LOCTSGENDISABLED             0x0
#define   DBG_PHYA_ITM_TCR__LTSENA__LOCTSGENENABLED             0x1
#define   DBG_PHYA_ITM_TCR__ITMENA___M           0x00000001
#define   DBG_PHYA_ITM_TCR__ITMENA___S                         0
#define   DBG_PHYA_ITM_TCR__ITMENA__ITMDISABLED              0x0
#define   DBG_PHYA_ITM_TCR__ITMENA__ITMENABLED               0x1
#define   DBG_PHYA_ITM_TCR___M                   0x00FF0F1F   
#define   DBG_PHYA_ITM_TCR___S                                 0

#define DBG_PHYA_ITM_ITATBSTAT                    (0x00BE8EF0)
#define   DBG_PHYA_ITM_ITATBSTAT___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ITM_ITATBSTAT___POR           0x00000001
#define   DBG_PHYA_ITM_ITATBSTAT__ATREADY___POR  0x1
#define   DBG_PHYA_ITM_ITATBSTAT__ATREADY___M    0x00000001
#define   DBG_PHYA_ITM_ITATBSTAT__ATREADY___S                  0
#define   DBG_PHYA_ITM_ITATBSTAT___M             0x00000001   
#define   DBG_PHYA_ITM_ITATBSTAT___S                           0

#define DBG_PHYA_ITM_ITATBDRV                     (0x00BE8EF8)
#define   DBG_PHYA_ITM_ITATBDRV___RWC               QCSR_REG_WO    
#define   DBG_PHYA_ITM_ITATBDRV___POR            0x00000000
#define   DBG_PHYA_ITM_ITATBDRV__ATVALID___POR   0x0
#define   DBG_PHYA_ITM_ITATBDRV__ATVALID___M     0x00000001
#define   DBG_PHYA_ITM_ITATBDRV__ATVALID___S                   0
#define   DBG_PHYA_ITM_ITATBDRV___M              0x00000001   
#define   DBG_PHYA_ITM_ITATBDRV___S                            0

#define DBG_PHYA_ITM_ITCTRL                       (0x00BE8F00)
#define   DBG_PHYA_ITM_ITCTRL___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_ITM_ITCTRL___POR              0x00000000
#define   DBG_PHYA_ITM_ITCTRL__ENABLE___POR      0x0
#define   DBG_PHYA_ITM_ITCTRL__ENABLE___M        0x00000001
#define   DBG_PHYA_ITM_ITCTRL__ENABLE___S                      0
#define   DBG_PHYA_ITM_ITCTRL___M                0x00000001   
#define   DBG_PHYA_ITM_ITCTRL___S                              0

#define DBG_PHYA_ITM_LAR                          (0x00BE8FB0)
#define   DBG_PHYA_ITM_LAR___RWC                    QCSR_REG_WO    
#define   DBG_PHYA_ITM_LAR___POR                 0x00000000
#define   DBG_PHYA_ITM_LAR__KEY___POR            0x00000000
#define   DBG_PHYA_ITM_LAR__KEY___M              0xFFFFFFFF
#define   DBG_PHYA_ITM_LAR__KEY___S                            0
#define   DBG_PHYA_ITM_LAR__KEY__UNLOCKKEY            0xC5ACCE55
#define   DBG_PHYA_ITM_LAR___M                   0xFFFFFFFF   
#define   DBG_PHYA_ITM_LAR___S                                 0

#define DBG_PHYA_ITM_LSR                          (0x00BE8FB4)
#define   DBG_PHYA_ITM_LSR___RWC                    QCSR_REG_RO    
#define   DBG_PHYA_ITM_LSR___POR                 0x00000003
#define   DBG_PHYA_ITM_LSR__LOCKED___POR         0x1
#define   DBG_PHYA_ITM_LSR__LOCKINGIMPL___POR    0x1
#define   DBG_PHYA_ITM_LSR__LOCKED___M           0x00000002
#define   DBG_PHYA_ITM_LSR__LOCKED___S                         1
#define   DBG_PHYA_ITM_LSR__LOCKED__ITM_UNLOCKED             0x0
#define   DBG_PHYA_ITM_LSR__LOCKED__ITM_LOCKED               0x1
#define   DBG_PHYA_ITM_LSR__LOCKINGIMPL___M      0x00000001
#define   DBG_PHYA_ITM_LSR__LOCKINGIMPL___S                    0
#define   DBG_PHYA_ITM_LSR___M                   0x00000003   
#define   DBG_PHYA_ITM_LSR___S                                 0

#define DBG_PHYA_ITM_PIDR4                        (0x00BE8FD0)
#define   DBG_PHYA_ITM_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR4___POR               0x00000004
#define   DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___POR 0x4
#define   DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___S               4
#define   DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___S               0
#define   DBG_PHYA_ITM_PIDR4___M                 0x000000FF   
#define   DBG_PHYA_ITM_PIDR4___S                               0

#define DBG_PHYA_ITM_PIDR5                        (0x00BE8FD4)
#define   DBG_PHYA_ITM_PIDR5___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR5___POR               0x00000000
#define   DBG_PHYA_ITM_PIDR5__PERIPHID5___POR    0x00000000
#define   DBG_PHYA_ITM_PIDR5__PERIPHID5___M      0xFFFFFFFF
#define   DBG_PHYA_ITM_PIDR5__PERIPHID5___S                    0
#define   DBG_PHYA_ITM_PIDR5___M                 0xFFFFFFFF   
#define   DBG_PHYA_ITM_PIDR5___S                               0

#define DBG_PHYA_ITM_PIDR6                        (0x00BE8FD8)
#define   DBG_PHYA_ITM_PIDR6___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR6___POR               0x00000000
#define   DBG_PHYA_ITM_PIDR6__PERIPHID6___POR    0x00000000
#define   DBG_PHYA_ITM_PIDR6__PERIPHID6___M      0xFFFFFFFF
#define   DBG_PHYA_ITM_PIDR6__PERIPHID6___S                    0
#define   DBG_PHYA_ITM_PIDR6___M                 0xFFFFFFFF   
#define   DBG_PHYA_ITM_PIDR6___S                               0

#define DBG_PHYA_ITM_PIDR7                        (0x00BE8FDC)
#define   DBG_PHYA_ITM_PIDR7___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR7___POR               0x00000000
#define   DBG_PHYA_ITM_PIDR7__PERIPHID7___POR    0x00000000
#define   DBG_PHYA_ITM_PIDR7__PERIPHID7___M      0xFFFFFFFF
#define   DBG_PHYA_ITM_PIDR7__PERIPHID7___S                    0
#define   DBG_PHYA_ITM_PIDR7___M                 0xFFFFFFFF   
#define   DBG_PHYA_ITM_PIDR7___S                               0

#define DBG_PHYA_ITM_PIDR0                        (0x00BE8FE0)
#define   DBG_PHYA_ITM_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR0___POR               0x00000001
#define   DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___POR  0x01
#define   DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___M    0x000000FF
#define   DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___S                  0
#define   DBG_PHYA_ITM_PIDR0___M                 0x000000FF   
#define   DBG_PHYA_ITM_PIDR0___S                               0

#define DBG_PHYA_ITM_PIDR1                        (0x00BE8FE4)
#define   DBG_PHYA_ITM_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR1___POR               0x000000B0
#define   DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___POR 0xB
#define   DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___POR 0x0
#define   DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___S               4
#define   DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___M   0x0000000F
#define   DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___S                 0
#define   DBG_PHYA_ITM_PIDR1___M                 0x000000FF   
#define   DBG_PHYA_ITM_PIDR1___S                               0

#define DBG_PHYA_ITM_PIDR2                        (0x00BE8FE8)
#define   DBG_PHYA_ITM_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR2___POR               0x0000003B
#define   DBG_PHYA_ITM_PIDR2__MAJREV___POR       0x3
#define   DBG_PHYA_ITM_PIDR2__JEDEC___POR        0x1
#define   DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___POR 0x3
#define   DBG_PHYA_ITM_PIDR2__MAJREV___M         0x000000F0
#define   DBG_PHYA_ITM_PIDR2__MAJREV___S                       4
#define   DBG_PHYA_ITM_PIDR2__JEDEC___M          0x00000008
#define   DBG_PHYA_ITM_PIDR2__JEDEC___S                        3
#define   DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___S               0
#define   DBG_PHYA_ITM_PIDR2___M                 0x000000FF   
#define   DBG_PHYA_ITM_PIDR2___S                               0

#define DBG_PHYA_ITM_PIDR3                        (0x00BE8FEC)
#define   DBG_PHYA_ITM_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_PIDR3___POR               0x00000000
#define   DBG_PHYA_ITM_PIDR3__REV_AND___POR      0x0
#define   DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_ITM_PIDR3__REV_AND___M        0x000000F0
#define   DBG_PHYA_ITM_PIDR3__REV_AND___S                      4
#define   DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_ITM_PIDR3___M                 0x000000FF   
#define   DBG_PHYA_ITM_PIDR3___S                               0

#define DBG_PHYA_ITM_CIDR0                        (0x00BE8FF0)
#define   DBG_PHYA_ITM_CIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_CIDR0___POR               0x0000000D
#define   DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___POR 0x0D
#define   DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___M   0x000000FF
#define   DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___S                 0
#define   DBG_PHYA_ITM_CIDR0___M                 0x000000FF   
#define   DBG_PHYA_ITM_CIDR0___S                               0

#define DBG_PHYA_ITM_CIDR1                        (0x00BE8FF4)
#define   DBG_PHYA_ITM_CIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_CIDR1___POR               0x000000E0
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___POR 0xE
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___POR 0x0
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___S               4
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___M  0x0000000F
#define   DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___S                0
#define   DBG_PHYA_ITM_CIDR1___M                 0x000000FF   
#define   DBG_PHYA_ITM_CIDR1___S                               0

#define DBG_PHYA_ITM_CIDR2                        (0x00BE8FF8)
#define   DBG_PHYA_ITM_CIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_CIDR2___POR               0x00000005
#define   DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___POR 0x05
#define   DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___S               0
#define   DBG_PHYA_ITM_CIDR2___M                 0x000000FF   
#define   DBG_PHYA_ITM_CIDR2___S                               0

#define DBG_PHYA_ITM_CIDR3                        (0x00BE8FFC)
#define   DBG_PHYA_ITM_CIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ITM_CIDR3___POR               0x000000B1
#define   DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___POR 0xB1
#define   DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___S               0
#define   DBG_PHYA_ITM_CIDR3___M                 0x000000FF   
#define   DBG_PHYA_ITM_CIDR3___S                               0

#define DBG_PHYA_DWT_CTRL                         (0x00BE9000)
#define   DBG_PHYA_DWT_CTRL___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_DWT_CTRL___POR                0x40000000
#define   DBG_PHYA_DWT_CTRL__NUMCOMP___POR       0x4
#define   DBG_PHYA_DWT_CTRL__NOTRCPKT___POR      0x0
#define   DBG_PHYA_DWT_CTRL__NOEXTTRIG___POR     0x0
#define   DBG_PHYA_DWT_CTRL__NOCYCCNT___POR      0x0
#define   DBG_PHYA_DWT_CTRL__NOPRFCNT___POR      0x0
#define   DBG_PHYA_DWT_CTRL__CYCEVTENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__FOLDEVTENA___POR    0x0
#define   DBG_PHYA_DWT_CTRL__LSUEVTENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__SLEEPEVTENA___POR   0x0
#define   DBG_PHYA_DWT_CTRL__EXCEVTENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__CPIEVTENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__EXCTRCENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__PCSAMPLENA___POR    0x0
#define   DBG_PHYA_DWT_CTRL__SYNCTAP___POR       0x0
#define   DBG_PHYA_DWT_CTRL__CYCTAP___POR        0x0
#define   DBG_PHYA_DWT_CTRL__POSTINIT___POR      0x0
#define   DBG_PHYA_DWT_CTRL__POSTPRESET___POR    0x0
#define   DBG_PHYA_DWT_CTRL__CYCCNTENA___POR     0x0
#define   DBG_PHYA_DWT_CTRL__NUMCOMP___M         0xF0000000
#define   DBG_PHYA_DWT_CTRL__NUMCOMP___S                      28
#define   DBG_PHYA_DWT_CTRL__NOTRCPKT___M        0x08000000
#define   DBG_PHYA_DWT_CTRL__NOTRCPKT___S                     27
#define   DBG_PHYA_DWT_CTRL__NOEXTTRIG___M       0x04000000
#define   DBG_PHYA_DWT_CTRL__NOEXTTRIG___S                    26
#define   DBG_PHYA_DWT_CTRL__NOCYCCNT___M        0x02000000
#define   DBG_PHYA_DWT_CTRL__NOCYCCNT___S                     25
#define   DBG_PHYA_DWT_CTRL__NOPRFCNT___M        0x01000000
#define   DBG_PHYA_DWT_CTRL__NOPRFCNT___S                     24
#define   DBG_PHYA_DWT_CTRL__CYCEVTENA___M       0x00400000
#define   DBG_PHYA_DWT_CTRL__CYCEVTENA___S                    22
#define   DBG_PHYA_DWT_CTRL__FOLDEVTENA___M      0x00200000
#define   DBG_PHYA_DWT_CTRL__FOLDEVTENA___S                   21
#define   DBG_PHYA_DWT_CTRL__LSUEVTENA___M       0x00100000
#define   DBG_PHYA_DWT_CTRL__LSUEVTENA___S                    20
#define   DBG_PHYA_DWT_CTRL__SLEEPEVTENA___M     0x00080000
#define   DBG_PHYA_DWT_CTRL__SLEEPEVTENA___S                  19
#define   DBG_PHYA_DWT_CTRL__EXCEVTENA___M       0x00040000
#define   DBG_PHYA_DWT_CTRL__EXCEVTENA___S                    18
#define   DBG_PHYA_DWT_CTRL__CPIEVTENA___M       0x00020000
#define   DBG_PHYA_DWT_CTRL__CPIEVTENA___S                    17
#define   DBG_PHYA_DWT_CTRL__EXCTRCENA___M       0x00010000
#define   DBG_PHYA_DWT_CTRL__EXCTRCENA___S                    16
#define   DBG_PHYA_DWT_CTRL__PCSAMPLENA___M      0x00001000
#define   DBG_PHYA_DWT_CTRL__PCSAMPLENA___S                   12
#define   DBG_PHYA_DWT_CTRL__SYNCTAP___M         0x00000C00
#define   DBG_PHYA_DWT_CTRL__SYNCTAP___S                      10
#define   DBG_PHYA_DWT_CTRL__CYCTAP___M          0x00000200
#define   DBG_PHYA_DWT_CTRL__CYCTAP___S                        9
#define   DBG_PHYA_DWT_CTRL__POSTINIT___M        0x000001E0
#define   DBG_PHYA_DWT_CTRL__POSTINIT___S                      5
#define   DBG_PHYA_DWT_CTRL__POSTPRESET___M      0x0000001E
#define   DBG_PHYA_DWT_CTRL__POSTPRESET___S                    1
#define   DBG_PHYA_DWT_CTRL__CYCCNTENA___M       0x00000001
#define   DBG_PHYA_DWT_CTRL__CYCCNTENA___S                     0
#define   DBG_PHYA_DWT_CTRL___M                  0xFF7F1FFF   
#define   DBG_PHYA_DWT_CTRL___S                                0

#define DBG_PHYA_DWT_CYCCNT                       (0x00BE9004)
#define   DBG_PHYA_DWT_CYCCNT___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_DWT_CYCCNT___POR              0x00000000
#define   DBG_PHYA_DWT_CYCCNT__CYCCNT___POR      0x00000000
#define   DBG_PHYA_DWT_CYCCNT__CYCCNT___M        0xFFFFFFFF
#define   DBG_PHYA_DWT_CYCCNT__CYCCNT___S                      0
#define   DBG_PHYA_DWT_CYCCNT___M                0xFFFFFFFF   
#define   DBG_PHYA_DWT_CYCCNT___S                              0

#define DBG_PHYA_DWT_CPICNT                       (0x00BE9008)
#define   DBG_PHYA_DWT_CPICNT___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_DWT_CPICNT___POR              0x00000000
#define   DBG_PHYA_DWT_CPICNT__CPICNT___POR      0x00
#define   DBG_PHYA_DWT_CPICNT__CPICNT___M        0x000000FF
#define   DBG_PHYA_DWT_CPICNT__CPICNT___S                      0
#define   DBG_PHYA_DWT_CPICNT___M                0x000000FF   
#define   DBG_PHYA_DWT_CPICNT___S                              0

#define DBG_PHYA_DWT_EXCCNT                       (0x00BE900C)
#define   DBG_PHYA_DWT_EXCCNT___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_DWT_EXCCNT___POR              0x00000000
#define   DBG_PHYA_DWT_EXCCNT__EXCCNT___POR      0x00
#define   DBG_PHYA_DWT_EXCCNT__EXCCNT___M        0x000000FF
#define   DBG_PHYA_DWT_EXCCNT__EXCCNT___S                      0
#define   DBG_PHYA_DWT_EXCCNT___M                0x000000FF   
#define   DBG_PHYA_DWT_EXCCNT___S                              0

#define DBG_PHYA_DWT_SLEEPCNT                     (0x00BE9010)
#define   DBG_PHYA_DWT_SLEEPCNT___RWC               QCSR_REG_RW    
#define   DBG_PHYA_DWT_SLEEPCNT___POR            0x00000000
#define   DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___POR  0x00
#define   DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___M    0x000000FF
#define   DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___S                  0
#define   DBG_PHYA_DWT_SLEEPCNT___M              0x000000FF   
#define   DBG_PHYA_DWT_SLEEPCNT___S                            0

#define DBG_PHYA_DWT_LSUCNT                       (0x00BE9014)
#define   DBG_PHYA_DWT_LSUCNT___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_DWT_LSUCNT___POR              0x00000000
#define   DBG_PHYA_DWT_LSUCNT__LSUCNT___POR      0x00
#define   DBG_PHYA_DWT_LSUCNT__LSUCNT___M        0x000000FF
#define   DBG_PHYA_DWT_LSUCNT__LSUCNT___S                      0
#define   DBG_PHYA_DWT_LSUCNT___M                0x000000FF   
#define   DBG_PHYA_DWT_LSUCNT___S                              0

#define DBG_PHYA_DWT_FOLDCNT                      (0x00BE9018)
#define   DBG_PHYA_DWT_FOLDCNT___RWC                QCSR_REG_RW    
#define   DBG_PHYA_DWT_FOLDCNT___POR             0x00000000
#define   DBG_PHYA_DWT_FOLDCNT__FOLDCNT___POR    0x00
#define   DBG_PHYA_DWT_FOLDCNT__FOLDCNT___M      0x000000FF
#define   DBG_PHYA_DWT_FOLDCNT__FOLDCNT___S                    0
#define   DBG_PHYA_DWT_FOLDCNT___M               0x000000FF   
#define   DBG_PHYA_DWT_FOLDCNT___S                             0

#define DBG_PHYA_DWT_PCSR                         (0x00BE901C)
#define   DBG_PHYA_DWT_PCSR___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_DWT_PCSR___POR                0x00000000
#define   DBG_PHYA_DWT_PCSR__EIASAMPLE___POR     0x00000000
#define   DBG_PHYA_DWT_PCSR__EIASAMPLE___M       0xFFFFFFFF
#define   DBG_PHYA_DWT_PCSR__EIASAMPLE___S                     0
#define   DBG_PHYA_DWT_PCSR___M                  0xFFFFFFFF   
#define   DBG_PHYA_DWT_PCSR___S                                0

#define DBG_PHYA_DWT_COMPn(n)            (0x00BE9020+0x10*(n))
#define   DBG_PHYA_DWT_COMPn_nMIN  0    
#define   DBG_PHYA_DWT_COMPn_nMAX  3    
#define   DBG_PHYA_DWT_COMPn_ELEM  4    
#define   DBG_PHYA_DWT_COMPn___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_COMPn___POR               0x00000000
#define   DBG_PHYA_DWT_COMPn__COMP___POR         0x00000000
#define   DBG_PHYA_DWT_COMPn__COMP___M           0xFFFFFFFF
#define   DBG_PHYA_DWT_COMPn__COMP___S                         0
#define   DBG_PHYA_DWT_COMPn___M                 0xFFFFFFFF   
#define   DBG_PHYA_DWT_COMPn___S                               0
#define DBG_PHYA_DWT_COMP0                        (0x00BE9020)
#define   DBG_PHYA_DWT_COMP0___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_COMP0__COMP___M           0xFFFFFFFF
#define   DBG_PHYA_DWT_COMP0__COMP___S                         0
#define DBG_PHYA_DWT_COMP1                        (0x00BE9030)
#define   DBG_PHYA_DWT_COMP1___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_COMP1__COMP___M           0xFFFFFFFF
#define   DBG_PHYA_DWT_COMP1__COMP___S                         0
#define DBG_PHYA_DWT_COMP2                        (0x00BE9040)
#define   DBG_PHYA_DWT_COMP2___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_COMP2__COMP___M           0xFFFFFFFF
#define   DBG_PHYA_DWT_COMP2__COMP___S                         0
#define DBG_PHYA_DWT_COMP3                        (0x00BE9050)
#define   DBG_PHYA_DWT_COMP3___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_COMP3__COMP___M           0xFFFFFFFF
#define   DBG_PHYA_DWT_COMP3__COMP___S                         0

#define DBG_PHYA_DWT_MASKn(n)            (0x00BE9024+0x10*(n))
#define   DBG_PHYA_DWT_MASKn_nMIN  0    
#define   DBG_PHYA_DWT_MASKn_nMAX  3    
#define   DBG_PHYA_DWT_MASKn_ELEM  4    
#define   DBG_PHYA_DWT_MASKn___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_MASKn___POR               0x00000000
#define   DBG_PHYA_DWT_MASKn__MASK___POR         0x00
#define   DBG_PHYA_DWT_MASKn__MASK___M           0x0000001F
#define   DBG_PHYA_DWT_MASKn__MASK___S                         0
#define   DBG_PHYA_DWT_MASKn___M                 0x0000001F   
#define   DBG_PHYA_DWT_MASKn___S                               0
#define DBG_PHYA_DWT_MASK0                        (0x00BE9024)
#define   DBG_PHYA_DWT_MASK0___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_MASK0__MASK___M           0x0000001F
#define   DBG_PHYA_DWT_MASK0__MASK___S                         0
#define DBG_PHYA_DWT_MASK1                        (0x00BE9034)
#define   DBG_PHYA_DWT_MASK1___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_MASK1__MASK___M           0x0000001F
#define   DBG_PHYA_DWT_MASK1__MASK___S                         0
#define DBG_PHYA_DWT_MASK2                        (0x00BE9044)
#define   DBG_PHYA_DWT_MASK2___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_MASK2__MASK___M           0x0000001F
#define   DBG_PHYA_DWT_MASK2__MASK___S                         0
#define DBG_PHYA_DWT_MASK3                        (0x00BE9054)
#define   DBG_PHYA_DWT_MASK3___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_DWT_MASK3__MASK___M           0x0000001F
#define   DBG_PHYA_DWT_MASK3__MASK___S                         0

#define DBG_PHYA_DWT_FUNCTIONn(n)        (0x00BE9028+0x10*(n))
#define   DBG_PHYA_DWT_FUNCTIONn_nMIN 0    
#define   DBG_PHYA_DWT_FUNCTIONn_nMAX 3    
#define   DBG_PHYA_DWT_FUNCTIONn_ELEM 4    
#define   DBG_PHYA_DWT_FUNCTIONn___RWC              QCSR_REG_RW    
#define   DBG_PHYA_DWT_FUNCTIONn___POR           0x00000000
#define   DBG_PHYA_DWT_FUNCTIONn__MATCHED___POR  0x0
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___POR  0x0
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__FUNCTION___POR 0x0
#define   DBG_PHYA_DWT_FUNCTIONn__MATCHED___M    0x01000000
#define   DBG_PHYA_DWT_FUNCTIONn__MATCHED___S                 24
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___M 0x000F0000
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___S              16
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___M 0x0000F000
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___S              12
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___M  0x00000C00
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___S               10
#define   DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___M    0x00000200
#define   DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___S                  9
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___M 0x00000100
#define   DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___S               8
#define   DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___M   0x00000080
#define   DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___S                 7
#define   DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___M  0x00000020
#define   DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___S                5
#define   DBG_PHYA_DWT_FUNCTIONn__FUNCTION___M   0x0000000F
#define   DBG_PHYA_DWT_FUNCTIONn__FUNCTION___S                 0
#define   DBG_PHYA_DWT_FUNCTIONn___M             0x010FFFAF   
#define   DBG_PHYA_DWT_FUNCTIONn___S                           0
#define DBG_PHYA_DWT_FUNCTION0                    (0x00BE9028)
#define   DBG_PHYA_DWT_FUNCTION0___RWC              QCSR_REG_RW    
#define   DBG_PHYA_DWT_FUNCTION0__MATCHED___M    0x01000000
#define   DBG_PHYA_DWT_FUNCTION0__MATCHED___S                 24
#define   DBG_PHYA_DWT_FUNCTION0__DATAVADDR1___M 0x000F0000
#define   DBG_PHYA_DWT_FUNCTION0__DATAVADDR1___S              16
#define   DBG_PHYA_DWT_FUNCTION0__DATAVADDR0___M 0x0000F000
#define   DBG_PHYA_DWT_FUNCTION0__DATAVADDR0___S              12
#define   DBG_PHYA_DWT_FUNCTION0__DATAVSIZE___M  0x00000C00
#define   DBG_PHYA_DWT_FUNCTION0__DATAVSIZE___S               10
#define   DBG_PHYA_DWT_FUNCTION0__LNK1ENA___M    0x00000200
#define   DBG_PHYA_DWT_FUNCTION0__LNK1ENA___S                  9
#define   DBG_PHYA_DWT_FUNCTION0__DATAVMATCH___M 0x00000100
#define   DBG_PHYA_DWT_FUNCTION0__DATAVMATCH___S               8
#define   DBG_PHYA_DWT_FUNCTION0__CYCMATCH___M   0x00000080
#define   DBG_PHYA_DWT_FUNCTION0__CYCMATCH___S                 7
#define   DBG_PHYA_DWT_FUNCTION0__EMITRANGE___M  0x00000020
#define   DBG_PHYA_DWT_FUNCTION0__EMITRANGE___S                5
#define   DBG_PHYA_DWT_FUNCTION0__FUNCTION___M   0x0000000F
#define   DBG_PHYA_DWT_FUNCTION0__FUNCTION___S                 0
#define DBG_PHYA_DWT_FUNCTION1                    (0x00BE9038)
#define   DBG_PHYA_DWT_FUNCTION1___RWC              QCSR_REG_RW    
#define   DBG_PHYA_DWT_FUNCTION1__MATCHED___M    0x01000000
#define   DBG_PHYA_DWT_FUNCTION1__MATCHED___S                 24
#define   DBG_PHYA_DWT_FUNCTION1__DATAVADDR1___M 0x000F0000
#define   DBG_PHYA_DWT_FUNCTION1__DATAVADDR1___S              16
#define   DBG_PHYA_DWT_FUNCTION1__DATAVADDR0___M 0x0000F000
#define   DBG_PHYA_DWT_FUNCTION1__DATAVADDR0___S              12
#define   DBG_PHYA_DWT_FUNCTION1__DATAVSIZE___M  0x00000C00
#define   DBG_PHYA_DWT_FUNCTION1__DATAVSIZE___S               10
#define   DBG_PHYA_DWT_FUNCTION1__LNK1ENA___M    0x00000200
#define   DBG_PHYA_DWT_FUNCTION1__LNK1ENA___S                  9
#define   DBG_PHYA_DWT_FUNCTION1__DATAVMATCH___M 0x00000100
#define   DBG_PHYA_DWT_FUNCTION1__DATAVMATCH___S               8
#define   DBG_PHYA_DWT_FUNCTION1__CYCMATCH___M   0x00000080
#define   DBG_PHYA_DWT_FUNCTION1__CYCMATCH___S                 7
#define   DBG_PHYA_DWT_FUNCTION1__EMITRANGE___M  0x00000020
#define   DBG_PHYA_DWT_FUNCTION1__EMITRANGE___S                5
#define   DBG_PHYA_DWT_FUNCTION1__FUNCTION___M   0x0000000F
#define   DBG_PHYA_DWT_FUNCTION1__FUNCTION___S                 0
#define DBG_PHYA_DWT_FUNCTION2                    (0x00BE9048)
#define   DBG_PHYA_DWT_FUNCTION2___RWC              QCSR_REG_RW    
#define   DBG_PHYA_DWT_FUNCTION2__MATCHED___M    0x01000000
#define   DBG_PHYA_DWT_FUNCTION2__MATCHED___S                 24
#define   DBG_PHYA_DWT_FUNCTION2__DATAVADDR1___M 0x000F0000
#define   DBG_PHYA_DWT_FUNCTION2__DATAVADDR1___S              16
#define   DBG_PHYA_DWT_FUNCTION2__DATAVADDR0___M 0x0000F000
#define   DBG_PHYA_DWT_FUNCTION2__DATAVADDR0___S              12
#define   DBG_PHYA_DWT_FUNCTION2__DATAVSIZE___M  0x00000C00
#define   DBG_PHYA_DWT_FUNCTION2__DATAVSIZE___S               10
#define   DBG_PHYA_DWT_FUNCTION2__LNK1ENA___M    0x00000200
#define   DBG_PHYA_DWT_FUNCTION2__LNK1ENA___S                  9
#define   DBG_PHYA_DWT_FUNCTION2__DATAVMATCH___M 0x00000100
#define   DBG_PHYA_DWT_FUNCTION2__DATAVMATCH___S               8
#define   DBG_PHYA_DWT_FUNCTION2__CYCMATCH___M   0x00000080
#define   DBG_PHYA_DWT_FUNCTION2__CYCMATCH___S                 7
#define   DBG_PHYA_DWT_FUNCTION2__EMITRANGE___M  0x00000020
#define   DBG_PHYA_DWT_FUNCTION2__EMITRANGE___S                5
#define   DBG_PHYA_DWT_FUNCTION2__FUNCTION___M   0x0000000F
#define   DBG_PHYA_DWT_FUNCTION2__FUNCTION___S                 0
#define DBG_PHYA_DWT_FUNCTION3                    (0x00BE9058)
#define   DBG_PHYA_DWT_FUNCTION3___RWC              QCSR_REG_RW    
#define   DBG_PHYA_DWT_FUNCTION3__MATCHED___M    0x01000000
#define   DBG_PHYA_DWT_FUNCTION3__MATCHED___S                 24
#define   DBG_PHYA_DWT_FUNCTION3__DATAVADDR1___M 0x000F0000
#define   DBG_PHYA_DWT_FUNCTION3__DATAVADDR1___S              16
#define   DBG_PHYA_DWT_FUNCTION3__DATAVADDR0___M 0x0000F000
#define   DBG_PHYA_DWT_FUNCTION3__DATAVADDR0___S              12
#define   DBG_PHYA_DWT_FUNCTION3__DATAVSIZE___M  0x00000C00
#define   DBG_PHYA_DWT_FUNCTION3__DATAVSIZE___S               10
#define   DBG_PHYA_DWT_FUNCTION3__LNK1ENA___M    0x00000200
#define   DBG_PHYA_DWT_FUNCTION3__LNK1ENA___S                  9
#define   DBG_PHYA_DWT_FUNCTION3__DATAVMATCH___M 0x00000100
#define   DBG_PHYA_DWT_FUNCTION3__DATAVMATCH___S               8
#define   DBG_PHYA_DWT_FUNCTION3__CYCMATCH___M   0x00000080
#define   DBG_PHYA_DWT_FUNCTION3__CYCMATCH___S                 7
#define   DBG_PHYA_DWT_FUNCTION3__EMITRANGE___M  0x00000020
#define   DBG_PHYA_DWT_FUNCTION3__EMITRANGE___S                5
#define   DBG_PHYA_DWT_FUNCTION3__FUNCTION___M   0x0000000F
#define   DBG_PHYA_DWT_FUNCTION3__FUNCTION___S                 0

#define DBG_PHYA_DWT_PIDR4                        (0x00BE9FD0)
#define   DBG_PHYA_DWT_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_PIDR4___POR               0x00000004
#define   DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___POR 0x4
#define   DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___S               4
#define   DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___S               0
#define   DBG_PHYA_DWT_PIDR4___M                 0x000000FF   
#define   DBG_PHYA_DWT_PIDR4___S                               0

#define DBG_PHYA_DWT_PIDR0                        (0x00BE9FE0)
#define   DBG_PHYA_DWT_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_PIDR0___POR               0x00000002
#define   DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___POR  0x02
#define   DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___M    0x000000FF
#define   DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___S                  0
#define   DBG_PHYA_DWT_PIDR0___M                 0x000000FF   
#define   DBG_PHYA_DWT_PIDR0___S                               0

#define DBG_PHYA_DWT_PIDR1                        (0x00BE9FE4)
#define   DBG_PHYA_DWT_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_PIDR1___POR               0x000000B0
#define   DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___POR 0xB
#define   DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___POR 0x0
#define   DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___S               4
#define   DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___M   0x0000000F
#define   DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___S                 0
#define   DBG_PHYA_DWT_PIDR1___M                 0x000000FF   
#define   DBG_PHYA_DWT_PIDR1___S                               0

#define DBG_PHYA_DWT_PIDR2                        (0x00BE9FE8)
#define   DBG_PHYA_DWT_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_PIDR2___POR               0x0000003B
#define   DBG_PHYA_DWT_PIDR2__MAJREV___POR       0x3
#define   DBG_PHYA_DWT_PIDR2__JEDEC___POR        0x1
#define   DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___POR 0x3
#define   DBG_PHYA_DWT_PIDR2__MAJREV___M         0x000000F0
#define   DBG_PHYA_DWT_PIDR2__MAJREV___S                       4
#define   DBG_PHYA_DWT_PIDR2__JEDEC___M          0x00000008
#define   DBG_PHYA_DWT_PIDR2__JEDEC___S                        3
#define   DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___S               0
#define   DBG_PHYA_DWT_PIDR2___M                 0x000000FF   
#define   DBG_PHYA_DWT_PIDR2___S                               0

#define DBG_PHYA_DWT_PIDR3                        (0x00BE9FEC)
#define   DBG_PHYA_DWT_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_PIDR3___POR               0x00000000
#define   DBG_PHYA_DWT_PIDR3__REV_AND___POR      0x0
#define   DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_DWT_PIDR3__REV_AND___M        0x000000F0
#define   DBG_PHYA_DWT_PIDR3__REV_AND___S                      4
#define   DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_DWT_PIDR3___M                 0x000000FF   
#define   DBG_PHYA_DWT_PIDR3___S                               0

#define DBG_PHYA_DWT_CIDR0                        (0x00BE9FF0)
#define   DBG_PHYA_DWT_CIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_CIDR0___POR               0x0000000D
#define   DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___POR 0x0D
#define   DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___M   0x000000FF
#define   DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___S                 0
#define   DBG_PHYA_DWT_CIDR0___M                 0x000000FF   
#define   DBG_PHYA_DWT_CIDR0___S                               0

#define DBG_PHYA_DWT_CIDR1                        (0x00BE9FF4)
#define   DBG_PHYA_DWT_CIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_CIDR1___POR               0x000000E0
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___POR 0xE
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___POR 0x0
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___S               4
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___M  0x0000000F
#define   DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___S                0
#define   DBG_PHYA_DWT_CIDR1___M                 0x000000FF   
#define   DBG_PHYA_DWT_CIDR1___S                               0

#define DBG_PHYA_DWT_CIDR2                        (0x00BE9FF8)
#define   DBG_PHYA_DWT_CIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_CIDR2___POR               0x00000005
#define   DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___POR 0x05
#define   DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___S               0
#define   DBG_PHYA_DWT_CIDR2___M                 0x000000FF   
#define   DBG_PHYA_DWT_CIDR2___S                               0

#define DBG_PHYA_DWT_CIDR3                        (0x00BE9FFC)
#define   DBG_PHYA_DWT_CIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_DWT_CIDR3___POR               0x000000B1
#define   DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___POR 0xB1
#define   DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___S               0
#define   DBG_PHYA_DWT_CIDR3___M                 0x000000FF   
#define   DBG_PHYA_DWT_CIDR3___S                               0

#define DBG_PHYA_FP_CTRL                          (0x00BEA000)
#define   DBG_PHYA_FP_CTRL___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_FP_CTRL___POR                 0x00000260
#define   DBG_PHYA_FP_CTRL__REV___POR            0x0
#define   DBG_PHYA_FP_CTRL__NUM_CODE_6_4___POR   0x0
#define   DBG_PHYA_FP_CTRL__NUM_LIT___POR        0x2
#define   DBG_PHYA_FP_CTRL__NUM_CODE_3_0___POR   0x6
#define   DBG_PHYA_FP_CTRL__KEY___POR            0x0
#define   DBG_PHYA_FP_CTRL__ENABLE___POR         0x0
#define   DBG_PHYA_FP_CTRL__REV___M              0xF0000000
#define   DBG_PHYA_FP_CTRL__REV___S                           28
#define   DBG_PHYA_FP_CTRL__NUM_CODE_6_4___M     0x00007000
#define   DBG_PHYA_FP_CTRL__NUM_CODE_6_4___S                  12
#define   DBG_PHYA_FP_CTRL__NUM_LIT___M          0x00000F00
#define   DBG_PHYA_FP_CTRL__NUM_LIT___S                        8
#define   DBG_PHYA_FP_CTRL__NUM_CODE_3_0___M     0x000000F0
#define   DBG_PHYA_FP_CTRL__NUM_CODE_3_0___S                   4
#define   DBG_PHYA_FP_CTRL__KEY___M              0x00000002
#define   DBG_PHYA_FP_CTRL__KEY___S                            1
#define   DBG_PHYA_FP_CTRL__ENABLE___M           0x00000001
#define   DBG_PHYA_FP_CTRL__ENABLE___S                         0
#define   DBG_PHYA_FP_CTRL___M                   0xF0007FF3   
#define   DBG_PHYA_FP_CTRL___S                                 0

#define DBG_PHYA_FP_REMAP                         (0x00BEA004)
#define   DBG_PHYA_FP_REMAP___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_REMAP__RMPSPT___M          0x20000000
#define   DBG_PHYA_FP_REMAP__RMPSPT___S                       29
#define   DBG_PHYA_FP_REMAP__RMPSPT__BKPT_ONLY               0x0
#define   DBG_PHYA_FP_REMAP__RMPSPT__REMAP_SUPPORTED             0x1
#define   DBG_PHYA_FP_REMAP__REMAP___M           0x1FFFFFE0
#define   DBG_PHYA_FP_REMAP__REMAP___S                         5
#define   DBG_PHYA_FP_REMAP___M                  0x3FFFFFE0   
#define   DBG_PHYA_FP_REMAP___S                                5

#define DBG_PHYA_FP_COMPn(n)             (0x00BEA008+0x4*(n))
#define   DBG_PHYA_FP_COMPn_nMIN   0    
#define   DBG_PHYA_FP_COMPn_nMAX   7    
#define   DBG_PHYA_FP_COMPn_ELEM   8    
#define   DBG_PHYA_FP_COMPn___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMPn___POR                0x00000000
#define   DBG_PHYA_FP_COMPn__REPLACE___POR       0x0
#define   DBG_PHYA_FP_COMPn__COMP___POR          0x0000000
#define   DBG_PHYA_FP_COMPn__ENABLE___POR        0x0
#define   DBG_PHYA_FP_COMPn__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMPn__REPLACE___S                      30
#define   DBG_PHYA_FP_COMPn__REPLACE__REPLACE                0x0
#define   DBG_PHYA_FP_COMPn__REPLACE__BKPTATZERO             0x1
#define   DBG_PHYA_FP_COMPn__REPLACE__BKPTATZEROANDTWO             0x2
#define   DBG_PHYA_FP_COMPn__REPLACE__BKPTATBOTH             0x3
#define   DBG_PHYA_FP_COMPn__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMPn__COMP___S                          2
#define   DBG_PHYA_FP_COMPn__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMPn__ENABLE___S                        0
#define   DBG_PHYA_FP_COMPn__ENABLE__COMPDISABLED             0x0
#define   DBG_PHYA_FP_COMPn__ENABLE__COMPENABLED             0x1
#define   DBG_PHYA_FP_COMPn___M                  0xDFFFFFFD   
#define   DBG_PHYA_FP_COMPn___S                                0
#define DBG_PHYA_FP_COMP0                         (0x00BEA008)
#define   DBG_PHYA_FP_COMP0___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP0__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP0__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP0__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP0__COMP___S                          2
#define   DBG_PHYA_FP_COMP0__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP0__ENABLE___S                        0
#define DBG_PHYA_FP_COMP1                         (0x00BEA00C)
#define   DBG_PHYA_FP_COMP1___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP1__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP1__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP1__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP1__COMP___S                          2
#define   DBG_PHYA_FP_COMP1__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP1__ENABLE___S                        0
#define DBG_PHYA_FP_COMP2                         (0x00BEA010)
#define   DBG_PHYA_FP_COMP2___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP2__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP2__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP2__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP2__COMP___S                          2
#define   DBG_PHYA_FP_COMP2__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP2__ENABLE___S                        0
#define DBG_PHYA_FP_COMP3                         (0x00BEA014)
#define   DBG_PHYA_FP_COMP3___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP3__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP3__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP3__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP3__COMP___S                          2
#define   DBG_PHYA_FP_COMP3__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP3__ENABLE___S                        0
#define DBG_PHYA_FP_COMP4                         (0x00BEA018)
#define   DBG_PHYA_FP_COMP4___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP4__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP4__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP4__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP4__COMP___S                          2
#define   DBG_PHYA_FP_COMP4__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP4__ENABLE___S                        0
#define DBG_PHYA_FP_COMP5                         (0x00BEA01C)
#define   DBG_PHYA_FP_COMP5___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP5__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP5__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP5__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP5__COMP___S                          2
#define   DBG_PHYA_FP_COMP5__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP5__ENABLE___S                        0
#define DBG_PHYA_FP_COMP6                         (0x00BEA020)
#define   DBG_PHYA_FP_COMP6___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP6__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP6__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP6__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP6__COMP___S                          2
#define   DBG_PHYA_FP_COMP6__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP6__ENABLE___S                        0
#define DBG_PHYA_FP_COMP7                         (0x00BEA024)
#define   DBG_PHYA_FP_COMP7___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_FP_COMP7__REPLACE___M         0xC0000000
#define   DBG_PHYA_FP_COMP7__REPLACE___S                      30
#define   DBG_PHYA_FP_COMP7__COMP___M            0x1FFFFFFC
#define   DBG_PHYA_FP_COMP7__COMP___S                          2
#define   DBG_PHYA_FP_COMP7__ENABLE___M          0x00000001
#define   DBG_PHYA_FP_COMP7__ENABLE___S                        0

#define DBG_PHYA_FP_PIDR4                         (0x00BEAFD0)
#define   DBG_PHYA_FP_PIDR4___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_PIDR4___POR                0x00000004
#define   DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___POR 0x4
#define   DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___S               4
#define   DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___S               0
#define   DBG_PHYA_FP_PIDR4___M                  0x000000FF   
#define   DBG_PHYA_FP_PIDR4___S                                0

#define DBG_PHYA_FP_PIDR0                         (0x00BEAFE0)
#define   DBG_PHYA_FP_PIDR0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_PIDR0___POR                0x00000003
#define   DBG_PHYA_FP_PIDR0__PARTNUM_7_0___POR   0x03
#define   DBG_PHYA_FP_PIDR0__PARTNUM_7_0___M     0x000000FF
#define   DBG_PHYA_FP_PIDR0__PARTNUM_7_0___S                   0
#define   DBG_PHYA_FP_PIDR0___M                  0x000000FF   
#define   DBG_PHYA_FP_PIDR0___S                                0

#define DBG_PHYA_FP_PIDR1                         (0x00BEAFE4)
#define   DBG_PHYA_FP_PIDR1___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_PIDR1___POR                0x000000B0
#define   DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___POR 0xB
#define   DBG_PHYA_FP_PIDR1__PARTNUM_11_8___POR  0x0
#define   DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___S               4
#define   DBG_PHYA_FP_PIDR1__PARTNUM_11_8___M    0x0000000F
#define   DBG_PHYA_FP_PIDR1__PARTNUM_11_8___S                  0
#define   DBG_PHYA_FP_PIDR1___M                  0x000000FF   
#define   DBG_PHYA_FP_PIDR1___S                                0

#define DBG_PHYA_FP_PIDR2                         (0x00BEAFE8)
#define   DBG_PHYA_FP_PIDR2___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_PIDR2___POR                0x0000002B
#define   DBG_PHYA_FP_PIDR2__MAJREV___POR        0x2
#define   DBG_PHYA_FP_PIDR2__JEDEC___POR         0x1
#define   DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___POR 0x3
#define   DBG_PHYA_FP_PIDR2__MAJREV___M          0x000000F0
#define   DBG_PHYA_FP_PIDR2__MAJREV___S                        4
#define   DBG_PHYA_FP_PIDR2__JEDEC___M           0x00000008
#define   DBG_PHYA_FP_PIDR2__JEDEC___S                         3
#define   DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___S               0
#define   DBG_PHYA_FP_PIDR2___M                  0x000000FF   
#define   DBG_PHYA_FP_PIDR2___S                                0

#define DBG_PHYA_FP_PIDR3                         (0x00BEAFEC)
#define   DBG_PHYA_FP_PIDR3___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_PIDR3___POR                0x00000000
#define   DBG_PHYA_FP_PIDR3__REV_AND___POR       0x0
#define   DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_FP_PIDR3__REV_AND___M         0x000000F0
#define   DBG_PHYA_FP_PIDR3__REV_AND___S                       4
#define   DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_FP_PIDR3___M                  0x000000FF   
#define   DBG_PHYA_FP_PIDR3___S                                0

#define DBG_PHYA_FP_CIDR0                         (0x00BEAFF0)
#define   DBG_PHYA_FP_CIDR0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_CIDR0___POR                0x0000000D
#define   DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___POR  0x0D
#define   DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___M    0x000000FF
#define   DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___S                  0
#define   DBG_PHYA_FP_CIDR0___M                  0x000000FF   
#define   DBG_PHYA_FP_CIDR0___S                                0

#define DBG_PHYA_FP_CIDR1                         (0x00BEAFF4)
#define   DBG_PHYA_FP_CIDR1___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_CIDR1___POR                0x000000E0
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___POR 0xE
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___POR 0x0
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___M  0x000000F0
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___S                4
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___M   0x0000000F
#define   DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___S                 0
#define   DBG_PHYA_FP_CIDR1___M                  0x000000FF   
#define   DBG_PHYA_FP_CIDR1___S                                0

#define DBG_PHYA_FP_CIDR2                         (0x00BEAFF8)
#define   DBG_PHYA_FP_CIDR2___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_CIDR2___POR                0x00000005
#define   DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___POR 0x05
#define   DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___M  0x000000FF
#define   DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___S                0
#define   DBG_PHYA_FP_CIDR2___M                  0x000000FF   
#define   DBG_PHYA_FP_CIDR2___S                                0

#define DBG_PHYA_FP_CIDR3                         (0x00BEAFFC)
#define   DBG_PHYA_FP_CIDR3___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_FP_CIDR3___POR                0x000000B1
#define   DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___POR 0xB1
#define   DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___M  0x000000FF
#define   DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___S                0
#define   DBG_PHYA_FP_CIDR3___M                  0x000000FF   
#define   DBG_PHYA_FP_CIDR3___S                                0

#define DBG_PHYA_SCS_ICTR                         (0x00BEB004)
#define   DBG_PHYA_SCS_ICTR___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_SCS_ICTR___POR                0x00000007
#define   DBG_PHYA_SCS_ICTR__INTLINESNUM___POR   0x7
#define   DBG_PHYA_SCS_ICTR__INTLINESNUM___M     0x0000000F
#define   DBG_PHYA_SCS_ICTR__INTLINESNUM___S                   0
#define   DBG_PHYA_SCS_ICTR___M                  0x0000000F   
#define   DBG_PHYA_SCS_ICTR___S                                0

#define DBG_PHYA_SCS_ACTLR                        (0x00BEB008)
#define   DBG_PHYA_SCS_ACTLR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_ACTLR___POR               0x00000000
#define   DBG_PHYA_SCS_ACTLR__DISFOLD___POR      0x0
#define   DBG_PHYA_SCS_ACTLR__DISDEFWBUF___POR   0x0
#define   DBG_PHYA_SCS_ACTLR__DISMCYCINT___POR   0x0
#define   DBG_PHYA_SCS_ACTLR__DISFOLD___M        0x00000004
#define   DBG_PHYA_SCS_ACTLR__DISFOLD___S                      2
#define   DBG_PHYA_SCS_ACTLR__DISDEFWBUF___M     0x00000002
#define   DBG_PHYA_SCS_ACTLR__DISDEFWBUF___S                   1
#define   DBG_PHYA_SCS_ACTLR__DISMCYCINT___M     0x00000001
#define   DBG_PHYA_SCS_ACTLR__DISMCYCINT___S                   0
#define   DBG_PHYA_SCS_ACTLR___M                 0x00000007   
#define   DBG_PHYA_SCS_ACTLR___S                               0

#define DBG_PHYA_SCS_STCSR                        (0x00BEB010)
#define   DBG_PHYA_SCS_STCSR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_STCSR___POR               0x00000004
#define   DBG_PHYA_SCS_STCSR__COUNTFLAG___POR    0x0
#define   DBG_PHYA_SCS_STCSR__CLKSOURCE___POR    0x1
#define   DBG_PHYA_SCS_STCSR__TICKINT___POR      0x0
#define   DBG_PHYA_SCS_STCSR__ENABLE___POR       0x0
#define   DBG_PHYA_SCS_STCSR__COUNTFLAG___M      0x00010000
#define   DBG_PHYA_SCS_STCSR__COUNTFLAG___S                   16
#define   DBG_PHYA_SCS_STCSR__CLKSOURCE___M      0x00000004
#define   DBG_PHYA_SCS_STCSR__CLKSOURCE___S                    2
#define   DBG_PHYA_SCS_STCSR__CLKSOURCE__EXTERNAL             0x0
#define   DBG_PHYA_SCS_STCSR__CLKSOURCE__CPU_CLK             0x1
#define   DBG_PHYA_SCS_STCSR__TICKINT___M        0x00000002
#define   DBG_PHYA_SCS_STCSR__TICKINT___S                      1
#define   DBG_PHYA_SCS_STCSR__ENABLE___M         0x00000001
#define   DBG_PHYA_SCS_STCSR__ENABLE___S                       0
#define   DBG_PHYA_SCS_STCSR___M                 0x00010007   
#define   DBG_PHYA_SCS_STCSR___S                               0

#define DBG_PHYA_SCS_STRVR                        (0x00BEB014)
#define   DBG_PHYA_SCS_STRVR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_STRVR___POR               0x00000000
#define   DBG_PHYA_SCS_STRVR__RELOAD___POR       0x000000
#define   DBG_PHYA_SCS_STRVR__RELOAD___M         0x00FFFFFF
#define   DBG_PHYA_SCS_STRVR__RELOAD___S                       0
#define   DBG_PHYA_SCS_STRVR___M                 0x00FFFFFF   
#define   DBG_PHYA_SCS_STRVR___S                               0

#define DBG_PHYA_SCS_STCVR                        (0x00BEB018)
#define   DBG_PHYA_SCS_STCVR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_STCVR___POR               0x00000000
#define   DBG_PHYA_SCS_STCVR__CURRENT___POR      0x000000
#define   DBG_PHYA_SCS_STCVR__CURRENT___M        0x00FFFFFF
#define   DBG_PHYA_SCS_STCVR__CURRENT___S                      0
#define   DBG_PHYA_SCS_STCVR___M                 0x00FFFFFF   
#define   DBG_PHYA_SCS_STCVR___S                               0

#define DBG_PHYA_SCS_STCR                         (0x00BEB01C)
#define   DBG_PHYA_SCS_STCR___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_SCS_STCR___POR                0x80000000
#define   DBG_PHYA_SCS_STCR__NOREF___POR         0x1
#define   DBG_PHYA_SCS_STCR__SKEW___POR          0x0
#define   DBG_PHYA_SCS_STCR__TENMS___POR         0x000000
#define   DBG_PHYA_SCS_STCR__NOREF___M           0x80000000
#define   DBG_PHYA_SCS_STCR__NOREF___S                        31
#define   DBG_PHYA_SCS_STCR__NOREF__REFCLKNOTIMPLEMENTED             0x1
#define   DBG_PHYA_SCS_STCR__SKEW___M            0x40000000
#define   DBG_PHYA_SCS_STCR__SKEW___S                         30
#define   DBG_PHYA_SCS_STCR__SKEW__CALVALUEEXACT             0x0
#define   DBG_PHYA_SCS_STCR__TENMS___M           0x00FFFFFF
#define   DBG_PHYA_SCS_STCR__TENMS___S                         0
#define   DBG_PHYA_SCS_STCR___M                  0xC0FFFFFF   
#define   DBG_PHYA_SCS_STCR___S                                0

#define DBG_PHYA_SCS_CPUID                        (0x00BEBD00)
#define   DBG_PHYA_SCS_CPUID___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_CPUID___POR               0x412FC231
#define   DBG_PHYA_SCS_CPUID__IMPLEMENTER___POR  0x41
#define   DBG_PHYA_SCS_CPUID__VARIANT___POR      0x2
#define   DBG_PHYA_SCS_CPUID__CONSTANT___POR     0xF
#define   DBG_PHYA_SCS_CPUID__PARTNO___POR       0xC23
#define   DBG_PHYA_SCS_CPUID__REVISION___POR     0x1
#define   DBG_PHYA_SCS_CPUID__IMPLEMENTER___M    0xFF000000
#define   DBG_PHYA_SCS_CPUID__IMPLEMENTER___S                 24
#define   DBG_PHYA_SCS_CPUID__IMPLEMENTER__ARM              0x41
#define   DBG_PHYA_SCS_CPUID__VARIANT___M        0x00F00000
#define   DBG_PHYA_SCS_CPUID__VARIANT___S                     20
#define   DBG_PHYA_SCS_CPUID__CONSTANT___M       0x000F0000
#define   DBG_PHYA_SCS_CPUID__CONSTANT___S                    16
#define   DBG_PHYA_SCS_CPUID__PARTNO___M         0x0000FFF0
#define   DBG_PHYA_SCS_CPUID__PARTNO___S                       4
#define   DBG_PHYA_SCS_CPUID__PARTNO__CORTEXM3             0xC23
#define   DBG_PHYA_SCS_CPUID__REVISION___M       0x0000000F
#define   DBG_PHYA_SCS_CPUID__REVISION___S                     0
#define   DBG_PHYA_SCS_CPUID___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_CPUID___S                               0

#define DBG_PHYA_SCS_ICSR                         (0x00BEBD04)
#define   DBG_PHYA_SCS_ICSR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_ICSR___POR                0x00000000
#define   DBG_PHYA_SCS_ICSR__NMIPENDSET___POR    0x0
#define   DBG_PHYA_SCS_ICSR__PENDSVSET___POR     0x0
#define   DBG_PHYA_SCS_ICSR__PENDSVCLR___POR     0x0
#define   DBG_PHYA_SCS_ICSR__PENDSTSET___POR     0x0
#define   DBG_PHYA_SCS_ICSR__PENDSTCLR___POR     0x0
#define   DBG_PHYA_SCS_ICSR__ISRPREEMPT___POR    0x0
#define   DBG_PHYA_SCS_ICSR__ISRPENDING___POR    0x0
#define   DBG_PHYA_SCS_ICSR__VECTPENDING___POR   0x000
#define   DBG_PHYA_SCS_ICSR__RETTOBASE___POR     0x0
#define   DBG_PHYA_SCS_ICSR__VECTACTIVE___POR    0x000
#define   DBG_PHYA_SCS_ICSR__NMIPENDSET___M      0x80000000
#define   DBG_PHYA_SCS_ICSR__NMIPENDSET___S                   31
#define   DBG_PHYA_SCS_ICSR__PENDSVSET___M       0x10000000
#define   DBG_PHYA_SCS_ICSR__PENDSVSET___S                    28
#define   DBG_PHYA_SCS_ICSR__PENDSVCLR___M       0x08000000
#define   DBG_PHYA_SCS_ICSR__PENDSVCLR___S                    27
#define   DBG_PHYA_SCS_ICSR__PENDSTSET___M       0x04000000
#define   DBG_PHYA_SCS_ICSR__PENDSTSET___S                    26
#define   DBG_PHYA_SCS_ICSR__PENDSTCLR___M       0x02000000
#define   DBG_PHYA_SCS_ICSR__PENDSTCLR___S                    25
#define   DBG_PHYA_SCS_ICSR__ISRPREEMPT___M      0x00800000
#define   DBG_PHYA_SCS_ICSR__ISRPREEMPT___S                   23
#define   DBG_PHYA_SCS_ICSR__ISRPENDING___M      0x00400000
#define   DBG_PHYA_SCS_ICSR__ISRPENDING___S                   22
#define   DBG_PHYA_SCS_ICSR__VECTPENDING___M     0x001FF000
#define   DBG_PHYA_SCS_ICSR__VECTPENDING___S                  12
#define   DBG_PHYA_SCS_ICSR__RETTOBASE___M       0x00000800
#define   DBG_PHYA_SCS_ICSR__RETTOBASE___S                    11
#define   DBG_PHYA_SCS_ICSR__VECTACTIVE___M      0x000001FF
#define   DBG_PHYA_SCS_ICSR__VECTACTIVE___S                    0
#define   DBG_PHYA_SCS_ICSR___M                  0x9EDFF9FF   
#define   DBG_PHYA_SCS_ICSR___S                                0

#define DBG_PHYA_SCS_VTOR                         (0x00BEBD08)
#define   DBG_PHYA_SCS_VTOR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_VTOR___POR                0x00000000
#define   DBG_PHYA_SCS_VTOR__TBLOFF___POR        0x0000000
#define   DBG_PHYA_SCS_VTOR__TBLOFF___M          0xFFFFFF80
#define   DBG_PHYA_SCS_VTOR__TBLOFF___S                        7
#define   DBG_PHYA_SCS_VTOR___M                  0xFFFFFF80   
#define   DBG_PHYA_SCS_VTOR___S                                7

#define DBG_PHYA_SCS_AIRCR                        (0x00BEBD0C)
#define   DBG_PHYA_SCS_AIRCR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_AIRCR___POR               0xFA050000
#define   DBG_PHYA_SCS_AIRCR__VECTKEY___POR      0xFA05
#define   DBG_PHYA_SCS_AIRCR__ENDIANESS___POR    0x0
#define   DBG_PHYA_SCS_AIRCR__PRIGROUP___POR     0x0
#define   DBG_PHYA_SCS_AIRCR__SYSRESETREQ___POR  0x0
#define   DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___POR 0x0
#define   DBG_PHYA_SCS_AIRCR__VECTRESET___POR    0x0
#define   DBG_PHYA_SCS_AIRCR__VECTKEY___M        0xFFFF0000
#define   DBG_PHYA_SCS_AIRCR__VECTKEY___S                     16
#define   DBG_PHYA_SCS_AIRCR__ENDIANESS___M      0x00008000
#define   DBG_PHYA_SCS_AIRCR__ENDIANESS___S                   15
#define   DBG_PHYA_SCS_AIRCR__ENDIANESS__LITTLE_ENDIAN             0x0
#define   DBG_PHYA_SCS_AIRCR__PRIGROUP___M       0x00000700
#define   DBG_PHYA_SCS_AIRCR__PRIGROUP___S                     8
#define   DBG_PHYA_SCS_AIRCR__SYSRESETREQ___M    0x00000004
#define   DBG_PHYA_SCS_AIRCR__SYSRESETREQ___S                  2
#define   DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___M  0x00000002
#define   DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___S                1
#define   DBG_PHYA_SCS_AIRCR__VECTRESET___M      0x00000001
#define   DBG_PHYA_SCS_AIRCR__VECTRESET___S                    0
#define   DBG_PHYA_SCS_AIRCR___M                 0xFFFF8707   
#define   DBG_PHYA_SCS_AIRCR___S                               0

#define DBG_PHYA_SCS_SCR                          (0x00BEBD10)
#define   DBG_PHYA_SCS_SCR___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_SCS_SCR___POR                 0x00000000
#define   DBG_PHYA_SCS_SCR__SEVONPEND___POR      0x0
#define   DBG_PHYA_SCS_SCR__SLEEPDEEP___POR      0x0
#define   DBG_PHYA_SCS_SCR__SLEEPONEXIT___POR    0x0
#define   DBG_PHYA_SCS_SCR__SEVONPEND___M        0x00000010
#define   DBG_PHYA_SCS_SCR__SEVONPEND___S                      4
#define   DBG_PHYA_SCS_SCR__SLEEPDEEP___M        0x00000004
#define   DBG_PHYA_SCS_SCR__SLEEPDEEP___S                      2
#define   DBG_PHYA_SCS_SCR__SLEEPONEXIT___M      0x00000002
#define   DBG_PHYA_SCS_SCR__SLEEPONEXIT___S                    1
#define   DBG_PHYA_SCS_SCR___M                   0x00000016   
#define   DBG_PHYA_SCS_SCR___S                                 1

#define DBG_PHYA_SCS_CCR                          (0x00BEBD14)
#define   DBG_PHYA_SCS_CCR___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_SCS_CCR___POR                 0x00000200
#define   DBG_PHYA_SCS_CCR__BP___POR             0x0
#define   DBG_PHYA_SCS_CCR__IC___POR             0x0
#define   DBG_PHYA_SCS_CCR__DC___POR             0x0
#define   DBG_PHYA_SCS_CCR__STKALIGN___POR       0x1
#define   DBG_PHYA_SCS_CCR__BFHFNMIGN___POR      0x0
#define   DBG_PHYA_SCS_CCR__DIV_0_TRP___POR      0x0
#define   DBG_PHYA_SCS_CCR__UNALIGN_TRP___POR    0x0
#define   DBG_PHYA_SCS_CCR__USERSETMPEND___POR   0x0
#define   DBG_PHYA_SCS_CCR__NONBASETHRDENA___POR 0x0
#define   DBG_PHYA_SCS_CCR__BP___M               0x00040000
#define   DBG_PHYA_SCS_CCR__BP___S                            18
#define   DBG_PHYA_SCS_CCR__IC___M               0x00020000
#define   DBG_PHYA_SCS_CCR__IC___S                            17
#define   DBG_PHYA_SCS_CCR__DC___M               0x00010000
#define   DBG_PHYA_SCS_CCR__DC___S                            16
#define   DBG_PHYA_SCS_CCR__STKALIGN___M         0x00000200
#define   DBG_PHYA_SCS_CCR__STKALIGN___S                       9
#define   DBG_PHYA_SCS_CCR__BFHFNMIGN___M        0x00000100
#define   DBG_PHYA_SCS_CCR__BFHFNMIGN___S                      8
#define   DBG_PHYA_SCS_CCR__DIV_0_TRP___M        0x00000010
#define   DBG_PHYA_SCS_CCR__DIV_0_TRP___S                      4
#define   DBG_PHYA_SCS_CCR__UNALIGN_TRP___M      0x00000008
#define   DBG_PHYA_SCS_CCR__UNALIGN_TRP___S                    3
#define   DBG_PHYA_SCS_CCR__USERSETMPEND___M     0x00000002
#define   DBG_PHYA_SCS_CCR__USERSETMPEND___S                   1
#define   DBG_PHYA_SCS_CCR__NONBASETHRDENA___M   0x00000001
#define   DBG_PHYA_SCS_CCR__NONBASETHRDENA___S                 0
#define   DBG_PHYA_SCS_CCR___M                   0x0007031B   
#define   DBG_PHYA_SCS_CCR___S                                 0

#define DBG_PHYA_SCS_SHPR1                        (0x00BEBD18)
#define   DBG_PHYA_SCS_SHPR1___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_SHPR1___POR               0x00000000
#define   DBG_PHYA_SCS_SHPR1__PRI_7___POR        0x00
#define   DBG_PHYA_SCS_SHPR1__PRI_6___POR        0x00
#define   DBG_PHYA_SCS_SHPR1__PRI_5___POR        0x00
#define   DBG_PHYA_SCS_SHPR1__PRI_4___POR        0x00
#define   DBG_PHYA_SCS_SHPR1__PRI_7___M          0xFF000000
#define   DBG_PHYA_SCS_SHPR1__PRI_7___S                       24
#define   DBG_PHYA_SCS_SHPR1__PRI_6___M          0x00FF0000
#define   DBG_PHYA_SCS_SHPR1__PRI_6___S                       16
#define   DBG_PHYA_SCS_SHPR1__PRI_5___M          0x0000FF00
#define   DBG_PHYA_SCS_SHPR1__PRI_5___S                        8
#define   DBG_PHYA_SCS_SHPR1__PRI_4___M          0x000000FF
#define   DBG_PHYA_SCS_SHPR1__PRI_4___S                        0
#define   DBG_PHYA_SCS_SHPR1___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_SHPR1___S                               0

#define DBG_PHYA_SCS_SHPR2                        (0x00BEBD1C)
#define   DBG_PHYA_SCS_SHPR2___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_SHPR2___POR               0x00000000
#define   DBG_PHYA_SCS_SHPR2__PRI_11___POR       0x00
#define   DBG_PHYA_SCS_SHPR2__PRI_10___POR       0x00
#define   DBG_PHYA_SCS_SHPR2__PRI_9___POR        0x00
#define   DBG_PHYA_SCS_SHPR2__PRI_8___POR        0x00
#define   DBG_PHYA_SCS_SHPR2__PRI_11___M         0xFF000000
#define   DBG_PHYA_SCS_SHPR2__PRI_11___S                      24
#define   DBG_PHYA_SCS_SHPR2__PRI_10___M         0x00FF0000
#define   DBG_PHYA_SCS_SHPR2__PRI_10___S                      16
#define   DBG_PHYA_SCS_SHPR2__PRI_9___M          0x0000FF00
#define   DBG_PHYA_SCS_SHPR2__PRI_9___S                        8
#define   DBG_PHYA_SCS_SHPR2__PRI_8___M          0x000000FF
#define   DBG_PHYA_SCS_SHPR2__PRI_8___S                        0
#define   DBG_PHYA_SCS_SHPR2___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_SHPR2___S                               0

#define DBG_PHYA_SCS_SHPR3                        (0x00BEBD20)
#define   DBG_PHYA_SCS_SHPR3___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_SHPR3___POR               0x00000000
#define   DBG_PHYA_SCS_SHPR3__PRI_15___POR       0x00
#define   DBG_PHYA_SCS_SHPR3__PRI_14___POR       0x00
#define   DBG_PHYA_SCS_SHPR3__PRI_13___POR       0x00
#define   DBG_PHYA_SCS_SHPR3__PRI_12___POR       0x00
#define   DBG_PHYA_SCS_SHPR3__PRI_15___M         0xFF000000
#define   DBG_PHYA_SCS_SHPR3__PRI_15___S                      24
#define   DBG_PHYA_SCS_SHPR3__PRI_14___M         0x00FF0000
#define   DBG_PHYA_SCS_SHPR3__PRI_14___S                      16
#define   DBG_PHYA_SCS_SHPR3__PRI_13___M         0x0000FF00
#define   DBG_PHYA_SCS_SHPR3__PRI_13___S                       8
#define   DBG_PHYA_SCS_SHPR3__PRI_12___M         0x000000FF
#define   DBG_PHYA_SCS_SHPR3__PRI_12___S                       0
#define   DBG_PHYA_SCS_SHPR3___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_SHPR3___S                               0

#define DBG_PHYA_SCS_SHCR                         (0x00BEBD24)
#define   DBG_PHYA_SCS_SHCR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_SHCR___POR                0x00000000
#define   DBG_PHYA_SCS_SHCR__USGFAULTENA___POR   0x0
#define   DBG_PHYA_SCS_SHCR__BUSFAULTENA___POR   0x0
#define   DBG_PHYA_SCS_SHCR__MEMFAULTENA___POR   0x0
#define   DBG_PHYA_SCS_SHCR__SVCALLPENDED___POR  0x0
#define   DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___POR 0x0
#define   DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___POR 0x0
#define   DBG_PHYA_SCS_SHCR__USGFAULTPENDED___POR 0x0
#define   DBG_PHYA_SCS_SHCR__SYSTICKACT___POR    0x0
#define   DBG_PHYA_SCS_SHCR__PENDSVACT___POR     0x0
#define   DBG_PHYA_SCS_SHCR__MONITORACT___POR    0x0
#define   DBG_PHYA_SCS_SHCR__SVCALLACT___POR     0x0
#define   DBG_PHYA_SCS_SHCR__USGFAULTACT___POR   0x0
#define   DBG_PHYA_SCS_SHCR__BUSFAULTACT___POR   0x0
#define   DBG_PHYA_SCS_SHCR__MEMFAULTACT___POR   0x0
#define   DBG_PHYA_SCS_SHCR__USGFAULTENA___M     0x00040000
#define   DBG_PHYA_SCS_SHCR__USGFAULTENA___S                  18
#define   DBG_PHYA_SCS_SHCR__BUSFAULTENA___M     0x00020000
#define   DBG_PHYA_SCS_SHCR__BUSFAULTENA___S                  17
#define   DBG_PHYA_SCS_SHCR__MEMFAULTENA___M     0x00010000
#define   DBG_PHYA_SCS_SHCR__MEMFAULTENA___S                  16
#define   DBG_PHYA_SCS_SHCR__SVCALLPENDED___M    0x00008000
#define   DBG_PHYA_SCS_SHCR__SVCALLPENDED___S                 15
#define   DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___M  0x00004000
#define   DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___S               14
#define   DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___M  0x00002000
#define   DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___S               13
#define   DBG_PHYA_SCS_SHCR__USGFAULTPENDED___M  0x00001000
#define   DBG_PHYA_SCS_SHCR__USGFAULTPENDED___S               12
#define   DBG_PHYA_SCS_SHCR__SYSTICKACT___M      0x00000800
#define   DBG_PHYA_SCS_SHCR__SYSTICKACT___S                   11
#define   DBG_PHYA_SCS_SHCR__PENDSVACT___M       0x00000400
#define   DBG_PHYA_SCS_SHCR__PENDSVACT___S                    10
#define   DBG_PHYA_SCS_SHCR__MONITORACT___M      0x00000200
#define   DBG_PHYA_SCS_SHCR__MONITORACT___S                    9
#define   DBG_PHYA_SCS_SHCR__SVCALLACT___M       0x00000080
#define   DBG_PHYA_SCS_SHCR__SVCALLACT___S                     7
#define   DBG_PHYA_SCS_SHCR__USGFAULTACT___M     0x00000008
#define   DBG_PHYA_SCS_SHCR__USGFAULTACT___S                   3
#define   DBG_PHYA_SCS_SHCR__BUSFAULTACT___M     0x00000002
#define   DBG_PHYA_SCS_SHCR__BUSFAULTACT___S                   1
#define   DBG_PHYA_SCS_SHCR__MEMFAULTACT___M     0x00000001
#define   DBG_PHYA_SCS_SHCR__MEMFAULTACT___S                   0
#define   DBG_PHYA_SCS_SHCR___M                  0x0007FE8B   
#define   DBG_PHYA_SCS_SHCR___S                                0

#define DBG_PHYA_SCS_CFSR                         (0x00BEBD28)
#define   DBG_PHYA_SCS_CFSR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_CFSR___POR                0x00000000
#define   DBG_PHYA_SCS_CFSR__USAGEFAULT___POR    0x0000
#define   DBG_PHYA_SCS_CFSR__BUSFAULT___POR      0x00
#define   DBG_PHYA_SCS_CFSR__MEMMANAGE___POR     0x00
#define   DBG_PHYA_SCS_CFSR__USAGEFAULT___M      0xFFFF0000
#define   DBG_PHYA_SCS_CFSR__USAGEFAULT___S                   16
#define   DBG_PHYA_SCS_CFSR__BUSFAULT___M        0x0000FF00
#define   DBG_PHYA_SCS_CFSR__BUSFAULT___S                      8
#define   DBG_PHYA_SCS_CFSR__MEMMANAGE___M       0x000000FF
#define   DBG_PHYA_SCS_CFSR__MEMMANAGE___S                     0
#define   DBG_PHYA_SCS_CFSR___M                  0xFFFFFFFF   
#define   DBG_PHYA_SCS_CFSR___S                                0

#define DBG_PHYA_SCS_HFSR                         (0x00BEBD2C)
#define   DBG_PHYA_SCS_HFSR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_HFSR___POR                0x00000000
#define   DBG_PHYA_SCS_HFSR__DEBUGEVT___POR      0x0
#define   DBG_PHYA_SCS_HFSR__FORCED___POR        0x0
#define   DBG_PHYA_SCS_HFSR__VECTTBL___POR       0x0
#define   DBG_PHYA_SCS_HFSR__DEBUGEVT___M        0x80000000
#define   DBG_PHYA_SCS_HFSR__DEBUGEVT___S                     31
#define   DBG_PHYA_SCS_HFSR__FORCED___M          0x40000000
#define   DBG_PHYA_SCS_HFSR__FORCED___S                       30
#define   DBG_PHYA_SCS_HFSR__VECTTBL___M         0x00000002
#define   DBG_PHYA_SCS_HFSR__VECTTBL___S                       1
#define   DBG_PHYA_SCS_HFSR___M                  0xC0000002   
#define   DBG_PHYA_SCS_HFSR___S                                1

#define DBG_PHYA_SCS_DFSR                         (0x00BEBD30)
#define   DBG_PHYA_SCS_DFSR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_DFSR___POR                0x00000000
#define   DBG_PHYA_SCS_DFSR__EXTERNAL___POR      0x0
#define   DBG_PHYA_SCS_DFSR__VCATCH___POR        0x0
#define   DBG_PHYA_SCS_DFSR__DWTTRAP___POR       0x0
#define   DBG_PHYA_SCS_DFSR__BKPT___POR          0x0
#define   DBG_PHYA_SCS_DFSR__HALTED___POR        0x0
#define   DBG_PHYA_SCS_DFSR__EXTERNAL___M        0x00000010
#define   DBG_PHYA_SCS_DFSR__EXTERNAL___S                      4
#define   DBG_PHYA_SCS_DFSR__VCATCH___M          0x00000008
#define   DBG_PHYA_SCS_DFSR__VCATCH___S                        3
#define   DBG_PHYA_SCS_DFSR__DWTTRAP___M         0x00000004
#define   DBG_PHYA_SCS_DFSR__DWTTRAP___S                       2
#define   DBG_PHYA_SCS_DFSR__BKPT___M            0x00000002
#define   DBG_PHYA_SCS_DFSR__BKPT___S                          1
#define   DBG_PHYA_SCS_DFSR__HALTED___M          0x00000001
#define   DBG_PHYA_SCS_DFSR__HALTED___S                        0
#define   DBG_PHYA_SCS_DFSR___M                  0x0000001F   
#define   DBG_PHYA_SCS_DFSR___S                                0

#define DBG_PHYA_SCS_MMFAR                        (0x00BEBD34)
#define   DBG_PHYA_SCS_MMFAR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_MMFAR___POR               0x00000000
#define   DBG_PHYA_SCS_MMFAR__ADDRESS___POR      0x00000000
#define   DBG_PHYA_SCS_MMFAR__ADDRESS___M        0xFFFFFFFF
#define   DBG_PHYA_SCS_MMFAR__ADDRESS___S                      0
#define   DBG_PHYA_SCS_MMFAR___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_MMFAR___S                               0

#define DBG_PHYA_SCS_BFAR                         (0x00BEBD38)
#define   DBG_PHYA_SCS_BFAR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_BFAR___POR                0x00000000
#define   DBG_PHYA_SCS_BFAR__ADDRESS___POR       0x00000000
#define   DBG_PHYA_SCS_BFAR__ADDRESS___M         0xFFFFFFFF
#define   DBG_PHYA_SCS_BFAR__ADDRESS___S                       0
#define   DBG_PHYA_SCS_BFAR___M                  0xFFFFFFFF   
#define   DBG_PHYA_SCS_BFAR___S                                0

#define DBG_PHYA_SCS_AFSR                         (0x00BEBD3C)
#define   DBG_PHYA_SCS_AFSR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_SCS_AFSR___POR                0x00000000
#define   DBG_PHYA_SCS_AFSR__AUXFAULT___POR      0x00000000
#define   DBG_PHYA_SCS_AFSR__AUXFAULT___M        0xFFFFFFFF
#define   DBG_PHYA_SCS_AFSR__AUXFAULT___S                      0
#define   DBG_PHYA_SCS_AFSR___M                  0xFFFFFFFF   
#define   DBG_PHYA_SCS_AFSR___S                                0

#define DBG_PHYA_SCS_ID_PFR0                      (0x00BEBD40)
#define   DBG_PHYA_SCS_ID_PFR0___RWC                QCSR_REG_RO    
#define   DBG_PHYA_SCS_ID_PFR0___POR             0x00000030
#define   DBG_PHYA_SCS_ID_PFR0__STATE1___POR     0x3
#define   DBG_PHYA_SCS_ID_PFR0__STATE0___POR     0x0
#define   DBG_PHYA_SCS_ID_PFR0__STATE1___M       0x000000F0
#define   DBG_PHYA_SCS_ID_PFR0__STATE1___S                     4
#define   DBG_PHYA_SCS_ID_PFR0__STATE1__THUMBSUPPORTED             0x3
#define   DBG_PHYA_SCS_ID_PFR0__STATE0___M       0x0000000F
#define   DBG_PHYA_SCS_ID_PFR0__STATE0___S                     0
#define   DBG_PHYA_SCS_ID_PFR0__STATE0__ARMINSTCTNSETNOTSUPPORTED             0x0
#define   DBG_PHYA_SCS_ID_PFR0___M               0x000000FF   
#define   DBG_PHYA_SCS_ID_PFR0___S                             0

#define DBG_PHYA_SCS_ID_PFR1                      (0x00BEBD44)
#define   DBG_PHYA_SCS_ID_PFR1___RWC                QCSR_REG_RO    
#define   DBG_PHYA_SCS_ID_PFR1___POR             0x00000200
#define   DBG_PHYA_SCS_ID_PFR1__MPROFILE___POR   0x2
#define   DBG_PHYA_SCS_ID_PFR1__MPROFILE___M     0x00000F00
#define   DBG_PHYA_SCS_ID_PFR1__MPROFILE___S                   8
#define   DBG_PHYA_SCS_ID_PFR1__MPROFILE__TWOSTACKSUPPORTED             0x2
#define   DBG_PHYA_SCS_ID_PFR1___M               0x00000F00   
#define   DBG_PHYA_SCS_ID_PFR1___S                             8

#define DBG_PHYA_SCS_ID_DFR0                      (0x00BEBD48)
#define   DBG_PHYA_SCS_ID_DFR0___RWC                QCSR_REG_RO    
#define   DBG_PHYA_SCS_ID_DFR0___POR             0x00100000
#define   DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___POR 0x1
#define   DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___M 0x00F00000
#define   DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___S              20
#define   DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE__DEBUGSUPPORTED             0x1
#define   DBG_PHYA_SCS_ID_DFR0___M               0x00F00000   
#define   DBG_PHYA_SCS_ID_DFR0___S                            20

#define DBG_PHYA_SCS_AFR0                         (0x00BEBD4C)
#define   DBG_PHYA_SCS_AFR0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_SCS_AFR0___POR                0x00000000
#define   DBG_PHYA_SCS_AFR0__VALUE___POR         0x00000000
#define   DBG_PHYA_SCS_AFR0__VALUE___M           0xFFFFFFFF
#define   DBG_PHYA_SCS_AFR0__VALUE___S                         0
#define   DBG_PHYA_SCS_AFR0___M                  0xFFFFFFFF   
#define   DBG_PHYA_SCS_AFR0___S                                0

#define DBG_PHYA_SCS_MMFR0                        (0x00BEBD50)
#define   DBG_PHYA_SCS_MMFR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_MMFR0___POR               0x00100030
#define   DBG_PHYA_SCS_MMFR0__AUXREGS___POR      0x1
#define   DBG_PHYA_SCS_MMFR0__TCMSUPPORT___POR   0x0
#define   DBG_PHYA_SCS_MMFR0__SHAREABILITY___POR 0x0
#define   DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___POR 0x0
#define   DBG_PHYA_SCS_MMFR0__PMSA___POR         0x3
#define   DBG_PHYA_SCS_MMFR0__AUXREGS___M        0x00F00000
#define   DBG_PHYA_SCS_MMFR0__AUXREGS___S                     20
#define   DBG_PHYA_SCS_MMFR0__AUXREGS__AUXCTRLONLY             0x1
#define   DBG_PHYA_SCS_MMFR0__TCMSUPPORT___M     0x000F0000
#define   DBG_PHYA_SCS_MMFR0__TCMSUPPORT___S                  16
#define   DBG_PHYA_SCS_MMFR0__TCMSUPPORT__TCMNOTSUPPORTED             0x0
#define   DBG_PHYA_SCS_MMFR0__SHAREABILITY___M   0x0000F000
#define   DBG_PHYA_SCS_MMFR0__SHAREABILITY___S                12
#define   DBG_PHYA_SCS_MMFR0__SHAREABILITY__ONELEVEL             0x0
#define   DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___M 0x00000F00
#define   DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___S               8
#define   DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY__NONCACHEABLE             0x0
#define   DBG_PHYA_SCS_MMFR0__PMSA___M           0x000000F0
#define   DBG_PHYA_SCS_MMFR0__PMSA___S                         4
#define   DBG_PHYA_SCS_MMFR0__PMSA__PMSAV7                   0x3
#define   DBG_PHYA_SCS_MMFR0___M                 0x00FFFFF0   
#define   DBG_PHYA_SCS_MMFR0___S                               4

#define DBG_PHYA_SCS_MMFR1                        (0x00BEBD54)
#define   DBG_PHYA_SCS_MMFR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_MMFR1___POR               0x00000000
#define   DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___POR 0x00000000
#define   DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___M 0xFFFFFFFF
#define   DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___S               0
#define   DBG_PHYA_SCS_MMFR1___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_MMFR1___S                               0

#define DBG_PHYA_SCS_MMFR2                        (0x00BEBD58)
#define   DBG_PHYA_SCS_MMFR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_MMFR2___POR               0x01000000
#define   DBG_PHYA_SCS_MMFR2__WFISTALL___POR     0x1
#define   DBG_PHYA_SCS_MMFR2__WFISTALL___M       0x0F000000
#define   DBG_PHYA_SCS_MMFR2__WFISTALL___S                    24
#define   DBG_PHYA_SCS_MMFR2__WFISTALL__WFISTALLSUPPORTED             0x1
#define   DBG_PHYA_SCS_MMFR2___M                 0x0F000000   
#define   DBG_PHYA_SCS_MMFR2___S                              24

#define DBG_PHYA_SCS_MMFR3                        (0x00BEBD5C)
#define   DBG_PHYA_SCS_MMFR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_MMFR3___POR               0x00000000
#define   DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___POR 0x00000000
#define   DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___M 0xFFFFFFFF
#define   DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___S               0
#define   DBG_PHYA_SCS_MMFR3___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_MMFR3___S                               0

#define DBG_PHYA_SCS_ISAR0                        (0x00BEBD60)
#define   DBG_PHYA_SCS_ISAR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_ISAR0___POR               0x01101110
#define   DBG_PHYA_SCS_ISAR0__FIXME___POR        0x01101110
#define   DBG_PHYA_SCS_ISAR0__FIXME___M          0xFFFFFFFF
#define   DBG_PHYA_SCS_ISAR0__FIXME___S                        0
#define   DBG_PHYA_SCS_ISAR0___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_ISAR0___S                               0

#define DBG_PHYA_SCS_ISAR1                        (0x00BEBD64)
#define   DBG_PHYA_SCS_ISAR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_ISAR1___POR               0x02111000
#define   DBG_PHYA_SCS_ISAR1__FIXME___POR        0x02111000
#define   DBG_PHYA_SCS_ISAR1__FIXME___M          0xFFFFFFFF
#define   DBG_PHYA_SCS_ISAR1__FIXME___S                        0
#define   DBG_PHYA_SCS_ISAR1___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_ISAR1___S                               0

#define DBG_PHYA_SCS_ISAR2                        (0x00BEBD68)
#define   DBG_PHYA_SCS_ISAR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_ISAR2___POR               0x21112231
#define   DBG_PHYA_SCS_ISAR2__FIXME___POR        0x21112231
#define   DBG_PHYA_SCS_ISAR2__FIXME___M          0xFFFFFFFF
#define   DBG_PHYA_SCS_ISAR2__FIXME___S                        0
#define   DBG_PHYA_SCS_ISAR2___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_ISAR2___S                               0

#define DBG_PHYA_SCS_ISAR3                        (0x00BEBD6C)
#define   DBG_PHYA_SCS_ISAR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_ISAR3___POR               0x01111110
#define   DBG_PHYA_SCS_ISAR3__FIXME___POR        0x01111110
#define   DBG_PHYA_SCS_ISAR3__FIXME___M          0xFFFFFFFF
#define   DBG_PHYA_SCS_ISAR3__FIXME___S                        0
#define   DBG_PHYA_SCS_ISAR3___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_ISAR3___S                               0

#define DBG_PHYA_SCS_ISAR4                        (0x00BEBD70)
#define   DBG_PHYA_SCS_ISAR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_ISAR4___POR               0x01310132
#define   DBG_PHYA_SCS_ISAR4__FIXME___POR        0x01310132
#define   DBG_PHYA_SCS_ISAR4__FIXME___M          0xFFFFFFFF
#define   DBG_PHYA_SCS_ISAR4__FIXME___S                        0
#define   DBG_PHYA_SCS_ISAR4___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_ISAR4___S                               0

#define DBG_PHYA_SCS_CPACR                        (0x00BEBD88)
#define   DBG_PHYA_SCS_CPACR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_CPACR___POR               0x00000000
#define   DBG_PHYA_SCS_CPACR__CP11___POR         0x0
#define   DBG_PHYA_SCS_CPACR__CP10___POR         0x0
#define   DBG_PHYA_SCS_CPACR__CP7___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP6___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP5___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP4___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP3___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP2___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP1___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP0___POR          0x0
#define   DBG_PHYA_SCS_CPACR__CP11___M           0x00C00000
#define   DBG_PHYA_SCS_CPACR__CP11___S                        22
#define   DBG_PHYA_SCS_CPACR__CP11__NOACCESS                 0x0
#define   DBG_PHYA_SCS_CPACR__CP11__PRIVILEGED               0x1
#define   DBG_PHYA_SCS_CPACR__CP11__FULL                     0x2
#define   DBG_PHYA_SCS_CPACR__CP10___M           0x00300000
#define   DBG_PHYA_SCS_CPACR__CP10___S                        20
#define   DBG_PHYA_SCS_CPACR__CP10__NOACCESS                 0x0
#define   DBG_PHYA_SCS_CPACR__CP10__PRIVILEGED               0x1
#define   DBG_PHYA_SCS_CPACR__CP10__FULL                     0x2
#define   DBG_PHYA_SCS_CPACR__CP7___M            0x0000C000
#define   DBG_PHYA_SCS_CPACR__CP7___S                         14
#define   DBG_PHYA_SCS_CPACR__CP7__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP7__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP7__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP6___M            0x00003000
#define   DBG_PHYA_SCS_CPACR__CP6___S                         12
#define   DBG_PHYA_SCS_CPACR__CP6__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP6__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP6__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP5___M            0x00000C00
#define   DBG_PHYA_SCS_CPACR__CP5___S                         10
#define   DBG_PHYA_SCS_CPACR__CP5__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP5__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP5__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP4___M            0x00000300
#define   DBG_PHYA_SCS_CPACR__CP4___S                          8
#define   DBG_PHYA_SCS_CPACR__CP4__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP4__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP4__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP3___M            0x000000C0
#define   DBG_PHYA_SCS_CPACR__CP3___S                          6
#define   DBG_PHYA_SCS_CPACR__CP3__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP3__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP3__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP2___M            0x00000030
#define   DBG_PHYA_SCS_CPACR__CP2___S                          4
#define   DBG_PHYA_SCS_CPACR__CP2__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP2__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP2__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP1___M            0x0000000C
#define   DBG_PHYA_SCS_CPACR__CP1___S                          2
#define   DBG_PHYA_SCS_CPACR__CP1__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP1__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP1__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR__CP0___M            0x00000003
#define   DBG_PHYA_SCS_CPACR__CP0___S                          0
#define   DBG_PHYA_SCS_CPACR__CP0__NOACCESS                  0x0
#define   DBG_PHYA_SCS_CPACR__CP0__PRIVILEGED                0x1
#define   DBG_PHYA_SCS_CPACR__CP0__FULL                      0x2
#define   DBG_PHYA_SCS_CPACR___M                 0x00F0FFFF   
#define   DBG_PHYA_SCS_CPACR___S                               0

#define DBG_PHYA_SCS_DHCSR_WR                     (0x00BEBDF0)
#define   DBG_PHYA_SCS_DHCSR_WR___RWC               QCSR_REG_WO    
#define   DBG_PHYA_SCS_DHCSR_WR___POR            0x00000000
#define   DBG_PHYA_SCS_DHCSR_WR__DBGKEY___POR    0x0000
#define   DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_WR__C_STEP___POR    0x0
#define   DBG_PHYA_SCS_DHCSR_WR__C_HALT___POR    0x0
#define   DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_WR__DBGKEY___M      0xFFFF0000
#define   DBG_PHYA_SCS_DHCSR_WR__DBGKEY___S                   16
#define   DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___M 0x00000020
#define   DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___S               5
#define   DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___M  0x00000008
#define   DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___S                3
#define   DBG_PHYA_SCS_DHCSR_WR__C_STEP___M      0x00000004
#define   DBG_PHYA_SCS_DHCSR_WR__C_STEP___S                    2
#define   DBG_PHYA_SCS_DHCSR_WR__C_HALT___M      0x00000002
#define   DBG_PHYA_SCS_DHCSR_WR__C_HALT___S                    1
#define   DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___M   0x00000001
#define   DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___S                 0
#define   DBG_PHYA_SCS_DHCSR_WR___M              0xFFFF002F   
#define   DBG_PHYA_SCS_DHCSR_WR___S                            0

#define DBG_PHYA_SCS_DHCSR_RD                     (0x00BEBDF0)
#define   DBG_PHYA_SCS_DHCSR_RD___RWC               QCSR_REG_RO    
#define   DBG_PHYA_SCS_DHCSR_RD___POR            0x02010000
#define   DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___POR 0x1
#define   DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___POR  0x0
#define   DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___POR   0x0
#define   DBG_PHYA_SCS_DHCSR_RD__S_HALT___POR    0x0
#define   DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___POR  0x1
#define   DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_RD__C_STEP___POR    0x0
#define   DBG_PHYA_SCS_DHCSR_RD__C_HALT___POR    0x0
#define   DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___POR 0x0
#define   DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___M  0x02000000
#define   DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___S               25
#define   DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___M 0x01000000
#define   DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___S              24
#define   DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___M    0x00080000
#define   DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___S                 19
#define   DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___M     0x00040000
#define   DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___S                  18
#define   DBG_PHYA_SCS_DHCSR_RD__S_HALT___M      0x00020000
#define   DBG_PHYA_SCS_DHCSR_RD__S_HALT___S                   17
#define   DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___M    0x00010000
#define   DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___S                 16
#define   DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___M 0x00000020
#define   DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___S               5
#define   DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___M  0x00000008
#define   DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___S                3
#define   DBG_PHYA_SCS_DHCSR_RD__C_STEP___M      0x00000004
#define   DBG_PHYA_SCS_DHCSR_RD__C_STEP___S                    2
#define   DBG_PHYA_SCS_DHCSR_RD__C_HALT___M      0x00000002
#define   DBG_PHYA_SCS_DHCSR_RD__C_HALT___S                    1
#define   DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___M   0x00000001
#define   DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___S                 0
#define   DBG_PHYA_SCS_DHCSR_RD___M              0x030F002F   
#define   DBG_PHYA_SCS_DHCSR_RD___S                            0

#define DBG_PHYA_SCS_DCRSR                        (0x00BEBDF4)
#define   DBG_PHYA_SCS_DCRSR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_DCRSR___POR               0x00000000
#define   DBG_PHYA_SCS_DCRSR__REGWNR___POR       0x0
#define   DBG_PHYA_SCS_DCRSR__REGSEL___POR       0x00
#define   DBG_PHYA_SCS_DCRSR__REGWNR___M         0x00010000
#define   DBG_PHYA_SCS_DCRSR__REGWNR___S                      16
#define   DBG_PHYA_SCS_DCRSR__REGWNR__READ                   0x0
#define   DBG_PHYA_SCS_DCRSR__REGWNR__WRITE                  0x1
#define   DBG_PHYA_SCS_DCRSR__REGSEL___M         0x0000007F
#define   DBG_PHYA_SCS_DCRSR__REGSEL___S                       0
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R0                    0x00
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R1                    0x01
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R2                    0x02
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R3                    0x03
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R4                    0x04
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R5                    0x05
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R6                    0x06
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R7                    0x07
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R8                    0x08
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R9                    0x09
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R10                   0x0A
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R11                   0x0B
#define   DBG_PHYA_SCS_DCRSR__REGSEL__R12                   0x0C
#define   DBG_PHYA_SCS_DCRSR__REGSEL__SP                    0x0D
#define   DBG_PHYA_SCS_DCRSR__REGSEL__LR                    0x0E
#define   DBG_PHYA_SCS_DCRSR__REGSEL__DBGRETADR             0x0F
#define   DBG_PHYA_SCS_DCRSR__REGSEL__XPSR                  0x10
#define   DBG_PHYA_SCS_DCRSR__REGSEL__MSP                   0x11
#define   DBG_PHYA_SCS_DCRSR__REGSEL__PSP                   0x12
#define   DBG_PHYA_SCS_DCRSR__REGSEL__MISC                  0x14
#define   DBG_PHYA_SCS_DCRSR___M                 0x0001007F   
#define   DBG_PHYA_SCS_DCRSR___S                               0

#define DBG_PHYA_SCS_DCRDR                        (0x00BEBDF8)
#define   DBG_PHYA_SCS_DCRDR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_DCRDR___POR               0x00000000
#define   DBG_PHYA_SCS_DCRDR__DBGTMP___POR       0x00000000
#define   DBG_PHYA_SCS_DCRDR__DBGTMP___M         0xFFFFFFFF
#define   DBG_PHYA_SCS_DCRDR__DBGTMP___S                       0
#define   DBG_PHYA_SCS_DCRDR___M                 0xFFFFFFFF   
#define   DBG_PHYA_SCS_DCRDR___S                               0

#define DBG_PHYA_SCS_DEMCR                        (0x00BEBDFC)
#define   DBG_PHYA_SCS_DEMCR___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_SCS_DEMCR___POR               0x00000000
#define   DBG_PHYA_SCS_DEMCR__TRCENA___POR       0x0
#define   DBG_PHYA_SCS_DEMCR__MON_REQ___POR      0x0
#define   DBG_PHYA_SCS_DEMCR__MON_STEP___POR     0x0
#define   DBG_PHYA_SCS_DEMCR__MON_PEND___POR     0x0
#define   DBG_PHYA_SCS_DEMCR__MON_EN___POR       0x0
#define   DBG_PHYA_SCS_DEMCR__VC_HARDERR___POR   0x0
#define   DBG_PHYA_SCS_DEMCR__VC_INTERR___POR    0x0
#define   DBG_PHYA_SCS_DEMCR__VC_BUSERR___POR    0x0
#define   DBG_PHYA_SCS_DEMCR__VC_STATERR___POR   0x0
#define   DBG_PHYA_SCS_DEMCR__VC_CHKERR___POR    0x0
#define   DBG_PHYA_SCS_DEMCR__VC_NOCPERR___POR   0x0
#define   DBG_PHYA_SCS_DEMCR__VC_MMERR___POR     0x0
#define   DBG_PHYA_SCS_DEMCR__VC_CORERESET___POR 0x0
#define   DBG_PHYA_SCS_DEMCR__TRCENA___M         0x01000000
#define   DBG_PHYA_SCS_DEMCR__TRCENA___S                      24
#define   DBG_PHYA_SCS_DEMCR__TRCENA__DWT_ITM_DISABLED             0x0
#define   DBG_PHYA_SCS_DEMCR__TRCENA__DWT_ITM_ENABLED             0x1
#define   DBG_PHYA_SCS_DEMCR__MON_REQ___M        0x00080000
#define   DBG_PHYA_SCS_DEMCR__MON_REQ___S                     19
#define   DBG_PHYA_SCS_DEMCR__MON_STEP___M       0x00040000
#define   DBG_PHYA_SCS_DEMCR__MON_STEP___S                    18
#define   DBG_PHYA_SCS_DEMCR__MON_PEND___M       0x00020000
#define   DBG_PHYA_SCS_DEMCR__MON_PEND___S                    17
#define   DBG_PHYA_SCS_DEMCR__MON_EN___M         0x00010000
#define   DBG_PHYA_SCS_DEMCR__MON_EN___S                      16
#define   DBG_PHYA_SCS_DEMCR__VC_HARDERR___M     0x00000400
#define   DBG_PHYA_SCS_DEMCR__VC_HARDERR___S                  10
#define   DBG_PHYA_SCS_DEMCR__VC_INTERR___M      0x00000200
#define   DBG_PHYA_SCS_DEMCR__VC_INTERR___S                    9
#define   DBG_PHYA_SCS_DEMCR__VC_BUSERR___M      0x00000100
#define   DBG_PHYA_SCS_DEMCR__VC_BUSERR___S                    8
#define   DBG_PHYA_SCS_DEMCR__VC_STATERR___M     0x00000080
#define   DBG_PHYA_SCS_DEMCR__VC_STATERR___S                   7
#define   DBG_PHYA_SCS_DEMCR__VC_CHKERR___M      0x00000040
#define   DBG_PHYA_SCS_DEMCR__VC_CHKERR___S                    6
#define   DBG_PHYA_SCS_DEMCR__VC_NOCPERR___M     0x00000020
#define   DBG_PHYA_SCS_DEMCR__VC_NOCPERR___S                   5
#define   DBG_PHYA_SCS_DEMCR__VC_MMERR___M       0x00000010
#define   DBG_PHYA_SCS_DEMCR__VC_MMERR___S                     4
#define   DBG_PHYA_SCS_DEMCR__VC_CORERESET___M   0x00000001
#define   DBG_PHYA_SCS_DEMCR__VC_CORERESET___S                 0
#define   DBG_PHYA_SCS_DEMCR___M                 0x010F07F1   
#define   DBG_PHYA_SCS_DEMCR___S                               0

#define DBG_PHYA_SCS_STIR                         (0x00BEBF00)
#define   DBG_PHYA_SCS_STIR___RWC                   QCSR_REG_WO    
#define   DBG_PHYA_SCS_STIR___POR                0x00000000
#define   DBG_PHYA_SCS_STIR__INTID___POR         0x000
#define   DBG_PHYA_SCS_STIR__INTID___M           0x000001FF
#define   DBG_PHYA_SCS_STIR__INTID___S                         0
#define   DBG_PHYA_SCS_STIR___M                  0x000001FF   
#define   DBG_PHYA_SCS_STIR___S                                0

#define DBG_PHYA_SCS_PIDR4                        (0x00BEBFD0)
#define   DBG_PHYA_SCS_PIDR4___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_PIDR4___POR               0x00000004
#define   DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___POR 0x4
#define   DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___S               4
#define   DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___S               0
#define   DBG_PHYA_SCS_PIDR4___M                 0x000000FF   
#define   DBG_PHYA_SCS_PIDR4___S                               0

#define DBG_PHYA_SCS_PIDR0                        (0x00BEBFE0)
#define   DBG_PHYA_SCS_PIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_PIDR0___POR               0x00000000
#define   DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___POR  0x00
#define   DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___M    0x000000FF
#define   DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___S                  0
#define   DBG_PHYA_SCS_PIDR0___M                 0x000000FF   
#define   DBG_PHYA_SCS_PIDR0___S                               0

#define DBG_PHYA_SCS_PIDR1                        (0x00BEBFE4)
#define   DBG_PHYA_SCS_PIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_PIDR1___POR               0x000000B0
#define   DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___POR 0xB
#define   DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___POR 0x0
#define   DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___S               4
#define   DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___M   0x0000000F
#define   DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___S                 0
#define   DBG_PHYA_SCS_PIDR1___M                 0x000000FF   
#define   DBG_PHYA_SCS_PIDR1___S                               0

#define DBG_PHYA_SCS_PIDR2                        (0x00BEBFE8)
#define   DBG_PHYA_SCS_PIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_PIDR2___POR               0x0000000B
#define   DBG_PHYA_SCS_PIDR2__MAJREV___POR       0x0
#define   DBG_PHYA_SCS_PIDR2__JEDEC___POR        0x1
#define   DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___POR 0x3
#define   DBG_PHYA_SCS_PIDR2__MAJREV___M         0x000000F0
#define   DBG_PHYA_SCS_PIDR2__MAJREV___S                       4
#define   DBG_PHYA_SCS_PIDR2__JEDEC___M          0x00000008
#define   DBG_PHYA_SCS_PIDR2__JEDEC___S                        3
#define   DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___S               0
#define   DBG_PHYA_SCS_PIDR2___M                 0x000000FF   
#define   DBG_PHYA_SCS_PIDR2___S                               0

#define DBG_PHYA_SCS_PIDR3                        (0x00BEBFEC)
#define   DBG_PHYA_SCS_PIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_PIDR3___POR               0x00000000
#define   DBG_PHYA_SCS_PIDR3__REV_AND___POR      0x0
#define   DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_SCS_PIDR3__REV_AND___M        0x000000F0
#define   DBG_PHYA_SCS_PIDR3__REV_AND___S                      4
#define   DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_SCS_PIDR3___M                 0x000000FF   
#define   DBG_PHYA_SCS_PIDR3___S                               0

#define DBG_PHYA_SCS_CIDR0                        (0x00BEBFF0)
#define   DBG_PHYA_SCS_CIDR0___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_CIDR0___POR               0x0000000D
#define   DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___POR 0x0D
#define   DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___M   0x000000FF
#define   DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___S                 0
#define   DBG_PHYA_SCS_CIDR0___M                 0x000000FF   
#define   DBG_PHYA_SCS_CIDR0___S                               0

#define DBG_PHYA_SCS_CIDR1                        (0x00BEBFF4)
#define   DBG_PHYA_SCS_CIDR1___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_CIDR1___POR               0x000000E0
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___POR 0xE
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___POR 0x0
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___M 0x000000F0
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___S               4
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___M  0x0000000F
#define   DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___S                0
#define   DBG_PHYA_SCS_CIDR1___M                 0x000000FF   
#define   DBG_PHYA_SCS_CIDR1___S                               0

#define DBG_PHYA_SCS_CIDR2                        (0x00BEBFF8)
#define   DBG_PHYA_SCS_CIDR2___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_CIDR2___POR               0x00000005
#define   DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___POR 0x05
#define   DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___M 0x000000FF
#define   DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___S               0
#define   DBG_PHYA_SCS_CIDR2___M                 0x000000FF   
#define   DBG_PHYA_SCS_CIDR2___S                               0

#define DBG_PHYA_SCS_CIDR3                        (0x00BEBFFC)
#define   DBG_PHYA_SCS_CIDR3___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_SCS_CIDR3___POR               0x000000B1
#define   DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___POR 0xB1
#define   DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___M 0x000000FF
#define   DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___S               0
#define   DBG_PHYA_SCS_CIDR3___M                 0x000000FF   
#define   DBG_PHYA_SCS_CIDR3___S                               0

#define DBG_PHYA_ETMCR                            (0x00BEC000)
#define   DBG_PHYA_ETMCR___RWC                      QCSR_REG_RW    
#define   DBG_PHYA_ETMCR___POR                   0x00000411
#define   DBG_PHYA_ETMCR__TSTMPEN___POR          0x0
#define   DBG_PHYA_ETMCR__ETMENOUTCTRL___POR     0x0
#define   DBG_PHYA_ETMCR__ETMPROGMODEEN___POR    0x1
#define   DBG_PHYA_ETMCR__DBGREQCTRL___POR       0x0
#define   DBG_PHYA_ETMCR__ALLBROUT___POR         0x0
#define   DBG_PHYA_ETMCR__STALLCPU___POR         0x0
#define   DBG_PHYA_ETMCR__PORTSZ___POR           0x1
#define   DBG_PHYA_ETMCR__ETMPWRDWN___POR        0x1
#define   DBG_PHYA_ETMCR__TSTMPEN___M            0x10000000
#define   DBG_PHYA_ETMCR__TSTMPEN___S                         28
#define   DBG_PHYA_ETMCR__TSTMPEN__TSTMPOFF                  0x0
#define   DBG_PHYA_ETMCR__TSTMPEN__TSTMPON                   0x1
#define   DBG_PHYA_ETMCR__ETMENOUTCTRL___M       0x00000800
#define   DBG_PHYA_ETMCR__ETMENOUTCTRL___S                    11
#define   DBG_PHYA_ETMCR__ETMENOUTCTRL__ETMENOUTLO             0x0
#define   DBG_PHYA_ETMCR__ETMENOUTCTRL__ETMENOUTHI             0x1
#define   DBG_PHYA_ETMCR__ETMPROGMODEEN___M      0x00000400
#define   DBG_PHYA_ETMCR__ETMPROGMODEEN___S                   10
#define   DBG_PHYA_ETMCR__ETMPROGMODEEN__PROGOFFTRACEON             0x0
#define   DBG_PHYA_ETMCR__ETMPROGMODEEN__PROGONTRACEOFF             0x1
#define   DBG_PHYA_ETMCR__DBGREQCTRL___M         0x00000200
#define   DBG_PHYA_ETMCR__DBGREQCTRL___S                       9
#define   DBG_PHYA_ETMCR__DBGREQCTRL__DBGREQOUTOFF             0x0
#define   DBG_PHYA_ETMCR__DBGREQCTRL__DBGREQOUTON             0x1
#define   DBG_PHYA_ETMCR__ALLBROUT___M           0x00000100
#define   DBG_PHYA_ETMCR__ALLBROUT___S                         8
#define   DBG_PHYA_ETMCR__ALLBROUT__CONDTKNBRONLY             0x0
#define   DBG_PHYA_ETMCR__ALLBROUT__ALLBREN                  0x1
#define   DBG_PHYA_ETMCR__STALLCPU___M           0x00000080
#define   DBG_PHYA_ETMCR__STALLCPU___S                         7
#define   DBG_PHYA_ETMCR__STALLCPU__STALLOFF                 0x0
#define   DBG_PHYA_ETMCR__STALLCPU__STALLON                  0x1
#define   DBG_PHYA_ETMCR__PORTSZ___M             0x00000070
#define   DBG_PHYA_ETMCR__PORTSZ___S                           4
#define   DBG_PHYA_ETMCR__PORTSZ__DEFAULT                    0x1
#define   DBG_PHYA_ETMCR__ETMPWRDWN___M          0x00000001
#define   DBG_PHYA_ETMCR__ETMPWRDWN___S                        0
#define   DBG_PHYA_ETMCR__ETMPWRDWN__PWRUP                   0x0
#define   DBG_PHYA_ETMCR__ETMPWRDWN__PWRDWN                  0x1
#define   DBG_PHYA_ETMCR___M                     0x10000FF1   
#define   DBG_PHYA_ETMCR___S                                   0

#define DBG_PHYA_ETMCCR                           (0x00BEC004)
#define   DBG_PHYA_ETMCCR___RWC                     QCSR_REG_RO    
#define   DBG_PHYA_ETMCCR___POR                  0x8C802000
#define   DBG_PHYA_ETMCCR__ETMIDREGPRESENT___POR 0x1
#define   DBG_PHYA_ETMCCR__MEMACCESS___POR       0x1
#define   DBG_PHYA_ETMCCR__STARTSTOPPRESENT___POR 0x1
#define   DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___POR 0x0
#define   DBG_PHYA_ETMCCR__FIFOFULLPRESENT___POR 0x1
#define   DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___POR   0x0
#define   DBG_PHYA_ETMCCR__NUMEXTINPUTS___POR    0x0
#define   DBG_PHYA_ETMCCR__SEQPRESENT___POR      0x0
#define   DBG_PHYA_ETMCCR__NUMCNTRS___POR        0x1
#define   DBG_PHYA_ETMCCR__NUMMEMMAPDEC___POR    0x00
#define   DBG_PHYA_ETMCCR__NUMDATACOMP___POR     0x0
#define   DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___POR 0x0
#define   DBG_PHYA_ETMCCR__ETMIDREGPRESENT___M   0x80000000
#define   DBG_PHYA_ETMCCR__ETMIDREGPRESENT___S                31
#define   DBG_PHYA_ETMCCR__ETMIDREGPRESENT__PRESENT             0x1
#define   DBG_PHYA_ETMCCR__MEMACCESS___M         0x08000000
#define   DBG_PHYA_ETMCCR__MEMACCESS___S                      27
#define   DBG_PHYA_ETMCCR__MEMACCESS__SUPPORTED              0x1
#define   DBG_PHYA_ETMCCR__STARTSTOPPRESENT___M  0x04000000
#define   DBG_PHYA_ETMCCR__STARTSTOPPRESENT___S               26
#define   DBG_PHYA_ETMCCR__STARTSTOPPRESENT__PRESENT             0x1
#define   DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___M  0x03000000
#define   DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___S               24
#define   DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP__NOTIMPLEMENTED             0x0
#define   DBG_PHYA_ETMCCR__FIFOFULLPRESENT___M   0x00800000
#define   DBG_PHYA_ETMCCR__FIFOFULLPRESENT___S                23
#define   DBG_PHYA_ETMCCR__FIFOFULLPRESENT__FIFOFULLPRESENT             0x1
#define   DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___M     0x00700000
#define   DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___S                  20
#define   DBG_PHYA_ETMCCR__NUMEXTOUTPUTS__NOTIMPLEMENTED             0x0
#define   DBG_PHYA_ETMCCR__NUMEXTINPUTS___M      0x000E0000
#define   DBG_PHYA_ETMCCR__NUMEXTINPUTS___S                   17
#define   DBG_PHYA_ETMCCR__SEQPRESENT___M        0x00010000
#define   DBG_PHYA_ETMCCR__SEQPRESENT___S                     16
#define   DBG_PHYA_ETMCCR__SEQPRESENT__NOTIMPLEMENTED             0x0
#define   DBG_PHYA_ETMCCR__NUMCNTRS___M          0x0000E000
#define   DBG_PHYA_ETMCCR__NUMCNTRS___S                       13
#define   DBG_PHYA_ETMCCR__NUMMEMMAPDEC___M      0x00001F00
#define   DBG_PHYA_ETMCCR__NUMMEMMAPDEC___S                    8
#define   DBG_PHYA_ETMCCR__NUMMEMMAPDEC__NOTIMPLEMENTED            0x00
#define   DBG_PHYA_ETMCCR__NUMDATACOMP___M       0x000000F0
#define   DBG_PHYA_ETMCCR__NUMDATACOMP___S                     4
#define   DBG_PHYA_ETMCCR__NUMDATACOMP__NOTIMPLEMENTED             0x0
#define   DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___M   0x0000000F
#define   DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___S                 0
#define   DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR__NOTIMPLEMENTED             0x0
#define   DBG_PHYA_ETMCCR___M                    0x8FFFFFFF   
#define   DBG_PHYA_ETMCCR___S                                  0

#define DBG_PHYA_ETMTRIGGER                       (0x00BEC008)
#define   DBG_PHYA_ETMTRIGGER___RWC                 QCSR_REG_RW    
#define   DBG_PHYA_ETMTRIGGER___POR              0x00000000
#define   DBG_PHYA_ETMTRIGGER__FUNCTION___POR    0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___POR 0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___POR 0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___POR 0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___POR 0x0
#define   DBG_PHYA_ETMTRIGGER__FUNCTION___M      0x0001C000
#define   DBG_PHYA_ETMTRIGGER__FUNCTION___S                   14
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__A                   0x0
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA                0x1
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__A_AND_B             0x2
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_AND_B             0x3
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_AND_NOTB             0x4
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__A_OR_B              0x5
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_OR_B             0x6
#define   DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_OR_NOTB             0x7
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___M 0x00003800
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___S              11
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__MISC1             0x5
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__MISC2             0x6
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___M 0x00000780
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___S               7
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___M 0x00000070
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___S               4
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__MISC1             0x5
#define   DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__MISC2             0x6
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___M 0x0000000F
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___S               0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTRIGGER___M                0x0001FFFF   
#define   DBG_PHYA_ETMTRIGGER___S                              0

#define DBG_PHYA_ETMSR                            (0x00BEC010)
#define   DBG_PHYA_ETMSR___RWC                      QCSR_REG_RW    
#define   DBG_PHYA_ETMSR___POR                   0x00000002
#define   DBG_PHYA_ETMSR__TRIGGER___POR          0x0
#define   DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___POR 0x0
#define   DBG_PHYA_ETMSR__PROGBITSTATUS___POR    0x1
#define   DBG_PHYA_ETMSR__OVFLOW___POR           0x0
#define   DBG_PHYA_ETMSR__TRIGGER___M            0x00000008
#define   DBG_PHYA_ETMSR__TRIGGER___S                          3
#define   DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___M 0x00000004
#define   DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___S               2
#define   DBG_PHYA_ETMSR__PROGBITSTATUS___M      0x00000002
#define   DBG_PHYA_ETMSR__PROGBITSTATUS___S                    1
#define   DBG_PHYA_ETMSR__OVFLOW___M             0x00000001
#define   DBG_PHYA_ETMSR__OVFLOW___S                           0
#define   DBG_PHYA_ETMSR___M                     0x0000000F   
#define   DBG_PHYA_ETMSR___S                                   0

#define DBG_PHYA_ETMSCR                           (0x00BEC014)
#define   DBG_PHYA_ETMSCR___RWC                     QCSR_REG_RO    
#define   DBG_PHYA_ETMSCR___POR                  0x00020D09
#define   DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___POR 0x1
#define   DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___POR 0x0
#define   DBG_PHYA_ETMSCR__PORTMODESUPPORT___POR 0x1
#define   DBG_PHYA_ETMSCR__PORTSZSUPPORT___POR   0x1
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_3___POR     0x0
#define   DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___POR 0x1
#define   DBG_PHYA_ETMSCR__RSVD___POR            0x1
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___POR   0x1
#define   DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___M 0x00020000
#define   DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___S              17
#define   DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS__FETCHCOMPNOTIMPLEMENTED             0x1
#define   DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___M   0x00007000
#define   DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___S                12
#define   DBG_PHYA_ETMSCR__NUMCPUSUPPORTED__ONECPU             0x0
#define   DBG_PHYA_ETMSCR__PORTMODESUPPORT___M   0x00000800
#define   DBG_PHYA_ETMSCR__PORTMODESUPPORT___S                11
#define   DBG_PHYA_ETMSCR__PORTMODESUPPORT__SUPPORTED             0x1
#define   DBG_PHYA_ETMSCR__PORTSZSUPPORT___M     0x00000400
#define   DBG_PHYA_ETMSCR__PORTSZSUPPORT___S                  10
#define   DBG_PHYA_ETMSCR__PORTSZSUPPORT__SUPPORTED             0x1
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_3___M       0x00000200
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_3___S                     9
#define   DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___M   0x00000100
#define   DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___S                 8
#define   DBG_PHYA_ETMSCR__FIFOFULLSUPPORT__SUPPORTED             0x1
#define   DBG_PHYA_ETMSCR__RSVD___M              0x00000008
#define   DBG_PHYA_ETMSCR__RSVD___S                            3
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___M     0x00000007
#define   DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___S                   0
#define   DBG_PHYA_ETMSCR___M                    0x00027F0F   
#define   DBG_PHYA_ETMSCR___S                                  0

#define DBG_PHYA_ETMTEEVR                         (0x00BEC020)
#define   DBG_PHYA_ETMTEEVR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_ETMTEEVR___POR                0x00000000
#define   DBG_PHYA_ETMTEEVR__FUNCTION___POR      0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___POR 0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___POR 0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE___POR 0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___POR 0x0
#define   DBG_PHYA_ETMTEEVR__FUNCTION___M        0x0001C000
#define   DBG_PHYA_ETMTEEVR__FUNCTION___S                     14
#define   DBG_PHYA_ETMTEEVR__FUNCTION__A                     0x0
#define   DBG_PHYA_ETMTEEVR__FUNCTION__NOTA                  0x1
#define   DBG_PHYA_ETMTEEVR__FUNCTION__A_AND_B               0x2
#define   DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_AND_B             0x3
#define   DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_AND_NOTB             0x4
#define   DBG_PHYA_ETMTEEVR__FUNCTION__A_OR_B                0x5
#define   DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_OR_B             0x6
#define   DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_OR_NOTB             0x7
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___M   0x00003800
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___S                11
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__MISC1             0x5
#define   DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__MISC2             0x6
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___M  0x00000780
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___S                7
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE___M   0x00000070
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE___S                 4
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE__MISC1             0x5
#define   DBG_PHYA_ETMTEEVR__RESOURCEATYPE__MISC2             0x6
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___M  0x0000000F
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___S                0
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTEEVR___M                  0x0001FFFF   
#define   DBG_PHYA_ETMTEEVR___S                                0

#define DBG_PHYA_ETMTECR1                         (0x00BEC024)
#define   DBG_PHYA_ETMTECR1___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_ETMTECR1___POR                0x00000000
#define   DBG_PHYA_ETMTECR1__TRACECTRLEN___POR   0x0
#define   DBG_PHYA_ETMTECR1__TRACECTRLEN___M     0x02000000
#define   DBG_PHYA_ETMTECR1__TRACECTRLEN___S                  25
#define   DBG_PHYA_ETMTECR1__TRACECTRLEN__TRCSTARTSTOPOFF             0x0
#define   DBG_PHYA_ETMTECR1__TRACECTRLEN__TRCSTARSTOPON             0x1
#define   DBG_PHYA_ETMTECR1___M                  0x02000000   
#define   DBG_PHYA_ETMTECR1___S                               25

#define DBG_PHYA_ETMFFLR                          (0x00BEC02C)
#define   DBG_PHYA_ETMFFLR___RWC                    QCSR_REG_RW    
#define   DBG_PHYA_ETMFFLR___POR                 0x00000000
#define   DBG_PHYA_ETMFFLR__NUMBYTESFREE___POR   0x00
#define   DBG_PHYA_ETMFFLR__NUMBYTESFREE___M     0x000000FF
#define   DBG_PHYA_ETMFFLR__NUMBYTESFREE___S                   0
#define   DBG_PHYA_ETMFFLR___M                   0x000000FF   
#define   DBG_PHYA_ETMFFLR___S                                 0

#define DBG_PHYA_ETMCNTRLDVR1                     (0x00BEC140)
#define   DBG_PHYA_ETMCNTRLDVR1___RWC               QCSR_REG_RW    
#define   DBG_PHYA_ETMCNTRLDVR1___POR            0x00000000
#define   DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___POR 0x0000
#define   DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___M   0x0000FFFF
#define   DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___S                 0
#define   DBG_PHYA_ETMCNTRLDVR1___M              0x0000FFFF   
#define   DBG_PHYA_ETMCNTRLDVR1___S                            0

#define DBG_PHYA_ETMSYNCFR                        (0x00BEC1E0)
#define   DBG_PHYA_ETMSYNCFR___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_ETMSYNCFR___POR               0x00000400
#define   DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___POR 0x400
#define   DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___M 0x00000FFF
#define   DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___S               0
#define   DBG_PHYA_ETMSYNCFR___M                 0x00000FFF   
#define   DBG_PHYA_ETMSYNCFR___S                               0

#define DBG_PHYA_ETMIDR                           (0x00BEC1E4)
#define   DBG_PHYA_ETMIDR___RWC                     QCSR_REG_RO    
#define   DBG_PHYA_ETMIDR___POR                  0x4114F253
#define   DBG_PHYA_ETMIDR__IMPLEMENTERCODE___POR 0x41
#define   DBG_PHYA_ETMIDR__BRPKTENC___POR        0x1
#define   DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___POR 0x0
#define   DBG_PHYA_ETMIDR__THUMBISTCNTRACE___POR 0x1
#define   DBG_PHYA_ETMIDR__LOADPCFIRST___POR     0x0
#define   DBG_PHYA_ETMIDR__CPUFAMILY___POR       0xF
#define   DBG_PHYA_ETMIDR__MAJORETMARCHREV___POR 0x2
#define   DBG_PHYA_ETMIDR__MINORETMARCHREV___POR 0x5
#define   DBG_PHYA_ETMIDR__IMPLREVISION___POR    0x3
#define   DBG_PHYA_ETMIDR__IMPLEMENTERCODE___M   0xFF000000
#define   DBG_PHYA_ETMIDR__IMPLEMENTERCODE___S                24
#define   DBG_PHYA_ETMIDR__IMPLEMENTERCODE__ARM             0x41
#define   DBG_PHYA_ETMIDR__BRPKTENC___M          0x00100000
#define   DBG_PHYA_ETMIDR__BRPKTENC___S                       20
#define   DBG_PHYA_ETMIDR__BRPKTENC__IMPLEMENTED             0x1
#define   DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___M 0x00080000
#define   DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___S              19
#define   DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT__ALWAYSASSECURE             0x0
#define   DBG_PHYA_ETMIDR__THUMBISTCNTRACE___M   0x00040000
#define   DBG_PHYA_ETMIDR__THUMBISTCNTRACE___S                18
#define   DBG_PHYA_ETMIDR__THUMBISTCNTRACE__THUMB32BTRACEDASSINGLE             0x1
#define   DBG_PHYA_ETMIDR__LOADPCFIRST___M       0x00010000
#define   DBG_PHYA_ETMIDR__LOADPCFIRST___S                    16
#define   DBG_PHYA_ETMIDR__LOADPCFIRST__DATATRCNOTSUPPORTED             0x0
#define   DBG_PHYA_ETMIDR__CPUFAMILY___M         0x0000F000
#define   DBG_PHYA_ETMIDR__CPUFAMILY___S                      12
#define   DBG_PHYA_ETMIDR__CPUFAMILY__NOTDEFINED             0xF
#define   DBG_PHYA_ETMIDR__MAJORETMARCHREV___M   0x00000F00
#define   DBG_PHYA_ETMIDR__MAJORETMARCHREV___S                 8
#define   DBG_PHYA_ETMIDR__MINORETMARCHREV___M   0x000000F0
#define   DBG_PHYA_ETMIDR__MINORETMARCHREV___S                 4
#define   DBG_PHYA_ETMIDR__IMPLREVISION___M      0x0000000F
#define   DBG_PHYA_ETMIDR__IMPLREVISION___S                    0
#define   DBG_PHYA_ETMIDR___M                    0xFF1DFFFF   
#define   DBG_PHYA_ETMIDR___S                                  0

#define DBG_PHYA_ETMCCER                          (0x00BEC1E8)
#define   DBG_PHYA_ETMCCER___RWC                    QCSR_REG_RO    
#define   DBG_PHYA_ETMCCER___POR                 0x18541800
#define   DBG_PHYA_ETMCCER__TSTMPSZ___POR        0x0
#define   DBG_PHYA_ETMCCER__TSTMPENC___POR       0x1
#define   DBG_PHYA_ETMCCER__REDFUNCTNCTR___POR   0x1
#define   DBG_PHYA_ETMCCER__TSTMPIMPL___POR      0x1
#define   DBG_PHYA_ETMCCER__ETMEIBCRIMPL___POR   0x0
#define   DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___POR 0x1
#define   DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___POR 0x4
#define   DBG_PHYA_ETMCCER__NUMINSTRRES___POR    0x0
#define   DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___POR 0x1
#define   DBG_PHYA_ETMCCER__REGSREADABLE___POR   0x1
#define   DBG_PHYA_ETMCCER__EXTINPBUSIMPL___POR  0x00
#define   DBG_PHYA_ETMCCER__EXTINPSEL___POR      0x0
#define   DBG_PHYA_ETMCCER__TSTMPSZ___M          0x20000000
#define   DBG_PHYA_ETMCCER__TSTMPSZ___S                       29
#define   DBG_PHYA_ETMCCER__TSTMPSZ__SZIS48BIT               0x0
#define   DBG_PHYA_ETMCCER__TSTMPENC___M         0x10000000
#define   DBG_PHYA_ETMCCER__TSTMPENC___S                      28
#define   DBG_PHYA_ETMCCER__TSTMPENC__ENCISNATBIN             0x1
#define   DBG_PHYA_ETMCCER__REDFUNCTNCTR___M     0x08000000
#define   DBG_PHYA_ETMCCER__REDFUNCTNCTR___S                  27
#define   DBG_PHYA_ETMCCER__REDFUNCTNCTR__CTRISREDFUNCCTR             0x1
#define   DBG_PHYA_ETMCCER__TSTMPIMPL___M        0x00400000
#define   DBG_PHYA_ETMCCER__TSTMPIMPL___S                     22
#define   DBG_PHYA_ETMCCER__TSTMPIMPL__TSTMPISIMPL             0x1
#define   DBG_PHYA_ETMCCER__ETMEIBCRIMPL___M     0x00200000
#define   DBG_PHYA_ETMCCER__ETMEIBCRIMPL___S                  21
#define   DBG_PHYA_ETMCCER__ETMEIBCRIMPL__ETMEIBCRNOTIMPL             0x0
#define   DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___M 0x00100000
#define   DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___S              20
#define   DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT__STARTSTOPUSESWTCHPTYES             0x1
#define   DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___M 0x000F0000
#define   DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___S              16
#define   DBG_PHYA_ETMCCER__NUMINSTRRES___M      0x0000E000
#define   DBG_PHYA_ETMCCER__NUMINSTRRES___S                   13
#define   DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___M 0x00001000
#define   DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___S              12
#define   DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP__DATAADDRCOMPNOTSUPPORTED             0x0
#define   DBG_PHYA_ETMCCER__REGSREADABLE___M     0x00000800
#define   DBG_PHYA_ETMCCER__REGSREADABLE___S                  11
#define   DBG_PHYA_ETMCCER__REGSREADABLE__REGSAREREADABLE             0x1
#define   DBG_PHYA_ETMCCER__EXTINPBUSIMPL___M    0x000007F8
#define   DBG_PHYA_ETMCCER__EXTINPBUSIMPL___S                  3
#define   DBG_PHYA_ETMCCER__EXTINPSEL___M        0x00000007
#define   DBG_PHYA_ETMCCER__EXTINPSEL___S                      0
#define   DBG_PHYA_ETMCCER___M                   0x387FFFFF   
#define   DBG_PHYA_ETMCCER___S                                 0

#define DBG_PHYA_ETMTESSEICR                      (0x00BEC1F0)
#define   DBG_PHYA_ETMTESSEICR___RWC                QCSR_REG_RW    
#define   DBG_PHYA_ETMTESSEICR___POR             0x00000000
#define   DBG_PHYA_ETMTESSEICR__STOPRESSEL___POR 0x0
#define   DBG_PHYA_ETMTESSEICR__STARTRESSEL___POR 0x00
#define   DBG_PHYA_ETMTESSEICR__STOPRESSEL___M   0x000F0000
#define   DBG_PHYA_ETMTESSEICR__STOPRESSEL___S                16
#define   DBG_PHYA_ETMTESSEICR__STARTRESSEL___M  0x000000FF
#define   DBG_PHYA_ETMTESSEICR__STARTRESSEL___S                0
#define   DBG_PHYA_ETMTESSEICR___M               0x000F00FF   
#define   DBG_PHYA_ETMTESSEICR___S                             0

#define DBG_PHYA_ETMTSEVR                         (0x00BEC1F8)
#define   DBG_PHYA_ETMTSEVR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_ETMTSEVR___POR                0x00000000
#define   DBG_PHYA_ETMTSEVR__FUNCTION___POR      0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___POR 0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___POR 0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE___POR 0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___POR 0x0
#define   DBG_PHYA_ETMTSEVR__FUNCTION___M        0x0001C000
#define   DBG_PHYA_ETMTSEVR__FUNCTION___S                     14
#define   DBG_PHYA_ETMTSEVR__FUNCTION__A                     0x0
#define   DBG_PHYA_ETMTSEVR__FUNCTION__NOTA                  0x1
#define   DBG_PHYA_ETMTSEVR__FUNCTION__A_AND_B               0x2
#define   DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_AND_B             0x3
#define   DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_AND_NOTB             0x4
#define   DBG_PHYA_ETMTSEVR__FUNCTION__A_OR_B                0x5
#define   DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_OR_B             0x6
#define   DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_OR_NOTB             0x7
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___M   0x00003800
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___S                11
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__MISC1             0x5
#define   DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__MISC2             0x6
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___M  0x00000780
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___S                7
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE___M   0x00000070
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE___S                 4
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE__ILLEGAL             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE__DWTCOMPINP             0x2
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE__CNTRZERO             0x4
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE__MISC1             0x5
#define   DBG_PHYA_ETMTSEVR__RESOURCEATYPE__MISC2             0x6
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___M  0x0000000F
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___S                0
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP1             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP2             0x1
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP3             0x2
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP4             0x3
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__CNTR1ATZERO             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__TRCSTARTSTOPRES             0xF
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__EXTINP1             0x0
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__EXTINP2             0x1
#define   DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__ALWAYSTRUE             0xF
#define   DBG_PHYA_ETMTSEVR___M                  0x0001FFFF   
#define   DBG_PHYA_ETMTSEVR___S                                0

#define DBG_PHYA_ETMTRACEIDR                      (0x00BEC200)
#define   DBG_PHYA_ETMTRACEIDR___RWC                QCSR_REG_RW    
#define   DBG_PHYA_ETMTRACEIDR___POR             0x00000000
#define   DBG_PHYA_ETMTRACEIDR__ATBID___POR      0x00
#define   DBG_PHYA_ETMTRACEIDR__ATBID___M        0x0000007F
#define   DBG_PHYA_ETMTRACEIDR__ATBID___S                      0
#define   DBG_PHYA_ETMTRACEIDR___M               0x0000007F   
#define   DBG_PHYA_ETMTRACEIDR___S                             0

#define DBG_PHYA_ETMIDR2                          (0x00BEC208)
#define   DBG_PHYA_ETMIDR2___RWC                    QCSR_REG_RO    
#define   DBG_PHYA_ETMIDR2___POR                 0x00000000
#define   DBG_PHYA_ETMIDR2__SWPXFERORDER___POR   0x0
#define   DBG_PHYA_ETMIDR2__RFEXFERORDER___POR   0x0
#define   DBG_PHYA_ETMIDR2__SWPXFERORDER___M     0x00000002
#define   DBG_PHYA_ETMIDR2__SWPXFERORDER___S                   1
#define   DBG_PHYA_ETMIDR2__SWPXFERORDER__LOADBEFORESTORE             0x0
#define   DBG_PHYA_ETMIDR2__SWPXFERORDER__STOREBEFORELOAD             0x1
#define   DBG_PHYA_ETMIDR2__RFEXFERORDER___M     0x00000001
#define   DBG_PHYA_ETMIDR2__RFEXFERORDER___S                   0
#define   DBG_PHYA_ETMIDR2__RFEXFERORDER__PCBEFORECPSR             0x0
#define   DBG_PHYA_ETMIDR2__RFEXFERORDER__CPSRBEFOREPC             0x1
#define   DBG_PHYA_ETMIDR2___M                   0x00000003   
#define   DBG_PHYA_ETMIDR2___S                                 0

#define DBG_PHYA_ETMPDSR                          (0x00BEC314)
#define   DBG_PHYA_ETMPDSR___RWC                    QCSR_REG_RO    
#define   DBG_PHYA_ETMPDSR___POR                 0x00000001
#define   DBG_PHYA_ETMPDSR__ETMPWRDUP___POR      0x1
#define   DBG_PHYA_ETMPDSR__ETMPWRDUP___M        0x00000001
#define   DBG_PHYA_ETMPDSR__ETMPWRDUP___S                      0
#define   DBG_PHYA_ETMPDSR___M                   0x00000001   
#define   DBG_PHYA_ETMPDSR___S                                 0

#define DBG_PHYA_ETM_ITMISCIN                     (0x00BECEE0)
#define   DBG_PHYA_ETM_ITMISCIN___RWC               QCSR_REG_RO    
#define   DBG_PHYA_ETM_ITMISCIN___POR            0x00000000
#define   DBG_PHYA_ETM_ITMISCIN__COREHALT___POR  0x0
#define   DBG_PHYA_ETM_ITMISCIN__EXTIN___POR     0x0
#define   DBG_PHYA_ETM_ITMISCIN__COREHALT___M    0x00000010
#define   DBG_PHYA_ETM_ITMISCIN__COREHALT___S                  4
#define   DBG_PHYA_ETM_ITMISCIN__EXTIN___M       0x00000003
#define   DBG_PHYA_ETM_ITMISCIN__EXTIN___S                     0
#define   DBG_PHYA_ETM_ITMISCIN___M              0x00000013   
#define   DBG_PHYA_ETM_ITMISCIN___S                            0

#define DBG_PHYA_ETM_ITTRIGOUT                    (0x00BECEE8)
#define   DBG_PHYA_ETM_ITTRIGOUT___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ETM_ITTRIGOUT___POR           0x00000000
#define   DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___POR  0x0
#define   DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___M    0x00000001
#define   DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___S                  0
#define   DBG_PHYA_ETM_ITTRIGOUT___M             0x00000001   
#define   DBG_PHYA_ETM_ITTRIGOUT___S                           0

#define DBG_PHYA_ETM_ITATBCTR2                    (0x00BECEF0)
#define   DBG_PHYA_ETM_ITATBCTR2___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ETM_ITATBCTR2___POR           0x00000001
#define   DBG_PHYA_ETM_ITATBCTR2__ATREADY___POR  0x1
#define   DBG_PHYA_ETM_ITATBCTR2__ATREADY___M    0x00000001
#define   DBG_PHYA_ETM_ITATBCTR2__ATREADY___S                  0
#define   DBG_PHYA_ETM_ITATBCTR2___M             0x00000001   
#define   DBG_PHYA_ETM_ITATBCTR2___S                           0

#define DBG_PHYA_ETM_ITATBCTR0                    (0x00BECEF8)
#define   DBG_PHYA_ETM_ITATBCTR0___RWC              QCSR_REG_WO    
#define   DBG_PHYA_ETM_ITATBCTR0___POR           0x00000000
#define   DBG_PHYA_ETM_ITATBCTR0__ATVALID___POR  0x0
#define   DBG_PHYA_ETM_ITATBCTR0__ATVALID___M    0x00000001
#define   DBG_PHYA_ETM_ITATBCTR0__ATVALID___S                  0
#define   DBG_PHYA_ETM_ITATBCTR0___M             0x00000001   
#define   DBG_PHYA_ETM_ITATBCTR0___S                           0

#define DBG_PHYA_ETMITCTRL                        (0x00BECF00)
#define   DBG_PHYA_ETMITCTRL___RWC                  QCSR_REG_RW    
#define   DBG_PHYA_ETMITCTRL___POR               0x00000000
#define   DBG_PHYA_ETMITCTRL__ENABLE___POR       0x0
#define   DBG_PHYA_ETMITCTRL__ENABLE___M         0x00000001
#define   DBG_PHYA_ETMITCTRL__ENABLE___S                       0
#define   DBG_PHYA_ETMITCTRL___M                 0x00000001   
#define   DBG_PHYA_ETMITCTRL___S                               0

#define DBG_PHYA_ETMCLAIMSET                      (0x00BECFA0)
#define   DBG_PHYA_ETMCLAIMSET___RWC                QCSR_REG_RW    
#define   DBG_PHYA_ETMCLAIMSET___POR             0x0000000F
#define   DBG_PHYA_ETMCLAIMSET__TAG___POR        0xF
#define   DBG_PHYA_ETMCLAIMSET__TAG___M          0x0000000F
#define   DBG_PHYA_ETMCLAIMSET__TAG___S                        0
#define   DBG_PHYA_ETMCLAIMSET___M               0x0000000F   
#define   DBG_PHYA_ETMCLAIMSET___S                             0

#define DBG_PHYA_ETMCLAIMCLR                      (0x00BECFA4)
#define   DBG_PHYA_ETMCLAIMCLR___RWC                QCSR_REG_RW    
#define   DBG_PHYA_ETMCLAIMCLR___POR             0x00000000
#define   DBG_PHYA_ETMCLAIMCLR__TAG___POR        0x00
#define   DBG_PHYA_ETMCLAIMCLR__TAG___M          0x000000FF
#define   DBG_PHYA_ETMCLAIMCLR__TAG___S                        0
#define   DBG_PHYA_ETMCLAIMCLR___M               0x000000FF   
#define   DBG_PHYA_ETMCLAIMCLR___S                             0

#define DBG_PHYA_ETMLAR                           (0x00BECFB0)
#define   DBG_PHYA_ETMLAR___RWC                     QCSR_REG_RW    
#define   DBG_PHYA_ETMLAR___POR                  0x00000000
#define   DBG_PHYA_ETMLAR__VALUE___POR           0x00000000
#define   DBG_PHYA_ETMLAR__VALUE___M             0xFFFFFFFF
#define   DBG_PHYA_ETMLAR__VALUE___S                           0
#define   DBG_PHYA_ETMLAR___M                    0xFFFFFFFF   
#define   DBG_PHYA_ETMLAR___S                                  0

#define DBG_PHYA_ETMLSR                           (0x00BECFB4)
#define   DBG_PHYA_ETMLSR___RWC                     QCSR_REG_RO    
#define   DBG_PHYA_ETMLSR___POR                  0x00000003
#define   DBG_PHYA_ETMLSR__LOCKED___POR          0x1
#define   DBG_PHYA_ETMLSR__LOCKINGIMPL___POR     0x1
#define   DBG_PHYA_ETMLSR__LOCKED___M            0x00000002
#define   DBG_PHYA_ETMLSR__LOCKED___S                          1
#define   DBG_PHYA_ETMLSR__LOCKED__ETMUNLOCKED               0x0
#define   DBG_PHYA_ETMLSR__LOCKED__ETMLOCKED                 0x1
#define   DBG_PHYA_ETMLSR__LOCKINGIMPL___M       0x00000001
#define   DBG_PHYA_ETMLSR__LOCKINGIMPL___S                     0
#define   DBG_PHYA_ETMLSR___M                    0x00000003   
#define   DBG_PHYA_ETMLSR___S                                  0

#define DBG_PHYA_ETMAUTHSTATUS                    (0x00BECFB8)
#define   DBG_PHYA_ETMAUTHSTATUS___RWC              QCSR_REG_RO    
#define   DBG_PHYA_ETMAUTHSTATUS__SNI___M        0x000000C0
#define   DBG_PHYA_ETMAUTHSTATUS__SNI___S                      6
#define   DBG_PHYA_ETMAUTHSTATUS__SI___M         0x00000030
#define   DBG_PHYA_ETMAUTHSTATUS__SI___S                       4
#define   DBG_PHYA_ETMAUTHSTATUS__NSNI___M       0x0000000C
#define   DBG_PHYA_ETMAUTHSTATUS__NSNI___S                     2
#define   DBG_PHYA_ETMAUTHSTATUS__NSI___M        0x00000003
#define   DBG_PHYA_ETMAUTHSTATUS__NSI___S                      0
#define   DBG_PHYA_ETMAUTHSTATUS___M             0x000000FF   
#define   DBG_PHYA_ETMAUTHSTATUS___S                           0

#define DBG_PHYA_ETMDEVTYPE                       (0x00BECFCC)
#define   DBG_PHYA_ETMDEVTYPE___RWC                 QCSR_REG_RO    
#define   DBG_PHYA_ETMDEVTYPE___POR              0x00000013
#define   DBG_PHYA_ETMDEVTYPE__SUBTYPE___POR     0x1
#define   DBG_PHYA_ETMDEVTYPE__MAJTYPE___POR     0x3
#define   DBG_PHYA_ETMDEVTYPE__SUBTYPE___M       0x000000F0
#define   DBG_PHYA_ETMDEVTYPE__SUBTYPE___S                     4
#define   DBG_PHYA_ETMDEVTYPE__MAJTYPE___M       0x0000000F
#define   DBG_PHYA_ETMDEVTYPE__MAJTYPE___S                     0
#define   DBG_PHYA_ETMDEVTYPE___M                0x000000FF   
#define   DBG_PHYA_ETMDEVTYPE___S                              0

#define DBG_PHYA_ETMPIDR4                         (0x00BECFD0)
#define   DBG_PHYA_ETMPIDR4___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMPIDR4___POR                0x00000004
#define   DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___POR 0x0
#define   DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___POR 0x4
#define   DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___M 0x000000F0
#define   DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___S               4
#define   DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___M 0x0000000F
#define   DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___S               0
#define   DBG_PHYA_ETMPIDR4___M                  0x000000FF   
#define   DBG_PHYA_ETMPIDR4___S                                0

#define DBG_PHYA_ETMPIDR0                         (0x00BECFE0)
#define   DBG_PHYA_ETMPIDR0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMPIDR0___POR                0x00000024
#define   DBG_PHYA_ETMPIDR0__PARTNUM_7_0___POR   0x24
#define   DBG_PHYA_ETMPIDR0__PARTNUM_7_0___M     0x000000FF
#define   DBG_PHYA_ETMPIDR0__PARTNUM_7_0___S                   0
#define   DBG_PHYA_ETMPIDR0___M                  0x000000FF   
#define   DBG_PHYA_ETMPIDR0___S                                0

#define DBG_PHYA_ETMPIDR1                         (0x00BECFE4)
#define   DBG_PHYA_ETMPIDR1___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMPIDR1___POR                0x000000B9
#define   DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___POR 0xB
#define   DBG_PHYA_ETMPIDR1__PARTNUM_11_8___POR  0x9
#define   DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___M 0x000000F0
#define   DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___S               4
#define   DBG_PHYA_ETMPIDR1__PARTNUM_11_8___M    0x0000000F
#define   DBG_PHYA_ETMPIDR1__PARTNUM_11_8___S                  0
#define   DBG_PHYA_ETMPIDR1___M                  0x000000FF   
#define   DBG_PHYA_ETMPIDR1___S                                0

#define DBG_PHYA_ETMPIDR2                         (0x00BECFE8)
#define   DBG_PHYA_ETMPIDR2___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMPIDR2___POR                0x0000003B
#define   DBG_PHYA_ETMPIDR2__MAJREV___POR        0x3
#define   DBG_PHYA_ETMPIDR2__JEDEC___POR         0x1
#define   DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___POR 0x3
#define   DBG_PHYA_ETMPIDR2__MAJREV___M          0x000000F0
#define   DBG_PHYA_ETMPIDR2__MAJREV___S                        4
#define   DBG_PHYA_ETMPIDR2__JEDEC___M           0x00000008
#define   DBG_PHYA_ETMPIDR2__JEDEC___S                         3
#define   DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___M 0x00000007
#define   DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___S               0
#define   DBG_PHYA_ETMPIDR2___M                  0x000000FF   
#define   DBG_PHYA_ETMPIDR2___S                                0

#define DBG_PHYA_ETMPIDR3                         (0x00BECFEC)
#define   DBG_PHYA_ETMPIDR3___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMPIDR3___POR                0x00000000
#define   DBG_PHYA_ETMPIDR3__REV_AND___POR       0x0
#define   DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___POR 0x0
#define   DBG_PHYA_ETMPIDR3__REV_AND___M         0x000000F0
#define   DBG_PHYA_ETMPIDR3__REV_AND___S                       4
#define   DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___M 0x0000000F
#define   DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___S               0
#define   DBG_PHYA_ETMPIDR3___M                  0x000000FF   
#define   DBG_PHYA_ETMPIDR3___S                                0

#define DBG_PHYA_ETMCIDR0                         (0x00BECFF0)
#define   DBG_PHYA_ETMCIDR0___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMCIDR0___POR                0x0000000D
#define   DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___POR  0x0D
#define   DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___M    0x000000FF
#define   DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___S                  0
#define   DBG_PHYA_ETMCIDR0___M                  0x000000FF   
#define   DBG_PHYA_ETMCIDR0___S                                0

#define DBG_PHYA_ETMCIDR1                         (0x00BECFF4)
#define   DBG_PHYA_ETMCIDR1___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMCIDR1___POR                0x00000090
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___POR 0x9
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___POR 0x0
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___M  0x000000F0
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___S                4
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___M   0x0000000F
#define   DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___S                 0
#define   DBG_PHYA_ETMCIDR1___M                  0x000000FF   
#define   DBG_PHYA_ETMCIDR1___S                                0

#define DBG_PHYA_ETMCIDR2                         (0x00BECFF8)
#define   DBG_PHYA_ETMCIDR2___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMCIDR2___POR                0x00000005
#define   DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___POR 0x05
#define   DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___M  0x000000FF
#define   DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___S                0
#define   DBG_PHYA_ETMCIDR2___M                  0x000000FF   
#define   DBG_PHYA_ETMCIDR2___S                                0

#define DBG_PHYA_ETMCIDR3                         (0x00BECFFC)
#define   DBG_PHYA_ETMCIDR3___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_ETMCIDR3___POR                0x000000B1
#define   DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___POR 0xB1
#define   DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___M  0x000000FF
#define   DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___S                0
#define   DBG_PHYA_ETMCIDR3___M                  0x000000FF   
#define   DBG_PHYA_ETMCIDR3___S                                0

#define DBG_PHYA_M3CTI_CTICONTROL                 (0x00BED000)
#define   DBG_PHYA_M3CTI_CTICONTROL___RWC           QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTICONTROL___POR        0x00000000
#define   DBG_PHYA_M3CTI_CTICONTROL__GLBEN___POR 0x0
#define   DBG_PHYA_M3CTI_CTICONTROL__GLBEN___M   0x00000001
#define   DBG_PHYA_M3CTI_CTICONTROL__GLBEN___S                 0
#define   DBG_PHYA_M3CTI_CTICONTROL__GLBEN__DISABLED             0x0
#define   DBG_PHYA_M3CTI_CTICONTROL__GLBEN__ENABLED             0x1
#define   DBG_PHYA_M3CTI_CTICONTROL___M          0x00000001   
#define   DBG_PHYA_M3CTI_CTICONTROL___S                        0

#define DBG_PHYA_M3CTI_CTIINTACK                  (0x00BED010)
#define   DBG_PHYA_M3CTI_CTIINTACK___RWC            QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_CTIINTACK___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIINTACK__INTACK___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINTACK__INTACK___M   0x000000FF
#define   DBG_PHYA_M3CTI_CTIINTACK__INTACK___S                 0
#define   DBG_PHYA_M3CTI_CTIINTACK___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINTACK___S                         0

#define DBG_PHYA_M3CTI_CTIAPPSET                  (0x00BED014)
#define   DBG_PHYA_M3CTI_CTIAPPSET___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIAPPSET___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIAPPSET__APPSET___POR 0x00
#define   DBG_PHYA_M3CTI_CTIAPPSET__APPSET___M   0x000000FF
#define   DBG_PHYA_M3CTI_CTIAPPSET__APPSET___S                 0
#define   DBG_PHYA_M3CTI_CTIAPPSET___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIAPPSET___S                         0

#define DBG_PHYA_M3CTI_CTIAPPCLEAR                (0x00BED018)
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR___RWC          QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR___POR       0x00000000
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___POR 0x00
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___S               0
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR___M         0x000000FF   
#define   DBG_PHYA_M3CTI_CTIAPPCLEAR___S                       0

#define DBG_PHYA_M3CTI_CTIAPPPULSE                (0x00BED01C)
#define   DBG_PHYA_M3CTI_CTIAPPPULSE___RWC          QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_CTIAPPPULSE___POR       0x00000000
#define   DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___POR 0x00
#define   DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___S               0
#define   DBG_PHYA_M3CTI_CTIAPPPULSE___M         0x000000FF   
#define   DBG_PHYA_M3CTI_CTIAPPPULSE___S                       0

#define DBG_PHYA_M3CTI_CTIINEN0                   (0x00BED020)
#define   DBG_PHYA_M3CTI_CTIINEN0___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN0___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN0___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN0___S                          0

#define DBG_PHYA_M3CTI_CTIINEN1                   (0x00BED024)
#define   DBG_PHYA_M3CTI_CTIINEN1___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN1___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN1___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN1___S                          0

#define DBG_PHYA_M3CTI_CTIINEN2                   (0x00BED028)
#define   DBG_PHYA_M3CTI_CTIINEN2___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN2___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN2___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN2___S                          0

#define DBG_PHYA_M3CTI_CTIINEN3                   (0x00BED02C)
#define   DBG_PHYA_M3CTI_CTIINEN3___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN3___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN3___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN3___S                          0

#define DBG_PHYA_M3CTI_CTIINEN4                   (0x00BED030)
#define   DBG_PHYA_M3CTI_CTIINEN4___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN4___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN4___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN4___S                          0

#define DBG_PHYA_M3CTI_CTIINEN5                   (0x00BED034)
#define   DBG_PHYA_M3CTI_CTIINEN5___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN5___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN5___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN5___S                          0

#define DBG_PHYA_M3CTI_CTIINEN6                   (0x00BED038)
#define   DBG_PHYA_M3CTI_CTIINEN6___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN6___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN6___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN6___S                          0

#define DBG_PHYA_M3CTI_CTIINEN7                   (0x00BED03C)
#define   DBG_PHYA_M3CTI_CTIINEN7___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIINEN7___POR          0x00000000
#define   DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___M  0x000000FF
#define   DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___S                0
#define   DBG_PHYA_M3CTI_CTIINEN7___M            0x000000FF   
#define   DBG_PHYA_M3CTI_CTIINEN7___S                          0

#define DBG_PHYA_M3CTI_CTIOUTEN0                  (0x00BED0A0)
#define   DBG_PHYA_M3CTI_CTIOUTEN0___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN0___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN0___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN0___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN1                  (0x00BED0A4)
#define   DBG_PHYA_M3CTI_CTIOUTEN1___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN1___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN1___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN1___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN2                  (0x00BED0A8)
#define   DBG_PHYA_M3CTI_CTIOUTEN2___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN2___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN2___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN2___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN3                  (0x00BED0AC)
#define   DBG_PHYA_M3CTI_CTIOUTEN3___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN3___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN3___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN3___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN4                  (0x00BED0B0)
#define   DBG_PHYA_M3CTI_CTIOUTEN4___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN4___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN4___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN4___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN5                  (0x00BED0B4)
#define   DBG_PHYA_M3CTI_CTIOUTEN5___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN5___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN5___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN5___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN6                  (0x00BED0B8)
#define   DBG_PHYA_M3CTI_CTIOUTEN6___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN6___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN6___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN6___S                         0

#define DBG_PHYA_M3CTI_CTIOUTEN7                  (0x00BED0BC)
#define   DBG_PHYA_M3CTI_CTIOUTEN7___RWC            QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIOUTEN7___POR         0x00000000
#define   DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___POR 0x00
#define   DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___S               0
#define   DBG_PHYA_M3CTI_CTIOUTEN7___M           0x000000FF   
#define   DBG_PHYA_M3CTI_CTIOUTEN7___S                         0

#define DBG_PHYA_M3CTI_CTITRIGINSTATUS            (0x00BED130)
#define   DBG_PHYA_M3CTI_CTITRIGINSTATUS___RWC      QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTITRIGINSTATUS__TRIGINSTATUS___S               0
#define   DBG_PHYA_M3CTI_CTITRIGINSTATUS___M     0x000000FF   
#define   DBG_PHYA_M3CTI_CTITRIGINSTATUS___S                   0

#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS           (0x00BED134)
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___RWC     QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___POR  0x00000000
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S               0
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___M    0x000000FF   
#define   DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___S                  0

#define DBG_PHYA_M3CTI_CTICHINSTATUS              (0x00BED138)
#define   DBG_PHYA_M3CTI_CTICHINSTATUS___RWC        QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTICHINSTATUS__CTICHINSTATUS___S               0
#define   DBG_PHYA_M3CTI_CTICHINSTATUS___M       0x000000FF   
#define   DBG_PHYA_M3CTI_CTICHINSTATUS___S                     0

#define DBG_PHYA_M3CTI_CTICHOUTSTATUS             (0x00BED13C)
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS___RWC       QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS___POR    0x00000000
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___S               0
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS___M      0x000000FF   
#define   DBG_PHYA_M3CTI_CTICHOUTSTATUS___S                    0

#define DBG_PHYA_M3CTI_CTIGATE                    (0x00BED140)
#define   DBG_PHYA_M3CTI_CTIGATE___RWC              QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CTIGATE___POR           0x000000FF
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___POR 0x1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___M 0x00000080
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___S               7
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___M 0x00000040
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___S               6
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___M 0x00000020
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___S               5
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___M 0x00000010
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___S               4
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___M 0x00000008
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___S               3
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___M 0x00000004
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___S               2
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___M 0x00000002
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___S               1
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___M 0x00000001
#define   DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___S               0
#define   DBG_PHYA_M3CTI_CTIGATE___M             0x000000FF   
#define   DBG_PHYA_M3CTI_CTIGATE___S                           0

#define DBG_PHYA_M3CTI_ASICCTL                    (0x00BED144)
#define   DBG_PHYA_M3CTI_ASICCTL___RWC              QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_ASICCTL___POR           0x00000000
#define   DBG_PHYA_M3CTI_ASICCTL__ASICCTL___POR  0x00000000
#define   DBG_PHYA_M3CTI_ASICCTL__ASICCTL___M    0xFFFFFFFF
#define   DBG_PHYA_M3CTI_ASICCTL__ASICCTL___S                  0
#define   DBG_PHYA_M3CTI_ASICCTL___M             0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_ASICCTL___S                           0

#define DBG_PHYA_M3CTI_ITCHINACK                  (0x00BEDEDC)
#define   DBG_PHYA_M3CTI_ITCHINACK___RWC            QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_ITCHINACK___POR         0x00000000
#define   DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___POR 0x00
#define   DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___M 0x000000FF
#define   DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___S               0
#define   DBG_PHYA_M3CTI_ITCHINACK___M           0x000000FF   
#define   DBG_PHYA_M3CTI_ITCHINACK___S                         0

#define DBG_PHYA_M3CTI_ITTRIGINACK                (0x00BEDEE0)
#define   DBG_PHYA_M3CTI_ITTRIGINACK___RWC          QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_ITTRIGINACK___POR       0x00000000
#define   DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___POR 0x00
#define   DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___M 0x000000FF
#define   DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___S               0
#define   DBG_PHYA_M3CTI_ITTRIGINACK___M         0x000000FF   
#define   DBG_PHYA_M3CTI_ITTRIGINACK___S                       0

#define DBG_PHYA_M3CTI_ITCHOUT                    (0x00BEDEE4)
#define   DBG_PHYA_M3CTI_ITCHOUT___RWC              QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_ITCHOUT___POR           0x00000000
#define   DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___POR  0x00
#define   DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___M    0x000000FF
#define   DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___S                  0
#define   DBG_PHYA_M3CTI_ITCHOUT___M             0x000000FF   
#define   DBG_PHYA_M3CTI_ITCHOUT___S                           0

#define DBG_PHYA_M3CTI_ITTRIGOUT                  (0x00BEDEE8)
#define   DBG_PHYA_M3CTI_ITTRIGOUT___RWC            QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_ITTRIGOUT___POR         0x00000000
#define   DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___POR 0x00
#define   DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___M 0x000000FF
#define   DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___S               0
#define   DBG_PHYA_M3CTI_ITTRIGOUT___M           0x000000FF   
#define   DBG_PHYA_M3CTI_ITTRIGOUT___S                         0

#define DBG_PHYA_M3CTI_ITCHOUTACK                 (0x00BEDEEC)
#define   DBG_PHYA_M3CTI_ITCHOUTACK___RWC           QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_ITCHOUTACK___POR        0x00000000
#define   DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___POR 0x00
#define   DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___M 0x000000FF
#define   DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___S               0
#define   DBG_PHYA_M3CTI_ITCHOUTACK___M          0x000000FF   
#define   DBG_PHYA_M3CTI_ITCHOUTACK___S                        0

#define DBG_PHYA_M3CTI_ITTRIGOUTACK               (0x00BEDEF0)
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK___RWC         QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK___POR      0x00000000
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000000FF
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___S               0
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK___M        0x000000FF   
#define   DBG_PHYA_M3CTI_ITTRIGOUTACK___S                      0

#define DBG_PHYA_M3CTI_ITCHIN                     (0x00BEDEF4)
#define   DBG_PHYA_M3CTI_ITCHIN___RWC               QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_ITCHIN___POR            0x00000000
#define   DBG_PHYA_M3CTI_ITCHIN__CTCHIN___POR    0x00
#define   DBG_PHYA_M3CTI_ITCHIN__CTCHIN___M      0x000000FF
#define   DBG_PHYA_M3CTI_ITCHIN__CTCHIN___S                    0
#define   DBG_PHYA_M3CTI_ITCHIN___M              0x000000FF   
#define   DBG_PHYA_M3CTI_ITCHIN___S                            0

#define DBG_PHYA_M3CTI_ITTRIGIN                   (0x00BEDEF8)
#define   DBG_PHYA_M3CTI_ITTRIGIN___RWC             QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_ITTRIGIN___POR          0x00000000
#define   DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___POR 0x00
#define   DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___M  0x000000FF
#define   DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___S                0
#define   DBG_PHYA_M3CTI_ITTRIGIN___M            0x000000FF   
#define   DBG_PHYA_M3CTI_ITTRIGIN___S                          0

#define DBG_PHYA_M3CTI_ITCTRL                     (0x00BEDF00)
#define   DBG_PHYA_M3CTI_ITCTRL___RWC               QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_ITCTRL___POR            0x00000000
#define   DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___POR 0x0
#define   DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___M 0x00000001
#define   DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___S               0
#define   DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE             0x0
#define   DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE             0x1
#define   DBG_PHYA_M3CTI_ITCTRL___M              0x00000001   
#define   DBG_PHYA_M3CTI_ITCTRL___S                            0

#define DBG_PHYA_M3CTI_CLAIMSET                   (0x00BEDFA0)
#define   DBG_PHYA_M3CTI_CLAIMSET___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CLAIMSET___POR          0x0000000F
#define   DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___POR 0xF
#define   DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___M  0x0000000F
#define   DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___S                0
#define   DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS             0xF
#define   DBG_PHYA_M3CTI_CLAIMSET___M            0x0000000F   
#define   DBG_PHYA_M3CTI_CLAIMSET___S                          0

#define DBG_PHYA_M3CTI_CLAIMCLR                   (0x00BEDFA4)
#define   DBG_PHYA_M3CTI_CLAIMCLR___RWC             QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_CLAIMCLR___POR          0x00000000
#define   DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___POR 0x0
#define   DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___M  0x0000000F
#define   DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___S                0
#define   DBG_PHYA_M3CTI_CLAIMCLR___M            0x0000000F   
#define   DBG_PHYA_M3CTI_CLAIMCLR___S                          0

#define DBG_PHYA_M3CTI_DEVAFF0                    (0x00BEDFA8)
#define   DBG_PHYA_M3CTI_DEVAFF0___RWC              QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVAFF0___POR           0x00000000
#define   DBG_PHYA_M3CTI_DEVAFF0__VAL___POR      0x00000000
#define   DBG_PHYA_M3CTI_DEVAFF0__VAL___M        0xFFFFFFFF
#define   DBG_PHYA_M3CTI_DEVAFF0__VAL___S                      0
#define   DBG_PHYA_M3CTI_DEVAFF0___M             0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_DEVAFF0___S                           0

#define DBG_PHYA_M3CTI_DEVAFF1                    (0x00BEDFAC)
#define   DBG_PHYA_M3CTI_DEVAFF1___RWC              QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVAFF1___POR           0x00000000
#define   DBG_PHYA_M3CTI_DEVAFF1__VAL___POR      0x00000000
#define   DBG_PHYA_M3CTI_DEVAFF1__VAL___M        0xFFFFFFFF
#define   DBG_PHYA_M3CTI_DEVAFF1__VAL___S                      0
#define   DBG_PHYA_M3CTI_DEVAFF1___M             0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_DEVAFF1___S                           0

#define DBG_PHYA_M3CTI_LAR                        (0x00BEDFB0)
#define   DBG_PHYA_M3CTI_LAR___RWC                  QCSR_REG_WO    
#define   DBG_PHYA_M3CTI_LAR__ACCESS_W___M       0xFFFFFFFF
#define   DBG_PHYA_M3CTI_LAR__ACCESS_W___S                     0
#define   DBG_PHYA_M3CTI_LAR__ACCESS_W__UNLOCK        0xC5ACCE55
#define   DBG_PHYA_M3CTI_LAR___M                 0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_LAR___S                               0

#define DBG_PHYA_M3CTI_LSR                        (0x00BEDFB4)
#define   DBG_PHYA_M3CTI_LSR___RWC                  QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_LSR___POR               0x00000003
#define   DBG_PHYA_M3CTI_LSR__LOCKTYPE___POR     0x0
#define   DBG_PHYA_M3CTI_LSR__LOCKGRANT___POR    0x1
#define   DBG_PHYA_M3CTI_LSR__LOCKEXIST___POR    0x1
#define   DBG_PHYA_M3CTI_LSR__LOCKTYPE___M       0x00000004
#define   DBG_PHYA_M3CTI_LSR__LOCKTYPE___S                     2
#define   DBG_PHYA_M3CTI_LSR__LOCKTYPE__SIZE_32BIT             0x0
#define   DBG_PHYA_M3CTI_LSR__LOCKGRANT___M      0x00000002
#define   DBG_PHYA_M3CTI_LSR__LOCKGRANT___S                    1
#define   DBG_PHYA_M3CTI_LSR__LOCKGRANT__ACCESS_PERMITTED             0x0
#define   DBG_PHYA_M3CTI_LSR__LOCKGRANT__DEVICE_LOCKED             0x1
#define   DBG_PHYA_M3CTI_LSR__LOCKEXIST___M      0x00000001
#define   DBG_PHYA_M3CTI_LSR__LOCKEXIST___S                    0
#define   DBG_PHYA_M3CTI_LSR__LOCKEXIST__LOCK_NOT_PRESENT             0x0
#define   DBG_PHYA_M3CTI_LSR__LOCKEXIST__LOCK_PRESENT             0x1
#define   DBG_PHYA_M3CTI_LSR___M                 0x00000007   
#define   DBG_PHYA_M3CTI_LSR___S                               0

#define DBG_PHYA_M3CTI_AUTHSTATUS                 (0x00BEDFB8)
#define   DBG_PHYA_M3CTI_AUTHSTATUS___RWC           QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SNID___M    0x000000C0
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SNID___S                  6
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SNID__NOT_IMPLEMENTED             0x0
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SID___M     0x00000030
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SID___S                   4
#define   DBG_PHYA_M3CTI_AUTHSTATUS__SID__NOT_IMPLEMENTED             0x0
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSNID___M   0x0000000C
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSNID___S                 2
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSNID__DISABLED             0x2
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSNID__ENABLED             0x3
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSID___M    0x00000003
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSID___S                  0
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSID__DISABLED             0x2
#define   DBG_PHYA_M3CTI_AUTHSTATUS__NSID__ENABLED             0x3
#define   DBG_PHYA_M3CTI_AUTHSTATUS___M          0x000000FF   
#define   DBG_PHYA_M3CTI_AUTHSTATUS___S                        0

#define DBG_PHYA_M3CTI_DEVARCH                    (0x00BEDFBC)
#define   DBG_PHYA_M3CTI_DEVARCH___RWC              QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVARCH___POR           0x8EF00A14
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___POR 0x477
#define   DBG_PHYA_M3CTI_DEVARCH__PRESENT___POR  0x1
#define   DBG_PHYA_M3CTI_DEVARCH__REVISION___POR 0x0
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHID___POR   0x0A14
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___M  0xFFE00000
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___S               21
#define   DBG_PHYA_M3CTI_DEVARCH__PRESENT___M    0x00100000
#define   DBG_PHYA_M3CTI_DEVARCH__PRESENT___S                 20
#define   DBG_PHYA_M3CTI_DEVARCH__REVISION___M   0x000F0000
#define   DBG_PHYA_M3CTI_DEVARCH__REVISION___S                16
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHID___M     0x0000FFFF
#define   DBG_PHYA_M3CTI_DEVARCH__ARCHID___S                   0
#define   DBG_PHYA_M3CTI_DEVARCH___M             0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_DEVARCH___S                           0

#define DBG_PHYA_M3CTI_DEVID2                     (0x00BEDFC0)
#define   DBG_PHYA_M3CTI_DEVID2___RWC               QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVID2___POR            0x00000000
#define   DBG_PHYA_M3CTI_DEVID2__IMPLDEF___POR   0x0
#define   DBG_PHYA_M3CTI_DEVID2__IMPLDEF___M     0x00000001
#define   DBG_PHYA_M3CTI_DEVID2__IMPLDEF___S                   0
#define   DBG_PHYA_M3CTI_DEVID2___M              0x00000001   
#define   DBG_PHYA_M3CTI_DEVID2___S                            0

#define DBG_PHYA_M3CTI_DEVID1                     (0x00BEDFC4)
#define   DBG_PHYA_M3CTI_DEVID1___RWC               QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVID1___POR            0x00000000
#define   DBG_PHYA_M3CTI_DEVID1__IMPLDEF___POR   0x0
#define   DBG_PHYA_M3CTI_DEVID1__IMPLDEF___M     0x00000001
#define   DBG_PHYA_M3CTI_DEVID1__IMPLDEF___S                   0
#define   DBG_PHYA_M3CTI_DEVID1___M              0x00000001   
#define   DBG_PHYA_M3CTI_DEVID1___S                            0

#define DBG_PHYA_M3CTI_DEVID                      (0x00BEDFC8)
#define   DBG_PHYA_M3CTI_DEVID___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVID___POR             0x00080800
#define   DBG_PHYA_M3CTI_DEVID__NUMCH___POR      0x8
#define   DBG_PHYA_M3CTI_DEVID__NUMTRIG___POR    0x8
#define   DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___POR  0x00
#define   DBG_PHYA_M3CTI_DEVID__NUMCH___M        0x003F0000
#define   DBG_PHYA_M3CTI_DEVID__NUMCH___S                     16
#define   DBG_PHYA_M3CTI_DEVID__NUMTRIG___M      0x0000FF00
#define   DBG_PHYA_M3CTI_DEVID__NUMTRIG___S                    8
#define   DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___M    0x0000001F
#define   DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___S                  0
#define   DBG_PHYA_M3CTI_DEVID___M               0x003FFF1F   
#define   DBG_PHYA_M3CTI_DEVID___S                             0

#define DBG_PHYA_M3CTI_DEVTYPE                    (0x00BEDFCC)
#define   DBG_PHYA_M3CTI_DEVTYPE___RWC              QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_DEVTYPE___POR           0x00000014
#define   DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___POR 0x1
#define   DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___POR 0x4
#define   DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___M   0x000000F0
#define   DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___S                 4
#define   DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX             0x1
#define   DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___M 0x0000000F
#define   DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___S               0
#define   DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL             0x4
#define   DBG_PHYA_M3CTI_DEVTYPE___M             0x000000FF   
#define   DBG_PHYA_M3CTI_DEVTYPE___S                           0

#define DBG_PHYA_M3CTI_PIDR0                      (0x00BEDFE0)
#define   DBG_PHYA_M3CTI_PIDR0___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_PIDR0___POR             0x00000006
#define   DBG_PHYA_M3CTI_PIDR0__PART_0___POR     0x06
#define   DBG_PHYA_M3CTI_PIDR0__PART_0___M       0x000000FF
#define   DBG_PHYA_M3CTI_PIDR0__PART_0___S                     0
#define   DBG_PHYA_M3CTI_PIDR0__PART_0__CTI_PART_NUMBER_7_0            0x06
#define   DBG_PHYA_M3CTI_PIDR0___M               0x000000FF   
#define   DBG_PHYA_M3CTI_PIDR0___S                             0

#define DBG_PHYA_M3CTI_PIDR1                      (0x00BEDFE4)
#define   DBG_PHYA_M3CTI_PIDR1___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_PIDR1___POR             0x000000B9
#define   DBG_PHYA_M3CTI_PIDR1__DES_0___POR      0xB
#define   DBG_PHYA_M3CTI_PIDR1__PART_1___POR     0x9
#define   DBG_PHYA_M3CTI_PIDR1__DES_0___M        0x000000F0
#define   DBG_PHYA_M3CTI_PIDR1__DES_0___S                      4
#define   DBG_PHYA_M3CTI_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0             0xB
#define   DBG_PHYA_M3CTI_PIDR1__PART_1___M       0x0000000F
#define   DBG_PHYA_M3CTI_PIDR1__PART_1___S                     0
#define   DBG_PHYA_M3CTI_PIDR1__PART_1__CTI_PART_NUMBER_11_8             0x9
#define   DBG_PHYA_M3CTI_PIDR1___M               0x000000FF   
#define   DBG_PHYA_M3CTI_PIDR1___S                             0

#define DBG_PHYA_M3CTI_PIDR2                      (0x00BEDFE8)
#define   DBG_PHYA_M3CTI_PIDR2___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_PIDR2___POR             0x0000004B
#define   DBG_PHYA_M3CTI_PIDR2__REVISION___POR   0x4
#define   DBG_PHYA_M3CTI_PIDR2__JEDEC___POR      0x1
#define   DBG_PHYA_M3CTI_PIDR2__DES_1___POR      0x3
#define   DBG_PHYA_M3CTI_PIDR2__REVISION___M     0x000000F0
#define   DBG_PHYA_M3CTI_PIDR2__REVISION___S                   4
#define   DBG_PHYA_M3CTI_PIDR2__REVISION__R0P4               0x4
#define   DBG_PHYA_M3CTI_PIDR2__REVISION__R0P5               0x5
#define   DBG_PHYA_M3CTI_PIDR2__JEDEC___M        0x00000008
#define   DBG_PHYA_M3CTI_PIDR2__JEDEC___S                      3
#define   DBG_PHYA_M3CTI_PIDR2__JEDEC__JEDEC_IDENTITY             0x1
#define   DBG_PHYA_M3CTI_PIDR2__DES_1___M        0x00000007
#define   DBG_PHYA_M3CTI_PIDR2__DES_1___S                      0
#define   DBG_PHYA_M3CTI_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4             0x3
#define   DBG_PHYA_M3CTI_PIDR2___M               0x000000FF   
#define   DBG_PHYA_M3CTI_PIDR2___S                             0

#define DBG_PHYA_M3CTI_PIDR3                      (0x00BEDFEC)
#define   DBG_PHYA_M3CTI_PIDR3___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_PIDR3___POR             0x00000000
#define   DBG_PHYA_M3CTI_PIDR3__REVAND___POR     0x0
#define   DBG_PHYA_M3CTI_PIDR3__CMOD___POR       0x0
#define   DBG_PHYA_M3CTI_PIDR3__REVAND___M       0x000000F0
#define   DBG_PHYA_M3CTI_PIDR3__REVAND___S                     4
#define   DBG_PHYA_M3CTI_PIDR3__REVAND__NO_MODIFICATION             0x0
#define   DBG_PHYA_M3CTI_PIDR3__CMOD___M         0x0000000F
#define   DBG_PHYA_M3CTI_PIDR3__CMOD___S                       0
#define   DBG_PHYA_M3CTI_PIDR3__CMOD__NO_MODIFICATION             0x0
#define   DBG_PHYA_M3CTI_PIDR3___M               0x000000FF   
#define   DBG_PHYA_M3CTI_PIDR3___S                             0

#define DBG_PHYA_M3CTI_PIDR4                      (0x00BEDFD0)
#define   DBG_PHYA_M3CTI_PIDR4___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_PIDR4___POR             0x00000004
#define   DBG_PHYA_M3CTI_PIDR4__SIZE___POR       0x0
#define   DBG_PHYA_M3CTI_PIDR4__DES_2___POR      0x4
#define   DBG_PHYA_M3CTI_PIDR4__SIZE___M         0x000000F0
#define   DBG_PHYA_M3CTI_PIDR4__SIZE___S                       4
#define   DBG_PHYA_M3CTI_PIDR4__SIZE__SIZE_4KB               0x0
#define   DBG_PHYA_M3CTI_PIDR4__DES_2___M        0x0000000F
#define   DBG_PHYA_M3CTI_PIDR4__DES_2___S                      0
#define   DBG_PHYA_M3CTI_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE             0x4
#define   DBG_PHYA_M3CTI_PIDR4___M               0x000000FF   
#define   DBG_PHYA_M3CTI_PIDR4___S                             0

#define DBG_PHYA_M3CTI_PIDR5                      (0x00BEDFD4)
#define   DBG_PHYA_M3CTI_PIDR5___RWC                QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_PIDR5__PERIPHID5___M    0xFFFFFFFF
#define   DBG_PHYA_M3CTI_PIDR5__PERIPHID5___S                  0
#define   DBG_PHYA_M3CTI_PIDR5___M               0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_PIDR5___S                             0

#define DBG_PHYA_M3CTI_PIDR6                      (0x00BEDFD8)
#define   DBG_PHYA_M3CTI_PIDR6___RWC                QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_PIDR6__PERIPHID6___M    0xFFFFFFFF
#define   DBG_PHYA_M3CTI_PIDR6__PERIPHID6___S                  0
#define   DBG_PHYA_M3CTI_PIDR6___M               0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_PIDR6___S                             0

#define DBG_PHYA_M3CTI_PIDR7                      (0x00BEDFDC)
#define   DBG_PHYA_M3CTI_PIDR7___RWC                QCSR_REG_RW    
#define   DBG_PHYA_M3CTI_PIDR7__PERIPHID7___M    0xFFFFFFFF
#define   DBG_PHYA_M3CTI_PIDR7__PERIPHID7___S                  0
#define   DBG_PHYA_M3CTI_PIDR7___M               0xFFFFFFFF   
#define   DBG_PHYA_M3CTI_PIDR7___S                             0

#define DBG_PHYA_M3CTI_CIDR0                      (0x00BEDFF0)
#define   DBG_PHYA_M3CTI_CIDR0___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CIDR0___POR             0x0000000D
#define   DBG_PHYA_M3CTI_CIDR0__PRMBL_0___POR    0x0D
#define   DBG_PHYA_M3CTI_CIDR0__PRMBL_0___M      0x000000FF
#define   DBG_PHYA_M3CTI_CIDR0__PRMBL_0___S                    0
#define   DBG_PHYA_M3CTI_CIDR0__PRMBL_0__ID_VALUE_0D            0x0D
#define   DBG_PHYA_M3CTI_CIDR0___M               0x000000FF   
#define   DBG_PHYA_M3CTI_CIDR0___S                             0

#define DBG_PHYA_M3CTI_CIDR1                      (0x00BEDFF4)
#define   DBG_PHYA_M3CTI_CIDR1___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CIDR1___POR             0x00000090
#define   DBG_PHYA_M3CTI_CIDR1__CLASS___POR      0x9
#define   DBG_PHYA_M3CTI_CIDR1__PRMBL_1___POR    0x0
#define   DBG_PHYA_M3CTI_CIDR1__CLASS___M        0x000000F0
#define   DBG_PHYA_M3CTI_CIDR1__CLASS___S                      4
#define   DBG_PHYA_M3CTI_CIDR1__CLASS__CORESIGHT_COMPONENT             0x9
#define   DBG_PHYA_M3CTI_CIDR1__PRMBL_1___M      0x0000000F
#define   DBG_PHYA_M3CTI_CIDR1__PRMBL_1___S                    0
#define   DBG_PHYA_M3CTI_CIDR1__PRMBL_1__ID_VALUE_0             0x0
#define   DBG_PHYA_M3CTI_CIDR1___M               0x000000FF   
#define   DBG_PHYA_M3CTI_CIDR1___S                             0

#define DBG_PHYA_M3CTI_CIDR2                      (0x00BEDFF8)
#define   DBG_PHYA_M3CTI_CIDR2___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CIDR2___POR             0x00000005
#define   DBG_PHYA_M3CTI_CIDR2__PRMBL_2___POR    0x05
#define   DBG_PHYA_M3CTI_CIDR2__PRMBL_2___M      0x000000FF
#define   DBG_PHYA_M3CTI_CIDR2__PRMBL_2___S                    0
#define   DBG_PHYA_M3CTI_CIDR2__PRMBL_2__ID_VALUE_05            0x05
#define   DBG_PHYA_M3CTI_CIDR2___M               0x000000FF   
#define   DBG_PHYA_M3CTI_CIDR2___S                             0

#define DBG_PHYA_M3CTI_CIDR3                      (0x00BEDFFC)
#define   DBG_PHYA_M3CTI_CIDR3___RWC                QCSR_REG_RO    
#define   DBG_PHYA_M3CTI_CIDR3___POR             0x000000B1
#define   DBG_PHYA_M3CTI_CIDR3__PRMBL_3___POR    0xB1
#define   DBG_PHYA_M3CTI_CIDR3__PRMBL_3___M      0x000000FF
#define   DBG_PHYA_M3CTI_CIDR3__PRMBL_3___S                    0
#define   DBG_PHYA_M3CTI_CIDR3__PRMBL_3__ID_VALUE_B1            0xB1
#define   DBG_PHYA_M3CTI_CIDR3___M               0x000000FF   
#define   DBG_PHYA_M3CTI_CIDR3___S                             0

#define DBG_PHYA_CPU0_CSW                         (0x00BEE000)
#define   DBG_PHYA_CPU0_CSW___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_CSW___POR                0x23000040
#define   DBG_PHYA_CPU0_CSW__MASTERTYPE___POR    0x1
#define   DBG_PHYA_CPU0_CSW__HPROT_1___POR       0x1
#define   DBG_PHYA_CPU0_CSW__HPROT_0___POR       0x1
#define   DBG_PHYA_CPU0_CSW__MODE___POR          0x0
#define   DBG_PHYA_CPU0_CSW__TRANSINPROG___POR   0x0
#define   DBG_PHYA_CPU0_CSW__DBGSTATUS___POR     0x1
#define   DBG_PHYA_CPU0_CSW__ADDRINC___POR       0x0
#define   DBG_PHYA_CPU0_CSW__SIZE___POR          0x0
#define   DBG_PHYA_CPU0_CSW__MASTERTYPE___M      0x20000000
#define   DBG_PHYA_CPU0_CSW__MASTERTYPE___S                   29
#define   DBG_PHYA_CPU0_CSW__MASTERTYPE__CORE                0x0
#define   DBG_PHYA_CPU0_CSW__MASTERTYPE__DEBUG               0x1
#define   DBG_PHYA_CPU0_CSW__HPROT_1___M         0x02000000
#define   DBG_PHYA_CPU0_CSW__HPROT_1___S                      25
#define   DBG_PHYA_CPU0_CSW__HPROT_1__USER                   0x0
#define   DBG_PHYA_CPU0_CSW__HPROT_1__PRIVILEGED             0x1
#define   DBG_PHYA_CPU0_CSW__HPROT_0___M         0x01000000
#define   DBG_PHYA_CPU0_CSW__HPROT_0___S                      24
#define   DBG_PHYA_CPU0_CSW__HPROT_0__DATA                   0x1
#define   DBG_PHYA_CPU0_CSW__MODE___M            0x00000F00
#define   DBG_PHYA_CPU0_CSW__MODE___S                          8
#define   DBG_PHYA_CPU0_CSW__MODE__NRMLUPDWN                 0x0
#define   DBG_PHYA_CPU0_CSW__TRANSINPROG___M     0x00000080
#define   DBG_PHYA_CPU0_CSW__TRANSINPROG___S                   7
#define   DBG_PHYA_CPU0_CSW__TRANSINPROG__AHBIDLE             0x0
#define   DBG_PHYA_CPU0_CSW__TRANSINPROG__AHBBUSY             0x1
#define   DBG_PHYA_CPU0_CSW__DBGSTATUS___M       0x00000040
#define   DBG_PHYA_CPU0_CSW__DBGSTATUS___S                     6
#define   DBG_PHYA_CPU0_CSW__DBGSTATUS__AHBXFRDIS             0x0
#define   DBG_PHYA_CPU0_CSW__DBGSTATUS__AHBXFREN             0x1
#define   DBG_PHYA_CPU0_CSW__ADDRINC___M         0x00000030
#define   DBG_PHYA_CPU0_CSW__ADDRINC___S                       4
#define   DBG_PHYA_CPU0_CSW__ADDRINC__INCROFF                0x0
#define   DBG_PHYA_CPU0_CSW__ADDRINC__INCRSINGLE             0x1
#define   DBG_PHYA_CPU0_CSW__ADDRINC__INCRPCKD               0x2
#define   DBG_PHYA_CPU0_CSW__SIZE___M            0x00000003
#define   DBG_PHYA_CPU0_CSW__SIZE___S                          0
#define   DBG_PHYA_CPU0_CSW__SIZE__SZBYTE                    0x0
#define   DBG_PHYA_CPU0_CSW__SIZE__SZWORD                    0x1
#define   DBG_PHYA_CPU0_CSW__SIZE__SZDWORD                   0x2
#define   DBG_PHYA_CPU0_CSW___M                  0x23000FF3   
#define   DBG_PHYA_CPU0_CSW___S                                0

#define DBG_PHYA_CPU0_TAR                         (0x00BEE004)
#define   DBG_PHYA_CPU0_TAR___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_TAR___POR                0x00000000
#define   DBG_PHYA_CPU0_TAR__ADDR___POR          0x00000000
#define   DBG_PHYA_CPU0_TAR__ADDR___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_TAR__ADDR___S                          0
#define   DBG_PHYA_CPU0_TAR___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_TAR___S                                0

#define DBG_PHYA_CPU0_DRW                         (0x00BEE00C)
#define   DBG_PHYA_CPU0_DRW___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_DRW___POR                0x00000000
#define   DBG_PHYA_CPU0_DRW__DATA___POR          0x00000000
#define   DBG_PHYA_CPU0_DRW__DATA___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_DRW__DATA___S                          0
#define   DBG_PHYA_CPU0_DRW___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_DRW___S                                0

#define DBG_PHYA_CPU0_BD0                         (0x00BEE010)
#define   DBG_PHYA_CPU0_BD0___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_BD0___POR                0x00000000
#define   DBG_PHYA_CPU0_BD0__DATA___POR          0x00000000
#define   DBG_PHYA_CPU0_BD0__DATA___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_BD0__DATA___S                          0
#define   DBG_PHYA_CPU0_BD0___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_BD0___S                                0

#define DBG_PHYA_CPU0_BD1                         (0x00BEE014)
#define   DBG_PHYA_CPU0_BD1___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_BD1___POR                0x00000000
#define   DBG_PHYA_CPU0_BD1__DATA___POR          0x00000000
#define   DBG_PHYA_CPU0_BD1__DATA___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_BD1__DATA___S                          0
#define   DBG_PHYA_CPU0_BD1___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_BD1___S                                0

#define DBG_PHYA_CPU0_BD2                         (0x00BEE018)
#define   DBG_PHYA_CPU0_BD2___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_BD2___POR                0x00000000
#define   DBG_PHYA_CPU0_BD2__DATA___POR          0x00000000
#define   DBG_PHYA_CPU0_BD2__DATA___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_BD2__DATA___S                          0
#define   DBG_PHYA_CPU0_BD2___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_BD2___S                                0

#define DBG_PHYA_CPU0_BD3                         (0x00BEE01C)
#define   DBG_PHYA_CPU0_BD3___RWC                   QCSR_REG_RW    
#define   DBG_PHYA_CPU0_BD3___POR                0x00000000
#define   DBG_PHYA_CPU0_BD3__DATA___POR          0x00000000
#define   DBG_PHYA_CPU0_BD3__DATA___M            0xFFFFFFFF
#define   DBG_PHYA_CPU0_BD3__DATA___S                          0
#define   DBG_PHYA_CPU0_BD3___M                  0xFFFFFFFF   
#define   DBG_PHYA_CPU0_BD3___S                                0

#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE             (0x00BEE0F8)
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE___RWC       QCSR_REG_RO    
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE___POR    0xE00FF003
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___POR 0xE00FF
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___POR 0x1
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___POR 0x1
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___M 0xFFFFF000
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___S              12
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___M 0x00000002
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___S               1
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___M 0x00000001
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___S               0
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE___M      0xFFFFF003   
#define   DBG_PHYA_CPU0_DBGDRAR_ROMBASE___S                    0

#define DBG_PHYA_CPU0_IDR                         (0x00BEE0FC)
#define   DBG_PHYA_CPU0_IDR___RWC                   QCSR_REG_RO    
#define   DBG_PHYA_CPU0_IDR___POR                0x24770011
#define   DBG_PHYA_CPU0_IDR__REVISION___POR      0x2
#define   DBG_PHYA_CPU0_IDR__JEDECBANK___POR     0x4
#define   DBG_PHYA_CPU0_IDR__JEDECCODE___POR     0x3B
#define   DBG_PHYA_CPU0_IDR__MEMAP___POR         0x1
#define   DBG_PHYA_CPU0_IDR__IDENVAL___POR       0x11
#define   DBG_PHYA_CPU0_IDR__REVISION___M        0xF0000000
#define   DBG_PHYA_CPU0_IDR__REVISION___S                     28
#define   DBG_PHYA_CPU0_IDR__JEDECBANK___M       0x0F000000
#define   DBG_PHYA_CPU0_IDR__JEDECBANK___S                    24
#define   DBG_PHYA_CPU0_IDR__JEDECCODE___M       0x00FE0000
#define   DBG_PHYA_CPU0_IDR__JEDECCODE___S                    17
#define   DBG_PHYA_CPU0_IDR__MEMAP___M           0x00010000
#define   DBG_PHYA_CPU0_IDR__MEMAP___S                        16
#define   DBG_PHYA_CPU0_IDR__IDENVAL___M         0x000000FF
#define   DBG_PHYA_CPU0_IDR__IDENVAL___S                       0
#define   DBG_PHYA_CPU0_IDR___M                  0xFFFF00FF   
#define   DBG_PHYA_CPU0_IDR___S                                0

#define DBG_ABT_HW_VERSION                        (0x00C31000)
#define   DBG_ABT_HW_VERSION___RWC                  QCSR_REG_RO    
#define   DBG_ABT_HW_VERSION___POR               0x10000000
#define   DBG_ABT_HW_VERSION__MAJOR___POR        0x1
#define   DBG_ABT_HW_VERSION__MINOR___POR        0x000
#define   DBG_ABT_HW_VERSION__STEP___POR         0x0000
#define   DBG_ABT_HW_VERSION__MAJOR___M          0xF0000000
#define   DBG_ABT_HW_VERSION__MAJOR___S                       28
#define   DBG_ABT_HW_VERSION__MINOR___M          0x0FFF0000
#define   DBG_ABT_HW_VERSION__MINOR___S                       16
#define   DBG_ABT_HW_VERSION__STEP___M           0x0000FFFF
#define   DBG_ABT_HW_VERSION__STEP___S                         0
#define   DBG_ABT_HW_VERSION___M                 0xFFFFFFFF   
#define   DBG_ABT_HW_VERSION___S                               0

#define DBG_ABT_INST_ID                           (0x00C31004)
#define   DBG_ABT_INST_ID___RWC                     QCSR_REG_RW    
#define   DBG_ABT_INST_ID___POR                  0x00000000
#define   DBG_ABT_INST_ID__INSTID___POR          0x00000000
#define   DBG_ABT_INST_ID__INSTID___M            0xFFFFFFFF
#define   DBG_ABT_INST_ID__INSTID___S                          0
#define   DBG_ABT_INST_ID___M                    0xFFFFFFFF   
#define   DBG_ABT_INST_ID___S                                  0

#define DBG_ABT_NUM_SLAVES                        (0x00C31008)
#define   DBG_ABT_NUM_SLAVES___RWC                  QCSR_REG_RO    
#define   DBG_ABT_NUM_SLAVES___POR               0x00000008
#define   DBG_ABT_NUM_SLAVES__NUMSLAVES___POR    0x8
#define   DBG_ABT_NUM_SLAVES__NUMSLAVES___M      0x0000003F
#define   DBG_ABT_NUM_SLAVES__NUMSLAVES___S                    0
#define   DBG_ABT_NUM_SLAVES___M                 0x0000003F   
#define   DBG_ABT_NUM_SLAVES___S                               0

#define DBG_ABT_TIMER_LOADVAL                     (0x00C3100C)
#define   DBG_ABT_TIMER_LOADVAL___RWC               QCSR_REG_RW    
#define   DBG_ABT_TIMER_LOADVAL___POR            0x000000FF
#define   DBG_ABT_TIMER_LOADVAL__LOADVAL___POR   0xFF
#define   DBG_ABT_TIMER_LOADVAL__LOADVAL___M     0x000000FF
#define   DBG_ABT_TIMER_LOADVAL__LOADVAL___S                   0
#define   DBG_ABT_TIMER_LOADVAL___M              0x000000FF   
#define   DBG_ABT_TIMER_LOADVAL___S                            0

#define DBG_ABT_TIMER_MODE                        (0x00C31010)
#define   DBG_ABT_TIMER_MODE___RWC                  QCSR_REG_RW    
#define   DBG_ABT_TIMER_MODE___POR               0x00000000
#define   DBG_ABT_TIMER_MODE__MODE___POR         0x0
#define   DBG_ABT_TIMER_MODE__MODE___M           0x00000001
#define   DBG_ABT_TIMER_MODE__MODE___S                         0
#define   DBG_ABT_TIMER_MODE___M                 0x00000001   
#define   DBG_ABT_TIMER_MODE___S                               0

#define DBG_ABT_INTR_STATUS                       (0x00C31014)
#define   DBG_ABT_INTR_STATUS___RWC                 QCSR_REG_RO    
#define   DBG_ABT_INTR_STATUS___POR              0x00000000
#define   DBG_ABT_INTR_STATUS__INTRSTATUS___POR  0x0
#define   DBG_ABT_INTR_STATUS__INTRSTATUS___M    0x00000001
#define   DBG_ABT_INTR_STATUS__INTRSTATUS___S                  0
#define   DBG_ABT_INTR_STATUS___M                0x00000001   
#define   DBG_ABT_INTR_STATUS___S                              0

#define DBG_ABT_INTR_CLEAR                        (0x00C31018)
#define   DBG_ABT_INTR_CLEAR___RWC                  QCSR_REG_WO    
#define   DBG_ABT_INTR_CLEAR___POR               0x00000000
#define   DBG_ABT_INTR_CLEAR__INTRCLEAR___POR    0x0
#define   DBG_ABT_INTR_CLEAR__INTRCLEAR___M      0x00000001
#define   DBG_ABT_INTR_CLEAR__INTRCLEAR___S                    0
#define   DBG_ABT_INTR_CLEAR___M                 0x00000001   
#define   DBG_ABT_INTR_CLEAR___S                               0

#define DBG_ABT_INTR_ENABLE                       (0x00C3101C)
#define   DBG_ABT_INTR_ENABLE___RWC                 QCSR_REG_RW    
#define   DBG_ABT_INTR_ENABLE___POR              0x00000000
#define   DBG_ABT_INTR_ENABLE__INTRENABLE___POR  0x0
#define   DBG_ABT_INTR_ENABLE__INTRENABLE___M    0x00000001
#define   DBG_ABT_INTR_ENABLE__INTRENABLE___S                  0
#define   DBG_ABT_INTR_ENABLE___M                0x00000001   
#define   DBG_ABT_INTR_ENABLE___S                              0

#define DBG_ABT_SYND_VALID                        (0x00C31020)
#define   DBG_ABT_SYND_VALID___RWC                  QCSR_REG_RO    
#define   DBG_ABT_SYND_VALID___POR               0x00000000
#define   DBG_ABT_SYND_VALID__SYNDVALID___POR    0x0
#define   DBG_ABT_SYND_VALID__SYNDVALID___M      0x00000001
#define   DBG_ABT_SYND_VALID__SYNDVALID___S                    0
#define   DBG_ABT_SYND_VALID___M                 0x00000001   
#define   DBG_ABT_SYND_VALID___S                               0

#define DBG_ABT_SYND_CLEAR                        (0x00C31024)
#define   DBG_ABT_SYND_CLEAR___RWC                  QCSR_REG_WO    
#define   DBG_ABT_SYND_CLEAR___POR               0x00000000
#define   DBG_ABT_SYND_CLEAR__SYNDCLEAR___POR    0x0
#define   DBG_ABT_SYND_CLEAR__SYNDCLEAR___M      0x00000001
#define   DBG_ABT_SYND_CLEAR__SYNDCLEAR___S                    0
#define   DBG_ABT_SYND_CLEAR___M                 0x00000001   
#define   DBG_ABT_SYND_CLEAR___S                               0

#define DBG_ABT_SYND_ID                           (0x00C31028)
#define   DBG_ABT_SYND_ID___RWC                     QCSR_REG_RO    
#define   DBG_ABT_SYND_ID___POR                  0x00000000
#define   DBG_ABT_SYND_ID__BID___POR             0x0
#define   DBG_ABT_SYND_ID__PID___POR             0x00
#define   DBG_ABT_SYND_ID__MID___POR             0x00
#define   DBG_ABT_SYND_ID__BID___M               0x0000E000
#define   DBG_ABT_SYND_ID__BID___S                            13
#define   DBG_ABT_SYND_ID__PID___M               0x00001F00
#define   DBG_ABT_SYND_ID__PID___S                             8
#define   DBG_ABT_SYND_ID__MID___M               0x000000FF
#define   DBG_ABT_SYND_ID__MID___S                             0
#define   DBG_ABT_SYND_ID___M                    0x0000FFFF   
#define   DBG_ABT_SYND_ID___S                                  0

#define DBG_ABT_SYND_ADDR0                        (0x00C3102C)
#define   DBG_ABT_SYND_ADDR0___RWC                  QCSR_REG_RO    
#define   DBG_ABT_SYND_ADDR0___POR               0x00000000
#define   DBG_ABT_SYND_ADDR0__SYNDADDR0___POR    0x00000000
#define   DBG_ABT_SYND_ADDR0__SYNDADDR0___M      0xFFFFFFFF
#define   DBG_ABT_SYND_ADDR0__SYNDADDR0___S                    0
#define   DBG_ABT_SYND_ADDR0___M                 0xFFFFFFFF   
#define   DBG_ABT_SYND_ADDR0___S                               0

#define DBG_ABT_SYND_ADDR1                        (0x00C31030)
#define   DBG_ABT_SYND_ADDR1___RWC                  QCSR_REG_RO    
#define   DBG_ABT_SYND_ADDR1___POR               0x00000000
#define   DBG_ABT_SYND_ADDR1__SYNDADDR1___POR    0x00000000
#define   DBG_ABT_SYND_ADDR1__SYNDADDR1___M      0xFFFFFFFF
#define   DBG_ABT_SYND_ADDR1__SYNDADDR1___S                    0
#define   DBG_ABT_SYND_ADDR1___M                 0xFFFFFFFF   
#define   DBG_ABT_SYND_ADDR1___S                               0

#define DBG_ABT_SYND_HREADY                       (0x00C31034)
#define   DBG_ABT_SYND_HREADY___RWC                 QCSR_REG_RO    
#define   DBG_ABT_SYND_HREADY___POR              0xFFFFFFFF
#define   DBG_ABT_SYND_HREADY__SYNDHREADY___POR  0xFFFFFFFF
#define   DBG_ABT_SYND_HREADY__SYNDHREADY___M    0xFFFFFFFF
#define   DBG_ABT_SYND_HREADY__SYNDHREADY___S                  0
#define   DBG_ABT_SYND_HREADY___M                0xFFFFFFFF   
#define   DBG_ABT_SYND_HREADY___S                              0


#define UMAC_NOC_BASE               (0x00140000)

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW (0x00140000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___POR 0x0001E93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH (0x00140004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW (0x00140008)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___POR 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___M 0x00000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW (0x00140010)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW (0x00140018)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW (0x00140020)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH (0x00140024)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW (0x00140028)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH (0x0014002C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW (0x00140030)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH (0x00140034)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW (0x00140038)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH (0x0014003C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW (0x00140080)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___POR 0x0001E93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH (0x00140084)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW (0x00140088)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___POR 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___M 0x00000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW (0x00140090)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW (0x00140098)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW (0x001400A0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH (0x001400A4)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW (0x001400A8)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH (0x001400AC)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW (0x001400B0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH (0x001400B4)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW (0x001400B8)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH (0x001400BC)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW (0x00140100)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___POR 0x0001E93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___POR 0x01
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___POR 0xE93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH (0x00140104)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW (0x00140108)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___POR 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___POR 0x1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___M 0x00000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW (0x00140110)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW (0x00140118)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW (0x00140120)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___M 0x00000070
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___M 0x0F3F7777   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH (0x00140124)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___M 0x00FF03FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW (0x00140128)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH (0x0014012C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___M 0x0003FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW (0x00140130)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH (0x00140134)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___M 0x0001FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW (0x00140138)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH (0x0014013C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW (0x00140200)
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___POR 0x000EEC22
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___POR 0xEC22
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH (0x00140204)
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW (0x00140240)
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___M 0x00002000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___S              13
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___M 0x00FDFD6F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW (0x00140248)
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___M 0x00002000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___S              13
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___M 0x00FDFD6F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW (0x00140400)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___POR 0x000E8DBE
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___POR 0x8DBE
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH (0x00140404)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW (0x00140480)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW (0x00140488)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW (0x00140490)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW (0x00140500)
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___M 0x00000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW (0x00140600)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___POR 0x0008317D
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___POR 0x317D
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH (0x00140604)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW (0x00140608)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___M 0x00003F37   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW (0x00140610)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW (0x00140618)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW (0x00140620)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW (0x00140640)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___M 0x00003303   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW (0x00140648)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___POR 0x00800400
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x400
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW (0x00140650)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___M 0x00003303   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW (0x00140658)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___POR 0x00800400
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x400
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW (0x00140700)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH (0x00140704)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW (0x00140708)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW (0x00140710)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW (0x00140718)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW (0x00140720)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW (0x00140780)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH (0x00140784)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW (0x00140788)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW (0x00140790)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW (0x00140798)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW (0x001407A0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW (0x00140800)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___POR 0x00087F1D
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___POR 0x7F1D
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH (0x00140804)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW (0x00140808)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW (0x00140810)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW (0x00140818)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW (0x00140820)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___M 0x1F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___M 0x001F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___M 0x00001F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___M 0x1F1F1F1F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW (0x00140880)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___POR 0x0008FDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH (0x00140884)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW (0x00140888)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___M 0x00000007   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW (0x00140890)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW (0x00140898)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW (0x001408A0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW (0x00140900)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___POR 0x00081500
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___POR 0x1500
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH (0x00140904)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW (0x00140908)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___M 0x00003F37   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW (0x00140910)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000007F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___M 0x0FFF007F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW (0x00140918)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW (0x00140920)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___M 0x3F000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___M 0x003F0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___M 0x00003F00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___M 0x0000003F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___M 0x3F3F3F3F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW (0x00140940)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___M 0x00003303   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW (0x00140948)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___POR 0x00800199
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x199
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW (0x00140950)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___M 0x00003303   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW (0x00140958)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___POR 0x00800199
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x199
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW     (0x00141000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___POR 0x000CE93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___POR 0x0C
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___POR 0xE93B
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH    (0x00141004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW    (0x00141008)
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW    (0x00141010)
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___M 0x0000007F
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___M 0x0000007F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW (0x00141018)
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW (0x00141400)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___POR 0x0003DBB2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xDBB2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH (0x00141404)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW (0x00141408)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW (0x00141410)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW (0x00141418)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW (0x00141420)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW (0x00141428)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH (0x0014142C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___S               8

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW (0x00141440)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW (0x00141448)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW (0x00141450)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW (0x00141458)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW (0x00141460)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW (0x00141468)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW (0x00141470)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW (0x00141478)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW (0x00141480)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00141520)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00141524)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00141528)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0014152C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW (0x00141538)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW (0x00141600)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___POR 0x0003CB09
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xCB09
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH (0x00141604)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW (0x00141608)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___M 0x0000033F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW (0x00141610)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW (0x00141618)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW (0x00141620)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___POR 0x00F00000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___M 0x0FFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW (0x00141628)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH (0x0014162C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___S               8

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW (0x00141640)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW (0x00141648)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW (0x00141650)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW (0x00141658)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW (0x00141660)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW (0x00141668)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW (0x00141670)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW (0x00141678)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW (0x00141680)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___M 0x000000FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00141720)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___S              10

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00141724)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00141728)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___S              10

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0014172C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW (0x00141738)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW (0x00142000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___POR 0x00122752
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___POR 0x12
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___POR 0x2752
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH (0x00142004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW (0x00142008)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___M 0x0000002F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW (0x00142010)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___M 0x80000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW (0x00142018)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___M 0x80000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW (0x00142020)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___M 0x80000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW (0x00142028)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___M 0x00000003
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___M 0x80000003   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW (0x00142120)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___S               6

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH (0x00142124)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW (0x00142128)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___S               6

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH (0x0014212C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW (0x00142138)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW (0x00142220)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___S               6

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH (0x00142224)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW (0x00142228)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___S               6

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH (0x0014222C)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW (0x00142238)
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW      (0x00143000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___POR 0x00023E6C
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___POR 0x02
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___POR 0x3E6C
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH     (0x00143004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW   (0x00143008)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___M 0x00000007   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW    (0x00143010)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW (0x00143018)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___M 0x0000001F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW   (0x00143020)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW  (0x00143028)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW  (0x00143030)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW (0x00143038)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW  (0x00143040)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___RWC QCSR_REG_WO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW   (0x00143048)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___M 0x00000001   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW (0x00143100)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW (0x00143140)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW (0x00143180)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW (0x001431C0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW (0x00143200)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW (0x00143240)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW (0x00143280)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW (0x001432C0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW (0x00143300)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW (0x00143340)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW (0x00143380)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW (0x001433C0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW (0x00143400)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW (0x00143440)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW (0x00143480)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___RWC QCSR_REG_RW    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___POR 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___POR 0x1F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___M 0x0000001F
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___M 0x0000071F   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW (0x001434C0)
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___M 0x0000FFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW (0x00144000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH (0x00144004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW (0x00144100)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW (0x00144200)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH (0x00144204)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW (0x00144300)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW (0x00144400)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH (0x00144404)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW (0x00144500)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW (0x00144600)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH (0x00144604)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW (0x00144700)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW (0x00144A00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH (0x00144A04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW (0x00144B00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW (0x00144C00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH (0x00144C04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW (0x00144D00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW (0x00145000)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH (0x00145004)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW (0x00145100)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW (0x00145400)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___POR 0x000E533C
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___POR 0x533C
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH (0x00145404)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW (0x00145500)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___M 0x00002000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___S              13
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___M 0x00003FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW (0x00145600)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___POR 0x000E4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH (0x00145604)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW (0x00145700)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH (0x00145704)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW (0x00145800)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___POR 0x000E4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH (0x00145804)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW (0x00145900)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH (0x00145904)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW (0x00145A00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___POR 0x000E4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH (0x00145A04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW (0x00145B00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH (0x00145B04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW (0x00145C00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___POR 0x000E4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH (0x00145C04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW (0x00145D00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH (0x00145D04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW (0x00145E00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___POR 0x000E4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___POR 0x4249
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH (0x00145E04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW (0x00145F00)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___S              31
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___S              30
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___S              29
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___S              28
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___S              27
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___S              26
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___S              25
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___S              24
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___M 0xFFFF1FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH (0x00145F04)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___S              23
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___S              22
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___S              21
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___S              20
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___S              19
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___S              18
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___S              17
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___S              15
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___S              14
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___M 0x00FFC0FF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW (0x00146200)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___POR 0x000EF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___S              16
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___M 0x00FFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH (0x00146204)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___M 0xFFFFFFFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___S               0

#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW (0x00146300)
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO    
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___POR 0x00000000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___S              12
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___S              11
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___S              10
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___S               9
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___S               8
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___S               7
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___S               6
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___S               5
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___S               4
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___S               3
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___S               2
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___S               1
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___S               0
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___M 0x00001FFF   
#define   UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___S               0


#define APB_TSLV_BASE               (0x00B40000)

#define APB_TSLV_ABT_HW_VERSION                   (0x00B40000)
#define   APB_TSLV_ABT_HW_VERSION___RWC             QCSR_REG_RO    
#define   APB_TSLV_ABT_HW_VERSION___POR          0x10000000
#define   APB_TSLV_ABT_HW_VERSION__MAJOR___POR   0x1
#define   APB_TSLV_ABT_HW_VERSION__MINOR___POR   0x000
#define   APB_TSLV_ABT_HW_VERSION__STEP___POR    0x0000
#define   APB_TSLV_ABT_HW_VERSION__MAJOR___M     0xF0000000
#define   APB_TSLV_ABT_HW_VERSION__MAJOR___S                  28
#define   APB_TSLV_ABT_HW_VERSION__MINOR___M     0x0FFF0000
#define   APB_TSLV_ABT_HW_VERSION__MINOR___S                  16
#define   APB_TSLV_ABT_HW_VERSION__STEP___M      0x0000FFFF
#define   APB_TSLV_ABT_HW_VERSION__STEP___S                    0
#define   APB_TSLV_ABT_HW_VERSION___M            0xFFFFFFFF   
#define   APB_TSLV_ABT_HW_VERSION___S                          0

#define APB_TSLV_ABT_INST_ID                      (0x00B40004)
#define   APB_TSLV_ABT_INST_ID___RWC                QCSR_REG_RW    
#define   APB_TSLV_ABT_INST_ID___POR             0x00000000
#define   APB_TSLV_ABT_INST_ID__INSTID___POR     0x00000000
#define   APB_TSLV_ABT_INST_ID__INSTID___M       0xFFFFFFFF
#define   APB_TSLV_ABT_INST_ID__INSTID___S                     0
#define   APB_TSLV_ABT_INST_ID___M               0xFFFFFFFF   
#define   APB_TSLV_ABT_INST_ID___S                             0

#define APB_TSLV_ABT_NUM_SLAVES                   (0x00B40008)
#define   APB_TSLV_ABT_NUM_SLAVES___RWC             QCSR_REG_RO    
#define   APB_TSLV_ABT_NUM_SLAVES___POR          0x00000009
#define   APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___POR 0x9
#define   APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___M 0x0000003F
#define   APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___S               0
#define   APB_TSLV_ABT_NUM_SLAVES___M            0x0000003F   
#define   APB_TSLV_ABT_NUM_SLAVES___S                          0

#define APB_TSLV_ABT_TIMER_LOADVAL                (0x00B4000C)
#define   APB_TSLV_ABT_TIMER_LOADVAL___RWC          QCSR_REG_RW    
#define   APB_TSLV_ABT_TIMER_LOADVAL___POR       0x000000FF
#define   APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___POR 0xFF
#define   APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___M 0x000000FF
#define   APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___S               0
#define   APB_TSLV_ABT_TIMER_LOADVAL___M         0x000000FF   
#define   APB_TSLV_ABT_TIMER_LOADVAL___S                       0

#define APB_TSLV_ABT_TIMER_MODE                   (0x00B40010)
#define   APB_TSLV_ABT_TIMER_MODE___RWC             QCSR_REG_RW    
#define   APB_TSLV_ABT_TIMER_MODE___POR          0x00000000
#define   APB_TSLV_ABT_TIMER_MODE__MODE___POR    0x0
#define   APB_TSLV_ABT_TIMER_MODE__MODE___M      0x00000001
#define   APB_TSLV_ABT_TIMER_MODE__MODE___S                    0
#define   APB_TSLV_ABT_TIMER_MODE___M            0x00000001   
#define   APB_TSLV_ABT_TIMER_MODE___S                          0

#define APB_TSLV_ABT_INTR_STATUS                  (0x00B40014)
#define   APB_TSLV_ABT_INTR_STATUS___RWC            QCSR_REG_RO    
#define   APB_TSLV_ABT_INTR_STATUS___POR         0x00000000
#define   APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___POR 0x0
#define   APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___M 0x00000001
#define   APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___S               0
#define   APB_TSLV_ABT_INTR_STATUS___M           0x00000001   
#define   APB_TSLV_ABT_INTR_STATUS___S                         0

#define APB_TSLV_ABT_INTR_CLEAR                   (0x00B40018)
#define   APB_TSLV_ABT_INTR_CLEAR___RWC             QCSR_REG_WO    
#define   APB_TSLV_ABT_INTR_CLEAR___POR          0x00000000
#define   APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___POR 0x0
#define   APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___M 0x00000001
#define   APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___S               0
#define   APB_TSLV_ABT_INTR_CLEAR___M            0x00000001   
#define   APB_TSLV_ABT_INTR_CLEAR___S                          0

#define APB_TSLV_ABT_INTR_ENABLE                  (0x00B4001C)
#define   APB_TSLV_ABT_INTR_ENABLE___RWC            QCSR_REG_RW    
#define   APB_TSLV_ABT_INTR_ENABLE___POR         0x00000000
#define   APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___POR 0x0
#define   APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___M 0x00000001
#define   APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___S               0
#define   APB_TSLV_ABT_INTR_ENABLE___M           0x00000001   
#define   APB_TSLV_ABT_INTR_ENABLE___S                         0

#define APB_TSLV_ABT_SYND_VALID                   (0x00B40020)
#define   APB_TSLV_ABT_SYND_VALID___RWC             QCSR_REG_RO    
#define   APB_TSLV_ABT_SYND_VALID___POR          0x00000000
#define   APB_TSLV_ABT_SYND_VALID__SYNDVALID___POR 0x0
#define   APB_TSLV_ABT_SYND_VALID__SYNDVALID___M 0x00000001
#define   APB_TSLV_ABT_SYND_VALID__SYNDVALID___S               0
#define   APB_TSLV_ABT_SYND_VALID___M            0x00000001   
#define   APB_TSLV_ABT_SYND_VALID___S                          0

#define APB_TSLV_ABT_SYND_CLEAR                   (0x00B40024)
#define   APB_TSLV_ABT_SYND_CLEAR___RWC             QCSR_REG_WO    
#define   APB_TSLV_ABT_SYND_CLEAR___POR          0x00000000
#define   APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___POR 0x0
#define   APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___M 0x00000001
#define   APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___S               0
#define   APB_TSLV_ABT_SYND_CLEAR___M            0x00000001   
#define   APB_TSLV_ABT_SYND_CLEAR___S                          0

#define APB_TSLV_ABT_SYND_ID                      (0x00B40028)
#define   APB_TSLV_ABT_SYND_ID___RWC                QCSR_REG_RO    
#define   APB_TSLV_ABT_SYND_ID___POR             0x00000000
#define   APB_TSLV_ABT_SYND_ID__BID___POR        0x0
#define   APB_TSLV_ABT_SYND_ID__PID___POR        0x00
#define   APB_TSLV_ABT_SYND_ID__MID___POR        0x00
#define   APB_TSLV_ABT_SYND_ID__BID___M          0x0000E000
#define   APB_TSLV_ABT_SYND_ID__BID___S                       13
#define   APB_TSLV_ABT_SYND_ID__PID___M          0x00001F00
#define   APB_TSLV_ABT_SYND_ID__PID___S                        8
#define   APB_TSLV_ABT_SYND_ID__MID___M          0x000000FF
#define   APB_TSLV_ABT_SYND_ID__MID___S                        0
#define   APB_TSLV_ABT_SYND_ID___M               0x0000FFFF   
#define   APB_TSLV_ABT_SYND_ID___S                             0

#define APB_TSLV_ABT_SYND_ADDR0                   (0x00B4002C)
#define   APB_TSLV_ABT_SYND_ADDR0___RWC             QCSR_REG_RO    
#define   APB_TSLV_ABT_SYND_ADDR0___POR          0x00000000
#define   APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___POR 0x00000000
#define   APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___M 0xFFFFFFFF
#define   APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___S               0
#define   APB_TSLV_ABT_SYND_ADDR0___M            0xFFFFFFFF   
#define   APB_TSLV_ABT_SYND_ADDR0___S                          0

#define APB_TSLV_ABT_SYND_ADDR1                   (0x00B40030)
#define   APB_TSLV_ABT_SYND_ADDR1___RWC             QCSR_REG_RO    
#define   APB_TSLV_ABT_SYND_ADDR1___POR          0x00000000
#define   APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___POR 0x00000000
#define   APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___M 0xFFFFFFFF
#define   APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___S               0
#define   APB_TSLV_ABT_SYND_ADDR1___M            0xFFFFFFFF   
#define   APB_TSLV_ABT_SYND_ADDR1___S                          0

#define APB_TSLV_ABT_SYND_HREADY                  (0x00B40034)
#define   APB_TSLV_ABT_SYND_HREADY___RWC            QCSR_REG_RO    
#define   APB_TSLV_ABT_SYND_HREADY___POR         0xFFFFFFFF
#define   APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___POR 0xFFFFFFFF
#define   APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___M 0xFFFFFFFF
#define   APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___S               0
#define   APB_TSLV_ABT_SYND_HREADY___M           0xFFFFFFFF   
#define   APB_TSLV_ABT_SYND_HREADY___S                         0


#define TOP_CMN_BASE                (0x00B50000)

#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION (0x00B50000)
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___POR 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___POR 0x000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___POR 0x0000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___M 0xF0000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___S              28
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___M 0x0FFF0000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___M 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___S               0

#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL         (0x00B50004)
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___RWC   QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___POR 0x0000
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___M 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___S               0
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___M  0x0000FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___S                0

#define TOP_CMN_WCSS_WCMN_R0_TRC_VID              (0x00B50010)
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID___RWC        QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID___POR     0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___M 0x0001E000
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___S              13
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___M 0x00001E00
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___S               9
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___M 0x000001E0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___S               5
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___M 0x0000001E
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___S               1
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___S               0
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID___M       0x0001FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_TRC_VID___S                     0

#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG       (0x00B50014)
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___S               0

#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL     (0x00B50018)
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___M 0x001C0000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___S              18
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___M 0x00030000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___S              16
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___S              15
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___M 0x00007000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___S              12
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___M 0x00000F80
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___S               7
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___M 0x00000070
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___S               4
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___M 0x0000000F
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___M 0x001FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___S               0

#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR (0x00B5001C)
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___M 0x0001FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___S               0

#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE          (0x00B50030)
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___RWC    QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___M   0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___S                 0

#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON          (0x00B50038)
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___RWC    QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___M 0xFF000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___S              24
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___M 0x00FF0000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___S              16
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___M 0x0000FF00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___S               8
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___M 0x000000FF
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___M   0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___S                 0

#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF         (0x00B5003C)
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___RWC   QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___M 0xFF000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___S              24
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___M 0x00FF0000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___S              16
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___M 0x0000FF00
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___S               8
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___M 0x000000FF
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___M  0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___S                0

#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON     (0x00B50040)
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___POR 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___POR 0x0000
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___POR 0xFFFF
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___M 0xFFFF0000
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___S              16
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___M 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___S               0

#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP      (0x00B50044)
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___POR 0x00002A80
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___S              17
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___S              16
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___S              15
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___S              14
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___S              13
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___S              12
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___S              11
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___S              10
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___S               9
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___S               8
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___S               7
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___S               6
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___S               5
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___S               4
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___S               3
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___S               2
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___S               1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___M 0x0003FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___S               0

#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP       (0x00B5004C)
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___POR 0x00002A80
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___S              17
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___S              16
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___S              15
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___S              14
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___S              13
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___S              12
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___S              11
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___S              10
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___S               9
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___S               8
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___S               7
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___S               6
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___S               5
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___S               4
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___S               3
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___S               2
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___S               1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___M 0x0003FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___S               0

#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION     (0x00B50054)
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___S               0

#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION    (0x00B50058)
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___S               0

#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG           (0x00B5005C)
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___RWC     QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___POR  0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___S               1
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___M    0x00000003   
#define   TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___S                  0

#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST         (0x00B50060)
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___RWC   QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___S               1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___M  0x00000003   
#define   TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___S                0

#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP        (0x00B5006C)
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___RWC  QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___S               1
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___M 0x00000003   
#define   TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___S               0

#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP        (0x00B50070)
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___RWC  QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___S               1
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___M 0x00000003   
#define   TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___S               0

#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL     (0x00B50074)
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___M 0x00000007
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___M 0x00000007   
#define   TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___S               0

#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR         (0x00B50078)
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___RWC   QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___M  0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___S                0

#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE   (0x00B5007C)
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0  (0x00B50080)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___POR 0x93F33C07
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x01
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___M 0x80000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___S              31
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___M 0x93F33FFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1  (0x00B50084)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___POR 0x00E07249
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___M 0x00E07249   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2  (0x00B50088)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___POR 0x0007FFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___M 0x0007FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3  (0x00B5008C)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___POR 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___POR 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4  (0x00B50090)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___POR 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___POR 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5  (0x00B50094)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___POR 0x3FFFFFC3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___POR 0xFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___M 0x3FFFFFC3   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0 (0x00B50098)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___M 0x80000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___S              31
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___M 0x93F33FFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1 (0x00B5009C)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___M 0x00E07249   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2 (0x00B500A0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___M 0x0007FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3 (0x00B500A4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4 (0x00B500A8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5 (0x00B500AC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___POR 0x000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___M 0x3FFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0 (0x00B500B0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___M 0x13F33FFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1 (0x00B500B4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___M 0x00007249   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2 (0x00B500B8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___M 0x0007FFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3 (0x00B500BC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4 (0x00B500C0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5 (0x00B500C4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___POR 0x000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___M 0x3FFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE (0x00B500C8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___S              30
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___M 0x20000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___S              29
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___M 0x08000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___S              27
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___M 0x04000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___S              26
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S              19
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___M 0x7FFFFE3B   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS (0x00B500CC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___S              30
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___M 0x20000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___S              29
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___M 0x08000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___S              27
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___M 0x04000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___S              26
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S              19
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___M 0x7FFFFE3B   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR (0x00B500D0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___S              30
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___S              28
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___M 0x08000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___S              27
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___M 0x04000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___S              26
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S              25
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S              23
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___S              20
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S              19
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___S               3
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___M 0x5FFFFE3F   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0 (0x00B500D4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___M 0x00000056   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___S               1

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1 (0x00B500D8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___M 0x01667FD5   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0 (0x00B500DC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___M 0x00000056   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___S               1

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1 (0x00B500E0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___M 0x01667FD5   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0 (0x00B500E4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___M 0x00000056   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___S               1

#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1 (0x00B500E8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S              24
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S              22
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S              21
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S               8
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S               7
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S               2
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___M 0x01667FD5   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES (0x00B500EC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES (0x00B500F0)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES (0x00B500F4)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES (0x00B500F8)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES (0x00B500FC)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES (0x00B50100)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS (0x00B50104)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS (0x00B50108)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS (0x00B5010C)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS (0x00B50110)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS (0x00B50114)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS (0x00B50118)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR (0x00B5011C)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR (0x00B50120)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR (0x00B50124)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR (0x00B50128)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR (0x00B5012C)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR (0x00B50130)
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___POR 0x00000
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___S               0
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___M 0x000FFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE (0x00B50148)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS (0x00B5014C)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR (0x00B50150)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE (0x00B50154)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___M 0x000003E0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___M 0x000783FF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR (0x00B50158)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___RWC QCSR_REG_WO    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___M 0x000003E0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___M 0x000783FF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS (0x00B501B0)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___M 0x0007801F   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___S               0

#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS (0x00B50200)
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___S               0

#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE (0x00B50204)
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___S               0
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___S               0

#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL (0x00B5020C)
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___POR 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___S               1
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___S               0
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___M 0x00000003   
#define   TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2 (0x00B50210)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3 (0x00B50214)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2 (0x00B50218)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3 (0x00B5021C)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2 (0x00B50220)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___S              17
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___S              16
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___S              15
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___S              12
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000400
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___S              10
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00000200
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S               9
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___S               8
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00000080
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S               7
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S               5
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00000010
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S               4
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00000008
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S               3
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S               2
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S               1
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___M 0x0007DFFF   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___S               0

#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3 (0x00B50224)
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___M 0x20000000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___S              29
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x1FF00000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S              20
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S              19
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00020000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              17
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              16
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000040
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S               6
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S               5
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___S               0
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___M 0x3FFF0061   
#define   TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___S               0

#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE     (0x00B50230)
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___POR 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___POR 0x0000FFFF
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___M 0xFFFFFFFF
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___S               0
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___M 0xFFFFFFFF   
#define   TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___S               0

#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS (0x00B5100C)
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___RWC QCSR_REG_RO    
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              23
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              22
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___S              19
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___S              16
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S              15
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___S               8
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___S               5
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___S               1
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___M 0x00CDF926   
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___S               1

#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR (0x00B51010)
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00800000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S              23
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00400000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S              22
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00080000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___S              19
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00040000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S              18
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___M 0x00010000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___S              16
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x00008000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S              15
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___M 0x00004000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___S              14
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___M 0x00002000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___S              13
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___M 0x00001000
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___S              12
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___M 0x00000800
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___S              11
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___M 0x00000100
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___S               8
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___M 0x00000020
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___S               5
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___M 0x00000004
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___S               2
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___M 0x00000002
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___S               1
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___S               0
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___M 0x00CDF927   
#define   TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___S               0

#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ  (0x00B51014)
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___POR 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___S               0
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___S               0

#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ (0x00B51018)
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___S               0
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___S               0

#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ     (0x00B5101C)
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___POR 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___S               0
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___S               0

#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ (0x00B51020)
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___POR 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___POR 0x1
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___S               0
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___S               0

#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ  (0x00B51024)
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___RWC QCSR_REG_RW    
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___POR 0x00000000
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___POR 0x0
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___M 0x00000001
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___S               0
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___M 0x00000001   
#define   TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___S               0


#define WCMN_CORE_BASE              (0x00B58000)

#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1    (0x00B58000)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___POR 0x00
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___POR 0x00000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___M 0x80000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___S              31
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___M 0x40000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___S              30
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___M 0x3C000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___S              26
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___M 0x03F00000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___S              20
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___M 0x000FFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2    (0x00B5800C)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___POR 0x00
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___POR 0x0000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___M 0xC0000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___S              30
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___M 0x20000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___S              29
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___M 0x1C000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___S              26
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___M 0x03FC0000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___S              18
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___M 0x00020000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___S              17
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___M 0x0001E000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___S              13
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___M 0x00001FFF
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___S               0

#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL      (0x00B58020)
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___POR 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___POR 0x1
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___M 0x00000020
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___S               5
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___M 0x00000010
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___S               4
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___M 0x00000008
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___S               3
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___M 0x00000004
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___S               2
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___M 0x0000003F   
#define   WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC          (0x00B58024)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___RWC    QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___M   0x00000003   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___S                 0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC          (0x00B58028)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___RWC    QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___M   0x00000003   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___S                 0

#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL           (0x00B5802C)
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___RWC     QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___POR  0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___M 0x00070000
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___S              16
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___M 0x0000E000
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___S              13
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___M 0x00001C00
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___S              10
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___M 0x00000300
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___S               8
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___M 0x000000C0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___S               6
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___M 0x00000030
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___S               4
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___M 0x00000008
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___S               3
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___M 0x00000004
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___S               2
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___S               1
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___S               0
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___M    0x0007FFFF   
#define   WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___S                  0

#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL (0x00B58034)
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___POR 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___POR 0x1
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___M 0x00000010
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___S               4
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___M 0x00000008
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___S               3
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___M 0x00000004
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___S               2
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___S               1
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___S               0
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___M 0x0000001F   
#define   WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE   (0x00B581B4)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___M 0x00000008
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___S               3
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___M 0x00000004
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___S               2
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___M 0x0000000F   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR    (0x00B581BC)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___M 0x00000008
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___S               3
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___M 0x00000004
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___S               2
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___M 0x0000000F   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___S               0

#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET     (0x00B58208)
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___POR 0x00000003
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___POR 0x1
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___POR 0x1
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___M 0x00000002
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___S               1
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___M 0x00000003   
#define   WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0 (0x00B58228)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___S               0

#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1 (0x00B5822C)
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___S               0

#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0           (0x00B58230)
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0___RWC     QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0___POR  0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___S               0
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0___M    0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_0___S                  0

#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1           (0x00B58234)
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1___RWC     QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1___POR  0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___S               0
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1___M    0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_1___S                  0

#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2           (0x00B58238)
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2___RWC     QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2___POR  0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___S               0
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2___M    0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_2___S                  0

#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3           (0x00B5823C)
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3___RWC     QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3___POR  0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___S               0
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3___M    0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_S_PARE_3___S                  0

#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n(n) (0x00B58240+0x4*(n))
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_nMIN 0    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_nMAX 31   
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_ELEM 32   
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___S               0
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0 (0x00B58240)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1 (0x00B58244)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2 (0x00B58248)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3 (0x00B5824C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4 (0x00B58250)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5 (0x00B58254)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6 (0x00B58258)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7 (0x00B5825C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8 (0x00B58260)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9 (0x00B58264)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10 (0x00B58268)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11 (0x00B5826C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12 (0x00B58270)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13 (0x00B58274)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14 (0x00B58278)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15 (0x00B5827C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16 (0x00B58280)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17 (0x00B58284)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18 (0x00B58288)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19 (0x00B5828C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20 (0x00B58290)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21 (0x00B58294)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22 (0x00B58298)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23 (0x00B5829C)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24 (0x00B582A0)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25 (0x00B582A4)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26 (0x00B582A8)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27 (0x00B582AC)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28 (0x00B582B0)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29 (0x00B582B4)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30 (0x00B582B8)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30__VAL___S               0
#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31 (0x00B582BC)
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31__VAL___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31__VAL___S               0

#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT      (0x00B582C0)
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___POR 0x0
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___M 0x00000001
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___S               0
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___M 0x00000001   
#define   WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___S               0

#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG      (0x00B58880)
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___RWC QCSR_REG_RW    
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___POR 0x00000000
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___M 0xFFFFFFFF
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___S               0
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___M 0xFFFFFFFF   
#define   WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___S               0


#define WFSS_PMM_BASE               (0x00B60000)

#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR (0x00B60000)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___POR 0x00000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___M 0x0001FFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___M 0x0001FFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY      (0x00B60004)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___M 0x0000FFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1 (0x00B60008)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___POR 0x00000781
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___POR 0x0F
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___M 0x80000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___S              31
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___M 0x7FFF8000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___S              15
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___M 0x00007F80
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___S               7
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___S               6
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___S               5
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD (0x00B6000C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___POR 0x000F00C8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___POR 0x0F
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___POR 0x00C8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___M 0x00FF0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___M 0x00FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT (0x00B60010)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___POR 0x000003E8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___POR 0x3E8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___M 0x000003FF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS (0x00B60014)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___POR 0x0101004E
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___POR 0x40
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___POR 0x40
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___POR 0x04E
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___M 0x04000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___S              26
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___M 0x03FC0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___S              18
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___M 0x0003FC00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___M 0x07FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY (0x00B60018)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___POR 0x00010019
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___POR 0x0019
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___M 0x00010000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___M 0x0001FFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS (0x00B6001C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___M 0x00000007
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___M 0x0000000F   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2 (0x00B60020)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___POR 0x00001080
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___M 0x00020000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___S              17
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___M 0x00010000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___M 0x00008000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___S              15
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___M 0x00004000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___S              14
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___M 0x00002000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___S              13
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___S              12
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___S              11
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___S               9
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___S               8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___S               7
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___M 0x00000070
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___M 0x0003FFFE   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___S               1

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3 (0x00B60024)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___S              12
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___M 0x00000FFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___M 0x00001FFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING (0x00B60028)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___M 0x0000FFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS (0x00B6002C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS (0x00B60030)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS (0x00B60034)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS (0x00B60038)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS (0x00B6003C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS (0x00B60040)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 (0x00B60044)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___POR 0x00010801
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___POR 0x00010801
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2 (0x00B60048)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___M 0x00C00000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___S              22
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___M 0x00200000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___S              21
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___M 0x00100000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___S              20
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___M 0x000FFC00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___M 0x00FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3 (0x00B6004C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___M 0x3FF00000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___S              20
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___M 0x000FFC00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___M 0x3FFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4 (0x00B60050)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___POR 0x000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___M 0x80000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___S              31
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___M 0x40000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___S              30
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___M 0x3FF00000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___S              20
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___M 0x000FFC00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1 (0x00B60054)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2 (0x00B60058)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3 (0x00B6005C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE (0x00B60060)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___M 0x0003E000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___S              13
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___S              12
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___S              11
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___S               9
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___M 0x000001F0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___M 0x0003FFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY  (0x00B60064)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___POR 0x0003FC03
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___POR 0x0FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___POR 0x003
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___M 0x000FFC00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___S              10
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG     (0x00B60068)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY  (0x00B6006C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___POR 0x00002000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___POR 0x02000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___M 0x000FFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY   (0x00B60070)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___POR 0x00002000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___POR 0x02000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___M 0x000FFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1  (0x00B60074)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___S               2
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___S               1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___M 0x00000007   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1 (0x00B60078)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___POR 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___POR 0x010
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___M 0x000003FF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN (0x00B6007C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___POR 0x0000003F
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___S               5
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___M 0x0000003F   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___S               0

#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK (0x00B60080)
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___POR 0x00000334
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___POR 0x00334
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___M 0x000FFFFF
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE             (0x00B60084)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___RWC       QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___POR    0x00000005
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___POR 0x05
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___S               8
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___M 0x000000FF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___M      0x000001FF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___S                    0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE (0x00B60088)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___POR 0x00000003
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___M 0x0000001F   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S        (0x00B6008C)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___RWC  QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___S               1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___M 0x00000002   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___S               1

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT (0x00B60090)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___S               4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___S               3
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___S               2
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___M 0x0000001F   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1   (0x00B60098)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___M 0xFFFF0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2   (0x00B6009C)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___M 0xFFFF0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR  (0x00B600A0)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR (0x00B600A4)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S            (0x00B600A8)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___RWC      QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___POR   0x00000148
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___POR 0x0A4
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___M 0x000007FE
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___S               1
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___M     0x000007FF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___S                   0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3       (0x00B600AC)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___POR 0x00000028
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___POR 0x28
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___S               9
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___S               8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___M 0x000000FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___M 0x000003FF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U (0x00B600B0)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L (0x00B600B4)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY (0x00B600B8)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___M 0x00080000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___S              19
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___M 0x00040000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___S              18
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___M 0x00020000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___S              17
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___M 0x00010000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___M 0x0000FF00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___S               8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___M 0x000000FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT   (0x00B600BC)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___POR 0x00190019
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___POR 0x0019
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___POR 0x0019
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___M 0xFFFF0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___M 0x0000FFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL             (0x00B600C0)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___RWC       QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___POR    0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___S               9
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___S               8
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___S               7
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___S               6
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___S               5
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___S               4
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___M 0x0000000F
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___M      0x000003FF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___S                    0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1 (0x00B600C4)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___POR 0x00000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___M 0x000FFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2 (0x00B600C8)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___POR 0x00000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___M 0x000FFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___M 0x000FFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___S               0

#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL          (0x00B600CC)
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___RWC    QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___POR 0x00000077
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___POR 0x077
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___S              12
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___S              11
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___S              10
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___M 0x000003FF
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___S               0
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___M   0x00001FFF   
#define   WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___S                 0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG        (0x00B600D0)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___RWC  QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1   (0x00B600D4)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___POR 0x00000400
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___M 0x80000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___S              31
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___M 0x40000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___S              30
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___M 0x20000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___S              29
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___M 0x10000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___S              28
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___M 0x00004000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___S              14
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___M 0x00002000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___S              13
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___S              12
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___S              11
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___S              10
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___S               9
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___S               8
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___S               7
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___S               6
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___S               5
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___S               4
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___S               3
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___S               2
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___S               1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___M 0xF0007FFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2    (0x00B600D8)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___POR 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___POR 0x0001
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___M 0x00020000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___S              17
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___M 0x00010000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___S              16
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___M 0x00007FFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___M 0x00037FFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA      (0x00B600DC)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB (0x00B600E0)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB (0x00B600E4)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG              (0x00B600E8)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG___RWC        QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG___POR     0x0000000E
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___S               3
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___S               2
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___S               1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG___M       0x0000000F   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_CFG___S                     0

#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS           (0x00B600EC)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___RWC     QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___POR  0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___S               1
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___M    0x00000003   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___S                  0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF (0x00B600F0)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___M 0xFFFE0000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___S              17
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___M 0x0001FE00
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___S               9
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___S               8
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___M 0x000000FF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___S               0

#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL  (0x00B600F4)
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___POR 0x00019000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___POR 0x019000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___M 0x01000000
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___S              24
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___M 0x00FFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___M 0x01FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0 (0x00B600F8)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1 (0x00B600FC)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2 (0x00B60100)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3 (0x00B60104)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4 (0x00B60108)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5 (0x00B6010C)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6 (0x00B60110)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7 (0x00B60114)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8 (0x00B60118)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___S               0

#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9 (0x00B6011C)
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___S               0
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0 (0x00B62000)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1 (0x00B62004)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0 (0x00B62008)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1 (0x00B6200C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L (0x00B62010)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H (0x00B62014)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___POR 0xDEADC0DE
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L (0x00B62018)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H (0x00B6201C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1    (0x00B62020)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___POR 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___POR 0x1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___M 0x00020000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___S              17
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___M 0x00010000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___S              16
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___M 0x00008000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___S              15
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___M 0x00004000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___S              14
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___M 0x00002000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___S              13
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___S              12
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___S              11
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___S              10
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___S               9
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___S               8
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___S               6
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___M 0x0003FFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1 (0x00B62024)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___POR 0x000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___M 0x00FFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___M 0x00FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2 (0x00B62028)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___POR 0x00
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___M 0x000000FF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___M 0x000000FF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL (0x00B6202C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___S               6
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___M 0x000000FF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___S               0

#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L    (0x00B62030)
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___S               0

#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H    (0x00B62034)
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___S               0

#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL (0x00B62038)
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___S               7
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___S               6
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___S               5
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___S               4
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___S               3
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___S               2
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___S               1
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___S               0
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___M 0x000000FF   
#define   WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR          (0x00B6203C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___RWC    QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___M 0x00001000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___S              12
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___S              11
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___S              10
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___S               9
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___S               8
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___S               6
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___M   0x00001FFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___S                 0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L  (0x00B62040)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H  (0x00B62044)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK     (0x00B62048)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___M 0x00001FFF
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___M 0x00001FFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK (0x00B6204C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___M 0x00000001   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT (0x00B62050)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___M 0x0000003F   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS (0x00B62054)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___M 0x00000800
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___S              11
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___M 0x00000400
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___S              10
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___S               9
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___S               8
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___S               6
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___M 0x00000FFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___S               0

#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL        (0x00B62058)
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___RWC  QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___S               2
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___S               1
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___S               0
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___M 0x00000007   
#define   WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP (0x00B6205C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___M 0x0000000F   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS (0x00B62060)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___M 0x0000003F   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___S               0

#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT (0x00B62064)
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___S               8
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___M 0x0000000F
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___S               0
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___M 0x0000010F   
#define   WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___S               0

#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1        (0x00B62068)
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___RWC  QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___S               4
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___S               3
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___S               2
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___S               1
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___M 0x0000001F   
#define   WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1      (0x00B6206C)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___RWC QCSR_REG_RO    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___M 0x00000070
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___M 0x0000000E
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___M 0x000000FF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___S               0

#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2       (0x00B62070)
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___POR 0x0000
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___POR 0x0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___M 0x03FFFC00
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___S              10
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___M 0x00000200
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___S               9
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___M 0x00000100
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___S               8
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___M 0x00000080
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___S               7
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___M 0x00000040
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___S               6
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___M 0x00000020
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___S               5
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___M 0x00000010
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___S               4
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___M 0x00000008
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___S               3
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___M 0x00000004
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___S               2
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___M 0x00000002
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___S               1
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___M 0x00000001
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___S               0
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___M 0x03FFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___S               0

#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0 (0x00B62074)
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW    
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___POR 0x00000000
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___M 0xFFFFFFFF
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___S               0
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF   
#define   WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___S               0


#define PMM_TOP_BASE                (0x00B70000)

#define PMM_TOP_HW_VERSION                        (0x00B70000)
#define   PMM_TOP_HW_VERSION___RWC                  QCSR_REG_RO    
#define   PMM_TOP_HW_VERSION___POR               0x50080000
#define   PMM_TOP_HW_VERSION__MAJOR___POR        0x5
#define   PMM_TOP_HW_VERSION__MINOR___POR        0x008
#define   PMM_TOP_HW_VERSION__STEP___POR         0x0000
#define   PMM_TOP_HW_VERSION__MAJOR___M          0xF0000000
#define   PMM_TOP_HW_VERSION__MAJOR___S                       28
#define   PMM_TOP_HW_VERSION__MINOR___M          0x0FFF0000
#define   PMM_TOP_HW_VERSION__MINOR___S                       16
#define   PMM_TOP_HW_VERSION__STEP___M           0x0000FFFF
#define   PMM_TOP_HW_VERSION__STEP___S                         0
#define   PMM_TOP_HW_VERSION___M                 0xFFFFFFFF   
#define   PMM_TOP_HW_VERSION___S                               0

#define PMM_TOP_WCSS_HM_VERSION                   (0x00B70004)
#define   PMM_TOP_WCSS_HM_VERSION___RWC             QCSR_REG_RO    
#define   PMM_TOP_WCSS_HM_VERSION___POR          0x00000000
#define   PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___POR 0x00000000
#define   PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___M 0xFFFFFFFF
#define   PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___S               0
#define   PMM_TOP_WCSS_HM_VERSION___M            0xFFFFFFFF   
#define   PMM_TOP_WCSS_HM_VERSION___S                          0

#define PMM_TOP_PMM_TOP_VERSION                   (0x00B70008)
#define   PMM_TOP_PMM_TOP_VERSION___RWC             QCSR_REG_RO    
#define   PMM_TOP_PMM_TOP_VERSION___POR          0x00000000
#define   PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___POR 0x00000000
#define   PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___M 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___S               0
#define   PMM_TOP_PMM_TOP_VERSION___M            0xFFFFFFFF   
#define   PMM_TOP_PMM_TOP_VERSION___S                          0

#define PMM_TOP_CFG                               (0x00B7000C)
#define   PMM_TOP_CFG___RWC                         QCSR_REG_RW    
#define   PMM_TOP_CFG___POR                      0x00000000
#define   PMM_TOP_CFG__WCSS_LPI_MODE___POR       0x0
#define   PMM_TOP_CFG__RF_XO_MODE___POR          0x0
#define   PMM_TOP_CFG__WARM_BOOT___POR           0x0
#define   PMM_TOP_CFG__WCSS_LPI_MODE___M         0x00000008
#define   PMM_TOP_CFG__WCSS_LPI_MODE___S                       3
#define   PMM_TOP_CFG__RF_XO_MODE___M            0x00000006
#define   PMM_TOP_CFG__RF_XO_MODE___S                          1
#define   PMM_TOP_CFG__WARM_BOOT___M             0x00000001
#define   PMM_TOP_CFG__WARM_BOOT___S                           0
#define   PMM_TOP_CFG___M                        0x0000000F   
#define   PMM_TOP_CFG___S                                      0

#define PMM_TOP_ROOT_CLK_ENABLE                   (0x00B70010)
#define   PMM_TOP_ROOT_CLK_ENABLE___RWC             QCSR_REG_RW    
#define   PMM_TOP_ROOT_CLK_ENABLE___POR          0x00006610
#define   PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___POR 0x1
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___POR 0x1
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___POR 0x1
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___POR 0x1
#define   PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___POR 0x1
#define   PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___M 0x00004000
#define   PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___S              14
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___M 0x00002000
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___S              13
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___M 0x00000400
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___S              10
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___M 0x00000200
#define   PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___S               9
#define   PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___M 0x00000010
#define   PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___S               4
#define   PMM_TOP_ROOT_CLK_ENABLE___M            0x00006610   
#define   PMM_TOP_ROOT_CLK_ENABLE___S                          4

#define PMM_TOP_CLKGATE_DISABLE                   (0x00B70014)
#define   PMM_TOP_CLKGATE_DISABLE___RWC             QCSR_REG_RW    
#define   PMM_TOP_CLKGATE_DISABLE___POR          0x00000000
#define   PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___POR 0x0
#define   PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___M 0x00800000
#define   PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___S              23
#define   PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___M 0x00400000
#define   PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___S              22
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___M 0x00200000
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___S              21
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___M 0x00100000
#define   PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___S              20
#define   PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___M 0x00008000
#define   PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___S              15
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___M 0x00002000
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___S              13
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___M 0x00001000
#define   PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___S              12
#define   PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___M 0x00000080
#define   PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___S               7
#define   PMM_TOP_CLKGATE_DISABLE___M            0x00F0B080   
#define   PMM_TOP_CLKGATE_DISABLE___S                          7

#define PMM_TOP_SOFT_RESET                        (0x00B70018)
#define   PMM_TOP_SOFT_RESET___RWC                  QCSR_REG_RW    
#define   PMM_TOP_SOFT_RESET___POR               0x00000000
#define   PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___POR 0x0
#define   PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___POR 0x0
#define   PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___POR 0x0
#define   PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___POR 0x0
#define   PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___M 0x00002000
#define   PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___S              13
#define   PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___M 0x00000200
#define   PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___S               9
#define   PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___M 0x00000100
#define   PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___S               8
#define   PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___M 0x00000010
#define   PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___S               4
#define   PMM_TOP_SOFT_RESET___M                 0x00002310   
#define   PMM_TOP_SOFT_RESET___S                               4

#define PMM_TOP_PMU_TESTBUS_CTL                   (0x00B7001C)
#define   PMM_TOP_PMU_TESTBUS_CTL___RWC             QCSR_REG_RW    
#define   PMM_TOP_PMU_TESTBUS_CTL___POR          0x0000000F
#define   PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___POR 0x0
#define   PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___POR 0x0
#define   PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___POR 0xF
#define   PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___M 0x00000100
#define   PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___S               8
#define   PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___M 0x000000F0
#define   PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___S               4
#define   PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___M 0x0000000F
#define   PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___S               0
#define   PMM_TOP_PMU_TESTBUS_CTL___M            0x000001FF   
#define   PMM_TOP_PMU_TESTBUS_CTL___S                          0

#define PMM_TOP_PMU_TESTBUS_STS                   (0x00B70020)
#define   PMM_TOP_PMU_TESTBUS_STS___RWC             QCSR_REG_RO    
#define   PMM_TOP_PMU_TESTBUS_STS___POR          0x00000000
#define   PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___POR 0x00000000
#define   PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___M 0xFFFFFFFF
#define   PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___S               0
#define   PMM_TOP_PMU_TESTBUS_STS___M            0xFFFFFFFF   
#define   PMM_TOP_PMU_TESTBUS_STS___S                          0

#define PMM_TOP_TESTBUS_CTL                       (0x00B70024)
#define   PMM_TOP_TESTBUS_CTL___RWC                 QCSR_REG_RW    
#define   PMM_TOP_TESTBUS_CTL___POR              0x00000000
#define   PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___POR 0x0
#define   PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___POR 0x0
#define   PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___POR 0x0
#define   PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___POR 0x00000
#define   PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___M 0x80000000
#define   PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___S              31
#define   PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___M 0x40000000
#define   PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___S              30
#define   PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___M 0x00700000
#define   PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___S              20
#define   PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___M   0x0007FFFF
#define   PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___S                 0
#define   PMM_TOP_TESTBUS_CTL___M                0xC077FFFF   
#define   PMM_TOP_TESTBUS_CTL___S                              0

#define PMM_TOP_TESTBUS_STS                       (0x00B70028)
#define   PMM_TOP_TESTBUS_STS___RWC                 QCSR_REG_RO    
#define   PMM_TOP_TESTBUS_STS___POR              0x00000000
#define   PMM_TOP_TESTBUS_STS__TESTBUS_STS___POR 0x00000000
#define   PMM_TOP_TESTBUS_STS__TESTBUS_STS___M   0xFFFFFFFF
#define   PMM_TOP_TESTBUS_STS__TESTBUS_STS___S                 0
#define   PMM_TOP_TESTBUS_STS___M                0xFFFFFFFF   
#define   PMM_TOP_TESTBUS_STS___S                              0

#define PMM_TOP_WDOG1_RESET                       (0x00B7002C)
#define   PMM_TOP_WDOG1_RESET___RWC                 QCSR_REG_WO    
#define   PMM_TOP_WDOG1_RESET___POR              0x00000000
#define   PMM_TOP_WDOG1_RESET__WDOG_RESET___POR  0x0
#define   PMM_TOP_WDOG1_RESET__WDOG_RESET___M    0x00000001
#define   PMM_TOP_WDOG1_RESET__WDOG_RESET___S                  0
#define   PMM_TOP_WDOG1_RESET___M                0x00000001   
#define   PMM_TOP_WDOG1_RESET___S                              0

#define PMM_TOP_WDOG1_CTL                         (0x00B70030)
#define   PMM_TOP_WDOG1_CTL___RWC                   QCSR_REG_RW    
#define   PMM_TOP_WDOG1_CTL___POR                0x00000000
#define   PMM_TOP_WDOG1_CTL__ENABLE___POR        0x0
#define   PMM_TOP_WDOG1_CTL__ENABLE___M          0x00000001
#define   PMM_TOP_WDOG1_CTL__ENABLE___S                        0
#define   PMM_TOP_WDOG1_CTL___M                  0x00000001   
#define   PMM_TOP_WDOG1_CTL___S                                0

#define PMM_TOP_WDOG1_STATUS                      (0x00B70034)
#define   PMM_TOP_WDOG1_STATUS___RWC                QCSR_REG_RW    
#define   PMM_TOP_WDOG1_STATUS___POR             0x00000000
#define   PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___POR 0x0
#define   PMM_TOP_WDOG1_STATUS__WDOG_COUNT___POR 0x00000
#define   PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___POR 0x0
#define   PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___M 0x80000000
#define   PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___S              31
#define   PMM_TOP_WDOG1_STATUS__WDOG_COUNT___M   0x001FFFFE
#define   PMM_TOP_WDOG1_STATUS__WDOG_COUNT___S                 1
#define   PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___M 0x00000001
#define   PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___S               0
#define   PMM_TOP_WDOG1_STATUS___M               0x801FFFFF   
#define   PMM_TOP_WDOG1_STATUS___S                             0

#define PMM_TOP_WDOG1_BITE_TIME                   (0x00B70038)
#define   PMM_TOP_WDOG1_BITE_TIME___RWC             QCSR_REG_RW    
#define   PMM_TOP_WDOG1_BITE_TIME___POR          0x000FFFFF
#define   PMM_TOP_WDOG1_BITE_TIME__DATA___POR    0xFFFFF
#define   PMM_TOP_WDOG1_BITE_TIME__DATA___M      0x000FFFFF
#define   PMM_TOP_WDOG1_BITE_TIME__DATA___S                    0
#define   PMM_TOP_WDOG1_BITE_TIME___M            0x000FFFFF   
#define   PMM_TOP_WDOG1_BITE_TIME___S                          0

#define PMM_TOP_WDOG1_TEST_LOAD                   (0x00B7003C)
#define   PMM_TOP_WDOG1_TEST_LOAD___RWC             QCSR_REG_WO    
#define   PMM_TOP_WDOG1_TEST_LOAD___POR          0x00000000
#define   PMM_TOP_WDOG1_TEST_LOAD__LOAD___POR    0x00000000
#define   PMM_TOP_WDOG1_TEST_LOAD__LOAD___M      0xFFFFFFFF
#define   PMM_TOP_WDOG1_TEST_LOAD__LOAD___S                    0
#define   PMM_TOP_WDOG1_TEST_LOAD___M            0xFFFFFFFF   
#define   PMM_TOP_WDOG1_TEST_LOAD___S                          0

#define PMM_TOP_WDOG1_TEST                        (0x00B70040)
#define   PMM_TOP_WDOG1_TEST___RWC                  QCSR_REG_RW    
#define   PMM_TOP_WDOG1_TEST___POR               0x00000000
#define   PMM_TOP_WDOG1_TEST__SYNC_STATUS___POR  0x0
#define   PMM_TOP_WDOG1_TEST__LOAD_VALUE___POR   0x00000
#define   PMM_TOP_WDOG1_TEST__SYNC_STATUS___M    0x00100000
#define   PMM_TOP_WDOG1_TEST__SYNC_STATUS___S                 20
#define   PMM_TOP_WDOG1_TEST__LOAD_VALUE___M     0x000FFFFF
#define   PMM_TOP_WDOG1_TEST__LOAD_VALUE___S                   0
#define   PMM_TOP_WDOG1_TEST___M                 0x001FFFFF   
#define   PMM_TOP_WDOG1_TEST___S                               0

#define PMM_TOP_WDOG2_RESET                       (0x00B70044)
#define   PMM_TOP_WDOG2_RESET___RWC                 QCSR_REG_WO    
#define   PMM_TOP_WDOG2_RESET___POR              0x00000000
#define   PMM_TOP_WDOG2_RESET__WDOG_RESET___POR  0x0
#define   PMM_TOP_WDOG2_RESET__WDOG_RESET___M    0x00000001
#define   PMM_TOP_WDOG2_RESET__WDOG_RESET___S                  0
#define   PMM_TOP_WDOG2_RESET___M                0x00000001   
#define   PMM_TOP_WDOG2_RESET___S                              0

#define PMM_TOP_WDOG2_CTL                         (0x00B70048)
#define   PMM_TOP_WDOG2_CTL___RWC                   QCSR_REG_RW    
#define   PMM_TOP_WDOG2_CTL___POR                0x00000000
#define   PMM_TOP_WDOG2_CTL__ENABLE___POR        0x0
#define   PMM_TOP_WDOG2_CTL__ENABLE___M          0x00000001
#define   PMM_TOP_WDOG2_CTL__ENABLE___S                        0
#define   PMM_TOP_WDOG2_CTL___M                  0x00000001   
#define   PMM_TOP_WDOG2_CTL___S                                0

#define PMM_TOP_WDOG2_STATUS                      (0x00B7004C)
#define   PMM_TOP_WDOG2_STATUS___RWC                QCSR_REG_RW    
#define   PMM_TOP_WDOG2_STATUS___POR             0x00000000
#define   PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___POR 0x0
#define   PMM_TOP_WDOG2_STATUS__WDOG_COUNT___POR 0x00000
#define   PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___POR 0x0
#define   PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___M 0x80000000
#define   PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___S              31
#define   PMM_TOP_WDOG2_STATUS__WDOG_COUNT___M   0x001FFFFE
#define   PMM_TOP_WDOG2_STATUS__WDOG_COUNT___S                 1
#define   PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___M 0x00000001
#define   PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___S               0
#define   PMM_TOP_WDOG2_STATUS___M               0x801FFFFF   
#define   PMM_TOP_WDOG2_STATUS___S                             0

#define PMM_TOP_WDOG2_BITE_TIME                   (0x00B70050)
#define   PMM_TOP_WDOG2_BITE_TIME___RWC             QCSR_REG_RW    
#define   PMM_TOP_WDOG2_BITE_TIME___POR          0x000FFFFF
#define   PMM_TOP_WDOG2_BITE_TIME__DATA___POR    0xFFFFF
#define   PMM_TOP_WDOG2_BITE_TIME__DATA___M      0x000FFFFF
#define   PMM_TOP_WDOG2_BITE_TIME__DATA___S                    0
#define   PMM_TOP_WDOG2_BITE_TIME___M            0x000FFFFF   
#define   PMM_TOP_WDOG2_BITE_TIME___S                          0

#define PMM_TOP_WDOG2_TEST_LOAD                   (0x00B70054)
#define   PMM_TOP_WDOG2_TEST_LOAD___RWC             QCSR_REG_WO    
#define   PMM_TOP_WDOG2_TEST_LOAD___POR          0x00000000
#define   PMM_TOP_WDOG2_TEST_LOAD__LOAD___POR    0x00000000
#define   PMM_TOP_WDOG2_TEST_LOAD__LOAD___M      0xFFFFFFFF
#define   PMM_TOP_WDOG2_TEST_LOAD__LOAD___S                    0
#define   PMM_TOP_WDOG2_TEST_LOAD___M            0xFFFFFFFF   
#define   PMM_TOP_WDOG2_TEST_LOAD___S                          0

#define PMM_TOP_WDOG2_TEST                        (0x00B70058)
#define   PMM_TOP_WDOG2_TEST___RWC                  QCSR_REG_RW    
#define   PMM_TOP_WDOG2_TEST___POR               0x00000000
#define   PMM_TOP_WDOG2_TEST__SYNC_STATUS___POR  0x0
#define   PMM_TOP_WDOG2_TEST__LOAD_VALUE___POR   0x00000
#define   PMM_TOP_WDOG2_TEST__SYNC_STATUS___M    0x00100000
#define   PMM_TOP_WDOG2_TEST__SYNC_STATUS___S                 20
#define   PMM_TOP_WDOG2_TEST__LOAD_VALUE___M     0x000FFFFF
#define   PMM_TOP_WDOG2_TEST__LOAD_VALUE___S                   0
#define   PMM_TOP_WDOG2_TEST___M                 0x001FFFFF   
#define   PMM_TOP_WDOG2_TEST___S                               0

#define PMM_TOP_SW_DEBUG                          (0x00B7005C)
#define   PMM_TOP_SW_DEBUG___RWC                    QCSR_REG_RW    
#define   PMM_TOP_SW_DEBUG___POR                 0xFFFF0040
#define   PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___POR 0xFFFF
#define   PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___POR 0x0
#define   PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___POR 0x0
#define   PMM_TOP_SW_DEBUG__AON_FIFO_CIR___POR   0x1
#define   PMM_TOP_SW_DEBUG__AON_DBG_DOWN___POR   0x0
#define   PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___POR 0x0
#define   PMM_TOP_SW_DEBUG__NO_XO_DISABLE___POR  0x0
#define   PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___M 0xFFFF0000
#define   PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___S              16
#define   PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___M 0x00000100
#define   PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___S               8
#define   PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___M 0x00000080
#define   PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___S               7
#define   PMM_TOP_SW_DEBUG__AON_FIFO_CIR___M     0x00000040
#define   PMM_TOP_SW_DEBUG__AON_FIFO_CIR___S                   6
#define   PMM_TOP_SW_DEBUG__AON_DBG_DOWN___M     0x00000020
#define   PMM_TOP_SW_DEBUG__AON_DBG_DOWN___S                   5
#define   PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___M   0x00000010
#define   PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___S                 4
#define   PMM_TOP_SW_DEBUG__NO_XO_DISABLE___M    0x00000008
#define   PMM_TOP_SW_DEBUG__NO_XO_DISABLE___S                  3
#define   PMM_TOP_SW_DEBUG___M                   0xFFFF01F8   
#define   PMM_TOP_SW_DEBUG___S                                 3

#define PMM_TOP_SPARE_IN                          (0x00B70060)
#define   PMM_TOP_SPARE_IN___RWC                    QCSR_REG_RO    
#define   PMM_TOP_SPARE_IN___POR                 0x00000000
#define   PMM_TOP_SPARE_IN__SPARE_IN___POR       0x00000000
#define   PMM_TOP_SPARE_IN__SPARE_IN___M         0xFFFFFFFF
#define   PMM_TOP_SPARE_IN__SPARE_IN___S                       0
#define   PMM_TOP_SPARE_IN___M                   0xFFFFFFFF   
#define   PMM_TOP_SPARE_IN___S                                 0

#define PMM_TOP_SPARE_OUT                         (0x00B70064)
#define   PMM_TOP_SPARE_OUT___RWC                   QCSR_REG_RW    
#define   PMM_TOP_SPARE_OUT___POR                0x00000000
#define   PMM_TOP_SPARE_OUT__SPARE_OUT___POR     0x00000000
#define   PMM_TOP_SPARE_OUT__SPARE_OUT___M       0xFFFFFFFF
#define   PMM_TOP_SPARE_OUT__SPARE_OUT___S                     0
#define   PMM_TOP_SPARE_OUT___M                  0xFFFFFFFF   
#define   PMM_TOP_SPARE_OUT___S                                0

#define PMM_TOP_AON_SPARE                         (0x00B70068)
#define   PMM_TOP_AON_SPARE___RWC                   QCSR_REG_RW    
#define   PMM_TOP_AON_SPARE___POR                0x00000000
#define   PMM_TOP_AON_SPARE__AON_SPARE_IN___POR  0x0000
#define   PMM_TOP_AON_SPARE__AON_SPARE_OUT___POR 0x0000
#define   PMM_TOP_AON_SPARE__AON_SPARE_IN___M    0xFFFF0000
#define   PMM_TOP_AON_SPARE__AON_SPARE_IN___S                 16
#define   PMM_TOP_AON_SPARE__AON_SPARE_OUT___M   0x0000FFFF
#define   PMM_TOP_AON_SPARE__AON_SPARE_OUT___S                 0
#define   PMM_TOP_AON_SPARE___M                  0xFFFFFFFF   
#define   PMM_TOP_AON_SPARE___S                                0

#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH        (0x00B7006C)
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___RWC  QCSR_REG_RW    
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___POR 0x00000000
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___POR 0x00000000
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___S               0
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF   
#define   PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___S               0

#define PMM_TOP_XO_SETTLE_TIMER_CSR               (0x00B70070)
#define   PMM_TOP_XO_SETTLE_TIMER_CSR___RWC         QCSR_REG_RW    
#define   PMM_TOP_XO_SETTLE_TIMER_CSR___POR      0x00000010
#define   PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___POR 0x1
#define   PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___M 0x00000010
#define   PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___S               4
#define   PMM_TOP_XO_SETTLE_TIMER_CSR___M        0x00000010   
#define   PMM_TOP_XO_SETTLE_TIMER_CSR___S                      4

#define PMM_TOP_AON_PWR_DOWN_CNT                  (0x00B70074)
#define   PMM_TOP_AON_PWR_DOWN_CNT___RWC            QCSR_REG_RO    
#define   PMM_TOP_AON_PWR_DOWN_CNT___POR         0x00000000
#define   PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___POR 0x00000000
#define   PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___M 0xFFFFFFFF
#define   PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___S               0
#define   PMM_TOP_AON_PWR_DOWN_CNT___M           0xFFFFFFFF   
#define   PMM_TOP_AON_PWR_DOWN_CNT___S                         0

#define PMM_TOP_TIMEOUT_SLAVE_CTL                 (0x00B70078)
#define   PMM_TOP_TIMEOUT_SLAVE_CTL___RWC           QCSR_REG_RW    
#define   PMM_TOP_TIMEOUT_SLAVE_CTL___POR        0x00000000
#define   PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___POR 0x0
#define   PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___M 0x00000001
#define   PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___S               0
#define   PMM_TOP_TIMEOUT_SLAVE_CTL___M          0x00000001   
#define   PMM_TOP_TIMEOUT_SLAVE_CTL___S                        0

#define PMM_TOP_TIMEOUT_EXP                       (0x00B7007C)
#define   PMM_TOP_TIMEOUT_EXP___RWC                 QCSR_REG_RW    
#define   PMM_TOP_TIMEOUT_EXP___POR              0x0000FFFF
#define   PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___POR 0xFFFF
#define   PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___M 0x0000FFFF
#define   PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___S               0
#define   PMM_TOP_TIMEOUT_EXP___M                0x0000FFFF   
#define   PMM_TOP_TIMEOUT_EXP___S                              0

#define PMM_TOP_PMU_CX_CSR                        (0x00B70080)
#define   PMM_TOP_PMU_CX_CSR___RWC                  QCSR_REG_RW    
#define   PMM_TOP_PMU_CX_CSR___POR               0x0001010E
#define   PMM_TOP_PMU_CX_CSR__PMM_CX_SM___POR    0x0001
#define   PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___POR 0x1
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___POR   0x0
#define   PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___POR 0x1
#define   PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___POR 0x1
#define   PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___POR 0x1
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___POR 0x0
#define   PMM_TOP_PMU_CX_CSR__PMM_CX_SM___M      0x1FFF0000
#define   PMM_TOP_PMU_CX_CSR__PMM_CX_SM___S                   16
#define   PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___M 0x00001000
#define   PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___S              12
#define   PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___M 0x00000800
#define   PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___S              11
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___M 0x00000400
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___S              10
#define   PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___M 0x00000200
#define   PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___S               9
#define   PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___M 0x00000100
#define   PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___S               8
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___M 0x00000080
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___S               7
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___M 0x00000040
#define   PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___S               6
#define   PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___M     0x00000020
#define   PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___S                   5
#define   PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___M  0x00000010
#define   PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___S                4
#define   PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___M 0x00000008
#define   PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___S               3
#define   PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___M 0x00000004
#define   PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___S               2
#define   PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___M 0x00000002
#define   PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___S               1
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___M   0x00000001
#define   PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___S                 0
#define   PMM_TOP_PMU_CX_CSR___M                 0x1FFF1FFF   
#define   PMM_TOP_PMU_CX_CSR___S                               0

#define PMM_TOP_WAKEUP_TIME1                      (0x00B70084)
#define   PMM_TOP_WAKEUP_TIME1___RWC                QCSR_REG_RO    
#define   PMM_TOP_WAKEUP_TIME1___POR             0x00000000
#define   PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___POR 0x00000000
#define   PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___M 0xFFFFFFFF
#define   PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___S               0
#define   PMM_TOP_WAKEUP_TIME1___M               0xFFFFFFFF   
#define   PMM_TOP_WAKEUP_TIME1___S                             0

#define PMM_TOP_WAKEUP_TIME2                      (0x00B70088)
#define   PMM_TOP_WAKEUP_TIME2___RWC                QCSR_REG_RO    
#define   PMM_TOP_WAKEUP_TIME2___POR             0x00000000
#define   PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___POR 0x00000000
#define   PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___M 0xFFFFFFFF
#define   PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___S               0
#define   PMM_TOP_WAKEUP_TIME2___M               0xFFFFFFFF   
#define   PMM_TOP_WAKEUP_TIME2___S                             0

#define PMM_TOP_PLL_OUT_DIS_DELAY                 (0x00B7008C)
#define   PMM_TOP_PLL_OUT_DIS_DELAY___RWC           QCSR_REG_RW    
#define   PMM_TOP_PLL_OUT_DIS_DELAY___POR        0x00000690
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___POR 0x0000
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___POR 0x0690
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___M 0xFFFF0000
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___S              16
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___M 0x0000FFFF
#define   PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___S               0
#define   PMM_TOP_PLL_OUT_DIS_DELAY___M          0xFFFFFFFF   
#define   PMM_TOP_PLL_OUT_DIS_DELAY___S                        0

#define PMM_TOP_PLL_LOCK_DIS_DELAY                (0x00B70090)
#define   PMM_TOP_PLL_LOCK_DIS_DELAY___RWC          QCSR_REG_RW    
#define   PMM_TOP_PLL_LOCK_DIS_DELAY___POR       0x00050019
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___POR 0x0005
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___POR 0x0019
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___M 0xFFFF0000
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___S              16
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___M 0x0000FFFF
#define   PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___S               0
#define   PMM_TOP_PLL_LOCK_DIS_DELAY___M         0xFFFFFFFF   
#define   PMM_TOP_PLL_LOCK_DIS_DELAY___S                       0

#define PMM_TOP_BACKOFF_TIME                      (0x00B70094)
#define   PMM_TOP_BACKOFF_TIME___RWC                QCSR_REG_RW    
#define   PMM_TOP_BACKOFF_TIME___POR             0x00000000
#define   PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___POR 0x00000000
#define   PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___M 0xFFFFFFFF
#define   PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___S               0
#define   PMM_TOP_BACKOFF_TIME___M               0xFFFFFFFF   
#define   PMM_TOP_BACKOFF_TIME___S                             0

#define PMM_TOP_AON_SM_CTL                        (0x00B70098)
#define   PMM_TOP_AON_SM_CTL___RWC                  QCSR_REG_RW    
#define   PMM_TOP_AON_SM_CTL___POR               0x00100008
#define   PMM_TOP_AON_SM_CTL__PMM_AON_SM___POR   0x0010
#define   PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___POR 0x0
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___POR 0x0
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___POR 0x0
#define   PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___POR 0x0
#define   PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___POR 0x1
#define   PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___POR 0x0
#define   PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___POR 0x0
#define   PMM_TOP_AON_SM_CTL__PMM_AON_SM___M     0xFFFF0000
#define   PMM_TOP_AON_SM_CTL__PMM_AON_SM___S                  16
#define   PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___M 0x00000080
#define   PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___S               7
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___M 0x00000040
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___S               6
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___M 0x00000020
#define   PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___S               5
#define   PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___M 0x00000010
#define   PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___S               4
#define   PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___M 0x00000008
#define   PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___S               3
#define   PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___M 0x00000004
#define   PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___S               2
#define   PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___M 0x00000002
#define   PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___S               1
#define   PMM_TOP_AON_SM_CTL___M                 0xFFFF00FE   
#define   PMM_TOP_AON_SM_CTL___S                               1

#define PMM_TOP_AON_SLP_TMR_CTL                   (0x00B7009C)
#define   PMM_TOP_AON_SLP_TMR_CTL___RWC             QCSR_REG_RW    
#define   PMM_TOP_AON_SLP_TMR_CTL___POR          0x00000000
#define   PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___POR 0x0
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___POR 0x0
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___POR 0x0
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___POR 0x0
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___POR 0x0
#define   PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___M 0x80000000
#define   PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___S              31
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___M 0x00000008
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___S               3
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___M 0x00000004
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___S               2
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___M 0x00000002
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___S               1
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___M 0x00000001
#define   PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___S               0
#define   PMM_TOP_AON_SLP_TMR_CTL___M            0x8000000F   
#define   PMM_TOP_AON_SLP_TMR_CTL___S                          0

#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO             (0x00B700A0)
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO___RWC       QCSR_REG_RW    
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO___POR    0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___POR 0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___M 0xFFFFFFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO___M      0xFFFFFFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_LO___S                    0

#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI             (0x00B700A4)
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI___RWC       QCSR_REG_RW    
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI___POR    0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___POR 0x0000
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___M 0x0000FFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI___M      0x0000FFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_WR_HI___S                    0

#define PMM_TOP_AON_SLP_TMR_VAL_LO                (0x00B700A8)
#define   PMM_TOP_AON_SLP_TMR_VAL_LO___RWC          QCSR_REG_RO    
#define   PMM_TOP_AON_SLP_TMR_VAL_LO___POR       0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___POR 0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___M 0xFFFFFFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_LO___M         0xFFFFFFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_LO___S                       0

#define PMM_TOP_AON_SLP_TMR_VAL_HI                (0x00B700AC)
#define   PMM_TOP_AON_SLP_TMR_VAL_HI___RWC          QCSR_REG_RO    
#define   PMM_TOP_AON_SLP_TMR_VAL_HI___POR       0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___POR 0x0000
#define   PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___M 0x0000FFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_HI___M         0x0000FFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_HI___S                       0

#define PMM_TOP_AON_SLP_TMR_VAL_G_LO              (0x00B700B0)
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO___RWC        QCSR_REG_RO    
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO___POR     0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___POR 0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___M 0xFFFFFFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO___M       0xFFFFFFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_G_LO___S                     0

#define PMM_TOP_AON_SLP_TMR_VAL_G_HI              (0x00B700B4)
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI___RWC        QCSR_REG_RO    
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI___POR     0x00000000
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___POR 0x0000
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___M 0x0000FFFF
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___S               0
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI___M       0x0000FFFF   
#define   PMM_TOP_AON_SLP_TMR_VAL_G_HI___S                     0

#define PMM_TOP_AON_SWITCHER_DLY                  (0x00B700B8)
#define   PMM_TOP_AON_SWITCHER_DLY___RWC            QCSR_REG_RW    
#define   PMM_TOP_AON_SWITCHER_DLY___POR         0x00000F0E
#define   PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___POR 0x0
#define   PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___POR 0x0000
#define   PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___POR 0x0F0E
#define   PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___M 0x80000000
#define   PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___S              31
#define   PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___M 0x7FFF0000
#define   PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___S              16
#define   PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___M 0x0000FFFF
#define   PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___S               0
#define   PMM_TOP_AON_SWITCHER_DLY___M           0xFFFFFFFF   
#define   PMM_TOP_AON_SWITCHER_DLY___S                         0

#define PMM_TOP_AON_TIMER_WAKEUP_THRESH           (0x00B700BC)
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH___RWC     QCSR_REG_RW    
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH___POR  0x00000000
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___POR 0x00000000
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___S               0
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH___M    0xFFFFFFFF   
#define   PMM_TOP_AON_TIMER_WAKEUP_THRESH___S                  0

#define PMM_TOP_AON_INT_CLR                       (0x00B700C0)
#define   PMM_TOP_AON_INT_CLR___RWC                 QCSR_REG_RW    
#define   PMM_TOP_AON_INT_CLR___POR              0x00000000
#define   PMM_TOP_AON_INT_CLR__AON_INT_CLR___POR 0x0000
#define   PMM_TOP_AON_INT_CLR__AON_INT_CLR___M   0x00001FFF
#define   PMM_TOP_AON_INT_CLR__AON_INT_CLR___S                 0
#define   PMM_TOP_AON_INT_CLR___M                0x00001FFF   
#define   PMM_TOP_AON_INT_CLR___S                              0

#define PMM_TOP_AON_INT_POL                       (0x00B700C4)
#define   PMM_TOP_AON_INT_POL___RWC                 QCSR_REG_RW    
#define   PMM_TOP_AON_INT_POL___POR              0x00001FFF
#define   PMM_TOP_AON_INT_POL__AON_INT_POL___POR 0x1FFF
#define   PMM_TOP_AON_INT_POL__AON_INT_POL___M   0x00001FFF
#define   PMM_TOP_AON_INT_POL__AON_INT_POL___S                 0
#define   PMM_TOP_AON_INT_POL___M                0x00001FFF   
#define   PMM_TOP_AON_INT_POL___S                              0

#define PMM_TOP_AON_INT_POS_EDGE_EN               (0x00B700C8)
#define   PMM_TOP_AON_INT_POS_EDGE_EN___RWC         QCSR_REG_RW    
#define   PMM_TOP_AON_INT_POS_EDGE_EN___POR      0x00000000
#define   PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___POR 0x0000
#define   PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___M 0x00001FFF
#define   PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___S               0
#define   PMM_TOP_AON_INT_POS_EDGE_EN___M        0x00001FFF   
#define   PMM_TOP_AON_INT_POS_EDGE_EN___S                      0

#define PMM_TOP_AON_INT_NEG_EDGE_EN               (0x00B700CC)
#define   PMM_TOP_AON_INT_NEG_EDGE_EN___RWC         QCSR_REG_RW    
#define   PMM_TOP_AON_INT_NEG_EDGE_EN___POR      0x00000000
#define   PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___POR 0x0000
#define   PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___M 0x00001FFF
#define   PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___S               0
#define   PMM_TOP_AON_INT_NEG_EDGE_EN___M        0x00001FFF   
#define   PMM_TOP_AON_INT_NEG_EDGE_EN___S                      0

#define PMM_TOP_AON_INT_EN                        (0x00B700D0)
#define   PMM_TOP_AON_INT_EN___RWC                  QCSR_REG_RW    
#define   PMM_TOP_AON_INT_EN___POR               0x00001FFF
#define   PMM_TOP_AON_INT_EN__AON_INT_EN___POR   0x1FFF
#define   PMM_TOP_AON_INT_EN__AON_INT_EN___M     0x00001FFF
#define   PMM_TOP_AON_INT_EN__AON_INT_EN___S                   0
#define   PMM_TOP_AON_INT_EN___M                 0x00001FFF   
#define   PMM_TOP_AON_INT_EN___S                               0

#define PMM_TOP_AON_INT_ACK_EN                    (0x00B700D4)
#define   PMM_TOP_AON_INT_ACK_EN___RWC              QCSR_REG_RW    
#define   PMM_TOP_AON_INT_ACK_EN___POR           0x00000020
#define   PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___POR 0x0020
#define   PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___M 0x00001FFF
#define   PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___S               0
#define   PMM_TOP_AON_INT_ACK_EN___M             0x00001FFF   
#define   PMM_TOP_AON_INT_ACK_EN___S                           0

#define PMM_TOP_AON_INT_STICKY_EN                 (0x00B700D8)
#define   PMM_TOP_AON_INT_STICKY_EN___RWC           QCSR_REG_RW    
#define   PMM_TOP_AON_INT_STICKY_EN___POR        0x8000007C
#define   PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___POR 0x1
#define   PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___POR 0x007C
#define   PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___M 0x80000000
#define   PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___S              31
#define   PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___M 0x00001FFF
#define   PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___S               0
#define   PMM_TOP_AON_INT_STICKY_EN___M          0x80001FFF   
#define   PMM_TOP_AON_INT_STICKY_EN___S                        0

#define PMM_TOP_AON_INT_STAT                      (0x00B700DC)
#define   PMM_TOP_AON_INT_STAT___RWC                QCSR_REG_RO    
#define   PMM_TOP_AON_INT_STAT___POR             0x00000000
#define   PMM_TOP_AON_INT_STAT__AON_INT_STAT___POR 0x0000
#define   PMM_TOP_AON_INT_STAT__AON_INT_STAT___M 0x00001FFF
#define   PMM_TOP_AON_INT_STAT__AON_INT_STAT___S               0
#define   PMM_TOP_AON_INT_STAT___M               0x00001FFF   
#define   PMM_TOP_AON_INT_STAT___S                             0

#define PMM_TOP_AON_INT_RAW_STAT                  (0x00B700E0)
#define   PMM_TOP_AON_INT_RAW_STAT___RWC            QCSR_REG_RO    
#define   PMM_TOP_AON_INT_RAW_STAT___POR         0x00000000
#define   PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___POR 0x0000
#define   PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___M 0x00001FFF
#define   PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___S               0
#define   PMM_TOP_AON_INT_RAW_STAT___M           0x00001FFF   
#define   PMM_TOP_AON_INT_RAW_STAT___S                         0

#define PMM_TOP_WSI_CMD                           (0x00B700E4)
#define   PMM_TOP_WSI_CMD___RWC                     QCSR_REG_RW    
#define   PMM_TOP_WSI_CMD___POR                  0x00010000
#define   PMM_TOP_WSI_CMD__RF_CMD_IP___POR       0x0
#define   PMM_TOP_WSI_CMD__WSI_ERR_STATUS___POR  0x0
#define   PMM_TOP_WSI_CMD__PMM_WSI_SM___POR      0x001
#define   PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___POR 0x0
#define   PMM_TOP_WSI_CMD__SW_FORCE_IDLE___POR   0x0
#define   PMM_TOP_WSI_CMD__SW_XO_DIS___POR       0x0
#define   PMM_TOP_WSI_CMD__SW_XO_EN___POR        0x0
#define   PMM_TOP_WSI_CMD__SW_REG_WRITE___POR    0x0
#define   PMM_TOP_WSI_CMD__SW_REG_READ___POR     0x0
#define   PMM_TOP_WSI_CMD__SW_RF_RESET___POR     0x0
#define   PMM_TOP_WSI_CMD__SW_BUS_SYNC___POR     0x0
#define   PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___POR  0x0
#define   PMM_TOP_WSI_CMD__RF_CMD_IP___M         0x80000000
#define   PMM_TOP_WSI_CMD__RF_CMD_IP___S                      31
#define   PMM_TOP_WSI_CMD__WSI_ERR_STATUS___M    0x70000000
#define   PMM_TOP_WSI_CMD__WSI_ERR_STATUS___S                 28
#define   PMM_TOP_WSI_CMD__PMM_WSI_SM___M        0x01FF0000
#define   PMM_TOP_WSI_CMD__PMM_WSI_SM___S                     16
#define   PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___M 0x00000400
#define   PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___S              10
#define   PMM_TOP_WSI_CMD__SW_FORCE_IDLE___M     0x00000200
#define   PMM_TOP_WSI_CMD__SW_FORCE_IDLE___S                   9
#define   PMM_TOP_WSI_CMD__SW_XO_DIS___M         0x00000100
#define   PMM_TOP_WSI_CMD__SW_XO_DIS___S                       8
#define   PMM_TOP_WSI_CMD__SW_XO_EN___M          0x00000080
#define   PMM_TOP_WSI_CMD__SW_XO_EN___S                        7
#define   PMM_TOP_WSI_CMD__SW_REG_WRITE___M      0x00000040
#define   PMM_TOP_WSI_CMD__SW_REG_WRITE___S                    6
#define   PMM_TOP_WSI_CMD__SW_REG_READ___M       0x00000020
#define   PMM_TOP_WSI_CMD__SW_REG_READ___S                     5
#define   PMM_TOP_WSI_CMD__SW_RF_RESET___M       0x00000010
#define   PMM_TOP_WSI_CMD__SW_RF_RESET___S                     4
#define   PMM_TOP_WSI_CMD__SW_BUS_SYNC___M       0x00000008
#define   PMM_TOP_WSI_CMD__SW_BUS_SYNC___S                     3
#define   PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___M    0x00000004
#define   PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___S                  2
#define   PMM_TOP_WSI_CMD___M                    0xF1FF07FC   
#define   PMM_TOP_WSI_CMD___S                                  2

#define PMM_TOP_WSI_MUX_SEL                       (0x00B700E8)
#define   PMM_TOP_WSI_MUX_SEL___RWC                 QCSR_REG_RW    
#define   PMM_TOP_WSI_MUX_SEL___POR              0x00000000
#define   PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___POR 0x0
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___POR 0x0
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___POR 0x0
#define   PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___POR 0x00
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___POR 0x0
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___POR 0x0
#define   PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___M 0x00000C00
#define   PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___S              10
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___M 0x00000200
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___S               9
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___M 0x00000100
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___S               8
#define   PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___M 0x000000FC
#define   PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___S               2
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___M 0x00000002
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___S               1
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___M 0x00000001
#define   PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___S               0
#define   PMM_TOP_WSI_MUX_SEL___M                0x00000FFF   
#define   PMM_TOP_WSI_MUX_SEL___S                              0

#define PMM_TOP_WSIM_CTL                          (0x00B700EC)
#define   PMM_TOP_WSIM_CTL___RWC                    QCSR_REG_RW    
#define   PMM_TOP_WSIM_CTL___POR                 0x00003A00
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___POR 0x00
#define   PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___POR 0x3
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___POR 0xA
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___POR 0x0
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___M 0x7C000000
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___S              26
#define   PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___M 0x02000000
#define   PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___S              25
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___M 0x01000000
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___S              24
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___M  0x00800000
#define   PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___S               23
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___M 0x00400000
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___S              22
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___M 0x00200000
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___S              21
#define   PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___M 0x00100000
#define   PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___S              20
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___M 0x000C0000
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___S              18
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___M 0x00030000
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___S              16
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___M 0x0000F000
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___S              12
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___M 0x00000F00
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___S               8
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___M 0x00000040
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___S               6
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___M 0x00000020
#define   PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___S               5
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___M 0x00000010
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___S               4
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___M 0x00000008
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___S               3
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___M 0x00000004
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___S               2
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___M 0x00000002
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___S               1
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___M 0x00000001
#define   PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___S               0
#define   PMM_TOP_WSIM_CTL___M                   0x7FFFFF7F   
#define   PMM_TOP_WSIM_CTL___S                                 0

#define PMM_TOP_XO_DIS_ADDR                       (0x00B700F0)
#define   PMM_TOP_XO_DIS_ADDR___RWC                 QCSR_REG_RW    
#define   PMM_TOP_XO_DIS_ADDR___POR              0x00000000
#define   PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___POR 0x0000
#define   PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___M   0x0000FFFF
#define   PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___S                 0
#define   PMM_TOP_XO_DIS_ADDR___M                0x0000FFFF   
#define   PMM_TOP_XO_DIS_ADDR___S                              0

#define PMM_TOP_XO_DIS_DATA                       (0x00B700F4)
#define   PMM_TOP_XO_DIS_DATA___RWC                 QCSR_REG_RW    
#define   PMM_TOP_XO_DIS_DATA___POR              0x00000000
#define   PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___POR 0x00000000
#define   PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___M   0xFFFFFFFF
#define   PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___S                 0
#define   PMM_TOP_XO_DIS_DATA___M                0xFFFFFFFF   
#define   PMM_TOP_XO_DIS_DATA___S                              0

#define PMM_TOP_REG_RW_ADDR                       (0x00B700F8)
#define   PMM_TOP_REG_RW_ADDR___RWC                 QCSR_REG_RW    
#define   PMM_TOP_REG_RW_ADDR___POR              0x00000000
#define   PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___POR 0x0000
#define   PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___M 0x0000FFFF
#define   PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___S               0
#define   PMM_TOP_REG_RW_ADDR___M                0x0000FFFF   
#define   PMM_TOP_REG_RW_ADDR___S                              0

#define PMM_TOP_REG_WRITE_DATA                    (0x00B700FC)
#define   PMM_TOP_REG_WRITE_DATA___RWC              QCSR_REG_RW    
#define   PMM_TOP_REG_WRITE_DATA___POR           0x00000000
#define   PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___POR 0x00000000
#define   PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___M 0xFFFFFFFF
#define   PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___S               0
#define   PMM_TOP_REG_WRITE_DATA___M             0xFFFFFFFF   
#define   PMM_TOP_REG_WRITE_DATA___S                           0

#define PMM_TOP_REG_READ_DATA                     (0x00B70100)
#define   PMM_TOP_REG_READ_DATA___RWC               QCSR_REG_RO    
#define   PMM_TOP_REG_READ_DATA___POR            0x00000000
#define   PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___POR 0x00000000
#define   PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___M 0xFFFFFFFF
#define   PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___S               0
#define   PMM_TOP_REG_READ_DATA___M              0xFFFFFFFF   
#define   PMM_TOP_REG_READ_DATA___S                            0

#define PMM_TOP_RF_VAULT_REG_ADDR                 (0x00B70104)
#define   PMM_TOP_RF_VAULT_REG_ADDR___RWC           QCSR_REG_RW    
#define   PMM_TOP_RF_VAULT_REG_ADDR___POR        0x00000000
#define   PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___POR 0x0000
#define   PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___M 0x0000FFFF
#define   PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___S               0
#define   PMM_TOP_RF_VAULT_REG_ADDR___M          0x0000FFFF   
#define   PMM_TOP_RF_VAULT_REG_ADDR___S                        0

#define PMM_TOP_RF_VAULT_REG_DATA                 (0x00B70108)
#define   PMM_TOP_RF_VAULT_REG_DATA___RWC           QCSR_REG_RW    
#define   PMM_TOP_RF_VAULT_REG_DATA___POR        0x00000000
#define   PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___POR 0x00000000
#define   PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___M 0xFFFFFFFF
#define   PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___S               0
#define   PMM_TOP_RF_VAULT_REG_DATA___M          0xFFFFFFFF   
#define   PMM_TOP_RF_VAULT_REG_DATA___S                        0

#define PMM_TOP_RF_RESET_ADDR                     (0x00B7010C)
#define   PMM_TOP_RF_RESET_ADDR___RWC               QCSR_REG_RW    
#define   PMM_TOP_RF_RESET_ADDR___POR            0x00000000
#define   PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___POR 0x0000
#define   PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___M 0x0000FFFF
#define   PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___S               0
#define   PMM_TOP_RF_RESET_ADDR___M              0x0000FFFF   
#define   PMM_TOP_RF_RESET_ADDR___S                            0

#define PMM_TOP_RF_RESET_DATA                     (0x00B70110)
#define   PMM_TOP_RF_RESET_DATA___RWC               QCSR_REG_RW    
#define   PMM_TOP_RF_RESET_DATA___POR            0x00000000
#define   PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___POR 0x00000000
#define   PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___M 0xFFFFFFFF
#define   PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___S               0
#define   PMM_TOP_RF_RESET_DATA___M              0xFFFFFFFF   
#define   PMM_TOP_RF_RESET_DATA___S                            0

#define PMM_TOP_SW_SCRATCH                        (0x00B70114)
#define   PMM_TOP_SW_SCRATCH___RWC                  QCSR_REG_RW    
#define   PMM_TOP_SW_SCRATCH___POR               0x00000000
#define   PMM_TOP_SW_SCRATCH__SCRATCH___POR      0x00000000
#define   PMM_TOP_SW_SCRATCH__SCRATCH___M        0xFFFFFFFF
#define   PMM_TOP_SW_SCRATCH__SCRATCH___S                      0
#define   PMM_TOP_SW_SCRATCH___M                 0xFFFFFFFF   
#define   PMM_TOP_SW_SCRATCH___S                               0

#define PMM_TOP_SW_SLP_TMR_CTL                    (0x00B70118)
#define   PMM_TOP_SW_SLP_TMR_CTL___RWC              QCSR_REG_RW    
#define   PMM_TOP_SW_SLP_TMR_CTL___POR           0x00000001
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___POR 0x0
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___POR 0x1
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___M 0x00000002
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___S               1
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___M 0x00000001
#define   PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___S               0
#define   PMM_TOP_SW_SLP_TMR_CTL___M             0x00000003   
#define   PMM_TOP_SW_SLP_TMR_CTL___S                           0

#define PMM_TOP_SW_SLP_TMR_STS                    (0x00B7011C)
#define   PMM_TOP_SW_SLP_TMR_STS___RWC              QCSR_REG_RO    
#define   PMM_TOP_SW_SLP_TMR_STS___POR           0x00000000
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___POR 0x0
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___POR 0x0
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___M 0x00000002
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___S               1
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___M 0x00000001
#define   PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___S               0
#define   PMM_TOP_SW_SLP_TMR_STS___M             0x00000003   
#define   PMM_TOP_SW_SLP_TMR_STS___S                           0

#define PMM_TOP_SW_SLP_TMR_EXP_LO                 (0x00B70120)
#define   PMM_TOP_SW_SLP_TMR_EXP_LO___RWC           QCSR_REG_RW    
#define   PMM_TOP_SW_SLP_TMR_EXP_LO___POR        0xFFFFFFFF
#define   PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___POR 0xFFFFFFFF
#define   PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___M 0xFFFFFFFF
#define   PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___S               0
#define   PMM_TOP_SW_SLP_TMR_EXP_LO___M          0xFFFFFFFF   
#define   PMM_TOP_SW_SLP_TMR_EXP_LO___S                        0

#define PMM_TOP_SW_SLP_TMR_EXP_HI                 (0x00B70124)
#define   PMM_TOP_SW_SLP_TMR_EXP_HI___RWC           QCSR_REG_RW    
#define   PMM_TOP_SW_SLP_TMR_EXP_HI___POR        0x00000000
#define   PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___POR 0x0000
#define   PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___M 0x0000FFFF
#define   PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___S               0
#define   PMM_TOP_SW_SLP_TMR_EXP_HI___M          0x0000FFFF   
#define   PMM_TOP_SW_SLP_TMR_EXP_HI___S                        0

#define PMM_TOP_COMMON_IDLEREQ_CSR                (0x00B70128)
#define   PMM_TOP_COMMON_IDLEREQ_CSR___RWC          QCSR_REG_RW    
#define   PMM_TOP_COMMON_IDLEREQ_CSR___POR       0x10000102
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___POR 0x1
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___POR 0x0
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___POR 0x0
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___POR 0x0
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___POR 0x0
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___POR 0x0
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___POR 0x1
#define   PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___POR 0x1
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___M 0x10000000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___S              28
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___M 0x08000000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___S              27
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___M 0x04000000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___S              26
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___M 0x02000000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___S              25
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___M 0x00020000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___S              17
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___M 0x00010000
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___S              16
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___M 0x00000100
#define   PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___S               8
#define   PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___M 0x00000002
#define   PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___S               1
#define   PMM_TOP_COMMON_IDLEREQ_CSR___M         0x1E030102   
#define   PMM_TOP_COMMON_IDLEREQ_CSR___S                       1

#define PMM_TOP_NAV_BLANK_CTL                     (0x00B7012C)
#define   PMM_TOP_NAV_BLANK_CTL___RWC               QCSR_REG_RW    
#define   PMM_TOP_NAV_BLANK_CTL___POR            0x00000000
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___POR 0x0
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___POR 0x0
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___POR 0x0
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___POR 0x0
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___M 0x00000200
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___S               9
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___M 0x00000100
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___S               8
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___M 0x00000002
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___S               1
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___M 0x00000001
#define   PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___S               0
#define   PMM_TOP_NAV_BLANK_CTL___M              0x00000303   
#define   PMM_TOP_NAV_BLANK_CTL___S                            0

#define PMM_TOP_GPIO_PWR_CSR                      (0x00B70130)
#define   PMM_TOP_GPIO_PWR_CSR___RWC                QCSR_REG_RW    
#define   PMM_TOP_GPIO_PWR_CSR___POR             0x00000000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___POR 0x0
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___M 0x00800000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___S              23
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___M 0x00400000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___S              22
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___M 0x00200000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___S              21
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___M 0x00100000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___S              20
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___M 0x00080000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___S              19
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___M 0x00040000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___S              18
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___M 0x00020000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___S              17
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___M 0x00010000
#define   PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___S              16
#define   PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___M 0x00000001
#define   PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___S               0
#define   PMM_TOP_GPIO_PWR_CSR___M               0x00FF0001   
#define   PMM_TOP_GPIO_PWR_CSR___S                             0

#define PMM_TOP_DBG_CSR                           (0x00B70160)
#define   PMM_TOP_DBG_CSR___RWC                     QCSR_REG_RW    
#define   PMM_TOP_DBG_CSR___POR                  0x0000005C
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___POR 0x1
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___POR 0x0
#define   PMM_TOP_DBG_CSR__CSYSACK___POR         0x1
#define   PMM_TOP_DBG_CSR__CACTIVE___POR         0x1
#define   PMM_TOP_DBG_CSR__CSYSREQ___POR         0x1
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___POR  0x0
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___POR  0x0
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___M 0x00000040
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___S               6
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___M 0x00000020
#define   PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___S               5
#define   PMM_TOP_DBG_CSR__CSYSACK___M           0x00000010
#define   PMM_TOP_DBG_CSR__CSYSACK___S                         4
#define   PMM_TOP_DBG_CSR__CACTIVE___M           0x00000008
#define   PMM_TOP_DBG_CSR__CACTIVE___S                         3
#define   PMM_TOP_DBG_CSR__CSYSREQ___M           0x00000004
#define   PMM_TOP_DBG_CSR__CSYSREQ___S                         2
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___M    0x00000002
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___S                  1
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___M    0x00000001
#define   PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___S                  0
#define   PMM_TOP_DBG_CSR___M                    0x0000007F   
#define   PMM_TOP_DBG_CSR___S                                  0

#define PMM_TOP_PMM_INT_STAT                      (0x00B70164)
#define   PMM_TOP_PMM_INT_STAT___RWC                QCSR_REG_RO    
#define   PMM_TOP_PMM_INT_STAT___POR             0x00000000
#define   PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___POR 0x0
#define   PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___M 0x00000001
#define   PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___S               0
#define   PMM_TOP_PMM_INT_STAT___M               0x00000001   
#define   PMM_TOP_PMM_INT_STAT___S                             0

#define PMM_TOP_PMM_INT_CLR                       (0x00B70168)
#define   PMM_TOP_PMM_INT_CLR___RWC                 QCSR_REG_WO    
#define   PMM_TOP_PMM_INT_CLR___POR              0x00000000
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___POR 0x0
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___POR 0x0
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___M 0x00000002
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___S               1
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___M 0x00000001
#define   PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___S               0
#define   PMM_TOP_PMM_INT_CLR___M                0x00000003   
#define   PMM_TOP_PMM_INT_CLR___S                              0

#define PMM_TOP_SNOC_IDLEREQ_CSR                  (0x00B7016C)
#define   PMM_TOP_SNOC_IDLEREQ_CSR___RWC            QCSR_REG_RW    
#define   PMM_TOP_SNOC_IDLEREQ_CSR___POR         0x00000000
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___POR 0x0
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___POR 0x0
#define   PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___POR 0x0
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___M 0x00000004
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___S               2
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___M 0x00000002
#define   PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___S               1
#define   PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___M 0x00000001
#define   PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___S               0
#define   PMM_TOP_SNOC_IDLEREQ_CSR___M           0x00000007   
#define   PMM_TOP_SNOC_IDLEREQ_CSR___S                         0

#define PMM_TOP_WLAN_TOP_CLKGEN_CTL               (0x00B70170)
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL___RWC         QCSR_REG_RW    
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL___POR      0x00000000
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___POR 0x0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___M 0x00020000
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___S              17
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___M 0x00010000
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___S              16
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___M 0x00001000
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___S              12
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___M 0x00000800
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___S              11
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___M 0x00000400
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___S              10
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___M 0x00000200
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___S               9
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___M 0x00000100
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___S               8
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___M 0x00000010
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___S               4
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___M 0x00000008
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___S               3
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___M 0x00000004
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___S               2
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___M 0x00000002
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___S               1
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___M 0x00000001
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___S               0
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL___M        0x00031F1F   
#define   PMM_TOP_WLAN_TOP_CLKGEN_CTL___S                      0

#define PMM_TOP_WLAN1_SLP_TMR_CTL                 (0x00B70180)
#define   PMM_TOP_WLAN1_SLP_TMR_CTL___RWC           QCSR_REG_RW    
#define   PMM_TOP_WLAN1_SLP_TMR_CTL___POR        0x00000001
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___POR 0x0
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___POR 0x1
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___M 0x00000002
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___S               1
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___M 0x00000001
#define   PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___S               0
#define   PMM_TOP_WLAN1_SLP_TMR_CTL___M          0x00000003   
#define   PMM_TOP_WLAN1_SLP_TMR_CTL___S                        0

#define PMM_TOP_WLAN1_SLP_TMR_STS                 (0x00B70184)
#define   PMM_TOP_WLAN1_SLP_TMR_STS___RWC           QCSR_REG_RO    
#define   PMM_TOP_WLAN1_SLP_TMR_STS___POR        0x00000000
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___POR 0x0
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___POR 0x0
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___M 0x00000002
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___S               1
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___M 0x00000001
#define   PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___S               0
#define   PMM_TOP_WLAN1_SLP_TMR_STS___M          0x00000003   
#define   PMM_TOP_WLAN1_SLP_TMR_STS___S                        0

#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO              (0x00B70188)
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO___RWC        QCSR_REG_RW    
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO___POR     0xFFFFFFFF
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___POR 0xFFFFFFFF
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___M 0xFFFFFFFF
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___S               0
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO___M       0xFFFFFFFF   
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_LO___S                     0

#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI              (0x00B7018C)
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI___RWC        QCSR_REG_RW    
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI___POR     0x00000000
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___POR 0x0000
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___M 0x0000FFFF
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___S               0
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI___M       0x0000FFFF   
#define   PMM_TOP_WLAN1_SLP_TMR_EXP_HI___S                     0

#define PMM_TOP_WLAN1_GPIO_PWR_MSK                (0x00B70190)
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK___RWC          QCSR_REG_RW    
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK___POR       0x000000FF
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___POR 0x1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___M 0x00000080
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___S               7
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___M 0x00000040
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___S               6
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___M 0x00000020
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___S               5
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___M 0x00000010
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___S               4
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___M 0x00000008
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___S               3
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___M 0x00000004
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___S               2
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___M 0x00000002
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___S               1
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___M 0x00000001
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___S               0
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK___M         0x000000FF   
#define   PMM_TOP_WLAN1_GPIO_PWR_MSK___S                       0

#define PMM_TOP_WLAN2_SLP_TMR_CTL                 (0x00B7019C)
#define   PMM_TOP_WLAN2_SLP_TMR_CTL___RWC           QCSR_REG_RW    
#define   PMM_TOP_WLAN2_SLP_TMR_CTL___POR        0x00000001
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___POR 0x0
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___POR 0x1
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___M 0x00000002
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___S               1
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___M 0x00000001
#define   PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___S               0
#define   PMM_TOP_WLAN2_SLP_TMR_CTL___M          0x00000003   
#define   PMM_TOP_WLAN2_SLP_TMR_CTL___S                        0

#define PMM_TOP_WLAN2_SLP_TMR_STS                 (0x00B701A0)
#define   PMM_TOP_WLAN2_SLP_TMR_STS___RWC           QCSR_REG_RO    
#define   PMM_TOP_WLAN2_SLP_TMR_STS___POR        0x00000000
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___POR 0x0
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___POR 0x0
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___M 0x00000002
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___S               1
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___M 0x00000001
#define   PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___S               0
#define   PMM_TOP_WLAN2_SLP_TMR_STS___M          0x00000003   
#define   PMM_TOP_WLAN2_SLP_TMR_STS___S                        0

#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO              (0x00B701A4)
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO___RWC        QCSR_REG_RW    
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO___POR     0x00000000
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___POR 0x00000000
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___M 0xFFFFFFFF
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___S               0
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO___M       0xFFFFFFFF   
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_LO___S                     0

#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI              (0x00B701A8)
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI___RWC        QCSR_REG_RW    
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI___POR     0x00000000
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___POR 0x0000
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___M 0x0000FFFF
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___S               0
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI___M       0x0000FFFF   
#define   PMM_TOP_WLAN2_SLP_TMR_EXP_HI___S                     0

#define PMM_TOP_WLAN2_GPIO_PWR_MSK                (0x00B701AC)
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK___RWC          QCSR_REG_RW    
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK___POR       0x000000FF
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___POR 0x1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___M 0x00000080
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___S               7
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___M 0x00000040
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___S               6
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___M 0x00000020
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___S               5
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___M 0x00000010
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___S               4
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___M 0x00000008
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___S               3
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___M 0x00000004
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___S               2
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___M 0x00000002
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___S               1
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___M 0x00000001
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___S               0
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK___M         0x000000FF   
#define   PMM_TOP_WLAN2_GPIO_PWR_MSK___S                       0

#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR      (0x00B701B8)
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___RWC QCSR_REG_RW    
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___POR 0x00000000
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___POR 0x0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___POR 0x0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___POR 0x0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___M 0x80000000
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___S              31
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___M 0x00000002
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___S               1
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___M 0x00000001
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___S               0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___M 0x80000013   
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___S               0

#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR      (0x00B701BC)
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___RWC QCSR_REG_RW    
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___POR 0x00000000
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___POR 0x0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___POR 0x00
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___M 0x00000700
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___S               8
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___M 0x0000001F
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___S               0
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___M 0x0000071F   
#define   PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___S               0

#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL         (0x00B701C0)
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___RWC   QCSR_REG_RW    
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___POR 0x00000000
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___POR 0x0
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___M 0x00000001
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___S               0
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___M  0x00000001   
#define   PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___S                0

#define PMM_TOP_BB_PLL                            (0x00B701C4)
#define   PMM_TOP_BB_PLL___RWC                      QCSR_REG_RW    
#define   PMM_TOP_BB_PLL___POR                   0x00000000
#define   PMM_TOP_BB_PLL__PLL_LOCK___POR         0x0
#define   PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___POR   0x0
#define   PMM_TOP_BB_PLL__PLL_RST_L___POR        0x0
#define   PMM_TOP_BB_PLL__PLL_ISO_EN_L___POR     0x0
#define   PMM_TOP_BB_PLL__PLL_LDO_EN___POR       0x0
#define   PMM_TOP_BB_PLL__PLL_ENABLE___POR       0x0
#define   PMM_TOP_BB_PLL__PLL_LOCK___M           0x80000000
#define   PMM_TOP_BB_PLL__PLL_LOCK___S                        31
#define   PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___M     0x00000010
#define   PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___S                   4
#define   PMM_TOP_BB_PLL__PLL_RST_L___M          0x00000008
#define   PMM_TOP_BB_PLL__PLL_RST_L___S                        3
#define   PMM_TOP_BB_PLL__PLL_ISO_EN_L___M       0x00000004
#define   PMM_TOP_BB_PLL__PLL_ISO_EN_L___S                     2
#define   PMM_TOP_BB_PLL__PLL_LDO_EN___M         0x00000002
#define   PMM_TOP_BB_PLL__PLL_LDO_EN___S                       1
#define   PMM_TOP_BB_PLL__PLL_ENABLE___M         0x00000001
#define   PMM_TOP_BB_PLL__PLL_ENABLE___S                       0
#define   PMM_TOP_BB_PLL___M                     0x8000001F   
#define   PMM_TOP_BB_PLL___S                                   0

#define PMM_TOP_HW_EVENT_CTL_0                    (0x00B701E0)
#define   PMM_TOP_HW_EVENT_CTL_0___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_0___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_0___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_0___S                           0

#define PMM_TOP_HW_EVENT_CTL_1                    (0x00B701E4)
#define   PMM_TOP_HW_EVENT_CTL_1___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_1___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_1___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_1___S                           0

#define PMM_TOP_HW_EVENT_CTL_2                    (0x00B701E8)
#define   PMM_TOP_HW_EVENT_CTL_2___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_2___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_2___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_2___S                           0

#define PMM_TOP_HW_EVENT_CTL_3                    (0x00B701EC)
#define   PMM_TOP_HW_EVENT_CTL_3___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_3___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_3___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_3___S                           0

#define PMM_TOP_HW_EVENT_CTL_4                    (0x00B701F0)
#define   PMM_TOP_HW_EVENT_CTL_4___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_4___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_4___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_4___S                           0

#define PMM_TOP_HW_EVENT_CTL_5                    (0x00B701F4)
#define   PMM_TOP_HW_EVENT_CTL_5___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_5___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_5___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_5___S                           0

#define PMM_TOP_HW_EVENT_CTL_6                    (0x00B701F8)
#define   PMM_TOP_HW_EVENT_CTL_6___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_6___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_6___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_6___S                           0

#define PMM_TOP_HW_EVENT_CTL_7                    (0x00B701FC)
#define   PMM_TOP_HW_EVENT_CTL_7___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_7___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_7___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_7___S                           0

#define PMM_TOP_HW_EVENT_CTL_8                    (0x00B70200)
#define   PMM_TOP_HW_EVENT_CTL_8___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_8___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_8___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_8___S                           0

#define PMM_TOP_HW_EVENT_CTL_9                    (0x00B70204)
#define   PMM_TOP_HW_EVENT_CTL_9___RWC              QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_9___POR           0x80000000
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_9___M             0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_9___S                           0

#define PMM_TOP_HW_EVENT_CTL_10                   (0x00B70208)
#define   PMM_TOP_HW_EVENT_CTL_10___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_10___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_10___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_10___S                          0

#define PMM_TOP_HW_EVENT_CTL_11                   (0x00B7020C)
#define   PMM_TOP_HW_EVENT_CTL_11___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_11___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_11___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_11___S                          0

#define PMM_TOP_HW_EVENT_CTL_12                   (0x00B70210)
#define   PMM_TOP_HW_EVENT_CTL_12___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_12___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_12___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_12___S                          0

#define PMM_TOP_HW_EVENT_CTL_13                   (0x00B70214)
#define   PMM_TOP_HW_EVENT_CTL_13___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_13___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_13___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_13___S                          0

#define PMM_TOP_HW_EVENT_CTL_14                   (0x00B70218)
#define   PMM_TOP_HW_EVENT_CTL_14___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_14___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_14___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_14___S                          0

#define PMM_TOP_HW_EVENT_CTL_15                   (0x00B7021C)
#define   PMM_TOP_HW_EVENT_CTL_15___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_15___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_15___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_15___S                          0

#define PMM_TOP_HW_EVENT_CTL_16                   (0x00B70220)
#define   PMM_TOP_HW_EVENT_CTL_16___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_16___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_16___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_16___S                          0

#define PMM_TOP_HW_EVENT_CTL_17                   (0x00B70224)
#define   PMM_TOP_HW_EVENT_CTL_17___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_17___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_17___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_17___S                          0

#define PMM_TOP_HW_EVENT_CTL_18                   (0x00B70228)
#define   PMM_TOP_HW_EVENT_CTL_18___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_18___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_18___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_18___S                          0

#define PMM_TOP_HW_EVENT_CTL_19                   (0x00B7022C)
#define   PMM_TOP_HW_EVENT_CTL_19___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_19___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_19___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_19___S                          0

#define PMM_TOP_HW_EVENT_CTL_20                   (0x00B70230)
#define   PMM_TOP_HW_EVENT_CTL_20___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_20___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_20___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_20___S                          0

#define PMM_TOP_HW_EVENT_CTL_21                   (0x00B70234)
#define   PMM_TOP_HW_EVENT_CTL_21___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_21___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_21___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_21___S                          0

#define PMM_TOP_HW_EVENT_CTL_22                   (0x00B70238)
#define   PMM_TOP_HW_EVENT_CTL_22___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_22___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_22___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_22___S                          0

#define PMM_TOP_HW_EVENT_CTL_23                   (0x00B7023C)
#define   PMM_TOP_HW_EVENT_CTL_23___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_23___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_23___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_23___S                          0

#define PMM_TOP_HW_EVENT_CTL_24                   (0x00B70240)
#define   PMM_TOP_HW_EVENT_CTL_24___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_24___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_24___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_24___S                          0

#define PMM_TOP_HW_EVENT_CTL_25                   (0x00B70244)
#define   PMM_TOP_HW_EVENT_CTL_25___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_25___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_25___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_25___S                          0

#define PMM_TOP_HW_EVENT_CTL_26                   (0x00B70248)
#define   PMM_TOP_HW_EVENT_CTL_26___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_26___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_26___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_26___S                          0

#define PMM_TOP_HW_EVENT_CTL_27                   (0x00B7024C)
#define   PMM_TOP_HW_EVENT_CTL_27___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_27___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_27___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_27___S                          0

#define PMM_TOP_HW_EVENT_CTL_28                   (0x00B70250)
#define   PMM_TOP_HW_EVENT_CTL_28___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_28___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_28___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_28___S                          0

#define PMM_TOP_HW_EVENT_CTL_29                   (0x00B70254)
#define   PMM_TOP_HW_EVENT_CTL_29___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_29___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_29___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_29___S                          0

#define PMM_TOP_HW_EVENT_CTL_30                   (0x00B70258)
#define   PMM_TOP_HW_EVENT_CTL_30___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_30___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_30___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_30___S                          0

#define PMM_TOP_HW_EVENT_CTL_31                   (0x00B7025C)
#define   PMM_TOP_HW_EVENT_CTL_31___RWC             QCSR_REG_RW    
#define   PMM_TOP_HW_EVENT_CTL_31___POR          0x80000000
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___POR 0x1
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___POR 0x0
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___M 0x80000000
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___S              31
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___M 0x0000000F
#define   PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___S               0
#define   PMM_TOP_HW_EVENT_CTL_31___M            0x8000000F   
#define   PMM_TOP_HW_EVENT_CTL_31___S                          0

#define PMM_TOP_LMAC_LPI                          (0x00B70280)
#define   PMM_TOP_LMAC_LPI___RWC                    QCSR_REG_RW    
#define   PMM_TOP_LMAC_LPI___POR                 0x00000000
#define   PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___POR 0x0
#define   PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___POR 0x0
#define   PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___POR 0x0
#define   PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___POR 0x0
#define   PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___POR 0x0
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___POR 0x0
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___POR 0x0
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___POR 0x0
#define   PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___M 0x00000200
#define   PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___S               9
#define   PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___M 0x00000100
#define   PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___S               8
#define   PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___M 0x00000080
#define   PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___S               7
#define   PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___M 0x00000040
#define   PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___S               6
#define   PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___M 0x00000020
#define   PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___S               5
#define   PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___M 0x00000010
#define   PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___S               4
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___M 0x00000008
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___S               3
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___M 0x00000004
#define   PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___S               2
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___M 0x00000002
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___S               1
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___M 0x00000001
#define   PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___S               0
#define   PMM_TOP_LMAC_LPI___M                   0x000003FF   
#define   PMM_TOP_LMAC_LPI___S                                 0

#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG             (0x00B70284)
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG___RWC       QCSR_REG_RW    
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG___POR    0x00000000
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___POR 0x0
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___M 0x0000000F
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___S               0
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG___M      0x0000000F   
#define   PMM_TOP_PMM_WLAN1_XBAR_CONFIG___S                    0

#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG             (0x00B70288)
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG___RWC       QCSR_REG_RW    
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG___POR    0x00000000
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___POR 0x0
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___M 0x0000000F
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___S               0
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG___M      0x0000000F   
#define   PMM_TOP_PMM_WLAN2_XBAR_CONFIG___S                    0

#define PMM_TOP_SOC_WDOG_TRIG                     (0x00B7028C)
#define   PMM_TOP_SOC_WDOG_TRIG___RWC               QCSR_REG_RW    
#define   PMM_TOP_SOC_WDOG_TRIG___POR            0x00000000
#define   PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___POR 0x0
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___POR 0x0
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___POR 0x0
#define   PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___M 0x00000004
#define   PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___S               2
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___M 0x00000002
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___S               1
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___M 0x00000001
#define   PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___S               0
#define   PMM_TOP_SOC_WDOG_TRIG___M              0x00000007   
#define   PMM_TOP_SOC_WDOG_TRIG___S                            0

#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE            (0x00B70290)
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___RWC      QCSR_REG_RW    
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___POR   0x00000000
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___POR 0x0
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___POR 0x0
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___M 0x80000000
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___S              31
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___M 0x00000007
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___S               0
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___M     0x80000007   
#define   PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___S                   0

#define PMM_TOP_UMAC_LPI_SLV_IFC                  (0x00B70294)
#define   PMM_TOP_UMAC_LPI_SLV_IFC___RWC            QCSR_REG_RW    
#define   PMM_TOP_UMAC_LPI_SLV_IFC___POR         0x00000801
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___POR 0x0000
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x1
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___POR 0x0
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___POR 0x1
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___M 0xFFFF0000
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___S              16
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___M 0x00004000
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___S              14
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___M 0x00002000
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___S              13
#define   PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___M 0x00001000
#define   PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___S              12
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000800
#define   PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___S              11
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___M 0x00000400
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___S              10
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___M 0x00000200
#define   PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___S               9
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___M 0x00000100
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___S               8
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___M 0x00000080
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___S               7
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000040
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___S               6
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000020
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___S               5
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___M 0x00000010
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___S               4
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___M 0x00000008
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___S               3
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___M 0x00000004
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___S               2
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___M 0x00000002
#define   PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___S               1
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___M 0x00000001
#define   PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___S               0
#define   PMM_TOP_UMAC_LPI_SLV_IFC___M           0xFFFF7FFF   
#define   PMM_TOP_UMAC_LPI_SLV_IFC___S                         0

#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN            (0x00B70298)
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN___RWC      QCSR_REG_RO    
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN___POR   0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___POR 0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___M 0xFFFFFFFF
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___S               0
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN___M     0xFFFFFFFF   
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MIN___S                   0

#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX            (0x00B7029C)
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX___RWC      QCSR_REG_RO    
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX___POR   0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___POR 0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___M 0xFFFFFFFF
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___S               0
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX___M     0xFFFFFFFF   
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MAX___S                   0

#define PMM_TOP_SOC_WAKEUP_LATENCY_MID            (0x00B702A0)
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID___RWC      QCSR_REG_RO    
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID___POR   0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___POR 0x00000000
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___M 0xFFFFFFFF
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___S               0
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID___M     0xFFFFFFFF   
#define   PMM_TOP_SOC_WAKEUP_LATENCY_MID___S                   0

#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN        (0x00B702A4)
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___RWC  QCSR_REG_RO    
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___POR 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___POR 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___M 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___S               0
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___M 0xFFFFFFFF   
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___S               0

#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX        (0x00B702A8)
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___RWC  QCSR_REG_RO    
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___POR 0x00000000
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___POR 0x00000000
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___M 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___S               0
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___M 0xFFFFFFFF   
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___S               0

#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID        (0x00B702AC)
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___RWC  QCSR_REG_RO    
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___POR 0x00000000
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___POR 0x00000000
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___M 0xFFFFFFFF
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___S               0
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___M 0xFFFFFFFF   
#define   PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___S               0


#define RET_AHB_BASE                (0x00C90000)

#define RET_AHB_AHB_PL1                           (0x00C90000)
#define   RET_AHB_AHB_PL1___RWC                     QCSR_REG_RW    
#define   RET_AHB_AHB_PL1___POR                  0x00000001
#define   RET_AHB_AHB_PL1__AHB_PL1___POR         0x1
#define   RET_AHB_AHB_PL1__AHB_PL1___M           0x0000000F
#define   RET_AHB_AHB_PL1__AHB_PL1___S                         0
#define   RET_AHB_AHB_PL1___M                    0x0000000F   
#define   RET_AHB_AHB_PL1___S                                  0

#define RET_AHB_AHB_PL2                           (0x00C90004)
#define   RET_AHB_AHB_PL2___RWC                     QCSR_REG_RW    
#define   RET_AHB_AHB_PL2___POR                  0x00000002
#define   RET_AHB_AHB_PL2__AHB_PL2___POR         0x2
#define   RET_AHB_AHB_PL2__AHB_PL2___M           0x0000000F
#define   RET_AHB_AHB_PL2__AHB_PL2___S                         0
#define   RET_AHB_AHB_PL2___M                    0x0000000F   
#define   RET_AHB_AHB_PL2___S                                  0

#define RET_AHB_AHB_PL3                           (0x00C90008)
#define   RET_AHB_AHB_PL3___RWC                     QCSR_REG_RW    
#define   RET_AHB_AHB_PL3___POR                  0x00000001
#define   RET_AHB_AHB_PL3__AHB_PL3___POR         0x1
#define   RET_AHB_AHB_PL3__AHB_PL3___M           0x0000000F
#define   RET_AHB_AHB_PL3__AHB_PL3___S                         0
#define   RET_AHB_AHB_PL3___M                    0x0000000F   
#define   RET_AHB_AHB_PL3___S                                  0

#define RET_AHB_AHB_DFLT_MASTER                   (0x00C90048)
#define   RET_AHB_AHB_DFLT_MASTER___RWC             QCSR_REG_RW    
#define   RET_AHB_AHB_DFLT_MASTER___POR          0x00000000
#define   RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___POR 0x0
#define   RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___M 0x0000000F
#define   RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___S               0
#define   RET_AHB_AHB_DFLT_MASTER___M            0x0000000F   
#define   RET_AHB_AHB_DFLT_MASTER___S                          0

#define RET_AHB_AHB_VERSION_ID                    (0x00C90090)
#define   RET_AHB_AHB_VERSION_ID___RWC              QCSR_REG_RO    
#define   RET_AHB_AHB_VERSION_ID___POR           0x3231312A
#define   RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___POR 0x3231312A
#define   RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___M 0xFFFFFFFF
#define   RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___S               0
#define   RET_AHB_AHB_VERSION_ID___M             0xFFFFFFFF   
#define   RET_AHB_AHB_VERSION_ID___S                           0


#define WAHB_TSLV_BASE              (0x00CA0000)

#define WAHB_TSLV_ABT_HW_VERSION                  (0x00CA0000)
#define   WAHB_TSLV_ABT_HW_VERSION___RWC            QCSR_REG_RO    
#define   WAHB_TSLV_ABT_HW_VERSION___POR         0x10000000
#define   WAHB_TSLV_ABT_HW_VERSION__MAJOR___POR  0x1
#define   WAHB_TSLV_ABT_HW_VERSION__MINOR___POR  0x000
#define   WAHB_TSLV_ABT_HW_VERSION__STEP___POR   0x0000
#define   WAHB_TSLV_ABT_HW_VERSION__MAJOR___M    0xF0000000
#define   WAHB_TSLV_ABT_HW_VERSION__MAJOR___S                 28
#define   WAHB_TSLV_ABT_HW_VERSION__MINOR___M    0x0FFF0000
#define   WAHB_TSLV_ABT_HW_VERSION__MINOR___S                 16
#define   WAHB_TSLV_ABT_HW_VERSION__STEP___M     0x0000FFFF
#define   WAHB_TSLV_ABT_HW_VERSION__STEP___S                   0
#define   WAHB_TSLV_ABT_HW_VERSION___M           0xFFFFFFFF   
#define   WAHB_TSLV_ABT_HW_VERSION___S                         0

#define WAHB_TSLV_ABT_INST_ID                     (0x00CA0004)
#define   WAHB_TSLV_ABT_INST_ID___RWC               QCSR_REG_RW    
#define   WAHB_TSLV_ABT_INST_ID___POR            0x00000000
#define   WAHB_TSLV_ABT_INST_ID__INSTID___POR    0x00000000
#define   WAHB_TSLV_ABT_INST_ID__INSTID___M      0xFFFFFFFF
#define   WAHB_TSLV_ABT_INST_ID__INSTID___S                    0
#define   WAHB_TSLV_ABT_INST_ID___M              0xFFFFFFFF   
#define   WAHB_TSLV_ABT_INST_ID___S                            0

#define WAHB_TSLV_ABT_NUM_SLAVES                  (0x00CA0008)
#define   WAHB_TSLV_ABT_NUM_SLAVES___RWC            QCSR_REG_RO    
#define   WAHB_TSLV_ABT_NUM_SLAVES___POR         0x00000005
#define   WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___POR 0x5
#define   WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___M 0x0000003F
#define   WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___S               0
#define   WAHB_TSLV_ABT_NUM_SLAVES___M           0x0000003F   
#define   WAHB_TSLV_ABT_NUM_SLAVES___S                         0

#define WAHB_TSLV_ABT_TIMER_LOADVAL               (0x00CA000C)
#define   WAHB_TSLV_ABT_TIMER_LOADVAL___RWC         QCSR_REG_RW    
#define   WAHB_TSLV_ABT_TIMER_LOADVAL___POR      0x000000FF
#define   WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___POR 0xFF
#define   WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___M 0x000000FF
#define   WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___S               0
#define   WAHB_TSLV_ABT_TIMER_LOADVAL___M        0x000000FF   
#define   WAHB_TSLV_ABT_TIMER_LOADVAL___S                      0

#define WAHB_TSLV_ABT_TIMER_MODE                  (0x00CA0010)
#define   WAHB_TSLV_ABT_TIMER_MODE___RWC            QCSR_REG_RW    
#define   WAHB_TSLV_ABT_TIMER_MODE___POR         0x00000000
#define   WAHB_TSLV_ABT_TIMER_MODE__MODE___POR   0x0
#define   WAHB_TSLV_ABT_TIMER_MODE__MODE___M     0x00000001
#define   WAHB_TSLV_ABT_TIMER_MODE__MODE___S                   0
#define   WAHB_TSLV_ABT_TIMER_MODE___M           0x00000001   
#define   WAHB_TSLV_ABT_TIMER_MODE___S                         0

#define WAHB_TSLV_ABT_INTR_STATUS                 (0x00CA0014)
#define   WAHB_TSLV_ABT_INTR_STATUS___RWC           QCSR_REG_RO    
#define   WAHB_TSLV_ABT_INTR_STATUS___POR        0x00000000
#define   WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___POR 0x0
#define   WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___M 0x00000001
#define   WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___S               0
#define   WAHB_TSLV_ABT_INTR_STATUS___M          0x00000001   
#define   WAHB_TSLV_ABT_INTR_STATUS___S                        0

#define WAHB_TSLV_ABT_INTR_CLEAR                  (0x00CA0018)
#define   WAHB_TSLV_ABT_INTR_CLEAR___RWC            QCSR_REG_WO    
#define   WAHB_TSLV_ABT_INTR_CLEAR___POR         0x00000000
#define   WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___POR 0x0
#define   WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___M 0x00000001
#define   WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___S               0
#define   WAHB_TSLV_ABT_INTR_CLEAR___M           0x00000001   
#define   WAHB_TSLV_ABT_INTR_CLEAR___S                         0

#define WAHB_TSLV_ABT_INTR_ENABLE                 (0x00CA001C)
#define   WAHB_TSLV_ABT_INTR_ENABLE___RWC           QCSR_REG_RW    
#define   WAHB_TSLV_ABT_INTR_ENABLE___POR        0x00000000
#define   WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___POR 0x0
#define   WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___M 0x00000001
#define   WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___S               0
#define   WAHB_TSLV_ABT_INTR_ENABLE___M          0x00000001   
#define   WAHB_TSLV_ABT_INTR_ENABLE___S                        0

#define WAHB_TSLV_ABT_SYND_VALID                  (0x00CA0020)
#define   WAHB_TSLV_ABT_SYND_VALID___RWC            QCSR_REG_RO    
#define   WAHB_TSLV_ABT_SYND_VALID___POR         0x00000000
#define   WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___POR 0x0
#define   WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___M 0x00000001
#define   WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___S               0
#define   WAHB_TSLV_ABT_SYND_VALID___M           0x00000001   
#define   WAHB_TSLV_ABT_SYND_VALID___S                         0

#define WAHB_TSLV_ABT_SYND_CLEAR                  (0x00CA0024)
#define   WAHB_TSLV_ABT_SYND_CLEAR___RWC            QCSR_REG_WO    
#define   WAHB_TSLV_ABT_SYND_CLEAR___POR         0x00000000
#define   WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___POR 0x0
#define   WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___M 0x00000001
#define   WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___S               0
#define   WAHB_TSLV_ABT_SYND_CLEAR___M           0x00000001   
#define   WAHB_TSLV_ABT_SYND_CLEAR___S                         0

#define WAHB_TSLV_ABT_SYND_ID                     (0x00CA0028)
#define   WAHB_TSLV_ABT_SYND_ID___RWC               QCSR_REG_RO    
#define   WAHB_TSLV_ABT_SYND_ID___POR            0x00000000
#define   WAHB_TSLV_ABT_SYND_ID__BID___POR       0x0
#define   WAHB_TSLV_ABT_SYND_ID__PID___POR       0x00
#define   WAHB_TSLV_ABT_SYND_ID__MID___POR       0x00
#define   WAHB_TSLV_ABT_SYND_ID__BID___M         0x0000E000
#define   WAHB_TSLV_ABT_SYND_ID__BID___S                      13
#define   WAHB_TSLV_ABT_SYND_ID__PID___M         0x00001F00
#define   WAHB_TSLV_ABT_SYND_ID__PID___S                       8
#define   WAHB_TSLV_ABT_SYND_ID__MID___M         0x000000FF
#define   WAHB_TSLV_ABT_SYND_ID__MID___S                       0
#define   WAHB_TSLV_ABT_SYND_ID___M              0x0000FFFF   
#define   WAHB_TSLV_ABT_SYND_ID___S                            0

#define WAHB_TSLV_ABT_SYND_ADDR0                  (0x00CA002C)
#define   WAHB_TSLV_ABT_SYND_ADDR0___RWC            QCSR_REG_RO    
#define   WAHB_TSLV_ABT_SYND_ADDR0___POR         0x00000000
#define   WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___POR 0x00000000
#define   WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___M 0xFFFFFFFF
#define   WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___S               0
#define   WAHB_TSLV_ABT_SYND_ADDR0___M           0xFFFFFFFF   
#define   WAHB_TSLV_ABT_SYND_ADDR0___S                         0

#define WAHB_TSLV_ABT_SYND_ADDR1                  (0x00CA0030)
#define   WAHB_TSLV_ABT_SYND_ADDR1___RWC            QCSR_REG_RO    
#define   WAHB_TSLV_ABT_SYND_ADDR1___POR         0x00000000
#define   WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___POR 0x00000000
#define   WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___M 0xFFFFFFFF
#define   WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___S               0
#define   WAHB_TSLV_ABT_SYND_ADDR1___M           0xFFFFFFFF   
#define   WAHB_TSLV_ABT_SYND_ADDR1___S                         0

#define WAHB_TSLV_ABT_SYND_HREADY                 (0x00CA0034)
#define   WAHB_TSLV_ABT_SYND_HREADY___RWC           QCSR_REG_RO    
#define   WAHB_TSLV_ABT_SYND_HREADY___POR        0xFFFFFFFF
#define   WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___POR 0xFFFFFFFF
#define   WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___M 0xFFFFFFFF
#define   WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___S               0
#define   WAHB_TSLV_ABT_SYND_HREADY___M          0xFFFFFFFF   
#define   WAHB_TSLV_ABT_SYND_HREADY___S                        0


#define CC_BASE                     (0x00CB0000)

#define CC_WCSS_NOC_CMD_RCGR                      (0x00CB0040)
#define   CC_WCSS_NOC_CMD_RCGR___RWC                QCSR_REG_RW    
#define   CC_WCSS_NOC_CMD_RCGR___POR             0x00000000
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___POR   0x0
#define   CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_EN___POR    0x0
#define   CC_WCSS_NOC_CMD_RCGR__UPDATE___POR     0x0
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___M     0x80000000
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___S                  31
#define   CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_EN___M      0x00000002
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_EN___S                    1
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_EN__DISABLE             0x0
#define   CC_WCSS_NOC_CMD_RCGR__ROOT_EN__ENABLE              0x1
#define   CC_WCSS_NOC_CMD_RCGR__UPDATE___M       0x00000001
#define   CC_WCSS_NOC_CMD_RCGR__UPDATE___S                     0
#define   CC_WCSS_NOC_CMD_RCGR__UPDATE__DISABLE              0x0
#define   CC_WCSS_NOC_CMD_RCGR__UPDATE__ENABLE               0x1
#define   CC_WCSS_NOC_CMD_RCGR___M               0x80000013   
#define   CC_WCSS_NOC_CMD_RCGR___S                             0

#define CC_WCSS_NOC_CFG_RCGR                      (0x00CB0044)
#define   CC_WCSS_NOC_CFG_RCGR___RWC                QCSR_REG_RW    
#define   CC_WCSS_NOC_CFG_RCGR___POR             0x00100000
#define   CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___POR 0x1
#define   CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___POR 0x0
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL___POR    0x0
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV___POR    0x00
#define   CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000
#define   CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___S              20
#define   CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL__DISABLE             0x0
#define   CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL__ENABLE             0x1
#define   CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000
#define   CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___S              16
#define   CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED             0x0
#define   CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED             0x1
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL___M      0x00000700
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL___S                    8
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC0                0x0
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC1                0x1
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC2                0x2
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC3                0x3
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC4                0x4
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC5                0x5
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC6                0x6
#define   CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC7                0x7
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV___M      0x0000001F
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV___S                    0
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__BYPASS             0x00
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV1               0x01
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV1_5             0x02
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV2               0x03
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV2_5             0x04
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV3               0x05
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV3_5             0x06
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV4               0x07
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV4_5             0x08
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV5               0x09
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV5_5             0x0A
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV6               0x0B
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV6_5             0x0C
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV7               0x0D
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV7_5             0x0E
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV8               0x0F
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV8_5             0x10
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV9               0x11
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV9_5             0x12
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV10              0x13
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV10_5            0x14
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV11              0x15
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV11_5            0x16
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV12              0x17
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV12_5            0x18
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV13              0x19
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV13_5            0x1A
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV14              0x1B
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV14_5            0x1C
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV15              0x1D
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV15_5            0x1E
#define   CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV16              0x1F
#define   CC_WCSS_NOC_CFG_RCGR___M               0x0011071F   
#define   CC_WCSS_NOC_CFG_RCGR___S                             0

#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR          (0x00CB0058)
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___RWC    QCSR_REG_RW    
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___POR 0x00000000
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___POR 0x0
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___M   0x0000000F   
#define   CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___S                 0

#define CC_WCSS_AHB_CDIVR                         (0x00CB005C)
#define   CC_WCSS_AHB_CDIVR___RWC                   QCSR_REG_RW    
#define   CC_WCSS_AHB_CDIVR___POR                0x00000002
#define   CC_WCSS_AHB_CDIVR__CLK_DIV___POR       0x2
#define   CC_WCSS_AHB_CDIVR__CLK_DIV___M         0x0000000F
#define   CC_WCSS_AHB_CDIVR__CLK_DIV___S                       0
#define   CC_WCSS_AHB_CDIVR___M                  0x0000000F   
#define   CC_WCSS_AHB_CDIVR___S                                0

#define CC_WCSS_TOP_AXI_CBCR                      (0x00CB0060)
#define   CC_WCSS_TOP_AXI_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_TOP_AXI_CBCR___POR             0x00000001
#define   CC_WCSS_TOP_AXI_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_AXI_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_TOP_AXI_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_AXI_CBCR___M               0x80000005   
#define   CC_WCSS_TOP_AXI_CBCR___S                             0

#define CC_WCSS_AXIB_AXI_S_CBCR                   (0x00CB0064)
#define   CC_WCSS_AXIB_AXI_S_CBCR___RWC             QCSR_REG_RW    
#define   CC_WCSS_AXIB_AXI_S_CBCR___POR          0x00000001
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___M   0x80000000
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___S                31
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___M  0x00000004
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___S                2
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_AXIB_AXI_S_CBCR___M            0x80000005   
#define   CC_WCSS_AXIB_AXI_S_CBCR___S                          0

#define CC_WCSS_TOP_AHB_CBCR                      (0x00CB0068)
#define   CC_WCSS_TOP_AHB_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_TOP_AHB_CBCR___POR             0x00000001
#define   CC_WCSS_TOP_AHB_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_AHB_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_TOP_AHB_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_AHB_CBCR___M               0x80000005   
#define   CC_WCSS_TOP_AHB_CBCR___S                             0

#define CC_WCSS_TOP_AHB_TSLV_CBCR                 (0x00CB006C)
#define   CC_WCSS_TOP_AHB_TSLV_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_TOP_AHB_TSLV_CBCR___POR        0x00000001
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___S              31
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___S               2
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_AHB_TSLV_CBCR___M          0x80000005   
#define   CC_WCSS_TOP_AHB_TSLV_CBCR___S                        0

#define CC_WCSS_TOP_SLP_CBCR                      (0x00CB0070)
#define   CC_WCSS_TOP_SLP_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_TOP_SLP_CBCR___POR             0x00000001
#define   CC_WCSS_TOP_SLP_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_SLP_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_TOP_SLP_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_SLP_CBCR___M               0x80000005   
#define   CC_WCSS_TOP_SLP_CBCR___S                             0

#define CC_WCSS_TOP_REF_CBCR                      (0x00CB0074)
#define   CC_WCSS_TOP_REF_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_TOP_REF_CBCR___POR             0x00000001
#define   CC_WCSS_TOP_REF_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_TOP_REF_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_REF_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_TOP_REF_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_TOP_REF_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_TOP_REF_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_TOP_REF_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_REF_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_TOP_REF_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_REF_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_REF_CBCR___M               0x80000005   
#define   CC_WCSS_TOP_REF_CBCR___S                             0

#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR             (0x00CB0078)
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR___RWC       QCSR_REG_RW    
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR___POR    0x00000001
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___S              31
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___S               2
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR___M      0x80000005   
#define   CC_WCSS_TOP_DBG_GDSC_REF_CBCR___S                    0

#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR         (0x00CB007C)
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___RWC   QCSR_REG_RW    
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___POR 0x00000003
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___POR 0x3
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___M 0x00000003
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___M  0x00000003   
#define   CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___S                0

#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR          (0x00CB0080)
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR___RWC    QCSR_REG_RW    
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR___POR 0x00000001
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___S              31
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___S               2
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR___M   0x80000005   
#define   CC_WCSS_TOP_RESET_DEMET_REF_CBCR___S                 0

#define CC_WCSS_PMM_LPO_CBCR                      (0x00CB0084)
#define   CC_WCSS_PMM_LPO_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_PMM_LPO_CBCR___POR             0x00000001
#define   CC_WCSS_PMM_LPO_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_PMM_LPO_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_PMM_LPO_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PMM_LPO_CBCR___M               0x80000005   
#define   CC_WCSS_PMM_LPO_CBCR___S                             0

#define CC_WCSS_WFSS_PMM_CDIVR                    (0x00CB0088)
#define   CC_WCSS_WFSS_PMM_CDIVR___RWC              QCSR_REG_RW    
#define   CC_WCSS_WFSS_PMM_CDIVR___POR           0x00000003
#define   CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___POR  0x3
#define   CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___M    0x00000003
#define   CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___S                  0
#define   CC_WCSS_WFSS_PMM_CDIVR___M             0x00000003   
#define   CC_WCSS_WFSS_PMM_CDIVR___S                           0

#define CC_WCSS_WFSS_PMM_CBCR                     (0x00CB008C)
#define   CC_WCSS_WFSS_PMM_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_WFSS_PMM_CBCR___POR            0x00000001
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___POR   0x0
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_WFSS_PMM_CBCR___M              0x80000005   
#define   CC_WCSS_WFSS_PMM_CBCR___S                            0

#define CC_WCSS_WLAN1_BCR                         (0x00CB0090)
#define   CC_WCSS_WLAN1_BCR___RWC                   QCSR_REG_RW    
#define   CC_WCSS_WLAN1_BCR___POR                0x00000000
#define   CC_WCSS_WLAN1_BCR__BLK_ARES___POR      0x0
#define   CC_WCSS_WLAN1_BCR__BLK_ARES___M        0x00000001
#define   CC_WCSS_WLAN1_BCR__BLK_ARES___S                      0
#define   CC_WCSS_WLAN1_BCR__BLK_ARES__DISABLE               0x0
#define   CC_WCSS_WLAN1_BCR__BLK_ARES__ENABLE                0x1
#define   CC_WCSS_WLAN1_BCR___M                  0x00000001   
#define   CC_WCSS_WLAN1_BCR___S                                0

#define CC_WCSS_WLAN1_GDSCR                       (0x00CB0094)
#define   CC_WCSS_WLAN1_GDSCR___RWC                 QCSR_REG_RW    
#define   CC_WCSS_WLAN1_GDSCR___POR              0x0022F001
#define   CC_WCSS_WLAN1_GDSCR__PWR_ON___POR      0x0
#define   CC_WCSS_WLAN1_GDSCR__GDSC_STATE___POR  0x0
#define   CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___POR 0x2
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___POR 0x2
#define   CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___POR 0xF
#define   CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___POR 0x0
#define   CC_WCSS_WLAN1_GDSCR__RESTORE___POR     0x0
#define   CC_WCSS_WLAN1_GDSCR__SAVE___POR        0x0
#define   CC_WCSS_WLAN1_GDSCR__RETAIN___POR      0x0
#define   CC_WCSS_WLAN1_GDSCR__EN_REST___POR     0x0
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW___POR      0x0
#define   CC_WCSS_WLAN1_GDSCR__CLAMP_IO___POR    0x0
#define   CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___POR 0x0
#define   CC_WCSS_WLAN1_GDSCR__PD_ARES___POR     0x0
#define   CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_GDSCR__HW_CONTROL___POR  0x0
#define   CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___POR 0x1
#define   CC_WCSS_WLAN1_GDSCR__PWR_ON___M        0x80000000
#define   CC_WCSS_WLAN1_GDSCR__PWR_ON___S                     31
#define   CC_WCSS_WLAN1_GDSCR__GDSC_STATE___M    0x78000000
#define   CC_WCSS_WLAN1_GDSCR__GDSC_STATE___S                 27
#define   CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___M  0x00F00000
#define   CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___S               20
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___M   0x000F0000
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___S                16
#define   CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___M  0x0000F000
#define   CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___S               12
#define   CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___M 0x00000800
#define   CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___S              11
#define   CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE__DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE__ENABLE             0x1
#define   CC_WCSS_WLAN1_GDSCR__RESTORE___M       0x00000400
#define   CC_WCSS_WLAN1_GDSCR__RESTORE___S                    10
#define   CC_WCSS_WLAN1_GDSCR__RESTORE__DISABLE              0x0
#define   CC_WCSS_WLAN1_GDSCR__RESTORE__ENABLE               0x1
#define   CC_WCSS_WLAN1_GDSCR__SAVE___M          0x00000200
#define   CC_WCSS_WLAN1_GDSCR__SAVE___S                        9
#define   CC_WCSS_WLAN1_GDSCR__SAVE__DISABLE                 0x0
#define   CC_WCSS_WLAN1_GDSCR__SAVE__ENABLE                  0x1
#define   CC_WCSS_WLAN1_GDSCR__RETAIN___M        0x00000100
#define   CC_WCSS_WLAN1_GDSCR__RETAIN___S                      8
#define   CC_WCSS_WLAN1_GDSCR__RETAIN__DISABLE               0x0
#define   CC_WCSS_WLAN1_GDSCR__RETAIN__ENABLE                0x1
#define   CC_WCSS_WLAN1_GDSCR__EN_REST___M       0x00000080
#define   CC_WCSS_WLAN1_GDSCR__EN_REST___S                     7
#define   CC_WCSS_WLAN1_GDSCR__EN_REST__DISABLE              0x0
#define   CC_WCSS_WLAN1_GDSCR__EN_REST__ENABLE               0x1
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW___M        0x00000040
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW___S                      6
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW__DISABLE               0x0
#define   CC_WCSS_WLAN1_GDSCR__EN_FEW__ENABLE                0x1
#define   CC_WCSS_WLAN1_GDSCR__CLAMP_IO___M      0x00000020
#define   CC_WCSS_WLAN1_GDSCR__CLAMP_IO___S                    5
#define   CC_WCSS_WLAN1_GDSCR__CLAMP_IO__DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__CLAMP_IO__ENABLE              0x1
#define   CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___M   0x00000010
#define   CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___S                 4
#define   CC_WCSS_WLAN1_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__CLK_DISABLE__CLK_DISABLE             0x1
#define   CC_WCSS_WLAN1_GDSCR__PD_ARES___M       0x00000008
#define   CC_WCSS_WLAN1_GDSCR__PD_ARES___S                     3
#define   CC_WCSS_WLAN1_GDSCR__PD_ARES__NO_RESET             0x0
#define   CC_WCSS_WLAN1_GDSCR__PD_ARES__RESET                0x1
#define   CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___M   0x00000004
#define   CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___S                 2
#define   CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE__DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE__ENABLE             0x1
#define   CC_WCSS_WLAN1_GDSCR__HW_CONTROL___M    0x00000002
#define   CC_WCSS_WLAN1_GDSCR__HW_CONTROL___S                  1
#define   CC_WCSS_WLAN1_GDSCR__HW_CONTROL__DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__HW_CONTROL__ENABLE             0x1
#define   CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___M   0x00000001
#define   CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___S                 0
#define   CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE__DISABLE             0x0
#define   CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE__ENABLE             0x1
#define   CC_WCSS_WLAN1_GDSCR___M                0xF8FFFFFF   
#define   CC_WCSS_WLAN1_GDSCR___S                              0

#define CC_WCSS_WLAN1_CFG_GDSCR                   (0x00CB0098)
#define   CC_WCSS_WLAN1_CFG_GDSCR___RWC             QCSR_REG_RW    
#define   CC_WCSS_WLAN1_CFG_GDSCR___POR          0x00088000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x1
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x1
#define   CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S              28
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S              26
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___S              25
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___S              24
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S              18
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S              17
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S              16
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S              15
#define   CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S              10
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S               7
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004
#define   CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S               2
#define   CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   CC_WCSS_WLAN1_CFG_GDSCR___M            0xFFFFFFFF   
#define   CC_WCSS_WLAN1_CFG_GDSCR___S                          0

#define CC_WCSS_WLAN1_CFG2_GDSCR                  (0x00CB009C)
#define   CC_WCSS_WLAN1_CFG2_GDSCR___RWC            QCSR_REG_RW    
#define   CC_WCSS_WLAN1_CFG2_GDSCR___POR         0x0000022A
#define   CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S              16
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___S              12
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S               8
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S               4
#define   CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S               0
#define   CC_WCSS_WLAN1_CFG2_GDSCR___M           0x0001FFFF   
#define   CC_WCSS_WLAN1_CFG2_GDSCR___S                         0

#define CC_WCSS_PHYA_NOC_CBCR                     (0x00CB00A0)
#define   CC_WCSS_PHYA_NOC_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_PHYA_NOC_CBCR___POR            0x80000000
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_NOC_CBCR___M              0x80000005   
#define   CC_WCSS_PHYA_NOC_CBCR___S                            0

#define CC_WCSS_PHYA_AHB_CBCR                     (0x00CB00A4)
#define   CC_WCSS_PHYA_AHB_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_PHYA_AHB_CBCR___POR            0x80000000
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_AHB_CBCR___M              0x80000005   
#define   CC_WCSS_PHYA_AHB_CBCR___S                            0

#define CC_WCSS_PHYA_DBG_ATB_CBCR                 (0x00CB00A8)
#define   CC_WCSS_PHYA_DBG_ATB_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_PHYA_DBG_ATB_CBCR___POR        0x00000001
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_DBG_ATB_CBCR___M          0x80000005   
#define   CC_WCSS_PHYA_DBG_ATB_CBCR___S                        0

#define CC_WCSS_PHYA_DBG_APB_CBCR                 (0x00CB00AC)
#define   CC_WCSS_PHYA_DBG_APB_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_PHYA_DBG_APB_CBCR___POR        0x00000001
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_DBG_APB_CBCR___M          0x80000005   
#define   CC_WCSS_PHYA_DBG_APB_CBCR___S                        0

#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR              (0x00CB00B0)
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR___RWC        QCSR_REG_RW    
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR___POR     0x00000001
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___S              31
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR___M       0x80000005   
#define   CC_WCSS_PHYA_DBG_DAPBUS_CBCR___S                     0

#define CC_WCSS_PHYA_DBG_TS_CBCR                  (0x00CB00B4)
#define   CC_WCSS_PHYA_DBG_TS_CBCR___RWC            QCSR_REG_RW    
#define   CC_WCSS_PHYA_DBG_TS_CBCR___POR         0x00000001
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___M  0x80000000
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___S               31
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_DBG_TS_CBCR___M           0x80000005   
#define   CC_WCSS_PHYA_DBG_TS_CBCR___S                         0

#define CC_WCSS_PHYA_ADC0_CBCR                    (0x00CB00B8)
#define   CC_WCSS_PHYA_ADC0_CBCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_PHYA_ADC0_CBCR___POR           0x80000000
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___POR  0x1
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___M    0x80000000
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___S                 31
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___M   0x00000004
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___S                 2
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_ADC0_CBCR___M             0x80000005   
#define   CC_WCSS_PHYA_ADC0_CBCR___S                           0

#define CC_WCSS_PHYA_ADC1_CBCR                    (0x00CB00BC)
#define   CC_WCSS_PHYA_ADC1_CBCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_PHYA_ADC1_CBCR___POR           0x80000000
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___POR  0x1
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___M    0x80000000
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___S                 31
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___M   0x00000004
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___S                 2
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_ADC1_CBCR___M             0x80000005   
#define   CC_WCSS_PHYA_ADC1_CBCR___S                           0

#define CC_WCSS_PHYA_480_CBCR                     (0x00CB00C0)
#define   CC_WCSS_PHYA_480_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_PHYA_480_CBCR___POR            0x80000220
#define   CC_WCSS_PHYA_480_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP___POR    0x2
#define   CC_WCSS_PHYA_480_CBCR__SLEEP___POR     0x2
#define   CC_WCSS_PHYA_480_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_480_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_PHYA_480_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP___M      0x00000F00
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP___S                    8
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK0              0x0
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK1              0x1
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK2              0x2
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK3              0x3
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK4              0x4
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK5              0x5
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK6              0x6
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK7              0x7
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK8              0x8
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK9              0x9
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_PHYA_480_CBCR__SLEEP___M       0x000000F0
#define   CC_WCSS_PHYA_480_CBCR__SLEEP___S                     4
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK0               0x0
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK1               0x1
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK2               0x2
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK3               0x3
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK4               0x4
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK5               0x5
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK6               0x6
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK7               0x7
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK8               0x8
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK9               0x9
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK10              0xA
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK11              0xB
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK12              0xC
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK13              0xD
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK14              0xE
#define   CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK15              0xF
#define   CC_WCSS_PHYA_480_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_PHYA_480_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_PHYA_480_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_480_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_PHYA_480_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_480_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_480_CBCR___M              0x80007FF5   
#define   CC_WCSS_PHYA_480_CBCR___S                            0

#define CC_WCSS_PHYA_480_SREGR                    (0x00CB00C4)
#define   CC_WCSS_PHYA_480_SREGR___RWC              QCSR_REG_RW    
#define   CC_WCSS_PHYA_480_SREGR___POR           0x00000000
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_PHYA_480_SREGR___M             0xFFFFF37E   
#define   CC_WCSS_PHYA_480_SREGR___S                           1

#define CC_WCSS_PHYA_320_CMD_RCGR                 (0x00CB00C8)
#define   CC_WCSS_PHYA_320_CMD_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_PHYA_320_CMD_RCGR___POR        0x80000000
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___POR 0x1
#define   CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___POR 0x0
#define   CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___POR 0x0
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___M 0x80000000
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___S              31
#define   CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___M 0x00000002
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___S               1
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN__DISABLE             0x0
#define   CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN__ENABLE             0x1
#define   CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___M  0x00000001
#define   CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___S                0
#define   CC_WCSS_PHYA_320_CMD_RCGR__UPDATE__DISABLE             0x0
#define   CC_WCSS_PHYA_320_CMD_RCGR__UPDATE__ENABLE             0x1
#define   CC_WCSS_PHYA_320_CMD_RCGR___M          0x80000013   
#define   CC_WCSS_PHYA_320_CMD_RCGR___S                        0

#define CC_WCSS_PHYA_320_CFG_RCGR                 (0x00CB00CC)
#define   CC_WCSS_PHYA_320_CFG_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_PHYA_320_CFG_RCGR___POR        0x00100000
#define   CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___POR 0x1
#define   CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___POR 0x0
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___POR 0x0
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___POR 0x00
#define   CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000
#define   CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___S              20
#define   CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL__DISABLE             0x0
#define   CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL__ENABLE             0x1
#define   CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000
#define   CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___S              16
#define   CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED             0x0
#define   CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED             0x1
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___M 0x00000700
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___S               8
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC0             0x0
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC1             0x1
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC2             0x2
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC3             0x3
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC4             0x4
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC5             0x5
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC6             0x6
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC7             0x7
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___M 0x0000001F
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___S               0
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__BYPASS            0x00
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV1            0x01
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV1_5            0x02
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV2            0x03
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV2_5            0x04
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV3            0x05
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV3_5            0x06
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV4            0x07
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV4_5            0x08
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV5            0x09
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV5_5            0x0A
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV6            0x0B
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV6_5            0x0C
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV7            0x0D
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV7_5            0x0E
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV8            0x0F
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV8_5            0x10
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV9            0x11
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV9_5            0x12
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV10            0x13
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV10_5            0x14
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV11            0x15
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV11_5            0x16
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV12            0x17
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV12_5            0x18
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV13            0x19
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV13_5            0x1A
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV14            0x1B
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV14_5            0x1C
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV15            0x1D
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV15_5            0x1E
#define   CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV16            0x1F
#define   CC_WCSS_PHYA_320_CFG_RCGR___M          0x0011071F   
#define   CC_WCSS_PHYA_320_CFG_RCGR___S                        0

#define CC_WCSS_PHYA_320_CBCR                     (0x00CB00E0)
#define   CC_WCSS_PHYA_320_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_PHYA_320_CBCR___POR            0x80000220
#define   CC_WCSS_PHYA_320_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP___POR    0x2
#define   CC_WCSS_PHYA_320_CBCR__SLEEP___POR     0x2
#define   CC_WCSS_PHYA_320_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_320_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_PHYA_320_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP___M      0x00000F00
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP___S                    8
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK0              0x0
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK1              0x1
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK2              0x2
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK3              0x3
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK4              0x4
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK5              0x5
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK6              0x6
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK7              0x7
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK8              0x8
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK9              0x9
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_PHYA_320_CBCR__SLEEP___M       0x000000F0
#define   CC_WCSS_PHYA_320_CBCR__SLEEP___S                     4
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK0               0x0
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK1               0x1
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK2               0x2
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK3               0x3
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK4               0x4
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK5               0x5
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK6               0x6
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK7               0x7
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK8               0x8
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK9               0x9
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK10              0xA
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK11              0xB
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK12              0xC
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK13              0xD
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK14              0xE
#define   CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK15              0xF
#define   CC_WCSS_PHYA_320_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_PHYA_320_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_PHYA_320_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_320_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_PHYA_320_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_320_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_320_CBCR___M              0x80007FF5   
#define   CC_WCSS_PHYA_320_CBCR___S                            0

#define CC_WCSS_PHYA_320_SREGR                    (0x00CB00E4)
#define   CC_WCSS_PHYA_320_SREGR___RWC              QCSR_REG_RW    
#define   CC_WCSS_PHYA_320_SREGR___POR           0x00000000
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_PHYA_320_SREGR___M             0xFFFFF37E   
#define   CC_WCSS_PHYA_320_SREGR___S                           1

#define CC_WCSS_PHYA_ROBE_CBCR                    (0x00CB00E8)
#define   CC_WCSS_PHYA_ROBE_CBCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_PHYA_ROBE_CBCR___POR           0x80000220
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___POR  0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___POR   0x2
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP___POR    0x2
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___M    0x80000000
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___S                 31
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___M     0x00000F00
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___S                   8
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK0             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK1             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK2             0x2
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK3             0x3
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK4             0x4
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK5             0x5
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK6             0x6
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK7             0x7
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK8             0x8
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK9             0x9
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP___M      0x000000F0
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP___S                    4
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK0              0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK1              0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK2              0x2
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK3              0x3
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK4              0x4
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK5              0x5
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK6              0x6
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK7              0x7
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK8              0x8
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK9              0x9
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK10             0xA
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK11             0xB
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK12             0xC
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK13             0xD
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK14             0xE
#define   CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK15             0xF
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___M   0x00000004
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___S                 2
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_CBCR___M             0x80007FF5   
#define   CC_WCSS_PHYA_ROBE_CBCR___S                           0

#define CC_WCSS_PHYA_ROBE_SREGR                   (0x00CB00EC)
#define   CC_WCSS_PHYA_ROBE_SREGR___RWC             QCSR_REG_RW    
#define   CC_WCSS_PHYA_ROBE_SREGR___POR          0x00000000
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_PHYA_ROBE_SREGR___M            0xFFFFF37E   
#define   CC_WCSS_PHYA_ROBE_SREGR___S                          1

#define CC_WCSS_MAC0_AHB_CBCR                     (0x00CB00F0)
#define   CC_WCSS_MAC0_AHB_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_MAC0_AHB_CBCR___POR            0x80000000
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_MAC0_AHB_CBCR___M              0x80000005   
#define   CC_WCSS_MAC0_AHB_CBCR___S                            0

#define CC_WCSS_MAC0_MAC_CMD_RCGR                 (0x00CB00F4)
#define   CC_WCSS_MAC0_MAC_CMD_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_MAC0_MAC_CMD_RCGR___POR        0x00000000
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___POR 0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___POR 0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___POR 0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___M 0x80000000
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___S              31
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___M 0x00000002
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___S               1
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN__DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN__ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___M  0x00000001
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___S                0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE__DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE__ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CMD_RCGR___M          0x80000013   
#define   CC_WCSS_MAC0_MAC_CMD_RCGR___S                        0

#define CC_WCSS_MAC0_MAC_CFG_RCGR                 (0x00CB00F8)
#define   CC_WCSS_MAC0_MAC_CFG_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_MAC0_MAC_CFG_RCGR___POR        0x00100000
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___POR 0x1
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___POR 0x0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___POR 0x0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___POR 0x00
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___S              20
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL__DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL__ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___S              16
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED             0x0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED             0x1
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___M 0x00000700
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___S               8
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC0             0x0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC1             0x1
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC2             0x2
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC3             0x3
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC4             0x4
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC5             0x5
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC6             0x6
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC7             0x7
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___M 0x0000001F
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___S               0
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__BYPASS            0x00
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV1            0x01
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV1_5            0x02
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV2            0x03
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV2_5            0x04
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV3            0x05
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV3_5            0x06
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV4            0x07
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV4_5            0x08
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV5            0x09
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV5_5            0x0A
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV6            0x0B
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV6_5            0x0C
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV7            0x0D
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV7_5            0x0E
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV8            0x0F
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV8_5            0x10
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV9            0x11
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV9_5            0x12
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV10            0x13
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV10_5            0x14
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV11            0x15
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV11_5            0x16
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV12            0x17
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV12_5            0x18
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV13            0x19
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV13_5            0x1A
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV14            0x1B
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV14_5            0x1C
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV15            0x1D
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV15_5            0x1E
#define   CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV16            0x1F
#define   CC_WCSS_MAC0_MAC_CFG_RCGR___M          0x0011071F   
#define   CC_WCSS_MAC0_MAC_CFG_RCGR___S                        0

#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR           (0x00CB010C)
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___RWC     QCSR_REG_RW    
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___POR  0x00000000
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___POR 0x0
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___M    0x0000000F   
#define   CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___S                  0

#define CC_WCSS_MAC0_MAC_CBCR                     (0x00CB0110)
#define   CC_WCSS_MAC0_MAC_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_MAC0_MAC_CBCR___POR            0x80000220
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP___POR    0x2
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP___POR     0x2
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP___M      0x00000F00
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP___S                    8
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK0              0x0
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK1              0x1
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK2              0x2
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK3              0x3
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK4              0x4
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK5              0x5
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK6              0x6
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK7              0x7
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK8              0x8
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK9              0x9
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP___M       0x000000F0
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP___S                     4
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK0               0x0
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK1               0x1
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK2               0x2
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK3               0x3
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK4               0x4
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK5               0x5
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK6               0x6
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK7               0x7
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK8               0x8
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK9               0x9
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK10              0xA
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK11              0xB
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK12              0xC
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK13              0xD
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK14              0xE
#define   CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK15              0xF
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_CBCR___M              0x80007FF5   
#define   CC_WCSS_MAC0_MAC_CBCR___S                            0

#define CC_WCSS_MAC0_MAC_SREGR                    (0x00CB0114)
#define   CC_WCSS_MAC0_MAC_SREGR___RWC              QCSR_REG_RW    
#define   CC_WCSS_MAC0_MAC_SREGR___POR           0x00000000
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_MAC0_MAC_SREGR___M             0xFFFFF37E   
#define   CC_WCSS_MAC0_MAC_SREGR___S                           1

#define CC_WCSS_DBG_BCR                           (0x00CB0118)
#define   CC_WCSS_DBG_BCR___RWC                     QCSR_REG_RW    
#define   CC_WCSS_DBG_BCR___POR                  0x00000000
#define   CC_WCSS_DBG_BCR__BLK_ARES___POR        0x0
#define   CC_WCSS_DBG_BCR__BLK_ARES___M          0x00000001
#define   CC_WCSS_DBG_BCR__BLK_ARES___S                        0
#define   CC_WCSS_DBG_BCR__BLK_ARES__DISABLE                 0x0
#define   CC_WCSS_DBG_BCR__BLK_ARES__ENABLE                  0x1
#define   CC_WCSS_DBG_BCR___M                    0x00000001   
#define   CC_WCSS_DBG_BCR___S                                  0

#define CC_WCSS_DBG_GDSCR                         (0x00CB011C)
#define   CC_WCSS_DBG_GDSCR___RWC                   QCSR_REG_RW    
#define   CC_WCSS_DBG_GDSCR___POR                0xF822F000
#define   CC_WCSS_DBG_GDSCR__PWR_ON___POR        0x1
#define   CC_WCSS_DBG_GDSCR__GDSC_STATE___POR    0xF
#define   CC_WCSS_DBG_GDSCR__EN_REST_WAIT___POR  0x2
#define   CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___POR   0x2
#define   CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___POR  0xF
#define   CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___POR 0x0
#define   CC_WCSS_DBG_GDSCR__RESTORE___POR       0x0
#define   CC_WCSS_DBG_GDSCR__SAVE___POR          0x0
#define   CC_WCSS_DBG_GDSCR__RETAIN___POR        0x0
#define   CC_WCSS_DBG_GDSCR__EN_REST___POR       0x0
#define   CC_WCSS_DBG_GDSCR__EN_FEW___POR        0x0
#define   CC_WCSS_DBG_GDSCR__CLAMP_IO___POR      0x0
#define   CC_WCSS_DBG_GDSCR__CLK_DISABLE___POR   0x0
#define   CC_WCSS_DBG_GDSCR__PD_ARES___POR       0x0
#define   CC_WCSS_DBG_GDSCR__SW_OVERRIDE___POR   0x0
#define   CC_WCSS_DBG_GDSCR__HW_CONTROL___POR    0x0
#define   CC_WCSS_DBG_GDSCR__SW_COLLAPSE___POR   0x0
#define   CC_WCSS_DBG_GDSCR__PWR_ON___M          0x80000000
#define   CC_WCSS_DBG_GDSCR__PWR_ON___S                       31
#define   CC_WCSS_DBG_GDSCR__GDSC_STATE___M      0x78000000
#define   CC_WCSS_DBG_GDSCR__GDSC_STATE___S                   27
#define   CC_WCSS_DBG_GDSCR__EN_REST_WAIT___M    0x00F00000
#define   CC_WCSS_DBG_GDSCR__EN_REST_WAIT___S                 20
#define   CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___M     0x000F0000
#define   CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___S                  16
#define   CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___M    0x0000F000
#define   CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___S                 12
#define   CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___M 0x00000800
#define   CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___S              11
#define   CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_GDSCR__RESTORE___M         0x00000400
#define   CC_WCSS_DBG_GDSCR__RESTORE___S                      10
#define   CC_WCSS_DBG_GDSCR__RESTORE__DISABLE                0x0
#define   CC_WCSS_DBG_GDSCR__RESTORE__ENABLE                 0x1
#define   CC_WCSS_DBG_GDSCR__SAVE___M            0x00000200
#define   CC_WCSS_DBG_GDSCR__SAVE___S                          9
#define   CC_WCSS_DBG_GDSCR__SAVE__DISABLE                   0x0
#define   CC_WCSS_DBG_GDSCR__SAVE__ENABLE                    0x1
#define   CC_WCSS_DBG_GDSCR__RETAIN___M          0x00000100
#define   CC_WCSS_DBG_GDSCR__RETAIN___S                        8
#define   CC_WCSS_DBG_GDSCR__RETAIN__DISABLE                 0x0
#define   CC_WCSS_DBG_GDSCR__RETAIN__ENABLE                  0x1
#define   CC_WCSS_DBG_GDSCR__EN_REST___M         0x00000080
#define   CC_WCSS_DBG_GDSCR__EN_REST___S                       7
#define   CC_WCSS_DBG_GDSCR__EN_REST__DISABLE                0x0
#define   CC_WCSS_DBG_GDSCR__EN_REST__ENABLE                 0x1
#define   CC_WCSS_DBG_GDSCR__EN_FEW___M          0x00000040
#define   CC_WCSS_DBG_GDSCR__EN_FEW___S                        6
#define   CC_WCSS_DBG_GDSCR__EN_FEW__DISABLE                 0x0
#define   CC_WCSS_DBG_GDSCR__EN_FEW__ENABLE                  0x1
#define   CC_WCSS_DBG_GDSCR__CLAMP_IO___M        0x00000020
#define   CC_WCSS_DBG_GDSCR__CLAMP_IO___S                      5
#define   CC_WCSS_DBG_GDSCR__CLAMP_IO__DISABLE               0x0
#define   CC_WCSS_DBG_GDSCR__CLAMP_IO__ENABLE                0x1
#define   CC_WCSS_DBG_GDSCR__CLK_DISABLE___M     0x00000010
#define   CC_WCSS_DBG_GDSCR__CLK_DISABLE___S                   4
#define   CC_WCSS_DBG_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE             0x0
#define   CC_WCSS_DBG_GDSCR__CLK_DISABLE__CLK_DISABLE             0x1
#define   CC_WCSS_DBG_GDSCR__PD_ARES___M         0x00000008
#define   CC_WCSS_DBG_GDSCR__PD_ARES___S                       3
#define   CC_WCSS_DBG_GDSCR__PD_ARES__NO_RESET               0x0
#define   CC_WCSS_DBG_GDSCR__PD_ARES__RESET                  0x1
#define   CC_WCSS_DBG_GDSCR__SW_OVERRIDE___M     0x00000004
#define   CC_WCSS_DBG_GDSCR__SW_OVERRIDE___S                   2
#define   CC_WCSS_DBG_GDSCR__SW_OVERRIDE__DISABLE             0x0
#define   CC_WCSS_DBG_GDSCR__SW_OVERRIDE__ENABLE             0x1
#define   CC_WCSS_DBG_GDSCR__HW_CONTROL___M      0x00000002
#define   CC_WCSS_DBG_GDSCR__HW_CONTROL___S                    1
#define   CC_WCSS_DBG_GDSCR__HW_CONTROL__DISABLE             0x0
#define   CC_WCSS_DBG_GDSCR__HW_CONTROL__ENABLE              0x1
#define   CC_WCSS_DBG_GDSCR__SW_COLLAPSE___M     0x00000001
#define   CC_WCSS_DBG_GDSCR__SW_COLLAPSE___S                   0
#define   CC_WCSS_DBG_GDSCR__SW_COLLAPSE__DISABLE             0x0
#define   CC_WCSS_DBG_GDSCR__SW_COLLAPSE__ENABLE             0x1
#define   CC_WCSS_DBG_GDSCR___M                  0xF8FFFFFF   
#define   CC_WCSS_DBG_GDSCR___S                                0

#define CC_WCSS_DBG_CFG_GDSCR                     (0x00CB0120)
#define   CC_WCSS_DBG_CFG_GDSCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_DBG_CFG_GDSCR___POR            0x00070000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x1
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x1
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x1
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S              28
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S              26
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___S              25
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___S              24
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S              18
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S              17
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S              16
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S              15
#define   CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S              10
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S               7
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004
#define   CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S               2
#define   CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   CC_WCSS_DBG_CFG_GDSCR___M              0xFFFFFFFF   
#define   CC_WCSS_DBG_CFG_GDSCR___S                            0

#define CC_WCSS_DBG_CFG2_GDSCR                    (0x00CB0124)
#define   CC_WCSS_DBG_CFG2_GDSCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_DBG_CFG2_GDSCR___POR           0x0000022A
#define   CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S              16
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___S              12
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S               8
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S               4
#define   CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S               0
#define   CC_WCSS_DBG_CFG2_GDSCR___M             0x0001FFFF   
#define   CC_WCSS_DBG_CFG2_GDSCR___S                           0

#define CC_WCSS_DBG_AHB_CBCR                      (0x00CB0128)
#define   CC_WCSS_DBG_AHB_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_DBG_AHB_CBCR___POR             0x00000001
#define   CC_WCSS_DBG_AHB_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_AHB_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_DBG_AHB_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_AHB_CBCR___M               0x80000005   
#define   CC_WCSS_DBG_AHB_CBCR___S                             0

#define CC_WCSS_DBG_NOC_CBCR                      (0x00CB012C)
#define   CC_WCSS_DBG_NOC_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_DBG_NOC_CBCR___POR             0x00000001
#define   CC_WCSS_DBG_NOC_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_NOC_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_DBG_NOC_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_NOC_CBCR___M               0x80000005   
#define   CC_WCSS_DBG_NOC_CBCR___S                             0

#define CC_WCSS_DBG_ATB_CMD_RCGR                  (0x00CB0130)
#define   CC_WCSS_DBG_ATB_CMD_RCGR___RWC            QCSR_REG_RW    
#define   CC_WCSS_DBG_ATB_CMD_RCGR___POR         0x00000000
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___POR 0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___POR 0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___POR 0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___M 0x80000000
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___S              31
#define   CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___M  0x00000002
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___S                1
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN__DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN__ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___M   0x00000001
#define   CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___S                 0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE__DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE__ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CMD_RCGR___M           0x80000013   
#define   CC_WCSS_DBG_ATB_CMD_RCGR___S                         0

#define CC_WCSS_DBG_ATB_CFG_RCGR                  (0x00CB0134)
#define   CC_WCSS_DBG_ATB_CFG_RCGR___RWC            QCSR_REG_RW    
#define   CC_WCSS_DBG_ATB_CFG_RCGR___POR         0x00100000
#define   CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___POR 0x1
#define   CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___POR 0x0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___POR 0x0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___POR 0x00
#define   CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000
#define   CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___S              20
#define   CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL__DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL__ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000
#define   CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___S              16
#define   CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED             0x0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED             0x1
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___M  0x00000700
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___S                8
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC0             0x0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC1             0x1
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC2             0x2
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC3             0x3
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC4             0x4
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC5             0x5
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC6             0x6
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC7             0x7
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___M  0x0000001F
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___S                0
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__BYPASS            0x00
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV1            0x01
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV1_5            0x02
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV2            0x03
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV2_5            0x04
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV3            0x05
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV3_5            0x06
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV4            0x07
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV4_5            0x08
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV5            0x09
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV5_5            0x0A
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV6            0x0B
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV6_5            0x0C
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV7            0x0D
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV7_5            0x0E
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV8            0x0F
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV8_5            0x10
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV9            0x11
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV9_5            0x12
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV10            0x13
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV10_5            0x14
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV11            0x15
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV11_5            0x16
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV12            0x17
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV12_5            0x18
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV13            0x19
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV13_5            0x1A
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV14            0x1B
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV14_5            0x1C
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV15            0x1D
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV15_5            0x1E
#define   CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV16            0x1F
#define   CC_WCSS_DBG_ATB_CFG_RCGR___M           0x0011071F   
#define   CC_WCSS_DBG_ATB_CFG_RCGR___S                         0

#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR            (0x00CB0148)
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___RWC      QCSR_REG_RW    
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___POR   0x00000000
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___POR 0x0
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___M     0x0000000F   
#define   CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___S                   0

#define CC_WCSS_DBG_ATB_CBCR                      (0x00CB014C)
#define   CC_WCSS_DBG_ATB_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_DBG_ATB_CBCR___POR             0x00000221
#define   CC_WCSS_DBG_ATB_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP___POR     0x2
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP___POR      0x2
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_ATB_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_DBG_ATB_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP___M       0x00000F00
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP___S                     8
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK0               0x0
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK1               0x1
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK2               0x2
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK3               0x3
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK4               0x4
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK5               0x5
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK6               0x6
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK7               0x7
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK8               0x8
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK9               0x9
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK10              0xA
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK11              0xB
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK12              0xC
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK13              0xD
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK14              0xE
#define   CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK15              0xF
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP___M        0x000000F0
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP___S                      4
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK0                0x0
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK1                0x1
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK2                0x2
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK3                0x3
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK4                0x4
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK5                0x5
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK6                0x6
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK7                0x7
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK8                0x8
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK9                0x9
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK10               0xA
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK11               0xB
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK12               0xC
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK13               0xD
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK14               0xE
#define   CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK15               0xF
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_ATB_CBCR___M               0x80007FF5   
#define   CC_WCSS_DBG_ATB_CBCR___S                             0

#define CC_WCSS_DBG_ATB_SREGR                     (0x00CB0150)
#define   CC_WCSS_DBG_ATB_SREGR___RWC               QCSR_REG_RW    
#define   CC_WCSS_DBG_ATB_SREGR___POR            0x00000000
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_DBG_ATB_SREGR___M              0xFFFFF37E   
#define   CC_WCSS_DBG_ATB_SREGR___S                            1

#define CC_WCSS_DBG_ATB_BDG_CBCR                  (0x00CB0154)
#define   CC_WCSS_DBG_ATB_BDG_CBCR___RWC            QCSR_REG_RW    
#define   CC_WCSS_DBG_ATB_BDG_CBCR___POR         0x00000001
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___M  0x80000000
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___S               31
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_ATB_BDG_CBCR___M           0x80000005   
#define   CC_WCSS_DBG_ATB_BDG_CBCR___S                         0

#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR            (0x00CB0158)
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR___RWC      QCSR_REG_RW    
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR___POR   0x00000003
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___POR 0x3
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR___M     0x0000000F   
#define   CC_WCSS_DBG_AFTERDIV_APB_CDIVR___S                   0

#define CC_WCSS_DBG_APB_CBCR                      (0x00CB015C)
#define   CC_WCSS_DBG_APB_CBCR___RWC                QCSR_REG_RW    
#define   CC_WCSS_DBG_APB_CBCR___POR             0x00000001
#define   CC_WCSS_DBG_APB_CBCR__CLK_OFF___POR    0x0
#define   CC_WCSS_DBG_APB_CBCR__CLK_ARES___POR   0x0
#define   CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_APB_CBCR__CLK_OFF___M      0x80000000
#define   CC_WCSS_DBG_APB_CBCR__CLK_OFF___S                   31
#define   CC_WCSS_DBG_APB_CBCR__CLK_ARES___M     0x00000004
#define   CC_WCSS_DBG_APB_CBCR__CLK_ARES___S                   2
#define   CC_WCSS_DBG_APB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_APB_CBCR__CLK_ARES__RESET              0x1
#define   CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___M   0x00000001
#define   CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___S                 0
#define   CC_WCSS_DBG_APB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_APB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_APB_CBCR___M               0x80000005   
#define   CC_WCSS_DBG_APB_CBCR___S                             0

#define CC_WCSS_DBG_APB_BDG_CBCR                  (0x00CB0160)
#define   CC_WCSS_DBG_APB_BDG_CBCR___RWC            QCSR_REG_RW    
#define   CC_WCSS_DBG_APB_BDG_CBCR___POR         0x00000001
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___M  0x80000000
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___S               31
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_APB_BDG_CBCR___M           0x80000005   
#define   CC_WCSS_DBG_APB_BDG_CBCR___S                         0

#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR         (0x00CB0164)
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___RWC   QCSR_REG_RW    
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___POR 0x00000003
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___POR 0x3
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___M  0x0000000F   
#define   CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___S                0

#define CC_WCSS_DBG_DAPBUS_CBCR                   (0x00CB0168)
#define   CC_WCSS_DBG_DAPBUS_CBCR___RWC             QCSR_REG_RW    
#define   CC_WCSS_DBG_DAPBUS_CBCR___POR          0x00000001
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___M   0x80000000
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___S                31
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___M  0x00000004
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___S                2
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_DAPBUS_CBCR___M            0x80000005   
#define   CC_WCSS_DBG_DAPBUS_CBCR___S                          0

#define CC_WCSS_DBG_DAPBUS_BDG_CBCR               (0x00CB016C)
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR___RWC         QCSR_REG_RW    
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR___POR      0x00000001
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR___M        0x80000005   
#define   CC_WCSS_DBG_DAPBUS_BDG_CBCR___S                      0

#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR          (0x00CB0170)
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___RWC    QCSR_REG_RW    
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___POR 0x00000001
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___POR 0x1
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___M   0x0000000F   
#define   CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___S                 0

#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR             (0x00CB0174)
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR___RWC       QCSR_REG_RW    
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR___POR    0x00000000
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___POR 0x0
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR___M      0x0000000F   
#define   CC_WCSS_DBG_AFTERDIV_TS_CDIVR___S                    0

#define CC_WCSS_DBG_TS_CBCR                       (0x00CB0178)
#define   CC_WCSS_DBG_TS_CBCR___RWC                 QCSR_REG_RW    
#define   CC_WCSS_DBG_TS_CBCR___POR              0x00000001
#define   CC_WCSS_DBG_TS_CBCR__CLK_OFF___POR     0x0
#define   CC_WCSS_DBG_TS_CBCR__CLK_ARES___POR    0x0
#define   CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___POR  0x1
#define   CC_WCSS_DBG_TS_CBCR__CLK_OFF___M       0x80000000
#define   CC_WCSS_DBG_TS_CBCR__CLK_OFF___S                    31
#define   CC_WCSS_DBG_TS_CBCR__CLK_ARES___M      0x00000004
#define   CC_WCSS_DBG_TS_CBCR__CLK_ARES___S                    2
#define   CC_WCSS_DBG_TS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_TS_CBCR__CLK_ARES__RESET               0x1
#define   CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___M    0x00000001
#define   CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___S                  0
#define   CC_WCSS_DBG_TS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_TS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_TS_CBCR___M                0x80000005   
#define   CC_WCSS_DBG_TS_CBCR___S                              0

#define CC_WCSS_DBG_TS_BDG_CBCR                   (0x00CB017C)
#define   CC_WCSS_DBG_TS_BDG_CBCR___RWC             QCSR_REG_RW    
#define   CC_WCSS_DBG_TS_BDG_CBCR___POR          0x00000001
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___M   0x80000000
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___S                31
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___M  0x00000004
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___S                2
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_TS_BDG_CBCR___M            0x80000005   
#define   CC_WCSS_DBG_TS_BDG_CBCR___S                          0

#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR        (0x00CB0180)
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___RWC  QCSR_REG_RW    
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___POR 0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___POR 0x1
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___M 0x0000000F   
#define   CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___S               0

#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR             (0x00CB0184)
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___RWC       QCSR_REG_RW    
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___POR    0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___M      0x80000005   
#define   CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___S                    0

#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR             (0x00CB0188)
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR___RWC       QCSR_REG_RW    
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR___POR    0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR___M      0x80000005   
#define   CC_WCSS_DBG_UMAC_NOC_APB_CBCR___S                    0

#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR              (0x00CB018C)
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR___RWC        QCSR_REG_RW    
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR___POR     0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR___M       0x80000005   
#define   CC_WCSS_DBG_UMAC_NOC_TS_CBCR___S                     0

#define CC_WCSS_DBG_PHYA_ATB_CBCR                 (0x00CB0190)
#define   CC_WCSS_DBG_PHYA_ATB_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_DBG_PHYA_ATB_CBCR___POR        0x00000001
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_PHYA_ATB_CBCR___M          0x80000005   
#define   CC_WCSS_DBG_PHYA_ATB_CBCR___S                        0

#define CC_WCSS_DBG_PHYA_APB_CBCR                 (0x00CB0194)
#define   CC_WCSS_DBG_PHYA_APB_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_DBG_PHYA_APB_CBCR___POR        0x00000001
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_PHYA_APB_CBCR___M          0x80000005   
#define   CC_WCSS_DBG_PHYA_APB_CBCR___S                        0

#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR              (0x00CB0198)
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR___RWC        QCSR_REG_RW    
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR___POR     0x00000001
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR___M       0x80000005   
#define   CC_WCSS_DBG_PHYA_DAPBUS_CBCR___S                     0

#define CC_WCSS_DBG_PHYA_TS_CBCR                  (0x00CB019C)
#define   CC_WCSS_DBG_PHYA_TS_CBCR___RWC            QCSR_REG_RW    
#define   CC_WCSS_DBG_PHYA_TS_CBCR___POR         0x00000001
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___M  0x80000000
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___S               31
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_PHYA_TS_CBCR___M           0x80000005   
#define   CC_WCSS_DBG_PHYA_TS_CBCR___S                         0

#define CC_WCSS_DBG_APB_TIME_CDIVR                (0x00CB01A0)
#define   CC_WCSS_DBG_APB_TIME_CDIVR___RWC          QCSR_REG_RW    
#define   CC_WCSS_DBG_APB_TIME_CDIVR___POR       0x00000000
#define   CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___POR 0x0
#define   CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___M 0x0000000F
#define   CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___S               0
#define   CC_WCSS_DBG_APB_TIME_CDIVR___M         0x0000000F   
#define   CC_WCSS_DBG_APB_TIME_CDIVR___S                       0

#define CC_WCSS_DBG_MAC0_MAC_CBCR                 (0x00CB01A4)
#define   CC_WCSS_DBG_MAC0_MAC_CBCR___RWC           QCSR_REG_RW    
#define   CC_WCSS_DBG_MAC0_MAC_CBCR___POR        0x00000001
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___S              31
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___S               2
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_DBG_MAC0_MAC_CBCR___M          0x80000005   
#define   CC_WCSS_DBG_MAC0_MAC_CBCR___S                        0

#define CC_WCSS_UMAC_BCR                          (0x00CB01A8)
#define   CC_WCSS_UMAC_BCR___RWC                    QCSR_REG_RW    
#define   CC_WCSS_UMAC_BCR___POR                 0x00000000
#define   CC_WCSS_UMAC_BCR__BLK_ARES___POR       0x0
#define   CC_WCSS_UMAC_BCR__BLK_ARES___M         0x00000001
#define   CC_WCSS_UMAC_BCR__BLK_ARES___S                       0
#define   CC_WCSS_UMAC_BCR__BLK_ARES__DISABLE                0x0
#define   CC_WCSS_UMAC_BCR__BLK_ARES__ENABLE                 0x1
#define   CC_WCSS_UMAC_BCR___M                   0x00000001   
#define   CC_WCSS_UMAC_BCR___S                                 0

#define CC_WCSS_UMAC_GDSCR                        (0x00CB01AC)
#define   CC_WCSS_UMAC_GDSCR___RWC                  QCSR_REG_RW    
#define   CC_WCSS_UMAC_GDSCR___POR               0xF822F000
#define   CC_WCSS_UMAC_GDSCR__PWR_ON___POR       0x1
#define   CC_WCSS_UMAC_GDSCR__GDSC_STATE___POR   0xF
#define   CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___POR 0x2
#define   CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___POR  0x2
#define   CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___POR 0xF
#define   CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___POR 0x0
#define   CC_WCSS_UMAC_GDSCR__RESTORE___POR      0x0
#define   CC_WCSS_UMAC_GDSCR__SAVE___POR         0x0
#define   CC_WCSS_UMAC_GDSCR__RETAIN___POR       0x0
#define   CC_WCSS_UMAC_GDSCR__EN_REST___POR      0x0
#define   CC_WCSS_UMAC_GDSCR__EN_FEW___POR       0x0
#define   CC_WCSS_UMAC_GDSCR__CLAMP_IO___POR     0x0
#define   CC_WCSS_UMAC_GDSCR__CLK_DISABLE___POR  0x0
#define   CC_WCSS_UMAC_GDSCR__PD_ARES___POR      0x0
#define   CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___POR  0x0
#define   CC_WCSS_UMAC_GDSCR__HW_CONTROL___POR   0x0
#define   CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___POR  0x0
#define   CC_WCSS_UMAC_GDSCR__PWR_ON___M         0x80000000
#define   CC_WCSS_UMAC_GDSCR__PWR_ON___S                      31
#define   CC_WCSS_UMAC_GDSCR__GDSC_STATE___M     0x78000000
#define   CC_WCSS_UMAC_GDSCR__GDSC_STATE___S                  27
#define   CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___M   0x00F00000
#define   CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___S                20
#define   CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___M    0x000F0000
#define   CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___S                 16
#define   CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___M   0x0000F000
#define   CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___S                12
#define   CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___M 0x00000800
#define   CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___S              11
#define   CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_GDSCR__RESTORE___M        0x00000400
#define   CC_WCSS_UMAC_GDSCR__RESTORE___S                     10
#define   CC_WCSS_UMAC_GDSCR__RESTORE__DISABLE               0x0
#define   CC_WCSS_UMAC_GDSCR__RESTORE__ENABLE                0x1
#define   CC_WCSS_UMAC_GDSCR__SAVE___M           0x00000200
#define   CC_WCSS_UMAC_GDSCR__SAVE___S                         9
#define   CC_WCSS_UMAC_GDSCR__SAVE__DISABLE                  0x0
#define   CC_WCSS_UMAC_GDSCR__SAVE__ENABLE                   0x1
#define   CC_WCSS_UMAC_GDSCR__RETAIN___M         0x00000100
#define   CC_WCSS_UMAC_GDSCR__RETAIN___S                       8
#define   CC_WCSS_UMAC_GDSCR__RETAIN__DISABLE                0x0
#define   CC_WCSS_UMAC_GDSCR__RETAIN__ENABLE                 0x1
#define   CC_WCSS_UMAC_GDSCR__EN_REST___M        0x00000080
#define   CC_WCSS_UMAC_GDSCR__EN_REST___S                      7
#define   CC_WCSS_UMAC_GDSCR__EN_REST__DISABLE               0x0
#define   CC_WCSS_UMAC_GDSCR__EN_REST__ENABLE                0x1
#define   CC_WCSS_UMAC_GDSCR__EN_FEW___M         0x00000040
#define   CC_WCSS_UMAC_GDSCR__EN_FEW___S                       6
#define   CC_WCSS_UMAC_GDSCR__EN_FEW__DISABLE                0x0
#define   CC_WCSS_UMAC_GDSCR__EN_FEW__ENABLE                 0x1
#define   CC_WCSS_UMAC_GDSCR__CLAMP_IO___M       0x00000020
#define   CC_WCSS_UMAC_GDSCR__CLAMP_IO___S                     5
#define   CC_WCSS_UMAC_GDSCR__CLAMP_IO__DISABLE              0x0
#define   CC_WCSS_UMAC_GDSCR__CLAMP_IO__ENABLE               0x1
#define   CC_WCSS_UMAC_GDSCR__CLK_DISABLE___M    0x00000010
#define   CC_WCSS_UMAC_GDSCR__CLK_DISABLE___S                  4
#define   CC_WCSS_UMAC_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE             0x0
#define   CC_WCSS_UMAC_GDSCR__CLK_DISABLE__CLK_DISABLE             0x1
#define   CC_WCSS_UMAC_GDSCR__PD_ARES___M        0x00000008
#define   CC_WCSS_UMAC_GDSCR__PD_ARES___S                      3
#define   CC_WCSS_UMAC_GDSCR__PD_ARES__NO_RESET              0x0
#define   CC_WCSS_UMAC_GDSCR__PD_ARES__RESET                 0x1
#define   CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___M    0x00000004
#define   CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___S                  2
#define   CC_WCSS_UMAC_GDSCR__SW_OVERRIDE__DISABLE             0x0
#define   CC_WCSS_UMAC_GDSCR__SW_OVERRIDE__ENABLE             0x1
#define   CC_WCSS_UMAC_GDSCR__HW_CONTROL___M     0x00000002
#define   CC_WCSS_UMAC_GDSCR__HW_CONTROL___S                   1
#define   CC_WCSS_UMAC_GDSCR__HW_CONTROL__DISABLE             0x0
#define   CC_WCSS_UMAC_GDSCR__HW_CONTROL__ENABLE             0x1
#define   CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___M    0x00000001
#define   CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___S                  0
#define   CC_WCSS_UMAC_GDSCR__SW_COLLAPSE__DISABLE             0x0
#define   CC_WCSS_UMAC_GDSCR__SW_COLLAPSE__ENABLE             0x1
#define   CC_WCSS_UMAC_GDSCR___M                 0xF8FFFFFF   
#define   CC_WCSS_UMAC_GDSCR___S                               0

#define CC_WCSS_UMAC_CFG_GDSCR                    (0x00CB01B0)
#define   CC_WCSS_UMAC_CFG_GDSCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_UMAC_CFG_GDSCR___POR           0x00070000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x1
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x1
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x1
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S              28
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S              26
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___S              25
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___S              24
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S              20
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S              19
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S              18
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S              17
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S              16
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S              15
#define   CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800
#define   CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S              11
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S              10
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S               9
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S               8
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S               7
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S               5
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010
#define   CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S               4
#define   CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008
#define   CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S               3
#define   CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004
#define   CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S               2
#define   CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002
#define   CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S               1
#define   CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001
#define   CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S               0
#define   CC_WCSS_UMAC_CFG_GDSCR___M             0xFFFFFFFF   
#define   CC_WCSS_UMAC_CFG_GDSCR___S                           0

#define CC_WCSS_UMAC_CFG2_GDSCR                   (0x00CB01B4)
#define   CC_WCSS_UMAC_CFG2_GDSCR___RWC             QCSR_REG_RW    
#define   CC_WCSS_UMAC_CFG2_GDSCR___POR          0x0000022A
#define   CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2
#define   CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA
#define   CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000
#define   CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S              16
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___S              12
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S               8
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0
#define   CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S               4
#define   CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F
#define   CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S               0
#define   CC_WCSS_UMAC_CFG2_GDSCR___M            0x0001FFFF   
#define   CC_WCSS_UMAC_CFG2_GDSCR___S                          0

#define CC_WCSS_UMAC_NOC_CBCR                     (0x00CB01B8)
#define   CC_WCSS_UMAC_NOC_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_CBCR___POR            0x80000220
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP___POR    0x2
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP___POR     0x2
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP___M      0x00000F00
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP___S                    8
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK0              0x0
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK1              0x1
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK2              0x2
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK3              0x3
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK4              0x4
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK5              0x5
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK6              0x6
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK7              0x7
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK8              0x8
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK9              0x9
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP___M       0x000000F0
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP___S                     4
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK0               0x0
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK1               0x1
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK2               0x2
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK3               0x3
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK4               0x4
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK5               0x5
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK6               0x6
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK7               0x7
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK8               0x8
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK9               0x9
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK10              0xA
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK11              0xB
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK12              0xC
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK13              0xD
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK14              0xE
#define   CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK15              0xF
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_CBCR___M              0x80007FF5   
#define   CC_WCSS_UMAC_NOC_CBCR___S                            0

#define CC_WCSS_UMAC_NOC_SREGR                    (0x00CB01BC)
#define   CC_WCSS_UMAC_NOC_SREGR___RWC              QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_SREGR___POR           0x00000000
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_SREGR___M             0xFFFFF37E   
#define   CC_WCSS_UMAC_NOC_SREGR___S                           1

#define CC_WCSS_UMAC_AHB_CBCR                     (0x00CB01C0)
#define   CC_WCSS_UMAC_AHB_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_UMAC_AHB_CBCR___POR            0x80000220
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___POR 0x0
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP___POR    0x2
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP___POR     0x2
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___M 0x00004000
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___S              14
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___S              13
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___S              12
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE             0x0
#define   CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP___M      0x00000F00
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP___S                    8
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK0              0x0
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK1              0x1
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK2              0x2
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK3              0x3
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK4              0x4
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK5              0x5
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK6              0x6
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK7              0x7
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK8              0x8
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK9              0x9
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK10             0xA
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK11             0xB
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK12             0xC
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK13             0xD
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK14             0xE
#define   CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK15             0xF
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP___M       0x000000F0
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP___S                     4
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK0               0x0
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK1               0x1
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK2               0x2
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK3               0x3
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK4               0x4
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK5               0x5
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK6               0x6
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK7               0x7
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK8               0x8
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK9               0x9
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK10              0xA
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK11              0xB
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK12              0xC
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK13              0xD
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK14              0xE
#define   CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK15              0xF
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_CBCR___M              0x80007FF5   
#define   CC_WCSS_UMAC_AHB_CBCR___S                            0

#define CC_WCSS_UMAC_AHB_SREGR                    (0x00CB01C4)
#define   CC_WCSS_UMAC_AHB_SREGR___RWC              QCSR_REG_RW    
#define   CC_WCSS_UMAC_AHB_SREGR___POR           0x00000000
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00
#define   CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___POR 0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S              24
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000
#define   CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S              16
#define   CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___M 0x0000E000
#define   CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___S              13
#define   CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000
#define   CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S              12
#define   CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S               8
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4             0x2
#define   CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8             0x3
#define   CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___M 0x00000040
#define   CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___S               6
#define   CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON__NO_FORCE             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON__FORCE_ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___S               5
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___M 0x00000010
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___S               4
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___S               3
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___S               2
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT             0x1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___S               1
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE             0x0
#define   CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE             0x1
#define   CC_WCSS_UMAC_AHB_SREGR___M             0xFFFFF37E   
#define   CC_WCSS_UMAC_AHB_SREGR___S                           1

#define CC_CLK_UMAC_INT_APB_CDIVR                 (0x00CB01C8)
#define   CC_CLK_UMAC_INT_APB_CDIVR___RWC           QCSR_REG_RW    
#define   CC_CLK_UMAC_INT_APB_CDIVR___POR        0x00000001
#define   CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___POR 0x1
#define   CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___M 0x00000003
#define   CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___S               0
#define   CC_CLK_UMAC_INT_APB_CDIVR___M          0x00000003   
#define   CC_CLK_UMAC_INT_APB_CDIVR___S                        0

#define CC_WCSS_UMAC_MAC0_CBCR                    (0x00CB01CC)
#define   CC_WCSS_UMAC_MAC0_CBCR___RWC              QCSR_REG_RW    
#define   CC_WCSS_UMAC_MAC0_CBCR___POR           0x80000000
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___POR  0x1
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___M    0x80000000
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___S                 31
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___M   0x00000004
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___S                 2
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_MAC0_CBCR___M             0x80000005   
#define   CC_WCSS_UMAC_MAC0_CBCR___S                           0

#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR             (0x00CB01D0)
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___RWC       QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___POR    0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___M      0x80000005   
#define   CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___S                    0

#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR             (0x00CB01D4)
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR___RWC       QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR___POR    0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___S              31
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___S               2
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR___M      0x80000005   
#define   CC_WCSS_UMAC_NOC_DBG_APB_CBCR___S                    0

#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR              (0x00CB01D8)
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR___RWC        QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR___POR     0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___POR 0x0
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___POR 0x1
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___M 0x80000000
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___S              31
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___M 0x00000004
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___S               2
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___M 0x00000001
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___S               0
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR___M       0x80000005   
#define   CC_WCSS_UMAC_NOC_DBG_TS_CBCR___S                     0

#define CC_WCSS_UMAC_WSI_CMD_RCGR                 (0x00CB01DC)
#define   CC_WCSS_UMAC_WSI_CMD_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_UMAC_WSI_CMD_RCGR___POR        0x80000000
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___POR 0x1
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___POR 0x0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___POR 0x0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___M 0x80000000
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___S              31
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___S               4
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___M 0x00000002
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___S               1
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN__DISABLE             0x0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN__ENABLE             0x1
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___M  0x00000001
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___S                0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE__DISABLE             0x0
#define   CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE__ENABLE             0x1
#define   CC_WCSS_UMAC_WSI_CMD_RCGR___M          0x80000013   
#define   CC_WCSS_UMAC_WSI_CMD_RCGR___S                        0

#define CC_WCSS_UMAC_WSI_CFG_RCGR                 (0x00CB01E0)
#define   CC_WCSS_UMAC_WSI_CFG_RCGR___RWC           QCSR_REG_RW    
#define   CC_WCSS_UMAC_WSI_CFG_RCGR___POR        0x00100000
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___POR 0x1
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___POR 0x0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___POR 0x0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___POR 0x00
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___S              20
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL__DISABLE             0x0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL__ENABLE             0x1
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___S              16
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED             0x0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED             0x1
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___M 0x00000700
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___S               8
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC0             0x0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC1             0x1
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC2             0x2
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC3             0x3
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC4             0x4
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC5             0x5
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC6             0x6
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC7             0x7
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___M 0x0000001F
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___S               0
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__BYPASS            0x00
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV1            0x01
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV1_5            0x02
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV2            0x03
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV2_5            0x04
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV3            0x05
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV3_5            0x06
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV4            0x07
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV4_5            0x08
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV5            0x09
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV5_5            0x0A
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV6            0x0B
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV6_5            0x0C
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV7            0x0D
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV7_5            0x0E
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV8            0x0F
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV8_5            0x10
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV9            0x11
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV9_5            0x12
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV10            0x13
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV10_5            0x14
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV11            0x15
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV11_5            0x16
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV12            0x17
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV12_5            0x18
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV13            0x19
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV13_5            0x1A
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV14            0x1B
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV14_5            0x1C
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV15            0x1D
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV15_5            0x1E
#define   CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV16            0x1F
#define   CC_WCSS_UMAC_WSI_CFG_RCGR___M          0x0011071F   
#define   CC_WCSS_UMAC_WSI_CFG_RCGR___S                        0

#define CC_WCSS_UMAC_WSI_CBCR                     (0x00CB01F4)
#define   CC_WCSS_UMAC_WSI_CBCR___RWC               QCSR_REG_RW    
#define   CC_WCSS_UMAC_WSI_CBCR___POR            0x80000000
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___POR   0x1
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___POR  0x0
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___POR 0x0
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___M     0x80000000
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___S                  31
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___M    0x00000004
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___S                  2
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ARES__NO_RESET             0x0
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ARES__RESET             0x1
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___M  0x00000001
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___S                0
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE__DISABLE             0x0
#define   CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE__ENABLE             0x1
#define   CC_WCSS_UMAC_WSI_CBCR___M              0x80000005   
#define   CC_WCSS_UMAC_WSI_CBCR___S                            0

#define CC_WCSS_NOC_TIME_CDIVR                    (0x00CB01F8)
#define   CC_WCSS_NOC_TIME_CDIVR___RWC              QCSR_REG_RW    
#define   CC_WCSS_NOC_TIME_CDIVR___POR           0x00000000
#define   CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___POR  0x0
#define   CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___M    0x0000000F
#define   CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___S                  0
#define   CC_WCSS_NOC_TIME_CDIVR___M             0x0000000F   
#define   CC_WCSS_NOC_TIME_CDIVR___S                           0

#define CC_WCSS_DEBUG_CLK                         (0x00CB1000)
#define   CC_WCSS_DEBUG_CLK___RWC                   QCSR_REG_RW    
#define   CC_WCSS_DEBUG_CLK___POR                0x00000000
#define   CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___POR 0x0
#define   CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___POR 0x000
#define   CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___M   0x00007800
#define   CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___S                11
#define   CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___M 0x000007FF
#define   CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___S               0
#define   CC_WCSS_DEBUG_CLK___M                  0x00007FFF   
#define   CC_WCSS_DEBUG_CLK___S                                0

#define CC_WCSS_SPARE_CFG                         (0x00CB1004)
#define   CC_WCSS_SPARE_CFG___RWC                   QCSR_REG_RW    
#define   CC_WCSS_SPARE_CFG___POR                0x00000000
#define   CC_WCSS_SPARE_CFG__MISC___POR          0x00000000
#define   CC_WCSS_SPARE_CFG__MISC___M            0xFFFFFFFF
#define   CC_WCSS_SPARE_CFG__MISC___S                          0
#define   CC_WCSS_SPARE_CFG___M                  0xFFFFFFFF   
#define   CC_WCSS_SPARE_CFG___S                                0

#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE (0x00CB1020)
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___RWC QCSR_REG_RW    
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___POR 0x00000000
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___POR 0x0
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___M 0x00000001
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___S               0
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___M 0x00000001   
#define   CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___S               0

#define CC_WCSS_MISC_POWER_SAVE_CTL               (0x00CB1030)
#define   CC_WCSS_MISC_POWER_SAVE_CTL___RWC         QCSR_REG_RW    
#define   CC_WCSS_MISC_POWER_SAVE_CTL___POR      0x008000AE
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___POR 0x0080
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___POR 0x0
#define   CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___POR 0x1
#define   CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___POR 0x1
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___POR 0x7
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___POR 0x0
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___M 0xFFFF0000
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___S              16
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___M 0x00000100
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___S               8
#define   CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___M 0x00000080
#define   CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___S               7
#define   CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___M 0x00000020
#define   CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___S               5
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___M 0x0000001E
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___S               1
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___M 0x00000001
#define   CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___S               0
#define   CC_WCSS_MISC_POWER_SAVE_CTL___M        0xFFFF01BF   
#define   CC_WCSS_MISC_POWER_SAVE_CTL___S                      0

#define CC_WCSS_MISC_POWER_SAVE_CTL_2             (0x00CB1034)
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2___RWC       QCSR_REG_RW    
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2___POR    0x00000404
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___POR 0x04
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___POR 0x04
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___M 0x0000FF00
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___S               8
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___M 0x000000FF
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___S               0
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2___M      0x0000FFFF   
#define   CC_WCSS_MISC_POWER_SAVE_CTL_2___S                    0

#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL        (0x00CB1044)
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___RWC  QCSR_REG_RW    
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___POR 0x00000000
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___POR 0x0
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___M 0x00000001
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___S               0
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___M 0x00000001   
#define   CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___S               0

#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL      (0x00CB1048)
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___RWC QCSR_REG_RW    
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___POR 0x00000001
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___POR 0x1
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___M 0x00000001
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___S               0
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___M 0x00000001   
#define   CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___S               0

#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL           (0x00CB104C)
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___RWC     QCSR_REG_RW    
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___POR  0x00000000
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___POR 0x0
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___M 0x00000001
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___S               0
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL__CLK_SRC_PHYA_DIGCLK480M             0x0
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL__CLK_SRR_PLL_MAIN_320M             0x1
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___M    0x00000001   
#define   CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___S                  0

#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL        (0x00CB1050)
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___RWC  QCSR_REG_RW    
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___POR 0x00000000
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___POR 0x0
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___M 0x00000001
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___S               0
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL__CLK_SRC_NOM_240             0x0
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL__CLK_SRR_SVS_160             0x1
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___M 0x00000001   
#define   CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___S               0

#define CC_WCSS_CC_DBG_CLK_GATE_CTL               (0x00CB106C)
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL___RWC         QCSR_REG_RW    
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL___POR      0x00000000
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___POR 0x00000000
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___M 0xFFFFFFFF
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___S               0
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL___M        0xFFFFFFFF   
#define   CC_WCSS_CC_DBG_CLK_GATE_CTL___S                      0

#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR              (0x00CB1070)
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR___POR     0x00000700
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___POR 0x07
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___POR 0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___M 0x0000FF00
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___S               8
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___M 0x00000040
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___S               6
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH__NO_FORCE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH__FORCE_HIGH_FREQ             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___M 0x00000020
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___S               5
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW__NO_FORCE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW__FORCE_LOW_FREQ             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___M 0x00000010
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___S               4
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN__DISABLE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN__ENABLE             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___M 0x00000008
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___S               3
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN__DISABLE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN__ENABLE             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___M 0x00000004
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___S               2
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN__DISABLE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN__ENABLE             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___M 0x00000002
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___S               1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN__DISABLE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN__ENABLE             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___M 0x00000001
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___S               0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN__DISABLE             0x0
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN__ENABLE             0x1
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR___M       0x0000FF7F   
#define   CC_WCSS_CC_DBG_ATB_CFG1_DCDR___S                     0

#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR              (0x00CB1074)
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR___POR     0x0050031F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___POR 0x0050
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___POR 0x03
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___POR 0x1F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___M 0xFFFF0000
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___S              16
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___M 0x0000FF00
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___S               8
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV1            0x00
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV2            0x01
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV8            0x07
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV16            0x0F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV32            0x1F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV128            0x7F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV256            0xFF
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___M 0x000000FF
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___S               0
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV1            0x00
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV2            0x01
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV8            0x07
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV16            0x0F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV32            0x1F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV128            0x7F
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV256            0xFF
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR___M       0xFFFFFFFF   
#define   CC_WCSS_CC_DBG_ATB_CFG2_DCDR___S                     0

#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR              (0x00CB1078)
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR___POR     0x00000700
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___POR 0x07
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___POR 0x0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___M 0x0000FF00
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___S               8
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___M 0x00000001
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___S               0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN__DISABLE             0x0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN__ENABLE             0x1
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR___M       0x0000FF01   
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCGR___S                     0

#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR              (0x00CB107C)
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR___POR     0x00000300
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___POR 0x3
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___POR 0x0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___M 0x00000F00
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___S               8
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___M 0x00000001
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___S               0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN__DISABLE             0x0
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN__ENABLE             0x1
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR___M       0x00000F01   
#define   CC_WCSS_CC_UMAC_NOC_CLK_DCDR___S                     0

#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR              (0x00CB1080)
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR___POR     0x00000700
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___POR 0x07
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___POR 0x0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___M 0x0000FF00
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___S               8
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___M 0x00000001
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___S               0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN__DISABLE             0x0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN__ENABLE             0x1
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR___M       0x0000FF01   
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCGR___S                     0

#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR              (0x00CB1084)
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR___RWC        QCSR_REG_RW    
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR___POR     0x00000300
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___POR 0x3
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___POR 0x0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___M 0x00000F00
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___S               8
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___M 0x00000001
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___S               0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN__DISABLE             0x0
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN__ENABLE             0x1
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR___M       0x00000F01   
#define   CC_WCSS_CC_MAC0_MAC_CLK_DCDR___S                     0

#define CC_QDSS_STM_EVENT0_CTL_REG                (0x00CB2000)
#define   CC_QDSS_STM_EVENT0_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT0_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT0_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT0_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT1_CTL_REG                (0x00CB2004)
#define   CC_QDSS_STM_EVENT1_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT1_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT1_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT1_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT2_CTL_REG                (0x00CB2008)
#define   CC_QDSS_STM_EVENT2_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT2_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT2_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT2_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT3_CTL_REG                (0x00CB200C)
#define   CC_QDSS_STM_EVENT3_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT3_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT3_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT3_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT4_CTL_REG                (0x00CB2010)
#define   CC_QDSS_STM_EVENT4_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT4_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT4_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT4_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT5_CTL_REG                (0x00CB2014)
#define   CC_QDSS_STM_EVENT5_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT5_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT5_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT5_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT6_CTL_REG                (0x00CB2018)
#define   CC_QDSS_STM_EVENT6_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT6_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT6_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT6_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT7_CTL_REG                (0x00CB201C)
#define   CC_QDSS_STM_EVENT7_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT7_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT7_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT7_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT8_CTL_REG                (0x00CB2020)
#define   CC_QDSS_STM_EVENT8_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT8_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT8_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT8_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT9_CTL_REG                (0x00CB2024)
#define   CC_QDSS_STM_EVENT9_CTL_REG___RWC          QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT9_CTL_REG___POR       0x00000000
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT9_CTL_REG___M         0x80000007   
#define   CC_QDSS_STM_EVENT9_CTL_REG___S                       0

#define CC_QDSS_STM_EVENT10_CTL_REG               (0x00CB2028)
#define   CC_QDSS_STM_EVENT10_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT10_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT10_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT10_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT11_CTL_REG               (0x00CB202C)
#define   CC_QDSS_STM_EVENT11_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT11_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT11_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT11_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT12_CTL_REG               (0x00CB2030)
#define   CC_QDSS_STM_EVENT12_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT12_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT12_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT12_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT13_CTL_REG               (0x00CB2034)
#define   CC_QDSS_STM_EVENT13_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT13_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT13_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT13_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT14_CTL_REG               (0x00CB2038)
#define   CC_QDSS_STM_EVENT14_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT14_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT14_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT14_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT15_CTL_REG               (0x00CB203C)
#define   CC_QDSS_STM_EVENT15_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT15_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT15_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT15_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT16_CTL_REG               (0x00CB2040)
#define   CC_QDSS_STM_EVENT16_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT16_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT16_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT16_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT17_CTL_REG               (0x00CB2044)
#define   CC_QDSS_STM_EVENT17_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT17_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT17_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT17_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT18_CTL_REG               (0x00CB2048)
#define   CC_QDSS_STM_EVENT18_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT18_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT18_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT18_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT19_CTL_REG               (0x00CB204C)
#define   CC_QDSS_STM_EVENT19_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT19_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT19_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT19_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT20_CTL_REG               (0x00CB2050)
#define   CC_QDSS_STM_EVENT20_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT20_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT20_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT20_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT21_CTL_REG               (0x00CB2054)
#define   CC_QDSS_STM_EVENT21_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT21_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT21_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT21_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT22_CTL_REG               (0x00CB2058)
#define   CC_QDSS_STM_EVENT22_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT22_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT22_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT22_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT23_CTL_REG               (0x00CB205C)
#define   CC_QDSS_STM_EVENT23_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT23_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT23_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT23_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT24_CTL_REG               (0x00CB2060)
#define   CC_QDSS_STM_EVENT24_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT24_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT24_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT24_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT25_CTL_REG               (0x00CB2064)
#define   CC_QDSS_STM_EVENT25_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT25_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT25_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT25_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT26_CTL_REG               (0x00CB2068)
#define   CC_QDSS_STM_EVENT26_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT26_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT26_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT26_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT27_CTL_REG               (0x00CB206C)
#define   CC_QDSS_STM_EVENT27_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT27_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT27_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT27_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT28_CTL_REG               (0x00CB2070)
#define   CC_QDSS_STM_EVENT28_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT28_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT28_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT28_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT29_CTL_REG               (0x00CB2074)
#define   CC_QDSS_STM_EVENT29_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT29_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT29_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT29_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT30_CTL_REG               (0x00CB2078)
#define   CC_QDSS_STM_EVENT30_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT30_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT30_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT30_CTL_REG___S                      0

#define CC_QDSS_STM_EVENT31_CTL_REG               (0x00CB207C)
#define   CC_QDSS_STM_EVENT31_CTL_REG___RWC         QCSR_REG_RW    
#define   CC_QDSS_STM_EVENT31_CTL_REG___POR      0x00000000
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___POR 0x0
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___POR 0x0
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___M 0x80000000
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___S              31
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE__DISABLE             0x0
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE__ENABLE             0x1
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___M 0x00000007
#define   CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___S               0
#define   CC_QDSS_STM_EVENT31_CTL_REG___M        0x80000007   
#define   CC_QDSS_STM_EVENT31_CTL_REG___S                      0


#define UMAC_ACMT_BASE              (0x00CC0000)

#define UMAC_ACMT_UMAC_ACMT_CTRL                  (0x00CC0000)
#define   UMAC_ACMT_UMAC_ACMT_CTRL___RWC            QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_CTRL___POR         0x00000000
#define   UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___M   0x00000001
#define   UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___S                 0
#define   UMAC_ACMT_UMAC_ACMT_CTRL___M           0x00000001   
#define   UMAC_ACMT_UMAC_ACMT_CTRL___S                         0

#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE           (0x00CC0004)
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___RWC     QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___POR  0x00000000
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___M 0x00000001
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___S               0
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___M    0x00000001   
#define   UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___S                  0

#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS           (0x00CC0008)
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS___RWC     QCSR_REG_RO    
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS___POR  0x00000000
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___M 0x00000001
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___S               0
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS___M    0x00000001   
#define   UMAC_ACMT_UMAC_ACMT_INTR_STATUS___S                  0

#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR            (0x00CC000C)
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___RWC      QCSR_REG_WO    
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___POR   0x00000000
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___M 0x00000001
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___S               0
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___M     0x00000001   
#define   UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___S                   0

#define UMAC_ACMT_UMAC_ACMT_DEBUG0                (0x00CC0010)
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0___RWC          QCSR_REG_RO    
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0___POR       0x00000000
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___POR 0x000000
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___M 0x00FFFFFF
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___S               0
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0___M         0x00FFFFFF   
#define   UMAC_ACMT_UMAC_ACMT_DEBUG0___S                       0

#define UMAC_ACMT_UMAC_ACMT_DEBUG1                (0x00CC0014)
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1___RWC          QCSR_REG_RO    
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1___POR       0x00000000
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___POR   0x0
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___M     0x10000000
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___S                  28
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1___M         0x10000000   
#define   UMAC_ACMT_UMAC_ACMT_DEBUG1___S                      28

#define UMAC_ACMT_UMAC_ACMT_CFG                   (0x00CC001C)
#define   UMAC_ACMT_UMAC_ACMT_CFG___RWC             QCSR_REG_RO    
#define   UMAC_ACMT_UMAC_ACMT_CFG___POR          0x00000001
#define   UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___POR 0x1
#define   UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___M 0x00000010
#define   UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___S               4
#define   UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___M 0x00000001
#define   UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___S               0
#define   UMAC_ACMT_UMAC_ACMT_CFG___M            0x00000011   
#define   UMAC_ACMT_UMAC_ACMT_CFG___S                          0

#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL         (0x00CC0040)
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___RWC   QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___POR 0x00000111
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___POR 0x1
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___POR 0x1
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___POR 0x1
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___M 0x00000100
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___S               8
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___M 0x00000010
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___S               4
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___M 0x00000001
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___S               0
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___M  0x00000111   
#define   UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___S                0

#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL       (0x00CC0044)
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___POR 0x0
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___M 0x0000000F
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___S               0
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___M 0x0000000F   
#define   UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0        (0x00CC0100)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1        (0x00CC0104)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2        (0x00CC0108)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3        (0x00CC010C)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4        (0x00CC0110)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5        (0x00CC0114)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6        (0x00CC0118)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7        (0x00CC011C)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8        (0x00CC0120)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9        (0x00CC0124)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___RWC  QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10       (0x00CC0128)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11       (0x00CC012C)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12       (0x00CC0130)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13       (0x00CC0134)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14       (0x00CC0138)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___S               0

#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15       (0x00CC013C)
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___RWC QCSR_REG_RW    
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___POR 0x00000000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___POR 0x0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___M 0x3FFF0000
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___S              16
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___M 0x00003FFF
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___S               0
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___M 0x3FFF3FFF   
#define   UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___S               0

////////////////////////////////////////////////////////////////////////// END
#endif